STM32L552 1.1 STM32L552 8 32 0x20 0x0 0xFFFFFFFF DCB Debug Control Block DCB 0xE000EE08 0x0 0x5 registers DSCSR DSCSR Debug Security Control and Status Register 0x0 0x20 read-write 0x00000000 CDS Current domain Secure 16 1 DFSDM1 Digital filter for sigma delta modulators DFSDM 0x40016000 0x0 0x800 registers DFSDM1_FLT0 DFSDM1_FLT0 global interrupt 102 DFSDM1_FLT1 DFSDM1_FLT1 global interrupt 103 DFSDM1_FLT2 DFSDM1_FLT2 global interrupt 104 DFSDM1_FLT3 DFSDM1_FLT3 global interrupt 105 CH0CFGR1 CH0CFGR1 channel configuration y register 0x0 0x20 read-write 0x0 DFSDMEN DFSDMEN 31 1 CKOUTSRC CKOUTSRC 30 1 CKOUTDIV CKOUTDIV 16 8 DATPACK DATPACK 14 2 DATMPX DATMPX 12 2 CHINSEL CHINSEL 8 1 CHEN CHEN 7 1 CKABEN CKABEN 6 1 SCDEN SCDEN 5 1 SPICKSEL SPICKSEL 2 2 SITP SITP 0 2 CH0CFGR2 CH0CFGR2 channel configuration y register 0x4 0x20 read-write 0x0 OFFSET OFFSET 8 24 DTRBS DTRBS 3 5 CH0AWSCDR CH0AWSCDR analog watchdog and short-circuit detector register 0x8 0x20 read-write 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CH0WDATR CH0WDATR channel watchdog filter data register 0xC 0x20 read-write 0x0 WDATA WDATA 0 16 CH0DATINR CH0DATINR channel data input register 0x10 0x20 read-write 0x0 INDAT1 INDAT1 16 16 INDAT0 INDAT0 0 16 CH1CFGR1 CH1CFGR1 CHCFG1R1 0x20 0x20 read-write 0x0 DATPACK DATPACK 14 2 DATMPX DATMPX 12 2 CHINSEL CHINSEL 8 1 CHEN CHEN 7 1 CKABEN CKABEN 6 1 SCDEN SCDEN 5 1 SPICKSEL SPICKSEL 2 2 SITP SITP 0 2 CKOUTDIV Output serial clock divider 16 8 CKOUTSRC Output serial clock source selection 30 1 DFSDMEN Global enable for DFSDM interface 31 1 CH1CFGR2 CH1CFGR2 CHCFG1R2 0x24 0x20 read-write 0x0 OFFSET OFFSET 8 24 DTRBS DTRBS 3 5 CH1AWSCDR CH1AWSCDR AWSCD1R 0x28 0x20 read-write 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CH1WDATR CH1WDATR CHWDAT1R 0x2C 0x20 read-write 0x0 WDATA WDATA 0 16 CH1DATINR CH1DATINR CHDATIN1R 0x30 0x20 read-write 0x0 INDAT1 INDAT1 16 16 INDAT0 INDAT0 0 16 CH2CFGR1 CH2CFGR1 CHCFG2R1 0x40 0x20 read-write 0x0 DATPACK DATPACK 14 2 DATMPX DATMPX 12 2 CHINSEL CHINSEL 8 1 CHEN CHEN 7 1 CKABEN CKABEN 6 1 SCDEN SCDEN 5 1 SPICKSEL SPICKSEL 2 2 SITP SITP 0 2 CKOUTDIV Output serial clock divider 16 8 CKOUTSRC Output serial clock source selection 30 1 DFSDMEN Global enable for DFSDM interface 31 1 CH2CFGR2 CH2CFGR2 CHCFG2R2 0x44 0x20 read-write 0x0 OFFSET OFFSET 8 24 DTRBS DTRBS 3 5 CH2AWSCDR CH2AWSCDR AWSCD2R 0x48 0x20 read-write 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CH2WDATR CH2WDATR CHWDAT2R 0x4C 0x20 read-write 0x0 WDATA WDATA 0 16 CH2DATINR CH2DATINR CHDATIN2R 0x50 0x20 read-write 0x0 INDAT1 INDAT1 16 16 INDAT0 INDAT0 0 16 CH3CFGR1 CH3CFGR1 CHCFG3R1 0x60 0x20 read-write 0x0 DATPACK DATPACK 14 2 DATMPX DATMPX 12 2 CHINSEL CHINSEL 8 1 CHEN CHEN 7 1 CKABEN CKABEN 6 1 SCDEN SCDEN 5 1 SPICKSEL SPICKSEL 2 2 SITP SITP 0 2 CKOUTDIV Output serial clock divider 16 8 CKOUTSRC Output serial clock source selection 30 1 DFSDMEN Global enable for DFSDM interface 31 1 CH3CFGR2 CH3CFGR2 CHCFG3R2 0x64 0x20 read-write 0x0 OFFSET OFFSET 8 24 DTRBS DTRBS 3 5 CH3AWSCDR CH3AWSCDR AWSCD3R 0x68 0x20 read-write 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CH3WDATR CH3WDATR CHWDAT3R 0x6C 0x20 read-write 0x0 WDATA WDATA 0 16 CH3DATINR CH3DATINR CHDATIN3R 0x70 0x20 read-write 0x0 INDAT1 INDAT1 16 16 INDAT0 INDAT0 0 16 CH4CFGR1 CH4CFGR1 CHCFG4R1 0x80 0x20 read-write 0x0 DATPACK DATPACK 14 2 DATMPX DATMPX 12 2 CHINSEL CHINSEL 8 1 CHEN CHEN 7 1 CKABEN CKABEN 6 1 SCDEN SCDEN 5 1 SPICKSEL SPICKSEL 2 2 SITP SITP 0 2 CKOUTDIV Output serial clock divider 16 8 CKOUTSRC Output serial clock source selection 30 1 DFSDMEN Global enable for DFSDM interface 31 1 CH4CFGR2 CH4CFGR2 CHCFG4R2 0x84 0x20 read-write 0x0 OFFSET OFFSET 8 24 DTRBS DTRBS 3 5 CH4AWSCDR CH4AWSCDR AWSCD4R 0x88 0x20 read-write 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CH4WDATR CH4WDATR CHWDAT4R 0x8C 0x20 read-write 0x0 WDATA WDATA 0 16 CH4DATINR CH4DATINR CHDATIN4R 0x90 0x20 read-write 0x0 INDAT1 INDAT1 16 16 INDAT0 INDAT0 0 16 CH5CFGR1 CH5CFGR1 CHCFG5R1 0xA0 0x20 read-write 0x0 DATPACK DATPACK 14 2 DATMPX DATMPX 12 2 CHINSEL CHINSEL 8 1 CHEN CHEN 7 1 CKABEN CKABEN 6 1 SCDEN SCDEN 5 1 SPICKSEL SPICKSEL 2 2 SITP SITP 0 2 CKOUTDIV Output serial clock divider 16 8 CKOUTSRC Output serial clock source selection 30 1 DFSDMEN Global enable for DFSDM interface 31 1 CH5CFGR2 CH5CFGR2 CHCFG5R2 0xA4 0x20 read-write 0x0 OFFSET OFFSET 8 24 DTRBS DTRBS 3 5 CH5AWSCDR CH5AWSCDR AWSCD5R 0xA8 0x20 read-write 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CH5WDATR CH5WDATR CHWDAT5R 0xAC 0x20 read-write 0x0 WDATA WDATA 0 16 CH5DATINR CH5DATINR CHDATIN5R 0xB0 0x20 read-write 0x0 INDAT1 INDAT1 16 16 INDAT0 INDAT0 0 16 CH6CFGR1 CH6CFGR1 CHCFG6R1 0xC0 0x20 read-write 0x0 DATPACK DATPACK 14 2 DATMPX DATMPX 12 2 CHINSEL CHINSEL 8 1 CHEN CHEN 7 1 CKABEN CKABEN 6 1 SCDEN SCDEN 5 1 SPICKSEL SPICKSEL 2 2 SITP SITP 0 2 CKOUTDIV Output serial clock divider 16 8 CKOUTSRC Output serial clock source selection 30 1 DFSDMEN Global enable for DFSDM interface 31 1 CH6CFGR2 CH6CFGR2 CH6CFGR2 0xC4 0x20 read-write 0x0 OFFSET OFFSET 8 24 DTRBS DTRBS 3 5 CH6AWSCDR CH6AWSCDR AWSCD6R 0xC8 0x20 read-write 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CH6WDATR CH6WDATR CHWDAT6R 0xCC 0x20 read-write 0x0 WDATA WDATA 0 16 CH6DATINR CH6DATINR CHDATIN6R 0xD0 0x20 read-write 0x0 INDAT1 INDAT1 16 16 INDAT0 INDAT0 0 16 CH7CFGR1 CH7CFGR1 CHCFG7R1 0xE0 0x20 read-write 0x0 DATPACK DATPACK 14 2 DATMPX DATMPX 12 2 CHINSEL CHINSEL 8 1 CHEN CHEN 7 1 CKABEN CKABEN 6 1 SCDEN SCDEN 5 1 SPICKSEL SPICKSEL 2 2 SITP SITP 0 2 CKOUTDIV Output serial clock divider 16 8 CKOUTSRC Output serial clock source selection 30 1 DFSDMEN Global enable for DFSDM interface 31 1 CH7CFGR2 CH7CFGR2 CHCFG7R2 0xE4 0x20 read-write 0x0 OFFSET OFFSET 8 24 DTRBS DTRBS 3 5 CH7AWSCDR CH7AWSCDR AWSCD7R 0xE8 0x20 read-write 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CH7WDATR CH7WDATR CHWDAT7R 0xEC 0x20 read-write 0x0 WDATA WDATA 0 16 CH7DATINR CH7DATINR CHDATIN7R 0xF0 0x20 read-write 0x0 INDAT1 INDAT1 16 16 INDAT0 INDAT0 0 16 FLT0CR1 FLT0CR1 control register 1 0x100 0x20 read-write 0x00000000 AWFSEL Analog watchdog fast mode select 30 1 FAST Fast conversion mode selection for regular conversions 29 1 RCH Regular channel selection 24 3 RDMAEN DMA channel enabled to read data for the regular conversion 21 1 RSYNC Launch regular conversion synchronously with DFSDM0 19 1 RCONT Continuous mode selection for regular conversions 18 1 RSWSTART Software start of a conversion on the regular channel 17 1 JEXTEN Trigger enable and trigger edge selection for injected conversions 13 2 JEXTSEL Trigger signal selection for launching injected conversions 8 3 JDMAEN DMA channel enabled to read data for the injected channel group 5 1 JSCAN Scanning conversion mode for injected conversions 4 1 JSYNC Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 3 1 JSWSTART Start a conversion of the injected group of channels 1 1 DFEN DFSDM enable 0 1 FLT0CR2 FLT0CR2 control register 2 0x104 0x20 read-write 0x00000000 AWDCH Analog watchdog channel selection 16 8 EXCH Extremes detector channel selection 8 8 CKABIE Clock absence interrupt enable 6 1 SCDIE Short-circuit detector interrupt enable 5 1 AWDIE Analog watchdog interrupt enable 4 1 ROVRIE Regular data overrun interrupt enable 3 1 JOVRIE Injected data overrun interrupt enable 2 1 REOCIE Regular end of conversion interrupt enable 1 1 JEOCIE Injected end of conversion interrupt enable 0 1 FLT0ISR FLT0ISR interrupt and status register 0x108 0x20 read-only 0x00FF0000 SCDF short-circuit detector flag 24 8 CKABF Clock absence flag 16 8 RCIP Regular conversion in progress status 14 1 JCIP Injected conversion in progress status 13 1 AWDF Analog watchdog 4 1 ROVRF Regular conversion overrun flag 3 1 JOVRF Injected conversion overrun flag 2 1 REOCF End of regular conversion flag 1 1 JEOCF End of injected conversion flag 0 1 FLT0ICR FLT0ICR interrupt flag clear register 0x10C 0x20 read-write 0x00000000 CLRSCDF Clear the short-circuit detector flag 24 8 CLRCKABF Clear the clock absence flag 16 8 CLRROVRF Clear the regular conversion overrun flag 3 1 CLRJOVRF Clear the injected conversion overrun flag 2 1 FLT0JCHGR FLT0JCHGR injected channel group selection register 0x110 0x20 read-write 0x00000001 JCHG Injected channel group selection 0 8 FLT0FCR FLT0FCR filter control register 0x114 0x20 read-write 0x00000000 FORD Sinc filter order 29 3 FOSR Sinc filter oversampling ratio (decimation rate) 16 10 IOSR Integrator oversampling ratio (averaging length) 0 8 FLT0JDATAR FLT0JDATAR data register for injected group 0x118 0x20 read-only 0x00000000 JDATA Injected group conversion data 8 24 JDATACH Injected channel most recently converted 0 3 FLT0RDATAR FLT0RDATAR data register for the regular channel 0x11C 0x20 read-only 0x00000000 RDATA Regular channel conversion data 8 24 RPEND Regular channel pending data 4 1 RDATACH Regular channel most recently converted 0 3 FLT0AWHTR FLT0AWHTR analog watchdog high threshold register 0x120 0x20 read-write 0x00000000 AWHT Analog watchdog high threshold 8 24 BKAWH Break signal assignment to analog watchdog high threshold event 0 4 FLT0AWLTR FLT0AWLTR analog watchdog low threshold register 0x124 0x20 read-write 0x00000000 AWLT Analog watchdog low threshold 8 24 BKAWL Break signal assignment to analog watchdog low threshold event 0 4 FLT0AWSR FLT0AWSR analog watchdog status register 0x128 0x20 read-only 0x00000000 AWHTF Analog watchdog high threshold flag 8 8 AWLTF Analog watchdog low threshold flag 0 8 FLT0AWCFR FLT0AWCFR analog watchdog clear flag register 0x12C 0x20 read-write 0x00000000 CLRAWHTF Clear the analog watchdog high threshold flag 8 8 CLRAWLTF Clear the analog watchdog low threshold flag 0 8 FLT0EXMAX FLT0EXMAX Extremes detector maximum register 0x130 0x20 read-only 0x80000000 EXMAX Extremes detector maximum value 8 24 EXMAXCH Extremes detector maximum data channel 0 3 FLT0EXMIN FLT0EXMIN Extremes detector minimum register 0x134 0x20 read-only 0x7FFFFF00 EXMIN EXMIN 8 24 EXMINCH Extremes detector minimum data channel 0 3 FLT0CNVTIMR FLT0CNVTIMR conversion timer register 0x138 0x20 read-only 0x00000000 CNVCNT 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN 4 28 FLT1CR1 FLT1CR1 control register 1 0x180 0x20 read-write 0x00000000 AWFSEL Analog watchdog fast mode select 30 1 FAST Fast conversion mode selection for regular conversions 29 1 RCH Regular channel selection 24 3 RDMAEN DMA channel enabled to read data for the regular conversion 21 1 RSYNC Launch regular conversion synchronously with DFSDM0 19 1 RCONT Continuous mode selection for regular conversions 18 1 RSWSTART Software start of a conversion on the regular channel 17 1 JEXTEN Trigger enable and trigger edge selection for injected conversions 13 2 JEXTSEL Trigger signal selection for launching injected conversions 8 3 JDMAEN DMA channel enabled to read data for the injected channel group 5 1 JSCAN Scanning conversion mode for injected conversions 4 1 JSYNC Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 3 1 JSWSTART Start a conversion of the injected group of channels 1 1 DFEN DFSDM enable 0 1 FLT1CR2 FLT1CR2 control register 2 0x184 0x20 read-write 0x00000000 AWDCH Analog watchdog channel selection 16 8 EXCH Extremes detector channel selection 8 8 CKABIE Clock absence interrupt enable 6 1 SCDIE Short-circuit detector interrupt enable 5 1 AWDIE Analog watchdog interrupt enable 4 1 ROVRIE Regular data overrun interrupt enable 3 1 JOVRIE Injected data overrun interrupt enable 2 1 REOCIE Regular end of conversion interrupt enable 1 1 JEOCIE Injected end of conversion interrupt enable 0 1 FLT1ISR FLT1ISR interrupt and status register 0x188 0x20 read-only 0x00FF0000 SCDF short-circuit detector flag 24 8 CKABF Clock absence flag 16 8 RCIP Regular conversion in progress status 14 1 JCIP Injected conversion in progress status 13 1 AWDF Analog watchdog 4 1 ROVRF Regular conversion overrun flag 3 1 JOVRF Injected conversion overrun flag 2 1 REOCF End of regular conversion flag 1 1 JEOCF End of injected conversion flag 0 1 FLT1ICR FLT1ICR interrupt flag clear register 0x18C 0x20 read-write 0x00000000 CLRSCDF Clear the short-circuit detector flag 24 8 CLRCKABF Clear the clock absence flag 16 8 CLRROVRF Clear the regular conversion overrun flag 3 1 CLRJOVRF Clear the injected conversion overrun flag 2 1 FLT1JCHGR FLT1JCHGR injected channel group selection register 0x190 0x20 read-write 0x00000001 JCHG Injected channel group selection 0 8 FLT1FCR FLT1FCR filter control register 0x194 0x20 read-write 0x00000000 FORD Sinc filter order 29 3 FOSR Sinc filter oversampling ratio (decimation rate) 16 10 IOSR Integrator oversampling ratio (averaging length) 0 8 FLT1JDATAR FLT1JDATAR data register for injected group 0x198 0x20 read-only 0x00000000 JDATA Injected group conversion data 8 24 JDATACH Injected channel most recently converted 0 3 FLT1RDATAR FLT1RDATAR data register for the regular channel 0x19C 0x20 read-only 0x00000000 RDATA Regular channel conversion data 8 24 RPEND Regular channel pending data 4 1 RDATACH Regular channel most recently converted 0 3 FLT1AWHTR FLT1AWHTR analog watchdog high threshold register 0x1AC 0x20 read-write 0x00000000 AWHT Analog watchdog high threshold 8 24 BKAWH Break signal assignment to analog watchdog high threshold event 0 4 FLT1AWLTR FLT1AWLTR analog watchdog low threshold register 0x1A4 0x20 read-write 0x00000000 AWLT Analog watchdog low threshold 8 24 BKAWL Break signal assignment to analog watchdog low threshold event 0 4 FLT1AWSR FLT1AWSR analog watchdog status register 0x1A8 0x20 read-only 0x00000000 AWHTF Analog watchdog high threshold flag 8 8 AWLTF Analog watchdog low threshold flag 0 8 FLT1AWCFR FLT1AWCFR analog watchdog clear flag register FLT1AWHTR 0x1AC 0x20 read-write 0x00000000 CLRAWHTF Clear the analog watchdog high threshold flag 8 8 CLRAWLTF Clear the analog watchdog low threshold flag 0 8 FLT1EXMAX FLT1EXMAX Extremes detector maximum register 0x1B0 0x20 read-only 0x80000000 EXMAX Extremes detector maximum value 8 24 EXMAXCH Extremes detector maximum data channel 0 3 FLT1EXMIN FLT1EXMIN Extremes detector minimum register 0x1B4 0x20 read-only 0x7FFFFF00 EXMIN EXMIN 8 24 EXMINCH Extremes detector minimum data channel 0 3 FLT1CNVTIMR FLT1CNVTIMR conversion timer register 0x1B8 0x20 read-only 0x00000000 CNVCNT 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN 4 28 FLT2CR1 FLT2CR1 control register 1 0x200 0x20 read-write 0x00000000 AWFSEL Analog watchdog fast mode select 30 1 FAST Fast conversion mode selection for regular conversions 29 1 RCH Regular channel selection 24 3 RDMAEN DMA channel enabled to read data for the regular conversion 21 1 RSYNC Launch regular conversion synchronously with DFSDM0 19 1 RCONT Continuous mode selection for regular conversions 18 1 RSWSTART Software start of a conversion on the regular channel 17 1 JEXTEN Trigger enable and trigger edge selection for injected conversions 13 2 JEXTSEL Trigger signal selection for launching injected conversions 8 3 JDMAEN DMA channel enabled to read data for the injected channel group 5 1 JSCAN Scanning conversion mode for injected conversions 4 1 JSYNC Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 3 1 JSWSTART Start a conversion of the injected group of channels 1 1 DFEN DFSDM enable 0 1 FLT2CR2 FLT2CR2 control register 2 0x204 0x20 read-write 0x00000000 AWDCH Analog watchdog channel selection 16 8 EXCH Extremes detector channel selection 8 8 CKABIE Clock absence interrupt enable 6 1 SCDIE Short-circuit detector interrupt enable 5 1 AWDIE Analog watchdog interrupt enable 4 1 ROVRIE Regular data overrun interrupt enable 3 1 JOVRIE Injected data overrun interrupt enable 2 1 REOCIE Regular end of conversion interrupt enable 1 1 JEOCIE Injected end of conversion interrupt enable 0 1 FLT2ISR FLT2ISR interrupt and status register 0x208 0x20 read-only 0x00FF0000 SCDF short-circuit detector flag 24 8 CKABF Clock absence flag 16 8 RCIP Regular conversion in progress status 14 1 JCIP Injected conversion in progress status 13 1 AWDF Analog watchdog 4 1 ROVRF Regular conversion overrun flag 3 1 JOVRF Injected conversion overrun flag 2 1 REOCF End of regular conversion flag 1 1 JEOCF End of injected conversion flag 0 1 FLT2ICR FLT2ICR interrupt flag clear register 0x20C 0x20 read-write 0x00000000 CLRSCDF Clear the short-circuit detector flag 24 8 CLRCKABF Clear the clock absence flag 16 8 CLRROVRF Clear the regular conversion overrun flag 3 1 CLRJOVRF Clear the injected conversion overrun flag 2 1 FLT2JCHGR FLT2JCHGR injected channel group selection register 0x210 0x20 read-write 0x00000001 JCHG Injected channel group selection 0 8 FLT2FCR FLT2FCR filter control register 0x214 0x20 read-write 0x00000000 FORD Sinc filter order 29 3 FOSR Sinc filter oversampling ratio (decimation rate) 16 10 IOSR Integrator oversampling ratio (averaging length) 0 8 FLT2JDATAR FLT2JDATAR data register for injected group 0x218 0x20 read-only 0x00000000 JDATA Injected group conversion data 8 24 JDATACH Injected channel most recently converted 0 3 FLT2RDATAR FLT2RDATAR data register for the regular channel 0x21C 0x20 read-only 0x00000000 RDATA Regular channel conversion data 8 24 RPEND Regular channel pending data 4 1 RDATACH Regular channel most recently converted 0 3 FLT2AWHTR FLT2AWHTR analog watchdog high threshold register 0x220 0x20 read-write 0x00000000 AWHT Analog watchdog high threshold 8 24 BKAWH Break signal assignment to analog watchdog high threshold event 0 4 FLT2AWLTR FLT2AWLTR analog watchdog low threshold register 0x224 0x20 read-write 0x00000000 AWLT Analog watchdog low threshold 8 24 BKAWL Break signal assignment to analog watchdog low threshold event 0 4 FLT2AWSR FLT2AWSR analog watchdog status register 0x228 0x20 read-only 0x00000000 AWHTF Analog watchdog high threshold flag 8 8 AWLTF Analog watchdog low threshold flag 0 8 FLT2AWCFR FLT2AWCFR analog watchdog clear flag register 0x22C 0x20 read-write 0x00000000 CLRAWHTF Clear the analog watchdog high threshold flag 8 8 CLRAWLTF Clear the analog watchdog low threshold flag 0 8 FLT2EXMAX FLT2EXMAX Extremes detector maximum register 0x230 0x20 read-only 0x80000000 EXMAX Extremes detector maximum value 8 24 EXMAXCH Extremes detector maximum data channel 0 3 FLT2EXMIN FLT2EXMIN Extremes detector minimum register 0x234 0x20 read-only 0x7FFFFF00 EXMIN EXMIN 8 24 EXMINCH Extremes detector minimum data channel 0 3 FLT2CNVTIMR FLT2CNVTIMR conversion timer register 0x238 0x20 read-only 0x00000000 CNVCNT 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN 4 28 FLT3CR1 FLT3CR1 control register 1 0x280 0x20 read-write 0x00000000 AWFSEL Analog watchdog fast mode select 30 1 FAST Fast conversion mode selection for regular conversions 29 1 RCH Regular channel selection 24 3 RDMAEN DMA channel enabled to read data for the regular conversion 21 1 RSYNC Launch regular conversion synchronously with DFSDM0 19 1 RCONT Continuous mode selection for regular conversions 18 1 RSWSTART Software start of a conversion on the regular channel 17 1 JEXTEN Trigger enable and trigger edge selection for injected conversions 13 2 JEXTSEL Trigger signal selection for launching injected conversions 8 3 JDMAEN DMA channel enabled to read data for the injected channel group 5 1 JSCAN Scanning conversion mode for injected conversions 4 1 JSYNC Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 3 1 JSWSTART Start a conversion of the injected group of channels 1 1 DFEN DFSDM enable 0 1 FLT3CR2 FLT3CR2 control register 2 0x284 0x20 read-write 0x00000000 AWDCH Analog watchdog channel selection 16 8 EXCH Extremes detector channel selection 8 8 CKABIE Clock absence interrupt enable 6 1 SCDIE Short-circuit detector interrupt enable 5 1 AWDIE Analog watchdog interrupt enable 4 1 ROVRIE Regular data overrun interrupt enable 3 1 JOVRIE Injected data overrun interrupt enable 2 1 REOCIE Regular end of conversion interrupt enable 1 1 JEOCIE Injected end of conversion interrupt enable 0 1 FLT3ISR FLT3ISR interrupt and status register 0x288 0x20 read-only 0x00FF0000 SCDF short-circuit detector flag 24 8 CKABF Clock absence flag 16 8 RCIP Regular conversion in progress status 14 1 JCIP Injected conversion in progress status 13 1 AWDF Analog watchdog 4 1 ROVRF Regular conversion overrun flag 3 1 JOVRF Injected conversion overrun flag 2 1 REOCF End of regular conversion flag 1 1 JEOCF End of injected conversion flag 0 1 FLT3ICR FLT3ICR interrupt flag clear register 0x28C 0x20 read-write 0x00000000 CLRSCDF Clear the short-circuit detector flag 24 8 CLRCKABF Clear the clock absence flag 16 8 CLRROVRF Clear the regular conversion overrun flag 3 1 CLRJOVRF Clear the injected conversion overrun flag 2 1 FLT3JCHGR FLT3JCHGR injected channel group selection register 0x290 0x20 read-write 0x00000001 JCHG Injected channel group selection 0 8 FLT3FCR FLT3FCR filter control register 0x294 0x20 read-write 0x00000000 FORD Sinc filter order 29 3 FOSR Sinc filter oversampling ratio (decimation rate) 16 10 IOSR Integrator oversampling ratio (averaging length) 0 8 FLT3JDATAR FLT3JDATAR data register for injected group 0x298 0x20 read-only 0x00000000 JDATA Injected group conversion data 8 24 JDATACH Injected channel most recently converted 0 3 FLT3RDATAR FLT3RDATAR data register for the regular channel 0x29C 0x20 read-only 0x00000000 RDATA Regular channel conversion data 8 24 RPEND Regular channel pending data 4 1 RDATACH Regular channel most recently converted 0 3 FLT3AWHTR FLT3AWHTR analog watchdog high threshold register 0x2A0 0x20 read-write 0x00000000 AWHT Analog watchdog high threshold 8 24 BKAWH Break signal assignment to analog watchdog high threshold event 0 4 FLT3AWLTR FLT3AWLTR analog watchdog low threshold register 0x2A4 0x20 read-write 0x00000000 AWLT Analog watchdog low threshold 8 24 BKAWL Break signal assignment to analog watchdog low threshold event 0 4 FLT3AWSR FLT3AWSR analog watchdog status register 0x2A8 0x20 read-only 0x00000000 AWHTF Analog watchdog high threshold flag 8 8 AWLTF Analog watchdog low threshold flag 0 8 FLT3AWCFR FLT3AWCFR analog watchdog clear flag register 0x2AC 0x20 read-write 0x00000000 CLRAWHTF Clear the analog watchdog high threshold flag 8 8 CLRAWLTF Clear the analog watchdog low threshold flag 0 8 FLT3EXMAX FLT3EXMAX Extremes detector maximum register 0x2B0 0x20 read-only 0x80000000 EXMAX Extremes detector maximum value 8 24 EXMAXCH Extremes detector maximum data channel 0 3 FLT3EXMIN FLT3EXMIN Extremes detector minimum register 0x2B4 0x20 read-only 0x7FFFFF00 EXMIN EXMIN 8 24 EXMINCH Extremes detector minimum data channel 0 3 FLT3CNVTIMR FLT3CNVTIMR conversion timer register 0x2B8 0x20 read-only 0x00000000 CNVCNT 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN 4 28 CH0DLYR CH0DLYR DFSDM channel y delay register 0x14 0x20 read-write 0x00000000 PLSSKP Pulses to skip for input data skipping function 0 6 CH1DLYR CH1DLYR DFSDM channel y delay register 0x34 0x20 read-write 0x00000000 PLSSKP PLSSKP 0 6 CH2DLYR CH2DLYR DFSDM channel y delay register 0x54 0x20 read-write 0x00000000 PLSSKP PLSSKP 0 6 CH3DLYR CH3DLYR DFSDM channel y delay register 0x74 0x20 read-write 0x00000000 PLSSKP PLSSKP 0 6 CH4DLYR CH4DLYR DFSDM channel y delay register 0x94 0x20 read-write 0x00000000 PLSSKP PLSSKP 0 6 CH5DLYR CH5DLYR DFSDM channel y delay register 0xB4 0x20 read-write 0x00000000 PLSSKP read-only 0 6 CH6DLYR CH6DLYR DFSDM channel y delay register 0xD4 0x20 read-write 0x00000000 PLSSKP PLSSKP 0 6 CH7DLYR CH7DLYR DFSDM channel y delay register 0xF4 0x20 read-write 0x00000000 PLSSKP PLSSKP 0 6 SEC_DFSDM1 !(DCB->DSCSR & (1 << 16)) 0x50016000 DMAMUX1 Direct memory access Multiplexer DMAMUX 0x40020800 0x0 0x400 registers DMAMUX1_OVR DMAMUX overrun interrupt 027 DMAMUX1_OVR_S DMAMUX1 secure overRun interrupt 028 C0CR C0CR DMA Multiplexer Channel 0 Control register 0x0 0x20 read-write 0x00000000 SYNC_ID SYNC_ID 24 5 NBREQ Nb request 19 5 SPOL Sync polarity 17 2 SE Synchronization enable 16 1 EGE Event Generation Enable 9 1 SOIE Synchronization Overrun Interrupt Enable 8 1 DMAREQ_ID DMA Request ID 0 7 C1CR C1CR DMA Multiplexer Channel 1 Control register 0x4 0x20 read-write 0x00000000 SYNC_ID SYNC_ID 24 5 NBREQ Nb request 19 5 SPOL Sync polarity 17 2 SE Synchronization enable 16 1 EGE Event Generation Enable 9 1 SOIE Synchronization Overrun Interrupt Enable 8 1 DMAREQ_ID DMA Request ID 0 7 C2CR C2CR DMA Multiplexer Channel 2 Control register 0x8 0x20 read-write 0x00000000 SYNC_ID SYNC_ID 24 5 NBREQ Nb request 19 5 SPOL Sync polarity 17 2 SE Synchronization enable 16 1 EGE Event Generation Enable 9 1 SOIE Synchronization Overrun Interrupt Enable 8 1 DMAREQ_ID DMA Request ID 0 7 C3CR C3CR DMA Multiplexer Channel 3 Control register 0xC 0x20 read-write 0x00000000 SYNC_ID SYNC_ID 24 5 NBREQ Nb request 19 5 SPOL Sync polarity 17 2 SE Synchronization enable 16 1 EGE Event Generation Enable 9 1 SOIE Synchronization Overrun Interrupt Enable 8 1 DMAREQ_ID DMA Request ID 0 7 C4CR C4CR DMA Multiplexer Channel 4 Control register 0x10 0x20 read-write 0x00000000 SYNC_ID SYNC_ID 24 5 NBREQ Nb request 19 5 SPOL Sync polarity 17 2 SE Synchronization enable 16 1 EGE Event Generation Enable 9 1 SOIE Synchronization Overrun Interrupt Enable 8 1 DMAREQ_ID DMA Request ID 0 7 C5CR C5CR DMA Multiplexer Channel 5 Control register 0x14 0x20 read-write 0x00000000 SYNC_ID SYNC_ID 24 5 NBREQ Nb request 19 5 SPOL Sync polarity 17 2 SE Synchronization enable 16 1 EGE Event Generation Enable 9 1 OIE Synchronization Overrun Interrupt Enable 8 1 DMAREQ_ID DMA Request ID 0 7 C6CR C6CR DMA Multiplexer Channel 6 Control register 0x18 0x20 read-write 0x00000000 SYNC_ID SYNC_ID 24 5 NBREQ Nb request 19 5 SPOL Sync polarity 17 2 SE Synchronization enable 16 1 EGE Event Generation Enable 9 1 SOIE Synchronization Overrun Interrupt Enable 8 1 DMAREQ_ID DMA Request ID 0 7 C7CR C7CR DMA Multiplexer Channel 7 Control register 0x1C 0x20 read-write 0x00000000 SYNC_ID SYNC_ID 24 5 NBREQ Nb request 19 5 SPOL Sync polarity 17 2 SE Synchronization enable 16 1 EGE Event Generation Enable 9 1 SOIE Synchronization Overrun Interrupt Enable 8 1 DMAREQ_ID DMA Request ID 0 7 C8CR C8CR DMA Multiplexer Channel 8 Control register 0x20 0x20 read-write 0x00000000 SYNC_ID SYNC_ID 24 5 NBREQ Nb request 19 5 SPOL Sync polarity 17 2 SE Synchronization enable 16 1 EGE Event Generation Enable 9 1 SOIE Synchronization Overrun Interrupt Enable 8 1 DMAREQ_ID DMA Request ID 0 7 C9CR C9CR DMA Multiplexer Channel 9 Control register 0x24 0x20 read-write 0x00000000 SYNC_ID SYNC_ID 24 5 NBREQ Nb request 19 5 SPOL Sync polarity 17 2 SE Synchronization enable 16 1 EGE Event Generation Enable 9 1 SOIE Synchronization Overrun Interrupt Enable 8 1 DMAREQ_ID DMA Request ID 0 7 C10CR C10CR DMA Multiplexer Channel 10 Control register 0x28 0x20 read-write 0x00000000 SYNC_ID SYNC_ID 24 5 NBREQ Nb request 19 5 SPOL Sync polarity 17 2 SE Synchronization enable 16 1 EGE Event Generation Enable 9 1 SOIE Synchronization Overrun Interrupt Enable 8 1 DMAREQ_ID DMA Request ID 0 7 C11CR C11CR DMA Multiplexer Channel 11 Control register 0x2C 0x20 read-write 0x00000000 SYNC_ID SYNC_ID 24 5 NBREQ Nb request 19 5 SPOL Sync polarity 17 2 SE Synchronization enable 16 1 EGE Event Generation Enable 9 1 SOIE Synchronization Overrun Interrupt Enable 8 1 DMAREQ_ID DMA Request ID 0 7 C12CR C12CR DMA Multiplexer Channel 12 Control register 0x30 0x20 read-write 0x00000000 SYNC_ID SYNC_ID 24 5 NBREQ Nb request 19 5 SPOL Sync polarity 17 2 SE Synchronization enable 16 1 EGE Event Generation Enable 9 1 SOIE Synchronization Overrun Interrupt Enable 8 1 DMAREQ_ID DMA Request ID 0 7 C13CR C13CR DMA Multiplexer Channel 13 Control register 0x34 0x20 read-write 0x00000000 SYNC_ID SYNC_ID 24 5 NBREQ Nb request 19 5 SPOL Sync polarity 17 2 SE Synchronization enable 16 1 EGE Event Generation Enable 9 1 SOIE Synchronization Overrun Interrupt Enable 8 1 DMAREQ_ID DMA Request ID 0 7 CSR CSR DMA Multiplexer Channel Status register 0x80 0x20 read-write 0x00000000 SOF0 Synchronization Overrun Flag 0 0 1 SOF1 Synchronization Overrun Flag 1 1 1 SOF2 Synchronization Overrun Flag 2 2 1 SOF3 Synchronization Overrun Flag 3 3 1 SOF4 Synchronization Overrun Flag 4 4 1 SOF5 Synchronization Overrun Flag 5 5 1 SOF6 Synchronization Overrun Flag 6 6 1 SOF7 Synchronization Overrun Flag 7 7 1 SOF8 Synchronization Overrun Flag 8 8 1 SOF9 Synchronization Overrun Flag 9 9 1 SOF10 Synchronization Overrun Flag 10 10 1 SOF11 Synchronization Overrun Flag 11 11 1 SOF12 Synchronization Overrun Flag 12 12 1 SOF13 Synchronization Overrun Flag 13 13 1 SOF14 Synchronization Overrun Flag 13 14 1 SOF15 Synchronization Overrun Flag 13 15 1 CCFR CCFR DMA Channel Clear Flag Register 0x84 0x20 read-write 0x00000000 CSOF0 Synchronization Clear Overrun Flag 0 0 1 CSOF1 Synchronization Clear Overrun Flag 1 1 1 CSOF2 Synchronization Clear Overrun Flag 2 2 1 CSOF3 Synchronization Clear Overrun Flag 3 3 1 CSOF4 Synchronization Clear Overrun Flag 4 4 1 CSOF5 Synchronization Clear Overrun Flag 5 5 1 CSOF6 Synchronization Clear Overrun Flag 6 6 1 CSOF7 Synchronization Clear Overrun Flag 7 7 1 CSOF8 Synchronization Clear Overrun Flag 8 8 1 CSOF9 Synchronization Clear Overrun Flag 9 9 1 CSOF10 Synchronization Clear Overrun Flag 10 10 1 CSOF11 Synchronization Clear Overrun Flag 11 11 1 CSOF12 Synchronization Clear Overrun Flag 12 12 1 CSOF13 Synchronization Clear Overrun Flag 13 13 1 CSOF14 Synchronization Clear Overrun Flag 13 14 1 CSOF15 Synchronization Clear Overrun Flag 13 15 1 RG0CR RG0CR DMA Request Generator 0 Control Register 0x100 0x20 read-write 0x00000000 GNBREQ Number of Request 19 5 GPOL Generation Polarity 17 2 GE Generation Enable 16 1 OIE Overrun Interrupt Enable 8 1 SIG_ID Signal ID 0 5 RG1CR RG1CR DMA Request Generator 1 Control Register 0x104 0x20 read-write 0x00000000 GNBREQ Number of Request 19 5 GPOL Generation Polarity 17 2 GE Generation Enable 16 1 OIE Overrun Interrupt Enable 8 1 SIG_ID Signal ID 0 5 RG2CR RG2CR DMA Request Generator 2 Control Register 0x108 0x20 read-write 0x00000000 GNBREQ Number of Request 19 5 GPOL Generation Polarity 17 2 GE Generation Enable 16 1 OIE Overrun Interrupt Enable 8 1 SIG_ID Signal ID 0 5 RG3CR RG3CR DMA Request Generator 3 Control Register 0x10C 0x20 read-write 0x00000000 GNBREQ Number of Request 19 5 GPOL Generation Polarity 17 2 GE Generation Enable 16 1 OIE Overrun Interrupt Enable 8 1 SIG_ID Signal ID 0 5 RGSR RGSR DMA Request Generator Status Register 0x140 0x20 read-only 0x00000000 OF0 Generator Overrun Flag 0 0 1 OF1 Generator Overrun Flag 1 1 1 OF2 Generator Overrun Flag 2 2 1 OF3 Generator Overrun Flag 3 3 1 RGCFR RGCFR DMA Request Generator Clear Flag Register 0x144 0x20 read-write 0x00000000 CSOF0 Generator Clear Overrun Flag 0 0 1 CSOF1 Generator Clear Overrun Flag 1 1 1 CSOF2 Generator Clear Overrun Flag 2 2 1 CSOF3 Generator Clear Overrun Flag 3 3 1 C14CR C14CR DMA Multiplexer Channel 10 Control register 0x138 0x20 read-write 0x00000000 SYNC_ID Synchronization identification 24 5 NBREQ Number of DMA requests minus 1 to forward 19 5 SPOL Synchronization polarity 17 2 SE Synchronization enable 16 1 EGE Event generation enable 9 1 SOIE Synchronization overrun interrupt enable 8 1 DMAREQ_ID DMA request identification 0 7 C15CR C15CR DMA Multiplexer Channel 10 Control register 0x13C 0x20 read-write 0x00000000 SYNC_ID Synchronization identification 24 5 NBREQ Number of DMA requests minus 1 to forward 19 5 SPOL Synchronization polarity 17 2 SE Synchronization enable 16 1 EGE Event generation enable 9 1 SOIE Synchronization overrun interrupt enable 8 1 DMAREQ_ID DMA request identification 0 7 SEC_DMAMUX1 !(DCB->DSCSR & (1 << 16)) 0x50020800 EXTI External interrupt/event controller EXTI 0x4002F400 0x0 0x400 registers PVD_PVM PVD/PVM1/PVM2/PVM3/PVM4 through EXTI 001 TAMP TAMPTamper global interrupt (EXTI line 19) 004 TAMP_S Tamper secure global interrupt (EXTI line 20) 005 EXTI0 EXTI line0 interrupt 011 EXTI1 EXTI line1 interrupt 012 EXTI2 EXTI line2 interrupt 013 EXTI3 EXTI line3 interrupt 014 EXTI4 EXTI line4 interrupt 015 EXTI5 EXTI line5 interrupt 016 EXTI6 EXTI line6 interrupt 017 EXTI7 EXTI line7 interrupt 018 EXTI8 EXTI line8 interrupt 019 EXTI9 EXTI line9 interrupt 020 EXTI10 EXTI line10 interrupt 021 EXTI11 EXTI line11 interrupt 022 EXTI12 EXTI line12 interrupt 023 EXTI13 EXTI line13 interrupt 024 EXTI14 EXTI line14 interrupt 025 EXTI15 EXTI line15 interrupt 026 RTSR1 RTSR1 EXTI rising trigger selection register 0x0 0x20 read-write 0x00000000 RT0 Rising trigger event configuration bit of configurable event input x 0 1 RT1 Rising trigger event configuration bit of configurable event input x 1 1 RT2 Rising trigger event configuration bit of configurable event input x 2 1 RT3 Rising trigger event configuration bit of configurable event input x 3 1 RT4 Rising trigger event configuration bit of configurable event input x 4 1 RT5 Rising trigger event configuration bit of configurable event input x 5 1 RT6 Rising trigger event configuration bit of configurable event input x 6 1 RT7 Rising trigger event configuration bit of configurable event input x 7 1 RT8 Rising trigger event configuration bit of configurable event input x 8 1 RT9 Rising trigger event configuration bit of configurable event input x 9 1 RT10 Rising trigger event configuration bit of configurable event input x 10 1 RT11 Rising trigger event configuration bit of configurable event input x 11 1 RT12 Rising trigger event configuration bit of configurable event input x 12 1 RT13 Rising trigger event configuration bit of configurable event input x 13 1 RT14 Rising trigger event configuration bit of configurable event input x 14 1 RT15 Rising trigger event configuration bit of configurable event input x 15 1 RT16 Rising trigger event configuration bit of configurable event input x 16 1 RT21 Rising trigger event configuration bit of configurable event input x 21 1 RT22 Rising trigger event configuration bit of configurable event input x 22 1 FTSR1 FTSR1 EXTI falling trigger selection register 0x4 0x20 read-write 0x00000000 FT0 Falling trigger event configuration bit of configurable event input x 0 1 FT1 Falling trigger event configuration bit of configurable event input x 1 1 FT2 Falling trigger event configuration bit of configurable event input x 2 1 FT3 Falling trigger event configuration bit of configurable event input x 3 1 FT4 Falling trigger event configuration bit of configurable event input x 4 1 FT5 Falling trigger event configuration bit of configurable event input x 5 1 FT6 Falling trigger event configuration bit of configurable event input x 6 1 FT7 Falling trigger event configuration bit of configurable event input x 7 1 FT8 Falling trigger event configuration bit of configurable event input x 8 1 FT9 Falling trigger event configuration bit of configurable event input x 9 1 FT10 Falling trigger event configuration bit of configurable event input x 10 1 FT11 Falling trigger event configuration bit of configurable event input x 11 1 FT12 Falling trigger event configuration bit of configurable event input x 12 1 FT13 Falling trigger event configuration bit of configurable event input x 13 1 FT14 Falling trigger event configuration bit of configurable event input x 14 1 FT15 Falling trigger event configuration bit of configurable event input x 15 1 FT16 Falling trigger event configuration bit of configurable event input x 16 1 FT21 Falling trigger event configuration bit of configurable event input x 21 1 FT22 Falling trigger event configuration bit of configurable event input x 22 1 SWIER1 SWIER1 EXTI software interrupt event register 0x8 0x20 read-write 0x00000000 SWI0 Software interrupt on event x 0 1 SWI1 Software interrupt on event x 1 1 SWI2 Software interrupt on event x 2 1 SWI3 Software interrupt on event x 3 1 SWI4 Software interrupt on event x 4 1 SWI5 Software interrupt on event x 5 1 SWI6 Software interrupt on event x 6 1 SWI7 Software interrupt on event x 7 1 SWI8 Software interrupt on event x 8 1 SWI9 Software interrupt on event x 9 1 SWI10 Software interrupt on event x 10 1 SWI11 Software interrupt on event x 11 1 SWI12 Software interrupt on event x 12 1 SWI13 Software interrupt on event x 13 1 SWI14 Software interrupt on event x 14 1 SWI15 Software interrupt on event x 15 1 SWI16 Software interrupt on event x 16 1 SWI21 Software interrupt on event x 21 1 SWI22 Software interrupt on event x 22 1 RPR1 RPR1 EXTI rising edge pending register 0xC 0x20 read-write 0x00000000 RPIF0 configurable event inputs x rising edge pending bit 0 1 RPIF1 configurable event inputs x rising edge pending bit 1 1 RPIF2 configurable event inputs x rising edge pending bit 2 1 RPIF3 configurable event inputs x rising edge pending bit 3 1 RPIF4 configurable event inputs x rising edge pending bit 4 1 RPIF5 configurable event inputs x rising edge pending bit 5 1 RPIF6 configurable event inputs x rising edge pending bit 6 1 RPIF7 configurable event inputs x rising edge pending bit 7 1 RPIF8 configurable event inputs x rising edge pending bit 8 1 RPIF9 configurable event inputs x rising edge pending bit 9 1 RPIF10 configurable event inputs x rising edge pending bit 10 1 RPIF11 configurable event inputs x rising edge pending bit 11 1 RPIF12 configurable event inputs x rising edge pending bit 12 1 RPIF13 configurable event inputs x rising edge pending bit 13 1 RPIF14 configurable event inputs x rising edge pending bit 14 1 RPIF15 configurable event inputs x rising edge pending bit 15 1 RPIF16 configurable event inputs x rising edge pending bit 16 1 RPIF21 configurable event inputs x rising edge pending bit 21 1 RPIF22 configurable event inputs x rising edge pending bit 22 1 FPR1 FPR1 EXTI falling edge pending register 0x10 0x20 read-write 0x00000000 FPIF0 configurable event inputs x falling edge pending bit. 0 1 FPIF1 configurable event inputs x falling edge pending bit. 1 1 FPIF2 configurable event inputs x falling edge pending bit. 2 1 FPIF3 configurable event inputs x falling edge pending bit. 3 1 FPIF4 configurable event inputs x falling edge pending bit. 4 1 FPIF5 configurable event inputs x falling edge pending bit. 5 1 FPIF6 configurable event inputs x falling edge pending bit. 6 1 FPIF7 configurable event inputs x falling edge pending bit. 7 1 FPIF8 configurable event inputs x falling edge pending bit. 8 1 FPIF9 configurable event inputs x falling edge pending bit. 9 1 FPIF10 configurable event inputs x falling edge pending bit. 10 1 FPIF11 configurable event inputs x falling edge pending bit. 11 1 FPIF12 configurable event inputs x falling edge pending bit. 12 1 FPIF13 configurable event inputs x falling edge pending bit. 13 1 FPIF14 configurable event inputs x falling edge pending bit. 14 1 FPIF15 configurable event inputs x falling edge pending bit. 15 1 FPIF16 configurable event inputs x falling edge pending bit. 16 1 FPIF21 configurable event inputs x falling edge pending bit. 21 1 FPIF22 configurable event inputs x falling edge pending bit. 22 1 SECCFGR1 SECCFGR1 EXTI security configuration register 0x14 0x20 read-write 0x00000000 SEC0 Security enable on event input x 0 1 SEC1 Security enable on event input x 1 1 SEC2 Security enable on event input x 2 1 SEC3 Security enable on event input x 3 1 SEC4 Security enable on event input x 4 1 SEC5 Security enable on event input x 5 1 SEC6 Security enable on event input x 6 1 SEC7 Security enable on event input x 7 1 SEC8 Security enable on event input x 8 1 SEC9 Security enable on event input x 9 1 SEC10 Security enable on event input x 10 1 SEC11 Security enable on event input x 11 1 SEC12 Security enable on event input x 12 1 SEC13 Security enable on event input x 13 1 SEC14 Security enable on event input x 14 1 SEC15 Security enable on event input x 15 1 SEC16 Security enable on event input x 16 1 SEC17 Security enable on event input x 17 1 SEC18 Security enable on event input x 18 1 SEC19 Security enable on event input x 19 1 SEC20 Security enable on event input x 20 1 SEC21 Security enable on event input x 21 1 SEC22 Security enable on event input x 22 1 SEC23 Security enable on event input x 23 1 SEC24 Security enable on event input x 24 1 SEC25 Security enable on event input x 25 1 SEC26 Security enable on event input x 26 1 SEC27 Security enable on event input x 27 1 SEC28 Security enable on event input x 28 1 SEC29 Security enable on event input x 29 1 SEC30 Security enable on event input x 30 1 SEC31 Security enable on event input x 31 1 PRIVCFGR1 PRIVCFGR1 EXTI privilege configuration register 0x18 0x20 read-write 0x00000000 PRIV0 Security enable on event input x 0 1 PRIV1 Security enable on event input x 1 1 PRIV2 Security enable on event input x 2 1 PRIV3 Security enable on event input x 3 1 PRIV4 Security enable on event input x 4 1 PRIV5 Security enable on event input x 5 1 PRIV6 Security enable on event input x 6 1 PRIV7 Security enable on event input x 7 1 PRIV8 Security enable on event input x 8 1 PRIV9 Security enable on event input x 9 1 PRIV10 Security enable on event input x 10 1 PRIV11 Security enable on event input x 11 1 PRIV12 Security enable on event input x 12 1 PRIV13 Security enable on event input x 13 1 PRIV14 Security enable on event input x 14 1 PRIV15 Security enable on event input x 15 1 PRIV16 Security enable on event input x 16 1 PRIV17 Security enable on event input x 17 1 PRIV18 Security enable on event input x 18 1 PRIV19 Security enable on event input x 19 1 PRIV20 Security enable on event input x 20 1 PRIV21 Security enable on event input x 21 1 PRIV22 Security enable on event input x 22 1 PRIV23 Security enable on event input x 23 1 PRIV24 Security enable on event input x 24 1 PRIV25 Security enable on event input x 25 1 PRIV26 Security enable on event input x 26 1 PRIV27 Security enable on event input x 27 1 PRIV28 Security enable on event input x 28 1 PRIV29 Security enable on event input x 29 1 PRIV30 Security enable on event input x 30 1 PRIV31 Security enable on event input x 31 1 RTSR2 RTSR2 EXTI rising trigger selection register 0x20 0x20 read-write 0x00000000 RT35 Rising trigger event configuration bit of configurable event input x 3 1 RT36 Rising trigger event configuration bit of configurable event input x 4 1 RT37 Rising trigger event configuration bit of configurable event input x 5 1 RT38 Rising trigger event configuration bit of configurable event input x 6 1 FTSR2 FTSR2 EXTI falling trigger selection register 0x24 0x20 read-write 0x00000000 FT35 FT35 3 1 FT36 FT36 4 1 FT37 FT37 5 1 FT38 FT38 6 1 SWIER2 SWIER2 EXTI software interrupt event register 0x28 0x20 read-write 0x00000000 SWI35 SWI35 3 1 SWI36 SWI36 4 1 SWI37 SWI37 5 1 SWI38 SWI38 6 1 RPR2 RPR2 EXTI rising edge pending register 0x2C 0x20 read-write 0x00000000 RPIF35 RPIF35 3 1 RPIF36 RPIF36 4 1 RPIF37 RPIF37 5 1 RPIF38 RPIF38 6 1 FPR2 FPR2 EXTI falling edge pending register 0x30 0x20 read-write 0x00000000 FPIF35 FPIF35 3 1 FPIF36 FPIF36 4 1 FPIF37 FPIF37 5 1 FPIF38 FPIF38 6 1 SECCFGR2 SECCFGR2 EXTI security enable register 0x38 0x20 read-write 0x00000000 SEC32 SEC32 0 1 SEC33 SEC33 1 1 SEC34 SEC34 2 1 SEC35 SEC35 3 1 SEC36 SEC36 4 1 SEC37 SEC37 5 1 SEC38 SEC38 6 1 SEC39 SEC39 7 1 SEC40 SEC40 8 1 SEC41 SEC41 9 1 SEC42 SEC42 10 1 PRIVCFGR2 PRIVCFGR2 EXTI security enable register 0x34 0x20 read-write 0x00000000 PRIV32 PRIV32 0 1 PRIV33 PRIV33 1 1 PRIV34 PRIV34 2 1 PRIV35 PRIV35 3 1 PRIV36 PRIV36 4 1 PRIV37 PRIV37 5 1 PRIV38 PRIV38 6 1 PRIV39 PRIV39 7 1 PRIV40 PRIV40 8 1 PRIV41 PRIV41 9 1 PRIV42 PRIV42 10 1 EXTICR1 EXTICR1 EXTI external interrupt selection register 0x60 0x20 read-write 0x00000000 EXTI0_7 EXTIm GPIO port selection 0 8 EXTI8_15 EXTIm+1 GPIO port selection 8 8 EXTI16_23 EXTIm+2 GPIO port selection 16 8 EXTI24_31 EXTIm+3 GPIO port selection 24 8 EXTICR2 EXTICR2 EXTI external interrupt selection register 0x64 0x20 read-write 0x00000000 EXTI0_7 EXTIm GPIO port selection 0 8 EXTI8_15 EXTIm+1 GPIO port selection 8 8 EXTI16_23 EXTIm+2 GPIO port selection 16 8 EXTI24_31 EXTIm+3 GPIO port selection 24 8 EXTICR3 EXTICR3 EXTI external interrupt selection register 0x68 0x20 read-write 0x00000000 EXTI0_7 EXTIm GPIO port selection 0 8 EXTI8_15 EXTIm+1 GPIO port selection 8 8 EXTI16_23 EXTIm+2 GPIO port selection 16 8 EXTI24_31 EXTIm+3 GPIO port selection 24 8 EXTICR4 EXTICR4 EXTI external interrupt selection register 0x6C 0x20 read-write 0x00000000 EXTI0_7 EXTIm GPIO port selection 0 8 EXTI8_15 EXTIm+1 GPIO port selection 8 8 EXTI16_23 EXTIm+2 GPIO port selection 16 8 EXTI24_31 EXTIm+3 GPIO port selection 24 8 LOCKRG LOCKRG EXTI lock register 0x70 0x20 read-write 0x00000000 LOCK LOCK 0 1 IMR1 IMR1 EXTI CPU wakeup with interrupt mask register 0x80 0x20 read-write 0xFF9E0000 IM0 CPU wakeup with interrupt mask on event input 0 1 IM1 CPU wakeup with interrupt mask on event input 1 1 IM2 CPU wakeup with interrupt mask on event input 2 1 IM3 CPU wakeup with interrupt mask on event input 3 1 IM4 CPU wakeup with interrupt mask on event input 4 1 IM5 CPU wakeup with interrupt mask on event input 5 1 IM6 CPU wakeup with interrupt mask on event input 6 1 IM7 CPU wakeup with interrupt mask on event input 7 1 IM8 CPU wakeup with interrupt mask on event input 8 1 IM9 CPU wakeup with interrupt mask on event input 9 1 IM10 CPU wakeup with interrupt mask on event input 10 1 IM11 CPU wakeup with interrupt mask on event input 11 1 IM12 CPU wakeup with interrupt mask on event input 12 1 IM13 CPU wakeup with interrupt mask on event input 13 1 IM14 CPU wakeup with interrupt mask on event input 14 1 IM15 CPU wakeup with interrupt mask on event input 15 1 IM16 CPU wakeup with interrupt mask on event input 16 1 IM17 CPU wakeup with interrupt mask on event input 17 1 IM18 CPU wakeup with interrupt mask on event input 18 1 IM19 CPU wakeup with interrupt mask on event input 19 1 IM20 CPU wakeup with interrupt mask on event input 20 1 IM21 CPU wakeup with interrupt mask on event input 21 1 IM22 CPU wakeup with interrupt mask on event input 22 1 IM23 CPU wakeup with interrupt mask on event input 23 1 IM24 CPU wakeup with interrupt mask on event input 24 1 IM25 CPU wakeup with interrupt mask on event input 25 1 IM26 CPU wakeup with interrupt mask on event input 26 1 IM27 CPU wakeup with interrupt mask on event input 27 1 IM28 CPU wakeup with interrupt mask on event input 28 1 IM29 CPU wakeup with interrupt mask on event input 29 1 IM30 CPU wakeup with interrupt mask on event input 30 1 IM31 CPU wakeup with interrupt mask on event input 31 1 EMR1 EMR1 EXTI CPU wakeup with event mask register 0x84 0x20 read-write 0x00000000 EM0 CPU wakeup with interrupt mask on event input 0 1 EM1 CPU wakeup with interrupt mask on event input 1 1 EM2 CPU wakeup with interrupt mask on event input 2 1 EM3 CPU wakeup with interrupt mask on event input 3 1 EM4 CPU wakeup with interrupt mask on event input 4 1 EM5 CPU wakeup with interrupt mask on event input 5 1 EM6 CPU wakeup with interrupt mask on event input 6 1 EM7 CPU wakeup with interrupt mask on event input 7 1 EM8 CPU wakeup with interrupt mask on event input 8 1 EM9 CPU wakeup with interrupt mask on event input 9 1 EM10 CPU wakeup with interrupt mask on event input 10 1 EM11 CPU wakeup with interrupt mask on event input 11 1 EM12 CPU wakeup with interrupt mask on event input 12 1 EM13 CPU wakeup with interrupt mask on event input 13 1 EM14 CPU wakeup with interrupt mask on event input 14 1 EM15 CPU wakeup with interrupt mask on event input 15 1 EM16 CPU wakeup with interrupt mask on event input 16 1 EM17 CPU wakeup with interrupt mask on event input 17 1 EM18 CPU wakeup with interrupt mask on event input 18 1 EM19 CPU wakeup with interrupt mask on event input 19 1 EM20 CPU wakeup with interrupt mask on event input 20 1 EM21 CPU wakeup with interrupt mask on event input 21 1 EM22 CPU wakeup with interrupt mask on event input 22 1 EM23 CPU wakeup with interrupt mask on event input 23 1 EM24 CPU wakeup with interrupt mask on event input 24 1 EM25 CPU wakeup with interrupt mask on event input 25 1 EM26 CPU wakeup with interrupt mask on event input 26 1 EM27 CPU wakeup with interrupt mask on event input 27 1 EM28 CPU wakeup with interrupt mask on event input 28 1 EM29 CPU wakeup with interrupt mask on event input 29 1 EM30 CPU wakeup with interrupt mask on event input 30 1 EM31 CPU wakeup with interrupt mask on event input 31 1 IMR2 IMR2 EXTI CPUm wakeup with interrupt mask register 0x90 0x20 read-write 0x00000787 IM32 CPU wakeup with interrupt mask on event input 0 1 IM33 CPU wakeup with interrupt mask on event input 1 1 IM34 CPU wakeup with interrupt mask on event input 2 1 IM35 CPU wakeup with interrupt mask on event input 3 1 IM36 CPU wakeup with interrupt mask on event input 4 1 IM37 CPU wakeup with interrupt mask on event input 5 1 IM38 CPU wakeup with interrupt mask on event input 6 1 IM40 CPU wakeup with interrupt mask on event input 8 1 IM41 CPU wakeup with interrupt mask on event input 9 1 IM42 CPU wakeup with interrupt mask on event input 10 1 EMR2 EMR2 EXTI CPU wakeup with event mask register 0x94 0x20 read-write 0x00000000 EM32 CPU wakeup with interrupt mask on event input 0 1 EM33 CPU wakeup with interrupt mask on event input 1 1 EM34 CPU wakeup with interrupt mask on event input 2 1 EM35 CPU wakeup with interrupt mask on event input 3 1 EM36 CPU wakeup with interrupt mask on event input 4 1 EM37 CPU wakeup with interrupt mask on event input 5 1 EM38 CPU wakeup with interrupt mask on event input 6 1 EM40 CPU wakeup with interrupt mask on event input 8 1 EM41 CPU wakeup with interrupt mask on event input 9 1 EM42 CPU wakeup with interrupt mask on event input 10 1 SEC_EXTI !(DCB->DSCSR & (1 << 16)) 0x5002F400 FLASH Flash Flash 0x40022000 0x0 0x400 registers FLASH Flash global interrupt 006 FLASH_S Flash memory secure global interrupt 007 ACR ACR Access control register 0x0 0x20 read-write 0x00000000 LATENCY Latency 0 4 RUN_PD Flash Power-down mode during Low-power run mode 13 1 SLEEP_PD Flash Power-down mode during Low-power sleep mode 14 1 LVEN LVEN 15 1 PDKEYR PDKEYR Power down key register 0x4 0x20 write-only 0x00000000 PDKEYR RUN_PD in FLASH_ACR key 0 32 NSKEYR NSKEYR Flash non-secure key register 0x8 0x20 write-only 0x00000000 NSKEYR NSKEYR 0 32 SECKEYR SECKEYR Flash secure key register 0xC 0x20 write-only 0x00000000 SECKEYR SECKEYR 0 32 OPTKEYR OPTKEYR Flash option key register 0x10 0x20 write-only 0x00000000 OPTKEYR OPTKEYR 0 32 LVEKEYR LVEKEYR Flash low voltage key register 0x14 0x20 write-only 0x00000000 LVEKEYR LVEKEYR 0 32 NSSR NSSR Flash status register 0x20 0x20 0x00000000 NSEOP NSEOP 0 1 read-write NSOPERR NSOPERR 1 1 read-write NSPROGERR NSPROGERR 3 1 read-write NSWRPERR NSWRPERR 4 1 read-write NSPGAERR NSPGAERR 5 1 read-write NSSIZERR NSSIZERR 6 1 read-write NSPGSERR NSPGSERR 7 1 read-write OPTWERR OPTWERR 13 1 read-write OPTVERR OPTVERR 15 1 read-write NSBSY NSBusy 16 1 read-only SECSR SECSR Flash status register 0x24 0x20 0x00000000 SECEOP SECEOP 0 1 read-write SECOPERR SECOPERR 1 1 read-write SECPROGERR SECPROGERR 3 1 read-write SECWRPERR SECWRPERR 4 1 read-write SECPGAERR SECPGAERR 5 1 read-write SECSIZERR SECSIZERR 6 1 read-write SECPGSERR SECPGSERR 7 1 read-write SECRDERR Secure read protection error 14 1 read-write SECBSY SECBusy 16 1 read-only NSCR NSCR Flash non-secure control register 0x28 0x20 read-write 0xC0000000 NSPG NSPG 0 1 NSPER NSPER 1 1 NSMER1 NSMER1 2 1 NSPNB NSPNB 3 7 NSBKER NSBKER 11 1 NSMER2 NSMER2 15 1 NSSTRT Options modification start 16 1 OPTSTRT Options modification start 17 1 NSEOPIE NSEOPIE 24 1 NSERRIE NSERRIE 25 1 OBL_LAUNCH Force the option byte loading 27 1 OPTLOCK Options Lock 30 1 NSLOCK NSLOCK 31 1 SECCR SECCR Flash secure control register 0x2C 0x20 read-write 0x80000000 SECPG SECPG 0 1 SECPER SECPER 1 1 SECMER1 SECMER1 2 1 SECPNB SECPNB 3 7 SECBKER SECBKER 11 1 SECMER2 SECMER2 15 1 SECSTRT SECSTRT 16 1 SECEOPIE SECEOPIE 24 1 SECERRIE SECERRIE 25 1 SECRDERRIE SECRDERRIE 26 1 SECINV SECINV 29 1 SECLOCK SECLOCK 31 1 ECCR ECCR Flash ECC register 0x30 0x20 0x00000000 ADDR_ECC ECC fail address 0 19 read-only BK_ECC BK_ECC 21 1 read-only SYSF_ECC SYSF_ECC 22 1 read-only ECCIE ECC correction interrupt enable 24 1 read-write ECCC2 ECCC2 28 1 read-write ECCD2 ECCD2 29 1 read-write ECCC ECC correction 30 1 read-write ECCD ECC detection 31 1 read-write OPTR OPTR Flash option register 0x40 0x20 read-write 0x00000000 RDP Read protection level 0 8 BOR_LEV BOR reset Level 8 3 nRST_STOP nRST_STOP 12 1 nRST_STDBY nRST_STDBY 13 1 nRST_SHDW nRST_SHDW 14 1 IWDG_SW Independent watchdog selection 16 1 IWDG_STOP Independent watchdog counter freeze in Stop mode 17 1 IWDG_STDBY Independent watchdog counter freeze in Standby mode 18 1 WWDG_SW Window watchdog selection 19 1 SWAP_BANK SWAP_BANK 20 1 DB256K DB256K 21 1 DBANK DBANK 22 1 SRAM2_PE SRAM2 parity check enable 24 1 SRAM2_RST SRAM2 Erase when system reset 25 1 nSWBOOT0 nSWBOOT0 26 1 nBOOT0 nBOOT0 27 1 PA15_PUPEN PA15_PUPEN 28 1 TZEN TZEN 31 1 NSBOOTADD0R NSBOOTADD0R Flash non-secure boot address 0 register 0x44 0x20 write-only 0x0000000F NSBOOTADD0 NSBOOTADD0 7 25 NSBOOTADD1R NSBOOTADD1R Flash non-secure boot address 1 register 0x48 0x20 write-only 0x0000000F NSBOOTADD1 NSBOOTADD1 7 25 SECBOOTADD0R SECBOOTADD0R FFlash secure boot address 0 register 0x4C 0x20 0x00000000 BOOT_LOCK BOOT_LOCK 0 1 read-write SECBOOTADD0 SECBOOTADD0 7 25 write-only SECWM1R1 SECWM1R1 Flash bank 1 secure watermak1 register 0x50 0x20 read-write 0xFF00FF00 SECWM1_PSTRT SECWM1_PSTRT 0 7 SECWM1_PEND SECWM1_PEND 16 7 SECWM1R2 SECWM1R2 Flash secure watermak1 register 2 0x54 0x20 read-write 0x0F000F00 PCROP1_PSTRT PCROP1_PSTRT 0 7 PCROP1EN PCROP1EN 15 1 HDP1_PEND HDP1_PEND 16 7 HDP1EN HDP1EN 31 1 WRP1AR WRP1AR Flash Bank 1 WRP area A address register 0x58 0x20 read-write 0xFF00FF00 WRP1A_PSTRT WRP1A_PSTRT 0 7 WRP1A_PEND WRP1A_PEND 16 7 WRP1BR WRP1BR Flash Bank 1 WRP area B address register 0x5C 0x20 read-write 0xFF00FF00 WRP1B_PSTRT WRP1B_PSTRT 0 7 WRP1B_PEND WRP1B_PEND 16 7 SECWM2R1 SECWM2R1 Flash secure watermak2 register 0x60 0x20 read-write 0xFF00FF00 SECWM2_PSTRT SECWM2_PSTRT 0 7 SECWM2_PEND SECWM2_PEND 16 7 SECWM2R2 SECWM2R2 Flash secure watermak2 register2 0x64 0x20 read-write 0x0F000F00 PCROP2_PSTRT PCROP2_PSTRT 0 7 PCROP2EN PCROP2EN 15 1 HDP2_PEND HDP2_PEND 16 7 HDP2EN HDP2EN 31 1 WRP2AR WRP2AR Flash WPR2 area A address register 0x68 0x20 read-write 0xFF00FF00 WRP2A_PSTRT WRP2A_PSTRT 0 7 WRP2A_PEND WRP2A_PEND 16 7 WRP2BR WRP2BR Flash WPR2 area B address register 0x6C 0x20 read-write 0xFF00FF00 WRP2B_PSTRT WRP2B_PSTRT 0 7 WRP2B_PEND WRP2B_PEND 16 7 SECBB1R1 SECBB1R1 FLASH secure block based bank 1 register 0x80 0x20 read-write 0x00000000 SECBB1 SECBB1 0 32 SECBB1R2 SECBB1R2 FLASH secure block based bank 1 register 0x84 0x20 read-write 0x00000000 SECBB1 SECBB1 0 32 SECBB1R3 SECBB1R3 FLASH secure block based bank 1 register 0x88 0x20 read-write 0x00000000 SECBB1 SECBB1 0 32 SECBB1R4 SECBB1R4 FLASH secure block based bank 1 register 0x8C 0x20 read-write 0x00000000 SECBB1 SECBB1 0 32 SECBB2R1 SECBB2R1 FLASH secure block based bank 2 register 0xA0 0x20 read-write 0x00000000 SECBB2 SECBB2 0 32 SECBB2R2 SECBB2R2 FLASH secure block based bank 2 register 0xA4 0x20 read-write 0x00000000 SECBB2 SECBB2 0 32 SECBB2R3 SECBB2R3 FLASH secure block based bank 2 register 0xA8 0x20 read-write 0x00000000 SECBB2 SECBB2 0 32 SECBB2R4 SECBB2R4 FLASH secure block based bank 2 register 0xAC 0x20 read-write 0x00000000 SECBB2 SECBB2 0 32 SECHDPCR SECHDPCR FLASH secure HDP control register 0xC0 0x20 read-write 0x00000000 HDP1_ACCDIS HDP1_ACCDIS 0 1 HDP2_ACCDIS HDP2_ACCDIS 1 1 PRIVCFGR PRIVCFGR Power privilege configuration register 0xC4 0x20 read-write 0x00000000 PRIV PRIV 0 1 SEC_FLASH !(DCB->DSCSR & (1 << 16)) 0x50022000 GPIOA General-purpose I/Os GPIO 0x42020000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xABFFFFFF MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x0C000000 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x64000000 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFSEL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFSEL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFSEL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFSEL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFSEL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFSEL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFSEL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFSEL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFSEL15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFSEL14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFSEL13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFSEL12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFSEL11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFSEL10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFSEL9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFSEL8 Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR GPIO port bit reset register 0x28 0x20 write-only 0x00000000 BR0 Port x reset IO pin y 0 1 BR1 Port x reset IO pin y 1 1 BR2 Port x reset IO pin y 2 1 BR3 Port x reset IO pin y 3 1 BR4 Port x reset IO pin y 4 1 BR5 Port x reset IO pin y 5 1 BR6 Port x reset IO pin y 6 1 BR7 Port x reset IO pin y 7 1 BR8 Port x reset IO pin y 8 1 BR9 Port x reset IO pin y 9 1 BR10 Port x reset IO pin y 10 1 BR11 Port x reset IO pin y 11 1 BR12 Port x reset IO pin y 12 1 BR13 Port x reset IO pin y 13 1 BR14 Port x reset IO pin y 14 1 BR15 Port x reset IO pin y 15 1 SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 write-only 0x00000000 SEC0 I/O pin of Port x secure bit enable 0 1 SEC1 I/O pin of Port x secure bit enable 1 1 SEC2 I/O pin of Port x secure bit enable 2 1 SEC3 I/O pin of Port x secure bit enable 3 1 SEC4 I/O pin of Port x secure bit enable 4 1 SEC5 I/O pin of Port x secure bit enable 5 1 SEC6 I/O pin of Port x secure bit enable 6 1 SEC7 I/O pin of Port x secure bit enable 7 1 SEC8 I/O pin of Port x secure bit enable 8 1 SEC9 I/O pin of Port x secure bit enable 9 1 SEC10 I/O pin of Port x secure bit enable 10 1 SEC11 I/O pin of Port x secure bit enable 11 1 SEC12 I/O pin of Port x secure bit enable 12 1 SEC13 I/O pin of Port x secure bit enable 13 1 SEC14 I/O pin of Port x secure bit enable 14 1 SEC15 I/O pin of Port x secure bit enable 15 1 SEC_GPIOA !(DCB->DSCSR & (1 << 16)) 0x52020000 GPIOB General-purpose I/Os GPIO 0x42020400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFEBF MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000100 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFSEL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFSEL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFSEL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFSEL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFSEL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFSEL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFSEL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFSEL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFSEL15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFSEL14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFSEL13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFSEL12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFSEL11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFSEL10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFSEL9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFSEL8 Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR GPIO port bit reset register 0x28 0x20 write-only 0x00000000 BR0 Port x reset IO pin y 0 1 BR1 Port x reset IO pin y 1 1 BR2 Port x reset IO pin y 2 1 BR3 Port x reset IO pin y 3 1 BR4 Port x reset IO pin y 4 1 BR5 Port x reset IO pin y 5 1 BR6 Port x reset IO pin y 6 1 BR7 Port x reset IO pin y 7 1 BR8 Port x reset IO pin y 8 1 BR9 Port x reset IO pin y 9 1 BR10 Port x reset IO pin y 10 1 BR11 Port x reset IO pin y 11 1 BR12 Port x reset IO pin y 12 1 BR13 Port x reset IO pin y 13 1 BR14 Port x reset IO pin y 14 1 BR15 Port x reset IO pin y 15 1 SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 write-only 0x00000000 SEC0 I/O pin of Port x secure bit enable 0 1 SEC1 I/O pin of Port x secure bit enable 1 1 SEC2 I/O pin of Port x secure bit enable 2 1 SEC3 I/O pin of Port x secure bit enable 3 1 SEC4 I/O pin of Port x secure bit enable 4 1 SEC5 I/O pin of Port x secure bit enable 5 1 SEC6 I/O pin of Port x secure bit enable 6 1 SEC7 I/O pin of Port x secure bit enable 7 1 SEC8 I/O pin of Port x secure bit enable 8 1 SEC9 I/O pin of Port x secure bit enable 9 1 SEC10 I/O pin of Port x secure bit enable 10 1 SEC11 I/O pin of Port x secure bit enable 11 1 SEC12 I/O pin of Port x secure bit enable 12 1 SEC13 I/O pin of Port x secure bit enable 13 1 SEC14 I/O pin of Port x secure bit enable 14 1 SEC15 I/O pin of Port x secure bit enable 15 1 SEC_GPIOB !(DCB->DSCSR & (1 << 16)) 0x52020400 GPIOC General-purpose I/Os GPIO 0x42020800 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFSEL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFSEL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFSEL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFSEL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFSEL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFSEL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFSEL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFSEL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFSEL15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFSEL14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFSEL13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFSEL12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFSEL11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFSEL10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFSEL9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFSEL8 Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR GPIO port bit reset register 0x28 0x20 write-only 0x00000000 BR0 Port x reset IO pin y 0 1 BR1 Port x reset IO pin y 1 1 BR2 Port x reset IO pin y 2 1 BR3 Port x reset IO pin y 3 1 BR4 Port x reset IO pin y 4 1 BR5 Port x reset IO pin y 5 1 BR6 Port x reset IO pin y 6 1 BR7 Port x reset IO pin y 7 1 BR8 Port x reset IO pin y 8 1 BR9 Port x reset IO pin y 9 1 BR10 Port x reset IO pin y 10 1 BR11 Port x reset IO pin y 11 1 BR12 Port x reset IO pin y 12 1 BR13 Port x reset IO pin y 13 1 BR14 Port x reset IO pin y 14 1 BR15 Port x reset IO pin y 15 1 SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 write-only 0x00000000 SEC0 I/O pin of Port x secure bit enable 0 1 SEC1 I/O pin of Port x secure bit enable 1 1 SEC2 I/O pin of Port x secure bit enable 2 1 SEC3 I/O pin of Port x secure bit enable 3 1 SEC4 I/O pin of Port x secure bit enable 4 1 SEC5 I/O pin of Port x secure bit enable 5 1 SEC6 I/O pin of Port x secure bit enable 6 1 SEC7 I/O pin of Port x secure bit enable 7 1 SEC8 I/O pin of Port x secure bit enable 8 1 SEC9 I/O pin of Port x secure bit enable 9 1 SEC10 I/O pin of Port x secure bit enable 10 1 SEC11 I/O pin of Port x secure bit enable 11 1 SEC12 I/O pin of Port x secure bit enable 12 1 SEC13 I/O pin of Port x secure bit enable 13 1 SEC14 I/O pin of Port x secure bit enable 14 1 SEC15 I/O pin of Port x secure bit enable 15 1 GPIOD 0x42020C00 GPIOE 0x42021000 GPIOF 0x42021400 GPIOG 0x42021800 SEC_GPIOC !(DCB->DSCSR & (1 << 16)) 0x52020800 SEC_GPIOD !(DCB->DSCSR & (1 << 16)) 0x52020C00 SEC_GPIOE !(DCB->DSCSR & (1 << 16)) 0x52021000 SEC_GPIOF !(DCB->DSCSR & (1 << 16)) 0x52021400 SEC_GPIOG !(DCB->DSCSR & (1 << 16)) 0x52021800 GPIOH General-purpose I/Os GPIO 0x42021C00 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x0000000F MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFSEL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFSEL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFSEL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFSEL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFSEL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFSEL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFSEL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFSEL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFSEL15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFSEL14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFSEL13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFSEL12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFSEL11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFSEL10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFSEL9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFSEL8 Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR GPIO port bit reset register 0x28 0x20 write-only 0x00000000 BR0 Port x reset IO pin y 0 1 BR1 Port x reset IO pin y 1 1 BR2 Port x reset IO pin y 2 1 BR3 Port x reset IO pin y 3 1 BR4 Port x reset IO pin y 4 1 BR5 Port x reset IO pin y 5 1 BR6 Port x reset IO pin y 6 1 BR7 Port x reset IO pin y 7 1 BR8 Port x reset IO pin y 8 1 BR9 Port x reset IO pin y 9 1 BR10 Port x reset IO pin y 10 1 BR11 Port x reset IO pin y 11 1 BR12 Port x reset IO pin y 12 1 BR13 Port x reset IO pin y 13 1 BR14 Port x reset IO pin y 14 1 BR15 Port x reset IO pin y 15 1 SECCFGR SECCFGR GPIO secure configuration register 0x30 0x20 write-only 0x00000000 SEC0 I/O pin of Port x secure bit enable 0 1 SEC1 I/O pin of Port x secure bit enable 1 1 SEC2 I/O pin of Port x secure bit enable 2 1 SEC3 I/O pin of Port x secure bit enable 3 1 SEC4 I/O pin of Port x secure bit enable 4 1 SEC5 I/O pin of Port x secure bit enable 5 1 SEC6 I/O pin of Port x secure bit enable 6 1 SEC7 I/O pin of Port x secure bit enable 7 1 SEC8 I/O pin of Port x secure bit enable 8 1 SEC9 I/O pin of Port x secure bit enable 9 1 SEC10 I/O pin of Port x secure bit enable 10 1 SEC11 I/O pin of Port x secure bit enable 11 1 SEC12 I/O pin of Port x secure bit enable 12 1 SEC13 I/O pin of Port x secure bit enable 13 1 SEC14 I/O pin of Port x secure bit enable 14 1 SEC15 I/O pin of Port x secure bit enable 15 1 SEC_GPIOH !(DCB->DSCSR & (1 << 16)) 0x52021C00 TAMP Tamper and backup registers TAMP 0x40003400 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0xFFFF0000 TAMP1E TAMP1E 0 1 TAMP2E TAMP2E 1 1 TAMP3E TAMP3E 2 1 TAMP4E TAMP4E 3 1 TAMP5E TAMP5E 4 1 TAMP6E TAMP6E 5 1 TAMP7E TAMP7E 6 1 TAMP8E TAMP8E 7 1 ITAMP1E ITAMP1E 16 1 ITAMP2E ITAMP2E 17 1 ITAMP3E ITAMP3E 18 1 ITAMP5E ITAMP5E 20 1 ITAMP8E ITAMP5E 23 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 TAMP1NOER TAMP1NOER 0 1 TAMP2NOER TAMP2NOER 1 1 TAMP3NOER TAMP3NOER 2 1 TAMP4NOER TAMP4NOER 3 1 TAMP5NOER TAMP5NOER 4 1 TAMP6NOER TAMP6NOER 5 1 TAMP7NOER TAMP7NOER 6 1 TAMP8NOER TAMP8NOER 7 1 TAMP1MSK TAMP1MSK 16 1 TAMP2MSK TAMP2MSK 17 1 TAMP3MSK TAMP3MSK 18 1 BKERASE BKERASE 23 1 TAMP1TRG TAMP1TRG 24 1 TAMP2TRG TAMP2TRG 25 1 TAMP3TRG TAMP3TRG 26 1 TAMP4TRG TAMP4TRG 27 1 TAMP5TRG TAMP5TRG 28 1 TAMP6TRG TAMP6TRG 29 1 TAMP7TRG TAMP7TRG 30 1 TAMP8TRG TAMP8TRG 31 1 CR3 CR3 control register 3 0x8 0x20 read-write 0x00000000 ITAMP1NOER ITAMP1NOER 0 1 ITAMP2NOER ITAMP2NOER 1 1 ITAMP3NOER ITAMP3NOER 2 1 ITAMP5NOER ITAMP5NOER 4 1 ITAMP8NOER ITAMP8NOER 7 1 FLTCR FLTCR TAMP filter control register 0xC 0x20 read-write 0x00000000 TAMPFREQ TAMPFREQ 0 3 TAMPFLT TAMPFLT 3 2 TAMPPRCH TAMPPRCH 5 2 TAMPPUDIS TAMPPUDIS 7 1 ATCR1 ATCR1 TAMP active tamper control register 1 0x10 0x20 read-write 0x00070000 TAMP1AM TAMP1AM 0 1 TAMP2AM TAMP2AM 1 1 TAMP3AM TAMP3AM 2 1 TAMP4AM TAMP4AM 3 1 TAMP5AM TAMP5AM 4 1 TAMP6AM TAMP6AM 5 1 TAMP7AM TAMP7AM 6 1 TAMP8AM TAMP8AM 7 1 ATOSEL1 ATOSEL1 8 2 ATOSEL2 ATOSEL2 10 2 ATOSEL3 ATOSEL3 12 2 ATOSEL4 ATOSEL4 14 2 ATCKSEL ATCKSEL 16 2 ATPER ATPER 24 2 ATOSHARE ATOSHARE 30 1 FLTEN FLTEN 31 1 ATSEEDR ATSEEDR TAMP active tamper seed register 0x14 0x20 write-only 0x00000000 SEED Pseudo-random generator seed value 0 32 ATOR ATOR TAMP active tamper output register 0x18 0x20 read-only 0x00000000 PRNG Pseudo-random generator value 0 8 SEEDF Seed running flag 14 1 INITS Active tamper initialization status 15 1 ATCR2 ATCR2 TAMP active tamper control register 2 0x1C 0x20 read-write 0x00000000 ATOSEL1 ATOSEL1 8 3 ATOSEL2 ATOSEL2 11 3 ATOSEL3 ATOSEL3 14 3 ATOSEL4 ATOSEL4 17 3 ATOSEL5 ATOSEL5 20 3 ATOSEL6 ATOSEL6 23 3 ATOSEL7 ATOSEL7 26 3 ATOSEL8 ATOSEL8 29 3 SMCR SMCR TAMP secure mode register 0x20 0x20 read-write 0x00000000 BKPRWDPROT Backup registers read/write protection offset 0 8 BKPWDPROT Backup registers write protection offset 16 8 TAMPDPROT Tamper protection 31 1 PRIVCR PRIVCR TAMP privilege mode control register 0x24 0x20 read-write 0x00000000 BKPRWPRIV Backup registers zone 1 privilege protection 29 1 BKPWPRIV Backup registers zone 2 privilege protection 30 1 TAMPPRIV Tamper privilege protection 31 1 IER IER TAMP interrupt enable register 0x2C 0x20 read-write 0x00000000 TAMP1IE TAMP1IE 0 1 TAMP2IE TAMP2IE 1 1 TAMP3IE TAMP3IE 2 1 TAMP4IE TAMP4IE 3 1 TAMP5IE TAMP5IE 4 1 TAMP6IE TAMP6IE 5 1 TAMP7IE TAMP7IE 6 1 TAMP8IE TAMP8IE 7 1 ITAMP1IE ITAMP1IE 16 1 ITAMP2IE ITAMP2IE 17 1 ITAMP3IE ITAMP3IE 18 1 ITAMP5IE ITAMP5IE 20 1 ITAMP8IE ITAMP8IE 23 1 SR SR TAMP status register 0x30 0x20 read-only 0x00000000 TAMP1F TAMP1F 0 1 TAMP2F TAMP2F 1 1 TAMP3F TAMP3F 2 1 TAMP4F TAMP4F 3 1 TAMP5F TAMP5F 4 1 TAMP6F TAMP6F 5 1 TAMP7F TAMP7F 6 1 TAMP8F TAMP8F 7 1 ITAMP1F ITAMP1F 16 1 ITAMP2F ITAMP2F 17 1 ITAMP3F ITAMP3F 18 1 ITAMP5F ITAMP5F 20 1 ITAMP8F ITAMP8F 23 1 MISR MISR TAMP masked interrupt status register 0x34 0x20 read-only 0x00000000 TAMP1MF TAMP1MF: 0 1 TAMP2MF TAMP2MF 1 1 TAMP3MF TAMP3MF 2 1 TAMP4MF TAMP4MF 3 1 TAMP5MF TAMP5MF 4 1 TAMP6MF TAMP6MF 5 1 TAMP7MF TAMP7MF: 6 1 TAMP8MF TAMP8MF 7 1 ITAMP1MF ITAMP1MF 16 1 ITAMP2MF ITAMP2MF 17 1 ITAMP3MF ITAMP3MF 18 1 ITAMP5MF ITAMP5MF 20 1 ITAMP8MF ITAMP8MF 23 1 SMISR SMISR TAMP secure masked interrupt status register 0x38 0x20 read-only 0x00000000 TAMP1MF TAMP1MF: 0 1 TAMP2MF TAMP2MF 1 1 TAMP3MF TAMP3MF 2 1 TAMP4MF TAMP4MF 3 1 TAMP5MF TAMP5MF 4 1 TAMP6MF TAMP6MF 5 1 TAMP7MF TAMP7MF: 6 1 TAMP8MF TAMP8MF 7 1 ITAMP1MF ITAMP1MF 16 1 ITAMP2MF ITAMP2MF 17 1 ITAMP3MF ITAMP3MF 18 1 ITAMP5MF ITAMP5MF 20 1 ITAMP8MF ITAMP8MF 23 1 SCR SCR TAMP status clear register 0x3C 0x20 write-only 0x00000000 CTAMP1F CTAMP1F 0 1 CTAMP2F CTAMP2F 1 1 CTAMP3F CTAMP3F 2 1 CTAMP4F CTAMP4F 3 1 CTAMP5F CTAMP5F 4 1 CTAMP6F CTAMP6F 5 1 CTAMP7F CTAMP7F 6 1 CTAMP8F CTAMP8F 7 1 CITAMP1F CITAMP1F 16 1 CITAMP2F CITAMP2F 17 1 CITAMP3F CITAMP3F 18 1 CITAMP5F CITAMP5F 20 1 CITAMP8F CITAMP8F 23 1 COUNTR COUNTR TAMP monotonic counter register 0x040 0x20 read-only 0x00000000 COUNT COUNT 0 32 CFGR CFGR TAMP configuration register 0x50 0x20 read-write 0x00000000 TMONEN TMONEN 1 1 VMONEN VMONEN 2 1 WUTMONEN WUTMONEN 3 1 BKP0R BKP0R TAMP backup register 0x100 0x20 read-write 0x00000000 BKP BKP 0 32 BKP1R BKP1R TAMP backup register 0x104 0x20 read-write 0x00000000 BKP BKP 0 32 BKP2R BKP2R TAMP backup register 0x108 0x20 read-write 0x00000000 BKP BKP 0 32 BKP3R BKP3R TAMP backup register 0x10C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP4R BKP4R TAMP backup register 0x110 0x20 read-write 0x00000000 BKP BKP 0 32 BKP5R BKP5R TAMP backup register 0x114 0x20 read-write 0x00000000 BKP BKP 0 32 BKP6R BKP6R TAMP backup register 0x118 0x20 read-write 0x00000000 BKP BKP 0 32 BKP7R BKP7R TAMP backup register 0x11C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP8R BKP8R TAMP backup register 0x120 0x20 read-write 0x00000000 BKP BKP 0 32 BKP9R BKP9R TAMP backup register 0x124 0x20 read-write 0x00000000 BKP BKP 0 32 BKP10R BKP10R TAMP backup register 0x128 0x20 read-write 0x00000000 BKP BKP 0 32 BKP11R BKP11R TAMP backup register 0x12C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP12R BKP12R TAMP backup register 0x130 0x20 read-write 0x00000000 BKP BKP 0 32 BKP13R BKP13R TAMP backup register 0x134 0x20 read-write 0x00000000 BKP BKP 0 32 BKP14R BKP14R TAMP backup register 0x138 0x20 read-write 0x00000000 BKP BKP 0 32 BKP15R BKP15R TAMP backup register 0x13C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP16R BKP16R TAMP backup register 0x140 0x20 read-write 0x00000000 BKP BKP 0 32 BKP17R BKP17R TAMP backup register 0x144 0x20 read-write 0x00000000 BKP BKP 0 32 BKP18R BKP18R TAMP backup register 0x148 0x20 read-write 0x00000000 BKP BKP 0 32 BKP19R BKP19R TAMP backup register 0x14C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP20R BKP20R TAMP backup register 0x150 0x20 read-write 0x00000000 BKP BKP 0 32 BKP21R BKP21R TAMP backup register 0x154 0x20 read-write 0x00000000 BKP BKP 0 32 BKP22R BKP22R TAMP backup register 0x158 0x20 read-write 0x00000000 BKP BKP 0 32 BKP23R BKP23R TAMP backup register 0x15C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP24R BKP24R TAMP backup register 0x160 0x20 read-write 0x00000000 BKP BKP 0 32 BKP25R BKP25R TAMP backup register 0x164 0x20 read-write 0x00000000 BKP BKP 0 32 BKP26R BKP26R TAMP backup register 0x168 0x20 read-write 0x00000000 BKP BKP 0 32 BKP27R BKP27R TAMP backup register 0x16C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP28R BKP28R TAMP backup register 0x170 0x20 read-write 0x00000000 BKP BKP 0 32 BKP29R BKP29R TAMP backup register 0x174 0x20 read-write 0x00000000 BKP BKP 0 32 BKP30R BKP30R TAMP backup register 0x178 0x20 read-write 0x00000000 BKP BKP 0 32 BKP31R BKP31R TAMP backup register 0x17C 0x20 read-write 0x00000000 BKP BKP 0 32 SEC_TAMP !(DCB->DSCSR & (1 << 16)) 0x50003400 I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1 event interrupt 055 I2C1_ER I2C1 error interrupt 056 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 PE Peripheral enable 0 1 TXIE TX Interrupt enable 1 1 RXIE RX Interrupt enable 2 1 ADDRIE Address match interrupt enable (slave only) 3 1 NACKIE Not acknowledge received interrupt enable 4 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 ERRIE Error interrupts enable 7 1 DNF Digital noise filter 8 4 ANFOFF Analog noise filter OFF 12 1 TXDMAEN DMA transmission requests enable 14 1 RXDMAEN DMA reception requests enable 15 1 SBC Slave byte control 16 1 NOSTRETCH Clock stretching disable 17 1 WUPEN Wakeup from STOP enable 18 1 GCEN General call enable 19 1 SMBHEN SMBus Host address enable 20 1 SMBDEN SMBus Device Default address enable 21 1 ALERTEN SMBUS alert enable 22 1 PECEN PEC enable 23 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 PECBYTE Packet error checking byte 26 1 AUTOEND Automatic end mode (master mode) 25 1 RELOAD NBYTES reload mode 24 1 NBYTES Number of bytes 16 8 NACK NACK generation (slave mode) 15 1 STOP Stop generation (master mode) 14 1 START Start generation 13 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 ADD10 10-bit addressing mode (master mode) 11 1 RD_WRN Transfer direction (master mode) 10 1 SADD Slave address bit (master mode) 0 10 OAR1 OAR1 Own address register 1 0x8 0x20 read-write 0x00000000 OA1 Interface address 0 10 OA1MODE Own Address 1 10-bit mode 10 1 OA1EN Own Address 1 enable 15 1 OAR2 OAR2 Own address register 2 0xC 0x20 read-write 0x00000000 OA2 Interface address 1 7 OA2MSK Own Address 2 masks 8 3 OA2EN Own Address 2 enable 15 1 TIMINGR TIMINGR Timing register 0x10 0x20 read-write 0x00000000 SCLL SCL low period (master mode) 0 8 SCLH SCL high period (master mode) 8 8 SDADEL Data hold time 16 4 SCLDEL Data setup time 20 4 PRESC Timing prescaler 28 4 TIMEOUTR TIMEOUTR Status register 1 0x14 0x20 read-write 0x00000000 TIMEOUTA Bus timeout A 0 12 TIDLE Idle clock timeout detection 12 1 TIMOUTEN Clock timeout enable 15 1 TIMEOUTB Bus timeout B 16 12 TEXTEN Extended clock timeout enable 31 1 ISR ISR Interrupt and Status register 0x18 0x20 0x00000001 ADDCODE Address match code (Slave mode) 17 7 read-only DIR Transfer direction (Slave mode) 16 1 read-only BUSY Bus busy 15 1 read-only ALERT SMBus alert 13 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only PECERR PEC Error in reception 11 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only TCR Transfer Complete Reload 7 1 read-only TC Transfer Complete (master mode) 6 1 read-only STOPF Stop detection flag 5 1 read-only NACKF Not acknowledge received flag 4 1 read-only ADDR Address matched (slave mode) 3 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only TXIS Transmit interrupt status (transmitters) 1 1 read-write TXE Transmit data register empty (transmitters) 0 1 read-write ICR ICR Interrupt clear register 0x1C 0x20 write-only 0x00000000 ALERTCF Alert flag clear 13 1 TIMOUTCF Timeout detection flag clear 12 1 PECCF PEC Error flag clear 11 1 OVRCF Overrun/Underrun flag clear 10 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 STOPCF Stop detection flag clear 5 1 NACKCF Not Acknowledge flag clear 4 1 ADDRCF Address Matched flag clear 3 1 PECR PECR PEC register 0x20 0x20 read-only 0x00000000 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 0x20 read-only 0x00000000 RXDATA 8-bit receive data 0 8 TXDR TXDR Transmit data register 0x28 0x20 read-write 0x00000000 TXDATA 8-bit transmit data 0 8 I2C2 0x40005800 I2C2_EV I2C2 event interrupt 057 I2C2_ER I2C2 error interrupt 058 I2C3 0x40005C00 I2C3_EV I2C3 event interrupt 088 I2C3_ER I2C3 error interrupt 089 I2C4 0x40008400 I2C4_ER I2C4 error interrupt 100 I2C4_EV I2C4 event interrupt 101 SEC_I2C1 !(DCB->DSCSR & (1 << 16)) 0x50005400 SEC_I2C2 !(DCB->DSCSR & (1 << 16)) 0x50005800 SEC_I2C3 !(DCB->DSCSR & (1 << 16)) 0x50005C00 SEC_I2C4 !(DCB->DSCSR & (1 << 16)) 0x50008400 ICache ICache ICache 0x40030400 0x0 0x400 registers ICACHE ICACHE 107 ICACHE_CR ICACHE_CR ICACHE control register 0x0 0x20 read-write 0x00000004 EN EN 0 1 CACHEINV CACHEINV 1 1 WAYSEL WAYSEL 2 1 HITMEN HITMEN 16 1 MISSMEN MISSMEN 17 1 HITMRST HITMRST 18 1 MISSMRST MISSMRST 19 1 ICACHE_SR ICACHE_SR ICACHE status register 0x4 0x20 read-only 0x00000001 BUSYF BUSYF 0 1 BSYENDF BSYENDF 1 1 ERRF ERRF 2 1 ICACHE_IER ICACHE_IER ICACHE interrupt enable register 0x8 0x20 read-write 0x00000000 BSYENDIE BSYENDIE 1 1 ERRIE ERRIE 2 1 ICACHE_FCR ICACHE_FCR ICACHE flag clear register 0xC 0x20 write-only 0x00000000 CBSYENDF CBSYENDF 1 1 CERRF CERRF 2 1 ICACHE_HMONR ICACHE_HMONR ICACHE hit monitor register 0x10 0x20 read-only 0x00000000 HITMON HITMON 0 32 ICACHE_MMONR ICACHE_MMONR ICACHE miss monitor register 0x14 0x20 read-only 0x00000000 MISSMON MISSMON 0 16 ICACHE_CRR0 ICACHE_CRR0 ICACHE region configuration register 0x20 0x20 read-write 0x00000200 BASEADDR BASEADDR 0 8 RSIZE RSIZE 9 3 REN REN 15 1 REMAPADDR REMAPADDR 16 11 MSTSEL MSTSEL 28 1 HBURST HBURST 31 1 ICACHE_CRR1 ICACHE_CRR1 ICACHE region configuration register 0x24 0x20 read-write 0x00000200 BASEADDR BASEADDR 0 8 RSIZE RSIZE 9 3 REN REN 15 1 REMAPADDR REMAPADDR 16 11 MSTSEL MSTSEL 28 1 HBURST HBURST 31 1 ICACHE_CRR2 ICACHE_CRR2 ICACHE region configuration register 0x28 0x20 read-write 0x00000200 BASEADDR BASEADDR 0 8 RSIZE RSIZE 9 3 REN REN 15 1 REMAPADDR REMAPADDR 16 11 MSTSEL MSTSEL 28 1 HBURST HBURST 31 1 ICACHE_CRR3 ICACHE_CRR3 ICACHE region configuration register 0x2C 0x20 read-write 0x00000200 BASEADDR BASEADDR 0 8 RSIZE RSIZE 9 3 REN REN 15 1 REMAPADDR REMAPADDR 16 11 MSTSEL MSTSEL 28 1 HBURST HBURST 31 1 SEC_ICache !(DCB->DSCSR & (1 << 16)) 0x50030400 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register 0x0 0x20 write-only 0x00000000 KEY Key value (write only, read 0x0000) 0 16 PR PR Prescaler register 0x4 0x20 read-write 0x00000000 PR Prescaler divider 0 3 RLR RLR Reload register 0x8 0x20 read-write 0x00000FFF RL Watchdog counter reload value 0 12 SR SR Status register 0xC 0x20 read-only 0x00000000 WVU Watchdog counter window value update 2 1 RVU Watchdog counter reload value update 1 1 PVU Watchdog prescaler value update 0 1 WINR WINR Window register 0x10 0x20 read-write 0x00000FFF WIN Watchdog counter window value 0 12 SEC_IWDG !(DCB->DSCSR & (1 << 16)) 0x50003000 LPTIM1 Low power timer LPTIM 0x40007C00 0x0 0x400 registers LPTIM1 LP TIM1 interrupt 067 LPTIM2 LP TIM2 interrupt 068 ISR ISR Interrupt and Status Register 0x0 0x20 read-only 0x00000000 DOWN Counter direction change up to down 6 1 UP Counter direction change down to up 5 1 ARROK Autoreload register update OK 4 1 CMPOK Compare register update OK 3 1 EXTTRIG External trigger edge event 2 1 ARRM Autoreload match 1 1 CMPM Compare match 0 1 UE LPTIM update event occurred 7 1 REPOK Repetition register update Ok 8 1 ICR ICR Interrupt Clear Register 0x4 0x20 write-only 0x00000000 DOWNCF Direction change to down Clear Flag 6 1 UPCF Direction change to UP Clear Flag 5 1 ARROKCF Autoreload register update OK Clear Flag 4 1 CMPOKCF Compare register update OK Clear Flag 3 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 ARRMCF Autoreload match Clear Flag 1 1 CMPMCF compare match Clear Flag 0 1 UECF Update event clear flag 7 1 REPOKCF Repetition register update OK clear flag 8 1 IER IER Interrupt Enable Register 0x8 0x20 read-write 0x00000000 DOWNIE Direction change to down Interrupt Enable 6 1 UPIE Direction change to UP Interrupt Enable 5 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 CMPOKIE Compare register update OK Interrupt Enable 3 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 ARRMIE Autoreload match Interrupt Enable 1 1 CMPMIE Compare match Interrupt Enable 0 1 UEIE Update event interrupt enable 7 1 REPOKIE REPOKIE 8 1 CFGR CFGR Configuration Register 0xC 0x20 read-write 0x00000000 ENC Encoder mode enable 24 1 COUNTMODE counter mode enabled 23 1 PRELOAD Registers update mode 22 1 WAVPOL Waveform shape polarity 21 1 WAVE Waveform shape 20 1 TIMOUT Timeout enable 19 1 TRIGEN Trigger enable and polarity 17 2 TRIGSEL Trigger selector 13 3 PRESC Clock prescaler 9 3 TRGFLT Configurable digital filter for trigger 6 2 CKFLT Configurable digital filter for external clock 3 2 CKPOL Clock Polarity 1 2 CKSEL Clock selector 0 1 CR CR Control Register 0x10 0x20 read-write 0x00000000 CNTSTRT Timer start in continuous mode 2 1 SNGSTRT LPTIM start in single mode 1 1 ENABLE LPTIM Enable 0 1 COUNTRST Counter reset 4 1 RSTARE Reset after read enable 3 1 CMP CMP Compare Register 0x14 0x20 read-write 0x00000000 CMP Compare value 0 16 ARR ARR Autoreload Register 0x18 0x20 read-write 0x00000001 ARR Auto reload value 0 16 CNT CNT Counter Register 0x1C 0x20 read-only 0x00000000 CNT Counter value 0 16 OR OR LPTIM option register 0x20 0x20 read-write 0x00000000 OR_0 Option register bit 0 0 1 OR_1 Option register bit 1 1 1 RCR RCR LPTIM repetition register 0x28 0x20 read-write 0x00000000 REP Repetition register value 0 8 LPTIM2 0x40009400 LPTIM3 0x40009800 LPTIM3 LPTIM3 098 SEC_LPTIM1 !(DCB->DSCSR & (1 << 16)) 0x50007C00 SEC_LPTIM2 !(DCB->DSCSR & (1 << 16)) 0x50009400 SEC_LPTIM3 !(DCB->DSCSR & (1 << 16)) 0x50009800 GTZC_MPCBB1 GTZC_MPCBB1 GTZC 0x40032C00 0x0 0x400 registers MPCBB1_CR MPCBB1_CR MPCBB control register 0x0 0x20 read-write 0x00000000 LCK LCK 0 1 INVSECSTATE INVSECSTATE 30 1 SRWILADIS SRWILADIS 31 1 MPCBB1_LCKVTR1 MPCBB1_LCKVTR1 MPCBB control register 0x10 0x20 read-write 0x00000000 LCKSB0 LCKSB0 0 1 LCKSB1 LCKSB1 1 1 LCKSB2 LCKSB2 2 1 LCKSB3 LCKSB3 3 1 LCKSB4 LCKSB4 4 1 LCKSB5 LCKSB5 5 1 LCKSB6 LCKSB6 6 1 LCKSB7 LCKSB7 7 1 LCKSB8 LCKSB8 8 1 LCKSB9 LCKSB9 9 1 LCKSB10 LCKSB10 10 1 LCKSB11 LCKSB11 11 1 LCKSB12 LCKSB12 12 1 LCKSB13 LCKSB13 13 1 LCKSB14 LCKSB14 14 1 LCKSB15 LCKSB15 15 1 LCKSB16 LCKSB16 16 1 LCKSB17 LCKSB17 17 1 LCKSB18 LCKSB18 18 1 LCKSB19 LCKSB19 19 1 LCKSB20 LCKSB20 20 1 LCKSB21 LCKSB21 21 1 LCKSB22 LCKSB22 22 1 LCKSB23 LCKSB23 23 1 LCKSB24 LCKSB24 24 1 LCKSB25 LCKSB25 25 1 LCKSB26 LCKSB26 26 1 LCKSB27 LCKSB27 27 1 LCKSB28 LCKSB28 28 1 LCKSB29 LCKSB29 29 1 LCKSB30 LCKSB30 30 1 LCKSB31 LCKSB31 31 1 MPCBB1_LCKVTR2 MPCBB1_LCKVTR2 MPCBB control register 0x14 0x20 read-write 0x00000000 LCKSB32 LCKSB32 0 1 LCKSB33 LCKSB33 1 1 LCKSB34 LCKSB34 2 1 LCKSB35 LCKSB35 3 1 LCKSB36 LCKSB36 4 1 LCKSB37 LCKSB37 5 1 LCKSB38 LCKSB38 6 1 LCKSB39 LCKSB39 7 1 LCKSB40 LCKSB40 8 1 LCKSB41 LCKSB41 9 1 LCKSB42 LCKSB42 10 1 LCKSB43 LCKSB43 11 1 LCKSB44 LCKSB44 12 1 LCKSB45 LCKSB45 13 1 LCKSB46 LCKSB46 14 1 LCKSB47 LCKSB47 15 1 LCKSB48 LCKSB48 16 1 LCKSB49 LCKSB49 17 1 LCKSB50 LCKSB50 18 1 LCKSB51 LCKSB51 19 1 LCKSB52 LCKSB52 20 1 LCKSB53 LCKSB53 21 1 LCKSB54 LCKSB54 22 1 LCKSB55 LCKSB55 23 1 LCKSB56 LCKSB56 24 1 LCKSB57 LCKSB57 25 1 LCKSB58 LCKSB58 26 1 LCKSB59 LCKSB59 27 1 LCKSB60 LCKSB60 28 1 LCKSB61 LCKSB61 29 1 LCKSB62 LCKSB62 30 1 LCKSB63 LCKSB63 31 1 MPCBB1_VCTR0 MPCBB1_VCTR0 MPCBBx vector register 0x100 0x20 read-write 0xFFFFFFFF B0 B0 0 1 B1 B1 1 1 B2 B2 2 1 B3 B3 3 1 B4 B4 4 1 B5 B5 5 1 B6 B6 6 1 B7 B7 7 1 B8 B8 8 1 B9 B9 9 1 B10 B10 10 1 B11 B11 11 1 B12 B12 12 1 B13 B13 13 1 B14 B14 14 1 B15 B15 15 1 B16 B16 16 1 B17 B17 17 1 B18 B18 18 1 B19 B19 19 1 B20 B20 20 1 B21 B21 21 1 B22 B22 22 1 B23 B23 23 1 B24 B24 24 1 B25 B25 25 1 B26 B26 26 1 B27 B27 27 1 B28 B28 28 1 B29 B29 29 1 B30 B30 30 1 B31 B31 31 1 MPCBB1_VCTR1 MPCBB1_VCTR1 MPCBBx vector register 0x104 0x20 read-write 0xFFFFFFFF B32 B32 0 1 B33 B33 1 1 B34 B34 2 1 B35 B35 3 1 B36 B36 4 1 B37 B37 5 1 B38 B38 6 1 B39 B39 7 1 B40 B40 8 1 B41 B41 9 1 B42 B42 10 1 B43 B43 11 1 B44 B44 12 1 B45 B45 13 1 B46 B46 14 1 B47 B47 15 1 B48 B48 16 1 B49 B49 17 1 B50 B50 18 1 B51 B51 19 1 B52 B52 20 1 B53 B53 21 1 B54 B54 22 1 B55 B55 23 1 B56 B56 24 1 B57 B57 25 1 B58 B58 26 1 B59 B59 27 1 B60 B60 28 1 B61 B61 29 1 B62 B62 30 1 B63 B63 31 1 MPCBB1_VCTR2 MPCBB1_VCTR2 MPCBBx vector register 0x108 0x20 read-write 0xFFFFFFFF B64 B64 0 1 B65 B65 1 1 B66 B66 2 1 B67 B67 3 1 B68 B68 4 1 B69 B69 5 1 B70 B70 6 1 B71 B71 7 1 B72 B72 8 1 B73 B73 9 1 B74 B74 10 1 B75 B75 11 1 B76 B76 12 1 B77 B77 13 1 B78 B78 14 1 B79 B79 15 1 B80 B80 16 1 B81 B81 17 1 B82 B82 18 1 B83 B83 19 1 B84 B84 20 1 B85 B85 21 1 B86 B86 22 1 B87 B87 23 1 B88 B88 24 1 B89 B89 25 1 B90 B90 26 1 B91 B91 27 1 B92 B92 28 1 B93 B93 29 1 B94 B94 30 1 B95 B95 31 1 MPCBB1_VCTR3 MPCBB1_VCTR3 MPCBBx vector register 0x10C 0x20 read-write 0xFFFFFFFF B96 B96 0 1 B97 B97 1 1 B98 B98 2 1 B99 B99 3 1 B100 B100 4 1 B101 B101 5 1 B102 B102 6 1 B103 B103 7 1 B104 B104 8 1 B105 B105 9 1 B106 B106 10 1 B107 B107 11 1 B108 B108 12 1 B109 B109 13 1 B110 B110 14 1 B111 B111 15 1 B112 B112 16 1 B113 B113 17 1 B114 B114 18 1 B115 B115 19 1 B116 B116 20 1 B117 B117 21 1 B118 B118 22 1 B119 B119 23 1 B120 B120 24 1 B121 B121 25 1 B122 B122 26 1 B123 B123 27 1 B124 B124 28 1 B125 B125 29 1 B126 B126 30 1 B127 B127 31 1 MPCBB1_VCTR4 MPCBB1_VCTR4 MPCBBx vector register 0x110 0x20 read-write 0xFFFFFFFF B128 B128 0 1 B129 B129 1 1 B130 B130 2 1 B131 B131 3 1 B132 B132 4 1 B133 B133 5 1 B134 B134 6 1 B135 B135 7 1 B136 B136 8 1 B137 B137 9 1 B138 B138 10 1 B139 B139 11 1 B140 B140 12 1 B141 B141 13 1 B142 B142 14 1 B143 B143 15 1 B144 B144 16 1 B145 B145 17 1 B146 B146 18 1 B147 B147 19 1 B148 B148 20 1 B149 B149 21 1 B150 B150 22 1 B151 B151 23 1 B152 B152 24 1 B153 B153 25 1 B154 B154 26 1 B155 B155 27 1 B156 B156 28 1 B157 B157 29 1 B158 B158 30 1 B159 B159 31 1 MPCBB1_VCTR5 MPCBB1_VCTR5 MPCBBx vector register 0x114 0x20 read-write 0xFFFFFFFF B160 B160 0 1 B161 B161 1 1 B162 B162 2 1 B163 B163 3 1 B164 B164 4 1 B165 B165 5 1 B166 B166 6 1 B167 B167 7 1 B168 B168 8 1 B169 B169 9 1 B170 B170 10 1 B171 B171 11 1 B172 B172 12 1 B173 B173 13 1 B174 B174 14 1 B175 B175 15 1 B176 B176 16 1 B177 B177 17 1 B178 B178 18 1 B179 B179 19 1 B180 B180 20 1 B181 B181 21 1 B182 B182 22 1 B183 B183 23 1 B184 B184 24 1 B185 B185 25 1 B186 B186 26 1 B187 B187 27 1 B188 B188 28 1 B189 B189 29 1 B190 B190 30 1 B191 B191 31 1 MPCBB1_VCTR6 MPCBB1_VCTR6 MPCBBx vector register 0x118 0x20 read-write 0xFFFFFFFF B192 B192 0 1 B193 B193 1 1 B194 B194 2 1 B195 B195 3 1 B196 B196 4 1 B197 B197 5 1 B198 B198 6 1 B199 B199 7 1 B200 B200 8 1 B201 B201 9 1 B202 B202 10 1 B203 B203 11 1 B204 B204 12 1 B205 B205 13 1 B206 B206 14 1 B207 B207 15 1 B208 B208 16 1 B209 B209 17 1 B210 B210 18 1 B211 B211 19 1 B212 B212 20 1 B213 B213 21 1 B214 B214 22 1 B215 B215 23 1 B216 B216 24 1 B217 B217 25 1 B218 B218 26 1 B219 B219 27 1 B220 B220 28 1 B221 B221 29 1 B222 B222 30 1 B223 B223 31 1 MPCBB1_VCTR7 MPCBB1_VCTR7 MPCBBx vector register 0x11C 0x20 read-write 0xFFFFFFFF B224 B224 0 1 B225 B225 1 1 B226 B226 2 1 B227 B227 3 1 B228 B228 4 1 B229 B229 5 1 B230 B230 6 1 B231 B231 7 1 B232 B232 8 1 B233 B233 9 1 B234 B234 10 1 B235 B235 11 1 B236 B236 12 1 B237 B237 13 1 B238 B238 14 1 B239 B239 15 1 B240 B240 16 1 B241 B241 17 1 B242 B242 18 1 B243 B243 19 1 B244 B244 20 1 B245 B245 21 1 B246 B246 22 1 B247 B247 23 1 B248 B248 24 1 B249 B249 25 1 B250 B250 26 1 B251 B251 27 1 B252 B252 28 1 B253 B253 29 1 B254 B254 30 1 B255 B255 31 1 MPCBB1_VCTR8 MPCBB1_VCTR8 MPCBBx vector register 0x120 0x20 read-write 0xFFFFFFFF B256 B256 0 1 B257 B257 1 1 B258 B258 2 1 B259 B259 3 1 B260 B260 4 1 B261 B261 5 1 B262 B262 6 1 B263 B263 7 1 B264 B264 8 1 B265 B265 9 1 B266 B266 10 1 B267 B267 11 1 B268 B268 12 1 B269 B269 13 1 B270 B270 14 1 B271 B271 15 1 B272 B272 16 1 B273 B273 17 1 B274 B274 18 1 B275 B275 19 1 B276 B276 20 1 B277 B277 21 1 B278 B278 22 1 B279 B279 23 1 B280 B280 24 1 B281 B281 25 1 B282 B282 26 1 B283 B283 27 1 B284 B284 28 1 B285 B285 29 1 B286 B286 30 1 B287 B287 31 1 MPCBB1_VCTR9 MPCBB1_VCTR9 MPCBBx vector register 0x124 0x20 read-write 0xFFFFFFFF B288 B288 0 1 B289 B289 1 1 B290 B290 2 1 B291 B291 3 1 B292 B292 4 1 B293 B293 5 1 B294 B294 6 1 B295 B295 7 1 B296 B296 8 1 B297 B297 9 1 B298 B298 10 1 B299 B299 11 1 B300 B300 12 1 B301 B301 13 1 B302 B302 14 1 B303 B303 15 1 B304 B304 16 1 B305 B305 17 1 B306 B306 18 1 B307 B307 19 1 B308 B308 20 1 B309 B309 21 1 B310 B310 22 1 B311 B311 23 1 B312 B312 24 1 B313 B313 25 1 B314 B314 26 1 B315 B315 27 1 B316 B316 28 1 B317 B317 29 1 B318 B318 30 1 B319 B319 31 1 MPCBB1_VCTR10 MPCBB1_VCTR10 MPCBBx vector register 0x128 0x20 read-write 0xFFFFFFFF B320 B320 0 1 B321 B321 1 1 B322 B322 2 1 B323 B323 3 1 B324 B324 4 1 B325 B325 5 1 B326 B326 6 1 B327 B327 7 1 B328 B328 8 1 B329 B329 9 1 B330 B330 10 1 B331 B331 11 1 B332 B332 12 1 B333 B333 13 1 B334 B334 14 1 B335 B335 15 1 B336 B336 16 1 B337 B337 17 1 B338 B338 18 1 B339 B339 19 1 B340 B340 20 1 B341 B341 21 1 B342 B342 22 1 B343 B343 23 1 B344 B344 24 1 B345 B345 25 1 B346 B346 26 1 B347 B347 27 1 B348 B348 28 1 B349 B349 29 1 B350 B350 30 1 B351 B351 31 1 MPCBB1_VCTR11 MPCBB1_VCTR11 MPCBBx vector register 0x12C 0x20 read-write 0xFFFFFFFF B352 B352 0 1 B353 B353 1 1 B354 B354 2 1 B355 B355 3 1 B356 B356 4 1 B357 B357 5 1 B358 B358 6 1 B359 B359 7 1 B360 B360 8 1 B361 B361 9 1 B362 B362 10 1 B363 B363 11 1 B364 B364 12 1 B365 B365 13 1 B366 B366 14 1 B367 B367 15 1 B368 B368 16 1 B369 B369 17 1 B370 B370 18 1 B371 B371 19 1 B372 B372 20 1 B373 B373 21 1 B374 B374 22 1 B375 B375 23 1 B376 B376 24 1 B377 B377 25 1 B378 B378 26 1 B379 B379 27 1 B380 B380 28 1 B381 B381 29 1 B382 B382 30 1 B383 B383 31 1 MPCBB1_VCTR12 MPCBB1_VCTR12 MPCBBx vector register 0x130 0x20 read-write 0xFFFFFFFF B384 B384 0 1 B385 B385 1 1 B386 B386 2 1 B387 B387 3 1 B388 B388 4 1 B389 B389 5 1 B390 B390 6 1 B391 B391 7 1 B392 B392 8 1 B393 B393 9 1 B394 B394 10 1 B395 B395 11 1 B396 B396 12 1 B397 B397 13 1 B398 B398 14 1 B399 B399 15 1 B400 B400 16 1 B401 B401 17 1 B402 B402 18 1 B403 B403 19 1 B404 B404 20 1 B405 B405 21 1 B406 B406 22 1 B407 B407 23 1 B408 B408 24 1 B409 B409 25 1 B410 B410 26 1 B411 B411 27 1 B412 B412 28 1 B413 B413 29 1 B414 B414 30 1 B415 B415 31 1 MPCBB1_VCTR13 MPCBB1_VCTR13 MPCBBx vector register 0x134 0x20 read-write 0xFFFFFFFF B416 B416 0 1 B417 B417 1 1 B418 B418 2 1 B419 B419 3 1 B420 B420 4 1 B421 B421 5 1 B422 B422 6 1 B423 B423 7 1 B424 B424 8 1 B425 B425 9 1 B426 B426 10 1 B427 B427 11 1 B428 B428 12 1 B429 B429 13 1 B430 B430 14 1 B431 B431 15 1 B432 B432 16 1 B433 B433 17 1 B434 B434 18 1 B435 B435 19 1 B436 B436 20 1 B437 B437 21 1 B438 B438 22 1 B439 B439 23 1 B440 B440 24 1 B441 B441 25 1 B442 B442 26 1 B443 B443 27 1 B444 B444 28 1 B445 B445 29 1 B446 B446 30 1 B447 B447 31 1 MPCBB1_VCTR14 MPCBB1_VCTR14 MPCBBx vector register 0x138 0x20 read-write 0xFFFFFFFF B448 B448 0 1 B449 B449 1 1 B450 B450 2 1 B451 B451 3 1 B452 B452 4 1 B453 B453 5 1 B454 B454 6 1 B455 B455 7 1 B456 B456 8 1 B457 B457 9 1 B458 B458 10 1 B459 B459 11 1 B460 B460 12 1 B461 B461 13 1 B462 B462 14 1 B463 B463 15 1 B464 B464 16 1 B465 B465 17 1 B466 B466 18 1 B467 B467 19 1 B468 B468 20 1 B469 B469 21 1 B470 B470 22 1 B471 B471 23 1 B472 B472 24 1 B473 B473 25 1 B474 B474 26 1 B475 B475 27 1 B476 B476 28 1 B477 B477 29 1 B478 B478 30 1 B479 B479 31 1 MPCBB1_VCTR15 MPCBB1_VCTR15 MPCBBx vector register 0x13C 0x20 read-write 0xFFFFFFFF B480 B480 0 1 B481 B481 1 1 B482 B482 2 1 B483 B483 3 1 B484 B484 4 1 B485 B485 5 1 B486 B486 6 1 B487 B487 7 1 B488 B488 8 1 B489 B489 9 1 B490 B490 10 1 B491 B491 11 1 B492 B492 12 1 B493 B493 13 1 B494 B494 14 1 B495 B495 15 1 B496 B496 16 1 B497 B497 17 1 B498 B498 18 1 B499 B499 19 1 B500 B500 20 1 B501 B501 21 1 B502 B502 22 1 B503 B503 23 1 B504 B504 24 1 B505 B505 25 1 B506 B506 26 1 B507 B507 27 1 B508 B508 28 1 B509 B509 29 1 B510 B510 30 1 B511 B511 31 1 MPCBB1_VCTR16 MPCBB1_VCTR16 MPCBBx vector register 0x140 0x20 read-write 0xFFFFFFFF B512 B512 0 1 B513 B513 1 1 B514 B514 2 1 B515 B515 3 1 B516 B516 4 1 B517 B517 5 1 B518 B518 6 1 B519 B519 7 1 B520 B520 8 1 B521 B521 9 1 B522 B522 10 1 B523 B523 11 1 B524 B524 12 1 B525 B525 13 1 B526 B526 14 1 B527 B527 15 1 B528 B528 16 1 B529 B529 17 1 B530 B530 18 1 B531 B531 19 1 B532 B532 20 1 B533 B533 21 1 B534 B534 22 1 B535 B535 23 1 B536 B536 24 1 B537 B537 25 1 B538 B538 26 1 B539 B539 27 1 B540 B540 28 1 B541 B541 29 1 B542 B542 30 1 B543 B543 31 1 MPCBB1_VCTR17 MPCBB1_VCTR17 MPCBBx vector register 0x144 0x20 read-write 0xFFFFFFFF B544 B544 0 1 B545 B545 1 1 B546 B546 2 1 B547 B547 3 1 B548 B548 4 1 B549 B549 5 1 B550 B550 6 1 B551 B551 7 1 B552 B552 8 1 B553 B553 9 1 B554 B554 10 1 B555 B555 11 1 B556 B556 12 1 B557 B557 13 1 B558 B558 14 1 B559 B559 15 1 B560 B560 16 1 B561 B561 17 1 B562 B562 18 1 B563 B563 19 1 B564 B564 20 1 B565 B565 21 1 B566 B566 22 1 B567 B567 23 1 B568 B568 24 1 B569 B569 25 1 B570 B570 26 1 B571 B571 27 1 B572 B572 28 1 B573 B573 29 1 B574 B574 30 1 B575 B575 31 1 MPCBB1_VCTR18 MPCBB1_VCTR18 MPCBBx vector register 0x148 0x20 read-write 0xFFFFFFFF B576 B576 0 1 B577 B577 1 1 B578 B578 2 1 B579 B579 3 1 B580 B580 4 1 B581 B581 5 1 B582 B582 6 1 B583 B583 7 1 B584 B584 8 1 B585 B585 9 1 B586 B586 10 1 B587 B587 11 1 B588 B588 12 1 B589 B589 13 1 B590 B590 14 1 B591 B591 15 1 B592 B592 16 1 B593 B593 17 1 B594 B594 18 1 B595 B595 19 1 B596 B596 20 1 B597 B597 21 1 B598 B598 22 1 B599 B599 23 1 B600 B600 24 1 B601 B601 25 1 B602 B602 26 1 B603 B603 27 1 B604 B604 28 1 B605 B605 29 1 B606 B606 30 1 B607 B607 31 1 MPCBB1_VCTR19 MPCBB1_VCTR19 MPCBBx vector register 0x14C 0x20 read-write 0xFFFFFFFF B608 B608 0 1 B609 B609 1 1 B610 B610 2 1 B611 B611 3 1 B612 B612 4 1 B613 B613 5 1 B614 B614 6 1 B615 B615 7 1 B616 B616 8 1 B617 B617 9 1 B618 B618 10 1 B619 B619 11 1 B620 B620 12 1 B621 B621 13 1 B622 B622 14 1 B623 B623 15 1 B624 B624 16 1 B625 B625 17 1 B626 B626 18 1 B627 B627 19 1 B628 B628 20 1 B629 B629 21 1 B630 B630 22 1 B631 B631 23 1 B632 B632 24 1 B633 B633 25 1 B634 B634 26 1 B635 B635 27 1 B636 B636 28 1 B637 B637 29 1 B638 B638 30 1 B639 B639 31 1 MPCBB1_VCTR20 MPCBB1_VCTR20 MPCBBx vector register 0x150 0x20 read-write 0xFFFFFFFF B640 B640 0 1 B641 B641 1 1 B642 B642 2 1 B643 B643 3 1 B644 B644 4 1 B645 B645 5 1 B646 B646 6 1 B647 B647 7 1 B648 B648 8 1 B649 B649 9 1 B650 B650 10 1 B651 B651 11 1 B652 B652 12 1 B653 B653 13 1 B654 B654 14 1 B655 B655 15 1 B656 B656 16 1 B657 B657 17 1 B658 B658 18 1 B659 B659 19 1 B660 B660 20 1 B661 B661 21 1 B662 B662 22 1 B663 B663 23 1 B664 B664 24 1 B665 B665 25 1 B666 B666 26 1 B667 B667 27 1 B668 B668 28 1 B669 B669 29 1 B670 B670 30 1 B671 B671 31 1 MPCBB1_VCTR21 MPCBB1_VCTR21 MPCBBx vector register 0x154 0x20 read-write 0xFFFFFFFF B672 B672 0 1 B673 B673 1 1 B674 B674 2 1 B675 B675 3 1 B676 B676 4 1 B677 B677 5 1 B678 B678 6 1 B679 B679 7 1 B680 B680 8 1 B681 B681 9 1 B682 B682 10 1 B683 B683 11 1 B684 B684 12 1 B685 B685 13 1 B686 B686 14 1 B687 B687 15 1 B688 B688 16 1 B689 B689 17 1 B690 B690 18 1 B691 B691 19 1 B692 B692 20 1 B693 B693 21 1 B694 B694 22 1 B695 B695 23 1 B696 B696 24 1 B697 B697 25 1 B698 B698 26 1 B699 B699 27 1 B700 B700 28 1 B701 B701 29 1 B702 B702 30 1 B703 B703 31 1 MPCBB1_VCTR22 MPCBB1_VCTR22 MPCBBx vector register 0x158 0x20 read-write 0xFFFFFFFF B704 B704 0 1 B705 B705 1 1 B706 B706 2 1 B707 B707 3 1 B708 B708 4 1 B709 B709 5 1 B710 B710 6 1 B711 B711 7 1 B712 B712 8 1 B713 B713 9 1 B714 B714 10 1 B715 B715 11 1 B716 B716 12 1 B717 B717 13 1 B718 B718 14 1 B719 B719 15 1 B720 B720 16 1 B721 B721 17 1 B722 B722 18 1 B723 B723 19 1 B724 B724 20 1 B725 B725 21 1 B726 B726 22 1 B727 B727 23 1 B728 B728 24 1 B729 B729 25 1 B730 B730 26 1 B731 B731 27 1 B732 B732 28 1 B733 B733 29 1 B734 B734 30 1 B735 B735 31 1 MPCBB1_VCTR23 MPCBB1_VCTR23 MPCBBx vector register 0x15C 0x20 read-write 0xFFFFFFFF B736 B736 0 1 B737 B737 1 1 B738 B738 2 1 B739 B739 3 1 B740 B740 4 1 B741 B741 5 1 B742 B742 6 1 B743 B743 7 1 B744 B744 8 1 B745 B745 9 1 B746 B746 10 1 B747 B747 11 1 B748 B748 12 1 B749 B749 13 1 B750 B750 14 1 B751 B751 15 1 B752 B752 16 1 B753 B753 17 1 B754 B754 18 1 B755 B755 19 1 B756 B756 20 1 B757 B757 21 1 B758 B758 22 1 B759 B759 23 1 B760 B760 24 1 B761 B761 25 1 B762 B762 26 1 B763 B763 27 1 B764 B764 28 1 B765 B765 29 1 B766 B766 30 1 B767 B767 31 1 MPCBB1_VCTR24 MPCBB1_VCTR24 MPCBBx vector register 0x160 0x20 read-write 0xFFFFFFFF B768 B768 0 1 B769 B769 1 1 B770 B770 2 1 B771 B771 3 1 B772 B772 4 1 B773 B773 5 1 B774 B774 6 1 B775 B775 7 1 B776 B776 8 1 B777 B777 9 1 B778 B778 10 1 B779 B779 11 1 B780 B780 12 1 B781 B781 13 1 B782 B782 14 1 B783 B783 15 1 B784 B784 16 1 B785 B785 17 1 B786 B786 18 1 B787 B787 19 1 B788 B788 20 1 B789 B789 21 1 B790 B790 22 1 B791 B791 23 1 B792 B792 24 1 B793 B793 25 1 B794 B794 26 1 B795 B795 27 1 B796 B796 28 1 B797 B797 29 1 B798 B798 30 1 B799 B799 31 1 MPCBB1_VCTR25 MPCBB1_VCTR25 MPCBBx vector register 0x164 0x20 read-write 0xFFFFFFFF B800 B800 0 1 B801 B801 1 1 B802 B802 2 1 B803 B803 3 1 B804 B804 4 1 B805 B805 5 1 B806 B806 6 1 B807 B807 7 1 B808 B808 8 1 B809 B809 9 1 B810 B810 10 1 B811 B811 11 1 B812 B812 12 1 B813 B813 13 1 B814 B814 14 1 B815 B815 15 1 B816 B816 16 1 B817 B817 17 1 B818 B818 18 1 B819 B819 19 1 B820 B820 20 1 B821 B821 21 1 B822 B822 22 1 B823 B823 23 1 B824 B824 24 1 B825 B825 25 1 B826 B826 26 1 B827 B827 27 1 B828 B828 28 1 B829 B829 29 1 B830 B830 30 1 B831 B831 31 1 MPCBB1_VCTR26 MPCBB1_VCTR26 MPCBBx vector register 0x168 0x20 read-write 0xFFFFFFFF B832 B832 0 1 B833 B833 1 1 B834 B834 2 1 B835 B835 3 1 B836 B836 4 1 B837 B837 5 1 B838 B838 6 1 B839 B839 7 1 B840 B840 8 1 B841 B841 9 1 B842 B842 10 1 B843 B843 11 1 B844 B844 12 1 B845 B845 13 1 B846 B846 14 1 B847 B847 15 1 B848 B848 16 1 B849 B849 17 1 B850 B850 18 1 B851 B851 19 1 B852 B852 20 1 B853 B853 21 1 B854 B854 22 1 B855 B855 23 1 B856 B856 24 1 B857 B857 25 1 B858 B858 26 1 B859 B859 27 1 B860 B860 28 1 B861 B861 29 1 B862 B862 30 1 B863 B863 31 1 MPCBB1_VCTR27 MPCBB1_VCTR27 MPCBBx vector register 0x16C 0x20 read-write 0xFFFFFFFF B864 B864 0 1 B865 B865 1 1 B866 B866 2 1 B867 B867 3 1 B868 B868 4 1 B869 B869 5 1 B870 B870 6 1 B871 B871 7 1 B872 B872 8 1 B873 B873 9 1 B874 B874 10 1 B875 B875 11 1 B876 B876 12 1 B877 B877 13 1 B878 B878 14 1 B879 B879 15 1 B880 B880 16 1 B881 B881 17 1 B882 B882 18 1 B883 B883 19 1 B884 B884 20 1 B885 B885 21 1 B886 B886 22 1 B887 B887 23 1 B888 B888 24 1 B889 B889 25 1 B890 B890 26 1 B891 B891 27 1 B892 B892 28 1 B893 B893 29 1 B894 B894 30 1 B895 B895 31 1 MPCBB1_VCTR28 MPCBB1_VCTR28 MPCBBx vector register 0x170 0x20 read-write 0xFFFFFFFF B896 B896 0 1 B897 B897 1 1 B898 B898 2 1 B899 B899 3 1 B900 B900 4 1 B901 B901 5 1 B902 B902 6 1 B903 B903 7 1 B904 B904 8 1 B905 B905 9 1 B906 B906 10 1 B907 B907 11 1 B908 B908 12 1 B909 B909 13 1 B910 B910 14 1 B911 B911 15 1 B912 B912 16 1 B913 B913 17 1 B914 B914 18 1 B915 B915 19 1 B916 B916 20 1 B917 B917 21 1 B918 B918 22 1 B919 B919 23 1 B920 B920 24 1 B921 B921 25 1 B922 B922 26 1 B923 B923 27 1 B924 B924 28 1 B925 B925 29 1 B926 B926 30 1 B927 B927 31 1 MPCBB1_VCTR29 MPCBB1_VCTR29 MPCBBx vector register 0x174 0x20 read-write 0xFFFFFFFF B928 B928 0 1 B929 B929 1 1 B930 B930 2 1 B931 B931 3 1 B932 B932 4 1 B933 B933 5 1 B934 B934 6 1 B935 B935 7 1 B936 B936 8 1 B937 B937 9 1 B938 B938 10 1 B939 B939 11 1 B940 B940 12 1 B941 B941 13 1 B942 B942 14 1 B943 B943 15 1 B944 B944 16 1 B945 B945 17 1 B946 B946 18 1 B947 B947 19 1 B948 B948 20 1 B949 B949 21 1 B950 B950 22 1 B951 B951 23 1 B952 B952 24 1 B953 B953 25 1 B954 B954 26 1 B955 B955 27 1 B956 B956 28 1 B957 B957 29 1 B958 B958 30 1 B959 B959 31 1 MPCBB1_VCTR30 MPCBB1_VCTR30 MPCBBx vector register 0x178 0x20 read-write 0xFFFFFFFF B960 B960 0 1 B961 B961 1 1 B962 B962 2 1 B963 B963 3 1 B964 B964 4 1 B965 B965 5 1 B966 B966 6 1 B967 B967 7 1 B968 B968 8 1 B969 B969 9 1 B970 B970 10 1 B971 B971 11 1 B972 B972 12 1 B973 B973 13 1 B974 B974 14 1 B975 B975 15 1 B976 B976 16 1 B977 B977 17 1 B978 B978 18 1 B979 B979 19 1 B980 B980 20 1 B981 B981 21 1 B982 B982 22 1 B983 B983 23 1 B984 B984 24 1 B985 B985 25 1 B986 B986 26 1 B987 B987 27 1 B988 B988 28 1 B989 B989 29 1 B990 B990 30 1 B991 B991 31 1 MPCBB1_VCTR31 MPCBB1_VCTR31 MPCBBx vector register 0x17C 0x20 read-write 0xFFFFFFFF B992 B992 0 1 B993 B993 1 1 B994 B994 2 1 B995 B995 3 1 B996 B996 4 1 B997 B997 5 1 B998 B998 6 1 B999 B999 7 1 B1000 B1000 8 1 B1001 B1001 9 1 B1002 B1002 10 1 B1003 B1003 11 1 B1004 B1004 12 1 B1005 B1005 13 1 B1006 B1006 14 1 B1007 B1007 15 1 B1008 B1008 16 1 B1009 B1009 17 1 B1010 B1010 18 1 B1011 B1011 19 1 B1012 B1012 20 1 B1013 B1013 21 1 B1014 B1014 22 1 B1015 B1015 23 1 B1016 B1016 24 1 B1017 B1017 25 1 B1018 B1018 26 1 B1019 B1019 27 1 B1020 B1020 28 1 B1021 B1021 29 1 B1022 B1022 30 1 B1023 B1023 31 1 MPCBB1_VCTR32 MPCBB1_VCTR32 MPCBBx vector register 0x180 0x20 read-write 0xFFFFFFFF B1024 B1024 0 1 B1025 B1025 1 1 B1026 B1026 2 1 B1027 B1027 3 1 B1028 B1028 4 1 B1029 B1029 5 1 B1030 B1030 6 1 B1031 B1031 7 1 B1032 B1032 8 1 B1033 B1033 9 1 B1034 B1034 10 1 B1035 B1035 11 1 B1036 B1036 12 1 B1037 B1037 13 1 B1038 B1038 14 1 B1039 B1039 15 1 B1040 B1040 16 1 B1041 B1041 17 1 B1042 B1042 18 1 B1043 B1043 19 1 B1044 B1044 20 1 B1045 B1045 21 1 B1046 B1046 22 1 B1047 B1047 23 1 B1048 B1048 24 1 B1049 B1049 25 1 B1050 B1050 26 1 B1051 B1051 27 1 B1052 B1052 28 1 B1053 B1053 29 1 B1054 B1054 30 1 B1055 B1055 31 1 MPCBB1_VCTR33 MPCBB1_VCTR33 MPCBBx vector register 0x184 0x20 read-write 0xFFFFFFFF B1056 B1056 0 1 B1057 B1057 1 1 B1058 B1058 2 1 B1059 B1059 3 1 B1060 B1060 4 1 B1061 B1061 5 1 B1062 B1062 6 1 B1063 B1063 7 1 B1064 B1064 8 1 B1065 B1065 9 1 B1066 B1066 10 1 B1067 B1067 11 1 B1068 B1068 12 1 B1069 B1069 13 1 B1070 B1070 14 1 B1071 B1071 15 1 B1072 B1072 16 1 B1073 B1073 17 1 B1074 B1074 18 1 B1075 B1075 19 1 B1076 B1076 20 1 B1077 B1077 21 1 B1078 B1078 22 1 B1079 B1079 23 1 B1080 B1080 24 1 B1081 B1081 25 1 B1082 B1082 26 1 B1083 B1083 27 1 B1084 B1084 28 1 B1085 B1085 29 1 B1086 B1086 30 1 B1087 B1087 31 1 MPCBB1_VCTR34 MPCBB1_VCTR34 MPCBBx vector register 0x188 0x20 read-write 0xFFFFFFFF B1088 B1088 0 1 B1089 B1089 1 1 B1090 B1090 2 1 B1091 B1091 3 1 B1092 B1092 4 1 B1093 B1093 5 1 B1094 B1094 6 1 B1095 B1095 7 1 B1096 B1096 8 1 B1097 B1097 9 1 B1098 B1098 10 1 B1099 B1099 11 1 B1100 B1100 12 1 B1101 B1101 13 1 B1102 B1102 14 1 B1103 B1103 15 1 B1104 B1104 16 1 B1105 B1105 17 1 B1106 B1106 18 1 B1107 B1107 19 1 B1108 B1108 20 1 B1109 B1109 21 1 B1110 B1110 22 1 B1111 B1111 23 1 B1112 B1112 24 1 B1113 B1113 25 1 B1114 B1114 26 1 B1115 B1115 27 1 B1116 B1116 28 1 B1117 B1117 29 1 B1118 B1118 30 1 B1119 B1119 31 1 MPCBB1_VCTR35 MPCBB1_VCTR35 MPCBBx vector register 0x18C 0x20 read-write 0xFFFFFFFF B1120 B1120 0 1 B1121 B1121 1 1 B1122 B1122 2 1 B1123 B1123 3 1 B1124 B1124 4 1 B1125 B1125 5 1 B1126 B1126 6 1 B1127 B1127 7 1 B1128 B1128 8 1 B1129 B1129 9 1 B1130 B1130 10 1 B1131 B1131 11 1 B1132 B1132 12 1 B1133 B1133 13 1 B1134 B1134 14 1 B1135 B1135 15 1 B1136 B1136 16 1 B1137 B1137 17 1 B1138 B1138 18 1 B1139 B1139 19 1 B1140 B1140 20 1 B1141 B1141 21 1 B1142 B1142 22 1 B1143 B1143 23 1 B1144 B1144 24 1 B1145 B1145 25 1 B1146 B1146 26 1 B1147 B1147 27 1 B1148 B1148 28 1 B1149 B1149 29 1 B1150 B1150 30 1 B1151 B1151 31 1 MPCBB1_VCTR36 MPCBB1_VCTR36 MPCBBx vector register 0x190 0x20 read-write 0xFFFFFFFF B1152 B1152 0 1 B1153 B1153 1 1 B1154 B1154 2 1 B1155 B1155 3 1 B1156 B1156 4 1 B1157 B1157 5 1 B1158 B1158 6 1 B1159 B1159 7 1 B1160 B1160 8 1 B1161 B1161 9 1 B1162 B1162 10 1 B1163 B1163 11 1 B1164 B1164 12 1 B1165 B1165 13 1 B1166 B1166 14 1 B1167 B1167 15 1 B1168 B1168 16 1 B1169 B1169 17 1 B1170 B1170 18 1 B1171 B1171 19 1 B1172 B1172 20 1 B1173 B1173 21 1 B1174 B1174 22 1 B1175 B1175 23 1 B1176 B1176 24 1 B1177 B1177 25 1 B1178 B1178 26 1 B1179 B1179 27 1 B1180 B1180 28 1 B1181 B1181 29 1 B1182 B1182 30 1 B1183 B1183 31 1 MPCBB1_VCTR37 MPCBB1_VCTR37 MPCBBx vector register 0x194 0x20 read-write 0xFFFFFFFF B1184 B1184 0 1 B1185 B1185 1 1 B1186 B1186 2 1 B1187 B1187 3 1 B1188 B1188 4 1 B1189 B1189 5 1 B1190 B1190 6 1 B1191 B1191 7 1 B1192 B1192 8 1 B1193 B1193 9 1 B1194 B1194 10 1 B1195 B1195 11 1 B1196 B1196 12 1 B1197 B1197 13 1 B1198 B1198 14 1 B1199 B1199 15 1 B1200 B1200 16 1 B1201 B1201 17 1 B1202 B1202 18 1 B1203 B1203 19 1 B1204 B1204 20 1 B1205 B1205 21 1 B1206 B1206 22 1 B1207 B1207 23 1 B1208 B1208 24 1 B1209 B1209 25 1 B1210 B1210 26 1 B1211 B1211 27 1 B1212 B1212 28 1 B1213 B1213 29 1 B1214 B1214 30 1 B1215 B1215 31 1 MPCBB1_VCTR38 MPCBB1_VCTR38 MPCBBx vector register 0x198 0x20 read-write 0xFFFFFFFF B1216 B1216 0 1 B1217 B1217 1 1 B1218 B1218 2 1 B1219 B1219 3 1 B1220 B1220 4 1 B1221 B1221 5 1 B1222 B1222 6 1 B1223 B1223 7 1 B1224 B1224 8 1 B1225 B1225 9 1 B1226 B1226 10 1 B1227 B1227 11 1 B1228 B1228 12 1 B1229 B1229 13 1 B1230 B1230 14 1 B1231 B1231 15 1 B1232 B1232 16 1 B1233 B1233 17 1 B1234 B1234 18 1 B1235 B1235 19 1 B1236 B1236 20 1 B1237 B1237 21 1 B1238 B1238 22 1 B1239 B1239 23 1 B1240 B1240 24 1 B1241 B1241 25 1 B1242 B1242 26 1 B1243 B1243 27 1 B1244 B1244 28 1 B1245 B1245 29 1 B1246 B1246 30 1 B1247 B1247 31 1 MPCBB1_VCTR39 MPCBB1_VCTR39 MPCBBx vector register 0x19C 0x20 read-write 0xFFFFFFFF B1248 B1248 0 1 B1249 B1249 1 1 B1250 B1250 2 1 B1251 B1251 3 1 B1252 B1252 4 1 B1253 B1253 5 1 B1254 B1254 6 1 B1255 B1255 7 1 B1256 B1256 8 1 B1257 B1257 9 1 B1258 B1258 10 1 B1259 B1259 11 1 B1260 B1260 12 1 B1261 B1261 13 1 B1262 B1262 14 1 B1263 B1263 15 1 B1264 B1264 16 1 B1265 B1265 17 1 B1266 B1266 18 1 B1267 B1267 19 1 B1268 B1268 20 1 B1269 B1269 21 1 B1270 B1270 22 1 B1271 B1271 23 1 B1272 B1272 24 1 B1273 B1273 25 1 B1274 B1274 26 1 B1275 B1275 27 1 B1276 B1276 28 1 B1277 B1277 29 1 B1278 B1278 30 1 B1279 B1279 31 1 MPCBB1_VCTR40 MPCBB1_VCTR40 MPCBBx vector register 0x1A0 0x20 read-write 0xFFFFFFFF B1280 B1280 0 1 B1281 B1281 1 1 B1282 B1282 2 1 B1283 B1283 3 1 B1284 B1284 4 1 B1285 B1285 5 1 B1286 B1286 6 1 B1287 B1287 7 1 B1288 B1288 8 1 B1289 B1289 9 1 B1290 B1290 10 1 B1291 B1291 11 1 B1292 B1292 12 1 B1293 B1293 13 1 B1294 B1294 14 1 B1295 B1295 15 1 B1296 B1296 16 1 B1297 B1297 17 1 B1298 B1298 18 1 B1299 B1299 19 1 B1300 B1300 20 1 B1301 B1301 21 1 B1302 B1302 22 1 B1303 B1303 23 1 B1304 B1304 24 1 B1305 B1305 25 1 B1306 B1306 26 1 B1307 B1307 27 1 B1308 B1308 28 1 B1309 B1309 29 1 B1310 B1310 30 1 B1311 B1311 31 1 MPCBB1_VCTR41 MPCBB1_VCTR41 MPCBBx vector register 0x1A4 0x20 read-write 0xFFFFFFFF B1312 B1312 0 1 B1313 B1313 1 1 B1314 B1314 2 1 B1315 B1315 3 1 B1316 B1316 4 1 B1317 B1317 5 1 B1318 B1318 6 1 B1319 B1319 7 1 B1320 B1320 8 1 B1321 B1321 9 1 B1322 B1322 10 1 B1323 B1323 11 1 B1324 B1324 12 1 B1325 B1325 13 1 B1326 B1326 14 1 B1327 B1327 15 1 B1328 B1328 16 1 B1329 B1329 17 1 B1330 B1330 18 1 B1331 B1331 19 1 B1332 B1332 20 1 B1333 B1333 21 1 B1334 B1334 22 1 B1335 B1335 23 1 B1336 B1336 24 1 B1337 B1337 25 1 B1338 B1338 26 1 B1339 B1339 27 1 B1340 B1340 28 1 B1341 B1341 29 1 B1342 B1342 30 1 B1343 B1343 31 1 MPCBB1_VCTR42 MPCBB1_VCTR42 MPCBBx vector register 0x1A8 0x20 read-write 0xFFFFFFFF B1344 B1344 0 1 B1345 B1345 1 1 B1346 B1346 2 1 B1347 B1347 3 1 B1348 B1348 4 1 B1349 B1349 5 1 B1350 B1350 6 1 B1351 B1351 7 1 B1352 B1352 8 1 B1353 B1353 9 1 B1354 B1354 10 1 B1355 B1355 11 1 B1356 B1356 12 1 B1357 B1357 13 1 B1358 B1358 14 1 B1359 B1359 15 1 B1360 B1360 16 1 B1361 B1361 17 1 B1362 B1362 18 1 B1363 B1363 19 1 B1364 B1364 20 1 B1365 B1365 21 1 B1366 B1366 22 1 B1367 B1367 23 1 B1368 B1368 24 1 B1369 B1369 25 1 B1370 B1370 26 1 B1371 B1371 27 1 B1372 B1372 28 1 B1373 B1373 29 1 B1374 B1374 30 1 B1375 B1375 31 1 MPCBB1_VCTR43 MPCBB1_VCTR43 MPCBBx vector register 0x1AC 0x20 read-write 0xFFFFFFFF B1376 B1376 0 1 B1377 B1377 1 1 B1378 B1378 2 1 B1379 B1379 3 1 B1380 B1380 4 1 B1381 B1381 5 1 B1382 B1382 6 1 B1383 B1383 7 1 B1384 B1384 8 1 B1385 B1385 9 1 B1386 B1386 10 1 B1387 B1387 11 1 B1388 B1388 12 1 B1389 B1389 13 1 B1390 B1390 14 1 B1391 B1391 15 1 B1392 B1392 16 1 B1393 B1393 17 1 B1394 B1394 18 1 B1395 B1395 19 1 B1396 B1396 20 1 B1397 B1397 21 1 B1398 B1398 22 1 B1399 B1399 23 1 B1400 B1400 24 1 B1401 B1401 25 1 B1402 B1402 26 1 B1403 B1403 27 1 B1404 B1404 28 1 B1405 B1405 29 1 B1406 B1406 30 1 B1407 B1407 31 1 MPCBB1_VCTR44 MPCBB1_VCTR44 MPCBBx vector register 0x1B0 0x20 read-write 0xFFFFFFFF B1408 B1408 0 1 B1409 B1409 1 1 B1410 B1410 2 1 B1411 B1411 3 1 B1412 B1412 4 1 B1413 B1413 5 1 B1414 B1414 6 1 B1415 B1415 7 1 B1416 B1416 8 1 B1417 B1417 9 1 B1418 B1418 10 1 B1419 B1419 11 1 B1420 B1420 12 1 B1421 B1421 13 1 B1422 B1422 14 1 B1423 B1423 15 1 B1424 B1424 16 1 B1425 B1425 17 1 B1426 B1426 18 1 B1427 B1427 19 1 B1428 B1428 20 1 B1429 B1429 21 1 B1430 B1430 22 1 B1431 B1431 23 1 B1432 B1432 24 1 B1433 B1433 25 1 B1434 B1434 26 1 B1435 B1435 27 1 B1436 B1436 28 1 B1437 B1437 29 1 B1438 B1438 30 1 B1439 B1439 31 1 MPCBB1_VCTR45 MPCBB1_VCTR45 MPCBBx vector register 0x1B4 0x20 read-write 0xFFFFFFFF B1440 B1440 0 1 B1441 B1441 1 1 B1442 B1442 2 1 B1443 B1443 3 1 B1444 B1444 4 1 B1445 B1445 5 1 B1446 B1446 6 1 B1447 B1447 7 1 B1448 B1448 8 1 B1449 B1449 9 1 B1450 B1450 10 1 B1451 B1451 11 1 B1452 B1452 12 1 B1453 B1453 13 1 B1454 B1454 14 1 B1455 B1455 15 1 B1456 B1456 16 1 B1457 B1457 17 1 B1458 B1458 18 1 B1459 B1459 19 1 B1460 B1460 20 1 B1461 B1461 21 1 B1462 B1462 22 1 B1463 B1463 23 1 B1464 B1464 24 1 B1465 B1465 25 1 B1466 B1466 26 1 B1467 B1467 27 1 B1468 B1468 28 1 B1469 B1469 29 1 B1470 B1470 30 1 B1471 B1471 31 1 MPCBB1_VCTR46 MPCBB1_VCTR46 MPCBBx vector register 0x1B8 0x20 read-write 0xFFFFFFFF B1472 B1472 0 1 B1473 B1473 1 1 B1474 B1474 2 1 B1475 B1475 3 1 B1476 B1476 4 1 B1477 B1477 5 1 B1478 B1478 6 1 B1479 B1479 7 1 B1480 B1480 8 1 B1481 B1481 9 1 B1482 B1482 10 1 B1483 B1483 11 1 B1484 B1484 12 1 B1485 B1485 13 1 B1486 B1486 14 1 B1487 B1487 15 1 B1488 B1488 16 1 B1489 B1489 17 1 B1490 B1490 18 1 B1491 B1491 19 1 B1492 B1492 20 1 B1493 B1493 21 1 B1494 B1494 22 1 B1495 B1495 23 1 B1496 B1496 24 1 B1497 B1497 25 1 B1498 B1498 26 1 B1499 B1499 27 1 B1500 B1500 28 1 B1501 B1501 29 1 B1502 B1502 30 1 B1503 B1503 31 1 MPCBB1_VCTR47 MPCBB1_VCTR47 MPCBBx vector register 0x1BC 0x20 read-write 0xFFFFFFFF B1504 B1504 0 1 B1505 B1505 1 1 B1506 B1506 2 1 B1507 B1507 3 1 B1508 B1508 4 1 B1509 B1509 5 1 B1510 B1510 6 1 B1511 B1511 7 1 B1512 B1512 8 1 B1513 B1513 9 1 B1514 B1514 10 1 B1515 B1515 11 1 B1516 B1516 12 1 B1517 B1517 13 1 B1518 B1518 14 1 B1519 B1519 15 1 B1520 B1520 16 1 B1521 B1521 17 1 B1522 B1522 18 1 B1523 B1523 19 1 B1524 B1524 20 1 B1525 B1525 21 1 B1526 B1526 22 1 B1527 B1527 23 1 B1528 B1528 24 1 B1529 B1529 25 1 B1530 B1530 26 1 B1531 B1531 27 1 B1532 B1532 28 1 B1533 B1533 29 1 B1534 B1534 30 1 B1535 B1535 31 1 MPCBB1_VCTR48 MPCBB1_VCTR48 MPCBBx vector register 0x1C0 0x20 read-write 0xFFFFFFFF B1536 B1536 0 1 B1537 B1537 1 1 B1538 B1538 2 1 B1539 B1539 3 1 B1540 B1540 4 1 B1541 B1541 5 1 B1542 B1542 6 1 B1543 B1543 7 1 B1544 B1544 8 1 B1545 B1545 9 1 B1546 B1546 10 1 B1547 B1547 11 1 B1548 B1548 12 1 B1549 B1549 13 1 B1550 B1550 14 1 B1551 B1551 15 1 B1552 B1552 16 1 B1553 B1553 17 1 B1554 B1554 18 1 B1555 B1555 19 1 B1556 B1556 20 1 B1557 B1557 21 1 B1558 B1558 22 1 B1559 B1559 23 1 B1560 B1560 24 1 B1561 B1561 25 1 B1562 B1562 26 1 B1563 B1563 27 1 B1564 B1564 28 1 B1565 B1565 29 1 B1566 B1566 30 1 B1567 B1567 31 1 MPCBB1_VCTR49 MPCBB1_VCTR49 MPCBBx vector register 0x1C4 0x20 read-write 0xFFFFFFFF B1568 B1568 0 1 B1569 B1569 1 1 B1570 B1570 2 1 B1571 B1571 3 1 B1572 B1572 4 1 B1573 B1573 5 1 B1574 B1574 6 1 B1575 B1575 7 1 B1576 B1576 8 1 B1577 B1577 9 1 B1578 B1578 10 1 B1579 B1579 11 1 B1580 B1580 12 1 B1581 B1581 13 1 B1582 B1582 14 1 B1583 B1583 15 1 B1584 B1584 16 1 B1585 B1585 17 1 B1586 B1586 18 1 B1587 B1587 19 1 B1588 B1588 20 1 B1589 B1589 21 1 B1590 B1590 22 1 B1591 B1591 23 1 B1592 B1592 24 1 B1593 B1593 25 1 B1594 B1594 26 1 B1595 B1595 27 1 B1596 B1596 28 1 B1597 B1597 29 1 B1598 B1598 30 1 B1599 B1599 31 1 MPCBB1_VCTR50 MPCBB1_VCTR50 MPCBBx vector register 0x1C8 0x20 read-write 0xFFFFFFFF B1600 B1600 0 1 B1601 B1601 1 1 B1602 B1602 2 1 B1603 B1603 3 1 B1604 B1604 4 1 B1605 B1605 5 1 B1606 B1606 6 1 B1607 B1607 7 1 B1608 B1608 8 1 B1609 B1609 9 1 B1610 B1610 10 1 B1611 B1611 11 1 B1612 B1612 12 1 B1613 B1613 13 1 B1614 B1614 14 1 B1615 B1615 15 1 B1616 B1616 16 1 B1617 B1617 17 1 B1618 B1618 18 1 B1619 B1619 19 1 B1620 B1620 20 1 B1621 B1621 21 1 B1622 B1622 22 1 B1623 B1623 23 1 B1624 B1624 24 1 B1625 B1625 25 1 B1626 B1626 26 1 B1627 B1627 27 1 B1628 B1628 28 1 B1629 B1629 29 1 B1630 B1630 30 1 B1631 B1631 31 1 MPCBB1_VCTR51 MPCBB1_VCTR51 MPCBBx vector register 0x1CC 0x20 read-write 0xFFFFFFFF B1632 B1632 0 1 B1633 B1633 1 1 B1634 B1634 2 1 B1635 B1635 3 1 B1636 B1636 4 1 B1637 B1637 5 1 B1638 B1638 6 1 B1639 B1639 7 1 B1640 B1640 8 1 B1641 B1641 9 1 B1642 B1642 10 1 B1643 B1643 11 1 B1644 B1644 12 1 B1645 B1645 13 1 B1646 B1646 14 1 B1647 B1647 15 1 B1648 B1648 16 1 B1649 B1649 17 1 B1650 B1650 18 1 B1651 B1651 19 1 B1652 B1652 20 1 B1653 B1653 21 1 B1654 B1654 22 1 B1655 B1655 23 1 B1656 B1656 24 1 B1657 B1657 25 1 B1658 B1658 26 1 B1659 B1659 27 1 B1660 B1660 28 1 B1661 B1661 29 1 B1662 B1662 30 1 B1663 B1663 31 1 MPCBB1_VCTR52 MPCBB1_VCTR52 MPCBBx vector register 0x1D0 0x20 read-write 0xFFFFFFFF B1664 B1664 0 1 B1665 B1665 1 1 B1666 B1666 2 1 B1667 B1667 3 1 B1668 B1668 4 1 B1669 B1669 5 1 B1670 B1670 6 1 B1671 B1671 7 1 B1672 B1672 8 1 B1673 B1673 9 1 B1674 B1674 10 1 B1675 B1675 11 1 B1676 B1676 12 1 B1677 B1677 13 1 B1678 B1678 14 1 B1679 B1679 15 1 B1680 B1680 16 1 B1681 B1681 17 1 B1682 B1682 18 1 B1683 B1683 19 1 B1684 B1684 20 1 B1685 B1685 21 1 B1686 B1686 22 1 B1687 B1687 23 1 B1688 B1688 24 1 B1689 B1689 25 1 B1690 B1690 26 1 B1691 B1691 27 1 B1692 B1692 28 1 B1693 B1693 29 1 B1694 B1694 30 1 B1695 B1695 31 1 MPCBB1_VCTR53 MPCBB1_VCTR53 MPCBBx vector register 0x1D4 0x20 read-write 0xFFFFFFFF B1696 B1696 0 1 B1697 B1697 1 1 B1698 B1698 2 1 B1699 B1699 3 1 B1700 B1700 4 1 B1701 B1701 5 1 B1702 B1702 6 1 B1703 B1703 7 1 B1704 B1704 8 1 B1705 B1705 9 1 B1706 B1706 10 1 B1707 B1707 11 1 B1708 B1708 12 1 B1709 B1709 13 1 B1710 B1710 14 1 B1711 B1711 15 1 B1712 B1712 16 1 B1713 B1713 17 1 B1714 B1714 18 1 B1715 B1715 19 1 B1716 B1716 20 1 B1717 B1717 21 1 B1718 B1718 22 1 B1719 B1719 23 1 B1720 B1720 24 1 B1721 B1721 25 1 B1722 B1722 26 1 B1723 B1723 27 1 B1724 B1724 28 1 B1725 B1725 29 1 B1726 B1726 30 1 B1727 B1727 31 1 MPCBB1_VCTR54 MPCBB1_VCTR54 MPCBBx vector register 0x1D8 0x20 read-write 0xFFFFFFFF B1728 B1728 0 1 B1729 B1729 1 1 B1730 B1730 2 1 B1731 B1731 3 1 B1732 B1732 4 1 B1733 B1733 5 1 B1734 B1734 6 1 B1735 B1735 7 1 B1736 B1736 8 1 B1737 B1737 9 1 B1738 B1738 10 1 B1739 B1739 11 1 B1740 B1740 12 1 B1741 B1741 13 1 B1742 B1742 14 1 B1743 B1743 15 1 B1744 B1744 16 1 B1745 B1745 17 1 B1746 B1746 18 1 B1747 B1747 19 1 B1748 B1748 20 1 B1749 B1749 21 1 B1750 B1750 22 1 B1751 B1751 23 1 B1752 B1752 24 1 B1753 B1753 25 1 B1754 B1754 26 1 B1755 B1755 27 1 B1756 B1756 28 1 B1757 B1757 29 1 B1758 B1758 30 1 B1759 B1759 31 1 MPCBB1_VCTR55 MPCBB1_VCTR55 MPCBBx vector register 0x1DC 0x20 read-write 0xFFFFFFFF B1760 B1760 0 1 B1761 B1761 1 1 B1762 B1762 2 1 B1763 B1763 3 1 B1764 B1764 4 1 B1765 B1765 5 1 B1766 B1766 6 1 B1767 B1767 7 1 B1768 B1768 8 1 B1769 B1769 9 1 B1770 B1770 10 1 B1771 B1771 11 1 B1772 B1772 12 1 B1773 B1773 13 1 B1774 B1774 14 1 B1775 B1775 15 1 B1776 B1776 16 1 B1777 B1777 17 1 B1778 B1778 18 1 B1779 B1779 19 1 B1780 B1780 20 1 B1781 B1781 21 1 B1782 B1782 22 1 B1783 B1783 23 1 B1784 B1784 24 1 B1785 B1785 25 1 B1786 B1786 26 1 B1787 B1787 27 1 B1788 B1788 28 1 B1789 B1789 29 1 B1790 B1790 30 1 B1791 B1791 31 1 MPCBB1_VCTR56 MPCBB1_VCTR56 MPCBBx vector register 0x1E0 0x20 read-write 0xFFFFFFFF B1792 B1792 0 1 B1793 B1793 1 1 B1794 B1794 2 1 B1795 B1795 3 1 B1796 B1796 4 1 B1797 B1797 5 1 B1798 B1798 6 1 B1799 B1799 7 1 B1800 B1800 8 1 B1801 B1801 9 1 B1802 B1802 10 1 B1803 B1803 11 1 B1804 B1804 12 1 B1805 B1805 13 1 B1806 B1806 14 1 B1807 B1807 15 1 B1808 B1808 16 1 B1809 B1809 17 1 B1810 B1810 18 1 B1811 B1811 19 1 B1812 B1812 20 1 B1813 B1813 21 1 B1814 B1814 22 1 B1815 B1815 23 1 B1816 B1816 24 1 B1817 B1817 25 1 B1818 B1818 26 1 B1819 B1819 27 1 B1820 B1820 28 1 B1821 B1821 29 1 B1822 B1822 30 1 B1823 B1823 31 1 MPCBB1_VCTR57 MPCBB1_VCTR57 MPCBBx vector register 0x1E4 0x20 read-write 0xFFFFFFFF B1824 B1824 0 1 B1825 B1825 1 1 B1826 B1826 2 1 B1827 B1827 3 1 B1828 B1828 4 1 B1829 B1829 5 1 B1830 B1830 6 1 B1831 B1831 7 1 B1832 B1832 8 1 B1833 B1833 9 1 B1834 B1834 10 1 B1835 B1835 11 1 B1836 B1836 12 1 B1837 B1837 13 1 B1838 B1838 14 1 B1839 B1839 15 1 B1840 B1840 16 1 B1841 B1841 17 1 B1842 B1842 18 1 B1843 B1843 19 1 B1844 B1844 20 1 B1845 B1845 21 1 B1846 B1846 22 1 B1847 B1847 23 1 B1848 B1848 24 1 B1849 B1849 25 1 B1850 B1850 26 1 B1851 B1851 27 1 B1852 B1852 28 1 B1853 B1853 29 1 B1854 B1854 30 1 B1855 B1855 31 1 MPCBB1_VCTR58 MPCBB1_VCTR58 MPCBBx vector register 0x1E8 0x20 read-write 0xFFFFFFFF B1856 B1856 0 1 B1857 B1857 1 1 B1858 B1858 2 1 B1859 B1859 3 1 B1860 B1860 4 1 B1861 B1861 5 1 B1862 B1862 6 1 B1863 B1863 7 1 B1864 B1864 8 1 B1865 B1865 9 1 B1866 B1866 10 1 B1867 B1867 11 1 B1868 B1868 12 1 B1869 B1869 13 1 B1870 B1870 14 1 B1871 B1871 15 1 B1872 B1872 16 1 B1873 B1873 17 1 B1874 B1874 18 1 B1875 B1875 19 1 B1876 B1876 20 1 B1877 B1877 21 1 B1878 B1878 22 1 B1879 B1879 23 1 B1880 B1880 24 1 B1881 B1881 25 1 B1882 B1882 26 1 B1883 B1883 27 1 B1884 B1884 28 1 B1885 B1885 29 1 B1886 B1886 30 1 B1887 B1887 31 1 MPCBB1_VCTR59 MPCBB1_VCTR59 MPCBBx vector register 0x1EC 0x20 read-write 0xFFFFFFFF B1888 B1888 0 1 B1889 B1889 1 1 B1890 B1890 2 1 B1891 B1891 3 1 B1892 B1892 4 1 B1893 B1893 5 1 B1894 B1894 6 1 B1895 B1895 7 1 B1896 B1896 8 1 B1897 B1897 9 1 B1898 B1898 10 1 B1899 B1899 11 1 B1900 B1900 12 1 B1901 B1901 13 1 B1902 B1902 14 1 B1903 B1903 15 1 B1904 B1904 16 1 B1905 B1905 17 1 B1906 B1906 18 1 B1907 B1907 19 1 B1908 B1908 20 1 B1909 B1909 21 1 B1910 B1910 22 1 B1911 B1911 23 1 B1912 B1912 24 1 B1913 B1913 25 1 B1914 B1914 26 1 B1915 B1915 27 1 B1916 B1916 28 1 B1917 B1917 29 1 B1918 B1918 30 1 B1919 B1919 31 1 MPCBB1_VCTR60 MPCBB1_VCTR60 MPCBBx vector register 0x1F0 0x20 read-write 0xFFFFFFFF B1920 B1920 0 1 B1921 B1921 1 1 B1922 B1922 2 1 B1923 B1923 3 1 B1924 B1924 4 1 B1925 B1925 5 1 B1926 B1926 6 1 B1927 B1927 7 1 B1928 B1928 8 1 B1929 B1929 9 1 B1930 B1930 10 1 B1931 B1931 11 1 B1932 B1932 12 1 B1933 B1933 13 1 B1934 B1934 14 1 B1935 B1935 15 1 B1936 B1936 16 1 B1937 B1937 17 1 B1938 B1938 18 1 B1939 B1939 19 1 B1940 B1940 20 1 B1941 B1941 21 1 B1942 B1942 22 1 B1943 B1943 23 1 B1944 B1944 24 1 B1945 B1945 25 1 B1946 B1946 26 1 B1947 B1947 27 1 B1948 B1948 28 1 B1949 B1949 29 1 B1950 B1950 30 1 B1951 B1951 31 1 MPCBB1_VCTR61 MPCBB1_VCTR61 MPCBBx vector register 0x1F4 0x20 read-write 0xFFFFFFFF B1952 B1952 0 1 B1953 B1953 1 1 B1954 B1954 2 1 B1955 B1955 3 1 B1956 B1956 4 1 B1957 B1957 5 1 B1958 B1958 6 1 B1959 B1959 7 1 B1960 B1960 8 1 B1961 B1961 9 1 B1962 B1962 10 1 B1963 B1963 11 1 B1964 B1964 12 1 B1965 B1965 13 1 B1966 B1966 14 1 B1967 B1967 15 1 B1968 B1968 16 1 B1969 B1969 17 1 B1970 B1970 18 1 B1971 B1971 19 1 B1972 B1972 20 1 B1973 B1973 21 1 B1974 B1974 22 1 B1975 B1975 23 1 B1976 B1976 24 1 B1977 B1977 25 1 B1978 B1978 26 1 B1979 B1979 27 1 B1980 B1980 28 1 B1981 B1981 29 1 B1982 B1982 30 1 B1983 B1983 31 1 MPCBB1_VCTR62 MPCBB1_VCTR62 MPCBBx vector register 0x1F8 0x20 read-write 0xFFFFFFFF B1984 B1984 0 1 B1985 B1985 1 1 B1986 B1986 2 1 B1987 B1987 3 1 B1988 B1988 4 1 B1989 B1989 5 1 B1990 B1990 6 1 B1991 B1991 7 1 B1992 B1992 8 1 B1993 B1993 9 1 B1994 B1994 10 1 B1995 B1995 11 1 B1996 B1996 12 1 B1997 B1997 13 1 B1998 B1998 14 1 B1999 B1999 15 1 B2000 B2000 16 1 B2001 B2001 17 1 B2002 B2002 18 1 B2003 B2003 19 1 B2004 B2004 20 1 B2005 B2005 21 1 B2006 B2006 22 1 B2007 B2007 23 1 B2008 B2008 24 1 B2009 B2009 25 1 B2010 B2010 26 1 B2011 B2011 27 1 B2012 B2012 28 1 B2013 B2013 29 1 B2014 B2014 30 1 B2015 B2015 31 1 MPCBB1_VCTR63 MPCBB1_VCTR63 MPCBBx vector register 0x1FC 0x20 read-write 0xFFFFFFFF B2016 B2016 0 1 B2017 B2017 1 1 B2018 B2018 2 1 B2019 B2019 3 1 B2020 B2020 4 1 B2021 B2021 5 1 B2022 B2022 6 1 B2023 B2023 7 1 B2024 B2024 8 1 B2025 B2025 9 1 B2026 B2026 10 1 B2027 B2027 11 1 B2028 B2028 12 1 B2029 B2029 13 1 B2030 B2030 14 1 B2031 B2031 15 1 B2032 B2032 16 1 B2033 B2033 17 1 B2034 B2034 18 1 B2035 B2035 19 1 B2036 B2036 20 1 B2037 B2037 21 1 B2038 B2038 22 1 B2039 B2039 23 1 B2040 B2040 24 1 B2041 B2041 25 1 B2042 B2042 26 1 B2043 B2043 27 1 B2044 B2044 28 1 B2045 B2045 29 1 B2046 B2046 30 1 B2047 B2047 31 1 GTZC_MPCBB2 GTZC_MPCBB2 GTZC 0x40033000 0x0 0x400 registers MPCBB2_CR MPCBB2_CR MPCBB control register 0x0 0x20 read-write 0x00000000 LCK LCK 0 1 INVSECSTATE INVSECSTATE 30 1 SRWILADIS SRWILADIS 31 1 MPCBB2_LCKVTR1 MPCBB2_LCKVTR1 MPCBB control register 0x10 0x20 read-write 0x00000000 LCKSB0 LCKSB0 0 1 LCKSB1 LCKSB1 1 1 LCKSB2 LCKSB2 2 1 LCKSB3 LCKSB3 3 1 LCKSB4 LCKSB4 4 1 LCKSB5 LCKSB5 5 1 LCKSB6 LCKSB6 6 1 LCKSB7 LCKSB7 7 1 LCKSB8 LCKSB8 8 1 LCKSB9 LCKSB9 9 1 LCKSB10 LCKSB10 10 1 LCKSB11 LCKSB11 11 1 LCKSB12 LCKSB12 12 1 LCKSB13 LCKSB13 13 1 LCKSB14 LCKSB14 14 1 LCKSB15 LCKSB15 15 1 LCKSB16 LCKSB16 16 1 LCKSB17 LCKSB17 17 1 LCKSB18 LCKSB18 18 1 LCKSB19 LCKSB19 19 1 LCKSB20 LCKSB20 20 1 LCKSB21 LCKSB21 21 1 LCKSB22 LCKSB22 22 1 LCKSB23 LCKSB23 23 1 LCKSB24 LCKSB24 24 1 LCKSB25 LCKSB25 25 1 LCKSB26 LCKSB26 26 1 LCKSB27 LCKSB27 27 1 LCKSB28 LCKSB28 28 1 LCKSB29 LCKSB29 29 1 LCKSB30 LCKSB30 30 1 LCKSB31 LCKSB31 31 1 MPCBB2_LCKVTR2 MPCBB2_LCKVTR2 MPCBB control register 0x14 0x20 read-write 0x00000000 LCKSB32 LCKSB32 0 1 LCKSB33 LCKSB33 1 1 LCKSB34 LCKSB34 2 1 LCKSB35 LCKSB35 3 1 LCKSB36 LCKSB36 4 1 LCKSB37 LCKSB37 5 1 LCKSB38 LCKSB38 6 1 LCKSB39 LCKSB39 7 1 LCKSB40 LCKSB40 8 1 LCKSB41 LCKSB41 9 1 LCKSB42 LCKSB42 10 1 LCKSB43 LCKSB43 11 1 LCKSB44 LCKSB44 12 1 LCKSB45 LCKSB45 13 1 LCKSB46 LCKSB46 14 1 LCKSB47 LCKSB47 15 1 LCKSB48 LCKSB48 16 1 LCKSB49 LCKSB49 17 1 LCKSB50 LCKSB50 18 1 LCKSB51 LCKSB51 19 1 LCKSB52 LCKSB52 20 1 LCKSB53 LCKSB53 21 1 LCKSB54 LCKSB54 22 1 LCKSB55 LCKSB55 23 1 LCKSB56 LCKSB56 24 1 LCKSB57 LCKSB57 25 1 LCKSB58 LCKSB58 26 1 LCKSB59 LCKSB59 27 1 LCKSB60 LCKSB60 28 1 LCKSB61 LCKSB61 29 1 LCKSB62 LCKSB62 30 1 LCKSB63 LCKSB63 31 1 MPCBB2_VCTR0 MPCBB2_VCTR0 MPCBBx vector register 0x100 0x20 read-write 0xFFFFFFFF B0 B0 0 1 B1 B1 1 1 B2 B2 2 1 B3 B3 3 1 B4 B4 4 1 B5 B5 5 1 B6 B6 6 1 B7 B7 7 1 B8 B8 8 1 B9 B9 9 1 B10 B10 10 1 B11 B11 11 1 B12 B12 12 1 B13 B13 13 1 B14 B14 14 1 B15 B15 15 1 B16 B16 16 1 B17 B17 17 1 B18 B18 18 1 B19 B19 19 1 B20 B20 20 1 B21 B21 21 1 B22 B22 22 1 B23 B23 23 1 B24 B24 24 1 B25 B25 25 1 B26 B26 26 1 B27 B27 27 1 B28 B28 28 1 B29 B29 29 1 B30 B30 30 1 B31 B31 31 1 MPCBB2_VCTR1 MPCBB2_VCTR1 MPCBBx vector register 0x104 0x20 read-write 0xFFFFFFFF B32 B32 0 1 B33 B33 1 1 B34 B34 2 1 B35 B35 3 1 B36 B36 4 1 B37 B37 5 1 B38 B38 6 1 B39 B39 7 1 B40 B40 8 1 B41 B41 9 1 B42 B42 10 1 B43 B43 11 1 B44 B44 12 1 B45 B45 13 1 B46 B46 14 1 B47 B47 15 1 B48 B48 16 1 B49 B49 17 1 B50 B50 18 1 B51 B51 19 1 B52 B52 20 1 B53 B53 21 1 B54 B54 22 1 B55 B55 23 1 B56 B56 24 1 B57 B57 25 1 B58 B58 26 1 B59 B59 27 1 B60 B60 28 1 B61 B61 29 1 B62 B62 30 1 B63 B63 31 1 MPCBB2_VCTR2 MPCBB2_VCTR2 MPCBBx vector register 0x108 0x20 read-write 0xFFFFFFFF B64 B64 0 1 B65 B65 1 1 B66 B66 2 1 B67 B67 3 1 B68 B68 4 1 B69 B69 5 1 B70 B70 6 1 B71 B71 7 1 B72 B72 8 1 B73 B73 9 1 B74 B74 10 1 B75 B75 11 1 B76 B76 12 1 B77 B77 13 1 B78 B78 14 1 B79 B79 15 1 B80 B80 16 1 B81 B81 17 1 B82 B82 18 1 B83 B83 19 1 B84 B84 20 1 B85 B85 21 1 B86 B86 22 1 B87 B87 23 1 B88 B88 24 1 B89 B89 25 1 B90 B90 26 1 B91 B91 27 1 B92 B92 28 1 B93 B93 29 1 B94 B94 30 1 B95 B95 31 1 MPCBB2_VCTR3 MPCBB2_VCTR3 MPCBBx vector register 0x10C 0x20 read-write 0xFFFFFFFF B96 B96 0 1 B97 B97 1 1 B98 B98 2 1 B99 B99 3 1 B100 B100 4 1 B101 B101 5 1 B102 B102 6 1 B103 B103 7 1 B104 B104 8 1 B105 B105 9 1 B106 B106 10 1 B107 B107 11 1 B108 B108 12 1 B109 B109 13 1 B110 B110 14 1 B111 B111 15 1 B112 B112 16 1 B113 B113 17 1 B114 B114 18 1 B115 B115 19 1 B116 B116 20 1 B117 B117 21 1 B118 B118 22 1 B119 B119 23 1 B120 B120 24 1 B121 B121 25 1 B122 B122 26 1 B123 B123 27 1 B124 B124 28 1 B125 B125 29 1 B126 B126 30 1 B127 B127 31 1 MPCBB2_VCTR4 MPCBB2_VCTR4 MPCBBx vector register 0x110 0x20 read-write 0xFFFFFFFF B128 B128 0 1 B129 B129 1 1 B130 B130 2 1 B131 B131 3 1 B132 B132 4 1 B133 B133 5 1 B134 B134 6 1 B135 B135 7 1 B136 B136 8 1 B137 B137 9 1 B138 B138 10 1 B139 B139 11 1 B140 B140 12 1 B141 B141 13 1 B142 B142 14 1 B143 B143 15 1 B144 B144 16 1 B145 B145 17 1 B146 B146 18 1 B147 B147 19 1 B148 B148 20 1 B149 B149 21 1 B150 B150 22 1 B151 B151 23 1 B152 B152 24 1 B153 B153 25 1 B154 B154 26 1 B155 B155 27 1 B156 B156 28 1 B157 B157 29 1 B158 B158 30 1 B159 B159 31 1 MPCBB2_VCTR5 MPCBB2_VCTR5 MPCBBx vector register 0x114 0x20 read-write 0xFFFFFFFF B160 B160 0 1 B161 B161 1 1 B162 B162 2 1 B163 B163 3 1 B164 B164 4 1 B165 B165 5 1 B166 B166 6 1 B167 B167 7 1 B168 B168 8 1 B169 B169 9 1 B170 B170 10 1 B171 B171 11 1 B172 B172 12 1 B173 B173 13 1 B174 B174 14 1 B175 B175 15 1 B176 B176 16 1 B177 B177 17 1 B178 B178 18 1 B179 B179 19 1 B180 B180 20 1 B181 B181 21 1 B182 B182 22 1 B183 B183 23 1 B184 B184 24 1 B185 B185 25 1 B186 B186 26 1 B187 B187 27 1 B188 B188 28 1 B189 B189 29 1 B190 B190 30 1 B191 B191 31 1 MPCBB2_VCTR6 MPCBB2_VCTR6 MPCBBx vector register 0x118 0x20 read-write 0xFFFFFFFF B192 B192 0 1 B193 B193 1 1 B194 B194 2 1 B195 B195 3 1 B196 B196 4 1 B197 B197 5 1 B198 B198 6 1 B199 B199 7 1 B200 B200 8 1 B201 B201 9 1 B202 B202 10 1 B203 B203 11 1 B204 B204 12 1 B205 B205 13 1 B206 B206 14 1 B207 B207 15 1 B208 B208 16 1 B209 B209 17 1 B210 B210 18 1 B211 B211 19 1 B212 B212 20 1 B213 B213 21 1 B214 B214 22 1 B215 B215 23 1 B216 B216 24 1 B217 B217 25 1 B218 B218 26 1 B219 B219 27 1 B220 B220 28 1 B221 B221 29 1 B222 B222 30 1 B223 B223 31 1 MPCBB2_VCTR7 MPCBB2_VCTR7 MPCBBx vector register 0x11C 0x20 read-write 0xFFFFFFFF B224 B224 0 1 B225 B225 1 1 B226 B226 2 1 B227 B227 3 1 B228 B228 4 1 B229 B229 5 1 B230 B230 6 1 B231 B231 7 1 B232 B232 8 1 B233 B233 9 1 B234 B234 10 1 B235 B235 11 1 B236 B236 12 1 B237 B237 13 1 B238 B238 14 1 B239 B239 15 1 B240 B240 16 1 B241 B241 17 1 B242 B242 18 1 B243 B243 19 1 B244 B244 20 1 B245 B245 21 1 B246 B246 22 1 B247 B247 23 1 B248 B248 24 1 B249 B249 25 1 B250 B250 26 1 B251 B251 27 1 B252 B252 28 1 B253 B253 29 1 B254 B254 30 1 B255 B255 31 1 MPCBB2_VCTR8 MPCBB2_VCTR8 MPCBBx vector register 0x120 0x20 read-write 0xFFFFFFFF B256 B256 0 1 B257 B257 1 1 B258 B258 2 1 B259 B259 3 1 B260 B260 4 1 B261 B261 5 1 B262 B262 6 1 B263 B263 7 1 B264 B264 8 1 B265 B265 9 1 B266 B266 10 1 B267 B267 11 1 B268 B268 12 1 B269 B269 13 1 B270 B270 14 1 B271 B271 15 1 B272 B272 16 1 B273 B273 17 1 B274 B274 18 1 B275 B275 19 1 B276 B276 20 1 B277 B277 21 1 B278 B278 22 1 B279 B279 23 1 B280 B280 24 1 B281 B281 25 1 B282 B282 26 1 B283 B283 27 1 B284 B284 28 1 B285 B285 29 1 B286 B286 30 1 B287 B287 31 1 MPCBB2_VCTR9 MPCBB2_VCTR9 MPCBBx vector register 0x124 0x20 read-write 0xFFFFFFFF B288 B288 0 1 B289 B289 1 1 B290 B290 2 1 B291 B291 3 1 B292 B292 4 1 B293 B293 5 1 B294 B294 6 1 B295 B295 7 1 B296 B296 8 1 B297 B297 9 1 B298 B298 10 1 B299 B299 11 1 B300 B300 12 1 B301 B301 13 1 B302 B302 14 1 B303 B303 15 1 B304 B304 16 1 B305 B305 17 1 B306 B306 18 1 B307 B307 19 1 B308 B308 20 1 B309 B309 21 1 B310 B310 22 1 B311 B311 23 1 B312 B312 24 1 B313 B313 25 1 B314 B314 26 1 B315 B315 27 1 B316 B316 28 1 B317 B317 29 1 B318 B318 30 1 B319 B319 31 1 MPCBB2_VCTR10 MPCBB2_VCTR10 MPCBBx vector register 0x128 0x20 read-write 0xFFFFFFFF B320 B320 0 1 B321 B321 1 1 B322 B322 2 1 B323 B323 3 1 B324 B324 4 1 B325 B325 5 1 B326 B326 6 1 B327 B327 7 1 B328 B328 8 1 B329 B329 9 1 B330 B330 10 1 B331 B331 11 1 B332 B332 12 1 B333 B333 13 1 B334 B334 14 1 B335 B335 15 1 B336 B336 16 1 B337 B337 17 1 B338 B338 18 1 B339 B339 19 1 B340 B340 20 1 B341 B341 21 1 B342 B342 22 1 B343 B343 23 1 B344 B344 24 1 B345 B345 25 1 B346 B346 26 1 B347 B347 27 1 B348 B348 28 1 B349 B349 29 1 B350 B350 30 1 B351 B351 31 1 MPCBB2_VCTR11 MPCBB2_VCTR11 MPCBBx vector register 0x12C 0x20 read-write 0xFFFFFFFF B352 B352 0 1 B353 B353 1 1 B354 B354 2 1 B355 B355 3 1 B356 B356 4 1 B357 B357 5 1 B358 B358 6 1 B359 B359 7 1 B360 B360 8 1 B361 B361 9 1 B362 B362 10 1 B363 B363 11 1 B364 B364 12 1 B365 B365 13 1 B366 B366 14 1 B367 B367 15 1 B368 B368 16 1 B369 B369 17 1 B370 B370 18 1 B371 B371 19 1 B372 B372 20 1 B373 B373 21 1 B374 B374 22 1 B375 B375 23 1 B376 B376 24 1 B377 B377 25 1 B378 B378 26 1 B379 B379 27 1 B380 B380 28 1 B381 B381 29 1 B382 B382 30 1 B383 B383 31 1 MPCBB2_VCTR12 MPCBB2_VCTR12 MPCBBx vector register 0x130 0x20 read-write 0xFFFFFFFF B384 B384 0 1 B385 B385 1 1 B386 B386 2 1 B387 B387 3 1 B388 B388 4 1 B389 B389 5 1 B390 B390 6 1 B391 B391 7 1 B392 B392 8 1 B393 B393 9 1 B394 B394 10 1 B395 B395 11 1 B396 B396 12 1 B397 B397 13 1 B398 B398 14 1 B399 B399 15 1 B400 B400 16 1 B401 B401 17 1 B402 B402 18 1 B403 B403 19 1 B404 B404 20 1 B405 B405 21 1 B406 B406 22 1 B407 B407 23 1 B408 B408 24 1 B409 B409 25 1 B410 B410 26 1 B411 B411 27 1 B412 B412 28 1 B413 B413 29 1 B414 B414 30 1 B415 B415 31 1 MPCBB2_VCTR13 MPCBB2_VCTR13 MPCBBx vector register 0x134 0x20 read-write 0xFFFFFFFF B416 B416 0 1 B417 B417 1 1 B418 B418 2 1 B419 B419 3 1 B420 B420 4 1 B421 B421 5 1 B422 B422 6 1 B423 B423 7 1 B424 B424 8 1 B425 B425 9 1 B426 B426 10 1 B427 B427 11 1 B428 B428 12 1 B429 B429 13 1 B430 B430 14 1 B431 B431 15 1 B432 B432 16 1 B433 B433 17 1 B434 B434 18 1 B435 B435 19 1 B436 B436 20 1 B437 B437 21 1 B438 B438 22 1 B439 B439 23 1 B440 B440 24 1 B441 B441 25 1 B442 B442 26 1 B443 B443 27 1 B444 B444 28 1 B445 B445 29 1 B446 B446 30 1 B447 B447 31 1 MPCBB2_VCTR14 MPCBB2_VCTR14 MPCBBx vector register 0x138 0x20 read-write 0xFFFFFFFF B448 B448 0 1 B449 B449 1 1 B450 B450 2 1 B451 B451 3 1 B452 B452 4 1 B453 B453 5 1 B454 B454 6 1 B455 B455 7 1 B456 B456 8 1 B457 B457 9 1 B458 B458 10 1 B459 B459 11 1 B460 B460 12 1 B461 B461 13 1 B462 B462 14 1 B463 B463 15 1 B464 B464 16 1 B465 B465 17 1 B466 B466 18 1 B467 B467 19 1 B468 B468 20 1 B469 B469 21 1 B470 B470 22 1 B471 B471 23 1 B472 B472 24 1 B473 B473 25 1 B474 B474 26 1 B475 B475 27 1 B476 B476 28 1 B477 B477 29 1 B478 B478 30 1 B479 B479 31 1 MPCBB2_VCTR15 MPCBB2_VCTR15 MPCBBx vector register 0x13C 0x20 read-write 0xFFFFFFFF B480 B480 0 1 B481 B481 1 1 B482 B482 2 1 B483 B483 3 1 B484 B484 4 1 B485 B485 5 1 B486 B486 6 1 B487 B487 7 1 B488 B488 8 1 B489 B489 9 1 B490 B490 10 1 B491 B491 11 1 B492 B492 12 1 B493 B493 13 1 B494 B494 14 1 B495 B495 15 1 B496 B496 16 1 B497 B497 17 1 B498 B498 18 1 B499 B499 19 1 B500 B500 20 1 B501 B501 21 1 B502 B502 22 1 B503 B503 23 1 B504 B504 24 1 B505 B505 25 1 B506 B506 26 1 B507 B507 27 1 B508 B508 28 1 B509 B509 29 1 B510 B510 30 1 B511 B511 31 1 MPCBB2_VCTR16 MPCBB2_VCTR16 MPCBBx vector register 0x140 0x20 read-write 0xFFFFFFFF B512 B512 0 1 B513 B513 1 1 B514 B514 2 1 B515 B515 3 1 B516 B516 4 1 B517 B517 5 1 B518 B518 6 1 B519 B519 7 1 B520 B520 8 1 B521 B521 9 1 B522 B522 10 1 B523 B523 11 1 B524 B524 12 1 B525 B525 13 1 B526 B526 14 1 B527 B527 15 1 B528 B528 16 1 B529 B529 17 1 B530 B530 18 1 B531 B531 19 1 B532 B532 20 1 B533 B533 21 1 B534 B534 22 1 B535 B535 23 1 B536 B536 24 1 B537 B537 25 1 B538 B538 26 1 B539 B539 27 1 B540 B540 28 1 B541 B541 29 1 B542 B542 30 1 B543 B543 31 1 MPCBB2_VCTR17 MPCBB2_VCTR17 MPCBBx vector register 0x144 0x20 read-write 0xFFFFFFFF B544 B544 0 1 B545 B545 1 1 B546 B546 2 1 B547 B547 3 1 B548 B548 4 1 B549 B549 5 1 B550 B550 6 1 B551 B551 7 1 B552 B552 8 1 B553 B553 9 1 B554 B554 10 1 B555 B555 11 1 B556 B556 12 1 B557 B557 13 1 B558 B558 14 1 B559 B559 15 1 B560 B560 16 1 B561 B561 17 1 B562 B562 18 1 B563 B563 19 1 B564 B564 20 1 B565 B565 21 1 B566 B566 22 1 B567 B567 23 1 B568 B568 24 1 B569 B569 25 1 B570 B570 26 1 B571 B571 27 1 B572 B572 28 1 B573 B573 29 1 B574 B574 30 1 B575 B575 31 1 MPCBB2_VCTR18 MPCBB2_VCTR18 MPCBBx vector register 0x148 0x20 read-write 0xFFFFFFFF B576 B576 0 1 B577 B577 1 1 B578 B578 2 1 B579 B579 3 1 B580 B580 4 1 B581 B581 5 1 B582 B582 6 1 B583 B583 7 1 B584 B584 8 1 B585 B585 9 1 B586 B586 10 1 B587 B587 11 1 B588 B588 12 1 B589 B589 13 1 B590 B590 14 1 B591 B591 15 1 B592 B592 16 1 B593 B593 17 1 B594 B594 18 1 B595 B595 19 1 B596 B596 20 1 B597 B597 21 1 B598 B598 22 1 B599 B599 23 1 B600 B600 24 1 B601 B601 25 1 B602 B602 26 1 B603 B603 27 1 B604 B604 28 1 B605 B605 29 1 B606 B606 30 1 B607 B607 31 1 MPCBB2_VCTR19 MPCBB2_VCTR19 MPCBBx vector register 0x14C 0x20 read-write 0xFFFFFFFF B608 B608 0 1 B609 B609 1 1 B610 B610 2 1 B611 B611 3 1 B612 B612 4 1 B613 B613 5 1 B614 B614 6 1 B615 B615 7 1 B616 B616 8 1 B617 B617 9 1 B618 B618 10 1 B619 B619 11 1 B620 B620 12 1 B621 B621 13 1 B622 B622 14 1 B623 B623 15 1 B624 B624 16 1 B625 B625 17 1 B626 B626 18 1 B627 B627 19 1 B628 B628 20 1 B629 B629 21 1 B630 B630 22 1 B631 B631 23 1 B632 B632 24 1 B633 B633 25 1 B634 B634 26 1 B635 B635 27 1 B636 B636 28 1 B637 B637 29 1 B638 B638 30 1 B639 B639 31 1 MPCBB2_VCTR20 MPCBB2_VCTR20 MPCBBx vector register 0x150 0x20 read-write 0xFFFFFFFF B640 B640 0 1 B641 B641 1 1 B642 B642 2 1 B643 B643 3 1 B644 B644 4 1 B645 B645 5 1 B646 B646 6 1 B647 B647 7 1 B648 B648 8 1 B649 B649 9 1 B650 B650 10 1 B651 B651 11 1 B652 B652 12 1 B653 B653 13 1 B654 B654 14 1 B655 B655 15 1 B656 B656 16 1 B657 B657 17 1 B658 B658 18 1 B659 B659 19 1 B660 B660 20 1 B661 B661 21 1 B662 B662 22 1 B663 B663 23 1 B664 B664 24 1 B665 B665 25 1 B666 B666 26 1 B667 B667 27 1 B668 B668 28 1 B669 B669 29 1 B670 B670 30 1 B671 B671 31 1 MPCBB2_VCTR21 MPCBB2_VCTR21 MPCBBx vector register 0x154 0x20 read-write 0xFFFFFFFF B672 B672 0 1 B673 B673 1 1 B674 B674 2 1 B675 B675 3 1 B676 B676 4 1 B677 B677 5 1 B678 B678 6 1 B679 B679 7 1 B680 B680 8 1 B681 B681 9 1 B682 B682 10 1 B683 B683 11 1 B684 B684 12 1 B685 B685 13 1 B686 B686 14 1 B687 B687 15 1 B688 B688 16 1 B689 B689 17 1 B690 B690 18 1 B691 B691 19 1 B692 B692 20 1 B693 B693 21 1 B694 B694 22 1 B695 B695 23 1 B696 B696 24 1 B697 B697 25 1 B698 B698 26 1 B699 B699 27 1 B700 B700 28 1 B701 B701 29 1 B702 B702 30 1 B703 B703 31 1 MPCBB2_VCTR22 MPCBB2_VCTR22 MPCBBx vector register 0x158 0x20 read-write 0xFFFFFFFF B704 B704 0 1 B705 B705 1 1 B706 B706 2 1 B707 B707 3 1 B708 B708 4 1 B709 B709 5 1 B710 B710 6 1 B711 B711 7 1 B712 B712 8 1 B713 B713 9 1 B714 B714 10 1 B715 B715 11 1 B716 B716 12 1 B717 B717 13 1 B718 B718 14 1 B719 B719 15 1 B720 B720 16 1 B721 B721 17 1 B722 B722 18 1 B723 B723 19 1 B724 B724 20 1 B725 B725 21 1 B726 B726 22 1 B727 B727 23 1 B728 B728 24 1 B729 B729 25 1 B730 B730 26 1 B731 B731 27 1 B732 B732 28 1 B733 B733 29 1 B734 B734 30 1 B735 B735 31 1 MPCBB2_VCTR23 MPCBB2_VCTR23 MPCBBx vector register 0x15C 0x20 read-write 0xFFFFFFFF B736 B736 0 1 B737 B737 1 1 B738 B738 2 1 B739 B739 3 1 B740 B740 4 1 B741 B741 5 1 B742 B742 6 1 B743 B743 7 1 B744 B744 8 1 B745 B745 9 1 B746 B746 10 1 B747 B747 11 1 B748 B748 12 1 B749 B749 13 1 B750 B750 14 1 B751 B751 15 1 B752 B752 16 1 B753 B753 17 1 B754 B754 18 1 B755 B755 19 1 B756 B756 20 1 B757 B757 21 1 B758 B758 22 1 B759 B759 23 1 B760 B760 24 1 B761 B761 25 1 B762 B762 26 1 B763 B763 27 1 B764 B764 28 1 B765 B765 29 1 B766 B766 30 1 B767 B767 31 1 MPCBB2_VCTR24 MPCBB2_VCTR24 MPCBBx vector register 0x160 0x20 read-write 0xFFFFFFFF B768 B768 0 1 B769 B769 1 1 B770 B770 2 1 B771 B771 3 1 B772 B772 4 1 B773 B773 5 1 B774 B774 6 1 B775 B775 7 1 B776 B776 8 1 B777 B777 9 1 B778 B778 10 1 B779 B779 11 1 B780 B780 12 1 B781 B781 13 1 B782 B782 14 1 B783 B783 15 1 B784 B784 16 1 B785 B785 17 1 B786 B786 18 1 B787 B787 19 1 B788 B788 20 1 B789 B789 21 1 B790 B790 22 1 B791 B791 23 1 B792 B792 24 1 B793 B793 25 1 B794 B794 26 1 B795 B795 27 1 B796 B796 28 1 B797 B797 29 1 B798 B798 30 1 B799 B799 31 1 MPCBB2_VCTR25 MPCBB2_VCTR25 MPCBBx vector register 0x164 0x20 read-write 0xFFFFFFFF B800 B800 0 1 B801 B801 1 1 B802 B802 2 1 B803 B803 3 1 B804 B804 4 1 B805 B805 5 1 B806 B806 6 1 B807 B807 7 1 B808 B808 8 1 B809 B809 9 1 B810 B810 10 1 B811 B811 11 1 B812 B812 12 1 B813 B813 13 1 B814 B814 14 1 B815 B815 15 1 B816 B816 16 1 B817 B817 17 1 B818 B818 18 1 B819 B819 19 1 B820 B820 20 1 B821 B821 21 1 B822 B822 22 1 B823 B823 23 1 B824 B824 24 1 B825 B825 25 1 B826 B826 26 1 B827 B827 27 1 B828 B828 28 1 B829 B829 29 1 B830 B830 30 1 B831 B831 31 1 MPCBB2_VCTR26 MPCBB2_VCTR26 MPCBBx vector register 0x168 0x20 read-write 0xFFFFFFFF B832 B832 0 1 B833 B833 1 1 B834 B834 2 1 B835 B835 3 1 B836 B836 4 1 B837 B837 5 1 B838 B838 6 1 B839 B839 7 1 B840 B840 8 1 B841 B841 9 1 B842 B842 10 1 B843 B843 11 1 B844 B844 12 1 B845 B845 13 1 B846 B846 14 1 B847 B847 15 1 B848 B848 16 1 B849 B849 17 1 B850 B850 18 1 B851 B851 19 1 B852 B852 20 1 B853 B853 21 1 B854 B854 22 1 B855 B855 23 1 B856 B856 24 1 B857 B857 25 1 B858 B858 26 1 B859 B859 27 1 B860 B860 28 1 B861 B861 29 1 B862 B862 30 1 B863 B863 31 1 MPCBB2_VCTR27 MPCBB2_VCTR27 MPCBBx vector register 0x16C 0x20 read-write 0xFFFFFFFF B864 B864 0 1 B865 B865 1 1 B866 B866 2 1 B867 B867 3 1 B868 B868 4 1 B869 B869 5 1 B870 B870 6 1 B871 B871 7 1 B872 B872 8 1 B873 B873 9 1 B874 B874 10 1 B875 B875 11 1 B876 B876 12 1 B877 B877 13 1 B878 B878 14 1 B879 B879 15 1 B880 B880 16 1 B881 B881 17 1 B882 B882 18 1 B883 B883 19 1 B884 B884 20 1 B885 B885 21 1 B886 B886 22 1 B887 B887 23 1 B888 B888 24 1 B889 B889 25 1 B890 B890 26 1 B891 B891 27 1 B892 B892 28 1 B893 B893 29 1 B894 B894 30 1 B895 B895 31 1 MPCBB2_VCTR28 MPCBB2_VCTR28 MPCBBx vector register 0x170 0x20 read-write 0xFFFFFFFF B896 B896 0 1 B897 B897 1 1 B898 B898 2 1 B899 B899 3 1 B900 B900 4 1 B901 B901 5 1 B902 B902 6 1 B903 B903 7 1 B904 B904 8 1 B905 B905 9 1 B906 B906 10 1 B907 B907 11 1 B908 B908 12 1 B909 B909 13 1 B910 B910 14 1 B911 B911 15 1 B912 B912 16 1 B913 B913 17 1 B914 B914 18 1 B915 B915 19 1 B916 B916 20 1 B917 B917 21 1 B918 B918 22 1 B919 B919 23 1 B920 B920 24 1 B921 B921 25 1 B922 B922 26 1 B923 B923 27 1 B924 B924 28 1 B925 B925 29 1 B926 B926 30 1 B927 B927 31 1 MPCBB2_VCTR29 MPCBB2_VCTR29 MPCBBx vector register 0x174 0x20 read-write 0xFFFFFFFF B928 B928 0 1 B929 B929 1 1 B930 B930 2 1 B931 B931 3 1 B932 B932 4 1 B933 B933 5 1 B934 B934 6 1 B935 B935 7 1 B936 B936 8 1 B937 B937 9 1 B938 B938 10 1 B939 B939 11 1 B940 B940 12 1 B941 B941 13 1 B942 B942 14 1 B943 B943 15 1 B944 B944 16 1 B945 B945 17 1 B946 B946 18 1 B947 B947 19 1 B948 B948 20 1 B949 B949 21 1 B950 B950 22 1 B951 B951 23 1 B952 B952 24 1 B953 B953 25 1 B954 B954 26 1 B955 B955 27 1 B956 B956 28 1 B957 B957 29 1 B958 B958 30 1 B959 B959 31 1 MPCBB2_VCTR30 MPCBB2_VCTR30 MPCBBx vector register 0x178 0x20 read-write 0xFFFFFFFF B960 B960 0 1 B961 B961 1 1 B962 B962 2 1 B963 B963 3 1 B964 B964 4 1 B965 B965 5 1 B966 B966 6 1 B967 B967 7 1 B968 B968 8 1 B969 B969 9 1 B970 B970 10 1 B971 B971 11 1 B972 B972 12 1 B973 B973 13 1 B974 B974 14 1 B975 B975 15 1 B976 B976 16 1 B977 B977 17 1 B978 B978 18 1 B979 B979 19 1 B980 B980 20 1 B981 B981 21 1 B982 B982 22 1 B983 B983 23 1 B984 B984 24 1 B985 B985 25 1 B986 B986 26 1 B987 B987 27 1 B988 B988 28 1 B989 B989 29 1 B990 B990 30 1 B991 B991 31 1 MPCBB2_VCTR31 MPCBB2_VCTR31 MPCBBx vector register 0x17C 0x20 read-write 0xFFFFFFFF B992 B992 0 1 B993 B993 1 1 B994 B994 2 1 B995 B995 3 1 B996 B996 4 1 B997 B997 5 1 B998 B998 6 1 B999 B999 7 1 B1000 B1000 8 1 B1001 B1001 9 1 B1002 B1002 10 1 B1003 B1003 11 1 B1004 B1004 12 1 B1005 B1005 13 1 B1006 B1006 14 1 B1007 B1007 15 1 B1008 B1008 16 1 B1009 B1009 17 1 B1010 B1010 18 1 B1011 B1011 19 1 B1012 B1012 20 1 B1013 B1013 21 1 B1014 B1014 22 1 B1015 B1015 23 1 B1016 B1016 24 1 B1017 B1017 25 1 B1018 B1018 26 1 B1019 B1019 27 1 B1020 B1020 28 1 B1021 B1021 29 1 B1022 B1022 30 1 B1023 B1023 31 1 MPCBB2_VCTR32 MPCBB2_VCTR32 MPCBBx vector register 0x180 0x20 read-write 0xFFFFFFFF B1024 B1024 0 1 B1025 B1025 1 1 B1026 B1026 2 1 B1027 B1027 3 1 B1028 B1028 4 1 B1029 B1029 5 1 B1030 B1030 6 1 B1031 B1031 7 1 B1032 B1032 8 1 B1033 B1033 9 1 B1034 B1034 10 1 B1035 B1035 11 1 B1036 B1036 12 1 B1037 B1037 13 1 B1038 B1038 14 1 B1039 B1039 15 1 B1040 B1040 16 1 B1041 B1041 17 1 B1042 B1042 18 1 B1043 B1043 19 1 B1044 B1044 20 1 B1045 B1045 21 1 B1046 B1046 22 1 B1047 B1047 23 1 B1048 B1048 24 1 B1049 B1049 25 1 B1050 B1050 26 1 B1051 B1051 27 1 B1052 B1052 28 1 B1053 B1053 29 1 B1054 B1054 30 1 B1055 B1055 31 1 MPCBB2_VCTR33 MPCBB2_VCTR33 MPCBBx vector register 0x184 0x20 read-write 0xFFFFFFFF B1056 B1056 0 1 B1057 B1057 1 1 B1058 B1058 2 1 B1059 B1059 3 1 B1060 B1060 4 1 B1061 B1061 5 1 B1062 B1062 6 1 B1063 B1063 7 1 B1064 B1064 8 1 B1065 B1065 9 1 B1066 B1066 10 1 B1067 B1067 11 1 B1068 B1068 12 1 B1069 B1069 13 1 B1070 B1070 14 1 B1071 B1071 15 1 B1072 B1072 16 1 B1073 B1073 17 1 B1074 B1074 18 1 B1075 B1075 19 1 B1076 B1076 20 1 B1077 B1077 21 1 B1078 B1078 22 1 B1079 B1079 23 1 B1080 B1080 24 1 B1081 B1081 25 1 B1082 B1082 26 1 B1083 B1083 27 1 B1084 B1084 28 1 B1085 B1085 29 1 B1086 B1086 30 1 B1087 B1087 31 1 MPCBB2_VCTR34 MPCBB2_VCTR34 MPCBBx vector register 0x188 0x20 read-write 0xFFFFFFFF B1088 B1088 0 1 B1089 B1089 1 1 B1090 B1090 2 1 B1091 B1091 3 1 B1092 B1092 4 1 B1093 B1093 5 1 B1094 B1094 6 1 B1095 B1095 7 1 B1096 B1096 8 1 B1097 B1097 9 1 B1098 B1098 10 1 B1099 B1099 11 1 B1100 B1100 12 1 B1101 B1101 13 1 B1102 B1102 14 1 B1103 B1103 15 1 B1104 B1104 16 1 B1105 B1105 17 1 B1106 B1106 18 1 B1107 B1107 19 1 B1108 B1108 20 1 B1109 B1109 21 1 B1110 B1110 22 1 B1111 B1111 23 1 B1112 B1112 24 1 B1113 B1113 25 1 B1114 B1114 26 1 B1115 B1115 27 1 B1116 B1116 28 1 B1117 B1117 29 1 B1118 B1118 30 1 B1119 B1119 31 1 MPCBB2_VCTR35 MPCBB2_VCTR35 MPCBBx vector register 0x18C 0x20 read-write 0xFFFFFFFF B1120 B1120 0 1 B1121 B1121 1 1 B1122 B1122 2 1 B1123 B1123 3 1 B1124 B1124 4 1 B1125 B1125 5 1 B1126 B1126 6 1 B1127 B1127 7 1 B1128 B1128 8 1 B1129 B1129 9 1 B1130 B1130 10 1 B1131 B1131 11 1 B1132 B1132 12 1 B1133 B1133 13 1 B1134 B1134 14 1 B1135 B1135 15 1 B1136 B1136 16 1 B1137 B1137 17 1 B1138 B1138 18 1 B1139 B1139 19 1 B1140 B1140 20 1 B1141 B1141 21 1 B1142 B1142 22 1 B1143 B1143 23 1 B1144 B1144 24 1 B1145 B1145 25 1 B1146 B1146 26 1 B1147 B1147 27 1 B1148 B1148 28 1 B1149 B1149 29 1 B1150 B1150 30 1 B1151 B1151 31 1 MPCBB2_VCTR36 MPCBB2_VCTR36 MPCBBx vector register 0x190 0x20 read-write 0xFFFFFFFF B1152 B1152 0 1 B1153 B1153 1 1 B1154 B1154 2 1 B1155 B1155 3 1 B1156 B1156 4 1 B1157 B1157 5 1 B1158 B1158 6 1 B1159 B1159 7 1 B1160 B1160 8 1 B1161 B1161 9 1 B1162 B1162 10 1 B1163 B1163 11 1 B1164 B1164 12 1 B1165 B1165 13 1 B1166 B1166 14 1 B1167 B1167 15 1 B1168 B1168 16 1 B1169 B1169 17 1 B1170 B1170 18 1 B1171 B1171 19 1 B1172 B1172 20 1 B1173 B1173 21 1 B1174 B1174 22 1 B1175 B1175 23 1 B1176 B1176 24 1 B1177 B1177 25 1 B1178 B1178 26 1 B1179 B1179 27 1 B1180 B1180 28 1 B1181 B1181 29 1 B1182 B1182 30 1 B1183 B1183 31 1 MPCBB2_VCTR37 MPCBB2_VCTR37 MPCBBx vector register 0x194 0x20 read-write 0xFFFFFFFF B1184 B1184 0 1 B1185 B1185 1 1 B1186 B1186 2 1 B1187 B1187 3 1 B1188 B1188 4 1 B1189 B1189 5 1 B1190 B1190 6 1 B1191 B1191 7 1 B1192 B1192 8 1 B1193 B1193 9 1 B1194 B1194 10 1 B1195 B1195 11 1 B1196 B1196 12 1 B1197 B1197 13 1 B1198 B1198 14 1 B1199 B1199 15 1 B1200 B1200 16 1 B1201 B1201 17 1 B1202 B1202 18 1 B1203 B1203 19 1 B1204 B1204 20 1 B1205 B1205 21 1 B1206 B1206 22 1 B1207 B1207 23 1 B1208 B1208 24 1 B1209 B1209 25 1 B1210 B1210 26 1 B1211 B1211 27 1 B1212 B1212 28 1 B1213 B1213 29 1 B1214 B1214 30 1 B1215 B1215 31 1 MPCBB2_VCTR38 MPCBB2_VCTR38 MPCBBx vector register 0x198 0x20 read-write 0xFFFFFFFF B1216 B1216 0 1 B1217 B1217 1 1 B1218 B1218 2 1 B1219 B1219 3 1 B1220 B1220 4 1 B1221 B1221 5 1 B1222 B1222 6 1 B1223 B1223 7 1 B1224 B1224 8 1 B1225 B1225 9 1 B1226 B1226 10 1 B1227 B1227 11 1 B1228 B1228 12 1 B1229 B1229 13 1 B1230 B1230 14 1 B1231 B1231 15 1 B1232 B1232 16 1 B1233 B1233 17 1 B1234 B1234 18 1 B1235 B1235 19 1 B1236 B1236 20 1 B1237 B1237 21 1 B1238 B1238 22 1 B1239 B1239 23 1 B1240 B1240 24 1 B1241 B1241 25 1 B1242 B1242 26 1 B1243 B1243 27 1 B1244 B1244 28 1 B1245 B1245 29 1 B1246 B1246 30 1 B1247 B1247 31 1 MPCBB2_VCTR39 MPCBB2_VCTR39 MPCBBx vector register 0x19C 0x20 read-write 0xFFFFFFFF B1248 B1248 0 1 B1249 B1249 1 1 B1250 B1250 2 1 B1251 B1251 3 1 B1252 B1252 4 1 B1253 B1253 5 1 B1254 B1254 6 1 B1255 B1255 7 1 B1256 B1256 8 1 B1257 B1257 9 1 B1258 B1258 10 1 B1259 B1259 11 1 B1260 B1260 12 1 B1261 B1261 13 1 B1262 B1262 14 1 B1263 B1263 15 1 B1264 B1264 16 1 B1265 B1265 17 1 B1266 B1266 18 1 B1267 B1267 19 1 B1268 B1268 20 1 B1269 B1269 21 1 B1270 B1270 22 1 B1271 B1271 23 1 B1272 B1272 24 1 B1273 B1273 25 1 B1274 B1274 26 1 B1275 B1275 27 1 B1276 B1276 28 1 B1277 B1277 29 1 B1278 B1278 30 1 B1279 B1279 31 1 MPCBB2_VCTR40 MPCBB2_VCTR40 MPCBBx vector register 0x1A0 0x20 read-write 0xFFFFFFFF B1280 B1280 0 1 B1281 B1281 1 1 B1282 B1282 2 1 B1283 B1283 3 1 B1284 B1284 4 1 B1285 B1285 5 1 B1286 B1286 6 1 B1287 B1287 7 1 B1288 B1288 8 1 B1289 B1289 9 1 B1290 B1290 10 1 B1291 B1291 11 1 B1292 B1292 12 1 B1293 B1293 13 1 B1294 B1294 14 1 B1295 B1295 15 1 B1296 B1296 16 1 B1297 B1297 17 1 B1298 B1298 18 1 B1299 B1299 19 1 B1300 B1300 20 1 B1301 B1301 21 1 B1302 B1302 22 1 B1303 B1303 23 1 B1304 B1304 24 1 B1305 B1305 25 1 B1306 B1306 26 1 B1307 B1307 27 1 B1308 B1308 28 1 B1309 B1309 29 1 B1310 B1310 30 1 B1311 B1311 31 1 MPCBB2_VCTR41 MPCBB2_VCTR41 MPCBBx vector register 0x1A4 0x20 read-write 0xFFFFFFFF B1312 B1312 0 1 B1313 B1313 1 1 B1314 B1314 2 1 B1315 B1315 3 1 B1316 B1316 4 1 B1317 B1317 5 1 B1318 B1318 6 1 B1319 B1319 7 1 B1320 B1320 8 1 B1321 B1321 9 1 B1322 B1322 10 1 B1323 B1323 11 1 B1324 B1324 12 1 B1325 B1325 13 1 B1326 B1326 14 1 B1327 B1327 15 1 B1328 B1328 16 1 B1329 B1329 17 1 B1330 B1330 18 1 B1331 B1331 19 1 B1332 B1332 20 1 B1333 B1333 21 1 B1334 B1334 22 1 B1335 B1335 23 1 B1336 B1336 24 1 B1337 B1337 25 1 B1338 B1338 26 1 B1339 B1339 27 1 B1340 B1340 28 1 B1341 B1341 29 1 B1342 B1342 30 1 B1343 B1343 31 1 MPCBB2_VCTR42 MPCBB2_VCTR42 MPCBBx vector register 0x1A8 0x20 read-write 0xFFFFFFFF B1344 B1344 0 1 B1345 B1345 1 1 B1346 B1346 2 1 B1347 B1347 3 1 B1348 B1348 4 1 B1349 B1349 5 1 B1350 B1350 6 1 B1351 B1351 7 1 B1352 B1352 8 1 B1353 B1353 9 1 B1354 B1354 10 1 B1355 B1355 11 1 B1356 B1356 12 1 B1357 B1357 13 1 B1358 B1358 14 1 B1359 B1359 15 1 B1360 B1360 16 1 B1361 B1361 17 1 B1362 B1362 18 1 B1363 B1363 19 1 B1364 B1364 20 1 B1365 B1365 21 1 B1366 B1366 22 1 B1367 B1367 23 1 B1368 B1368 24 1 B1369 B1369 25 1 B1370 B1370 26 1 B1371 B1371 27 1 B1372 B1372 28 1 B1373 B1373 29 1 B1374 B1374 30 1 B1375 B1375 31 1 MPCBB2_VCTR43 MPCBB2_VCTR43 MPCBBx vector register 0x1AC 0x20 read-write 0xFFFFFFFF B1376 B1376 0 1 B1377 B1377 1 1 B1378 B1378 2 1 B1379 B1379 3 1 B1380 B1380 4 1 B1381 B1381 5 1 B1382 B1382 6 1 B1383 B1383 7 1 B1384 B1384 8 1 B1385 B1385 9 1 B1386 B1386 10 1 B1387 B1387 11 1 B1388 B1388 12 1 B1389 B1389 13 1 B1390 B1390 14 1 B1391 B1391 15 1 B1392 B1392 16 1 B1393 B1393 17 1 B1394 B1394 18 1 B1395 B1395 19 1 B1396 B1396 20 1 B1397 B1397 21 1 B1398 B1398 22 1 B1399 B1399 23 1 B1400 B1400 24 1 B1401 B1401 25 1 B1402 B1402 26 1 B1403 B1403 27 1 B1404 B1404 28 1 B1405 B1405 29 1 B1406 B1406 30 1 B1407 B1407 31 1 MPCBB2_VCTR44 MPCBB2_VCTR44 MPCBBx vector register 0x1B0 0x20 read-write 0xFFFFFFFF B1408 B1408 0 1 B1409 B1409 1 1 B1410 B1410 2 1 B1411 B1411 3 1 B1412 B1412 4 1 B1413 B1413 5 1 B1414 B1414 6 1 B1415 B1415 7 1 B1416 B1416 8 1 B1417 B1417 9 1 B1418 B1418 10 1 B1419 B1419 11 1 B1420 B1420 12 1 B1421 B1421 13 1 B1422 B1422 14 1 B1423 B1423 15 1 B1424 B1424 16 1 B1425 B1425 17 1 B1426 B1426 18 1 B1427 B1427 19 1 B1428 B1428 20 1 B1429 B1429 21 1 B1430 B1430 22 1 B1431 B1431 23 1 B1432 B1432 24 1 B1433 B1433 25 1 B1434 B1434 26 1 B1435 B1435 27 1 B1436 B1436 28 1 B1437 B1437 29 1 B1438 B1438 30 1 B1439 B1439 31 1 MPCBB2_VCTR45 MPCBB2_VCTR45 MPCBBx vector register 0x1B4 0x20 read-write 0xFFFFFFFF B1440 B1440 0 1 B1441 B1441 1 1 B1442 B1442 2 1 B1443 B1443 3 1 B1444 B1444 4 1 B1445 B1445 5 1 B1446 B1446 6 1 B1447 B1447 7 1 B1448 B1448 8 1 B1449 B1449 9 1 B1450 B1450 10 1 B1451 B1451 11 1 B1452 B1452 12 1 B1453 B1453 13 1 B1454 B1454 14 1 B1455 B1455 15 1 B1456 B1456 16 1 B1457 B1457 17 1 B1458 B1458 18 1 B1459 B1459 19 1 B1460 B1460 20 1 B1461 B1461 21 1 B1462 B1462 22 1 B1463 B1463 23 1 B1464 B1464 24 1 B1465 B1465 25 1 B1466 B1466 26 1 B1467 B1467 27 1 B1468 B1468 28 1 B1469 B1469 29 1 B1470 B1470 30 1 B1471 B1471 31 1 MPCBB2_VCTR46 MPCBB2_VCTR46 MPCBBx vector register 0x1B8 0x20 read-write 0xFFFFFFFF B1472 B1472 0 1 B1473 B1473 1 1 B1474 B1474 2 1 B1475 B1475 3 1 B1476 B1476 4 1 B1477 B1477 5 1 B1478 B1478 6 1 B1479 B1479 7 1 B1480 B1480 8 1 B1481 B1481 9 1 B1482 B1482 10 1 B1483 B1483 11 1 B1484 B1484 12 1 B1485 B1485 13 1 B1486 B1486 14 1 B1487 B1487 15 1 B1488 B1488 16 1 B1489 B1489 17 1 B1490 B1490 18 1 B1491 B1491 19 1 B1492 B1492 20 1 B1493 B1493 21 1 B1494 B1494 22 1 B1495 B1495 23 1 B1496 B1496 24 1 B1497 B1497 25 1 B1498 B1498 26 1 B1499 B1499 27 1 B1500 B1500 28 1 B1501 B1501 29 1 B1502 B1502 30 1 B1503 B1503 31 1 MPCBB2_VCTR47 MPCBB2_VCTR47 MPCBBx vector register 0x1BC 0x20 read-write 0xFFFFFFFF B1504 B1504 0 1 B1505 B1505 1 1 B1506 B1506 2 1 B1507 B1507 3 1 B1508 B1508 4 1 B1509 B1509 5 1 B1510 B1510 6 1 B1511 B1511 7 1 B1512 B1512 8 1 B1513 B1513 9 1 B1514 B1514 10 1 B1515 B1515 11 1 B1516 B1516 12 1 B1517 B1517 13 1 B1518 B1518 14 1 B1519 B1519 15 1 B1520 B1520 16 1 B1521 B1521 17 1 B1522 B1522 18 1 B1523 B1523 19 1 B1524 B1524 20 1 B1525 B1525 21 1 B1526 B1526 22 1 B1527 B1527 23 1 B1528 B1528 24 1 B1529 B1529 25 1 B1530 B1530 26 1 B1531 B1531 27 1 B1532 B1532 28 1 B1533 B1533 29 1 B1534 B1534 30 1 B1535 B1535 31 1 MPCBB2_VCTR48 MPCBB2_VCTR48 MPCBBx vector register 0x1C0 0x20 read-write 0xFFFFFFFF B1536 B1536 0 1 B1537 B1537 1 1 B1538 B1538 2 1 B1539 B1539 3 1 B1540 B1540 4 1 B1541 B1541 5 1 B1542 B1542 6 1 B1543 B1543 7 1 B1544 B1544 8 1 B1545 B1545 9 1 B1546 B1546 10 1 B1547 B1547 11 1 B1548 B1548 12 1 B1549 B1549 13 1 B1550 B1550 14 1 B1551 B1551 15 1 B1552 B1552 16 1 B1553 B1553 17 1 B1554 B1554 18 1 B1555 B1555 19 1 B1556 B1556 20 1 B1557 B1557 21 1 B1558 B1558 22 1 B1559 B1559 23 1 B1560 B1560 24 1 B1561 B1561 25 1 B1562 B1562 26 1 B1563 B1563 27 1 B1564 B1564 28 1 B1565 B1565 29 1 B1566 B1566 30 1 B1567 B1567 31 1 MPCBB2_VCTR49 MPCBB2_VCTR49 MPCBBx vector register 0x1C4 0x20 read-write 0xFFFFFFFF B1568 B1568 0 1 B1569 B1569 1 1 B1570 B1570 2 1 B1571 B1571 3 1 B1572 B1572 4 1 B1573 B1573 5 1 B1574 B1574 6 1 B1575 B1575 7 1 B1576 B1576 8 1 B1577 B1577 9 1 B1578 B1578 10 1 B1579 B1579 11 1 B1580 B1580 12 1 B1581 B1581 13 1 B1582 B1582 14 1 B1583 B1583 15 1 B1584 B1584 16 1 B1585 B1585 17 1 B1586 B1586 18 1 B1587 B1587 19 1 B1588 B1588 20 1 B1589 B1589 21 1 B1590 B1590 22 1 B1591 B1591 23 1 B1592 B1592 24 1 B1593 B1593 25 1 B1594 B1594 26 1 B1595 B1595 27 1 B1596 B1596 28 1 B1597 B1597 29 1 B1598 B1598 30 1 B1599 B1599 31 1 MPCBB2_VCTR50 MPCBB2_VCTR50 MPCBBx vector register 0x1C8 0x20 read-write 0xFFFFFFFF B1600 B1600 0 1 B1601 B1601 1 1 B1602 B1602 2 1 B1603 B1603 3 1 B1604 B1604 4 1 B1605 B1605 5 1 B1606 B1606 6 1 B1607 B1607 7 1 B1608 B1608 8 1 B1609 B1609 9 1 B1610 B1610 10 1 B1611 B1611 11 1 B1612 B1612 12 1 B1613 B1613 13 1 B1614 B1614 14 1 B1615 B1615 15 1 B1616 B1616 16 1 B1617 B1617 17 1 B1618 B1618 18 1 B1619 B1619 19 1 B1620 B1620 20 1 B1621 B1621 21 1 B1622 B1622 22 1 B1623 B1623 23 1 B1624 B1624 24 1 B1625 B1625 25 1 B1626 B1626 26 1 B1627 B1627 27 1 B1628 B1628 28 1 B1629 B1629 29 1 B1630 B1630 30 1 B1631 B1631 31 1 MPCBB2_VCTR51 MPCBB2_VCTR51 MPCBBx vector register 0x1CC 0x20 read-write 0xFFFFFFFF B1632 B1632 0 1 B1633 B1633 1 1 B1634 B1634 2 1 B1635 B1635 3 1 B1636 B1636 4 1 B1637 B1637 5 1 B1638 B1638 6 1 B1639 B1639 7 1 B1640 B1640 8 1 B1641 B1641 9 1 B1642 B1642 10 1 B1643 B1643 11 1 B1644 B1644 12 1 B1645 B1645 13 1 B1646 B1646 14 1 B1647 B1647 15 1 B1648 B1648 16 1 B1649 B1649 17 1 B1650 B1650 18 1 B1651 B1651 19 1 B1652 B1652 20 1 B1653 B1653 21 1 B1654 B1654 22 1 B1655 B1655 23 1 B1656 B1656 24 1 B1657 B1657 25 1 B1658 B1658 26 1 B1659 B1659 27 1 B1660 B1660 28 1 B1661 B1661 29 1 B1662 B1662 30 1 B1663 B1663 31 1 MPCBB2_VCTR52 MPCBB2_VCTR52 MPCBBx vector register 0x1D0 0x20 read-write 0xFFFFFFFF B1664 B1664 0 1 B1665 B1665 1 1 B1666 B1666 2 1 B1667 B1667 3 1 B1668 B1668 4 1 B1669 B1669 5 1 B1670 B1670 6 1 B1671 B1671 7 1 B1672 B1672 8 1 B1673 B1673 9 1 B1674 B1674 10 1 B1675 B1675 11 1 B1676 B1676 12 1 B1677 B1677 13 1 B1678 B1678 14 1 B1679 B1679 15 1 B1680 B1680 16 1 B1681 B1681 17 1 B1682 B1682 18 1 B1683 B1683 19 1 B1684 B1684 20 1 B1685 B1685 21 1 B1686 B1686 22 1 B1687 B1687 23 1 B1688 B1688 24 1 B1689 B1689 25 1 B1690 B1690 26 1 B1691 B1691 27 1 B1692 B1692 28 1 B1693 B1693 29 1 B1694 B1694 30 1 B1695 B1695 31 1 MPCBB2_VCTR53 MPCBB2_VCTR53 MPCBBx vector register 0x1D4 0x20 read-write 0xFFFFFFFF B1696 B1696 0 1 B1697 B1697 1 1 B1698 B1698 2 1 B1699 B1699 3 1 B1700 B1700 4 1 B1701 B1701 5 1 B1702 B1702 6 1 B1703 B1703 7 1 B1704 B1704 8 1 B1705 B1705 9 1 B1706 B1706 10 1 B1707 B1707 11 1 B1708 B1708 12 1 B1709 B1709 13 1 B1710 B1710 14 1 B1711 B1711 15 1 B1712 B1712 16 1 B1713 B1713 17 1 B1714 B1714 18 1 B1715 B1715 19 1 B1716 B1716 20 1 B1717 B1717 21 1 B1718 B1718 22 1 B1719 B1719 23 1 B1720 B1720 24 1 B1721 B1721 25 1 B1722 B1722 26 1 B1723 B1723 27 1 B1724 B1724 28 1 B1725 B1725 29 1 B1726 B1726 30 1 B1727 B1727 31 1 MPCBB2_VCTR54 MPCBB2_VCTR54 MPCBBx vector register 0x1D8 0x20 read-write 0xFFFFFFFF B1728 B1728 0 1 B1729 B1729 1 1 B1730 B1730 2 1 B1731 B1731 3 1 B1732 B1732 4 1 B1733 B1733 5 1 B1734 B1734 6 1 B1735 B1735 7 1 B1736 B1736 8 1 B1737 B1737 9 1 B1738 B1738 10 1 B1739 B1739 11 1 B1740 B1740 12 1 B1741 B1741 13 1 B1742 B1742 14 1 B1743 B1743 15 1 B1744 B1744 16 1 B1745 B1745 17 1 B1746 B1746 18 1 B1747 B1747 19 1 B1748 B1748 20 1 B1749 B1749 21 1 B1750 B1750 22 1 B1751 B1751 23 1 B1752 B1752 24 1 B1753 B1753 25 1 B1754 B1754 26 1 B1755 B1755 27 1 B1756 B1756 28 1 B1757 B1757 29 1 B1758 B1758 30 1 B1759 B1759 31 1 MPCBB2_VCTR55 MPCBB2_VCTR55 MPCBBx vector register 0x1DC 0x20 read-write 0xFFFFFFFF B1760 B1760 0 1 B1761 B1761 1 1 B1762 B1762 2 1 B1763 B1763 3 1 B1764 B1764 4 1 B1765 B1765 5 1 B1766 B1766 6 1 B1767 B1767 7 1 B1768 B1768 8 1 B1769 B1769 9 1 B1770 B1770 10 1 B1771 B1771 11 1 B1772 B1772 12 1 B1773 B1773 13 1 B1774 B1774 14 1 B1775 B1775 15 1 B1776 B1776 16 1 B1777 B1777 17 1 B1778 B1778 18 1 B1779 B1779 19 1 B1780 B1780 20 1 B1781 B1781 21 1 B1782 B1782 22 1 B1783 B1783 23 1 B1784 B1784 24 1 B1785 B1785 25 1 B1786 B1786 26 1 B1787 B1787 27 1 B1788 B1788 28 1 B1789 B1789 29 1 B1790 B1790 30 1 B1791 B1791 31 1 MPCBB2_VCTR56 MPCBB2_VCTR56 MPCBBx vector register 0x1E0 0x20 read-write 0xFFFFFFFF B1792 B1792 0 1 B1793 B1793 1 1 B1794 B1794 2 1 B1795 B1795 3 1 B1796 B1796 4 1 B1797 B1797 5 1 B1798 B1798 6 1 B1799 B1799 7 1 B1800 B1800 8 1 B1801 B1801 9 1 B1802 B1802 10 1 B1803 B1803 11 1 B1804 B1804 12 1 B1805 B1805 13 1 B1806 B1806 14 1 B1807 B1807 15 1 B1808 B1808 16 1 B1809 B1809 17 1 B1810 B1810 18 1 B1811 B1811 19 1 B1812 B1812 20 1 B1813 B1813 21 1 B1814 B1814 22 1 B1815 B1815 23 1 B1816 B1816 24 1 B1817 B1817 25 1 B1818 B1818 26 1 B1819 B1819 27 1 B1820 B1820 28 1 B1821 B1821 29 1 B1822 B1822 30 1 B1823 B1823 31 1 MPCBB2_VCTR57 MPCBB2_VCTR57 MPCBBx vector register 0x1E4 0x20 read-write 0xFFFFFFFF B1824 B1824 0 1 B1825 B1825 1 1 B1826 B1826 2 1 B1827 B1827 3 1 B1828 B1828 4 1 B1829 B1829 5 1 B1830 B1830 6 1 B1831 B1831 7 1 B1832 B1832 8 1 B1833 B1833 9 1 B1834 B1834 10 1 B1835 B1835 11 1 B1836 B1836 12 1 B1837 B1837 13 1 B1838 B1838 14 1 B1839 B1839 15 1 B1840 B1840 16 1 B1841 B1841 17 1 B1842 B1842 18 1 B1843 B1843 19 1 B1844 B1844 20 1 B1845 B1845 21 1 B1846 B1846 22 1 B1847 B1847 23 1 B1848 B1848 24 1 B1849 B1849 25 1 B1850 B1850 26 1 B1851 B1851 27 1 B1852 B1852 28 1 B1853 B1853 29 1 B1854 B1854 30 1 B1855 B1855 31 1 MPCBB2_VCTR58 MPCBB2_VCTR58 MPCBBx vector register 0x1E8 0x20 read-write 0xFFFFFFFF B1856 B1856 0 1 B1857 B1857 1 1 B1858 B1858 2 1 B1859 B1859 3 1 B1860 B1860 4 1 B1861 B1861 5 1 B1862 B1862 6 1 B1863 B1863 7 1 B1864 B1864 8 1 B1865 B1865 9 1 B1866 B1866 10 1 B1867 B1867 11 1 B1868 B1868 12 1 B1869 B1869 13 1 B1870 B1870 14 1 B1871 B1871 15 1 B1872 B1872 16 1 B1873 B1873 17 1 B1874 B1874 18 1 B1875 B1875 19 1 B1876 B1876 20 1 B1877 B1877 21 1 B1878 B1878 22 1 B1879 B1879 23 1 B1880 B1880 24 1 B1881 B1881 25 1 B1882 B1882 26 1 B1883 B1883 27 1 B1884 B1884 28 1 B1885 B1885 29 1 B1886 B1886 30 1 B1887 B1887 31 1 MPCBB2_VCTR59 MPCBB2_VCTR59 MPCBBx vector register 0x1EC 0x20 read-write 0xFFFFFFFF B1888 B1888 0 1 B1889 B1889 1 1 B1890 B1890 2 1 B1891 B1891 3 1 B1892 B1892 4 1 B1893 B1893 5 1 B1894 B1894 6 1 B1895 B1895 7 1 B1896 B1896 8 1 B1897 B1897 9 1 B1898 B1898 10 1 B1899 B1899 11 1 B1900 B1900 12 1 B1901 B1901 13 1 B1902 B1902 14 1 B1903 B1903 15 1 B1904 B1904 16 1 B1905 B1905 17 1 B1906 B1906 18 1 B1907 B1907 19 1 B1908 B1908 20 1 B1909 B1909 21 1 B1910 B1910 22 1 B1911 B1911 23 1 B1912 B1912 24 1 B1913 B1913 25 1 B1914 B1914 26 1 B1915 B1915 27 1 B1916 B1916 28 1 B1917 B1917 29 1 B1918 B1918 30 1 B1919 B1919 31 1 MPCBB2_VCTR60 MPCBB2_VCTR60 MPCBBx vector register 0x1F0 0x20 read-write 0xFFFFFFFF B1920 B1920 0 1 B1921 B1921 1 1 B1922 B1922 2 1 B1923 B1923 3 1 B1924 B1924 4 1 B1925 B1925 5 1 B1926 B1926 6 1 B1927 B1927 7 1 B1928 B1928 8 1 B1929 B1929 9 1 B1930 B1930 10 1 B1931 B1931 11 1 B1932 B1932 12 1 B1933 B1933 13 1 B1934 B1934 14 1 B1935 B1935 15 1 B1936 B1936 16 1 B1937 B1937 17 1 B1938 B1938 18 1 B1939 B1939 19 1 B1940 B1940 20 1 B1941 B1941 21 1 B1942 B1942 22 1 B1943 B1943 23 1 B1944 B1944 24 1 B1945 B1945 25 1 B1946 B1946 26 1 B1947 B1947 27 1 B1948 B1948 28 1 B1949 B1949 29 1 B1950 B1950 30 1 B1951 B1951 31 1 MPCBB2_VCTR61 MPCBB2_VCTR61 MPCBBx vector register 0x1F4 0x20 read-write 0xFFFFFFFF B1952 B1952 0 1 B1953 B1953 1 1 B1954 B1954 2 1 B1955 B1955 3 1 B1956 B1956 4 1 B1957 B1957 5 1 B1958 B1958 6 1 B1959 B1959 7 1 B1960 B1960 8 1 B1961 B1961 9 1 B1962 B1962 10 1 B1963 B1963 11 1 B1964 B1964 12 1 B1965 B1965 13 1 B1966 B1966 14 1 B1967 B1967 15 1 B1968 B1968 16 1 B1969 B1969 17 1 B1970 B1970 18 1 B1971 B1971 19 1 B1972 B1972 20 1 B1973 B1973 21 1 B1974 B1974 22 1 B1975 B1975 23 1 B1976 B1976 24 1 B1977 B1977 25 1 B1978 B1978 26 1 B1979 B1979 27 1 B1980 B1980 28 1 B1981 B1981 29 1 B1982 B1982 30 1 B1983 B1983 31 1 MPCBB2_VCTR62 MPCBB2_VCTR62 MPCBBx vector register 0x1F8 0x20 read-write 0xFFFFFFFF B1984 B1984 0 1 B1985 B1985 1 1 B1986 B1986 2 1 B1987 B1987 3 1 B1988 B1988 4 1 B1989 B1989 5 1 B1990 B1990 6 1 B1991 B1991 7 1 B1992 B1992 8 1 B1993 B1993 9 1 B1994 B1994 10 1 B1995 B1995 11 1 B1996 B1996 12 1 B1997 B1997 13 1 B1998 B1998 14 1 B1999 B1999 15 1 B2000 B2000 16 1 B2001 B2001 17 1 B2002 B2002 18 1 B2003 B2003 19 1 B2004 B2004 20 1 B2005 B2005 21 1 B2006 B2006 22 1 B2007 B2007 23 1 B2008 B2008 24 1 B2009 B2009 25 1 B2010 B2010 26 1 B2011 B2011 27 1 B2012 B2012 28 1 B2013 B2013 29 1 B2014 B2014 30 1 B2015 B2015 31 1 MPCBB2_VCTR63 MPCBB2_VCTR63 MPCBBx vector register 0x1FC 0x20 read-write 0xFFFFFFFF B2016 B2016 0 1 B2017 B2017 1 1 B2018 B2018 2 1 B2019 B2019 3 1 B2020 B2020 4 1 B2021 B2021 5 1 B2022 B2022 6 1 B2023 B2023 7 1 B2024 B2024 8 1 B2025 B2025 9 1 B2026 B2026 10 1 B2027 B2027 11 1 B2028 B2028 12 1 B2029 B2029 13 1 B2030 B2030 14 1 B2031 B2031 15 1 B2032 B2032 16 1 B2033 B2033 17 1 B2034 B2034 18 1 B2035 B2035 19 1 B2036 B2036 20 1 B2037 B2037 21 1 B2038 B2038 22 1 B2039 B2039 23 1 B2040 B2040 24 1 B2041 B2041 25 1 B2042 B2042 26 1 B2043 B2043 27 1 B2044 B2044 28 1 B2045 B2045 29 1 B2046 B2046 30 1 B2047 B2047 31 1 PWR Power control PWR 0x40007000 0x0 0x400 registers CR1 CR1 Power control register 1 0x0 0x20 read-write 0x00000400 LPR Low-power run 14 1 VOS Voltage scaling range selection 9 2 DBP Disable backup domain write protection 8 1 LPMS Low-power mode selection 0 3 CR2 CR2 Power control register 2 0x4 0x20 read-write 0x00000000 USV VDDUSB USB supply valid 10 1 IOSV VDDIO2 Independent I/Os supply valid 9 1 PVME4 Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V 7 1 PVME3 Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V 6 1 PVME2 Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V 5 1 PVME1 Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V 4 1 PLS Power voltage detector level selection 1 3 PVDE Power voltage detector enable 0 1 CR3 CR3 Power control register 3 0x8 0x20 read-write 0X00000000 UCPD_DBDIS UCPD_DBDIS 14 1 UCPD_STDBY UCPD_STDBY 13 1 ULPMEN ULPMEN 11 1 APC Apply pull-up and pull-down configuration 10 1 RRS SRAM2 retention in Standby mode 8 2 EWUP5 Enable Wakeup pin WKUP5 4 1 EWUP4 Enable Wakeup pin WKUP4 3 1 EWUP3 Enable Wakeup pin WKUP3 2 1 EWUP2 Enable Wakeup pin WKUP2 1 1 EWUP1 Enable Wakeup pin WKUP1 0 1 CR4 CR4 Power control register 4 0xC 0x20 read-write 0x00000000 SMPSLPEN SMPSLPEN 15 1 SMPSFSTEN SMPSFSTEN 14 1 EXTSMPSEN EXTSMPSEN 13 1 SMPSBYP SMPSBYP 12 1 VBRS VBAT battery charging resistor selection 9 1 VBE VBAT battery charging enable 8 1 WUPP5 Wakeup pin WKUP5 polarity 4 1 WUPP4 Wakeup pin WKUP4 polarity 3 1 WUPP3 Wakeup pin WKUP3 polarity 2 1 WUPP2 Wakeup pin WKUP2 polarity 1 1 WUPP1 Wakeup pin WKUP1 polarity 0 1 SR1 SR1 Power status register 1 0x10 0x20 read-only 0x00000000 SMPSHPRDY SMPSHPRDY 15 1 EXTSMPSRDY EXTSMPSRDY 13 1 SMPSBYPRDY SMPSBYPRDY 12 1 SBF Standby flag 8 1 WUF5 Wakeup flag 5 4 1 WUF4 Wakeup flag 4 3 1 WUF3 Wakeup flag 3 2 1 WUF2 Wakeup flag 2 1 1 WUF1 Wakeup flag 1 0 1 SR2 SR2 Power status register 2 0x14 0x20 read-only 0x00000000 PVMO4 Peripheral voltage monitoring output: VDDA vs. 2.2 V 15 1 PVMO3 Peripheral voltage monitoring output: VDDA vs. 1.62 V 14 1 PVMO2 Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V 13 1 PVMO1 Peripheral voltage monitoring output: VDDUSB vs. 1.2 V 12 1 PVDO Power voltage detector output 11 1 VOSF Voltage scaling flag 10 1 REGLPF Low-power regulator flag 9 1 REGLPS Low-power regulator started 8 1 SCR SCR Power status clear register 0x18 0x20 write-only 0x00000000 CSBF Clear standby flag 8 1 CWUF5 Clear wakeup flag 5 4 1 CWUF4 Clear wakeup flag 4 3 1 CWUF3 Clear wakeup flag 3 2 1 CWUF2 Clear wakeup flag 2 1 1 CWUF1 Clear wakeup flag 1 0 1 PUCRA PUCRA Power Port A pull-up control register 0x20 0x20 read-write 0x00000000 PU15 Port A pull-up bit y (y=0..15) 15 1 PU14 Port A pull-up bit y (y=0..15) 14 1 PU13 Port A pull-up bit y (y=0..15) 13 1 PU12 Port A pull-up bit y (y=0..15) 12 1 PU11 Port A pull-up bit y (y=0..15) 11 1 PU10 Port A pull-up bit y (y=0..15) 10 1 PU9 Port A pull-up bit y (y=0..15) 9 1 PU8 Port A pull-up bit y (y=0..15) 8 1 PU7 Port A pull-up bit y (y=0..15) 7 1 PU6 Port A pull-up bit y (y=0..15) 6 1 PU5 Port A pull-up bit y (y=0..15) 5 1 PU4 Port A pull-up bit y (y=0..15) 4 1 PU3 Port A pull-up bit y (y=0..15) 3 1 PU2 Port A pull-up bit y (y=0..15) 2 1 PU1 Port A pull-up bit y (y=0..15) 1 1 PU0 Port A pull-up bit y (y=0..15) 0 1 PDCRA PDCRA Power Port A pull-down control register 0x24 0x20 read-write 0x00000000 PD15 Port A pull-down bit y (y=0..15) 15 1 PD14 Port A pull-down bit y (y=0..15) 14 1 PD13 Port A pull-down bit y (y=0..15) 13 1 PD12 Port A pull-down bit y (y=0..15) 12 1 PD11 Port A pull-down bit y (y=0..15) 11 1 PD10 Port A pull-down bit y (y=0..15) 10 1 PD9 Port A pull-down bit y (y=0..15) 9 1 PD8 Port A pull-down bit y (y=0..15) 8 1 PD7 Port A pull-down bit y (y=0..15) 7 1 PD6 Port A pull-down bit y (y=0..15) 6 1 PD5 Port A pull-down bit y (y=0..15) 5 1 PD4 Port A pull-down bit y (y=0..15) 4 1 PD3 Port A pull-down bit y (y=0..15) 3 1 PD2 Port A pull-down bit y (y=0..15) 2 1 PD1 Port A pull-down bit y (y=0..15) 1 1 PD0 Port A pull-down bit y (y=0..15) 0 1 PUCRB PUCRB Power Port B pull-up control register 0x28 0x20 read-write 0x00000000 PU15 Port B pull-up bit y (y=0..15) 15 1 PU14 Port B pull-up bit y (y=0..15) 14 1 PU13 Port B pull-up bit y (y=0..15) 13 1 PU12 Port B pull-up bit y (y=0..15) 12 1 PU11 Port B pull-up bit y (y=0..15) 11 1 PU10 Port B pull-up bit y (y=0..15) 10 1 PU9 Port B pull-up bit y (y=0..15) 9 1 PU8 Port B pull-up bit y (y=0..15) 8 1 PU7 Port B pull-up bit y (y=0..15) 7 1 PU6 Port B pull-up bit y (y=0..15) 6 1 PU5 Port B pull-up bit y (y=0..15) 5 1 PU4 Port B pull-up bit y (y=0..15) 4 1 PU3 Port B pull-up bit y (y=0..15) 3 1 PU2 Port B pull-up bit y (y=0..15) 2 1 PU1 Port B pull-up bit y (y=0..15) 1 1 PU0 Port B pull-up bit y (y=0..15) 0 1 PDCRB PDCRB Power Port B pull-down control register 0x2C 0x20 read-write 0x00000000 PD15 Port B pull-down bit y (y=0..15) 15 1 PD14 Port B pull-down bit y (y=0..15) 14 1 PD13 Port B pull-down bit y (y=0..15) 13 1 PD12 Port B pull-down bit y (y=0..15) 12 1 PD11 Port B pull-down bit y (y=0..15) 11 1 PD10 Port B pull-down bit y (y=0..15) 10 1 PD9 Port B pull-down bit y (y=0..15) 9 1 PD8 Port B pull-down bit y (y=0..15) 8 1 PD7 Port B pull-down bit y (y=0..15) 7 1 PD6 Port B pull-down bit y (y=0..15) 6 1 PD5 Port B pull-down bit y (y=0..15) 5 1 PD4 Port B pull-down bit y (y=0..15) 4 1 PD3 Port B pull-down bit y (y=0..15) 3 1 PD2 Port B pull-down bit y (y=0..15) 2 1 PD1 Port B pull-down bit y (y=0..15) 1 1 PD0 Port B pull-down bit y (y=0..15) 0 1 PUCRC PUCRC Power Port C pull-up control register 0x30 0x20 read-write 0x00000000 PU15 Port C pull-up bit y (y=0..15) 15 1 PU14 Port C pull-up bit y (y=0..15) 14 1 PU13 Port C pull-up bit y (y=0..15) 13 1 PU12 Port C pull-up bit y (y=0..15) 12 1 PU11 Port C pull-up bit y (y=0..15) 11 1 PU10 Port C pull-up bit y (y=0..15) 10 1 PU9 Port C pull-up bit y (y=0..15) 9 1 PU8 Port C pull-up bit y (y=0..15) 8 1 PU7 Port C pull-up bit y (y=0..15) 7 1 PU6 Port C pull-up bit y (y=0..15) 6 1 PU5 Port C pull-up bit y (y=0..15) 5 1 PU4 Port C pull-up bit y (y=0..15) 4 1 PU3 Port C pull-up bit y (y=0..15) 3 1 PU2 Port C pull-up bit y (y=0..15) 2 1 PU1 Port C pull-up bit y (y=0..15) 1 1 PU0 Port C pull-up bit y (y=0..15) 0 1 PDCRC PDCRC Power Port C pull-down control register 0x34 0x20 read-write 0x00000000 PD15 Port C pull-down bit y (y=0..15) 15 1 PD14 Port C pull-down bit y (y=0..15) 14 1 PD13 Port C pull-down bit y (y=0..15) 13 1 PD12 Port C pull-down bit y (y=0..15) 12 1 PD11 Port C pull-down bit y (y=0..15) 11 1 PD10 Port C pull-down bit y (y=0..15) 10 1 PD9 Port C pull-down bit y (y=0..15) 9 1 PD8 Port C pull-down bit y (y=0..15) 8 1 PD7 Port C pull-down bit y (y=0..15) 7 1 PD6 Port C pull-down bit y (y=0..15) 6 1 PD5 Port C pull-down bit y (y=0..15) 5 1 PD4 Port C pull-down bit y (y=0..15) 4 1 PD3 Port C pull-down bit y (y=0..15) 3 1 PD2 Port C pull-down bit y (y=0..15) 2 1 PD1 Port C pull-down bit y (y=0..15) 1 1 PD0 Port C pull-down bit y (y=0..15) 0 1 PUCRD PUCRD Power Port D pull-up control register 0x38 0x20 read-write 0x00000000 PU15 Port D pull-up bit y (y=0..15) 15 1 PU14 Port D pull-up bit y (y=0..15) 14 1 PU13 Port D pull-up bit y (y=0..15) 13 1 PU12 Port D pull-up bit y (y=0..15) 12 1 PU11 Port D pull-up bit y (y=0..15) 11 1 PU10 Port D pull-up bit y (y=0..15) 10 1 PU9 Port D pull-up bit y (y=0..15) 9 1 PU8 Port D pull-up bit y (y=0..15) 8 1 PU7 Port D pull-up bit y (y=0..15) 7 1 PU6 Port D pull-up bit y (y=0..15) 6 1 PU5 Port D pull-up bit y (y=0..15) 5 1 PU4 Port D pull-up bit y (y=0..15) 4 1 PU3 Port D pull-up bit y (y=0..15) 3 1 PU2 Port D pull-up bit y (y=0..15) 2 1 PU1 Port D pull-up bit y (y=0..15) 1 1 PU0 Port D pull-up bit y (y=0..15) 0 1 PDCRD PDCRD Power Port D pull-down control register 0x3C 0x20 read-write 0x00000000 PD15 Port D pull-down bit y (y=0..15) 15 1 PD14 Port D pull-down bit y (y=0..15) 14 1 PD13 Port D pull-down bit y (y=0..15) 13 1 PD12 Port D pull-down bit y (y=0..15) 12 1 PD11 Port D pull-down bit y (y=0..15) 11 1 PD10 Port D pull-down bit y (y=0..15) 10 1 PD9 Port D pull-down bit y (y=0..15) 9 1 PD8 Port D pull-down bit y (y=0..15) 8 1 PD7 Port D pull-down bit y (y=0..15) 7 1 PD6 Port D pull-down bit y (y=0..15) 6 1 PD5 Port D pull-down bit y (y=0..15) 5 1 PD4 Port D pull-down bit y (y=0..15) 4 1 PD3 Port D pull-down bit y (y=0..15) 3 1 PD2 Port D pull-down bit y (y=0..15) 2 1 PD1 Port D pull-down bit y (y=0..15) 1 1 PD0 Port D pull-down bit y (y=0..15) 0 1 PUCRE PUCRE Power Port E pull-up control register 0x40 0x20 read-write 0x00000000 PU15 Port E pull-up bit y (y=0..15) 15 1 PU14 Port E pull-up bit y (y=0..15) 14 1 PU13 Port E pull-up bit y (y=0..15) 13 1 PU12 Port E pull-up bit y (y=0..15) 12 1 PU11 Port E pull-up bit y (y=0..15) 11 1 PU10 Port E pull-up bit y (y=0..15) 10 1 PU9 Port E pull-up bit y (y=0..15) 9 1 PU8 Port E pull-up bit y (y=0..15) 8 1 PU7 Port E pull-up bit y (y=0..15) 7 1 PU6 Port E pull-up bit y (y=0..15) 6 1 PU5 Port E pull-up bit y (y=0..15) 5 1 PU4 Port E pull-up bit y (y=0..15) 4 1 PU3 Port E pull-up bit y (y=0..15) 3 1 PU2 Port E pull-up bit y (y=0..15) 2 1 PU1 Port E pull-up bit y (y=0..15) 1 1 PU0 Port E pull-up bit y (y=0..15) 0 1 PDCRE PDCRE Power Port E pull-down control register 0x44 0x20 read-write 0x00000000 PD15 Port E pull-down bit y (y=0..15) 15 1 PD14 Port E pull-down bit y (y=0..15) 14 1 PD13 Port E pull-down bit y (y=0..15) 13 1 PD12 Port E pull-down bit y (y=0..15) 12 1 PD11 Port E pull-down bit y (y=0..15) 11 1 PD10 Port E pull-down bit y (y=0..15) 10 1 PD9 Port E pull-down bit y (y=0..15) 9 1 PD8 Port E pull-down bit y (y=0..15) 8 1 PD7 Port E pull-down bit y (y=0..15) 7 1 PD6 Port E pull-down bit y (y=0..15) 6 1 PD5 Port E pull-down bit y (y=0..15) 5 1 PD4 Port E pull-down bit y (y=0..15) 4 1 PD3 Port E pull-down bit y (y=0..15) 3 1 PD2 Port E pull-down bit y (y=0..15) 2 1 PD1 Port E pull-down bit y (y=0..15) 1 1 PD0 Port E pull-down bit y (y=0..15) 0 1 PUCRF PUCRF Power Port F pull-up control register 0x48 0x20 read-write 0x00000000 PU15 Port F pull-up bit y (y=0..15) 15 1 PU14 Port F pull-up bit y (y=0..15) 14 1 PU13 Port F pull-up bit y (y=0..15) 13 1 PU12 Port F pull-up bit y (y=0..15) 12 1 PU11 Port F pull-up bit y (y=0..15) 11 1 PU10 Port F pull-up bit y (y=0..15) 10 1 PU9 Port F pull-up bit y (y=0..15) 9 1 PU8 Port F pull-up bit y (y=0..15) 8 1 PU7 Port F pull-up bit y (y=0..15) 7 1 PU6 Port F pull-up bit y (y=0..15) 6 1 PU5 Port F pull-up bit y (y=0..15) 5 1 PU4 Port F pull-up bit y (y=0..15) 4 1 PU3 Port F pull-up bit y (y=0..15) 3 1 PU2 Port F pull-up bit y (y=0..15) 2 1 PU1 Port F pull-up bit y (y=0..15) 1 1 PU0 Port F pull-up bit y (y=0..15) 0 1 PDCRF PDCRF Power Port F pull-down control register 0x4C 0x20 read-write 0x00000000 PD15 Port F pull-down bit y (y=0..15) 15 1 PD14 Port F pull-down bit y (y=0..15) 14 1 PD13 Port F pull-down bit y (y=0..15) 13 1 PD12 Port F pull-down bit y (y=0..15) 12 1 PD11 Port F pull-down bit y (y=0..15) 11 1 PD10 Port F pull-down bit y (y=0..15) 10 1 PD9 Port F pull-down bit y (y=0..15) 9 1 PD8 Port F pull-down bit y (y=0..15) 8 1 PD7 Port F pull-down bit y (y=0..15) 7 1 PD6 Port F pull-down bit y (y=0..15) 6 1 PD5 Port F pull-down bit y (y=0..15) 5 1 PD4 Port F pull-down bit y (y=0..15) 4 1 PD3 Port F pull-down bit y (y=0..15) 3 1 PD2 Port F pull-down bit y (y=0..15) 2 1 PD1 Port F pull-down bit y (y=0..15) 1 1 PD0 Port F pull-down bit y (y=0..15) 0 1 PUCRG PUCRG Power Port G pull-up control register 0x50 0x20 read-write 0x00000000 PU15 Port G pull-up bit y (y=0..15) 15 1 PU14 Port G pull-up bit y (y=0..15) 14 1 PU13 Port G pull-up bit y (y=0..15) 13 1 PU12 Port G pull-up bit y (y=0..15) 12 1 PU11 Port G pull-up bit y (y=0..15) 11 1 PU10 Port G pull-up bit y (y=0..15) 10 1 PU9 Port G pull-up bit y (y=0..15) 9 1 PU8 Port G pull-up bit y (y=0..15) 8 1 PU7 Port G pull-up bit y (y=0..15) 7 1 PU6 Port G pull-up bit y (y=0..15) 6 1 PU5 Port G pull-up bit y (y=0..15) 5 1 PU4 Port G pull-up bit y (y=0..15) 4 1 PU3 Port G pull-up bit y (y=0..15) 3 1 PU2 Port G pull-up bit y (y=0..15) 2 1 PU1 Port G pull-up bit y (y=0..15) 1 1 PU0 Port G pull-up bit y (y=0..15) 0 1 PDCRG PDCRG Power Port G pull-down control register 0x54 0x20 read-write 0x00000000 PD15 Port G pull-down bit y (y=0..15) 15 1 PD14 Port G pull-down bit y (y=0..15) 14 1 PD13 Port G pull-down bit y (y=0..15) 13 1 PD12 Port G pull-down bit y (y=0..15) 12 1 PD11 Port G pull-down bit y (y=0..15) 11 1 PD10 Port G pull-down bit y (y=0..15) 10 1 PD9 Port G pull-down bit y (y=0..15) 9 1 PD8 Port G pull-down bit y (y=0..15) 8 1 PD7 Port G pull-down bit y (y=0..15) 7 1 PD6 Port G pull-down bit y (y=0..15) 6 1 PD5 Port G pull-down bit y (y=0..15) 5 1 PD4 Port G pull-down bit y (y=0..15) 4 1 PD3 Port G pull-down bit y (y=0..15) 3 1 PD2 Port G pull-down bit y (y=0..15) 2 1 PD1 Port G pull-down bit y (y=0..15) 1 1 PD0 Port G pull-down bit y (y=0..15) 0 1 PUCRH PUCRH Power Port H pull-up control register 0x58 0x20 read-write 0x00000000 PU15 Port G pull-up bit y (y=0..15) 15 1 PU14 Port G pull-up bit y (y=0..15) 14 1 PU13 Port G pull-up bit y (y=0..15) 13 1 PU12 Port G pull-up bit y (y=0..15) 12 1 PU11 Port G pull-up bit y (y=0..15) 11 1 PU10 Port G pull-up bit y (y=0..15) 10 1 PU9 Port G pull-up bit y (y=0..15) 9 1 PU8 Port G pull-up bit y (y=0..15) 8 1 PU7 Port G pull-up bit y (y=0..15) 7 1 PU6 Port G pull-up bit y (y=0..15) 6 1 PU5 Port G pull-up bit y (y=0..15) 5 1 PU4 Port G pull-up bit y (y=0..15) 4 1 PU3 Port G pull-up bit y (y=0..15) 3 1 PU2 Port G pull-up bit y (y=0..15) 2 1 PU1 Port G pull-up bit y (y=0..15) 1 1 PU0 Port G pull-up bit y (y=0..15) 0 1 PDCRH PDCRH Power Port H pull-down control register 0x5C 0x20 read-write 0x00000000 PD15 Port G pull-down bit y (y=0..15) 15 1 PD14 Port G pull-down bit y (y=0..15) 14 1 PD13 Port G pull-down bit y (y=0..15) 13 1 PD12 Port G pull-down bit y (y=0..15) 12 1 PD11 Port G pull-down bit y (y=0..15) 11 1 PD10 Port G pull-down bit y (y=0..15) 10 1 PD9 Port G pull-down bit y (y=0..15) 9 1 PD8 Port G pull-down bit y (y=0..15) 8 1 PD7 Port G pull-down bit y (y=0..15) 7 1 PD6 Port G pull-down bit y (y=0..15) 6 1 PD5 Port G pull-down bit y (y=0..15) 5 1 PD4 Port G pull-down bit y (y=0..15) 4 1 PD3 Port G pull-down bit y (y=0..15) 3 1 PD2 Port G pull-down bit y (y=0..15) 2 1 PD1 Port G pull-down bit y (y=0..15) 1 1 PD0 Port G pull-down bit y (y=0..15) 0 1 SECCFGR SECCFGR Power secure configuration register 0x78 0x20 read-write 0x00000000 APCSEC APCSEC 11 1 VBSEC VBSEC 10 1 VDMSEC VDMSEC 9 1 LPMSEC LPMSEC 8 1 WUP5SEC WKUP5 pin security 4 1 WUP4SEC WKUP4 pin security 3 1 WUP3SEC WKUP3 pin security 2 1 WUP2SEC WKUP2 pin security 1 1 WUP1SEC WKUP1 pin security 0 1 PRIVCFGR PRIVCFGR Power privilege configuration register 0x80 0x20 read-write 0x00000000 PRIV PRIV 0 1 SEC_PWR !(DCB->DSCSR & (1 << 16)) 0x50007000 RCC Reset and clock control RCC 0x40021000 0x0 0x400 registers RCC RCC global interrupt 009 RCC_S RCC SECURE GLOBAL INTERRUPT 010 CR CR Clock control register 0x0 0x20 0x00000063 PRIV PRIV 31 1 read-write PLLSAI2RDY SAI2 PLL clock ready flag 29 1 read-only PLLSAI2ON SAI2 PLL enable 28 1 read-write PLLSAI1RDY SAI1 PLL clock ready flag 27 1 read-only PLLSAI1ON SAI1 PLL enable 26 1 read-write PLLRDY Main PLL clock ready flag 25 1 read-only PLLON Main PLL enable 24 1 read-write CSSON Clock security system enable 19 1 write-only HSEBYP HSE crystal oscillator bypass 18 1 read-write HSERDY HSE clock ready flag 17 1 read-only HSEON HSE clock enable 16 1 read-write HSIASFS HSI automatic start from Stop 11 1 read-write HSIRDY HSI clock ready flag 10 1 read-only HSIKERON HSI always enable for peripheral kernels 9 1 read-write HSION HSI clock enable 8 1 read-write MSIRANGE MSI clock ranges 4 4 read-write MSIRGSEL MSI clock range selection 3 1 write-only MSIPLLEN MSI clock PLL enable 2 1 read-write MSIRDY MSI clock ready flag 1 1 read-only MSION MSI clock enable 0 1 read-write ICSCR ICSCR Internal clock sources calibration register 0x4 0x20 0x40000000 HSITRIM HSI clock trimming 24 7 read-write HSICAL HSI clock calibration 16 8 read-only MSITRIM MSI clock trimming 8 8 read-write MSICAL MSI clock calibration 0 8 read-only CFGR CFGR Clock configuration register 0x8 0x20 0x00000000 MCOPRE Microcontroller clock output prescaler 28 3 read-only MCOSEL Microcontroller clock output 24 4 read-write STOPWUCK Wakeup from Stop and CSS backup clock selection 15 1 read-write PPRE2 APB high-speed prescaler (APB2) 11 3 read-write PPRE1 PB low-speed prescaler (APB1) 8 3 read-write HPRE AHB prescaler 4 4 read-write SWS System clock switch status 2 2 read-only SW System clock switch 0 2 read-write PLLCFGR PLLCFGR PLL configuration register 0xC 0x20 read-write 0x00001000 PLLPDIV Main PLL division factor for PLLSAI2CLK 27 5 PLLR Main PLL division factor for PLLCLK (system clock) 25 2 PLLREN Main PLL PLLCLK output enable 24 1 PLLQ Main PLL division factor for PLLUSB1CLK(48 MHz clock) 21 2 PLLQEN Main PLL PLLUSB1CLK output enable 20 1 PLLP Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) 17 1 PLLPEN Main PLL PLLSAI3CLK output enable 16 1 PLLN Main PLL multiplication factor for VCO 8 7 PLLM Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock 4 4 PLLSRC Main PLL, PLLSAI1 and PLLSAI2 entry clock source 0 2 PLLSAI1CFGR PLLSAI1CFGR PLLSAI1 configuration register 0x10 0x20 read-write 0x00001000 PLLSAI1PDIV PLLSAI1 division factor for PLLSAI1CLK 27 5 PLLSAI1R PLLSAI1 division factor for PLLADC1CLK (ADC clock) 25 2 PLLSAI1REN PLLSAI1 PLLADC1CLK output enable 24 1 PLLSAI1Q SAI1PLL division factor for PLLUSB2CLK (48 MHz clock) 21 2 PLLSAI1QEN SAI1PLL PLLUSB2CLK output enable 20 1 PLLSAI1P SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock) 17 1 PLLSAI1PEN SAI1PLL PLLSAI1CLK output enable 16 1 PLLSAI1N SAI1PLL multiplication factor for VCO 8 7 PLLSAI1M Division factor for PLLSAI1 input clock 4 4 PLLSAI1SRC PLLSAI1SRC 0 2 PLLSAI2CFGR PLLSAI2CFGR PLLSAI2 configuration register 0x14 0x20 read-write 0x00001000 PLLSAI2PDIV PLLSAI2 division factor for PLLSAI2CLK 27 5 PLLSAI2P SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock) 17 1 PLLSAI2PEN SAI2PLL PLLSAI2CLK output enable 16 1 PLLSAI2N SAI2PLL multiplication factor for VCO 8 7 PLLSAI2M Division factor for PLLSAI2 input clock 4 4 PLLSAI2SRC PLLSAI2SRC 0 2 CIER CIER Clock interrupt enable register 0x18 0x20 read-write 0x00000000 LSIRDYIE LSI ready interrupt enable 0 1 LSERDYIE LSE ready interrupt enable 1 1 MSIRDYIE MSI ready interrupt enable 2 1 HSIRDYIE HSI ready interrupt enable 3 1 HSERDYIE HSE ready interrupt enable 4 1 PLLRDYIE PLL ready interrupt enable 5 1 PLLSAI1RDYIE PLLSAI1 ready interrupt enable 6 1 PLLSAI2RDYIE PLLSAI2 ready interrupt enable 7 1 LSECSSIE LSE clock security system interrupt enable 9 1 HSI48RDYIE HSI48 ready interrupt enable 10 1 CIFR CIFR Clock interrupt flag register 0x1C 0x20 read-only 0x00000000 LSIRDYF LSI ready interrupt flag 0 1 LSERDYF LSE ready interrupt flag 1 1 MSIRDYF MSI ready interrupt flag 2 1 HSIRDYF HSI ready interrupt flag 3 1 HSERDYF HSE ready interrupt flag 4 1 PLLRDYF PLL ready interrupt flag 5 1 PLLSAI1RDYF PLLSAI1 ready interrupt flag 6 1 PLLSAI2RDYF PLLSAI2 ready interrupt flag 7 1 CSSF Clock security system interrupt flag 8 1 LSECSSF LSE Clock security system interrupt flag 9 1 HSI48RDYF HSI48 ready interrupt flag 10 1 CICR CICR Clock interrupt clear register 0x20 0x20 write-only 0x00000000 LSIRDYC LSI ready interrupt clear 0 1 LSERDYC LSE ready interrupt clear 1 1 MSIRDYC MSI ready interrupt clear 2 1 HSIRDYC HSI ready interrupt clear 3 1 HSERDYC HSE ready interrupt clear 4 1 PLLRDYC PLL ready interrupt clear 5 1 PLLSAI1RDYC PLLSAI1 ready interrupt clear 6 1 PLLSAI2RDYC PLLSAI2 ready interrupt clear 7 1 CSSC Clock security system interrupt clear 8 1 LSECSSC LSE Clock security system interrupt clear 9 1 HSI48RDYC HSI48 oscillator ready interrupt clear 10 1 AHB1RSTR AHB1RSTR AHB1 peripheral reset register 0x28 0x20 read-write 0x00000000 DMA1RST DMA1 reset 0 1 DMA2RST DMA2 reset 1 1 DMAMUX1RST DMAMUXRST 2 1 FLASHRST Flash memory interface reset 8 1 CRCRST CRC reset 12 1 TSCRST Touch Sensing Controller reset 16 1 GTZCRST GTZC reset 22 1 AHB2RSTR AHB2RSTR AHB2 peripheral reset register 0x2C 0x20 read-write 0x00000000 GPIOARST IO port A reset 0 1 GPIOBRST IO port B reset 1 1 GPIOCRST IO port C reset 2 1 GPIODRST IO port D reset 3 1 GPIOERST IO port E reset 4 1 GPIOFRST IO port F reset 5 1 GPIOGRST IO port G reset 6 1 GPIOHRST IO port H reset 7 1 ADCRST ADC reset 13 1 AESRST AES hardware accelerator reset 16 1 HASHRST Hash reset 17 1 RNGRST Random number generator reset 18 1 PKARST PKARST 19 1 OTFDEC1RST OTFDEC1RST 21 1 SDMMC1RST SDMMC1 reset 22 1 AHB3RSTR AHB3RSTR AHB3 peripheral reset register 0x30 0x20 read-write 0x00000000 FMCRST Flexible memory controller reset 0 1 OSPI1RST OSPI1RST 8 1 APB1RSTR1 APB1RSTR1 APB1 peripheral reset register 1 0x38 0x20 read-write 0x00000000 LPTIM1RST Low Power Timer 1 reset 31 1 OPAMPRST OPAMP interface reset 30 1 DAC1RST DAC1 interface reset 29 1 PWRRST Power interface reset 28 1 CRSRST CRS reset 24 1 I2C3RST I2C3 reset 23 1 I2C2RST I2C2 reset 22 1 I2C1RST I2C1 reset 21 1 UART5RST UART5 reset 20 1 UART4RST UART4 reset 19 1 USART3RST USART3 reset 18 1 USART2RST USART2 reset 17 1 SPI3RST SPI3 reset 15 1 SPI2RST SPI2 reset 14 1 TIM7RST TIM7 timer reset 5 1 TIM6RST TIM6 timer reset 4 1 TIM5RST TIM5 timer reset 3 1 TIM4RST TIM3 timer reset 2 1 TIM3RST TIM3 timer reset 1 1 TIM2RST TIM2 timer reset 0 1 APB1RSTR2 APB1RSTR2 APB1 peripheral reset register 2 0x3C 0x20 read-write 0x00000000 LPUART1RST Low-power UART 1 reset 0 1 I2C4RST I2C4 reset 1 1 LPTIM2RST Low-power timer 2 reset 5 1 LPTIM3RST LPTIM3RST 6 1 FDCAN1RST FDCAN1RST 9 1 USBFSRST USBFSRST 21 1 UCPD1RST UCPD1RST 23 1 APB2RSTR APB2RSTR APB2 peripheral reset register 0x40 0x20 read-write 0x00000000 SYSCFGRST System configuration (SYSCFG) reset 0 1 TIM1RST TIM1 timer reset 11 1 SPI1RST SPI1 reset 12 1 TIM8RST TIM8 timer reset 13 1 USART1RST USART1 reset 14 1 TIM15RST TIM15 timer reset 16 1 TIM16RST TIM16 timer reset 17 1 TIM17RST TIM17 timer reset 18 1 SAI1RST Serial audio interface 1 (SAI1) reset 21 1 SAI2RST Serial audio interface 2 (SAI2) reset 22 1 DFSDM1RST Digital filters for sigma-delata modulators (DFSDM) reset 24 1 AHB1ENR AHB1ENR AHB1 peripheral clock enable register 0x48 0x20 read-write 0x00000100 DMA1EN DMA1 clock enable 0 1 DMA2EN DMA2 clock enable 1 1 DMAMUX1EN DMAMUX clock enable 2 1 FLASHEN Flash memory interface clock enable 8 1 CRCEN CRC clock enable 12 1 TSCEN Touch Sensing Controller clock enable 16 1 GTZCEN GTZCEN 22 1 AHB2ENR AHB2ENR AHB2 peripheral clock enable register 0x4C 0x20 read-write 0x00000000 GPIOAEN IO port A clock enable 0 1 GPIOBEN IO port B clock enable 1 1 GPIOCEN IO port C clock enable 2 1 GPIODEN IO port D clock enable 3 1 GPIOEEN IO port E clock enable 4 1 GPIOFEN IO port F clock enable 5 1 GPIOGEN IO port G clock enable 6 1 GPIOHEN IO port H clock enable 7 1 ADCEN ADC clock enable 13 1 AESEN AES accelerator clock enable 16 1 HASHEN HASH clock enable 17 1 RNGEN Random Number Generator clock enable 18 1 PKAEN PKAEN 19 1 OTFDEC1EN OTFDEC1EN 21 1 SDMMC1EN SDMMC1 clock enable 22 1 AHB3ENR AHB3ENR AHB3 peripheral clock enable register 0x50 0x20 read-write 0x00000000 FMCEN Flexible memory controller clock enable 0 1 OSPI1EN OSPI1EN 8 1 APB1ENR1 APB1ENR1 APB1ENR1 0x58 0x20 read-write 0x00000000 TIM2EN TIM2 timer clock enable 0 1 TIM3EN TIM3 timer clock enable 1 1 TIM4EN TIM4 timer clock enable 2 1 TIM5EN TIM5 timer clock enable 3 1 TIM6EN TIM6 timer clock enable 4 1 TIM7EN TIM7 timer clock enable 5 1 RTCAPBEN RTC APB clock enable 10 1 WWDGEN Window watchdog clock enable 11 1 SPI2EN SPI2 clock enable 14 1 SP3EN SPI3 clock enable 15 1 USART2EN USART2 clock enable 17 1 USART3EN USART3 clock enable 18 1 UART4EN UART4 clock enable 19 1 UART5EN UART5 clock enable 20 1 I2C1EN I2C1 clock enable 21 1 I2C2EN I2C2 clock enable 22 1 I2C3EN I2C3 clock enable 23 1 CRSEN Clock Recovery System clock enable 24 1 PWREN Power interface clock enable 28 1 DAC1EN DAC1 interface clock enable 29 1 OPAMPEN OPAMP interface clock enable 30 1 LPTIM1EN Low power timer 1 clock enable 31 1 APB1ENR2 APB1ENR2 APB1 peripheral clock enable register 2 0x5C 0x20 read-write 0x00000000 LPUART1EN Low power UART 1 clock enable 0 1 I2C4EN I2C4 clock enable 1 1 LPTIM2EN LPTIM2EN 5 1 LPTIM3EN LPTIM3EN 6 1 FDCAN1EN FDCAN1EN 9 1 USBFSEN USBFSEN 21 1 UCPD1EN UCPD1EN 23 1 APB2ENR APB2ENR APB2ENR 0x60 0x20 read-write 0x00000000 SYSCFGEN SYSCFG clock enable 0 1 TIM1EN TIM1 timer clock enable 11 1 SPI1EN SPI1 clock enable 12 1 TIM8EN TIM8 timer clock enable 13 1 USART1EN USART1clock enable 14 1 TIM15EN TIM15 timer clock enable 16 1 TIM16EN TIM16 timer clock enable 17 1 TIM17EN TIM17 timer clock enable 18 1 SAI1EN SAI1 clock enable 21 1 SAI2EN SAI2 clock enable 22 1 DFSDM1EN DFSDM timer clock enable 24 1 AHB1SMENR AHB1SMENR AHB1 peripheral clocks enable in Sleep and Stop modes register 0x68 0x20 read-write 0x00C11307 DMA1SMEN DMA1 clocks enable during Sleep and Stop modes 0 1 DMA2SMEN DMA2 clocks enable during Sleep and Stop modes 1 1 DMAMUX1SMEN DMAMUX clock enable during Sleep and Stop modes 2 1 FLASHSMEN Flash memory interface clocks enable during Sleep and Stop modes 8 1 SRAM1SMEN SRAM1 interface clocks enable during Sleep and Stop modes 9 1 CRCSMEN CRCSMEN 12 1 TSCSMEN Touch Sensing Controller clocks enable during Sleep and Stop modes 16 1 GTZCSMEN GTZCSMEN 22 1 ICACHESMEN ICACHESMEN 23 1 AHB2SMENR AHB2SMENR AHB2 peripheral clocks enable in Sleep and Stop modes register 0x6C 0x20 read-write 0x006F22FF GPIOASMEN IO port A clocks enable during Sleep and Stop modes 0 1 GPIOBSMEN IO port B clocks enable during Sleep and Stop modes 1 1 GPIOCSMEN IO port C clocks enable during Sleep and Stop modes 2 1 GPIODSMEN IO port D clocks enable during Sleep and Stop modes 3 1 GPIOESMEN IO port E clocks enable during Sleep and Stop modes 4 1 GPIOFSMEN IO port F clocks enable during Sleep and Stop modes 5 1 GPIOGSMEN IO port G clocks enable during Sleep and Stop modes 6 1 GPIOHSMEN IO port H clocks enable during Sleep and Stop modes 7 1 SRAM2SMEN SRAM2 interface clocks enable during Sleep and Stop modes 9 1 ADCFSSMEN ADC clocks enable during Sleep and Stop modes 13 1 AESSMEN AES accelerator clocks enable during Sleep and Stop modes 16 1 HASHSMEN HASH clock enable during Sleep and Stop modes 17 1 RNGSMEN Random Number Generator clocks enable during Sleep and Stop modes 18 1 PKASMEN PKASMEN 19 1 OTFDEC1SMEN OTFDEC1SMEN 21 1 SDMMC1SMEN SDMMC1 clocks enable during Sleep and Stop modes 22 1 AHB3SMENR AHB3SMENR AHB3 peripheral clocks enable in Sleep and Stop modes register 0x70 0x20 read-write 0x000000101 FMCSMEN Flexible memory controller clocks enable during Sleep and Stop modes 0 1 OSPI1SMEN OSPI1SMEN 8 1 APB1SMENR1 APB1SMENR1 APB1SMENR1 0x78 0x20 read-write 0xF1FECC3F TIM2SMEN TIM2 timer clocks enable during Sleep and Stop modes 0 1 TIM3SMEN TIM3 timer clocks enable during Sleep and Stop modes 1 1 TIM4SMEN TIM4 timer clocks enable during Sleep and Stop modes 2 1 TIM5SMEN TIM5 timer clocks enable during Sleep and Stop modes 3 1 TIM6SMEN TIM6 timer clocks enable during Sleep and Stop modes 4 1 TIM7SMEN TIM7 timer clocks enable during Sleep and Stop modes 5 1 RTCAPBSMEN RTC APB clock enable during Sleep and Stop modes 10 1 WWDGSMEN Window watchdog clocks enable during Sleep and Stop modes 11 1 SPI2SMEN SPI2 clocks enable during Sleep and Stop modes 14 1 SP3SMEN SPI3 clocks enable during Sleep and Stop modes 15 1 USART2SMEN USART2 clocks enable during Sleep and Stop modes 17 1 USART3SMEN USART3 clocks enable during Sleep and Stop modes 18 1 UART4SMEN UART4 clocks enable during Sleep and Stop modes 19 1 UART5SMEN UART5 clocks enable during Sleep and Stop modes 20 1 I2C1SMEN I2C1 clocks enable during Sleep and Stop modes 21 1 I2C2SMEN I2C2 clocks enable during Sleep and Stop modes 22 1 I2C3SMEN I2C3 clocks enable during Sleep and Stop modes 23 1 CRSSMEN CRS clock enable during Sleep and Stop modes 24 1 PWRSMEN Power interface clocks enable during Sleep and Stop modes 28 1 DAC1SMEN DAC1 interface clocks enable during Sleep and Stop modes 29 1 OPAMPSMEN OPAMP interface clocks enable during Sleep and Stop modes 30 1 LPTIM1SMEN Low power timer 1 clocks enable during Sleep and Stop modes 31 1 APB1SMENR2 APB1SMENR2 APB1 peripheral clocks enable in Sleep and Stop modes register 2 0x7C 0x20 read-write 0x00A00223 LPUART1SMEN Low power UART 1 clocks enable during Sleep and Stop modes 0 1 I2C4SMEN I2C4 clocks enable during Sleep and Stop modes 1 1 LPTIM2SMEN LPTIM2SMEN 5 1 LPTIM3SMEN LPTIM3SMEN 6 1 FDCAN1SMEN FDCAN1SMEN 9 1 USBFSSMEN USBFSSMEN 21 1 UCPD1SMEN UCPD1SMEN 23 1 APB2SMENR APB2SMENR APB2SMENR 0x80 0x20 read-write 0x01677801 SYSCFGSMEN SYSCFG clocks enable during Sleep and Stop modes 0 1 TIM1SMEN TIM1 timer clocks enable during Sleep and Stop modes 11 1 SPI1SMEN SPI1 clocks enable during Sleep and Stop modes 12 1 TIM8SMEN TIM8 timer clocks enable during Sleep and Stop modes 13 1 USART1SMEN USART1clocks enable during Sleep and Stop modes 14 1 TIM15SMEN TIM15 timer clocks enable during Sleep and Stop modes 16 1 TIM16SMEN TIM16 timer clocks enable during Sleep and Stop modes 17 1 TIM17SMEN TIM17 timer clocks enable during Sleep and Stop modes 18 1 SAI1SMEN SAI1 clocks enable during Sleep and Stop modes 21 1 SAI2SMEN SAI2 clocks enable during Sleep and Stop modes 22 1 DFSDM1SMEN DFSDM timer clocks enable during Sleep and Stop modes 24 1 CCIPR1 CCIPR1 CCIPR1 0x88 0x20 read-write 0x00000000 ADCSEL ADCs clock source selection 28 2 CLK48MSEL 48 MHz clock source selection 26 2 FDCANSEL FDCAN clock source selection 24 2 LPTIM3SEL Low-power timer 3 clock source selection 22 2 LPTIM2SEL Low power timer 2 clock source selection 20 2 LPTIM1SEL Low power timer 1 clock source selection 18 2 I2C3SEL I2C3 clock source selection 16 2 I2C2SEL I2C2 clock source selection 14 2 I2C1SEL I2C1 clock source selection 12 2 LPUART1SEL LPUART1 clock source selection 10 2 UART5SEL UART5 clock source selection 8 2 UART4SEL UART4 clock source selection 6 2 USART3SEL USART3 clock source selection 4 2 USART2SEL USART2 clock source selection 2 2 USART1SEL USART1 clock source selection 0 2 BDCR BDCR BDCR 0x90 0x20 0x00000000 LSCOSEL Low speed clock output selection 25 1 read-write LSCOEN Low speed clock output enable 24 1 read-write BDRST Backup domain software reset 16 1 read-write RTCEN RTC clock enable 15 1 read-write LSESYSRDY LSESYSRDY 11 1 read-write RTCSEL RTC clock source selection 8 2 read-write LSESYSEN LSESYSEN 7 1 read-write LSECSSD LSECSSD 6 1 read-only LSECSSON LSECSSON 5 1 read-write LSEDRV SE oscillator drive capability 3 2 read-write LSEBYP LSE oscillator bypass 2 1 read-write LSERDY LSE oscillator ready 1 1 read-only LSEON LSE oscillator enable 0 1 read-write CSR CSR CSR 0x94 0x20 0x0C000600 LPWRSTF Low-power reset flag 31 1 read-only WWDGRSTF Window watchdog reset flag 30 1 read-only IWWDGRSTF Independent window watchdog reset flag 29 1 read-only SFTRSTF Software reset flag 28 1 read-only BORRSTF BOR flag 27 1 read-only PINRSTF Pin reset flag 26 1 read-only OBLRSTF Option byte loader reset flag 25 1 read-only RMVF Remove reset flag 23 1 read-write MSISRANGE SI range after Standby mode 8 4 read-write LSIPREDIV LSIPREDIV 4 1 read-write LSIRDY LSI oscillator ready 1 1 read-only LSION LSI oscillator enable 0 1 read-write CRRCR CRRCR Clock recovery RC register 0x98 0x20 0x00000000 HSI48ON HSI48 clock enable 0 1 read-write HSI48RDY HSI48 clock ready flag 1 1 read-only HSI48CAL HSI48 clock calibration 7 9 read-only CCIPR2 CCIPR2 Peripherals independent clock configuration register 0x9C 0x20 read-write 0x00000000 I2C4SEL I2C4 clock source selection 0 2 DFSDMSEL Digital filter for sigma delta modulator kernel clock source selection 2 1 ADFSDMSEL Digital filter for sigma delta modulator audio clock source selection 3 2 SAI1SEL SAI1 clock source selection 5 3 SAI2SEL SAI2 clock source selection 8 3 SDMMCSEL SDMMC clock selection 14 1 OSPISEL Octospi clock source selection 20 2 SECCFGR SECCFGR RCC secure configuration register 0xB8 0x20 read-write 0x00000000 HSISEC HSISEC 0 1 HSESEC HSESEC 1 1 MSISEC MSISEC 2 1 LSISEC LSISEC 3 1 LSESEC LSESEC 4 1 SYSCLKSEC SYSCLKSEC 5 1 PRESCSEC PRESCSEC 6 1 PLLSEC PLLSEC 7 1 PLLSAI1SEC PLLSAI1SEC 8 1 PLLSAI2SEC PLLSAI2SEC 9 1 CLK48MSEC CLK48MSEC 10 1 HSI48SEC HSI48SEC 11 1 RMVFSEC RMVFSEC 12 1 SECSR SECSR RCC secure status register 0xBC 0x20 read-write 0x00000000 RMVFSECF RMVFSECF 12 1 HSI48SECF HSI48SECF 11 1 CLK48MSECF CLK48MSECF 10 1 PLLSAI2SECF PLLSAI2SECF 9 1 PLLSAI1SECF PLLSAI1SECF 8 1 PLLSECF PLLSECF 7 1 PRESCSECF PRESCSECF 6 1 SYSCLKSECF SYSCLKSECF 5 1 LSESECF LSESECF 4 1 LSISECF LSISECF 3 1 MSISECF MSISECF 2 1 HSESECF HSESECF 1 1 HSISECF HSISECF 0 1 AHB1SECSR AHB1SECSR RCC AHB1 security status register 0xE8 0x20 read-only 0x00400300 ICACHESECF ICACHESECF 23 1 GTZCSECF GTZCSECF 22 1 TSCSECF TSCSECF 16 1 CRCSECF CRCSECF 12 1 SRAM1SECF SRAM1SECF 9 1 FLASHSECF FLASHSECF 8 1 DMAMUX1SECF DMAMUX1SECF 2 1 DMA2SECF DMA2SECF 1 1 DMA1SECF DMA1SECF 0 1 AHB2SECSR AHB2SECSR RCC AHB2 security status register 0xEC 0x20 read-only 0x002002FF SDMMC1SECF SDMMC1SECF 22 1 OTFDEC1SECF OTFDEC1SECF 21 1 SRAM2SECF SRAM2SECF 9 1 GPIOHSECF GPIOHSECF 7 1 GPIOGSECF GPIOGSECF 6 1 GPIOFSECF GPIOFSECF 5 1 GPIOESECF GPIOESECF 4 1 GPIODSECF GPIODSECF 3 1 GPIOCSECF GPIOCSECF 2 1 GPIOBSECF GPIOBSECF 1 1 GPIOASECF GPIOASECF 0 1 AHB3SECSR AHB3SECSR RCC AHB3 security status register 0xF0 0x20 read-only 0x00000000 OSPI1SECF OSPI1SECF 8 1 FSMCSECF FSMCSECF 0 1 APB1SECSR1 APB1SECSR1 RCC APB1 security status register 1 0xF8 0x20 read-only 0x00000400 LPTIM1SECF LPTIM1SECF 31 1 OPAMPSECF OPAMPSECF 30 1 DACSECF DACSECF 29 1 PWRSECF PWRSECF 28 1 CRSSECF CRSSECF 24 1 I2C3SECF I2C3SECF 23 1 I2C2SECF I2C2SECF 22 1 I2C1SECF I2C1SECF 21 1 UART5SECF UART5SECF 20 1 UART4SECF UART4SECF 19 1 UART3SECF UART3SECF 18 1 UART2SECF UART2SECF 17 1 SPI3SECF SPI3SECF 15 1 SPI2SECF SPI2SECF 14 1 WWDGSECF WWDGSECF 11 1 RTCAPBSECF RTCAPBSECF 10 1 TIM7SECF TIM7SECF 5 1 TIM6SECF TIM6SECF 4 1 TIM5SECF TIM5SECF 3 1 TIM4SECF TIM4SECF 2 1 TIM3SECF TIM3SECF 1 1 TIM2SECF TIM2SECF 0 1 APB1SECSR2 APB1SECSR2 RCC APB1 security status register 2 0xFC 0x20 read-only 0x00000000 UCPD1SECF UCPD1SECF 23 1 USBFSSECF USBFSSECF 21 1 FDCAN1SECF FDCAN1SECF 9 1 LPTIM3SECF LPTIM3SECF 6 1 LPTIM2SECF LPTIM2SECF 5 1 I2C4SECF I2C4SECF 1 1 LPUART1SECF LPUART1SECF 0 1 APB2SECSR APB2SECSR RCC APB2 security status register 0x100 0x20 read-only 0x00000000 DFSDM1SECF DFSDM1SECF 24 1 SAI2SECF SAI2SECF 22 1 SAI1SECF SAI1SECF 21 1 TIM17SECF TIM17SECF 18 1 TIM16SECF TIM16SECF 17 1 TIM15SECF TIM15SECF 16 1 USART1SECF USART1SECF 14 1 TIM8SECF TIM8SECF 13 1 SPI1SECF SPI1SECF 12 1 TIM1SECF TIM1SECF 11 1 SYSCFGSECF SYSCFGSECF 0 1 SEC_RCC !(DCB->DSCSR & (1 << 16)) 0x50021000 RTC Real-time clock RTC 0x40002800 0x0 0x400 registers RTC RTC global interrupts (EXTI line 17) 002 RTC_S RTC secure global interrupts (EXTI line 18) 003 TR TR time register 0x0 0x20 read-write 0x00000000 PM AM/PM notation 22 1 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 DR DR date register 0x4 0x20 read-write 0x00002101 YT Year tens in BCD format 20 4 YU Year units in BCD format 16 4 WDU Week day units 13 3 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 SSR SSR RTC sub second register 0x8 0x20 read-only 0x00000000 SS SS 0 16 ICSR ICSR RTC initialization control and status register 0xC 0x20 0x00000007 ALRAWF Alarm A write flag 0 1 read-only ALRBWF Alarm B write flag 1 1 read-only WUTWF Wakeup timer write flag 2 1 read-only SHPF Shift operation pending 3 1 read-write INITS Initialization status flag 4 1 read-only RSF Registers synchronization flag 5 1 read-write INITF Initialization flag 6 1 read-only INIT Initialization mode 7 1 read-write RECALPF Recalibration pending Flag 16 1 read-only PRER PRER prescaler register 0x10 0x20 read-write 0x007F00FF PREDIV_A Asynchronous prescaler factor 16 7 PREDIV_S Synchronous prescaler factor 0 15 WUTR WUTR wakeup timer register 0x14 0x20 read-write 0x0000FFFF WUT Wakeup auto-reload value bits 0 16 WUTOCLR WUTOCLR 16 16 CR CR RTC control register 0x18 0x20 read-write 0x00000000 WUCKSEL WUCKSEL 0 3 TSEDGE TSEDGE 3 1 REFCKON REFCKON 4 1 BYPSHAD BYPSHAD 5 1 FMT FMT 6 1 ALRAE ALRAE 8 1 ALRBE ALRBE 9 1 WUTE WUTE 10 1 TSE TSE 11 1 ALRAIE ALRAIE 12 1 ALRBIE ALRBIE 13 1 WUTIE WUTIE 14 1 TSIE TSIE 15 1 ADD1H ADD1H 16 1 SUB1H SUB1H 17 1 BKP BKP 18 1 COSEL COSEL 19 1 POL POL 20 1 OSEL OSEL 21 2 COE COE 23 1 ITSE ITSE 24 1 TAMPTS TAMPTS 25 1 TAMPOE TAMPOE 26 1 TAMPALRM_PU TAMPALRM_PU 29 1 TAMPALRM_TYPE TAMPALRM_TYPE 30 1 OUT2EN OUT2EN 31 1 PRIVCR PRIVCR RTC privilege mode control register 0x1C 0x20 read-write 0x00000000 PRIV PRIV 15 1 INITPRIV INITPRIV 14 1 CALPRIV CALPRIV 13 1 TSPRIV TSPRIV 3 1 WUTPRIV WUTPRIV 2 1 ALRBPRIV ALRBPRIV 1 1 ALRAPRIV ALRAPRIV 0 1 SMCR SMCR RTC secure mode control register 0x20 0x20 read-write 0x0000E00F DECPROT DECPROT 15 1 INITDPROT INITDPROT 14 1 CALDPROT CALDPROT 13 1 TSDPROT TSDPROT 3 1 WUTDPROT WUTDPROT 2 1 ALRBDPROT ALRBDPROT 1 1 ALRADPROT ALRADPROT 0 1 WPR WPR write protection register 0x24 0x20 write-only 0x00000000 KEY Write protection key 0 8 CALR CALR calibration register 0x28 0x20 read-write 0x00000000 CALP Increase frequency of RTC by 488.5 ppm 15 1 CALW8 Use an 8-second calibration cycle period 14 1 CALW16 Use a 16-second calibration cycle period 13 1 LPCAL LPCAL 12 1 CALM Calibration minus 0 9 SHIFTR SHIFTR shift control register 0x2C 0x20 write-only 0x00000000 ADD1S Add one second 31 1 SUBFS Subtract a fraction of a second 0 15 TSTR TSTR time stamp time register 0x30 0x20 read-only 0x00000000 SU Second units in BCD format 0 4 ST Second tens in BCD format 4 3 MNU Minute units in BCD format 8 4 MNT Minute tens in BCD format 12 3 HU Hour units in BCD format 16 4 HT Hour tens in BCD format 20 2 PM AM/PM notation 22 1 TSDR TSDR time stamp date register 0x34 0x20 read-only 0x00000000 WDU Week day units 13 3 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 TSSSR TSSSR timestamp sub second register 0x38 0x20 read-only 0x00000000 SS Sub second value 0 16 ALRMAR ALRMAR alarm A register 0x40 0x20 read-write 0x00000000 MSK4 Alarm A date mask 31 1 WDSEL Week day selection 30 1 DT Date tens in BCD format 28 2 DU Date units or day in BCD format 24 4 MSK3 Alarm A hours mask 23 1 PM AM/PM notation 22 1 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MSK2 Alarm A minutes mask 15 1 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 MSK1 Alarm A seconds mask 7 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 ALRMASSR ALRMASSR alarm A sub second register 0x44 0x20 read-write 0x00000000 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 ALRMBR ALRMBR alarm B register 0x48 0x20 read-write 0x00000000 MSK4 Alarm B date mask 31 1 WDSEL Week day selection 30 1 DT Date tens in BCD format 28 2 DU Date units or day in BCD format 24 4 MSK3 Alarm B hours mask 23 1 PM AM/PM notation 22 1 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MSK2 Alarm B minutes mask 15 1 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 MSK1 Alarm B seconds mask 7 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 ALRMBSSR ALRMBSSR alarm B sub second register 0x4C 0x20 read-write 0x00000000 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 SR SR RTC status register 0x50 0x20 read-only 0x00000000 ALRAF ALRAF 0 1 ALRBF ALRBF 1 1 WUTF WUTF 2 1 TSF TSF 3 1 TSOVF TSOVF 4 1 ITSF ITSF 5 1 MISR MISR RTC non-secure masked interrupt status register 0x54 0x20 read-only 0x00000000 ALRAMF ALRAMF 0 1 ALRBMF ALRBMF 1 1 WUTMF WUTMF 2 1 TSMF TSMF 3 1 TSOVMF TSOVMF 4 1 ITSMF ITSMF 5 1 SMISR SMISR RTC secure masked interrupt status register 0x58 0x20 read-only 0x00000000 ALRAMF ALRAMF 0 1 ALRBMF ALRBMF 1 1 WUTMF WUTMF 2 1 TSMF TSMF 3 1 TSOVMF TSOVMF 4 1 ITSMF ITSMF 5 1 SCR SCR RTC status clear register 0x5C 0x20 write-only 0x00000000 CALRAF CALRAF 0 1 CALRBF CALRBF 1 1 CWUTF CWUTF 2 1 CTSF CTSF 3 1 CTSOVF CTSOVF 4 1 CITSF CITSF 5 1 SEC_RTC !(DCB->DSCSR & (1 << 16)) 0x50002800 SAI1 Serial audio interface SAI 0x40015400 0x0 0x400 registers SAI1 SAI1 global interrupt 090 BCR1 BCR1 BConfiguration register 1 0x24 0x20 read-write 0x00000040 MCJDIV Master clock divider 20 4 NODIV No divider 19 1 DMAEN DMA enable 17 1 SAIBEN Audio block B enable 16 1 OutDri Output drive 13 1 MONO Mono mode 12 1 SYNCEN Synchronization enable 10 2 CKSTR Clock strobing edge 9 1 LSBFIRST Least significant bit first 8 1 DS Data size 5 3 PRTCFG Protocol configuration 2 2 MODE Audio block mode 0 2 OSR Oversampling ratio for master clock 26 1 BCR2 BCR2 BConfiguration register 2 0x28 0x20 read-write 0x00000000 COMP Companding mode 14 2 CPL Complement bit 13 1 MUTECN Mute counter 7 6 MUTEVAL Mute value 6 1 MUTE Mute 5 1 TRIS Tristate management on data line 4 1 FFLUS FIFO flush 3 1 FTH FIFO threshold 0 3 BFRCR BFRCR BFRCR 0x2C 0x20 read-write 0x00000007 FSOFF Frame synchronization offset 18 1 FSPOL Frame synchronization polarity 17 1 FSDEF Frame synchronization definition 16 1 FSALL Frame synchronization active level length 8 7 FRL Frame length 0 8 BSLOTR BSLOTR BSlot register 0x30 0x20 read-write 0x00000000 SLOTEN Slot enable 16 16 NBSLOT Number of slots in an audio frame 8 4 SLOTSZ Slot size 6 2 FBOFF First bit offset 0 5 BIM BIM BInterrupt mask register2 0x34 0x20 read-write 0x00000000 LFSDETIE Late frame synchronization detection interrupt enable 6 1 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 CNRDYIE Codec not ready interrupt enable 4 1 FREQIE FIFO request interrupt enable 3 1 WCKCFG Wrong clock configuration interrupt enable 2 1 MUTEDET Mute detection interrupt enable 1 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 BSR BSR BStatus register 0x38 0x20 read-only 0x00000000 FLVL FIFO level threshold 16 3 LFSDET Late frame synchronization detection 6 1 AFSDET Anticipated frame synchronization detection 5 1 CNRDY Codec not ready 4 1 FREQ FIFO request 3 1 WCKCFG Wrong clock configuration flag 2 1 MUTEDET Mute detection 1 1 OVRUDR Overrun / underrun 0 1 BCLRFR BCLRFR BClear flag register 0x3C 0x20 write-only 0x00000000 LFSDET Clear late frame synchronization detection flag 6 1 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CNRDY Clear codec not ready flag 4 1 WCKCFG Clear wrong clock configuration flag 2 1 MUTEDET Mute detection flag 1 1 OVRUDR Clear overrun / underrun 0 1 BDR BDR BData register 0x40 0x20 read-write 0x00000000 DATA Data 0 32 ACR1 ACR1 AConfiguration register 1 0x4 0x20 read-write 0x00000040 MCJDIV Master clock divider 20 4 NODIV No divider 19 1 DMAEN DMA enable 17 1 SAIAEN Audio block A enable 16 1 OutDri Output drive 13 1 MONO Mono mode 12 1 SYNCEN Synchronization enable 10 2 CKSTR Clock strobing edge 9 1 LSBFIRST Least significant bit first 8 1 DS Data size 5 3 PRTCFG Protocol configuration 2 2 MODE Audio block mode 0 2 OSR OSR 26 1 ACR2 ACR2 AConfiguration register 2 0x8 0x20 read-write 0x00000000 COMP Companding mode 14 2 CPL Complement bit 13 1 MUTECN Mute counter 7 6 MUTEVAL Mute value 6 1 MUTE Mute 5 1 TRIS Tristate management on data line 4 1 FFLUS FIFO flush 3 1 FTH FIFO threshold 0 3 AFRCR AFRCR AFRCR 0xC 0x20 read-write 0x00000007 FSOFF Frame synchronization offset 18 1 FSPOL Frame synchronization polarity 17 1 FSDEF Frame synchronization definition 16 1 FSALL Frame synchronization active level length 8 7 FRL Frame length 0 8 ASLOTR ASLOTR ASlot register 0x10 0x20 read-write 0x00000000 SLOTEN Slot enable 16 16 NBSLOT Number of slots in an audio frame 8 4 SLOTSZ Slot size 6 2 FBOFF First bit offset 0 5 AIM AIM AInterrupt mask register2 0x14 0x20 read-write 0x00000000 LFSDET Late frame synchronization detection interrupt enable 6 1 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 CNRDYIE Codec not ready interrupt enable 4 1 FREQIE FIFO request interrupt enable 3 1 WCKCFG Wrong clock configuration interrupt enable 2 1 MUTEDET Mute detection interrupt enable 1 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 ASR ASR AStatus register 0x18 0x20 read-write 0x00000000 FLVL FIFO level threshold 16 3 LFSDET Late frame synchronization detection 6 1 AFSDET Anticipated frame synchronization detection 5 1 CNRDY Codec not ready 4 1 FREQ FIFO request 3 1 WCKCFG Wrong clock configuration flag. This bit is read only 2 1 MUTEDET Mute detection 1 1 OVRUDR Overrun / underrun 0 1 ACLRFR ACLRFR AClear flag register 0x1C 0x20 read-write 0x00000000 LFSDET Clear late frame synchronization detection flag 6 1 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CNRDY Clear codec not ready flag 4 1 WCKCFG Clear wrong clock configuration flag 2 1 MUTEDET Mute detection flag 1 1 OVRUDR Clear overrun / underrun 0 1 ADR ADR AData register 0x20 0x20 read-write 0x00000000 DATA Data 0 32 GCR GCR Global configuration register 0x0 0x20 read-write 0x00000000 SYNCIN Synchronization inputs 0 2 SYNCOUT Synchronization outputs 4 2 PDMCR PDMCR PDM control register 0x44 0x20 read-write 0x00000000 PDMEN PDM enable 0 1 MICNBR MICNBR 4 2 CKEN1 Clock enable of bitstream clock number 1 8 1 CKEN2 CKEN2 9 1 PDMDLY PDMDLY PDM delay register 0x48 0x20 read-write 0x00000000 DLYM1L Delay line adjust for first microphone of pair 1 0 3 DLYM1R Delay line adjust for second microphone of pair 1 4 3 DLYM2L Delay line for first microphone of pair 2 8 3 DLYM2R Delay line for second microphone of pair 2 12 3 DLYM3L DLYM3L 16 3 DLYM3R DLYM3R 20 3 DLYM4L DLYM4L 24 3 DLYM4R DLYM4R 28 3 SAI2 0x40015800 SAI2 SAI2 global interrupt 091 SEC_SAI1 !(DCB->DSCSR & (1 << 16)) 0x50015400 SEC_SAI2 !(DCB->DSCSR & (1 << 16)) 0x50015800 DMA1 Direct memory access controller DMA 0x40020000 0x0 0x400 registers DMA1_Channel1 DMA1 Channel1 global interrupt 029 DMA1_Channel2 DMA1 Channel2 global interrupt 030 DMA1_Channel3 DMA1 Channel3 interrupt 031 DMA1_Channel4 DMA1 Channel4 interrupt 032 DMA1_Channel5 DMA1 Channel5 interrupt 033 DMA1_Channel6 DMA1 Channel6 interrupt 034 DMA1_Channel7 DMA1 Channel 7 interrupt 035 DMA1_Channel8 DMA1_Channel8 036 ISR ISR interrupt status register 0x0 0x20 read-only 0x00000000 TEIF7 Channel x transfer error flag (x = 1 ..7) 27 1 HTIF7 Channel x half transfer flag (x = 1 ..7) 26 1 TCIF7 Channel x transfer complete flag (x = 1 ..7) 25 1 GIF7 Channel x global interrupt flag (x = 1 ..7) 24 1 TEIF6 Channel x transfer error flag (x = 1 ..7) 23 1 HTIF6 Channel x half transfer flag (x = 1 ..7) 22 1 TCIF6 Channel x transfer complete flag (x = 1 ..7) 21 1 GIF6 Channel x global interrupt flag (x = 1 ..7) 20 1 TEIF5 Channel x transfer error flag (x = 1 ..7) 19 1 HTIF5 Channel x half transfer flag (x = 1 ..7) 18 1 TCIF5 Channel x transfer complete flag (x = 1 ..7) 17 1 GIF5 Channel x global interrupt flag (x = 1 ..7) 16 1 TEIF4 Channel x transfer error flag (x = 1 ..7) 15 1 HTIF4 Channel x half transfer flag (x = 1 ..7) 14 1 TCIF4 Channel x transfer complete flag (x = 1 ..7) 13 1 GIF4 Channel x global interrupt flag (x = 1 ..7) 12 1 TEIF3 Channel x transfer error flag (x = 1 ..7) 11 1 HTIF3 Channel x half transfer flag (x = 1 ..7) 10 1 TCIF3 Channel x transfer complete flag (x = 1 ..7) 9 1 GIF3 Channel x global interrupt flag (x = 1 ..7) 8 1 TEIF2 Channel x transfer error flag (x = 1 ..7) 7 1 HTIF2 Channel x half transfer flag (x = 1 ..7) 6 1 TCIF2 Channel x transfer complete flag (x = 1 ..7) 5 1 GIF2 Channel x global interrupt flag (x = 1 ..7) 4 1 TEIF1 Channel x transfer error flag (x = 1 ..7) 3 1 HTIF1 Channel x half transfer flag (x = 1 ..7) 2 1 TCIF1 Channel x transfer complete flag (x = 1 ..7) 1 1 GIF1 Channel x global interrupt flag (x = 1 ..7) 0 1 GIF8 global interrupt flag for channel 8 28 1 TCIF8 transfer complete (TC) flag for channel 8 29 1 HTIF8 half transfer (HT) flag for channel 8 30 1 TEIF8 transfer error (TE) flag for channel 8 31 1 IFCR IFCR interrupt flag clear register 0x4 0x20 write-only 0x00000000 CTEIF7 Channel x transfer error clear (x = 1 ..7) 27 1 CHTIF7 Channel x half transfer clear (x = 1 ..7) 26 1 CTCIF7 Channel x transfer complete clear (x = 1 ..7) 25 1 CGIF7 Channel x global interrupt clear (x = 1 ..7) 24 1 CTEIF6 Channel x transfer error clear (x = 1 ..7) 23 1 CHTIF6 Channel x half transfer clear (x = 1 ..7) 22 1 CTCIF6 Channel x transfer complete clear (x = 1 ..7) 21 1 CGIF6 Channel x global interrupt clear (x = 1 ..7) 20 1 CTEIF5 Channel x transfer error clear (x = 1 ..7) 19 1 CHTIF5 Channel x half transfer clear (x = 1 ..7) 18 1 CTCIF5 Channel x transfer complete clear (x = 1 ..7) 17 1 CGIF5 Channel x global interrupt clear (x = 1 ..7) 16 1 CTEIF4 Channel x transfer error clear (x = 1 ..7) 15 1 CHTIF4 Channel x half transfer clear (x = 1 ..7) 14 1 CTCIF4 Channel x transfer complete clear (x = 1 ..7) 13 1 CGIF4 Channel x global interrupt clear (x = 1 ..7) 12 1 CTEIF3 Channel x transfer error clear (x = 1 ..7) 11 1 CHTIF3 Channel x half transfer clear (x = 1 ..7) 10 1 CTCIF3 Channel x transfer complete clear (x = 1 ..7) 9 1 CGIF3 Channel x global interrupt clear (x = 1 ..7) 8 1 CTEIF2 Channel x transfer error clear (x = 1 ..7) 7 1 CHTIF2 Channel x half transfer clear (x = 1 ..7) 6 1 CTCIF2 Channel x transfer complete clear (x = 1 ..7) 5 1 CGIF2 Channel x global interrupt clear (x = 1 ..7) 4 1 CTEIF1 Channel x transfer error clear (x = 1 ..7) 3 1 CHTIF1 Channel x half transfer clear (x = 1 ..7) 2 1 CTCIF1 Channel x transfer complete clear (x = 1 ..7) 1 1 CGIF1 Channel x global interrupt clear (x = 1 ..7) 0 1 CGIF8 global interrupt flag clear for channel 8 28 1 CTCIF8 transfer complete flag clear for channel 8 29 1 CHTIF8 half transfer flag clear for channel 8 30 1 CTEIF8 transfer error flag clear for channel 8 31 1 CCR1 CCR1 channel x configuration register 0x8 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 DBM double-buffer mode 15 1 CT current target memory of DMA transfer in double-buffer mode 16 1 SECM secure mode 17 1 SSEC security of the DMA transfer from the source 18 1 DSEC security of the DMA transfer to the destination 19 1 PRIV privileged mode 20 1 CNDTR1 CNDTR1 channel x number of data register 0xC 0x20 read-write 0x00000000 NDT Number of data to transfer 0 18 CPAR1 CPAR1 channel x peripheral address register 0x10 0x20 read-write 0x00000000 PA Peripheral address 0 32 CM0AR1 CM0AR1 channel x memory address register 0x14 0x20 read-write 0x00000000 MA Memory address 0 32 CM1AR1 CM1AR1 channel x memory address register 0x18 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 DBM double-buffer mode 15 1 CT current target memory of DMA transfer in double-buffer mode 16 1 SECM secure mode 17 1 SSEC security of the DMA transfer from the source 18 1 DSEC security of the DMA transfer to the destination 19 1 PRIV privileged mode 20 1 CCR2 CCR2 channel x configuration register 0x1C 0x20 read-write 0x00000000 NDT Number of data to transfer 0 18 CNDTR2 CNDTR2 channel x number of data register 0x20 0x20 read-write 0x00000000 PA Peripheral address 0 32 CPAR2 CPAR2 channel x peripheral address register 0x24 0x20 read-write 0x00000000 MA Memory address 0 32 CM0AR2 CM0AR2 channel x memory address register 0x28 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 DBM double-buffer mode 15 1 CT current target memory of DMA transfer in double-buffer mode 16 1 SECM secure mode 17 1 SSEC security of the DMA transfer from the source 18 1 DSEC security of the DMA transfer to the destination 19 1 PRIV privileged mode 20 1 CM1AR2 CM1AR2 channel x memory address register 0x2C 0x20 read-write 0x00000000 NDT Number of data to transfer 0 18 CCR3 CCR3 channel x configuration register 0x30 0x20 read-write 0x00000000 PA Peripheral address 0 32 CNDTR3 CNDTR3 channel x number of data register 0x34 0x20 read-write 0x00000000 MA Memory address 0 32 CPAR3 CPAR3 channel x peripheral address register 0x38 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 DBM double-buffer mode 15 1 CT current target memory of DMA transfer in double-buffer mode 16 1 SECM secure mode 17 1 SSEC security of the DMA transfer from the source 18 1 DSEC security of the DMA transfer to the destination 19 1 PRIV privileged mode 20 1 CM0AR3 CM0AR3 channel x memory address register 0x3C 0x20 read-write 0x00000000 NDT Number of data to transfer 0 18 CM1AR3 CM1AR3 channel x memory address register 0x40 0x20 read-write 0x00000000 PA Peripheral address 0 32 CCR4 CCR4 channel x configuration register 0x44 0x20 read-write 0x00000000 MA Memory address 0 32 CNDTR4 CNDTR4 channel x number of data register 0x48 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 DBM double-buffer mode 15 1 CT current target memory of DMA transfer in double-buffer mode 16 1 SECM secure mode 17 1 SSEC security of the DMA transfer from the source 18 1 DSEC security of the DMA transfer to the destination 19 1 PRIV privileged mode 20 1 CPAR4 CPAR4 channel x peripheral address register 0x4C 0x20 read-write 0x00000000 NDT Number of data to transfer 0 18 CM0AR4 CM0AR4 channel x memory address register 0x50 0x20 read-write 0x00000000 PA Peripheral address 0 32 CM1AR4 CM1AR4 channel x memory address register 0x54 0x20 read-write 0x00000000 MA Memory address 0 32 CCR5 CCR5 channel x configuration register 0x58 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 DBM double-buffer mode 15 1 CT current target memory of DMA transfer in double-buffer mode 16 1 SECM secure mode 17 1 SSEC security of the DMA transfer from the source 18 1 DSEC security of the DMA transfer to the destination 19 1 PRIV privileged mode 20 1 CNDTR5 CNDTR5 channel x number of data register 0x5C 0x20 read-write 0x00000000 NDT Number of data to transfer 0 18 CPAR5 CPAR5 channel x peripheral address register 0x60 0x20 read-write 0x00000000 PA Peripheral address 0 32 CM0AR5 CM0AR5 channel x memory address register 0x64 0x20 read-write 0x00000000 MA Memory address 0 32 CM1AR5 CM1AR5 channel x memory address register 0x68 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 DBM double-buffer mode 15 1 CT current target memory of DMA transfer in double-buffer mode 16 1 SECM secure mode 17 1 SSEC security of the DMA transfer from the source 18 1 DSEC security of the DMA transfer to the destination 19 1 PRIV privileged mode 20 1 CCR6 CCR6 channel x configuration register 0x6C 0x20 read-write 0x00000000 NDT Number of data to transfer 0 18 CNDTR6 CNDTR6 channel x number of data register 0x70 0x20 read-write 0x00000000 PA Peripheral address 0 32 CPAR6 CPAR6 channel x peripheral address register 0x74 0x20 read-write 0x00000000 MA Memory address 0 32 CM0AR6 CM0AR6 channel x memory address register 0x78 0x20 read-write 0x00000000 C7S DMA channel 7 selection 24 4 C6S DMA channel 6 selection 20 4 C5S DMA channel 5 selection 16 4 C4S DMA channel 4 selection 12 4 C3S DMA channel 3 selection 8 4 C2S DMA channel 2 selection 4 4 C1S DMA channel 1 selection 0 4 CM1AR6 CM1AR6 channel x memory address register 0x7C 0x20 read-write 0x00000000 MA peripheral address 0 32 CCR7 CCR7 channel x configuration register 0x80 0x20 read-write 0x00000000 MA peripheral address 0 32 CNDTR7 CNDTR7 channel x number of data register 0x84 0x20 read-write 0x00000000 MA peripheral address 0 32 CPAR7 CPAR7 channel x peripheral address register 0x88 0x20 read-write 0x00000000 MA peripheral address 0 32 CM0AR7 CM0AR7 channel x memory address register 0x8C 0x20 read-write 0x00000000 MA peripheral address 0 32 CM1AR7 CM1AR7 channel x memory address register 0x90 0x20 read-write 0x00000000 MA peripheral address 0 32 CCR8 CCR8 channel x configuration register 0x94 0x20 read-write 0x00000000 MA peripheral address 0 32 CNDTR8 CNDTR8 channel x number of data register 0x98 0x20 read-write 0x00000000 EN channel enable 0 1 TCIE transfer complete interrupt enable 1 1 HTIE half transfer interrupt enable 2 1 TEIE transfer error interrupt enable 3 1 DIR data transfer direction 4 1 CIRC circular mode 5 1 PINC peripheral increment mode 6 1 MINC memory increment mode 7 1 PSIZE peripheral size 8 2 MSIZE memory size 10 2 PL priority level 12 2 MEM2MEM memory-to-memory mode 14 1 DBM double-buffer mode 15 1 CT current target memory of DMA transfer in double-buffer mode 16 1 SECM secure mode 17 1 SSEC security of the DMA transfer from the source 18 1 DSEC security of the DMA transfer to the destination 19 1 PRIV privileged mode 20 1 CPAR8 CPAR8 channel x peripheral address register 0x9C 0x20 read-write 0x00000000 NDT number of data to transfer 0 18 CM0AR8 CM0AR8 channel x peripheral address register 0xA0 0x20 read-write 0x00000000 PA peripheral address 0 32 CM1AR8 CM1AR8 channel x peripheral address register 0xA4 0x20 read-write 0x00000000 MA peripheral address 0 32 CSELR CSELR channel selection register 0xA8 0x20 read-write 0x00000000 MA peripheral address 0 32 SEC_DMA1 !(DCB->DSCSR & (1 << 16)) 0x50020000 DMA2 0x40020400 DMA2_CH1 DMA2_CH1 080 DMA2_CH2 DMA2_CH2 081 DMA2_CH3 DMA2_CH3 082 DMA2_CH4 DMA2_CH4 083 DMA2_CH5 DMA2_CH5 084 DMA2_CH6 DMA2_CH6 085 DMA2_CH7 DMA2_CH7 086 DMA2_CH8 DMA2_CH8 087 SEC_DMA2 !(DCB->DSCSR & (1 << 16)) 0x50020400 SEC_GTZC_MPCBB1 SEC_GTZC_MPCBB1 SEC_GTZC !(DCB->DSCSR & (1 << 16)) 0x50032C00 0x0 0x400 registers MPCBB1_CR MPCBB1_CR MPCBB control register 0x0 0x20 read-write 0x00000000 LCK LCK 0 1 INVSECSTATE INVSECSTATE 30 1 SRWILADIS SRWILADIS 31 1 MPCBB1_LCKVTR1 MPCBB1_LCKVTR1 MPCBB control register 0x10 0x20 read-write 0x00000000 LCKSB0 LCKSB0 0 1 LCKSB1 LCKSB1 1 1 LCKSB2 LCKSB2 2 1 LCKSB3 LCKSB3 3 1 LCKSB4 LCKSB4 4 1 LCKSB5 LCKSB5 5 1 LCKSB6 LCKSB6 6 1 LCKSB7 LCKSB7 7 1 LCKSB8 LCKSB8 8 1 LCKSB9 LCKSB9 9 1 LCKSB10 LCKSB10 10 1 LCKSB11 LCKSB11 11 1 LCKSB12 LCKSB12 12 1 LCKSB13 LCKSB13 13 1 LCKSB14 LCKSB14 14 1 LCKSB15 LCKSB15 15 1 LCKSB16 LCKSB16 16 1 LCKSB17 LCKSB17 17 1 LCKSB18 LCKSB18 18 1 LCKSB19 LCKSB19 19 1 LCKSB20 LCKSB20 20 1 LCKSB21 LCKSB21 21 1 LCKSB22 LCKSB22 22 1 LCKSB23 LCKSB23 23 1 LCKSB24 LCKSB24 24 1 LCKSB25 LCKSB25 25 1 LCKSB26 LCKSB26 26 1 LCKSB27 LCKSB27 27 1 LCKSB28 LCKSB28 28 1 LCKSB29 LCKSB29 29 1 LCKSB30 LCKSB30 30 1 LCKSB31 LCKSB31 31 1 MPCBB1_LCKVTR2 MPCBB1_LCKVTR2 MPCBB control register 0x14 0x20 read-write 0x00000000 LCKSB32 LCKSB32 0 1 LCKSB33 LCKSB33 1 1 LCKSB34 LCKSB34 2 1 LCKSB35 LCKSB35 3 1 LCKSB36 LCKSB36 4 1 LCKSB37 LCKSB37 5 1 LCKSB38 LCKSB38 6 1 LCKSB39 LCKSB39 7 1 LCKSB40 LCKSB40 8 1 LCKSB41 LCKSB41 9 1 LCKSB42 LCKSB42 10 1 LCKSB43 LCKSB43 11 1 LCKSB44 LCKSB44 12 1 LCKSB45 LCKSB45 13 1 LCKSB46 LCKSB46 14 1 LCKSB47 LCKSB47 15 1 LCKSB48 LCKSB48 16 1 LCKSB49 LCKSB49 17 1 LCKSB50 LCKSB50 18 1 LCKSB51 LCKSB51 19 1 LCKSB52 LCKSB52 20 1 LCKSB53 LCKSB53 21 1 LCKSB54 LCKSB54 22 1 LCKSB55 LCKSB55 23 1 LCKSB56 LCKSB56 24 1 LCKSB57 LCKSB57 25 1 LCKSB58 LCKSB58 26 1 LCKSB59 LCKSB59 27 1 LCKSB60 LCKSB60 28 1 LCKSB61 LCKSB61 29 1 LCKSB62 LCKSB62 30 1 LCKSB63 LCKSB63 31 1 MPCBB1_VCTR0 MPCBB1_VCTR0 MPCBBx vector register 0x100 0x20 read-write 0xFFFFFFFF B0 B0 0 1 B1 B1 1 1 B2 B2 2 1 B3 B3 3 1 B4 B4 4 1 B5 B5 5 1 B6 B6 6 1 B7 B7 7 1 B8 B8 8 1 B9 B9 9 1 B10 B10 10 1 B11 B11 11 1 B12 B12 12 1 B13 B13 13 1 B14 B14 14 1 B15 B15 15 1 B16 B16 16 1 B17 B17 17 1 B18 B18 18 1 B19 B19 19 1 B20 B20 20 1 B21 B21 21 1 B22 B22 22 1 B23 B23 23 1 B24 B24 24 1 B25 B25 25 1 B26 B26 26 1 B27 B27 27 1 B28 B28 28 1 B29 B29 29 1 B30 B30 30 1 B31 B31 31 1 MPCBB1_VCTR1 MPCBB1_VCTR1 MPCBBx vector register 0x104 0x20 read-write 0xFFFFFFFF B32 B32 0 1 B33 B33 1 1 B34 B34 2 1 B35 B35 3 1 B36 B36 4 1 B37 B37 5 1 B38 B38 6 1 B39 B39 7 1 B40 B40 8 1 B41 B41 9 1 B42 B42 10 1 B43 B43 11 1 B44 B44 12 1 B45 B45 13 1 B46 B46 14 1 B47 B47 15 1 B48 B48 16 1 B49 B49 17 1 B50 B50 18 1 B51 B51 19 1 B52 B52 20 1 B53 B53 21 1 B54 B54 22 1 B55 B55 23 1 B56 B56 24 1 B57 B57 25 1 B58 B58 26 1 B59 B59 27 1 B60 B60 28 1 B61 B61 29 1 B62 B62 30 1 B63 B63 31 1 MPCBB1_VCTR2 MPCBB1_VCTR2 MPCBBx vector register 0x108 0x20 read-write 0xFFFFFFFF B64 B64 0 1 B65 B65 1 1 B66 B66 2 1 B67 B67 3 1 B68 B68 4 1 B69 B69 5 1 B70 B70 6 1 B71 B71 7 1 B72 B72 8 1 B73 B73 9 1 B74 B74 10 1 B75 B75 11 1 B76 B76 12 1 B77 B77 13 1 B78 B78 14 1 B79 B79 15 1 B80 B80 16 1 B81 B81 17 1 B82 B82 18 1 B83 B83 19 1 B84 B84 20 1 B85 B85 21 1 B86 B86 22 1 B87 B87 23 1 B88 B88 24 1 B89 B89 25 1 B90 B90 26 1 B91 B91 27 1 B92 B92 28 1 B93 B93 29 1 B94 B94 30 1 B95 B95 31 1 MPCBB1_VCTR3 MPCBB1_VCTR3 MPCBBx vector register 0x10C 0x20 read-write 0xFFFFFFFF B96 B96 0 1 B97 B97 1 1 B98 B98 2 1 B99 B99 3 1 B100 B100 4 1 B101 B101 5 1 B102 B102 6 1 B103 B103 7 1 B104 B104 8 1 B105 B105 9 1 B106 B106 10 1 B107 B107 11 1 B108 B108 12 1 B109 B109 13 1 B110 B110 14 1 B111 B111 15 1 B112 B112 16 1 B113 B113 17 1 B114 B114 18 1 B115 B115 19 1 B116 B116 20 1 B117 B117 21 1 B118 B118 22 1 B119 B119 23 1 B120 B120 24 1 B121 B121 25 1 B122 B122 26 1 B123 B123 27 1 B124 B124 28 1 B125 B125 29 1 B126 B126 30 1 B127 B127 31 1 MPCBB1_VCTR4 MPCBB1_VCTR4 MPCBBx vector register 0x110 0x20 read-write 0x00000000 B128 B128 0 1 B129 B129 1 1 B130 B130 2 1 B131 B131 3 1 B132 B132 4 1 B133 B133 5 1 B134 B134 6 1 B135 B135 7 1 B136 B136 8 1 B137 B137 9 1 B138 B138 10 1 B139 B139 11 1 B140 B140 12 1 B141 B141 13 1 B142 B142 14 1 B143 B143 15 1 B144 B144 16 1 B145 B145 17 1 B146 B146 18 1 B147 B147 19 1 B148 B148 20 1 B149 B149 21 1 B150 B150 22 1 B151 B151 23 1 B152 B152 24 1 B153 B153 25 1 B154 B154 26 1 B155 B155 27 1 B156 B156 28 1 B157 B157 29 1 B158 B158 30 1 B159 B159 31 1 MPCBB1_VCTR5 MPCBB1_VCTR5 MPCBBx vector register 0x114 0x20 read-write 0x00000000 B160 B160 0 1 B161 B161 1 1 B162 B162 2 1 B163 B163 3 1 B164 B164 4 1 B165 B165 5 1 B166 B166 6 1 B167 B167 7 1 B168 B168 8 1 B169 B169 9 1 B170 B170 10 1 B171 B171 11 1 B172 B172 12 1 B173 B173 13 1 B174 B174 14 1 B175 B175 15 1 B176 B176 16 1 B177 B177 17 1 B178 B178 18 1 B179 B179 19 1 B180 B180 20 1 B181 B181 21 1 B182 B182 22 1 B183 B183 23 1 B184 B184 24 1 B185 B185 25 1 B186 B186 26 1 B187 B187 27 1 B188 B188 28 1 B189 B189 29 1 B190 B190 30 1 B191 B191 31 1 MPCBB1_VCTR6 MPCBB1_VCTR6 MPCBBx vector register 0x118 0x20 read-write 0x00000000 B192 B192 0 1 B193 B193 1 1 B194 B194 2 1 B195 B195 3 1 B196 B196 4 1 B197 B197 5 1 B198 B198 6 1 B199 B199 7 1 B200 B200 8 1 B201 B201 9 1 B202 B202 10 1 B203 B203 11 1 B204 B204 12 1 B205 B205 13 1 B206 B206 14 1 B207 B207 15 1 B208 B208 16 1 B209 B209 17 1 B210 B210 18 1 B211 B211 19 1 B212 B212 20 1 B213 B213 21 1 B214 B214 22 1 B215 B215 23 1 B216 B216 24 1 B217 B217 25 1 B218 B218 26 1 B219 B219 27 1 B220 B220 28 1 B221 B221 29 1 B222 B222 30 1 B223 B223 31 1 MPCBB1_VCTR7 MPCBB1_VCTR7 MPCBBx vector register 0x11C 0x20 read-write 0x00000000 B224 B224 0 1 B225 B225 1 1 B226 B226 2 1 B227 B227 3 1 B228 B228 4 1 B229 B229 5 1 B230 B230 6 1 B231 B231 7 1 B232 B232 8 1 B233 B233 9 1 B234 B234 10 1 B235 B235 11 1 B236 B236 12 1 B237 B237 13 1 B238 B238 14 1 B239 B239 15 1 B240 B240 16 1 B241 B241 17 1 B242 B242 18 1 B243 B243 19 1 B244 B244 20 1 B245 B245 21 1 B246 B246 22 1 B247 B247 23 1 B248 B248 24 1 B249 B249 25 1 B250 B250 26 1 B251 B251 27 1 B252 B252 28 1 B253 B253 29 1 B254 B254 30 1 B255 B255 31 1 MPCBB1_VCTR8 MPCBB1_VCTR8 MPCBBx vector register 0x120 0x20 read-write 0x00000000 B256 B256 0 1 B257 B257 1 1 B258 B258 2 1 B259 B259 3 1 B260 B260 4 1 B261 B261 5 1 B262 B262 6 1 B263 B263 7 1 B264 B264 8 1 B265 B265 9 1 B266 B266 10 1 B267 B267 11 1 B268 B268 12 1 B269 B269 13 1 B270 B270 14 1 B271 B271 15 1 B272 B272 16 1 B273 B273 17 1 B274 B274 18 1 B275 B275 19 1 B276 B276 20 1 B277 B277 21 1 B278 B278 22 1 B279 B279 23 1 B280 B280 24 1 B281 B281 25 1 B282 B282 26 1 B283 B283 27 1 B284 B284 28 1 B285 B285 29 1 B286 B286 30 1 B287 B287 31 1 MPCBB1_VCTR9 MPCBB1_VCTR9 MPCBBx vector register 0x124 0x20 read-write 0x00000000 B288 B288 0 1 B289 B289 1 1 B290 B290 2 1 B291 B291 3 1 B292 B292 4 1 B293 B293 5 1 B294 B294 6 1 B295 B295 7 1 B296 B296 8 1 B297 B297 9 1 B298 B298 10 1 B299 B299 11 1 B300 B300 12 1 B301 B301 13 1 B302 B302 14 1 B303 B303 15 1 B304 B304 16 1 B305 B305 17 1 B306 B306 18 1 B307 B307 19 1 B308 B308 20 1 B309 B309 21 1 B310 B310 22 1 B311 B311 23 1 B312 B312 24 1 B313 B313 25 1 B314 B314 26 1 B315 B315 27 1 B316 B316 28 1 B317 B317 29 1 B318 B318 30 1 B319 B319 31 1 MPCBB1_VCTR10 MPCBB1_VCTR10 MPCBBx vector register 0x128 0x20 read-write 0x00000000 B320 B320 0 1 B321 B321 1 1 B322 B322 2 1 B323 B323 3 1 B324 B324 4 1 B325 B325 5 1 B326 B326 6 1 B327 B327 7 1 B328 B328 8 1 B329 B329 9 1 B330 B330 10 1 B331 B331 11 1 B332 B332 12 1 B333 B333 13 1 B334 B334 14 1 B335 B335 15 1 B336 B336 16 1 B337 B337 17 1 B338 B338 18 1 B339 B339 19 1 B340 B340 20 1 B341 B341 21 1 B342 B342 22 1 B343 B343 23 1 B344 B344 24 1 B345 B345 25 1 B346 B346 26 1 B347 B347 27 1 B348 B348 28 1 B349 B349 29 1 B350 B350 30 1 B351 B351 31 1 MPCBB1_VCTR11 MPCBB1_VCTR11 MPCBBx vector register 0x12C 0x20 read-write 0x00000000 B352 B352 0 1 B353 B353 1 1 B354 B354 2 1 B355 B355 3 1 B356 B356 4 1 B357 B357 5 1 B358 B358 6 1 B359 B359 7 1 B360 B360 8 1 B361 B361 9 1 B362 B362 10 1 B363 B363 11 1 B364 B364 12 1 B365 B365 13 1 B366 B366 14 1 B367 B367 15 1 B368 B368 16 1 B369 B369 17 1 B370 B370 18 1 B371 B371 19 1 B372 B372 20 1 B373 B373 21 1 B374 B374 22 1 B375 B375 23 1 B376 B376 24 1 B377 B377 25 1 B378 B378 26 1 B379 B379 27 1 B380 B380 28 1 B381 B381 29 1 B382 B382 30 1 B383 B383 31 1 MPCBB1_VCTR12 MPCBB1_VCTR12 MPCBBx vector register 0x130 0x20 read-write 0x00000000 B384 B384 0 1 B385 B385 1 1 B386 B386 2 1 B387 B387 3 1 B388 B388 4 1 B389 B389 5 1 B390 B390 6 1 B391 B391 7 1 B392 B392 8 1 B393 B393 9 1 B394 B394 10 1 B395 B395 11 1 B396 B396 12 1 B397 B397 13 1 B398 B398 14 1 B399 B399 15 1 B400 B400 16 1 B401 B401 17 1 B402 B402 18 1 B403 B403 19 1 B404 B404 20 1 B405 B405 21 1 B406 B406 22 1 B407 B407 23 1 B408 B408 24 1 B409 B409 25 1 B410 B410 26 1 B411 B411 27 1 B412 B412 28 1 B413 B413 29 1 B414 B414 30 1 B415 B415 31 1 MPCBB1_VCTR13 MPCBB1_VCTR13 MPCBBx vector register 0x134 0x20 read-write 0x00000000 B416 B416 0 1 B417 B417 1 1 B418 B418 2 1 B419 B419 3 1 B420 B420 4 1 B421 B421 5 1 B422 B422 6 1 B423 B423 7 1 B424 B424 8 1 B425 B425 9 1 B426 B426 10 1 B427 B427 11 1 B428 B428 12 1 B429 B429 13 1 B430 B430 14 1 B431 B431 15 1 B432 B432 16 1 B433 B433 17 1 B434 B434 18 1 B435 B435 19 1 B436 B436 20 1 B437 B437 21 1 B438 B438 22 1 B439 B439 23 1 B440 B440 24 1 B441 B441 25 1 B442 B442 26 1 B443 B443 27 1 B444 B444 28 1 B445 B445 29 1 B446 B446 30 1 B447 B447 31 1 MPCBB1_VCTR14 MPCBB1_VCTR14 MPCBBx vector register 0x138 0x20 read-write 0x00000000 B448 B448 0 1 B449 B449 1 1 B450 B450 2 1 B451 B451 3 1 B452 B452 4 1 B453 B453 5 1 B454 B454 6 1 B455 B455 7 1 B456 B456 8 1 B457 B457 9 1 B458 B458 10 1 B459 B459 11 1 B460 B460 12 1 B461 B461 13 1 B462 B462 14 1 B463 B463 15 1 B464 B464 16 1 B465 B465 17 1 B466 B466 18 1 B467 B467 19 1 B468 B468 20 1 B469 B469 21 1 B470 B470 22 1 B471 B471 23 1 B472 B472 24 1 B473 B473 25 1 B474 B474 26 1 B475 B475 27 1 B476 B476 28 1 B477 B477 29 1 B478 B478 30 1 B479 B479 31 1 MPCBB1_VCTR15 MPCBB1_VCTR15 MPCBBx vector register 0x13C 0x20 read-write 0x00000000 B480 B480 0 1 B481 B481 1 1 B482 B482 2 1 B483 B483 3 1 B484 B484 4 1 B485 B485 5 1 B486 B486 6 1 B487 B487 7 1 B488 B488 8 1 B489 B489 9 1 B490 B490 10 1 B491 B491 11 1 B492 B492 12 1 B493 B493 13 1 B494 B494 14 1 B495 B495 15 1 B496 B496 16 1 B497 B497 17 1 B498 B498 18 1 B499 B499 19 1 B500 B500 20 1 B501 B501 21 1 B502 B502 22 1 B503 B503 23 1 B504 B504 24 1 B505 B505 25 1 B506 B506 26 1 B507 B507 27 1 B508 B508 28 1 B509 B509 29 1 B510 B510 30 1 B511 B511 31 1 MPCBB1_VCTR16 MPCBB1_VCTR16 MPCBBx vector register 0x140 0x20 read-write 0x00000000 B512 B512 0 1 B513 B513 1 1 B514 B514 2 1 B515 B515 3 1 B516 B516 4 1 B517 B517 5 1 B518 B518 6 1 B519 B519 7 1 B520 B520 8 1 B521 B521 9 1 B522 B522 10 1 B523 B523 11 1 B524 B524 12 1 B525 B525 13 1 B526 B526 14 1 B527 B527 15 1 B528 B528 16 1 B529 B529 17 1 B530 B530 18 1 B531 B531 19 1 B532 B532 20 1 B533 B533 21 1 B534 B534 22 1 B535 B535 23 1 B536 B536 24 1 B537 B537 25 1 B538 B538 26 1 B539 B539 27 1 B540 B540 28 1 B541 B541 29 1 B542 B542 30 1 B543 B543 31 1 MPCBB1_VCTR17 MPCBB1_VCTR17 MPCBBx vector register 0x144 0x20 read-write 0x00000000 B544 B544 0 1 B545 B545 1 1 B546 B546 2 1 B547 B547 3 1 B548 B548 4 1 B549 B549 5 1 B550 B550 6 1 B551 B551 7 1 B552 B552 8 1 B553 B553 9 1 B554 B554 10 1 B555 B555 11 1 B556 B556 12 1 B557 B557 13 1 B558 B558 14 1 B559 B559 15 1 B560 B560 16 1 B561 B561 17 1 B562 B562 18 1 B563 B563 19 1 B564 B564 20 1 B565 B565 21 1 B566 B566 22 1 B567 B567 23 1 B568 B568 24 1 B569 B569 25 1 B570 B570 26 1 B571 B571 27 1 B572 B572 28 1 B573 B573 29 1 B574 B574 30 1 B575 B575 31 1 MPCBB1_VCTR18 MPCBB1_VCTR18 MPCBBx vector register 0x148 0x20 read-write 0x00000000 B576 B576 0 1 B577 B577 1 1 B578 B578 2 1 B579 B579 3 1 B580 B580 4 1 B581 B581 5 1 B582 B582 6 1 B583 B583 7 1 B584 B584 8 1 B585 B585 9 1 B586 B586 10 1 B587 B587 11 1 B588 B588 12 1 B589 B589 13 1 B590 B590 14 1 B591 B591 15 1 B592 B592 16 1 B593 B593 17 1 B594 B594 18 1 B595 B595 19 1 B596 B596 20 1 B597 B597 21 1 B598 B598 22 1 B599 B599 23 1 B600 B600 24 1 B601 B601 25 1 B602 B602 26 1 B603 B603 27 1 B604 B604 28 1 B605 B605 29 1 B606 B606 30 1 B607 B607 31 1 MPCBB1_VCTR19 MPCBB1_VCTR19 MPCBBx vector register 0x14C 0x20 read-write 0x00000000 B608 B608 0 1 B609 B609 1 1 B610 B610 2 1 B611 B611 3 1 B612 B612 4 1 B613 B613 5 1 B614 B614 6 1 B615 B615 7 1 B616 B616 8 1 B617 B617 9 1 B618 B618 10 1 B619 B619 11 1 B620 B620 12 1 B621 B621 13 1 B622 B622 14 1 B623 B623 15 1 B624 B624 16 1 B625 B625 17 1 B626 B626 18 1 B627 B627 19 1 B628 B628 20 1 B629 B629 21 1 B630 B630 22 1 B631 B631 23 1 B632 B632 24 1 B633 B633 25 1 B634 B634 26 1 B635 B635 27 1 B636 B636 28 1 B637 B637 29 1 B638 B638 30 1 B639 B639 31 1 MPCBB1_VCTR20 MPCBB1_VCTR20 MPCBBx vector register 0x150 0x20 read-write 0x00000000 B640 B640 0 1 B641 B641 1 1 B642 B642 2 1 B643 B643 3 1 B644 B644 4 1 B645 B645 5 1 B646 B646 6 1 B647 B647 7 1 B648 B648 8 1 B649 B649 9 1 B650 B650 10 1 B651 B651 11 1 B652 B652 12 1 B653 B653 13 1 B654 B654 14 1 B655 B655 15 1 B656 B656 16 1 B657 B657 17 1 B658 B658 18 1 B659 B659 19 1 B660 B660 20 1 B661 B661 21 1 B662 B662 22 1 B663 B663 23 1 B664 B664 24 1 B665 B665 25 1 B666 B666 26 1 B667 B667 27 1 B668 B668 28 1 B669 B669 29 1 B670 B670 30 1 B671 B671 31 1 MPCBB1_VCTR21 MPCBB1_VCTR21 MPCBBx vector register 0x154 0x20 read-write 0x00000000 B672 B672 0 1 B673 B673 1 1 B674 B674 2 1 B675 B675 3 1 B676 B676 4 1 B677 B677 5 1 B678 B678 6 1 B679 B679 7 1 B680 B680 8 1 B681 B681 9 1 B682 B682 10 1 B683 B683 11 1 B684 B684 12 1 B685 B685 13 1 B686 B686 14 1 B687 B687 15 1 B688 B688 16 1 B689 B689 17 1 B690 B690 18 1 B691 B691 19 1 B692 B692 20 1 B693 B693 21 1 B694 B694 22 1 B695 B695 23 1 B696 B696 24 1 B697 B697 25 1 B698 B698 26 1 B699 B699 27 1 B700 B700 28 1 B701 B701 29 1 B702 B702 30 1 B703 B703 31 1 MPCBB1_VCTR22 MPCBB1_VCTR22 MPCBBx vector register 0x158 0x20 read-write 0x00000000 B704 B704 0 1 B705 B705 1 1 B706 B706 2 1 B707 B707 3 1 B708 B708 4 1 B709 B709 5 1 B710 B710 6 1 B711 B711 7 1 B712 B712 8 1 B713 B713 9 1 B714 B714 10 1 B715 B715 11 1 B716 B716 12 1 B717 B717 13 1 B718 B718 14 1 B719 B719 15 1 B720 B720 16 1 B721 B721 17 1 B722 B722 18 1 B723 B723 19 1 B724 B724 20 1 B725 B725 21 1 B726 B726 22 1 B727 B727 23 1 B728 B728 24 1 B729 B729 25 1 B730 B730 26 1 B731 B731 27 1 B732 B732 28 1 B733 B733 29 1 B734 B734 30 1 B735 B735 31 1 MPCBB1_VCTR23 MPCBB1_VCTR23 MPCBBx vector register 0x15C 0x20 read-write 0x00000000 B736 B736 0 1 B737 B737 1 1 B738 B738 2 1 B739 B739 3 1 B740 B740 4 1 B741 B741 5 1 B742 B742 6 1 B743 B743 7 1 B744 B744 8 1 B745 B745 9 1 B746 B746 10 1 B747 B747 11 1 B748 B748 12 1 B749 B749 13 1 B750 B750 14 1 B751 B751 15 1 B752 B752 16 1 B753 B753 17 1 B754 B754 18 1 B755 B755 19 1 B756 B756 20 1 B757 B757 21 1 B758 B758 22 1 B759 B759 23 1 B760 B760 24 1 B761 B761 25 1 B762 B762 26 1 B763 B763 27 1 B764 B764 28 1 B765 B765 29 1 B766 B766 30 1 B767 B767 31 1 MPCBB1_VCTR24 MPCBB1_VCTR24 MPCBBx vector register 0x160 0x20 read-write 0x00000000 B768 B768 0 1 B769 B769 1 1 B770 B770 2 1 B771 B771 3 1 B772 B772 4 1 B773 B773 5 1 B774 B774 6 1 B775 B775 7 1 B776 B776 8 1 B777 B777 9 1 B778 B778 10 1 B779 B779 11 1 B780 B780 12 1 B781 B781 13 1 B782 B782 14 1 B783 B783 15 1 B784 B784 16 1 B785 B785 17 1 B786 B786 18 1 B787 B787 19 1 B788 B788 20 1 B789 B789 21 1 B790 B790 22 1 B791 B791 23 1 B792 B792 24 1 B793 B793 25 1 B794 B794 26 1 B795 B795 27 1 B796 B796 28 1 B797 B797 29 1 B798 B798 30 1 B799 B799 31 1 MPCBB1_VCTR25 MPCBB1_VCTR25 MPCBBx vector register 0x164 0x20 read-write 0x00000000 B800 B800 0 1 B801 B801 1 1 B802 B802 2 1 B803 B803 3 1 B804 B804 4 1 B805 B805 5 1 B806 B806 6 1 B807 B807 7 1 B808 B808 8 1 B809 B809 9 1 B810 B810 10 1 B811 B811 11 1 B812 B812 12 1 B813 B813 13 1 B814 B814 14 1 B815 B815 15 1 B816 B816 16 1 B817 B817 17 1 B818 B818 18 1 B819 B819 19 1 B820 B820 20 1 B821 B821 21 1 B822 B822 22 1 B823 B823 23 1 B824 B824 24 1 B825 B825 25 1 B826 B826 26 1 B827 B827 27 1 B828 B828 28 1 B829 B829 29 1 B830 B830 30 1 B831 B831 31 1 MPCBB1_VCTR26 MPCBB1_VCTR26 MPCBBx vector register 0x168 0x20 read-write 0x00000000 B832 B832 0 1 B833 B833 1 1 B834 B834 2 1 B835 B835 3 1 B836 B836 4 1 B837 B837 5 1 B838 B838 6 1 B839 B839 7 1 B840 B840 8 1 B841 B841 9 1 B842 B842 10 1 B843 B843 11 1 B844 B844 12 1 B845 B845 13 1 B846 B846 14 1 B847 B847 15 1 B848 B848 16 1 B849 B849 17 1 B850 B850 18 1 B851 B851 19 1 B852 B852 20 1 B853 B853 21 1 B854 B854 22 1 B855 B855 23 1 B856 B856 24 1 B857 B857 25 1 B858 B858 26 1 B859 B859 27 1 B860 B860 28 1 B861 B861 29 1 B862 B862 30 1 B863 B863 31 1 MPCBB1_VCTR27 MPCBB1_VCTR27 MPCBBx vector register 0x16C 0x20 read-write 0x00000000 B864 B864 0 1 B865 B865 1 1 B866 B866 2 1 B867 B867 3 1 B868 B868 4 1 B869 B869 5 1 B870 B870 6 1 B871 B871 7 1 B872 B872 8 1 B873 B873 9 1 B874 B874 10 1 B875 B875 11 1 B876 B876 12 1 B877 B877 13 1 B878 B878 14 1 B879 B879 15 1 B880 B880 16 1 B881 B881 17 1 B882 B882 18 1 B883 B883 19 1 B884 B884 20 1 B885 B885 21 1 B886 B886 22 1 B887 B887 23 1 B888 B888 24 1 B889 B889 25 1 B890 B890 26 1 B891 B891 27 1 B892 B892 28 1 B893 B893 29 1 B894 B894 30 1 B895 B895 31 1 MPCBB1_VCTR28 MPCBB1_VCTR28 MPCBBx vector register 0x170 0x20 read-write 0x00000000 B896 B896 0 1 B897 B897 1 1 B898 B898 2 1 B899 B899 3 1 B900 B900 4 1 B901 B901 5 1 B902 B902 6 1 B903 B903 7 1 B904 B904 8 1 B905 B905 9 1 B906 B906 10 1 B907 B907 11 1 B908 B908 12 1 B909 B909 13 1 B910 B910 14 1 B911 B911 15 1 B912 B912 16 1 B913 B913 17 1 B914 B914 18 1 B915 B915 19 1 B916 B916 20 1 B917 B917 21 1 B918 B918 22 1 B919 B919 23 1 B920 B920 24 1 B921 B921 25 1 B922 B922 26 1 B923 B923 27 1 B924 B924 28 1 B925 B925 29 1 B926 B926 30 1 B927 B927 31 1 MPCBB1_VCTR29 MPCBB1_VCTR29 MPCBBx vector register 0x174 0x20 read-write 0x00000000 B928 B928 0 1 B929 B929 1 1 B930 B930 2 1 B931 B931 3 1 B932 B932 4 1 B933 B933 5 1 B934 B934 6 1 B935 B935 7 1 B936 B936 8 1 B937 B937 9 1 B938 B938 10 1 B939 B939 11 1 B940 B940 12 1 B941 B941 13 1 B942 B942 14 1 B943 B943 15 1 B944 B944 16 1 B945 B945 17 1 B946 B946 18 1 B947 B947 19 1 B948 B948 20 1 B949 B949 21 1 B950 B950 22 1 B951 B951 23 1 B952 B952 24 1 B953 B953 25 1 B954 B954 26 1 B955 B955 27 1 B956 B956 28 1 B957 B957 29 1 B958 B958 30 1 B959 B959 31 1 MPCBB1_VCTR30 MPCBB1_VCTR30 MPCBBx vector register 0x178 0x20 read-write 0x00000000 B960 B960 0 1 B961 B961 1 1 B962 B962 2 1 B963 B963 3 1 B964 B964 4 1 B965 B965 5 1 B966 B966 6 1 B967 B967 7 1 B968 B968 8 1 B969 B969 9 1 B970 B970 10 1 B971 B971 11 1 B972 B972 12 1 B973 B973 13 1 B974 B974 14 1 B975 B975 15 1 B976 B976 16 1 B977 B977 17 1 B978 B978 18 1 B979 B979 19 1 B980 B980 20 1 B981 B981 21 1 B982 B982 22 1 B983 B983 23 1 B984 B984 24 1 B985 B985 25 1 B986 B986 26 1 B987 B987 27 1 B988 B988 28 1 B989 B989 29 1 B990 B990 30 1 B991 B991 31 1 MPCBB1_VCTR31 MPCBB1_VCTR31 MPCBBx vector register 0x17C 0x20 read-write 0x00000000 B992 B992 0 1 B993 B993 1 1 B994 B994 2 1 B995 B995 3 1 B996 B996 4 1 B997 B997 5 1 B998 B998 6 1 B999 B999 7 1 B1000 B1000 8 1 B1001 B1001 9 1 B1002 B1002 10 1 B1003 B1003 11 1 B1004 B1004 12 1 B1005 B1005 13 1 B1006 B1006 14 1 B1007 B1007 15 1 B1008 B1008 16 1 B1009 B1009 17 1 B1010 B1010 18 1 B1011 B1011 19 1 B1012 B1012 20 1 B1013 B1013 21 1 B1014 B1014 22 1 B1015 B1015 23 1 B1016 B1016 24 1 B1017 B1017 25 1 B1018 B1018 26 1 B1019 B1019 27 1 B1020 B1020 28 1 B1021 B1021 29 1 B1022 B1022 30 1 B1023 B1023 31 1 MPCBB1_VCTR32 MPCBB1_VCTR32 MPCBBx vector register 0x180 0x20 read-write 0x00000000 B1024 B1024 0 1 B1025 B1025 1 1 B1026 B1026 2 1 B1027 B1027 3 1 B1028 B1028 4 1 B1029 B1029 5 1 B1030 B1030 6 1 B1031 B1031 7 1 B1032 B1032 8 1 B1033 B1033 9 1 B1034 B1034 10 1 B1035 B1035 11 1 B1036 B1036 12 1 B1037 B1037 13 1 B1038 B1038 14 1 B1039 B1039 15 1 B1040 B1040 16 1 B1041 B1041 17 1 B1042 B1042 18 1 B1043 B1043 19 1 B1044 B1044 20 1 B1045 B1045 21 1 B1046 B1046 22 1 B1047 B1047 23 1 B1048 B1048 24 1 B1049 B1049 25 1 B1050 B1050 26 1 B1051 B1051 27 1 B1052 B1052 28 1 B1053 B1053 29 1 B1054 B1054 30 1 B1055 B1055 31 1 MPCBB1_VCTR33 MPCBB1_VCTR33 MPCBBx vector register 0x184 0x20 read-write 0x00000000 B1056 B1056 0 1 B1057 B1057 1 1 B1058 B1058 2 1 B1059 B1059 3 1 B1060 B1060 4 1 B1061 B1061 5 1 B1062 B1062 6 1 B1063 B1063 7 1 B1064 B1064 8 1 B1065 B1065 9 1 B1066 B1066 10 1 B1067 B1067 11 1 B1068 B1068 12 1 B1069 B1069 13 1 B1070 B1070 14 1 B1071 B1071 15 1 B1072 B1072 16 1 B1073 B1073 17 1 B1074 B1074 18 1 B1075 B1075 19 1 B1076 B1076 20 1 B1077 B1077 21 1 B1078 B1078 22 1 B1079 B1079 23 1 B1080 B1080 24 1 B1081 B1081 25 1 B1082 B1082 26 1 B1083 B1083 27 1 B1084 B1084 28 1 B1085 B1085 29 1 B1086 B1086 30 1 B1087 B1087 31 1 MPCBB1_VCTR34 MPCBB1_VCTR34 MPCBBx vector register 0x188 0x20 read-write 0x00000000 B1088 B1088 0 1 B1089 B1089 1 1 B1090 B1090 2 1 B1091 B1091 3 1 B1092 B1092 4 1 B1093 B1093 5 1 B1094 B1094 6 1 B1095 B1095 7 1 B1096 B1096 8 1 B1097 B1097 9 1 B1098 B1098 10 1 B1099 B1099 11 1 B1100 B1100 12 1 B1101 B1101 13 1 B1102 B1102 14 1 B1103 B1103 15 1 B1104 B1104 16 1 B1105 B1105 17 1 B1106 B1106 18 1 B1107 B1107 19 1 B1108 B1108 20 1 B1109 B1109 21 1 B1110 B1110 22 1 B1111 B1111 23 1 B1112 B1112 24 1 B1113 B1113 25 1 B1114 B1114 26 1 B1115 B1115 27 1 B1116 B1116 28 1 B1117 B1117 29 1 B1118 B1118 30 1 B1119 B1119 31 1 MPCBB1_VCTR35 MPCBB1_VCTR35 MPCBBx vector register 0x18C 0x20 read-write 0x00000000 B1120 B1120 0 1 B1121 B1121 1 1 B1122 B1122 2 1 B1123 B1123 3 1 B1124 B1124 4 1 B1125 B1125 5 1 B1126 B1126 6 1 B1127 B1127 7 1 B1128 B1128 8 1 B1129 B1129 9 1 B1130 B1130 10 1 B1131 B1131 11 1 B1132 B1132 12 1 B1133 B1133 13 1 B1134 B1134 14 1 B1135 B1135 15 1 B1136 B1136 16 1 B1137 B1137 17 1 B1138 B1138 18 1 B1139 B1139 19 1 B1140 B1140 20 1 B1141 B1141 21 1 B1142 B1142 22 1 B1143 B1143 23 1 B1144 B1144 24 1 B1145 B1145 25 1 B1146 B1146 26 1 B1147 B1147 27 1 B1148 B1148 28 1 B1149 B1149 29 1 B1150 B1150 30 1 B1151 B1151 31 1 MPCBB1_VCTR36 MPCBB1_VCTR36 MPCBBx vector register 0x190 0x20 read-write 0x00000000 B1152 B1152 0 1 B1153 B1153 1 1 B1154 B1154 2 1 B1155 B1155 3 1 B1156 B1156 4 1 B1157 B1157 5 1 B1158 B1158 6 1 B1159 B1159 7 1 B1160 B1160 8 1 B1161 B1161 9 1 B1162 B1162 10 1 B1163 B1163 11 1 B1164 B1164 12 1 B1165 B1165 13 1 B1166 B1166 14 1 B1167 B1167 15 1 B1168 B1168 16 1 B1169 B1169 17 1 B1170 B1170 18 1 B1171 B1171 19 1 B1172 B1172 20 1 B1173 B1173 21 1 B1174 B1174 22 1 B1175 B1175 23 1 B1176 B1176 24 1 B1177 B1177 25 1 B1178 B1178 26 1 B1179 B1179 27 1 B1180 B1180 28 1 B1181 B1181 29 1 B1182 B1182 30 1 B1183 B1183 31 1 MPCBB1_VCTR37 MPCBB1_VCTR37 MPCBBx vector register 0x194 0x20 read-write 0x00000000 B1184 B1184 0 1 B1185 B1185 1 1 B1186 B1186 2 1 B1187 B1187 3 1 B1188 B1188 4 1 B1189 B1189 5 1 B1190 B1190 6 1 B1191 B1191 7 1 B1192 B1192 8 1 B1193 B1193 9 1 B1194 B1194 10 1 B1195 B1195 11 1 B1196 B1196 12 1 B1197 B1197 13 1 B1198 B1198 14 1 B1199 B1199 15 1 B1200 B1200 16 1 B1201 B1201 17 1 B1202 B1202 18 1 B1203 B1203 19 1 B1204 B1204 20 1 B1205 B1205 21 1 B1206 B1206 22 1 B1207 B1207 23 1 B1208 B1208 24 1 B1209 B1209 25 1 B1210 B1210 26 1 B1211 B1211 27 1 B1212 B1212 28 1 B1213 B1213 29 1 B1214 B1214 30 1 B1215 B1215 31 1 MPCBB1_VCTR38 MPCBB1_VCTR38 MPCBBx vector register 0x198 0x20 read-write 0x00000000 B1216 B1216 0 1 B1217 B1217 1 1 B1218 B1218 2 1 B1219 B1219 3 1 B1220 B1220 4 1 B1221 B1221 5 1 B1222 B1222 6 1 B1223 B1223 7 1 B1224 B1224 8 1 B1225 B1225 9 1 B1226 B1226 10 1 B1227 B1227 11 1 B1228 B1228 12 1 B1229 B1229 13 1 B1230 B1230 14 1 B1231 B1231 15 1 B1232 B1232 16 1 B1233 B1233 17 1 B1234 B1234 18 1 B1235 B1235 19 1 B1236 B1236 20 1 B1237 B1237 21 1 B1238 B1238 22 1 B1239 B1239 23 1 B1240 B1240 24 1 B1241 B1241 25 1 B1242 B1242 26 1 B1243 B1243 27 1 B1244 B1244 28 1 B1245 B1245 29 1 B1246 B1246 30 1 B1247 B1247 31 1 MPCBB1_VCTR39 MPCBB1_VCTR39 MPCBBx vector register 0x19C 0x20 read-write 0x00000000 B1248 B1248 0 1 B1249 B1249 1 1 B1250 B1250 2 1 B1251 B1251 3 1 B1252 B1252 4 1 B1253 B1253 5 1 B1254 B1254 6 1 B1255 B1255 7 1 B1256 B1256 8 1 B1257 B1257 9 1 B1258 B1258 10 1 B1259 B1259 11 1 B1260 B1260 12 1 B1261 B1261 13 1 B1262 B1262 14 1 B1263 B1263 15 1 B1264 B1264 16 1 B1265 B1265 17 1 B1266 B1266 18 1 B1267 B1267 19 1 B1268 B1268 20 1 B1269 B1269 21 1 B1270 B1270 22 1 B1271 B1271 23 1 B1272 B1272 24 1 B1273 B1273 25 1 B1274 B1274 26 1 B1275 B1275 27 1 B1276 B1276 28 1 B1277 B1277 29 1 B1278 B1278 30 1 B1279 B1279 31 1 MPCBB1_VCTR40 MPCBB1_VCTR40 MPCBBx vector register 0x1A0 0x20 read-write 0x00000000 B1280 B1280 0 1 B1281 B1281 1 1 B1282 B1282 2 1 B1283 B1283 3 1 B1284 B1284 4 1 B1285 B1285 5 1 B1286 B1286 6 1 B1287 B1287 7 1 B1288 B1288 8 1 B1289 B1289 9 1 B1290 B1290 10 1 B1291 B1291 11 1 B1292 B1292 12 1 B1293 B1293 13 1 B1294 B1294 14 1 B1295 B1295 15 1 B1296 B1296 16 1 B1297 B1297 17 1 B1298 B1298 18 1 B1299 B1299 19 1 B1300 B1300 20 1 B1301 B1301 21 1 B1302 B1302 22 1 B1303 B1303 23 1 B1304 B1304 24 1 B1305 B1305 25 1 B1306 B1306 26 1 B1307 B1307 27 1 B1308 B1308 28 1 B1309 B1309 29 1 B1310 B1310 30 1 B1311 B1311 31 1 MPCBB1_VCTR41 MPCBB1_VCTR41 MPCBBx vector register 0x1A4 0x20 read-write 0x00000000 B1312 B1312 0 1 B1313 B1313 1 1 B1314 B1314 2 1 B1315 B1315 3 1 B1316 B1316 4 1 B1317 B1317 5 1 B1318 B1318 6 1 B1319 B1319 7 1 B1320 B1320 8 1 B1321 B1321 9 1 B1322 B1322 10 1 B1323 B1323 11 1 B1324 B1324 12 1 B1325 B1325 13 1 B1326 B1326 14 1 B1327 B1327 15 1 B1328 B1328 16 1 B1329 B1329 17 1 B1330 B1330 18 1 B1331 B1331 19 1 B1332 B1332 20 1 B1333 B1333 21 1 B1334 B1334 22 1 B1335 B1335 23 1 B1336 B1336 24 1 B1337 B1337 25 1 B1338 B1338 26 1 B1339 B1339 27 1 B1340 B1340 28 1 B1341 B1341 29 1 B1342 B1342 30 1 B1343 B1343 31 1 MPCBB1_VCTR42 MPCBB1_VCTR42 MPCBBx vector register 0x1A8 0x20 read-write 0x00000000 B1344 B1344 0 1 B1345 B1345 1 1 B1346 B1346 2 1 B1347 B1347 3 1 B1348 B1348 4 1 B1349 B1349 5 1 B1350 B1350 6 1 B1351 B1351 7 1 B1352 B1352 8 1 B1353 B1353 9 1 B1354 B1354 10 1 B1355 B1355 11 1 B1356 B1356 12 1 B1357 B1357 13 1 B1358 B1358 14 1 B1359 B1359 15 1 B1360 B1360 16 1 B1361 B1361 17 1 B1362 B1362 18 1 B1363 B1363 19 1 B1364 B1364 20 1 B1365 B1365 21 1 B1366 B1366 22 1 B1367 B1367 23 1 B1368 B1368 24 1 B1369 B1369 25 1 B1370 B1370 26 1 B1371 B1371 27 1 B1372 B1372 28 1 B1373 B1373 29 1 B1374 B1374 30 1 B1375 B1375 31 1 MPCBB1_VCTR43 MPCBB1_VCTR43 MPCBBx vector register 0x1AC 0x20 read-write 0x00000000 B1376 B1376 0 1 B1377 B1377 1 1 B1378 B1378 2 1 B1379 B1379 3 1 B1380 B1380 4 1 B1381 B1381 5 1 B1382 B1382 6 1 B1383 B1383 7 1 B1384 B1384 8 1 B1385 B1385 9 1 B1386 B1386 10 1 B1387 B1387 11 1 B1388 B1388 12 1 B1389 B1389 13 1 B1390 B1390 14 1 B1391 B1391 15 1 B1392 B1392 16 1 B1393 B1393 17 1 B1394 B1394 18 1 B1395 B1395 19 1 B1396 B1396 20 1 B1397 B1397 21 1 B1398 B1398 22 1 B1399 B1399 23 1 B1400 B1400 24 1 B1401 B1401 25 1 B1402 B1402 26 1 B1403 B1403 27 1 B1404 B1404 28 1 B1405 B1405 29 1 B1406 B1406 30 1 B1407 B1407 31 1 MPCBB1_VCTR44 MPCBB1_VCTR44 MPCBBx vector register 0x1B0 0x20 read-write 0x00000000 B1408 B1408 0 1 B1409 B1409 1 1 B1410 B1410 2 1 B1411 B1411 3 1 B1412 B1412 4 1 B1413 B1413 5 1 B1414 B1414 6 1 B1415 B1415 7 1 B1416 B1416 8 1 B1417 B1417 9 1 B1418 B1418 10 1 B1419 B1419 11 1 B1420 B1420 12 1 B1421 B1421 13 1 B1422 B1422 14 1 B1423 B1423 15 1 B1424 B1424 16 1 B1425 B1425 17 1 B1426 B1426 18 1 B1427 B1427 19 1 B1428 B1428 20 1 B1429 B1429 21 1 B1430 B1430 22 1 B1431 B1431 23 1 B1432 B1432 24 1 B1433 B1433 25 1 B1434 B1434 26 1 B1435 B1435 27 1 B1436 B1436 28 1 B1437 B1437 29 1 B1438 B1438 30 1 B1439 B1439 31 1 MPCBB1_VCTR45 MPCBB1_VCTR45 MPCBBx vector register 0x1B4 0x20 read-write 0x00000000 B1440 B1440 0 1 B1441 B1441 1 1 B1442 B1442 2 1 B1443 B1443 3 1 B1444 B1444 4 1 B1445 B1445 5 1 B1446 B1446 6 1 B1447 B1447 7 1 B1448 B1448 8 1 B1449 B1449 9 1 B1450 B1450 10 1 B1451 B1451 11 1 B1452 B1452 12 1 B1453 B1453 13 1 B1454 B1454 14 1 B1455 B1455 15 1 B1456 B1456 16 1 B1457 B1457 17 1 B1458 B1458 18 1 B1459 B1459 19 1 B1460 B1460 20 1 B1461 B1461 21 1 B1462 B1462 22 1 B1463 B1463 23 1 B1464 B1464 24 1 B1465 B1465 25 1 B1466 B1466 26 1 B1467 B1467 27 1 B1468 B1468 28 1 B1469 B1469 29 1 B1470 B1470 30 1 B1471 B1471 31 1 MPCBB1_VCTR46 MPCBB1_VCTR46 MPCBBx vector register 0x1B8 0x20 read-write 0x00000000 B1472 B1472 0 1 B1473 B1473 1 1 B1474 B1474 2 1 B1475 B1475 3 1 B1476 B1476 4 1 B1477 B1477 5 1 B1478 B1478 6 1 B1479 B1479 7 1 B1480 B1480 8 1 B1481 B1481 9 1 B1482 B1482 10 1 B1483 B1483 11 1 B1484 B1484 12 1 B1485 B1485 13 1 B1486 B1486 14 1 B1487 B1487 15 1 B1488 B1488 16 1 B1489 B1489 17 1 B1490 B1490 18 1 B1491 B1491 19 1 B1492 B1492 20 1 B1493 B1493 21 1 B1494 B1494 22 1 B1495 B1495 23 1 B1496 B1496 24 1 B1497 B1497 25 1 B1498 B1498 26 1 B1499 B1499 27 1 B1500 B1500 28 1 B1501 B1501 29 1 B1502 B1502 30 1 B1503 B1503 31 1 MPCBB1_VCTR47 MPCBB1_VCTR47 MPCBBx vector register 0x1BC 0x20 read-write 0x00000000 B1504 B1504 0 1 B1505 B1505 1 1 B1506 B1506 2 1 B1507 B1507 3 1 B1508 B1508 4 1 B1509 B1509 5 1 B1510 B1510 6 1 B1511 B1511 7 1 B1512 B1512 8 1 B1513 B1513 9 1 B1514 B1514 10 1 B1515 B1515 11 1 B1516 B1516 12 1 B1517 B1517 13 1 B1518 B1518 14 1 B1519 B1519 15 1 B1520 B1520 16 1 B1521 B1521 17 1 B1522 B1522 18 1 B1523 B1523 19 1 B1524 B1524 20 1 B1525 B1525 21 1 B1526 B1526 22 1 B1527 B1527 23 1 B1528 B1528 24 1 B1529 B1529 25 1 B1530 B1530 26 1 B1531 B1531 27 1 B1532 B1532 28 1 B1533 B1533 29 1 B1534 B1534 30 1 B1535 B1535 31 1 MPCBB1_VCTR48 MPCBB1_VCTR48 MPCBBx vector register 0x1C0 0x20 read-write 0x00000000 B1536 B1536 0 1 B1537 B1537 1 1 B1538 B1538 2 1 B1539 B1539 3 1 B1540 B1540 4 1 B1541 B1541 5 1 B1542 B1542 6 1 B1543 B1543 7 1 B1544 B1544 8 1 B1545 B1545 9 1 B1546 B1546 10 1 B1547 B1547 11 1 B1548 B1548 12 1 B1549 B1549 13 1 B1550 B1550 14 1 B1551 B1551 15 1 B1552 B1552 16 1 B1553 B1553 17 1 B1554 B1554 18 1 B1555 B1555 19 1 B1556 B1556 20 1 B1557 B1557 21 1 B1558 B1558 22 1 B1559 B1559 23 1 B1560 B1560 24 1 B1561 B1561 25 1 B1562 B1562 26 1 B1563 B1563 27 1 B1564 B1564 28 1 B1565 B1565 29 1 B1566 B1566 30 1 B1567 B1567 31 1 MPCBB1_VCTR49 MPCBB1_VCTR49 MPCBBx vector register 0x1C4 0x20 read-write 0x00000000 B1568 B1568 0 1 B1569 B1569 1 1 B1570 B1570 2 1 B1571 B1571 3 1 B1572 B1572 4 1 B1573 B1573 5 1 B1574 B1574 6 1 B1575 B1575 7 1 B1576 B1576 8 1 B1577 B1577 9 1 B1578 B1578 10 1 B1579 B1579 11 1 B1580 B1580 12 1 B1581 B1581 13 1 B1582 B1582 14 1 B1583 B1583 15 1 B1584 B1584 16 1 B1585 B1585 17 1 B1586 B1586 18 1 B1587 B1587 19 1 B1588 B1588 20 1 B1589 B1589 21 1 B1590 B1590 22 1 B1591 B1591 23 1 B1592 B1592 24 1 B1593 B1593 25 1 B1594 B1594 26 1 B1595 B1595 27 1 B1596 B1596 28 1 B1597 B1597 29 1 B1598 B1598 30 1 B1599 B1599 31 1 MPCBB1_VCTR50 MPCBB1_VCTR50 MPCBBx vector register 0x1C8 0x20 read-write 0x00000000 B1600 B1600 0 1 B1601 B1601 1 1 B1602 B1602 2 1 B1603 B1603 3 1 B1604 B1604 4 1 B1605 B1605 5 1 B1606 B1606 6 1 B1607 B1607 7 1 B1608 B1608 8 1 B1609 B1609 9 1 B1610 B1610 10 1 B1611 B1611 11 1 B1612 B1612 12 1 B1613 B1613 13 1 B1614 B1614 14 1 B1615 B1615 15 1 B1616 B1616 16 1 B1617 B1617 17 1 B1618 B1618 18 1 B1619 B1619 19 1 B1620 B1620 20 1 B1621 B1621 21 1 B1622 B1622 22 1 B1623 B1623 23 1 B1624 B1624 24 1 B1625 B1625 25 1 B1626 B1626 26 1 B1627 B1627 27 1 B1628 B1628 28 1 B1629 B1629 29 1 B1630 B1630 30 1 B1631 B1631 31 1 MPCBB1_VCTR51 MPCBB1_VCTR51 MPCBBx vector register 0x1CC 0x20 read-write 0x00000000 B1632 B1632 0 1 B1633 B1633 1 1 B1634 B1634 2 1 B1635 B1635 3 1 B1636 B1636 4 1 B1637 B1637 5 1 B1638 B1638 6 1 B1639 B1639 7 1 B1640 B1640 8 1 B1641 B1641 9 1 B1642 B1642 10 1 B1643 B1643 11 1 B1644 B1644 12 1 B1645 B1645 13 1 B1646 B1646 14 1 B1647 B1647 15 1 B1648 B1648 16 1 B1649 B1649 17 1 B1650 B1650 18 1 B1651 B1651 19 1 B1652 B1652 20 1 B1653 B1653 21 1 B1654 B1654 22 1 B1655 B1655 23 1 B1656 B1656 24 1 B1657 B1657 25 1 B1658 B1658 26 1 B1659 B1659 27 1 B1660 B1660 28 1 B1661 B1661 29 1 B1662 B1662 30 1 B1663 B1663 31 1 MPCBB1_VCTR52 MPCBB1_VCTR52 MPCBBx vector register 0x1D0 0x20 read-write 0x00000000 B1664 B1664 0 1 B1665 B1665 1 1 B1666 B1666 2 1 B1667 B1667 3 1 B1668 B1668 4 1 B1669 B1669 5 1 B1670 B1670 6 1 B1671 B1671 7 1 B1672 B1672 8 1 B1673 B1673 9 1 B1674 B1674 10 1 B1675 B1675 11 1 B1676 B1676 12 1 B1677 B1677 13 1 B1678 B1678 14 1 B1679 B1679 15 1 B1680 B1680 16 1 B1681 B1681 17 1 B1682 B1682 18 1 B1683 B1683 19 1 B1684 B1684 20 1 B1685 B1685 21 1 B1686 B1686 22 1 B1687 B1687 23 1 B1688 B1688 24 1 B1689 B1689 25 1 B1690 B1690 26 1 B1691 B1691 27 1 B1692 B1692 28 1 B1693 B1693 29 1 B1694 B1694 30 1 B1695 B1695 31 1 MPCBB1_VCTR53 MPCBB1_VCTR53 MPCBBx vector register 0x1D4 0x20 read-write 0x00000000 B1696 B1696 0 1 B1697 B1697 1 1 B1698 B1698 2 1 B1699 B1699 3 1 B1700 B1700 4 1 B1701 B1701 5 1 B1702 B1702 6 1 B1703 B1703 7 1 B1704 B1704 8 1 B1705 B1705 9 1 B1706 B1706 10 1 B1707 B1707 11 1 B1708 B1708 12 1 B1709 B1709 13 1 B1710 B1710 14 1 B1711 B1711 15 1 B1712 B1712 16 1 B1713 B1713 17 1 B1714 B1714 18 1 B1715 B1715 19 1 B1716 B1716 20 1 B1717 B1717 21 1 B1718 B1718 22 1 B1719 B1719 23 1 B1720 B1720 24 1 B1721 B1721 25 1 B1722 B1722 26 1 B1723 B1723 27 1 B1724 B1724 28 1 B1725 B1725 29 1 B1726 B1726 30 1 B1727 B1727 31 1 MPCBB1_VCTR54 MPCBB1_VCTR54 MPCBBx vector register 0x1D8 0x20 read-write 0x00000000 B1728 B1728 0 1 B1729 B1729 1 1 B1730 B1730 2 1 B1731 B1731 3 1 B1732 B1732 4 1 B1733 B1733 5 1 B1734 B1734 6 1 B1735 B1735 7 1 B1736 B1736 8 1 B1737 B1737 9 1 B1738 B1738 10 1 B1739 B1739 11 1 B1740 B1740 12 1 B1741 B1741 13 1 B1742 B1742 14 1 B1743 B1743 15 1 B1744 B1744 16 1 B1745 B1745 17 1 B1746 B1746 18 1 B1747 B1747 19 1 B1748 B1748 20 1 B1749 B1749 21 1 B1750 B1750 22 1 B1751 B1751 23 1 B1752 B1752 24 1 B1753 B1753 25 1 B1754 B1754 26 1 B1755 B1755 27 1 B1756 B1756 28 1 B1757 B1757 29 1 B1758 B1758 30 1 B1759 B1759 31 1 MPCBB1_VCTR55 MPCBB1_VCTR55 MPCBBx vector register 0x1DC 0x20 read-write 0x00000000 B1760 B1760 0 1 B1761 B1761 1 1 B1762 B1762 2 1 B1763 B1763 3 1 B1764 B1764 4 1 B1765 B1765 5 1 B1766 B1766 6 1 B1767 B1767 7 1 B1768 B1768 8 1 B1769 B1769 9 1 B1770 B1770 10 1 B1771 B1771 11 1 B1772 B1772 12 1 B1773 B1773 13 1 B1774 B1774 14 1 B1775 B1775 15 1 B1776 B1776 16 1 B1777 B1777 17 1 B1778 B1778 18 1 B1779 B1779 19 1 B1780 B1780 20 1 B1781 B1781 21 1 B1782 B1782 22 1 B1783 B1783 23 1 B1784 B1784 24 1 B1785 B1785 25 1 B1786 B1786 26 1 B1787 B1787 27 1 B1788 B1788 28 1 B1789 B1789 29 1 B1790 B1790 30 1 B1791 B1791 31 1 MPCBB1_VCTR56 MPCBB1_VCTR56 MPCBBx vector register 0x1E0 0x20 read-write 0x00000000 B1792 B1792 0 1 B1793 B1793 1 1 B1794 B1794 2 1 B1795 B1795 3 1 B1796 B1796 4 1 B1797 B1797 5 1 B1798 B1798 6 1 B1799 B1799 7 1 B1800 B1800 8 1 B1801 B1801 9 1 B1802 B1802 10 1 B1803 B1803 11 1 B1804 B1804 12 1 B1805 B1805 13 1 B1806 B1806 14 1 B1807 B1807 15 1 B1808 B1808 16 1 B1809 B1809 17 1 B1810 B1810 18 1 B1811 B1811 19 1 B1812 B1812 20 1 B1813 B1813 21 1 B1814 B1814 22 1 B1815 B1815 23 1 B1816 B1816 24 1 B1817 B1817 25 1 B1818 B1818 26 1 B1819 B1819 27 1 B1820 B1820 28 1 B1821 B1821 29 1 B1822 B1822 30 1 B1823 B1823 31 1 MPCBB1_VCTR57 MPCBB1_VCTR57 MPCBBx vector register 0x1E4 0x20 read-write 0x00000000 B1824 B1824 0 1 B1825 B1825 1 1 B1826 B1826 2 1 B1827 B1827 3 1 B1828 B1828 4 1 B1829 B1829 5 1 B1830 B1830 6 1 B1831 B1831 7 1 B1832 B1832 8 1 B1833 B1833 9 1 B1834 B1834 10 1 B1835 B1835 11 1 B1836 B1836 12 1 B1837 B1837 13 1 B1838 B1838 14 1 B1839 B1839 15 1 B1840 B1840 16 1 B1841 B1841 17 1 B1842 B1842 18 1 B1843 B1843 19 1 B1844 B1844 20 1 B1845 B1845 21 1 B1846 B1846 22 1 B1847 B1847 23 1 B1848 B1848 24 1 B1849 B1849 25 1 B1850 B1850 26 1 B1851 B1851 27 1 B1852 B1852 28 1 B1853 B1853 29 1 B1854 B1854 30 1 B1855 B1855 31 1 MPCBB1_VCTR58 MPCBB1_VCTR58 MPCBBx vector register 0x1E8 0x20 read-write 0x00000000 B1856 B1856 0 1 B1857 B1857 1 1 B1858 B1858 2 1 B1859 B1859 3 1 B1860 B1860 4 1 B1861 B1861 5 1 B1862 B1862 6 1 B1863 B1863 7 1 B1864 B1864 8 1 B1865 B1865 9 1 B1866 B1866 10 1 B1867 B1867 11 1 B1868 B1868 12 1 B1869 B1869 13 1 B1870 B1870 14 1 B1871 B1871 15 1 B1872 B1872 16 1 B1873 B1873 17 1 B1874 B1874 18 1 B1875 B1875 19 1 B1876 B1876 20 1 B1877 B1877 21 1 B1878 B1878 22 1 B1879 B1879 23 1 B1880 B1880 24 1 B1881 B1881 25 1 B1882 B1882 26 1 B1883 B1883 27 1 B1884 B1884 28 1 B1885 B1885 29 1 B1886 B1886 30 1 B1887 B1887 31 1 MPCBB1_VCTR59 MPCBB1_VCTR59 MPCBBx vector register 0x1EC 0x20 read-write 0x00000000 B1888 B1888 0 1 B1889 B1889 1 1 B1890 B1890 2 1 B1891 B1891 3 1 B1892 B1892 4 1 B1893 B1893 5 1 B1894 B1894 6 1 B1895 B1895 7 1 B1896 B1896 8 1 B1897 B1897 9 1 B1898 B1898 10 1 B1899 B1899 11 1 B1900 B1900 12 1 B1901 B1901 13 1 B1902 B1902 14 1 B1903 B1903 15 1 B1904 B1904 16 1 B1905 B1905 17 1 B1906 B1906 18 1 B1907 B1907 19 1 B1908 B1908 20 1 B1909 B1909 21 1 B1910 B1910 22 1 B1911 B1911 23 1 B1912 B1912 24 1 B1913 B1913 25 1 B1914 B1914 26 1 B1915 B1915 27 1 B1916 B1916 28 1 B1917 B1917 29 1 B1918 B1918 30 1 B1919 B1919 31 1 MPCBB1_VCTR60 MPCBB1_VCTR60 MPCBBx vector register 0x1F0 0x20 read-write 0x00000000 B1920 B1920 0 1 B1921 B1921 1 1 B1922 B1922 2 1 B1923 B1923 3 1 B1924 B1924 4 1 B1925 B1925 5 1 B1926 B1926 6 1 B1927 B1927 7 1 B1928 B1928 8 1 B1929 B1929 9 1 B1930 B1930 10 1 B1931 B1931 11 1 B1932 B1932 12 1 B1933 B1933 13 1 B1934 B1934 14 1 B1935 B1935 15 1 B1936 B1936 16 1 B1937 B1937 17 1 B1938 B1938 18 1 B1939 B1939 19 1 B1940 B1940 20 1 B1941 B1941 21 1 B1942 B1942 22 1 B1943 B1943 23 1 B1944 B1944 24 1 B1945 B1945 25 1 B1946 B1946 26 1 B1947 B1947 27 1 B1948 B1948 28 1 B1949 B1949 29 1 B1950 B1950 30 1 B1951 B1951 31 1 MPCBB1_VCTR61 MPCBB1_VCTR61 MPCBBx vector register 0x1F4 0x20 read-write 0x00000000 B1952 B1952 0 1 B1953 B1953 1 1 B1954 B1954 2 1 B1955 B1955 3 1 B1956 B1956 4 1 B1957 B1957 5 1 B1958 B1958 6 1 B1959 B1959 7 1 B1960 B1960 8 1 B1961 B1961 9 1 B1962 B1962 10 1 B1963 B1963 11 1 B1964 B1964 12 1 B1965 B1965 13 1 B1966 B1966 14 1 B1967 B1967 15 1 B1968 B1968 16 1 B1969 B1969 17 1 B1970 B1970 18 1 B1971 B1971 19 1 B1972 B1972 20 1 B1973 B1973 21 1 B1974 B1974 22 1 B1975 B1975 23 1 B1976 B1976 24 1 B1977 B1977 25 1 B1978 B1978 26 1 B1979 B1979 27 1 B1980 B1980 28 1 B1981 B1981 29 1 B1982 B1982 30 1 B1983 B1983 31 1 MPCBB1_VCTR62 MPCBB1_VCTR62 MPCBBx vector register 0x1F8 0x20 read-write 0x00000000 B1984 B1984 0 1 B1985 B1985 1 1 B1986 B1986 2 1 B1987 B1987 3 1 B1988 B1988 4 1 B1989 B1989 5 1 B1990 B1990 6 1 B1991 B1991 7 1 B1992 B1992 8 1 B1993 B1993 9 1 B1994 B1994 10 1 B1995 B1995 11 1 B1996 B1996 12 1 B1997 B1997 13 1 B1998 B1998 14 1 B1999 B1999 15 1 B2000 B2000 16 1 B2001 B2001 17 1 B2002 B2002 18 1 B2003 B2003 19 1 B2004 B2004 20 1 B2005 B2005 21 1 B2006 B2006 22 1 B2007 B2007 23 1 B2008 B2008 24 1 B2009 B2009 25 1 B2010 B2010 26 1 B2011 B2011 27 1 B2012 B2012 28 1 B2013 B2013 29 1 B2014 B2014 30 1 B2015 B2015 31 1 MPCBB1_VCTR63 MPCBB1_VCTR63 MPCBBx vector register 0x1FC 0x20 read-write 0x00000000 B2016 B2016 0 1 B2017 B2017 1 1 B2018 B2018 2 1 B2019 B2019 3 1 B2020 B2020 4 1 B2021 B2021 5 1 B2022 B2022 6 1 B2023 B2023 7 1 B2024 B2024 8 1 B2025 B2025 9 1 B2026 B2026 10 1 B2027 B2027 11 1 B2028 B2028 12 1 B2029 B2029 13 1 B2030 B2030 14 1 B2031 B2031 15 1 B2032 B2032 16 1 B2033 B2033 17 1 B2034 B2034 18 1 B2035 B2035 19 1 B2036 B2036 20 1 B2037 B2037 21 1 B2038 B2038 22 1 B2039 B2039 23 1 B2040 B2040 24 1 B2041 B2041 25 1 B2042 B2042 26 1 B2043 B2043 27 1 B2044 B2044 28 1 B2045 B2045 29 1 B2046 B2046 30 1 B2047 B2047 31 1 SEC_GTZC_MPCBB2 SEC_GTZC_MPCBB2 SEC_GTZC !(DCB->DSCSR & (1 << 16)) 0x50033000 0x0 0x400 registers MPCBB2_CR MPCBB2_CR MPCBB control register 0x0 0x20 read-write 0x00000000 LCK LCK 0 1 INVSECSTATE INVSECSTATE 30 1 SRWILADIS SRWILADIS 31 1 MPCBB2_LCKVTR1 MPCBB2_LCKVTR1 MPCBB control register 0x10 0x20 read-write 0x00000000 LCKSB0 LCKSB0 0 1 LCKSB1 LCKSB1 1 1 LCKSB2 LCKSB2 2 1 LCKSB3 LCKSB3 3 1 LCKSB4 LCKSB4 4 1 LCKSB5 LCKSB5 5 1 LCKSB6 LCKSB6 6 1 LCKSB7 LCKSB7 7 1 LCKSB8 LCKSB8 8 1 LCKSB9 LCKSB9 9 1 LCKSB10 LCKSB10 10 1 LCKSB11 LCKSB11 11 1 LCKSB12 LCKSB12 12 1 LCKSB13 LCKSB13 13 1 LCKSB14 LCKSB14 14 1 LCKSB15 LCKSB15 15 1 LCKSB16 LCKSB16 16 1 LCKSB17 LCKSB17 17 1 LCKSB18 LCKSB18 18 1 LCKSB19 LCKSB19 19 1 LCKSB20 LCKSB20 20 1 LCKSB21 LCKSB21 21 1 LCKSB22 LCKSB22 22 1 LCKSB23 LCKSB23 23 1 LCKSB24 LCKSB24 24 1 LCKSB25 LCKSB25 25 1 LCKSB26 LCKSB26 26 1 LCKSB27 LCKSB27 27 1 LCKSB28 LCKSB28 28 1 LCKSB29 LCKSB29 29 1 LCKSB30 LCKSB30 30 1 LCKSB31 LCKSB31 31 1 MPCBB2_LCKVTR2 MPCBB2_LCKVTR2 MPCBB control register 0x14 0x20 read-write 0x00000000 LCKSB32 LCKSB32 0 1 LCKSB33 LCKSB33 1 1 LCKSB34 LCKSB34 2 1 LCKSB35 LCKSB35 3 1 LCKSB36 LCKSB36 4 1 LCKSB37 LCKSB37 5 1 LCKSB38 LCKSB38 6 1 LCKSB39 LCKSB39 7 1 LCKSB40 LCKSB40 8 1 LCKSB41 LCKSB41 9 1 LCKSB42 LCKSB42 10 1 LCKSB43 LCKSB43 11 1 LCKSB44 LCKSB44 12 1 LCKSB45 LCKSB45 13 1 LCKSB46 LCKSB46 14 1 LCKSB47 LCKSB47 15 1 LCKSB48 LCKSB48 16 1 LCKSB49 LCKSB49 17 1 LCKSB50 LCKSB50 18 1 LCKSB51 LCKSB51 19 1 LCKSB52 LCKSB52 20 1 LCKSB53 LCKSB53 21 1 LCKSB54 LCKSB54 22 1 LCKSB55 LCKSB55 23 1 LCKSB56 LCKSB56 24 1 LCKSB57 LCKSB57 25 1 LCKSB58 LCKSB58 26 1 LCKSB59 LCKSB59 27 1 LCKSB60 LCKSB60 28 1 LCKSB61 LCKSB61 29 1 LCKSB62 LCKSB62 30 1 LCKSB63 LCKSB63 31 1 MPCBB2_VCTR0 MPCBB2_VCTR0 MPCBBx vector register 0x100 0x20 read-write 0xFFFFFFFF B0 B0 0 1 B1 B1 1 1 B2 B2 2 1 B3 B3 3 1 B4 B4 4 1 B5 B5 5 1 B6 B6 6 1 B7 B7 7 1 B8 B8 8 1 B9 B9 9 1 B10 B10 10 1 B11 B11 11 1 B12 B12 12 1 B13 B13 13 1 B14 B14 14 1 B15 B15 15 1 B16 B16 16 1 B17 B17 17 1 B18 B18 18 1 B19 B19 19 1 B20 B20 20 1 B21 B21 21 1 B22 B22 22 1 B23 B23 23 1 B24 B24 24 1 B25 B25 25 1 B26 B26 26 1 B27 B27 27 1 B28 B28 28 1 B29 B29 29 1 B30 B30 30 1 B31 B31 31 1 MPCBB2_VCTR1 MPCBB2_VCTR1 MPCBBx vector register 0x104 0x20 read-write 0xFFFFFFFF B32 B32 0 1 B33 B33 1 1 B34 B34 2 1 B35 B35 3 1 B36 B36 4 1 B37 B37 5 1 B38 B38 6 1 B39 B39 7 1 B40 B40 8 1 B41 B41 9 1 B42 B42 10 1 B43 B43 11 1 B44 B44 12 1 B45 B45 13 1 B46 B46 14 1 B47 B47 15 1 B48 B48 16 1 B49 B49 17 1 B50 B50 18 1 B51 B51 19 1 B52 B52 20 1 B53 B53 21 1 B54 B54 22 1 B55 B55 23 1 B56 B56 24 1 B57 B57 25 1 B58 B58 26 1 B59 B59 27 1 B60 B60 28 1 B61 B61 29 1 B62 B62 30 1 B63 B63 31 1 MPCBB2_VCTR2 MPCBB2_VCTR2 MPCBBx vector register 0x108 0x20 read-write 0xFFFFFFFF B64 B64 0 1 B65 B65 1 1 B66 B66 2 1 B67 B67 3 1 B68 B68 4 1 B69 B69 5 1 B70 B70 6 1 B71 B71 7 1 B72 B72 8 1 B73 B73 9 1 B74 B74 10 1 B75 B75 11 1 B76 B76 12 1 B77 B77 13 1 B78 B78 14 1 B79 B79 15 1 B80 B80 16 1 B81 B81 17 1 B82 B82 18 1 B83 B83 19 1 B84 B84 20 1 B85 B85 21 1 B86 B86 22 1 B87 B87 23 1 B88 B88 24 1 B89 B89 25 1 B90 B90 26 1 B91 B91 27 1 B92 B92 28 1 B93 B93 29 1 B94 B94 30 1 B95 B95 31 1 MPCBB2_VCTR3 MPCBB2_VCTR3 MPCBBx vector register 0x10C 0x20 read-write 0xFFFFFFFF B96 B96 0 1 B97 B97 1 1 B98 B98 2 1 B99 B99 3 1 B100 B100 4 1 B101 B101 5 1 B102 B102 6 1 B103 B103 7 1 B104 B104 8 1 B105 B105 9 1 B106 B106 10 1 B107 B107 11 1 B108 B108 12 1 B109 B109 13 1 B110 B110 14 1 B111 B111 15 1 B112 B112 16 1 B113 B113 17 1 B114 B114 18 1 B115 B115 19 1 B116 B116 20 1 B117 B117 21 1 B118 B118 22 1 B119 B119 23 1 B120 B120 24 1 B121 B121 25 1 B122 B122 26 1 B123 B123 27 1 B124 B124 28 1 B125 B125 29 1 B126 B126 30 1 B127 B127 31 1 MPCBB2_VCTR4 MPCBB2_VCTR4 MPCBBx vector register 0x110 0x20 read-write 0x00000000 B128 B128 0 1 B129 B129 1 1 B130 B130 2 1 B131 B131 3 1 B132 B132 4 1 B133 B133 5 1 B134 B134 6 1 B135 B135 7 1 B136 B136 8 1 B137 B137 9 1 B138 B138 10 1 B139 B139 11 1 B140 B140 12 1 B141 B141 13 1 B142 B142 14 1 B143 B143 15 1 B144 B144 16 1 B145 B145 17 1 B146 B146 18 1 B147 B147 19 1 B148 B148 20 1 B149 B149 21 1 B150 B150 22 1 B151 B151 23 1 B152 B152 24 1 B153 B153 25 1 B154 B154 26 1 B155 B155 27 1 B156 B156 28 1 B157 B157 29 1 B158 B158 30 1 B159 B159 31 1 MPCBB2_VCTR5 MPCBB2_VCTR5 MPCBBx vector register 0x114 0x20 read-write 0x00000000 B160 B160 0 1 B161 B161 1 1 B162 B162 2 1 B163 B163 3 1 B164 B164 4 1 B165 B165 5 1 B166 B166 6 1 B167 B167 7 1 B168 B168 8 1 B169 B169 9 1 B170 B170 10 1 B171 B171 11 1 B172 B172 12 1 B173 B173 13 1 B174 B174 14 1 B175 B175 15 1 B176 B176 16 1 B177 B177 17 1 B178 B178 18 1 B179 B179 19 1 B180 B180 20 1 B181 B181 21 1 B182 B182 22 1 B183 B183 23 1 B184 B184 24 1 B185 B185 25 1 B186 B186 26 1 B187 B187 27 1 B188 B188 28 1 B189 B189 29 1 B190 B190 30 1 B191 B191 31 1 MPCBB2_VCTR6 MPCBB2_VCTR6 MPCBBx vector register 0x118 0x20 read-write 0x00000000 B192 B192 0 1 B193 B193 1 1 B194 B194 2 1 B195 B195 3 1 B196 B196 4 1 B197 B197 5 1 B198 B198 6 1 B199 B199 7 1 B200 B200 8 1 B201 B201 9 1 B202 B202 10 1 B203 B203 11 1 B204 B204 12 1 B205 B205 13 1 B206 B206 14 1 B207 B207 15 1 B208 B208 16 1 B209 B209 17 1 B210 B210 18 1 B211 B211 19 1 B212 B212 20 1 B213 B213 21 1 B214 B214 22 1 B215 B215 23 1 B216 B216 24 1 B217 B217 25 1 B218 B218 26 1 B219 B219 27 1 B220 B220 28 1 B221 B221 29 1 B222 B222 30 1 B223 B223 31 1 MPCBB2_VCTR7 MPCBB2_VCTR7 MPCBBx vector register 0x11C 0x20 read-write 0x00000000 B224 B224 0 1 B225 B225 1 1 B226 B226 2 1 B227 B227 3 1 B228 B228 4 1 B229 B229 5 1 B230 B230 6 1 B231 B231 7 1 B232 B232 8 1 B233 B233 9 1 B234 B234 10 1 B235 B235 11 1 B236 B236 12 1 B237 B237 13 1 B238 B238 14 1 B239 B239 15 1 B240 B240 16 1 B241 B241 17 1 B242 B242 18 1 B243 B243 19 1 B244 B244 20 1 B245 B245 21 1 B246 B246 22 1 B247 B247 23 1 B248 B248 24 1 B249 B249 25 1 B250 B250 26 1 B251 B251 27 1 B252 B252 28 1 B253 B253 29 1 B254 B254 30 1 B255 B255 31 1 MPCBB2_VCTR8 MPCBB2_VCTR8 MPCBBx vector register 0x120 0x20 read-write 0x00000000 B256 B256 0 1 B257 B257 1 1 B258 B258 2 1 B259 B259 3 1 B260 B260 4 1 B261 B261 5 1 B262 B262 6 1 B263 B263 7 1 B264 B264 8 1 B265 B265 9 1 B266 B266 10 1 B267 B267 11 1 B268 B268 12 1 B269 B269 13 1 B270 B270 14 1 B271 B271 15 1 B272 B272 16 1 B273 B273 17 1 B274 B274 18 1 B275 B275 19 1 B276 B276 20 1 B277 B277 21 1 B278 B278 22 1 B279 B279 23 1 B280 B280 24 1 B281 B281 25 1 B282 B282 26 1 B283 B283 27 1 B284 B284 28 1 B285 B285 29 1 B286 B286 30 1 B287 B287 31 1 MPCBB2_VCTR9 MPCBB2_VCTR9 MPCBBx vector register 0x124 0x20 read-write 0x00000000 B288 B288 0 1 B289 B289 1 1 B290 B290 2 1 B291 B291 3 1 B292 B292 4 1 B293 B293 5 1 B294 B294 6 1 B295 B295 7 1 B296 B296 8 1 B297 B297 9 1 B298 B298 10 1 B299 B299 11 1 B300 B300 12 1 B301 B301 13 1 B302 B302 14 1 B303 B303 15 1 B304 B304 16 1 B305 B305 17 1 B306 B306 18 1 B307 B307 19 1 B308 B308 20 1 B309 B309 21 1 B310 B310 22 1 B311 B311 23 1 B312 B312 24 1 B313 B313 25 1 B314 B314 26 1 B315 B315 27 1 B316 B316 28 1 B317 B317 29 1 B318 B318 30 1 B319 B319 31 1 MPCBB2_VCTR10 MPCBB2_VCTR10 MPCBBx vector register 0x128 0x20 read-write 0x00000000 B320 B320 0 1 B321 B321 1 1 B322 B322 2 1 B323 B323 3 1 B324 B324 4 1 B325 B325 5 1 B326 B326 6 1 B327 B327 7 1 B328 B328 8 1 B329 B329 9 1 B330 B330 10 1 B331 B331 11 1 B332 B332 12 1 B333 B333 13 1 B334 B334 14 1 B335 B335 15 1 B336 B336 16 1 B337 B337 17 1 B338 B338 18 1 B339 B339 19 1 B340 B340 20 1 B341 B341 21 1 B342 B342 22 1 B343 B343 23 1 B344 B344 24 1 B345 B345 25 1 B346 B346 26 1 B347 B347 27 1 B348 B348 28 1 B349 B349 29 1 B350 B350 30 1 B351 B351 31 1 MPCBB2_VCTR11 MPCBB2_VCTR11 MPCBBx vector register 0x12C 0x20 read-write 0x00000000 B352 B352 0 1 B353 B353 1 1 B354 B354 2 1 B355 B355 3 1 B356 B356 4 1 B357 B357 5 1 B358 B358 6 1 B359 B359 7 1 B360 B360 8 1 B361 B361 9 1 B362 B362 10 1 B363 B363 11 1 B364 B364 12 1 B365 B365 13 1 B366 B366 14 1 B367 B367 15 1 B368 B368 16 1 B369 B369 17 1 B370 B370 18 1 B371 B371 19 1 B372 B372 20 1 B373 B373 21 1 B374 B374 22 1 B375 B375 23 1 B376 B376 24 1 B377 B377 25 1 B378 B378 26 1 B379 B379 27 1 B380 B380 28 1 B381 B381 29 1 B382 B382 30 1 B383 B383 31 1 MPCBB2_VCTR12 MPCBB2_VCTR12 MPCBBx vector register 0x130 0x20 read-write 0x00000000 B384 B384 0 1 B385 B385 1 1 B386 B386 2 1 B387 B387 3 1 B388 B388 4 1 B389 B389 5 1 B390 B390 6 1 B391 B391 7 1 B392 B392 8 1 B393 B393 9 1 B394 B394 10 1 B395 B395 11 1 B396 B396 12 1 B397 B397 13 1 B398 B398 14 1 B399 B399 15 1 B400 B400 16 1 B401 B401 17 1 B402 B402 18 1 B403 B403 19 1 B404 B404 20 1 B405 B405 21 1 B406 B406 22 1 B407 B407 23 1 B408 B408 24 1 B409 B409 25 1 B410 B410 26 1 B411 B411 27 1 B412 B412 28 1 B413 B413 29 1 B414 B414 30 1 B415 B415 31 1 MPCBB2_VCTR13 MPCBB2_VCTR13 MPCBBx vector register 0x134 0x20 read-write 0x00000000 B416 B416 0 1 B417 B417 1 1 B418 B418 2 1 B419 B419 3 1 B420 B420 4 1 B421 B421 5 1 B422 B422 6 1 B423 B423 7 1 B424 B424 8 1 B425 B425 9 1 B426 B426 10 1 B427 B427 11 1 B428 B428 12 1 B429 B429 13 1 B430 B430 14 1 B431 B431 15 1 B432 B432 16 1 B433 B433 17 1 B434 B434 18 1 B435 B435 19 1 B436 B436 20 1 B437 B437 21 1 B438 B438 22 1 B439 B439 23 1 B440 B440 24 1 B441 B441 25 1 B442 B442 26 1 B443 B443 27 1 B444 B444 28 1 B445 B445 29 1 B446 B446 30 1 B447 B447 31 1 MPCBB2_VCTR14 MPCBB2_VCTR14 MPCBBx vector register 0x138 0x20 read-write 0x00000000 B448 B448 0 1 B449 B449 1 1 B450 B450 2 1 B451 B451 3 1 B452 B452 4 1 B453 B453 5 1 B454 B454 6 1 B455 B455 7 1 B456 B456 8 1 B457 B457 9 1 B458 B458 10 1 B459 B459 11 1 B460 B460 12 1 B461 B461 13 1 B462 B462 14 1 B463 B463 15 1 B464 B464 16 1 B465 B465 17 1 B466 B466 18 1 B467 B467 19 1 B468 B468 20 1 B469 B469 21 1 B470 B470 22 1 B471 B471 23 1 B472 B472 24 1 B473 B473 25 1 B474 B474 26 1 B475 B475 27 1 B476 B476 28 1 B477 B477 29 1 B478 B478 30 1 B479 B479 31 1 MPCBB2_VCTR15 MPCBB2_VCTR15 MPCBBx vector register 0x13C 0x20 read-write 0x00000000 B480 B480 0 1 B481 B481 1 1 B482 B482 2 1 B483 B483 3 1 B484 B484 4 1 B485 B485 5 1 B486 B486 6 1 B487 B487 7 1 B488 B488 8 1 B489 B489 9 1 B490 B490 10 1 B491 B491 11 1 B492 B492 12 1 B493 B493 13 1 B494 B494 14 1 B495 B495 15 1 B496 B496 16 1 B497 B497 17 1 B498 B498 18 1 B499 B499 19 1 B500 B500 20 1 B501 B501 21 1 B502 B502 22 1 B503 B503 23 1 B504 B504 24 1 B505 B505 25 1 B506 B506 26 1 B507 B507 27 1 B508 B508 28 1 B509 B509 29 1 B510 B510 30 1 B511 B511 31 1 MPCBB2_VCTR16 MPCBB2_VCTR16 MPCBBx vector register 0x140 0x20 read-write 0x00000000 B512 B512 0 1 B513 B513 1 1 B514 B514 2 1 B515 B515 3 1 B516 B516 4 1 B517 B517 5 1 B518 B518 6 1 B519 B519 7 1 B520 B520 8 1 B521 B521 9 1 B522 B522 10 1 B523 B523 11 1 B524 B524 12 1 B525 B525 13 1 B526 B526 14 1 B527 B527 15 1 B528 B528 16 1 B529 B529 17 1 B530 B530 18 1 B531 B531 19 1 B532 B532 20 1 B533 B533 21 1 B534 B534 22 1 B535 B535 23 1 B536 B536 24 1 B537 B537 25 1 B538 B538 26 1 B539 B539 27 1 B540 B540 28 1 B541 B541 29 1 B542 B542 30 1 B543 B543 31 1 MPCBB2_VCTR17 MPCBB2_VCTR17 MPCBBx vector register 0x144 0x20 read-write 0x00000000 B544 B544 0 1 B545 B545 1 1 B546 B546 2 1 B547 B547 3 1 B548 B548 4 1 B549 B549 5 1 B550 B550 6 1 B551 B551 7 1 B552 B552 8 1 B553 B553 9 1 B554 B554 10 1 B555 B555 11 1 B556 B556 12 1 B557 B557 13 1 B558 B558 14 1 B559 B559 15 1 B560 B560 16 1 B561 B561 17 1 B562 B562 18 1 B563 B563 19 1 B564 B564 20 1 B565 B565 21 1 B566 B566 22 1 B567 B567 23 1 B568 B568 24 1 B569 B569 25 1 B570 B570 26 1 B571 B571 27 1 B572 B572 28 1 B573 B573 29 1 B574 B574 30 1 B575 B575 31 1 MPCBB2_VCTR18 MPCBB2_VCTR18 MPCBBx vector register 0x148 0x20 read-write 0x00000000 B576 B576 0 1 B577 B577 1 1 B578 B578 2 1 B579 B579 3 1 B580 B580 4 1 B581 B581 5 1 B582 B582 6 1 B583 B583 7 1 B584 B584 8 1 B585 B585 9 1 B586 B586 10 1 B587 B587 11 1 B588 B588 12 1 B589 B589 13 1 B590 B590 14 1 B591 B591 15 1 B592 B592 16 1 B593 B593 17 1 B594 B594 18 1 B595 B595 19 1 B596 B596 20 1 B597 B597 21 1 B598 B598 22 1 B599 B599 23 1 B600 B600 24 1 B601 B601 25 1 B602 B602 26 1 B603 B603 27 1 B604 B604 28 1 B605 B605 29 1 B606 B606 30 1 B607 B607 31 1 MPCBB2_VCTR19 MPCBB2_VCTR19 MPCBBx vector register 0x14C 0x20 read-write 0x00000000 B608 B608 0 1 B609 B609 1 1 B610 B610 2 1 B611 B611 3 1 B612 B612 4 1 B613 B613 5 1 B614 B614 6 1 B615 B615 7 1 B616 B616 8 1 B617 B617 9 1 B618 B618 10 1 B619 B619 11 1 B620 B620 12 1 B621 B621 13 1 B622 B622 14 1 B623 B623 15 1 B624 B624 16 1 B625 B625 17 1 B626 B626 18 1 B627 B627 19 1 B628 B628 20 1 B629 B629 21 1 B630 B630 22 1 B631 B631 23 1 B632 B632 24 1 B633 B633 25 1 B634 B634 26 1 B635 B635 27 1 B636 B636 28 1 B637 B637 29 1 B638 B638 30 1 B639 B639 31 1 MPCBB2_VCTR20 MPCBB2_VCTR20 MPCBBx vector register 0x150 0x20 read-write 0x00000000 B640 B640 0 1 B641 B641 1 1 B642 B642 2 1 B643 B643 3 1 B644 B644 4 1 B645 B645 5 1 B646 B646 6 1 B647 B647 7 1 B648 B648 8 1 B649 B649 9 1 B650 B650 10 1 B651 B651 11 1 B652 B652 12 1 B653 B653 13 1 B654 B654 14 1 B655 B655 15 1 B656 B656 16 1 B657 B657 17 1 B658 B658 18 1 B659 B659 19 1 B660 B660 20 1 B661 B661 21 1 B662 B662 22 1 B663 B663 23 1 B664 B664 24 1 B665 B665 25 1 B666 B666 26 1 B667 B667 27 1 B668 B668 28 1 B669 B669 29 1 B670 B670 30 1 B671 B671 31 1 MPCBB2_VCTR21 MPCBB2_VCTR21 MPCBBx vector register 0x154 0x20 read-write 0x00000000 B672 B672 0 1 B673 B673 1 1 B674 B674 2 1 B675 B675 3 1 B676 B676 4 1 B677 B677 5 1 B678 B678 6 1 B679 B679 7 1 B680 B680 8 1 B681 B681 9 1 B682 B682 10 1 B683 B683 11 1 B684 B684 12 1 B685 B685 13 1 B686 B686 14 1 B687 B687 15 1 B688 B688 16 1 B689 B689 17 1 B690 B690 18 1 B691 B691 19 1 B692 B692 20 1 B693 B693 21 1 B694 B694 22 1 B695 B695 23 1 B696 B696 24 1 B697 B697 25 1 B698 B698 26 1 B699 B699 27 1 B700 B700 28 1 B701 B701 29 1 B702 B702 30 1 B703 B703 31 1 MPCBB2_VCTR22 MPCBB2_VCTR22 MPCBBx vector register 0x158 0x20 read-write 0x00000000 B704 B704 0 1 B705 B705 1 1 B706 B706 2 1 B707 B707 3 1 B708 B708 4 1 B709 B709 5 1 B710 B710 6 1 B711 B711 7 1 B712 B712 8 1 B713 B713 9 1 B714 B714 10 1 B715 B715 11 1 B716 B716 12 1 B717 B717 13 1 B718 B718 14 1 B719 B719 15 1 B720 B720 16 1 B721 B721 17 1 B722 B722 18 1 B723 B723 19 1 B724 B724 20 1 B725 B725 21 1 B726 B726 22 1 B727 B727 23 1 B728 B728 24 1 B729 B729 25 1 B730 B730 26 1 B731 B731 27 1 B732 B732 28 1 B733 B733 29 1 B734 B734 30 1 B735 B735 31 1 MPCBB2_VCTR23 MPCBB2_VCTR23 MPCBBx vector register 0x15C 0x20 read-write 0x00000000 B736 B736 0 1 B737 B737 1 1 B738 B738 2 1 B739 B739 3 1 B740 B740 4 1 B741 B741 5 1 B742 B742 6 1 B743 B743 7 1 B744 B744 8 1 B745 B745 9 1 B746 B746 10 1 B747 B747 11 1 B748 B748 12 1 B749 B749 13 1 B750 B750 14 1 B751 B751 15 1 B752 B752 16 1 B753 B753 17 1 B754 B754 18 1 B755 B755 19 1 B756 B756 20 1 B757 B757 21 1 B758 B758 22 1 B759 B759 23 1 B760 B760 24 1 B761 B761 25 1 B762 B762 26 1 B763 B763 27 1 B764 B764 28 1 B765 B765 29 1 B766 B766 30 1 B767 B767 31 1 MPCBB2_VCTR24 MPCBB2_VCTR24 MPCBBx vector register 0x160 0x20 read-write 0x00000000 B768 B768 0 1 B769 B769 1 1 B770 B770 2 1 B771 B771 3 1 B772 B772 4 1 B773 B773 5 1 B774 B774 6 1 B775 B775 7 1 B776 B776 8 1 B777 B777 9 1 B778 B778 10 1 B779 B779 11 1 B780 B780 12 1 B781 B781 13 1 B782 B782 14 1 B783 B783 15 1 B784 B784 16 1 B785 B785 17 1 B786 B786 18 1 B787 B787 19 1 B788 B788 20 1 B789 B789 21 1 B790 B790 22 1 B791 B791 23 1 B792 B792 24 1 B793 B793 25 1 B794 B794 26 1 B795 B795 27 1 B796 B796 28 1 B797 B797 29 1 B798 B798 30 1 B799 B799 31 1 MPCBB2_VCTR25 MPCBB2_VCTR25 MPCBBx vector register 0x164 0x20 read-write 0x00000000 B800 B800 0 1 B801 B801 1 1 B802 B802 2 1 B803 B803 3 1 B804 B804 4 1 B805 B805 5 1 B806 B806 6 1 B807 B807 7 1 B808 B808 8 1 B809 B809 9 1 B810 B810 10 1 B811 B811 11 1 B812 B812 12 1 B813 B813 13 1 B814 B814 14 1 B815 B815 15 1 B816 B816 16 1 B817 B817 17 1 B818 B818 18 1 B819 B819 19 1 B820 B820 20 1 B821 B821 21 1 B822 B822 22 1 B823 B823 23 1 B824 B824 24 1 B825 B825 25 1 B826 B826 26 1 B827 B827 27 1 B828 B828 28 1 B829 B829 29 1 B830 B830 30 1 B831 B831 31 1 MPCBB2_VCTR26 MPCBB2_VCTR26 MPCBBx vector register 0x168 0x20 read-write 0x00000000 B832 B832 0 1 B833 B833 1 1 B834 B834 2 1 B835 B835 3 1 B836 B836 4 1 B837 B837 5 1 B838 B838 6 1 B839 B839 7 1 B840 B840 8 1 B841 B841 9 1 B842 B842 10 1 B843 B843 11 1 B844 B844 12 1 B845 B845 13 1 B846 B846 14 1 B847 B847 15 1 B848 B848 16 1 B849 B849 17 1 B850 B850 18 1 B851 B851 19 1 B852 B852 20 1 B853 B853 21 1 B854 B854 22 1 B855 B855 23 1 B856 B856 24 1 B857 B857 25 1 B858 B858 26 1 B859 B859 27 1 B860 B860 28 1 B861 B861 29 1 B862 B862 30 1 B863 B863 31 1 MPCBB2_VCTR27 MPCBB2_VCTR27 MPCBBx vector register 0x16C 0x20 read-write 0x00000000 B864 B864 0 1 B865 B865 1 1 B866 B866 2 1 B867 B867 3 1 B868 B868 4 1 B869 B869 5 1 B870 B870 6 1 B871 B871 7 1 B872 B872 8 1 B873 B873 9 1 B874 B874 10 1 B875 B875 11 1 B876 B876 12 1 B877 B877 13 1 B878 B878 14 1 B879 B879 15 1 B880 B880 16 1 B881 B881 17 1 B882 B882 18 1 B883 B883 19 1 B884 B884 20 1 B885 B885 21 1 B886 B886 22 1 B887 B887 23 1 B888 B888 24 1 B889 B889 25 1 B890 B890 26 1 B891 B891 27 1 B892 B892 28 1 B893 B893 29 1 B894 B894 30 1 B895 B895 31 1 MPCBB2_VCTR28 MPCBB2_VCTR28 MPCBBx vector register 0x170 0x20 read-write 0x00000000 B896 B896 0 1 B897 B897 1 1 B898 B898 2 1 B899 B899 3 1 B900 B900 4 1 B901 B901 5 1 B902 B902 6 1 B903 B903 7 1 B904 B904 8 1 B905 B905 9 1 B906 B906 10 1 B907 B907 11 1 B908 B908 12 1 B909 B909 13 1 B910 B910 14 1 B911 B911 15 1 B912 B912 16 1 B913 B913 17 1 B914 B914 18 1 B915 B915 19 1 B916 B916 20 1 B917 B917 21 1 B918 B918 22 1 B919 B919 23 1 B920 B920 24 1 B921 B921 25 1 B922 B922 26 1 B923 B923 27 1 B924 B924 28 1 B925 B925 29 1 B926 B926 30 1 B927 B927 31 1 MPCBB2_VCTR29 MPCBB2_VCTR29 MPCBBx vector register 0x174 0x20 read-write 0x00000000 B928 B928 0 1 B929 B929 1 1 B930 B930 2 1 B931 B931 3 1 B932 B932 4 1 B933 B933 5 1 B934 B934 6 1 B935 B935 7 1 B936 B936 8 1 B937 B937 9 1 B938 B938 10 1 B939 B939 11 1 B940 B940 12 1 B941 B941 13 1 B942 B942 14 1 B943 B943 15 1 B944 B944 16 1 B945 B945 17 1 B946 B946 18 1 B947 B947 19 1 B948 B948 20 1 B949 B949 21 1 B950 B950 22 1 B951 B951 23 1 B952 B952 24 1 B953 B953 25 1 B954 B954 26 1 B955 B955 27 1 B956 B956 28 1 B957 B957 29 1 B958 B958 30 1 B959 B959 31 1 MPCBB2_VCTR30 MPCBB2_VCTR30 MPCBBx vector register 0x178 0x20 read-write 0x00000000 B960 B960 0 1 B961 B961 1 1 B962 B962 2 1 B963 B963 3 1 B964 B964 4 1 B965 B965 5 1 B966 B966 6 1 B967 B967 7 1 B968 B968 8 1 B969 B969 9 1 B970 B970 10 1 B971 B971 11 1 B972 B972 12 1 B973 B973 13 1 B974 B974 14 1 B975 B975 15 1 B976 B976 16 1 B977 B977 17 1 B978 B978 18 1 B979 B979 19 1 B980 B980 20 1 B981 B981 21 1 B982 B982 22 1 B983 B983 23 1 B984 B984 24 1 B985 B985 25 1 B986 B986 26 1 B987 B987 27 1 B988 B988 28 1 B989 B989 29 1 B990 B990 30 1 B991 B991 31 1 MPCBB2_VCTR31 MPCBB2_VCTR31 MPCBBx vector register 0x17C 0x20 read-write 0x00000000 B992 B992 0 1 B993 B993 1 1 B994 B994 2 1 B995 B995 3 1 B996 B996 4 1 B997 B997 5 1 B998 B998 6 1 B999 B999 7 1 B1000 B1000 8 1 B1001 B1001 9 1 B1002 B1002 10 1 B1003 B1003 11 1 B1004 B1004 12 1 B1005 B1005 13 1 B1006 B1006 14 1 B1007 B1007 15 1 B1008 B1008 16 1 B1009 B1009 17 1 B1010 B1010 18 1 B1011 B1011 19 1 B1012 B1012 20 1 B1013 B1013 21 1 B1014 B1014 22 1 B1015 B1015 23 1 B1016 B1016 24 1 B1017 B1017 25 1 B1018 B1018 26 1 B1019 B1019 27 1 B1020 B1020 28 1 B1021 B1021 29 1 B1022 B1022 30 1 B1023 B1023 31 1 MPCBB2_VCTR32 MPCBB2_VCTR32 MPCBBx vector register 0x180 0x20 read-write 0x00000000 B1024 B1024 0 1 B1025 B1025 1 1 B1026 B1026 2 1 B1027 B1027 3 1 B1028 B1028 4 1 B1029 B1029 5 1 B1030 B1030 6 1 B1031 B1031 7 1 B1032 B1032 8 1 B1033 B1033 9 1 B1034 B1034 10 1 B1035 B1035 11 1 B1036 B1036 12 1 B1037 B1037 13 1 B1038 B1038 14 1 B1039 B1039 15 1 B1040 B1040 16 1 B1041 B1041 17 1 B1042 B1042 18 1 B1043 B1043 19 1 B1044 B1044 20 1 B1045 B1045 21 1 B1046 B1046 22 1 B1047 B1047 23 1 B1048 B1048 24 1 B1049 B1049 25 1 B1050 B1050 26 1 B1051 B1051 27 1 B1052 B1052 28 1 B1053 B1053 29 1 B1054 B1054 30 1 B1055 B1055 31 1 MPCBB2_VCTR33 MPCBB2_VCTR33 MPCBBx vector register 0x184 0x20 read-write 0x00000000 B1056 B1056 0 1 B1057 B1057 1 1 B1058 B1058 2 1 B1059 B1059 3 1 B1060 B1060 4 1 B1061 B1061 5 1 B1062 B1062 6 1 B1063 B1063 7 1 B1064 B1064 8 1 B1065 B1065 9 1 B1066 B1066 10 1 B1067 B1067 11 1 B1068 B1068 12 1 B1069 B1069 13 1 B1070 B1070 14 1 B1071 B1071 15 1 B1072 B1072 16 1 B1073 B1073 17 1 B1074 B1074 18 1 B1075 B1075 19 1 B1076 B1076 20 1 B1077 B1077 21 1 B1078 B1078 22 1 B1079 B1079 23 1 B1080 B1080 24 1 B1081 B1081 25 1 B1082 B1082 26 1 B1083 B1083 27 1 B1084 B1084 28 1 B1085 B1085 29 1 B1086 B1086 30 1 B1087 B1087 31 1 MPCBB2_VCTR34 MPCBB2_VCTR34 MPCBBx vector register 0x188 0x20 read-write 0x00000000 B1088 B1088 0 1 B1089 B1089 1 1 B1090 B1090 2 1 B1091 B1091 3 1 B1092 B1092 4 1 B1093 B1093 5 1 B1094 B1094 6 1 B1095 B1095 7 1 B1096 B1096 8 1 B1097 B1097 9 1 B1098 B1098 10 1 B1099 B1099 11 1 B1100 B1100 12 1 B1101 B1101 13 1 B1102 B1102 14 1 B1103 B1103 15 1 B1104 B1104 16 1 B1105 B1105 17 1 B1106 B1106 18 1 B1107 B1107 19 1 B1108 B1108 20 1 B1109 B1109 21 1 B1110 B1110 22 1 B1111 B1111 23 1 B1112 B1112 24 1 B1113 B1113 25 1 B1114 B1114 26 1 B1115 B1115 27 1 B1116 B1116 28 1 B1117 B1117 29 1 B1118 B1118 30 1 B1119 B1119 31 1 MPCBB2_VCTR35 MPCBB2_VCTR35 MPCBBx vector register 0x18C 0x20 read-write 0x00000000 B1120 B1120 0 1 B1121 B1121 1 1 B1122 B1122 2 1 B1123 B1123 3 1 B1124 B1124 4 1 B1125 B1125 5 1 B1126 B1126 6 1 B1127 B1127 7 1 B1128 B1128 8 1 B1129 B1129 9 1 B1130 B1130 10 1 B1131 B1131 11 1 B1132 B1132 12 1 B1133 B1133 13 1 B1134 B1134 14 1 B1135 B1135 15 1 B1136 B1136 16 1 B1137 B1137 17 1 B1138 B1138 18 1 B1139 B1139 19 1 B1140 B1140 20 1 B1141 B1141 21 1 B1142 B1142 22 1 B1143 B1143 23 1 B1144 B1144 24 1 B1145 B1145 25 1 B1146 B1146 26 1 B1147 B1147 27 1 B1148 B1148 28 1 B1149 B1149 29 1 B1150 B1150 30 1 B1151 B1151 31 1 MPCBB2_VCTR36 MPCBB2_VCTR36 MPCBBx vector register 0x190 0x20 read-write 0x00000000 B1152 B1152 0 1 B1153 B1153 1 1 B1154 B1154 2 1 B1155 B1155 3 1 B1156 B1156 4 1 B1157 B1157 5 1 B1158 B1158 6 1 B1159 B1159 7 1 B1160 B1160 8 1 B1161 B1161 9 1 B1162 B1162 10 1 B1163 B1163 11 1 B1164 B1164 12 1 B1165 B1165 13 1 B1166 B1166 14 1 B1167 B1167 15 1 B1168 B1168 16 1 B1169 B1169 17 1 B1170 B1170 18 1 B1171 B1171 19 1 B1172 B1172 20 1 B1173 B1173 21 1 B1174 B1174 22 1 B1175 B1175 23 1 B1176 B1176 24 1 B1177 B1177 25 1 B1178 B1178 26 1 B1179 B1179 27 1 B1180 B1180 28 1 B1181 B1181 29 1 B1182 B1182 30 1 B1183 B1183 31 1 MPCBB2_VCTR37 MPCBB2_VCTR37 MPCBBx vector register 0x194 0x20 read-write 0x00000000 B1184 B1184 0 1 B1185 B1185 1 1 B1186 B1186 2 1 B1187 B1187 3 1 B1188 B1188 4 1 B1189 B1189 5 1 B1190 B1190 6 1 B1191 B1191 7 1 B1192 B1192 8 1 B1193 B1193 9 1 B1194 B1194 10 1 B1195 B1195 11 1 B1196 B1196 12 1 B1197 B1197 13 1 B1198 B1198 14 1 B1199 B1199 15 1 B1200 B1200 16 1 B1201 B1201 17 1 B1202 B1202 18 1 B1203 B1203 19 1 B1204 B1204 20 1 B1205 B1205 21 1 B1206 B1206 22 1 B1207 B1207 23 1 B1208 B1208 24 1 B1209 B1209 25 1 B1210 B1210 26 1 B1211 B1211 27 1 B1212 B1212 28 1 B1213 B1213 29 1 B1214 B1214 30 1 B1215 B1215 31 1 MPCBB2_VCTR38 MPCBB2_VCTR38 MPCBBx vector register 0x198 0x20 read-write 0x00000000 B1216 B1216 0 1 B1217 B1217 1 1 B1218 B1218 2 1 B1219 B1219 3 1 B1220 B1220 4 1 B1221 B1221 5 1 B1222 B1222 6 1 B1223 B1223 7 1 B1224 B1224 8 1 B1225 B1225 9 1 B1226 B1226 10 1 B1227 B1227 11 1 B1228 B1228 12 1 B1229 B1229 13 1 B1230 B1230 14 1 B1231 B1231 15 1 B1232 B1232 16 1 B1233 B1233 17 1 B1234 B1234 18 1 B1235 B1235 19 1 B1236 B1236 20 1 B1237 B1237 21 1 B1238 B1238 22 1 B1239 B1239 23 1 B1240 B1240 24 1 B1241 B1241 25 1 B1242 B1242 26 1 B1243 B1243 27 1 B1244 B1244 28 1 B1245 B1245 29 1 B1246 B1246 30 1 B1247 B1247 31 1 MPCBB2_VCTR39 MPCBB2_VCTR39 MPCBBx vector register 0x19C 0x20 read-write 0x00000000 B1248 B1248 0 1 B1249 B1249 1 1 B1250 B1250 2 1 B1251 B1251 3 1 B1252 B1252 4 1 B1253 B1253 5 1 B1254 B1254 6 1 B1255 B1255 7 1 B1256 B1256 8 1 B1257 B1257 9 1 B1258 B1258 10 1 B1259 B1259 11 1 B1260 B1260 12 1 B1261 B1261 13 1 B1262 B1262 14 1 B1263 B1263 15 1 B1264 B1264 16 1 B1265 B1265 17 1 B1266 B1266 18 1 B1267 B1267 19 1 B1268 B1268 20 1 B1269 B1269 21 1 B1270 B1270 22 1 B1271 B1271 23 1 B1272 B1272 24 1 B1273 B1273 25 1 B1274 B1274 26 1 B1275 B1275 27 1 B1276 B1276 28 1 B1277 B1277 29 1 B1278 B1278 30 1 B1279 B1279 31 1 MPCBB2_VCTR40 MPCBB2_VCTR40 MPCBBx vector register 0x1A0 0x20 read-write 0x00000000 B1280 B1280 0 1 B1281 B1281 1 1 B1282 B1282 2 1 B1283 B1283 3 1 B1284 B1284 4 1 B1285 B1285 5 1 B1286 B1286 6 1 B1287 B1287 7 1 B1288 B1288 8 1 B1289 B1289 9 1 B1290 B1290 10 1 B1291 B1291 11 1 B1292 B1292 12 1 B1293 B1293 13 1 B1294 B1294 14 1 B1295 B1295 15 1 B1296 B1296 16 1 B1297 B1297 17 1 B1298 B1298 18 1 B1299 B1299 19 1 B1300 B1300 20 1 B1301 B1301 21 1 B1302 B1302 22 1 B1303 B1303 23 1 B1304 B1304 24 1 B1305 B1305 25 1 B1306 B1306 26 1 B1307 B1307 27 1 B1308 B1308 28 1 B1309 B1309 29 1 B1310 B1310 30 1 B1311 B1311 31 1 MPCBB2_VCTR41 MPCBB2_VCTR41 MPCBBx vector register 0x1A4 0x20 read-write 0x00000000 B1312 B1312 0 1 B1313 B1313 1 1 B1314 B1314 2 1 B1315 B1315 3 1 B1316 B1316 4 1 B1317 B1317 5 1 B1318 B1318 6 1 B1319 B1319 7 1 B1320 B1320 8 1 B1321 B1321 9 1 B1322 B1322 10 1 B1323 B1323 11 1 B1324 B1324 12 1 B1325 B1325 13 1 B1326 B1326 14 1 B1327 B1327 15 1 B1328 B1328 16 1 B1329 B1329 17 1 B1330 B1330 18 1 B1331 B1331 19 1 B1332 B1332 20 1 B1333 B1333 21 1 B1334 B1334 22 1 B1335 B1335 23 1 B1336 B1336 24 1 B1337 B1337 25 1 B1338 B1338 26 1 B1339 B1339 27 1 B1340 B1340 28 1 B1341 B1341 29 1 B1342 B1342 30 1 B1343 B1343 31 1 MPCBB2_VCTR42 MPCBB2_VCTR42 MPCBBx vector register 0x1A8 0x20 read-write 0x00000000 B1344 B1344 0 1 B1345 B1345 1 1 B1346 B1346 2 1 B1347 B1347 3 1 B1348 B1348 4 1 B1349 B1349 5 1 B1350 B1350 6 1 B1351 B1351 7 1 B1352 B1352 8 1 B1353 B1353 9 1 B1354 B1354 10 1 B1355 B1355 11 1 B1356 B1356 12 1 B1357 B1357 13 1 B1358 B1358 14 1 B1359 B1359 15 1 B1360 B1360 16 1 B1361 B1361 17 1 B1362 B1362 18 1 B1363 B1363 19 1 B1364 B1364 20 1 B1365 B1365 21 1 B1366 B1366 22 1 B1367 B1367 23 1 B1368 B1368 24 1 B1369 B1369 25 1 B1370 B1370 26 1 B1371 B1371 27 1 B1372 B1372 28 1 B1373 B1373 29 1 B1374 B1374 30 1 B1375 B1375 31 1 MPCBB2_VCTR43 MPCBB2_VCTR43 MPCBBx vector register 0x1AC 0x20 read-write 0x00000000 B1376 B1376 0 1 B1377 B1377 1 1 B1378 B1378 2 1 B1379 B1379 3 1 B1380 B1380 4 1 B1381 B1381 5 1 B1382 B1382 6 1 B1383 B1383 7 1 B1384 B1384 8 1 B1385 B1385 9 1 B1386 B1386 10 1 B1387 B1387 11 1 B1388 B1388 12 1 B1389 B1389 13 1 B1390 B1390 14 1 B1391 B1391 15 1 B1392 B1392 16 1 B1393 B1393 17 1 B1394 B1394 18 1 B1395 B1395 19 1 B1396 B1396 20 1 B1397 B1397 21 1 B1398 B1398 22 1 B1399 B1399 23 1 B1400 B1400 24 1 B1401 B1401 25 1 B1402 B1402 26 1 B1403 B1403 27 1 B1404 B1404 28 1 B1405 B1405 29 1 B1406 B1406 30 1 B1407 B1407 31 1 MPCBB2_VCTR44 MPCBB2_VCTR44 MPCBBx vector register 0x1B0 0x20 read-write 0x00000000 B1408 B1408 0 1 B1409 B1409 1 1 B1410 B1410 2 1 B1411 B1411 3 1 B1412 B1412 4 1 B1413 B1413 5 1 B1414 B1414 6 1 B1415 B1415 7 1 B1416 B1416 8 1 B1417 B1417 9 1 B1418 B1418 10 1 B1419 B1419 11 1 B1420 B1420 12 1 B1421 B1421 13 1 B1422 B1422 14 1 B1423 B1423 15 1 B1424 B1424 16 1 B1425 B1425 17 1 B1426 B1426 18 1 B1427 B1427 19 1 B1428 B1428 20 1 B1429 B1429 21 1 B1430 B1430 22 1 B1431 B1431 23 1 B1432 B1432 24 1 B1433 B1433 25 1 B1434 B1434 26 1 B1435 B1435 27 1 B1436 B1436 28 1 B1437 B1437 29 1 B1438 B1438 30 1 B1439 B1439 31 1 MPCBB2_VCTR45 MPCBB2_VCTR45 MPCBBx vector register 0x1B4 0x20 read-write 0x00000000 B1440 B1440 0 1 B1441 B1441 1 1 B1442 B1442 2 1 B1443 B1443 3 1 B1444 B1444 4 1 B1445 B1445 5 1 B1446 B1446 6 1 B1447 B1447 7 1 B1448 B1448 8 1 B1449 B1449 9 1 B1450 B1450 10 1 B1451 B1451 11 1 B1452 B1452 12 1 B1453 B1453 13 1 B1454 B1454 14 1 B1455 B1455 15 1 B1456 B1456 16 1 B1457 B1457 17 1 B1458 B1458 18 1 B1459 B1459 19 1 B1460 B1460 20 1 B1461 B1461 21 1 B1462 B1462 22 1 B1463 B1463 23 1 B1464 B1464 24 1 B1465 B1465 25 1 B1466 B1466 26 1 B1467 B1467 27 1 B1468 B1468 28 1 B1469 B1469 29 1 B1470 B1470 30 1 B1471 B1471 31 1 MPCBB2_VCTR46 MPCBB2_VCTR46 MPCBBx vector register 0x1B8 0x20 read-write 0x00000000 B1472 B1472 0 1 B1473 B1473 1 1 B1474 B1474 2 1 B1475 B1475 3 1 B1476 B1476 4 1 B1477 B1477 5 1 B1478 B1478 6 1 B1479 B1479 7 1 B1480 B1480 8 1 B1481 B1481 9 1 B1482 B1482 10 1 B1483 B1483 11 1 B1484 B1484 12 1 B1485 B1485 13 1 B1486 B1486 14 1 B1487 B1487 15 1 B1488 B1488 16 1 B1489 B1489 17 1 B1490 B1490 18 1 B1491 B1491 19 1 B1492 B1492 20 1 B1493 B1493 21 1 B1494 B1494 22 1 B1495 B1495 23 1 B1496 B1496 24 1 B1497 B1497 25 1 B1498 B1498 26 1 B1499 B1499 27 1 B1500 B1500 28 1 B1501 B1501 29 1 B1502 B1502 30 1 B1503 B1503 31 1 MPCBB2_VCTR47 MPCBB2_VCTR47 MPCBBx vector register 0x1BC 0x20 read-write 0x00000000 B1504 B1504 0 1 B1505 B1505 1 1 B1506 B1506 2 1 B1507 B1507 3 1 B1508 B1508 4 1 B1509 B1509 5 1 B1510 B1510 6 1 B1511 B1511 7 1 B1512 B1512 8 1 B1513 B1513 9 1 B1514 B1514 10 1 B1515 B1515 11 1 B1516 B1516 12 1 B1517 B1517 13 1 B1518 B1518 14 1 B1519 B1519 15 1 B1520 B1520 16 1 B1521 B1521 17 1 B1522 B1522 18 1 B1523 B1523 19 1 B1524 B1524 20 1 B1525 B1525 21 1 B1526 B1526 22 1 B1527 B1527 23 1 B1528 B1528 24 1 B1529 B1529 25 1 B1530 B1530 26 1 B1531 B1531 27 1 B1532 B1532 28 1 B1533 B1533 29 1 B1534 B1534 30 1 B1535 B1535 31 1 MPCBB2_VCTR48 MPCBB2_VCTR48 MPCBBx vector register 0x1C0 0x20 read-write 0x00000000 B1536 B1536 0 1 B1537 B1537 1 1 B1538 B1538 2 1 B1539 B1539 3 1 B1540 B1540 4 1 B1541 B1541 5 1 B1542 B1542 6 1 B1543 B1543 7 1 B1544 B1544 8 1 B1545 B1545 9 1 B1546 B1546 10 1 B1547 B1547 11 1 B1548 B1548 12 1 B1549 B1549 13 1 B1550 B1550 14 1 B1551 B1551 15 1 B1552 B1552 16 1 B1553 B1553 17 1 B1554 B1554 18 1 B1555 B1555 19 1 B1556 B1556 20 1 B1557 B1557 21 1 B1558 B1558 22 1 B1559 B1559 23 1 B1560 B1560 24 1 B1561 B1561 25 1 B1562 B1562 26 1 B1563 B1563 27 1 B1564 B1564 28 1 B1565 B1565 29 1 B1566 B1566 30 1 B1567 B1567 31 1 MPCBB2_VCTR49 MPCBB2_VCTR49 MPCBBx vector register 0x1C4 0x20 read-write 0x00000000 B1568 B1568 0 1 B1569 B1569 1 1 B1570 B1570 2 1 B1571 B1571 3 1 B1572 B1572 4 1 B1573 B1573 5 1 B1574 B1574 6 1 B1575 B1575 7 1 B1576 B1576 8 1 B1577 B1577 9 1 B1578 B1578 10 1 B1579 B1579 11 1 B1580 B1580 12 1 B1581 B1581 13 1 B1582 B1582 14 1 B1583 B1583 15 1 B1584 B1584 16 1 B1585 B1585 17 1 B1586 B1586 18 1 B1587 B1587 19 1 B1588 B1588 20 1 B1589 B1589 21 1 B1590 B1590 22 1 B1591 B1591 23 1 B1592 B1592 24 1 B1593 B1593 25 1 B1594 B1594 26 1 B1595 B1595 27 1 B1596 B1596 28 1 B1597 B1597 29 1 B1598 B1598 30 1 B1599 B1599 31 1 MPCBB2_VCTR50 MPCBB2_VCTR50 MPCBBx vector register 0x1C8 0x20 read-write 0x00000000 B1600 B1600 0 1 B1601 B1601 1 1 B1602 B1602 2 1 B1603 B1603 3 1 B1604 B1604 4 1 B1605 B1605 5 1 B1606 B1606 6 1 B1607 B1607 7 1 B1608 B1608 8 1 B1609 B1609 9 1 B1610 B1610 10 1 B1611 B1611 11 1 B1612 B1612 12 1 B1613 B1613 13 1 B1614 B1614 14 1 B1615 B1615 15 1 B1616 B1616 16 1 B1617 B1617 17 1 B1618 B1618 18 1 B1619 B1619 19 1 B1620 B1620 20 1 B1621 B1621 21 1 B1622 B1622 22 1 B1623 B1623 23 1 B1624 B1624 24 1 B1625 B1625 25 1 B1626 B1626 26 1 B1627 B1627 27 1 B1628 B1628 28 1 B1629 B1629 29 1 B1630 B1630 30 1 B1631 B1631 31 1 MPCBB2_VCTR51 MPCBB2_VCTR51 MPCBBx vector register 0x1CC 0x20 read-write 0x00000000 B1632 B1632 0 1 B1633 B1633 1 1 B1634 B1634 2 1 B1635 B1635 3 1 B1636 B1636 4 1 B1637 B1637 5 1 B1638 B1638 6 1 B1639 B1639 7 1 B1640 B1640 8 1 B1641 B1641 9 1 B1642 B1642 10 1 B1643 B1643 11 1 B1644 B1644 12 1 B1645 B1645 13 1 B1646 B1646 14 1 B1647 B1647 15 1 B1648 B1648 16 1 B1649 B1649 17 1 B1650 B1650 18 1 B1651 B1651 19 1 B1652 B1652 20 1 B1653 B1653 21 1 B1654 B1654 22 1 B1655 B1655 23 1 B1656 B1656 24 1 B1657 B1657 25 1 B1658 B1658 26 1 B1659 B1659 27 1 B1660 B1660 28 1 B1661 B1661 29 1 B1662 B1662 30 1 B1663 B1663 31 1 MPCBB2_VCTR52 MPCBB2_VCTR52 MPCBBx vector register 0x1D0 0x20 read-write 0x00000000 B1664 B1664 0 1 B1665 B1665 1 1 B1666 B1666 2 1 B1667 B1667 3 1 B1668 B1668 4 1 B1669 B1669 5 1 B1670 B1670 6 1 B1671 B1671 7 1 B1672 B1672 8 1 B1673 B1673 9 1 B1674 B1674 10 1 B1675 B1675 11 1 B1676 B1676 12 1 B1677 B1677 13 1 B1678 B1678 14 1 B1679 B1679 15 1 B1680 B1680 16 1 B1681 B1681 17 1 B1682 B1682 18 1 B1683 B1683 19 1 B1684 B1684 20 1 B1685 B1685 21 1 B1686 B1686 22 1 B1687 B1687 23 1 B1688 B1688 24 1 B1689 B1689 25 1 B1690 B1690 26 1 B1691 B1691 27 1 B1692 B1692 28 1 B1693 B1693 29 1 B1694 B1694 30 1 B1695 B1695 31 1 MPCBB2_VCTR53 MPCBB2_VCTR53 MPCBBx vector register 0x1D4 0x20 read-write 0x00000000 B1696 B1696 0 1 B1697 B1697 1 1 B1698 B1698 2 1 B1699 B1699 3 1 B1700 B1700 4 1 B1701 B1701 5 1 B1702 B1702 6 1 B1703 B1703 7 1 B1704 B1704 8 1 B1705 B1705 9 1 B1706 B1706 10 1 B1707 B1707 11 1 B1708 B1708 12 1 B1709 B1709 13 1 B1710 B1710 14 1 B1711 B1711 15 1 B1712 B1712 16 1 B1713 B1713 17 1 B1714 B1714 18 1 B1715 B1715 19 1 B1716 B1716 20 1 B1717 B1717 21 1 B1718 B1718 22 1 B1719 B1719 23 1 B1720 B1720 24 1 B1721 B1721 25 1 B1722 B1722 26 1 B1723 B1723 27 1 B1724 B1724 28 1 B1725 B1725 29 1 B1726 B1726 30 1 B1727 B1727 31 1 MPCBB2_VCTR54 MPCBB2_VCTR54 MPCBBx vector register 0x1D8 0x20 read-write 0x00000000 B1728 B1728 0 1 B1729 B1729 1 1 B1730 B1730 2 1 B1731 B1731 3 1 B1732 B1732 4 1 B1733 B1733 5 1 B1734 B1734 6 1 B1735 B1735 7 1 B1736 B1736 8 1 B1737 B1737 9 1 B1738 B1738 10 1 B1739 B1739 11 1 B1740 B1740 12 1 B1741 B1741 13 1 B1742 B1742 14 1 B1743 B1743 15 1 B1744 B1744 16 1 B1745 B1745 17 1 B1746 B1746 18 1 B1747 B1747 19 1 B1748 B1748 20 1 B1749 B1749 21 1 B1750 B1750 22 1 B1751 B1751 23 1 B1752 B1752 24 1 B1753 B1753 25 1 B1754 B1754 26 1 B1755 B1755 27 1 B1756 B1756 28 1 B1757 B1757 29 1 B1758 B1758 30 1 B1759 B1759 31 1 MPCBB2_VCTR55 MPCBB2_VCTR55 MPCBBx vector register 0x1DC 0x20 read-write 0x00000000 B1760 B1760 0 1 B1761 B1761 1 1 B1762 B1762 2 1 B1763 B1763 3 1 B1764 B1764 4 1 B1765 B1765 5 1 B1766 B1766 6 1 B1767 B1767 7 1 B1768 B1768 8 1 B1769 B1769 9 1 B1770 B1770 10 1 B1771 B1771 11 1 B1772 B1772 12 1 B1773 B1773 13 1 B1774 B1774 14 1 B1775 B1775 15 1 B1776 B1776 16 1 B1777 B1777 17 1 B1778 B1778 18 1 B1779 B1779 19 1 B1780 B1780 20 1 B1781 B1781 21 1 B1782 B1782 22 1 B1783 B1783 23 1 B1784 B1784 24 1 B1785 B1785 25 1 B1786 B1786 26 1 B1787 B1787 27 1 B1788 B1788 28 1 B1789 B1789 29 1 B1790 B1790 30 1 B1791 B1791 31 1 MPCBB2_VCTR56 MPCBB2_VCTR56 MPCBBx vector register 0x1E0 0x20 read-write 0x00000000 B1792 B1792 0 1 B1793 B1793 1 1 B1794 B1794 2 1 B1795 B1795 3 1 B1796 B1796 4 1 B1797 B1797 5 1 B1798 B1798 6 1 B1799 B1799 7 1 B1800 B1800 8 1 B1801 B1801 9 1 B1802 B1802 10 1 B1803 B1803 11 1 B1804 B1804 12 1 B1805 B1805 13 1 B1806 B1806 14 1 B1807 B1807 15 1 B1808 B1808 16 1 B1809 B1809 17 1 B1810 B1810 18 1 B1811 B1811 19 1 B1812 B1812 20 1 B1813 B1813 21 1 B1814 B1814 22 1 B1815 B1815 23 1 B1816 B1816 24 1 B1817 B1817 25 1 B1818 B1818 26 1 B1819 B1819 27 1 B1820 B1820 28 1 B1821 B1821 29 1 B1822 B1822 30 1 B1823 B1823 31 1 MPCBB2_VCTR57 MPCBB2_VCTR57 MPCBBx vector register 0x1E4 0x20 read-write 0x00000000 B1824 B1824 0 1 B1825 B1825 1 1 B1826 B1826 2 1 B1827 B1827 3 1 B1828 B1828 4 1 B1829 B1829 5 1 B1830 B1830 6 1 B1831 B1831 7 1 B1832 B1832 8 1 B1833 B1833 9 1 B1834 B1834 10 1 B1835 B1835 11 1 B1836 B1836 12 1 B1837 B1837 13 1 B1838 B1838 14 1 B1839 B1839 15 1 B1840 B1840 16 1 B1841 B1841 17 1 B1842 B1842 18 1 B1843 B1843 19 1 B1844 B1844 20 1 B1845 B1845 21 1 B1846 B1846 22 1 B1847 B1847 23 1 B1848 B1848 24 1 B1849 B1849 25 1 B1850 B1850 26 1 B1851 B1851 27 1 B1852 B1852 28 1 B1853 B1853 29 1 B1854 B1854 30 1 B1855 B1855 31 1 MPCBB2_VCTR58 MPCBB2_VCTR58 MPCBBx vector register 0x1E8 0x20 read-write 0x00000000 B1856 B1856 0 1 B1857 B1857 1 1 B1858 B1858 2 1 B1859 B1859 3 1 B1860 B1860 4 1 B1861 B1861 5 1 B1862 B1862 6 1 B1863 B1863 7 1 B1864 B1864 8 1 B1865 B1865 9 1 B1866 B1866 10 1 B1867 B1867 11 1 B1868 B1868 12 1 B1869 B1869 13 1 B1870 B1870 14 1 B1871 B1871 15 1 B1872 B1872 16 1 B1873 B1873 17 1 B1874 B1874 18 1 B1875 B1875 19 1 B1876 B1876 20 1 B1877 B1877 21 1 B1878 B1878 22 1 B1879 B1879 23 1 B1880 B1880 24 1 B1881 B1881 25 1 B1882 B1882 26 1 B1883 B1883 27 1 B1884 B1884 28 1 B1885 B1885 29 1 B1886 B1886 30 1 B1887 B1887 31 1 MPCBB2_VCTR59 MPCBB2_VCTR59 MPCBBx vector register 0x1EC 0x20 read-write 0x00000000 B1888 B1888 0 1 B1889 B1889 1 1 B1890 B1890 2 1 B1891 B1891 3 1 B1892 B1892 4 1 B1893 B1893 5 1 B1894 B1894 6 1 B1895 B1895 7 1 B1896 B1896 8 1 B1897 B1897 9 1 B1898 B1898 10 1 B1899 B1899 11 1 B1900 B1900 12 1 B1901 B1901 13 1 B1902 B1902 14 1 B1903 B1903 15 1 B1904 B1904 16 1 B1905 B1905 17 1 B1906 B1906 18 1 B1907 B1907 19 1 B1908 B1908 20 1 B1909 B1909 21 1 B1910 B1910 22 1 B1911 B1911 23 1 B1912 B1912 24 1 B1913 B1913 25 1 B1914 B1914 26 1 B1915 B1915 27 1 B1916 B1916 28 1 B1917 B1917 29 1 B1918 B1918 30 1 B1919 B1919 31 1 MPCBB2_VCTR60 MPCBB2_VCTR60 MPCBBx vector register 0x1F0 0x20 read-write 0x00000000 B1920 B1920 0 1 B1921 B1921 1 1 B1922 B1922 2 1 B1923 B1923 3 1 B1924 B1924 4 1 B1925 B1925 5 1 B1926 B1926 6 1 B1927 B1927 7 1 B1928 B1928 8 1 B1929 B1929 9 1 B1930 B1930 10 1 B1931 B1931 11 1 B1932 B1932 12 1 B1933 B1933 13 1 B1934 B1934 14 1 B1935 B1935 15 1 B1936 B1936 16 1 B1937 B1937 17 1 B1938 B1938 18 1 B1939 B1939 19 1 B1940 B1940 20 1 B1941 B1941 21 1 B1942 B1942 22 1 B1943 B1943 23 1 B1944 B1944 24 1 B1945 B1945 25 1 B1946 B1946 26 1 B1947 B1947 27 1 B1948 B1948 28 1 B1949 B1949 29 1 B1950 B1950 30 1 B1951 B1951 31 1 MPCBB2_VCTR61 MPCBB2_VCTR61 MPCBBx vector register 0x1F4 0x20 read-write 0x00000000 B1952 B1952 0 1 B1953 B1953 1 1 B1954 B1954 2 1 B1955 B1955 3 1 B1956 B1956 4 1 B1957 B1957 5 1 B1958 B1958 6 1 B1959 B1959 7 1 B1960 B1960 8 1 B1961 B1961 9 1 B1962 B1962 10 1 B1963 B1963 11 1 B1964 B1964 12 1 B1965 B1965 13 1 B1966 B1966 14 1 B1967 B1967 15 1 B1968 B1968 16 1 B1969 B1969 17 1 B1970 B1970 18 1 B1971 B1971 19 1 B1972 B1972 20 1 B1973 B1973 21 1 B1974 B1974 22 1 B1975 B1975 23 1 B1976 B1976 24 1 B1977 B1977 25 1 B1978 B1978 26 1 B1979 B1979 27 1 B1980 B1980 28 1 B1981 B1981 29 1 B1982 B1982 30 1 B1983 B1983 31 1 MPCBB2_VCTR62 MPCBB2_VCTR62 MPCBBx vector register 0x1F8 0x20 read-write 0x00000000 B1984 B1984 0 1 B1985 B1985 1 1 B1986 B1986 2 1 B1987 B1987 3 1 B1988 B1988 4 1 B1989 B1989 5 1 B1990 B1990 6 1 B1991 B1991 7 1 B1992 B1992 8 1 B1993 B1993 9 1 B1994 B1994 10 1 B1995 B1995 11 1 B1996 B1996 12 1 B1997 B1997 13 1 B1998 B1998 14 1 B1999 B1999 15 1 B2000 B2000 16 1 B2001 B2001 17 1 B2002 B2002 18 1 B2003 B2003 19 1 B2004 B2004 20 1 B2005 B2005 21 1 B2006 B2006 22 1 B2007 B2007 23 1 B2008 B2008 24 1 B2009 B2009 25 1 B2010 B2010 26 1 B2011 B2011 27 1 B2012 B2012 28 1 B2013 B2013 29 1 B2014 B2014 30 1 B2015 B2015 31 1 MPCBB2_VCTR63 MPCBB2_VCTR63 MPCBBx vector register 0x1FC 0x20 read-write 0x00000000 B2016 B2016 0 1 B2017 B2017 1 1 B2018 B2018 2 1 B2019 B2019 3 1 B2020 B2020 4 1 B2021 B2021 5 1 B2022 B2022 6 1 B2023 B2023 7 1 B2024 B2024 8 1 B2025 B2025 9 1 B2026 B2026 10 1 B2027 B2027 11 1 B2028 B2028 12 1 B2029 B2029 13 1 B2030 B2030 14 1 B2031 B2031 15 1 B2032 B2032 16 1 B2033 B2033 17 1 B2034 B2034 18 1 B2035 B2035 19 1 B2036 B2036 20 1 B2037 B2037 21 1 B2038 B2038 22 1 B2039 B2039 23 1 B2040 B2040 24 1 B2041 B2041 25 1 B2042 B2042 26 1 B2043 B2043 27 1 B2044 B2044 28 1 B2045 B2045 29 1 B2046 B2046 30 1 B2047 B2047 31 1 SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 059 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 RXONLY Receive only 10 1 SSM Software slave management 9 1 SSI Internal slave select 8 1 LSBFIRST Frame format 7 1 SPE SPI enable 6 1 BR Baud rate control 3 3 MSTR Master selection 2 1 CPOL Clock polarity 1 1 CPHA Clock phase 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 RXDMAEN Rx buffer DMA enable 0 1 TXDMAEN Tx buffer DMA enable 1 1 SSOE SS output enable 2 1 NSSP NSS pulse management 3 1 FRF Frame format 4 1 ERRIE Error interrupt enable 5 1 RXNEIE RX buffer not empty interrupt enable 6 1 TXEIE Tx buffer empty interrupt enable 7 1 DS Data size 8 4 FRXTH FIFO reception threshold 12 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_TX Last DMA transfer for transmission 14 1 SR SR status register 0x8 0x20 0x0002 RXNE Receive buffer not empty 0 1 read-only TXE Transmit buffer empty 1 1 read-only CRCERR CRC error flag 4 1 read-write MODF Mode fault 5 1 read-only OVR Overrun flag 6 1 read-only BSY Busy flag 7 1 read-only TIFRFE TI frame format error 8 1 read-only FRLVL FIFO reception level 9 2 read-only FTLVL FIFO transmission level 11 2 read-only DR DR data register 0xC 0x20 read-write 0x0000 DR Data register 0 16 CRCPR CRCPR CRC polynomial register 0x10 0x20 read-write 0x0007 CRCPOLY CRC polynomial register 0 16 RXCRCR RXCRCR RX CRC register 0x14 0x20 read-only 0x0000 RxCRC Rx CRC register 0 16 TXCRCR TXCRCR TX CRC register 0x18 0x20 read-only 0x0000 TxCRC Tx CRC register 0 16 SPI2 0x40003800 SPI2 SPI2 global interrupt 060 SPI3 0x40003C00 SPI3 SPI3 099 SEC_SPI1 !(DCB->DSCSR & (1 << 16)) 0x50013000 SEC_SPI2 !(DCB->DSCSR & (1 << 16)) 0x50003800 SEC_SPI3 !(DCB->DSCSR & (1 << 16)) 0x50003C00 TIM1 Advanced-timers TIM 0x40012C00 0x0 0x400 registers TIM1_BRK TIM1 Break 041 TIM1_UP TIM1 Update 042 TIM1_TRG_COM TIM1 Trigger and Commutation 043 TIM1_CC TIM1 Capture Compare interrupt 044 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 OIS4 Output Idle state 4 14 1 OIS3N Output Idle state 3 13 1 OIS3 Output Idle state 3 12 1 OIS2N Output Idle state 2 11 1 OIS2 Output Idle state 2 10 1 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 OIS5 Output Idle state 5 (OC5 output) 15 1 OIS6 Output Idle state 6 16 1 MMS2 Master mode selection 2 20 4 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 SMS_bit3 Slave mode selection - bit 3 16 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 COMDE COM DMA request enable 13 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 BIE Break interrupt enable 7 1 COMIE COM interrupt enable 5 1 SR SR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 COMIF COM interrupt flag 5 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 SBIF System Break interrupt flag 13 1 CC5IF Compare 5 interrupt flag 16 1 CC6IF Compare 6 interrupt flag 17 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 BG Break generation 7 1 TG Trigger generation 6 1 COMG Capture/Compare control update generation 5 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 B2G Break 2 generation 8 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2CE Output Compare 2 clear enable 15 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 OC2FE Output Compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 OC1M_bit3 Output Compare 1 mode - bit 3 16 1 OC2M_bit3 Output Compare 2 mode - bit 3 24 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PCS Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 ICPCS Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 OC3M_bit3 Output Compare 3 mode - bit 3 16 1 OC4M_bit3 Output Compare 4 mode - bit 3 24 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CC4NP Capture/Compare 4 complementary output polarity 15 1 CC5E Capture/Compare 5 output enable 16 1 CC5P Capture/Compare 5 output polarity 17 1 CC6E Capture/Compare 6 output enable 20 1 CC6P Capture/Compare 6 output polarity 21 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write UIFCPY UIF copy 31 1 read-only PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2 Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3 Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4 Capture/Compare value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 MOE Main output enable 15 1 AOE Automatic output enable 14 1 BKP Break polarity 13 1 BKE Break enable 12 1 OSSR Off-state selection for Run mode 11 1 OSSI Off-state selection for Idle mode 10 1 LOCK Lock configuration 8 2 DTG Dead-time generator setup 0 8 BKF Break filter 16 4 BK2F Break 2 filter 20 4 BK2E Break 2 enable 24 1 BK2P Break 2 polarity 25 1 BKDSRM Break Disarm 26 1 BK2DSRM Break2 Disarm 27 1 BKBID Break Bidirectional 28 1 BK2BID Break2 bidirectional 29 1 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 32 OR1 OR1 DMA address for full transfer 0x50 0x20 read-write 0x0000 ETR_ADC1_RMP External trigger remap on ADC1 analog watchdog 0 2 TI1_RMP Input Capture 1 remap 4 1 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x54 0x20 read-write 0x00000000 OC6M_bit3 Output Compare 6 mode bit 3 24 1 OC5M_bit3 Output Compare 5 mode bit 3 16 3 OC6CE Output compare 6 clear enable 15 1 OC6M Output compare 6 mode 12 3 OC6PE Output compare 6 preload enable 11 1 OC6FE Output compare 6 fast enable 10 1 OC5CE Output compare 5 clear enable 7 1 OC5M Output compare 5 mode 4 3 OC5PE Output compare 5 preload enable 3 1 OC5FE Output compare 5 fast enable 2 1 CCR5 CCR5 capture/compare register 4 0x58 0x20 read-write 0x00000000 CCR5 Capture/Compare value 0 16 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 4 0x5C 0x20 read-write 0x00000000 CCR6 Capture/Compare value 0 16 OR2 OR2 DMA address for full transfer 0x60 0x20 read-write 0x00000001 BKINE BRK BKIN input enable 0 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP2E BRK COMP2 enable 2 1 BKDFBK0E BRK DFSDM_BREAK0 enable 8 1 BKINP BRK BKIN input polarity 9 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2P BRK COMP2 input polarity 11 1 ETRSEL ETR source selection 14 3 OR3 OR3 DMA address for full transfer 0x64 0x20 read-write 0x00000001 BK2INE BRK2 BKIN input enable 0 1 BK2CMP1E BRK2 COMP1 enable 1 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2DFBK0E BRK2 DFSDM_BREAK0 enable 8 1 BK2INP BRK2 BKIN input polarity 9 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 SEC_TIM1 !(DCB->DSCSR & (1 << 16)) 0x50012C00 TIM15 General purpose timers TIM 0x40014000 0x0 0x400 registers TIM15 TIM15 global interrupt 069 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CEN Counter enable 0 1 UDIS Update disable 1 1 URS Update request source 2 1 OPM One-pulse mode 3 1 ARPE Auto-reload preload enable 7 1 CKD Clock division 8 2 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 MMS Master mode selection 4 2 TI1S TI1 selection 7 1 OIS2 Output idle state 2 (OC2 output) 10 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 COMDE COM DMA request enable 13 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 BIE Break interrupt enable 7 1 TIE Trigger interrupt enable 6 1 COMIE COM interrupt enable 5 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 SR SR status register 0x10 0x20 read-write 0x0000 CC1OF Capture/Compare 1 overcapture flag 9 1 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 COMIF COM interrupt flag 5 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 CC2OF Capture/Compare 2 overcapture flag 10 1 CC2IF Capture/Compare 2 interrupt flag 2 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 BG Break generation 7 1 TG Trigger generation 6 1 COMG Capture/Compare control update generation 5 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CC2G Capture/Compare 2 generation 2 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 OC1M_bit3 Output Compare 1 mode 16 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 OC2M_bit3 Output Compare 2 mode - bit 3 24 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 CC2S Capture/Compare 2 selection 8 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CC2NP Capture/Compare 2 complementary output polarity 7 1 CC2P Capture/Compare 2 output polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 BKE Break enable 12 1 BKP Break polarity 13 1 AOE Automatic output enable 14 1 MOE Main output enable 15 1 BKBID Break Bidirectional 28 1 BKDSRM Break Disarm 26 1 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 SMCR SMCR TIM15 slave mode control register 0x8 0x20 read-write 0x0000 SMS Slave mode selection 0 3 TS Trigger selection 4 3 MSM Master/slave mode 7 1 SMS_bit3 Slave mode selection - bit 3 16 1 OR1 OR1 TIM15 option register 1 0x50 0x20 read-write 0x0000 ENCODER_MODE Encoder mode 1 2 TI1_RMP Input capture 1 remap 0 1 OR2 OR2 TIM15 option register 2 0x60 0x20 read-write 0x0000 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP1P BRK COMP1 input polarity 10 1 BKINP BRK BKIN input polarity 9 1 BKDF1BK0E BRK dfsdm1_break[0] enable 8 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP1E BRK COMP1 enable 1 1 BKINE BRK BKIN input enable 0 1 CCR2 CCR2 TIM15 capture/compare register 2 PSC 0x28 0x20 read-write 0x0000 CCR2 Capture/Compare 2 value 0 16 SEC_TIM15 !(DCB->DSCSR & (1 << 16)) 0x50014000 TIM16 General purpose timers TIM 0x40014400 0x0 0x400 registers TIM16 TIM16 global interrupt 070 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CEN Counter enable 0 1 UDIS Update disable 1 1 URS Update request source 2 1 OPM One-pulse mode 3 1 ARPE Auto-reload preload enable 7 1 CKD Clock division 8 2 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 COMDE COM DMA request enable 13 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 BIE Break interrupt enable 7 1 COMIE COM interrupt enable 5 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC1OF Capture/Compare 1 overcapture flag 9 1 BIF Break interrupt flag 7 1 COMIF COM interrupt flag 5 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 BG Break generation 7 1 COMG Capture/Compare control update generation 5 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 OC1M_2 Output Compare 1 mode 16 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0xFFFF ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 BKE Break enable 12 1 BKP Break polarity 13 1 AOE Automatic output enable 14 1 MOE Main output enable 15 1 BKBID Break Bidirectional 28 1 BKDSRM Break Disarm 26 1 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 OR1 OR1 TIM16 option register 1 0x50 0x20 read-write 0x0000 TI1_RMP Input capture 1 remap 0 2 OR2 OR2 TIM17 option register 1 0x60 0x20 read-write 0x00000001 BKINE BRK BKIN input enable 0 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP2E BRK COMP2 enable 2 1 BKDF1BK1E BRK dfsdm1_break[1] enable 8 1 BKINP BRK BKIN input polarity 9 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2P BRK COMP2 input polarit 11 1 SEC_TIM16 !(DCB->DSCSR & (1 << 16)) 0x50014400 TIM17 General purpose timers TIM 0x40014800 0x0 0x400 registers TIM17 TIM17 global interrupt 071 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CEN Counter enable 0 1 UDIS Update disable 1 1 URS Update request source 2 1 OPM One-pulse mode 3 1 ARPE Auto-reload preload enable 7 1 CKD Clock division 8 2 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 COMDE COM DMA request enable 13 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 BIE Break interrupt enable 7 1 COMIE COM interrupt enable 5 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC1OF Capture/Compare 1 overcapture flag 9 1 BIF Break interrupt flag 7 1 COMIF COM interrupt flag 5 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 BG Break generation 7 1 COMG Capture/Compare control update generation 5 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 OC1M_2 Output Compare 1 mode 16 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0xFFFF ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 BKE Break enable 12 1 BKP Break polarity 13 1 AOE Automatic output enable 14 1 MOE Main output enable 15 1 BKBID Break Bidirectional 28 1 BKDSRM Break Disarm 26 1 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 OR1 OR1 TIM16 option register 1 0x50 0x20 read-write 0x0000 TI1_RMP Input capture 1 remap 0 2 OR2 OR2 TIM17 option register 1 0x60 0x20 read-write 0x00000001 BKINE BRK BKIN input enable 0 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP2E BRK COMP2 enable 2 1 BKDF1BK2E BRK dfsdm1_break[2] enable 8 1 BKINP BRK BKIN input polarity 9 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2P BRK COMP2 input polarit 11 1 SEC_TIM17 !(DCB->DSCSR & (1 << 16)) 0x50014800 TIM2 General-purpose-timers TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global interrupt 045 TIM2_3 TIM3 global interrupt 046 TIM2_4 TIM4 global interrupt 047 TIM2_5 TIM5 global interrupt 048 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 SMS_bit3 Slave mode selection - bit 3 16 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 TIF Trigger interrupt flag 6 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 TG Trigger generation 6 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2CE Output compare 2 clear enable 15 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 OC2FE Output compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC1FE Output compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 OC2M_bit3 Output Compare 2 mode - bit 3 24 1 OC1M_bit3 Output Compare 1 mode - bit 3 16 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 OC4M_bit3 Output Compare 2 mode - bit 3 24 1 OC3M_bit3 Output Compare 1 mode - bit 3 16 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/Compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT_H Most significant part counter value (on TIM2 and TIM5) 16 15 CNT_L Least significant part of counter value 0 16 CNT_bit31 Most significant bit of counter value (on TIM2 and TIM5) 31 1 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0xFFFFFFFF ARR_H High Auto-reload value (TIM2 only) 16 16 ARR_L Low Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1_H High Capture/Compare 1 value (TIM2 only) 16 16 CCR1_L Low Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2_H High Capture/Compare 2 value (TIM2 only) 16 16 CCR2_L Low Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3_H High Capture/Compare value (TIM2 only) 16 16 CCR3_L Low Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4_H High Capture/Compare value (TIM2 only) 16 16 CCR4_L Low Capture/Compare value 0 16 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB Low Capture/Compare 2 value 0 16 OR1 OR1 TIM2 option register 0x50 0x20 read-write 0x0000 ITR1_RMP Internal trigger 1 remap 0 1 TI4_RMP Input Capture 4 remap 2 2 ETR1_RMP External trigger remap 1 1 OR2 OR2 TIM3 option register 2 0x60 0x20 read-write 0x0000 ETRSEL ETR source selection 14 3 SEC_TIM2 !(DCB->DSCSR & (1 << 16)) 0x50000000 TIM3 General-purpose-timers TIM 0x40000400 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 SMS_bit3 Slave mode selection - bit 3 16 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 TIF Trigger interrupt flag 6 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 TG Trigger generation 6 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2CE Output compare 2 clear enable 15 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 OC2FE Output compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC1FE Output compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 OC2M_bit3 Output Compare 2 mode - bit 3 24 1 OC1M_bit3 Output Compare 1 mode - bit 3 16 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 OC4M_bit3 Output Compare 2 mode - bit 3 24 1 OC3M_bit3 Output Compare 1 mode - bit 3 16 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/Compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT_H Most significant part counter value (on TIM2 and TIM5) 16 15 CNT_L Least significant part of counter value 0 16 CNT_bit31 Most significant bit of counter value (on TIM2 and TIM5) 31 1 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0xFFFFFFFF ARR_H High Auto-reload value (TIM2 only) 16 16 ARR_L Low Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1_H High Capture/Compare 1 value (TIM2 only) 16 16 CCR1_L Low Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2_H High Capture/Compare 2 value (TIM2 only) 16 16 CCR2_L Low Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3_H High Capture/Compare value (TIM2 only) 16 16 CCR3_L Low Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4_H High Capture/Compare value (TIM2 only) 16 16 CCR4_L Low Capture/Compare value 0 16 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB Low Capture/Compare 2 value 0 16 OR1 OR1 TIM2 option register 0x50 0x20 read-write 0x0000 ITR1_RMP Internal trigger 1 remap 0 1 OR2 OR2 TIM3 option register 2 0x60 0x20 read-write 0x0000 ETRSEL ETR source selection 14 3 SEC_TIM3 !(DCB->DSCSR & (1 << 16)) 0x50000400 TIM4 General-purpose-timers TIM 0x40000800 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 SMS_bit3 Slave mode selection - bit 3 16 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 TIF Trigger interrupt flag 6 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 TG Trigger generation 6 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2CE Output compare 2 clear enable 15 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 OC2FE Output compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC1FE Output compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 OC2M_bit3 Output Compare 2 mode - bit 3 24 1 OC1M_bit3 Output Compare 1 mode - bit 3 16 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 OC4M_bit3 Output Compare 2 mode - bit 3 24 1 OC3M_bit3 Output Compare 1 mode - bit 3 16 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/Compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT_H Most significant part counter value (on TIM2 and TIM5) 16 15 CNT_L Least significant part of counter value 0 16 CNT_bit31 Most significant bit of counter value (on TIM2 and TIM5) 31 1 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0xFFFFFFFF ARR_H High Auto-reload value (TIM2 only) 16 16 ARR_L Low Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1_H High Capture/Compare 1 value (TIM2 only) 16 16 CCR1_L Low Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2_H High Capture/Compare 2 value (TIM2 only) 16 16 CCR2_L Low Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3_H High Capture/Compare value (TIM2 only) 16 16 CCR3_L Low Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4_H High Capture/Compare value (TIM2 only) 16 16 CCR4_L Low Capture/Compare value 0 16 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB Low Capture/Compare 2 value 0 16 SEC_TIM4 !(DCB->DSCSR & (1 << 16)) 0x50000800 TIM5 0x40000C00 SEC_TIM5 !(DCB->DSCSR & (1 << 16)) 0x50000C00 TIM6 General-purpose-timers TIM 0x40001000 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 ARPE Auto-reload preload enable 7 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 UIFREMA UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 MMS Master mode selection 4 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 UG Update generation 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT_bit0 CNT 0 16 UIFCPY UIFCPY or Res 31 1 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0xFFFFFFFF ARR_bit0 ARR_bit0 0 16 SEC_TIM6 !(DCB->DSCSR & (1 << 16)) 0x50001000 TIM7 General-purpose-timers TIM 0x40001400 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 ARPE Auto-reload preload enable 7 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 UIFREMA UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 MMS Master mode selection 4 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 UG Update generation 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT_bit0 CNT 0 16 UIFCPY UIFCPY or Res 31 1 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0xFFFFFFFF ARR_bit0 ARR_bit0 0 16 SEC_TIM7 !(DCB->DSCSR & (1 << 16)) 0x50001400 DAC DAC DAC 0x40007400 0x0 0x400 registers DAC_CR DAC_CR DAC control register 0x0 0x20 read-write 0x00000000 EN1 DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1. 0 1 TEN1 DAC channel1 trigger enable 1 1 TSEL10 TSEL10 2 1 TSEL11 TSEL11 3 1 TSEL12 TSEL12 4 1 TSEL13 TSEL13 5 1 WAVE1 DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). 6 2 MAMP1 DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 8 4 DMAEN1 DAC channel1 DMA enable This bit is set and cleared by software. 12 1 DMAUDRIE1 DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software. 13 1 CEN1 DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 14 1 HFSEL HFSEL 15 1 EN2 DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. 16 1 TEN2 DAC channel2 trigger enable 17 1 TSEL20 TSEL20 18 1 TSEL21 TSEL21 19 1 TSEL22 TSEL22 20 1 TSEL23 TSEL23 21 1 WAVE2 DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) 22 2 MAMP2 DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 24 4 DMAEN2 DAC channel2 DMA enable This bit is set and cleared by software. 28 1 DMAUDRIE2 DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. 29 1 CEN2 DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 30 1 DAC_SWTRGR DAC_SWTRGR DAC software trigger register 0x4 0x20 write-only 0x00000000 SWTRIG1 DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register. 0 1 SWTRIG2 DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. 1 1 DAC_DHR12R1 DAC_DHR12R1 DAC channel1 12-bit right-aligned data holding register 0x8 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 0 12 DAC_DHR12L1 DAC_DHR12L1 DAC channel1 12-bit left aligned data holding register 0xC 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 4 12 DAC_DHR8R1 DAC_DHR8R1 DAC channel1 8-bit right aligned data holding register 0x10 0x20 read-write 0x00000000 DACC1DHR DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 0 8 DAC_DHR12R2 DAC_DHR12R2 DAC channel2 12-bit right aligned data holding register 0x14 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 0 12 DAC_DHR12L2 DAC_DHR12L2 DAC channel2 12-bit left aligned data holding register 0x18 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. 4 12 DAC_DHR8R2 DAC_DHR8R2 DAC channel2 8-bit right-aligned data holding register 0x1C 0x20 read-write 0x00000000 DACC2DHR DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. 0 8 DAC_DHR12RD DAC_DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 0 12 DACC2DHR DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 16 12 DAC_DHR12LD DAC_DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 4 12 DACC2DHR DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 20 12 DAC_DHR8RD DAC_DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 0x20 read-write 0x00000000 DACC1DHR DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 0 8 DACC2DHR DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. 8 8 DAC_DOR1 DAC_DOR1 DAC channel1 data output register 0x2C 0x20 read-only 0x00000000 DACC1DOR DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. 0 12 DAC_DOR2 DAC_DOR2 DAC channel2 data output register 0x30 0x20 read-only 0x00000000 DACC2DOR DAC channel2 data output These bits are read-only, they contain data output for DAC channel2. 0 12 DAC_SR DAC_SR DAC status register 0x34 0x20 0x00000000 DMAUDR1 DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 13 1 read-write CAL_FLAG1 DAC Channel 1 calibration offset status This bit is set and cleared by hardware 14 1 read-only BWST1 DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization). 15 1 read-only DMAUDR2 DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 29 1 read-write CAL_FLAG2 DAC Channel 2 calibration offset status This bit is set and cleared by hardware 30 1 read-only BWST2 DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). 31 1 read-only DAC_CCR DAC_CCR DAC calibration control register 0x38 0x20 read-write 0x00000000 OTRIM1 DAC Channel 1 offset trimming value 0 5 OTRIM2 DAC Channel 2 offset trimming value 16 5 DAC_MCR DAC_MCR DAC mode control register 0x3C 0x20 read-write 0x00000000 MODE1 DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample &amp; hold mode 0 3 MODE2 DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample &amp; hold mode 16 3 DAC_SHSR1 DAC_SHSR1 DAC Sample and Hold sample time register 1 0x40 0x20 read-write 0x00000000 TSAMPLE1 DAC Channel 1 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored. 0 10 DAC_SHSR2 DAC_SHSR2 DAC Sample and Hold sample time register 2 0x44 0x20 read-write 0x00000000 TSAMPLE2 DAC Channel 2 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored. 0 10 DAC_SHHR DAC_SHHR DAC Sample and Hold hold time register 0x48 0x20 read-write 0x00010001 THOLD1 DAC Channel 1 hold Time (only valid in sample &amp; hold mode) Hold time= (THOLD[9:0]) x T LSI 0 10 THOLD2 DAC Channel 2 hold time (only valid in sample &amp; hold mode). Hold time= (THOLD[9:0]) x T LSI 16 10 DAC_SHRR DAC_SHRR DAC Sample and Hold refresh time register 0x4C 0x20 read-write 0x00010001 TREFRESH1 DAC Channel 1 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI 0 8 TREFRESH2 DAC Channel 2 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI 16 8 SEC_DAC !(DCB->DSCSR & (1 << 16)) 0x50007400 OPAMP Operational amplifiers OPAMP 0x40007800 0x0 0x400 registers OPAMP1_CSR OPAMP1_CSR OPAMP1 control/status register 0x0 0x20 read-write 0x00000000 OPAEN Operational amplifier Enable 0 1 OPALPM Operational amplifier Low Power Mode 1 1 OPAMODE Operational amplifier PGA mode 2 2 PGA_GAIN Operational amplifier Programmable amplifier gain value 4 2 VM_SEL inverting input selection 8 2 VP_SEL non inverted input selection 10 1 CALON calibration mode enable 12 1 CALSEL calibration selection 13 1 USERTRIM User trimming enable 14 1 CALOUT Operational amplifier calibration output 15 1 OPA_RANGE Operational amplifier power supply range for stability 31 1 OPAMP1_OTR OPAMP1_OTR OPAMP1 offset trimming register in normal mode 0x4 0x20 read-write 0x00000000 TRIMOFFSETN Trim for NMOS differential pairs 0 5 TRIMOFFSETP Trim for PMOS differential pairs 8 5 OPAMP1_LPOTR OPAMP1_LPOTR OPAMP1 offset trimming register in low-powe mode 0x8 0x20 read-write 0x00000000 TRIMLPOFFSETN Trim for NMOS differential pairs 0 5 TRIMLPOFFSETP Trim for PMOS differential pairs 8 5 OPAMP2_CRS OPAMP2_CRS OPAMP2 control/status register 0x10 0x20 read-write 0x00000000 OPAEN Operational amplifier Enable 0 1 OPALPM Operational amplifier Low Power Mode 1 1 OPAMODE Operational amplifier PGA mode 2 2 PGA_GAIN Operational amplifier Programmable amplifier gain value 4 2 VM_SEL inverting input selection 8 2 VP_SEL non inverted input selection 10 1 CALON calibration mode enable 12 1 CALSEL calibration selection 13 1 USERTRIM User trimming enable 14 1 CALOUT Operational amplifier calibration output 15 1 OPAMP2_OTR OPAMP2_OTR OPAMP2 offset trimming register in normal mode 0x14 0x20 read-write 0x00000000 TRIMOFFSETN Trim for NMOS differential pairs 0 5 TRIMOFFSETP Trim for PMOS differential pairs 8 5 OPAMP2_LPOTR OPAMP2_LPOTR OPAMP2 offset trimming register in low-power mode 0x18 0x20 read-write 0x00000000 TRIMLPOFFSETN Trim for NMOS differential pairs 0 5 TRIMLPOFFSETP Trim for PMOS differential pairs 8 5 SEC_OPAMP !(DCB->DSCSR & (1 << 16)) 0x50007800 TIM8 Advanced-timers TIM 0x40013400 0x0 0x400 registers TIM8_BRK TIM8 Break Interrupt 051 TIM8_UP TIM8 Update Interrupt 052 TIM8_TRG_COM TIM8 Trigger and Commutation Interrupt 053 TIM8_CC TIM8 Capture Compare Interrupt 054 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 OIS4 Output Idle state 4 14 1 OIS3N Output Idle state 3 13 1 OIS3 Output Idle state 3 12 1 OIS2N Output Idle state 2 11 1 OIS2 Output Idle state 2 10 1 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 OIS5 Output Idle state 5 (OC5 output) 15 1 OIS6 Output Idle state 6 16 1 MMS2 Master mode selection 2 20 4 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 SMS_bit3 Slave mode selection - bit 3 16 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 COMDE COM DMA request enable 13 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 BIE Break interrupt enable 7 1 COMIE COM interrupt enable 5 1 SR SR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 COMIF COM interrupt flag 5 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 SBIF System Break interrupt flag 13 1 CC5IF Compare 5 interrupt flag 16 1 CC6IF Compare 6 interrupt flag 17 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 BG Break generation 7 1 TG Trigger generation 6 1 COMG Capture/Compare control update generation 5 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 B2G Break 2 generation 8 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2CE Output Compare 2 clear enable 15 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 OC2FE Output Compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 OC1M_bit3 Output Compare 1 mode - bit 3 16 1 OC2M_bit3 Output Compare 2 mode - bit 3 24 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PCS Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 ICPCS Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 OC3M_bit3 Output Compare 3 mode - bit 3 16 1 OC4M_bit3 Output Compare 4 mode - bit 3 24 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CC4NP Capture/Compare 4 complementary output polarity 15 1 CC5E Capture/Compare 5 output enable 16 1 CC5P Capture/Compare 5 output polarity 17 1 CC6E Capture/Compare 6 output enable 20 1 CC6P Capture/Compare 6 output polarity 21 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write UIFCPY UIF copy 31 1 read-only PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2 Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3 Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4 Capture/Compare value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 MOE Main output enable 15 1 AOE Automatic output enable 14 1 BKP Break polarity 13 1 BKE Break enable 12 1 OSSR Off-state selection for Run mode 11 1 OSSI Off-state selection for Idle mode 10 1 LOCK Lock configuration 8 2 DTG Dead-time generator setup 0 8 BKF Break filter 16 4 BK2F Break 2 filter 20 4 BK2E Break 2 enable 24 1 BK2P Break 2 polarity 25 1 BKDSRM Break Disarm 26 1 BK2DSRM Break2 Disarm 27 1 BKBID Break Bidirectional 28 1 BK2BID Break2 bidirectional 29 1 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 32 OR1 OR1 DMA address for full transfer 0x50 0x20 read-write 0x0000 TI1_RMP Input Capture 1 remap 4 1 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x54 0x20 read-write 0x00000000 OC6M_bit3 Output Compare 6 mode bit 3 24 1 OC5M_bit3 Output Compare 5 mode bit 3 16 3 OC6CE Output compare 6 clear enable 15 1 OC6M Output compare 6 mode 12 3 OC6PE Output compare 6 preload enable 11 1 OC6FE Output compare 6 fast enable 10 1 OC5CE Output compare 5 clear enable 7 1 OC5M Output compare 5 mode 4 3 OC5PE Output compare 5 preload enable 3 1 OC5FE Output compare 5 fast enable 2 1 CCR5 CCR5 capture/compare register 4 0x58 0x20 read-write 0x00000000 CCR5 Capture/Compare value 0 16 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 4 0x5C 0x20 read-write 0x00000000 CCR6 Capture/Compare value 0 16 OR2 OR2 DMA address for full transfer 0x60 0x20 read-write 0x00000001 BKINE BRK BKIN input enable 0 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP2E BRK COMP2 enable 2 1 BKDF1BK2E BRK dfsdm1_break[2] enable 8 1 BKINP BRK BKIN input polarity 9 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2P BRK COMP2 input polarity 11 1 ETRSEL ETR source selection 14 3 OR3 OR3 DMA address for full transfer 0x64 0x20 read-write 0x00000001 BK2INE BRK2 BKIN input enable 0 1 BK2CMP1E BRK2 COMP1 enable 1 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2DFBK3E BRK2 DFSDM_BREAK0 enable 8 1 BK2INP BRK2 BKIN input polarity 9 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 SEC_TIM8 !(DCB->DSCSR & (1 << 16)) 0x50013400 GTZC_TZIC GTZC_TZIC GTZC 0x40032800 0x0 0x400 registers IER1 IER1 TZIC interrupt enable register 1 0x0 0x20 read-write 0x00000000 TIM2IE TIM2IE 0 1 TIM3IE TIM3IE 1 1 TIM4IE TIM4IE 2 1 TIM5IE TIM5IE 3 1 TIM6IE TIM6IE 4 1 TIM7IE TIM7IE 5 1 WWDGIE WWDGIE 6 1 IWDGIE IWDGIE 7 1 SPI2IE SPI2IE 8 1 SPI3IE SPI3IE 9 1 USART2IE USART2IE 10 1 USART3IE USART3IE 11 1 UART4IE UART4IE 12 1 UART5IE UART5IE 13 1 I2C1IE I2C1IE 14 1 I2C2IE I2C2IE 15 1 I2C3IE I2C3IE 16 1 CRSIE CRSIE 17 1 DACIE DACIE 18 1 OPAMPIE OPAMPIE 19 1 LPTIM1IE LPTIM1IE 20 1 LPUART1IE LPUART1IE 21 1 I2C4IE I2C4IE 22 1 LPTIM2IE LPTIM2IE 23 1 LPTIM3IE LPTIM3IE 24 1 FDCAN1IE FDCAN1IE 25 1 USBFSIE USBFSIE 26 1 UCPD1IE UCPD1IE 27 1 VREFBUFIE VREFBUFIE 28 1 COMPIE COMPIE 29 1 TIM1IE TIM1IE 30 1 SPI1IE SPI1IE 31 1 IER2 IER2 TZIC interrupt enable register 2 0x4 0x20 read-write 0x00000000 TIM8IE TIM8IE 0 1 USART1IE USART1IE 1 1 TIM15IE TIM15IE 2 1 TIM16IE TIM16IE 3 1 TIM17IE TIM17IE 4 1 SAI1IE SAI1IE 5 1 SAI2IE SAI2IE 6 1 DFSDM1IE DFSDM1IE 7 1 CRCIE CRCIE 8 1 TSCIE TSCIE 9 1 ICACHEIE ICACHEIE 10 1 ADCIE ADCIE 11 1 AESIE AESIE 12 1 HASHIE HASHIE 13 1 RNGIE RNGIE 14 1 PKAIE PKAIE 15 1 SDMMC1IE SDMMC1IE 16 1 FMC_REGIE FMC_REGIE 17 1 OCTOSPI1_REGIE OCTOSPI1_REGIE 18 1 RTCIE RTCIE 19 1 PWRIE PWRIE 20 1 SYSCFGIE SYSCFGIE 21 1 DMA1IE DMA1IE 22 1 DMA2IE DMA2IE 23 1 DMAMUX1IE DMAMUX1IE 24 1 RCCIE RCCIE 25 1 FLASHIE FLASHIE 26 1 FLASH_REGIE FLASH_REGIE 27 1 EXTIIE EXTIIE 28 1 OTFDEC1IE OTFDEC1IE 29 1 IER3 IER3 TZIC interrupt enable register 3 0x8 0x20 read-write 0x00000000 TZSCIE TZSCIE 0 1 TZICIE TZICIE 1 1 MPCWM1IE MPCWM1IE 2 1 MPCWM2IE MPCWM2IE 3 1 MPCBB1IE MPCBB1IE 4 1 MPCBB1_REGIE MPCBB1_REGIE 5 1 MPCBB2IE MPCBB2IE 6 1 MPCBB2_REGIE MPCBB2_REGIE 7 1 SR1 SR1 TZIC interrupt status register 1 0x10 0x20 read-only 0x00000000 TIM2F TIM2F 0 1 TIM3F TIM3F 1 1 TIM4F TIM4F 2 1 TIM5F TIM5F 3 1 TIM6F TIM6F 4 1 TIM7F TIM7F 5 1 WWDGF WWDGF 6 1 IWDGF IWDGF 7 1 SPI2F SPI2F 8 1 SPI3F SPI3F 9 1 USART2F USART2F 10 1 USART3F USART3F 11 1 UART4F UART4F 12 1 UART5F UART5F 13 1 I2C1F I2C1F 14 1 I2C2F I2C2F 15 1 I2C3F I2C3F 16 1 CRSF CRSF 17 1 DACF DACF 18 1 OPAMPF OPAMPF 19 1 LPTIM1F LPTIM1F 20 1 LPUART1F LPUART1F 21 1 I2C4F I2C4F 22 1 LPTIM2F LPTIM2F 23 1 LPTIM3F LPTIM3F 24 1 FDCAN1F FDCAN1F 25 1 USBFSF USBFSF 26 1 UCPD1F UCPD1F 27 1 VREFBUFF VREFBUFF 28 1 COMPF COMPF 29 1 TIM1F TIM1F 30 1 SPI1F SPI1F 31 1 SR2 SR2 TZIC interrupt status register 2 0x14 0x20 read-write 0x00000000 TIM8F TIM8F 0 1 USART1F USART1F 1 1 TIM15F TIM15F 2 1 TIM16F TIM16F 3 1 TIM17F TIM17F 4 1 SAI1F SAI1F 5 1 SAI2F SAI2F 6 1 DFSDM1F DFSDM1F 7 1 CRCF CRCF 8 1 TSCF TSCF 9 1 ICACHEF ICACHEF 10 1 ADCF ADCF 11 1 AESF AESF 12 1 HASHF HASHF 13 1 RNGF RNGF 14 1 PKAF PKAF 15 1 SDMMC1F SDMMC1F 16 1 FMC_REGF FMC_REGF 17 1 OCTOSPI1_REGF OCTOSPI1_REGF 18 1 RTCF RTCF 19 1 PWRF PWRF 20 1 SYSCFGF SYSCFGF 21 1 DMA1F DMA1F 22 1 DMA2F DMA2F 23 1 DMAMUX1F DMAMUX1F 24 1 RCCF RCCF 25 1 FLASHF FLASHF 26 1 FLASH_REGF FLASH_REGF 27 1 EXTIF EXTIF 28 1 OTFDEC1F OTFDEC1F 29 1 SR3 SR3 TZIC interrupt status register 3 0x18 0x20 read-write 0x00000000 TZSCF TZSCF 0 1 TZICF TZICF 1 1 MPCWM1F MPCWM1F 2 1 MPCWM2F MPCWM2F 3 1 MPCBB1F MPCBB1F 4 1 MPCBB1_REGF MPCBB1_REGF 5 1 MPCBB2F MPCBB2F 6 1 MPCBB2_REGF MPCBB2_REGF 7 1 FCR1 FCR1 TZIC interrupt clear register 1 0x20 0x20 write-only 0x00000000 TIM2FC TIM2FC 0 1 TIM3FC TIM3FC 1 1 TIM4FC TIM4FC 2 1 TIM5FC TIM5FC 3 1 TIM6FC TIM6FC 4 1 TIM7FC TIM7FC 5 1 WWDGFC WWDGFC 6 1 IWDGFC IWDGFC 7 1 SPI2FC SPI2FC 8 1 SPI3FC SPI3FC 9 1 USART2FC USART2FC 10 1 USART3FC USART3FC 11 1 UART4FC UART4FC 12 1 UART5FC UART5FC 13 1 I2C1FC I2C1FC 14 1 I2C2FC I2C2FC 15 1 I2C3FC I2C3FC 16 1 CRSFC CRSFC 17 1 DACFC DACFC 18 1 OPAMPFC OPAMPFC 19 1 LPTIM1FC LPTIM1FC 20 1 LPUART1FC LPUART1FC 21 1 I2C4FC I2C4FC 22 1 LPTIM2FC LPTIM2FC 23 1 LPTIM3FC LPTIM3FC 24 1 FDCAN1FC FDCAN1FC 25 1 USBFSFC USBFSFC 26 1 UCPD1FC UCPD1FC 27 1 VREFBUFFC VREFBUFFC 28 1 COMPFC COMPFC 29 1 TIM1FC TIM1FC 30 1 SPI1FC SPI1FC 31 1 FCR2 ICR2 TZIC interrupt clear register 2 0x24 0x20 read-write 0x00000000 TIM8FC TIM8FC 0 1 USART1FC USART1FC 1 1 TIM15FC TIM15FC 2 1 TIM16FC TIM16FC 3 1 TIM17FC TIM17FC 4 1 SAI1FC SAI1FC 5 1 SAI2FC SAI2FC 6 1 DFSDM1FC DFSDM1FC 7 1 CRCFC CRCFC 8 1 TSCFC TSCFC 9 1 ICACHEFC ICACHEFC 10 1 ADCFC ADCFC 11 1 AESFC AESFC 12 1 HASHFC HASHFC 13 1 RNGFC RNGFC 14 1 PKAFC PKAFC 15 1 SDMMC1FC SDMMC1FC 16 1 FMC_REGFC FMC_REGFC 17 1 OCTOSPI1_REGFC OCTOSPI1_REGFC 18 1 RTCFC RTCFC 19 1 PWRFC PWRFC 20 1 SYSCFGFC SYSCFGFC 21 1 DMA1FC DMA1FC 22 1 DMA2FC DMA2FC 23 1 DMAMUX1FC DMAMUX1FC 24 1 RCCFC RCCFC 25 1 FLASHFC FLASHFC 26 1 FLASH_REGFC FLASH_REGFC 27 1 EXTIFC EXTIFC 28 1 OTFDEC1FC OTFDEC1FC 29 1 FCR3 FCR3 TZIC interrupt clear register 3 0x28 0x20 read-write 0x00000000 TZSCFC TZSCFC 0 1 TZICFC TZICFC 1 1 MPCWM1FC MPCWM1FC 2 1 MPCWM2FC MPCWM2FC 3 1 MPCBB1FC MPCBB1FC 4 1 MPCBB1_REGFC MPCBB1_REGFC 5 1 MPCBB2FC MPCBB2FC 6 1 MPCBB2_REGFC MPCBB2_REGFC 7 1 SEC_GTZC_TZIC !(DCB->DSCSR & (1 << 16)) 0x50032800 GTZC_TZSC GTZC_TZSC GTZC 0x40032400 0x0 0x400 registers TZSC_CR TZSC_CR TZSC control register 0x0 0x20 read-write 0x00000000 LCK LCK 0 1 TZSC_SECCFGR1 TZSC_SECCFGR1 TZSC secure configuration register 1 0x10 0x20 read-write 0x00000000 TIM2SEC TIM2SEC 0 1 TIM3SEC TIM3SEC 1 1 TIM4SEC TIM4SEC 2 1 TIM5SEC TIM5SEC 3 1 TIM6SEC TIM6SEC 4 1 TIM7SEC TIM7SEC 5 1 WWDGSEC WWDGSEC 6 1 IWDGSEC IWDGSEC 7 1 SPI2SEC SPI2SEC 8 1 SPI3SEC SPI3SEC 9 1 USART2SEC USART2SEC 10 1 USART3SEC USART3SEC 11 1 UART4SEC UART4SEC 12 1 UART5SEC UART5SEC 13 1 I2C1SEC I2C1SEC 14 1 I2C2SEC I2C2SEC 15 1 I2C3SEC I2C3SEC 16 1 CRSSEC CRSSEC 17 1 DACSEC DACSEC 18 1 OPAMPSEC OPAMPSEC 19 1 LPTIM1SEC LPTIM1SEC 20 1 LPUART1SEC LPUART1SEC 21 1 I2C4SEC I2C4SEC 22 1 LPTIM2SEC LPTIM2SEC 23 1 LPTIM3SEC LPTIM3SEC 24 1 FDCAN1SEC FDCAN1SEC 25 1 USBFSSEC USBFSSEC 26 1 UCPD1SEC UCPD1SEC 27 1 VREFBUFSEC VREFBUFSEC 28 1 COMPSEC COMPSEC 29 1 TIM1SEC TIM1SEC 30 1 SPI1SEC SPI1SEC 31 1 TZSC_SECCFGR2 TZSC_SECCFGR2 TZSC secure configuration register 2 0x14 0x20 read-write 0x00000000 TIM8SEC TIM8SEC 0 1 USART1SEC USART1SEC 1 1 TIM15SEC TIM15SEC 2 1 TIM16SEC TIM16SEC 3 1 TIM17SEC TIM17SEC 4 1 SAI1SEC SAI1SEC 5 1 SAI2SEC SAI2SEC 6 1 DFSDM1SEC DFSDM1SEC 7 1 CRCSEC CRCSEC 8 1 TSCSEC TSCSEC 9 1 ICACHESEC ICACHESEC 10 1 ADCSEC ADCSEC 11 1 AESSEC AESSEC 12 1 HASHSEC HASHSEC 13 1 RNGSEC RNGSEC 14 1 PKASEC PKASEC 15 1 SDMMC1SEC SDMMC1SEC 16 1 FSMC_REGSEC FSMC_REGSEC 17 1 OCTOSPI1_REGSEC OCTOSPI1_REGSEC 18 1 TZSC_PRIVCFGR1 TZSC_PRIVCFGR1 TZSC privilege configuration register 1 0x20 0x20 read-write 0x00000000 TIM2PRIV TIM2PRIV 0 1 TIM3PRIV TIM3PRIV 1 1 TIM4PRIV TIM4PRIV 2 1 TIM5PRIV TIM5PRIV 3 1 TIM6PRIV TIM6PRIV 4 1 TIM7PRIV TIM7PRIV 5 1 WWDGPRIV WWDGPRIV 6 1 IWDGPRIV IWDGPRIV 7 1 SPI2PRIV SPI2PRIV 8 1 SPI3PRIV SPI3PRIV 9 1 USART2PRIV USART2PRIV 10 1 USART3PRIV USART3PRIV 11 1 UART4PRIV UART4PRIV 12 1 UART5PRIV UART5PRIV 13 1 I2C1PRIV I2C1PRIV 14 1 I2C2PRIV I2C2PRIV 15 1 I2C3PRIV I2C3PRIV 16 1 CRSPRIV CRSPRIV 17 1 DACPRIV DACPRIV 18 1 OPAMPPRIV OPAMPPRIV 19 1 LPTIM1PRIV LPTIM1PRIV 20 1 LPUART1PRIV LPUART1PRIV 21 1 I2C4PRIV I2C4PRIV 22 1 LPTIM2PRIV LPTIM2PRIV 23 1 LPTIM3PRIV LPTIM3PRIV 24 1 FDCAN1PRIV FDCAN1PRIV 25 1 USBFSPRIV USBFSPRIV 26 1 UCPD1PRIV UCPD1PRIV 27 1 VREFBUFPRIV VREFBUFPRIV 28 1 COMPPRIV COMPPRIV 29 1 TIM1PRIV TIM1PRIV 30 1 SPI1PRIV SPI1PRIV 31 1 TZSC_PRIVCFGR2 TZSC_PRIVCFGR2 TZSC privilege configuration register 2 0x24 0x20 read-write 0x00000000 TIM8PRIV TIM8PRIV 0 1 USART1PRIV USART1PRIV 1 1 TIM15PRIV TIM15PRIV 2 1 TIM16PRIV TIM16PRIV 3 1 TIM17PRIV TIM17PRIV 4 1 SAI1PRIV SAI1PRIV 5 1 SAI2PRIV SAI2PRIV 6 1 DFSDM1PRIV DFSDM1PRIV 7 1 CRCPRIV CRCPRIV 8 1 TSCPRIV TSCPRIV 9 1 ICACHEPRIV ICACHEPRIV 10 1 ADCPRIV ADCPRIV 11 1 AESPRIV AESPRIV 12 1 HASHPRIV HASHPRIV 13 1 RNGPRIV RNGPRIV 14 1 PKAPRIV PKAPRIV 15 1 SDMMC1PRIV SDMMC1PRIV 16 1 FSMC_REGPRIV FSMC_REGPRIV 17 1 OCTOSPI1_REGPRIV OCTOSPI1_REGRIV 18 1 TZSC_MPCWM1_NSWMR1 TZSC_MPCWM1_NSWMR1 TZSC external memory non-secure watermark register 1 0x30 0x20 read-write 0x00000000 NSWM1STRT NSWM1STRT 0 11 NSWM1LGTH NSWM1LGTH 16 12 TZSC_MPCWM1_NSWMR2 TZSC_MPCWM1_NSWMR2 TZSC external memory non-secure watermark register 1 0x34 0x20 read-write 0x00000000 NSWM2STRT NSWM2STRT 0 11 NSWM2LGTH NSWM2LGTH 16 12 TZSC_MPCWM2_NSWMR1 TZSC_MPCWM2_NSWMR1 TZSC external memory non-secure watermark register 1 0x38 0x20 read-write 0x00000000 NSWM1STRT NSWM1STRT 0 11 NSWM1LGTH NSWM1LGTH 16 12 TZSC_MPCWM3_NSWMR1 TZSC_MPCWM3_NSWMR1 TZSC external memory non-secure watermark register 2 0x40 0x20 read-write 0x00000000 NSWM2STRT NSWM2STRT 0 11 NSWM2LGTH NSWM2LGTH 16 12 TZSC_MPCWM2_NSWMR2 TZSC_MPCWM2_NSWMR2 TZSC external memory non-secure watermark register 2 0x3C 0x20 read-write 0x00000000 NSWM2STRT NSWM2STRT 0 11 NSWM2LGTH NSWM2LGTH 16 12 SEC_GTZC_TZSC !(DCB->DSCSR & (1 << 16)) 0x50032400 WWDG System window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window Watchdog interrupt 000 CR CR Control register 0x0 0x20 read-write 0x0000007F WDGA Activation bit 7 1 T 7-bit counter (MSB to LSB) 0 7 CFR CFR Configuration register 0x4 0x20 read-write 0x0000007F EWI Early wakeup interrupt 9 1 WDGTB Timer base 7 2 W 7-bit window value 0 7 SR SR Status register 0x8 0x20 read-write 0x00000000 EWIF Early wakeup interrupt flag 0 1 SEC_WWDG !(DCB->DSCSR & (1 << 16)) 0x50002C00 SYSCFG System configuration controller SYSCFG 0x40010000 0x0 0x30 registers SECCFGR SECCFGR SYSCFG secure configuration register 0x0 0x20 read-write 0x00000000 SRAM2SEC SRAM2 security 2 1 CLASSBSEC ClassB security 1 1 SYSCFGSEC SYSCFG clock control security 0 1 FPUSEC FPUSEC 3 1 CFGR1 CFGR1 configuration register 1 0x4 0x20 read-write 0x00000000 I2C4_FMP I2C4_FMP 23 1 I2C3_FMP I2C3 Fast-mode Plus driving capability activation 22 1 I2C2_FMP I2C2 Fast-mode Plus driving capability activation 21 1 I2C1_FMP I2C1 Fast-mode Plus driving capability activation 20 1 I2C_PB9_FMP Fast-mode Plus (Fm+) driving capability activation on PB9 19 1 I2C_PB8_FMP Fast-mode Plus (Fm+) driving capability activation on PB8 18 1 I2C_PB7_FMP Fast-mode Plus (Fm+) driving capability activation on PB7 17 1 I2C_PB6_FMP Fast-mode Plus (Fm+) driving capability activation on PB6 16 1 BOOSTEN I/O analog switch voltage booster enable 8 1 ANASWVDD GPIO analog switch control voltage selection 9 1 FPUIMR FPUIMR FPU interrupt mask register 0x8 0x20 read-write 0x0000001F FPU_IE Floating point unit interrupts enable bits 0 6 CNSLCKR CNSLCKR SYSCFG CPU non-secure lock register 0xC 0x20 read-write 0x00000000 LOCKNSVTOR VTOR_NS register lock 0 1 LOCKNSMPU Non-secure MPU registers lock 1 1 CSLOCKR CSLOCKR SYSCFG CPU secure lock register 0x10 0x20 read-write 0x00000000 LOCKSVTAIRCR LOCKSVTAIRCR 0 1 LOCKSMPU LOCKSMPU 1 1 LOCKSAU LOCKSAU 2 1 SCSR SCSR SCSR 0x18 0x20 0x00000000 SRAM2BSY SRAM2 busy by erase operation 1 1 read-only SRAM2ER SRAM2 Erase 0 1 read-write CFGR2 CFGR2 CFGR2 0x14 0x20 0x00000000 SPF SRAM2 parity error flag 8 1 read-write ECCL ECC Lock 3 1 write-only PVDL PVD lock enable bit 2 1 write-only SPL SRAM2 parity lock bit 1 1 write-only CLL LOCKUP (hardfault) output enable bit 0 1 write-only SWPR SWPR SWPR 0x20 0x20 write-only 0x00000000 P31WP SRAM2 page 31 write protection 31 1 P30WP P30WP 30 1 P29WP P29WP 29 1 P28WP P28WP 28 1 P27WP P27WP 27 1 P26WP P26WP 26 1 P25WP P25WP 25 1 P24WP P24WP 24 1 P23WP P23WP 23 1 P22WP P22WP 22 1 P21WP P21WP 21 1 P20WP P20WP 20 1 P19WP P19WP 19 1 P18WP P18WP 18 1 P17WP P17WP 17 1 P16WP P16WP 16 1 P15WP P15WP 15 1 P14WP P14WP 14 1 P13WP P13WP 13 1 P12WP P12WP 12 1 P11WP P11WP 11 1 P10WP P10WP 10 1 P9WP P9WP 9 1 P8WP P8WP 8 1 P7WP P7WP 7 1 P6WP P6WP 6 1 P5WP P5WP 5 1 P4WP P4WP 4 1 P3WP P3WP 3 1 P2WP P2WP 2 1 P1WP P1WP 1 1 P0WP P0WP 0 1 SKR SKR SKR 0x1C 0x20 write-only 0x00000000 KEY SRAM2 write protection key for software erase 0 8 SWPR2 SWPR2 SWPR2 0x24 0x20 write-only 0x00000000 P32WP P32WP 0 1 P33WP P33WP 1 1 P34WP P34WP 2 1 P35WP P35WP 3 1 P36WP P36WP 4 1 P37WP P37WP 5 1 P38WP P38WP 6 1 P39WP P39WP 7 1 P40WP P40WP 8 1 P41WP P41WP 9 1 P42WP P42WP 10 1 P43WP P43WP 11 1 P44WP P44WP 12 1 P45WP P45WP 13 1 P46WP P46WP 14 1 P47WP P47WP 15 1 P48WP P48WP 16 1 P49WP P49WP 17 1 P50WP P50WP 18 1 P51WP P51WP 19 1 P52WP P52WP 20 1 P53WP P53WP 21 1 P54WP P54WP 22 1 P55WP P55WP 23 1 P56WP P56WP 24 1 P57WP P57WP 25 1 P58WP P58WP 26 1 P59WP P59WP 27 1 P60WP P60WP 28 1 P61WP P61WP 29 1 P62WP P62WP 30 1 P63WP P63WP 31 1 RSSCMDR RSSCMDR RSSCMDR 0x2C 0x20 read-write 0x00000000 RSSCMD RSS commands 0 8 SEC_SYSCFG !(DCB->DSCSR & (1 << 16)) 0x50010000 DBGMCU MCU debug component DBGMCU 0xE0044000 0x0 0x400 registers IDCODE IDCODE DBGMCU_IDCODE 0x0 0x20 read-only 0x00000000 DEV_ID Device identifier 0 12 REV_ID Revision identifie 16 16 CR CR Debug MCU configuration register 0x4 0x20 read-write 0x00000000 DBG_STOP Debug Stop mode 1 1 DBG_STANDBY Debug Standby mode 2 1 TRACE_IOEN Trace pin assignment control 4 1 TRACE_MODE Trace pin assignment control 6 2 TRACE_EN trace port and clock enable 5 1 APB1LFZR APB1LFZR Debug MCU APB1 freeze register1 0x8 0x20 read-write 0x00000000 DBG_TIM2_STOP TIM2 counter stopped when core is halted 0 1 DBG_TIM6_STOP TIM6 counter stopped when core is halted 4 1 DBG_TIM7_STOP TIM7 counter stopped when core is halted 5 1 DBG_RTC_STOP RTC counter stopped when core is halted 10 1 DBG_WWDG_STOP Window watchdog counter stopped when core is halted 11 1 DBG_IWDG_STOP Independent watchdog counter stopped when core is halted 12 1 DBG_I2C1_STOP I2C1 SMBUS timeout counter stopped when core is halted 21 1 DBG_I2C2_STOP I2C2 SMBUS timeout counter stopped when core is halted 22 1 DBG_I2C3_STOP I2C3 SMBUS timeout counter stopped when core is halted 23 1 DBG_LPTIM1_STOP LPTIM1 counter stopped when core is halted 31 1 DBG_TIM3_STOP TIM3 stop in debug 1 1 DBG_TIM4_STOP TIM4 stop in debug 2 1 DBG_TIM5_STOP TIM5 stop in debug 3 1 APB1HFZR APB1HFZR Debug MCU APB1 freeze register 2 0xC 0x20 read-write 0x00000000 DBG_LPTIM2_STOP LPTIM2 counter stopped when core is halted 5 1 DBG_I2C4_STOP I2C4 stop in debug 1 1 DBG_LPTIM3_STOP LPTIM3 stop in debug 6 1 APB2FZR APB2FZR Debug MCU APB2 freeze register 0x10 0x20 read-write 0x00000000 DBG_TIM1_STOP TIM1 counter stopped when core is halted 11 1 DBG_TIM15_STOP TIM15 counter stopped when core is halted 16 1 DBG_TIM16_STOP TIM16 counter stopped when core is halted 17 1 DBG_TIM8_STOP TIM8 stop in debug 13 1 DBG_TIM17_STOP DBG_TIM17_STOP 18 1 USB Universal serial bus full-speed device interface USB 0x4000D400 0x0 0x800 registers USB_FS USB FS global interrupt 073 EP0R EP0R endpoint 0 register 0x0 0x10 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP1R EP1R endpoint 1 register 0x4 0x10 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP2R EP2R endpoint 2 register 0x8 0x10 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP3R EP3R endpoint 3 register 0xC 0x10 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP4R EP4R endpoint 4 register 0x10 0x10 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP5R EP5R endpoint 5 register 0x14 0x10 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP6R EP6R endpoint 6 register 0x18 0x10 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP7R EP7R endpoint 7 register 0x1C 0x10 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 CNTR CNTR control register 0x40 0x10 read-write 0x00000003 FRES Force USB Reset 0 1 PDWN Power down 1 1 LPMODE Low-power mode 2 1 FSUSP Force suspend 3 1 RESUME Resume request 4 1 L1RESUME LPM L1 Resume request 5 1 L1REQM LPM L1 state request interrupt mask 7 1 ESOFM Expected start of frame interrupt mask 8 1 SOFM Start of frame interrupt mask 9 1 RESETM USB reset interrupt mask 10 1 SUSPM Suspend mode interrupt mask 11 1 WKUPM Wakeup interrupt mask 12 1 ERRM Error interrupt mask 13 1 PMAOVRM Packet memory area over / underrun interrupt mask 14 1 CTRM Correct transfer interrupt mask 15 1 ISTR ISTR interrupt status register 0x44 0x10 0x00000000 EP_ID Endpoint Identifier 0 4 read-only DIR Direction of transaction 4 1 read-only L1REQ LPM L1 state request 7 1 read-write ESOF Expected start frame 8 1 read-write SOF start of frame 9 1 read-write RESET reset request 10 1 read-write SUSP Suspend mode request 11 1 read-write WKUP Wakeup 12 1 read-write ERR Error 13 1 read-write PMAOVR Packet memory area over / underrun 14 1 read-write CTR Correct transfer 15 1 read-only FNR FNR frame number register 0x48 0x10 read-only 0x0000 FN Frame number 0 11 LSOF Lost SOF 11 2 LCK Locked 13 1 RXDM Receive data - line status 14 1 RXDP Receive data + line status 15 1 DADDR DADDR device address 0x4C 0x10 read-write 0x0000 ADD Device address 0 7 EF Enable function 7 1 BTABLE BTABLE Buffer table address 0x50 0x10 read-write 0x0000 BTABLE Buffer table 3 13 LPMCSR LPMCSR LPM control and status register 0x54 0x10 read-write 0x0000 LPMEN LPM support enable 0 1 LPMACK LPM Token acknowledge enable 1 1 REMWAKE RemoteWake value 3 1 BESL BESL value 4 4 BCDR BCDR Battery charging detector 0x58 0x10 read-write 0x0000 BCDEN Battery charging detector (BCD) enable 0 1 DCDEN Data contact detection (DCD) mode enable 1 1 PDEN Primary detection (PD) mode enable 2 1 SDEN Secondary detection (SD) mode enable 3 1 DCDET Data contact detection (DCD) status 4 1 PDET Primary detection (PD) status 5 1 SDET Secondary detection (SD) status 6 1 PS2DET DM pull-up detection status 7 1 DPPU DP pull-up control 15 1 COUNT0_TX COUNT0_TX Transmission byte count 0 0x52 0x10 read-write 0x0000 COUNT0_TX Transmission byte count 0 10 COUNT1_TX COUNT1_TX Transmission byte count 0 0x5A 0x10 read-write 0x0000 COUNT1_TX Transmission byte count 0 10 COUNT2_TX COUNT2_TX Transmission byte count 0 0x62 0x10 read-write 0x0000 COUNT2_TX Transmission byte count 0 10 COUNT3_TX COUNT3_TX Transmission byte count 0 0x6A 0x10 read-write 0x0000 COUNT3_TX Transmission byte count 0 10 COUNT4_TX COUNT4_TX Transmission byte count 0 0x72 0x10 read-write 0x0000 COUNT4_TX Transmission byte count 0 10 COUNT5_TX COUNT5_TX Transmission byte count 0 0x7A 0x10 read-write 0x0000 COUNT5_TX Transmission byte count 0 10 COUNT6_TX COUNT6_TX Transmission byte count 0 0x82 0x10 read-write 0x0000 COUNT6_TX Transmission byte count 0 10 COUNT7_TX COUNT7_TX Transmission byte count 0 0x8A 0x10 read-write 0x0000 COUNT7_TX Transmission byte count 0 10 ADDR0_RX ADDR0_RX Reception buffer address 0 0x5C 0x10 read-write 0x0000 ADDR0_RX Reception buffer address 1 15 ADDR1_RX ADDR1_RX Reception buffer address 0 0x64 0x10 read-write 0x0000 ADDR1_RX Reception buffer address 1 15 ADDR2_RX ADDR2_RX Reception buffer address 0 0x6C 0x10 read-write 0x0000 ADDR2_RX Reception buffer address 1 15 ADDR3_RX ADDR3_RX Reception buffer address 0 0x74 0x10 read-write 0x0000 ADDR3_RX Reception buffer address 1 15 ADDR4_RX ADDR4_RX Reception buffer address 0 0x7C 0x10 read-write 0x0000 ADDR4_RX Reception buffer address 1 15 ADDR5_RX ADDR5_RX Reception buffer address 0 0x84 0x10 read-write 0x0000 ADDR5_RX Reception buffer address 1 15 ADDR6_RX ADDR6_RX Reception buffer address 0 0x8C 0x10 read-write 0x0000 ADDR6_RX Reception buffer address 1 15 ADDR7_RX ADDR7_RX Reception buffer address 0 0x94 0x10 read-write 0x0000 ADDR7_RX Reception buffer address 1 15 COUNT0_RX COUNT0_RX Reception byte count 0 0x56 0x10 0x0000 COUNT0_RX Reception byte count 0 10 read-only NUM_BLOCK Number of blocks 10 5 read-write BL_SIZE Block size 15 1 read-write COUNT1_RX COUNT1_RX Reception byte count 0 0x5E 0x10 0x0000 COUNT1_RX Reception byte count 0 10 read-only NUM_BLOCK Number of blocks 10 5 read-write BL_SIZE Block size 15 1 read-write COUNT2_RX COUNT2_RX Reception byte count 0 0x66 0x10 0x0000 COUNT2_RX Reception byte count 0 10 read-only NUM_BLOCK Number of blocks 10 5 read-write BL_SIZE Block size 15 1 read-write COUNT3_RX COUNT3_RX Reception byte count 0 0x6E 0x10 0x0000 COUNT3_RX Reception byte count 0 10 read-only NUM_BLOCK Number of blocks 10 5 read-write BL_SIZE Block size 15 1 read-write COUNT4_RX COUNT4_RX Reception byte count 0 0x76 0x10 0x0000 COUNT4_RX Reception byte count 0 10 read-only NUM_BLOCK Number of blocks 10 5 read-write BL_SIZE Block size 15 1 read-write COUNT5_RX COUNT5_RX Reception byte count 0 0x7E 0x10 0x0000 COUNT5_RX Reception byte count 0 10 read-only NUM_BLOCK Number of blocks 10 5 read-write BL_SIZE Block size 15 1 read-write COUNT6_RX COUNT6_RX Reception byte count 0 0x86 0x10 0x0000 COUNT6_RX Reception byte count 0 10 read-only NUM_BLOCK Number of blocks 10 5 read-write BL_SIZE Block size 15 1 read-write COUNT7_RX COUNT7_RX Reception byte count 0 0x8E 0x10 0x0000 COUNT7_RX Reception byte count 0 10 read-only NUM_BLOCK Number of blocks 10 5 read-write BL_SIZE Block size 15 1 read-write SEC_USB !(DCB->DSCSR & (1 << 16)) 0x5000D400 OCTOSPI1 OctoSPI OctoSPI 0x44021000 0x0 0x400 registers OCTOSPI1 OCTOSPI1 global interrupt 076 CR CR control register 0x0 0x20 read-write 0x00000000 FMODE Functional mode 28 2 PMM Polling match mode 23 1 APMS Automatic poll mode stop 22 1 TOIE TimeOut interrupt enable 20 1 SMIE Status match interrupt enable 19 1 FTIE FIFO threshold interrupt enable 18 1 TCIE Transfer complete interrupt enable 17 1 TEIE Transfer error interrupt enable 16 1 FTHRES IFO threshold level 8 5 FSEL FLASH memory selection 7 1 DQM Dual-quad mode 6 1 TCEN Timeout counter enable 3 1 DMAEN DMA enable 2 1 ABORT Abort request 1 1 EN Enable 0 1 DCR1 DCR1 device configuration register 0x8 0x20 read-write 0x00000000 CKMODE Mode 0 / mode 3 0 1 FRCK Free running clock 1 1 CSHT Chip-select high time 8 3 DEVSIZE Device size 16 5 MTYP Memory type 24 2 DCR2 DCR2 device configuration register 2 0xC 0x20 read-write 0x00000000 PRESCALER Clock prescaler 0 8 WRAPSIZE Wrap size 16 3 DCR3 DCR3 device configuration register 3 0x10 0x20 read-write 0x00000000 CSBOUND CS boundary 16 5 DCR4 DCR4 DCR4 0x14 0x20 read-write 0x00000000 TEF Transfer error flag 0 1 TCF Transfer complete flag 1 1 FTF FIFO threshold flag 2 1 SMF Status match flag 3 1 TOF Timeout flag 4 1 BUSY BUSY 5 1 FLEVEL FIFO level 8 6 SR SR status register 0x20 0x20 write-only 0x00000000 CTEF Clear transfer error flag 0 1 CTCF Clear transfer complete flag 1 1 CSMF Clear status match flag 3 1 CTOF Clear timeout flag 4 1 FCR FCR flag clear register 0x24 0x20 read-write 0x00000000 DL Data length 0 32 DLR DLR data length register 0x40 0x20 read-write 0x00000000 ADDRESS ADDRESS 0 32 AR AR address register 0x48 0x20 read-write 0x00000000 DATA Data 0 32 DR DR data register 0x50 0x20 read-write 0x00000000 MASK Status mask 0 32 PSMKR PSMKR polling status mask register 0x80 0x20 read-write 0x00000000 MATCH Status match 0 32 PSMAR PSMAR polling status match register 0x88 0x20 read-write 0x00000000 INTERVAL Polling interval 0 16 PIR PIR polling interval register 0x90 0x20 read-write 0x00000000 IMODE Instruction mode 0 3 IDTR Instruction double transfer rate 3 1 ISIZE Instruction size 4 2 ADMODE Address mode 8 3 ADDTR Address double transfer rate 11 1 ADSIZE Address size 12 2 ABMODE Alternate byte mode 16 3 ABDTR Alternate bytes double transfer rate 19 1 ABSIZE Alternate bytes size 20 2 DMODE Data mode 24 3 DDTR Alternate bytes double transfer rate 27 1 DQSE DQS enable 29 1 SIOO Send instruction only once mode 31 1 CCR CCR communication configuration register 0x100 0x20 read-write 0x00000000 DCYC Number of dummy cycles 0 5 DHQC Delay hold quarter cycle 28 1 SSHIFT Sample shift 30 1 TCR TCR timing configuration register 0x108 0x20 read-write 0x00000000 INSTRUCTION INSTRUCTION 0 32 IR IR instruction register 0x110 0x20 read-write 0x00000000 ALTERNATE Alternate bytes 0 32 ABR ABR alternate bytes register 0x120 0x20 read-write 0x00000000 TIMEOUT Timeout period 0 16 LPTR LPTR low-power timeout register 0x130 0x20 read-write 0x00000000 IMODE Instruction mode 0 3 IDTR Instruction double transfer rate 3 1 ISIZE Instruction size 4 2 ADMODE Address mode 8 3 ADDTR Address double transfer rate 11 1 ADSIZE Address size 12 2 ABMODE Alternate byte mode 16 3 ABDTR Alternate bytes double transfer rate 19 1 ABSIZE Alternate bytes size 20 2 DMODE Data mode 24 3 DDTR alternate bytes double transfer rate 27 1 DQSE DQS enable 29 1 WPCCR WPCCR write communication configuration register 0x140 0x20 read-write 0x00000000 DCYC Number of dummy cycles 0 5 DHQC Delay hold quarter cycle 28 1 SSHIFT Sample shift 30 1 WPTCR WPTCR write timing configuration register 0x148 0x20 read-write 0x00000000 INSTRUCTION INSTRUCTION 0 32 WPIR WPIR write instruction register 0x150 0x20 read-write 0x00000000 ALTERNATE Alternate bytes 0 32 WPABR WPABR write alternate bytes register 0x160 0x20 read-write 0x00000000 LM Latency mode 0 1 WZL Write zero latency 1 1 TACC Access time 8 8 TRWR Read write recovery time 16 8 WCCR WCCR WCCR 0x180 0x20 read-write 0x00000000 REFRESH REFRESH 0 16 WTCR WTCR WTCR 0x188 0x20 read-write 0x00000000 IMODE IMODE 0 3 IDTR IDTR 3 1 ISIZE ISIZE 4 2 ADMODE ADMODE 8 3 ADDTR ADDTR 11 1 ADSIZE ADSIZE 12 2 ABMODE ABMODE 16 3 ABDTR ABDTR 19 1 ABSIZE ABSIZE 20 2 DMODE DMODE 24 3 DDTR DDTR 27 1 DQSE DQSE 29 1 WIR WIR WIR 0x190 0x20 read-write 0x00000000 DCYC DCYC 0 5 WABR WABR WABR 0x1A0 0x20 read-write 0x00000000 INSTRUCTION INSTRUCTION 0 32 HLCR HLCR HyperBusTM latency configuration register 0x200 0x20 read-write 0x00000000 ALTERNATE Alternate bytes 0 32 SEC_OCTOSPI1 !(DCB->DSCSR & (1 << 16)) 0x54021000 LPUART1 Universal synchronous asynchronous receiver transmitter USART 0x40008000 0x0 0x400 registers LPUART1 LPUART1 global interrupt 066 CR1 CR1 Control register 1 0x0 0x20 read-write 0x0000 M1 Word length 28 1 DEAT DEAT 21 5 DEDT DEDT 16 5 CMIE Character match interrupt enable 14 1 MME Mute mode enable 13 1 M0 Word length 12 1 WAKE Receiver wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXEIE interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXNEIE RXNE interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 UESM USART enable in Stop mode 1 1 UE USART enable 0 1 FIFOEN FIFOEN 29 1 TXFEIE TXFEIE 30 1 RXFFIE RXFFIE 31 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x0000 ADD4_7 Address of the USART node 28 4 ADD0_3 Address of the USART node 24 4 MSBFIRST Most significant bit first 19 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 RXINV RX pin active level inversion 16 1 SWAP Swap TX/RX pins 15 1 STOP STOP bits 12 2 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x0000 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 DEP Driver enable polarity selection 15 1 DEM Driver enable mode 14 1 DDRE DMA Disable on Reception Error 13 1 OVRDIS Overrun Disable 12 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 HDSEL Half-duplex selection 3 1 EIE Error interrupt enable 0 1 TXFTIE TXFTIE 23 1 RXFTCFG RXFTCFG 25 3 RXFTIE RXFTIE 28 1 TXFTCFG TXFTCFG 29 3 BRR BRR Baud rate register 0xC 0x20 read-write 0x0000 BRR BRR 0 20 RQR RQR Request register 0x18 0x20 write-only 0x0000 RXFRQ Receive data flush request 3 1 MMRQ Mute mode request 2 1 SBKRQ Send break request 1 1 TXFRQ TXFRQ 4 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x00C0 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 SBKF SBKF 18 1 CMF CMF 17 1 BUSY BUSY 16 1 CTS CTS 10 1 CTSIF CTSIF 9 1 TXE TXE 7 1 TC TC 6 1 RXNE RXNE 5 1 IDLE IDLE 4 1 ORE ORE 3 1 NF NF 2 1 FE FE 1 1 PE PE 0 1 TXFE TXFE 23 1 RXFF RXFF 24 1 RXFT RXFT 26 1 TXFT TXFT 27 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x0000 WUCF Wakeup from Stop mode clear flag 20 1 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 TCCF Transmission complete clear flag 6 1 IDLECF Idle line detected clear flag 4 1 ORECF Overrun error clear flag 3 1 NCF Noise detected clear flag 2 1 FECF Framing error clear flag 1 1 PECF Parity error clear flag 0 1 RDR RDR Receive data register 0x24 0x20 read-only 0x0000 RDR Receive data value 0 9 TDR TDR Transmit data register 0x28 0x20 read-write 0x0000 TDR Transmit data value 0 9 PRESC PRESC PRESC 0x2C 0x20 read-write 0x0000 PRESCALER PRESCALER 0 4 SEC_LPUART1 !(DCB->DSCSR & (1 << 16)) 0x50008000 COMP Comparator COMP 0x40010200 0x0 0x200 registers COMP COMP1 and COMP2 interrupts 072 COMP1_CSR COMP1_CSR Comparator 1 control and status register 0x0 0x20 0x0 COMP1_EN Comparator 1 enable bit 0 1 read-write COMP1_PWRMODE Power Mode of the comparator 1 2 2 read-write COMP1_INMSEL Comparator 1 Input Minus connection configuration bit 4 3 read-write COMP1_INPSEL Comparator1 input plus selection bit 7 1 read-write COMP1_POLARITY Comparator 1 polarity selection bit 15 1 read-write COMP1_HYST Comparator 1 hysteresis selection bits 16 2 read-write COMP1_BLANKING Comparator 1 blanking source selection bits 18 3 read-write COMP1_BRGEN Scaler bridge enable 22 1 read-write COMP1_SCALEN Voltage scaler enable bit 23 1 read-write COMP1_VALUE Comparator 1 output status bit 30 1 read-only COMP1_LOCK COMP1_CSR register lock bit 31 1 write-only COMP2_CSR COMP2_CSR Comparator 2 control and status register 0x4 0x20 0x0 COMP2_EN Comparator 2 enable bit 0 1 read-write COMP2_PWRMODE Power Mode of the comparator 2 2 2 read-write COMP2_INMSEL Comparator 2 Input Minus connection configuration bit 4 3 read-write COMP2_INPSEL Comparator 2 Input Plus connection configuration bit 7 1 read-write COMP2_WINMODE Windows mode selection bit 9 1 read-write COMP2_POLARITY Comparator 2 polarity selection bit 15 1 read-write COMP2_HYST Comparator 2 hysteresis selection bits 16 2 read-write COMP2_BLANKING Comparator 2 blanking source selection bits 18 3 read-write COMP2_BRGEN Scaler bridge enable 22 1 read-write COMP2_SCALEN Voltage scaler enable bit 23 1 read-write COMP2_VALUE Comparator 2 output status bit 30 1 read-only COMP2_LOCK COMP2_CSR register lock bit 31 1 write-only SEC_COMP !(DCB->DSCSR & (1 << 16)) 0x50010200 VREFBUF Voltage reference buffer VREF 0x40010030 0x0 0x1D0 registers CSR CSR VREF control and status register 0x0 0x20 0x00000002 ENVR Voltage reference buffer enable 0 1 read-write HIZ High impedance mode 1 1 read-write VRS Voltage reference scale 2 1 read-write VRR Voltage reference buffer ready 3 1 read-only CCR CCR calibration control register 0x4 0x20 read-write 0x00000000 TRIM Trimming code 0 6 SEC_VREFBUF !(DCB->DSCSR & (1 << 16)) 0x50010030 TSC Touch sensing controller TSC 0x40024000 0x0 0x400 registers TSC TSC global interrupt 092 CR CR control register 0x0 0x20 read-write 0x00000000 CTPH Charge transfer pulse high 28 4 CTPL Charge transfer pulse low 24 4 SSD Spread spectrum deviation 17 7 SSE Spread spectrum enable 16 1 SSPSC Spread spectrum prescaler 15 1 PGPSC pulse generator prescaler 12 3 MCV Max count value 5 3 IODEF I/O Default mode 4 1 SYNCPOL Synchronization pin polarity 3 1 AM Acquisition mode 2 1 START Start a new acquisition 1 1 TSCE Touch sensing controller enable 0 1 IER IER interrupt enable register 0x4 0x20 read-write 0x00000000 MCEIE Max count error interrupt enable 1 1 EOAIE End of acquisition interrupt enable 0 1 ICR ICR interrupt clear register 0x8 0x20 read-write 0x00000000 MCEIC Max count error interrupt clear 1 1 EOAIC End of acquisition interrupt clear 0 1 ISR ISR interrupt status register 0xC 0x20 read-write 0x00000000 MCEF Max count error flag 1 1 EOAF End of acquisition flag 0 1 IOHCR IOHCR I/O hysteresis control register 0x10 0x20 read-write 0xFFFFFFFF G8_IO4 G8_IO4 31 1 G8_IO3 G8_IO3 30 1 G8_IO2 G8_IO2 29 1 G8_IO1 G8_IO1 28 1 G7_IO4 G7_IO4 27 1 G7_IO3 G7_IO3 26 1 G7_IO2 G7_IO2 25 1 G7_IO1 G7_IO1 24 1 G6_IO4 G6_IO4 23 1 G6_IO3 G6_IO3 22 1 G6_IO2 G6_IO2 21 1 G6_IO1 G6_IO1 20 1 G5_IO4 G5_IO4 19 1 G5_IO3 G5_IO3 18 1 G5_IO2 G5_IO2 17 1 G5_IO1 G5_IO1 16 1 G4_IO4 G4_IO4 15 1 G4_IO3 G4_IO3 14 1 G4_IO2 G4_IO2 13 1 G4_IO1 G4_IO1 12 1 G3_IO4 G3_IO4 11 1 G3_IO3 G3_IO3 10 1 G3_IO2 G3_IO2 9 1 G3_IO1 G3_IO1 8 1 G2_IO4 G2_IO4 7 1 G2_IO3 G2_IO3 6 1 G2_IO2 G2_IO2 5 1 G2_IO1 G2_IO1 4 1 G1_IO4 G1_IO4 3 1 G1_IO3 G1_IO3 2 1 G1_IO2 G1_IO2 1 1 G1_IO1 G1_IO1 0 1 IOASCR IOASCR I/O analog switch control register 0x18 0x20 read-write 0x00000000 G8_IO4 G8_IO4 31 1 G8_IO3 G8_IO3 30 1 G8_IO2 G8_IO2 29 1 G8_IO1 G8_IO1 28 1 G7_IO4 G7_IO4 27 1 G7_IO3 G7_IO3 26 1 G7_IO2 G7_IO2 25 1 G7_IO1 G7_IO1 24 1 G6_IO4 G6_IO4 23 1 G6_IO3 G6_IO3 22 1 G6_IO2 G6_IO2 21 1 G6_IO1 G6_IO1 20 1 G5_IO4 G5_IO4 19 1 G5_IO3 G5_IO3 18 1 G5_IO2 G5_IO2 17 1 G5_IO1 G5_IO1 16 1 G4_IO4 G4_IO4 15 1 G4_IO3 G4_IO3 14 1 G4_IO2 G4_IO2 13 1 G4_IO1 G4_IO1 12 1 G3_IO4 G3_IO4 11 1 G3_IO3 G3_IO3 10 1 G3_IO2 G3_IO2 9 1 G3_IO1 G3_IO1 8 1 G2_IO4 G2_IO4 7 1 G2_IO3 G2_IO3 6 1 G2_IO2 G2_IO2 5 1 G2_IO1 G2_IO1 4 1 G1_IO4 G1_IO4 3 1 G1_IO3 G1_IO3 2 1 G1_IO2 G1_IO2 1 1 G1_IO1 G1_IO1 0 1 IOSCR IOSCR I/O sampling control register 0x20 0x20 read-write 0x00000000 G8_IO4 G8_IO4 31 1 G8_IO3 G8_IO3 30 1 G8_IO2 G8_IO2 29 1 G8_IO1 G8_IO1 28 1 G7_IO4 G7_IO4 27 1 G7_IO3 G7_IO3 26 1 G7_IO2 G7_IO2 25 1 G7_IO1 G7_IO1 24 1 G6_IO4 G6_IO4 23 1 G6_IO3 G6_IO3 22 1 G6_IO2 G6_IO2 21 1 G6_IO1 G6_IO1 20 1 G5_IO4 G5_IO4 19 1 G5_IO3 G5_IO3 18 1 G5_IO2 G5_IO2 17 1 G5_IO1 G5_IO1 16 1 G4_IO4 G4_IO4 15 1 G4_IO3 G4_IO3 14 1 G4_IO2 G4_IO2 13 1 G4_IO1 G4_IO1 12 1 G3_IO4 G3_IO4 11 1 G3_IO3 G3_IO3 10 1 G3_IO2 G3_IO2 9 1 G3_IO1 G3_IO1 8 1 G2_IO4 G2_IO4 7 1 G2_IO3 G2_IO3 6 1 G2_IO2 G2_IO2 5 1 G2_IO1 G2_IO1 4 1 G1_IO4 G1_IO4 3 1 G1_IO3 G1_IO3 2 1 G1_IO2 G1_IO2 1 1 G1_IO1 G1_IO1 0 1 IOCCR IOCCR I/O channel control register 0x28 0x20 read-write 0x00000000 G8_IO4 G8_IO4 31 1 G8_IO3 G8_IO3 30 1 G8_IO2 G8_IO2 29 1 G8_IO1 G8_IO1 28 1 G7_IO4 G7_IO4 27 1 G7_IO3 G7_IO3 26 1 G7_IO2 G7_IO2 25 1 G7_IO1 G7_IO1 24 1 G6_IO4 G6_IO4 23 1 G6_IO3 G6_IO3 22 1 G6_IO2 G6_IO2 21 1 G6_IO1 G6_IO1 20 1 G5_IO4 G5_IO4 19 1 G5_IO3 G5_IO3 18 1 G5_IO2 G5_IO2 17 1 G5_IO1 G5_IO1 16 1 G4_IO4 G4_IO4 15 1 G4_IO3 G4_IO3 14 1 G4_IO2 G4_IO2 13 1 G4_IO1 G4_IO1 12 1 G3_IO4 G3_IO4 11 1 G3_IO3 G3_IO3 10 1 G3_IO2 G3_IO2 9 1 G3_IO1 G3_IO1 8 1 G2_IO4 G2_IO4 7 1 G2_IO3 G2_IO3 6 1 G2_IO2 G2_IO2 5 1 G2_IO1 G2_IO1 4 1 G1_IO4 G1_IO4 3 1 G1_IO3 G1_IO3 2 1 G1_IO2 G1_IO2 1 1 G1_IO1 G1_IO1 0 1 IOGCSR IOGCSR I/O group control status register 0x30 0x20 0x00000000 G8S Analog I/O group x status 23 1 read-only G7S Analog I/O group x status 22 1 read-only G6S Analog I/O group x status 21 1 read-only G5S Analog I/O group x status 20 1 read-only G4S Analog I/O group x status 19 1 read-only G3S Analog I/O group x status 18 1 read-only G2S Analog I/O group x status 17 1 read-only G1S Analog I/O group x status 16 1 read-only G8E Analog I/O group x enable 7 1 read-write G7E Analog I/O group x enable 6 1 read-write G6E Analog I/O group x enable 5 1 read-write G5E Analog I/O group x enable 4 1 read-write G4E Analog I/O group x enable 3 1 read-write G3E Analog I/O group x enable 2 1 read-write G2E Analog I/O group x enable 1 1 read-write G1E Analog I/O group x enable 0 1 read-write IOG1CR IOG1CR I/O group x counter register 0x34 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG2CR IOG2CR I/O group x counter register 0x38 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG3CR IOG3CR I/O group x counter register 0x3C 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG4CR IOG4CR I/O group x counter register 0x40 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG5CR IOG5CR I/O group x counter register 0x44 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG6CR IOG6CR I/O group x counter register 0x48 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG7CR IOG7CR I/O group x counter register 0x4C 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG8CR IOG8CR I/O group x counter register 0x50 0x20 read-only 0x00000000 CNT Counter value 0 14 SEC_TSC !(DCB->DSCSR & (1 << 16)) 0x50024000 UCPD1 USB Power Delivery interface UCPD 0x4000DC00 0x0 0x400 registers UCPD1 UCPD global interrupt 106 CFG1 CFG1 UCPD configuration register 0x0 0x20 read-write 0x00000000 HBITCLKDIV HBITCLKDIV 0 6 IFRGAP IFRGAP 6 5 TRANSWIN TRANSWIN 11 5 PSC_USBPDCLK PSC_USBPDCLK 17 3 RXORDSETEN RXORDSETEN 20 9 TXDMAEN TXDMAEN 29 1 RXDMAEN RXDMAEN: 30 1 UCPDEN UCPDEN 31 1 CFG2 CFG2 UCPD configuration register 2 0x4 0x20 read-write 0x00000000 RXFILTDIS RXFILTDIS 0 1 RXFILT2N3 RXFILT2N3 1 1 FORCECLK FORCECLK 2 1 WUPEN WUPEN 3 1 CFG3 CFG3 UCPD configuration register 3 0x8 0x20 read-write 0x00000000 TRIM1_NG_CCRPD TRIM1_NG_CCRPD 0 4 TRIM1_NG_CC1A5 TRIM1_NG_CC1A5 4 5 TRIM1_NG_CC3A0 TRIM1_NG_CC3A0 9 4 TRIM2_NG_CCRPD TRIM2_NG_CCRPD 16 4 TRIM2_NG_CC1A5 TRIM2_NG_CC1A5 20 5 TRIM2_NG_CC3A0 TRIM2_NG_CC3A0 25 4 CR CR UCPD control register 0xC 0x20 read-write 0x00000000 TXMODE TXMODE 0 2 TXSEND TXSEND 2 1 TXHRST TXHRST 3 1 RXMODE RXMODE 4 1 PHYRXEN PHYRXEN 5 1 PHYCCSEL PHYCCSEL 6 1 ANASUBMODE ANASUBMODE 7 2 ANAMODE ANAMODE 9 1 CCENABLE CCENABLE 10 2 FRSRXEN FRSRXEN 16 1 FRSTX FRSTX 17 1 RDCH RDCH 18 1 CC1TCDIS CC1TCDIS 20 1 CC2TCDIS CC2TCDIS 21 1 IMR IMR UCPD Interrupt Mask Register 0x10 0x20 read-write 0x00000000 TXISIE TXISIE 0 1 TXMSGDISCIE TXMSGDISCIE 1 1 TXMSGSENTIE TXMSGSENTIE 2 1 TXMSGABTIE TXMSGABTIE 3 1 HRSTDISCIE HRSTDISCIE 4 1 HRSTSENTIE HRSTSENTIE 5 1 TXUNDIE TXUNDIE 6 1 RXNEIE RXNEIE 8 1 RXORDDETIE RXORDDETIE 9 1 RXHRSTDETIE RXHRSTDETIE 10 1 RXOVRIE RXOVRIE 11 1 RXMSGENDIE RXMSGENDIE 12 1 TYPECEVT1IE TYPECEVT1IE 14 1 TYPECEVT2IE TYPECEVT2IE 15 1 FRSEVTIE FRSEVTIE 20 1 SR SR UCPD Status Register 0x14 0x20 read-only 0x00000000 TXIS TXIS 0 1 TXMSGDISC TXMSGDISC 1 1 TXMSGSENT TXMSGSENT 2 1 TXMSGABT TXMSGABT 3 1 HRSTDISC HRSTDISC 4 1 HRSTSENT HRSTSENT 5 1 TXUND TXUND 6 1 RXNE RXNE 8 1 RXORDDET RXORDDET 9 1 RXHRSTDET RXHRSTDET 10 1 RXOVR RXOVR 11 1 RXMSGEND RXMSGEND 12 1 RXERR RXERR 13 1 TYPECEVT1 TYPECEVT1 14 1 TYPECEVT2 TYPECEVT2 15 1 TYPEC_VSTATE_CC1 TYPEC_VSTATE_CC1 16 2 TYPEC_VSTATE_CC2 TYPEC_VSTATE_CC2 18 2 FRSEVT FRSEVT 20 1 ICR ICR UCPD Interrupt Clear Register 0x18 0x20 read-write 0x00000000 TXMSGDISCCF TXMSGDISCCF 1 1 TXMSGSENTCF TXMSGSENTCF 2 1 TXMSGABTCF TXMSGABTCF 3 1 HRSTDISCCF HRSTDISCCF 4 1 HRSTSENTCF HRSTSENTCF 5 1 TXUNDCF TXUNDCF 6 1 RXORDDETCF RXORDDETCF 9 1 RXHRSTDETCF RXHRSTDETCF 10 1 RXOVRCF RXOVRCF 11 1 RXMSGENDCF RXMSGENDCF 12 1 TYPECEVT1CF TYPECEVT1CF 14 1 TYPECEVT2CF TYPECEVT2CF 15 1 FRSEVTCF FRSEVTCF 20 1 TX_ORDSET TX_ORDSET UCPD Tx Ordered Set Type Register 0x1C 0x20 read-write 0x00000000 TXORDSET TXORDSET 0 20 TX_PAYSZ TX_PAYSZ UCPD Tx Paysize Register 0x20 0x20 read-write 0x00000000 TXPAYSZ TXPAYSZ 0 10 TXDR TXDR UCPD Tx Data Register 0x24 0x20 read-write 0x00000000 TXDATA TXDATA 0 8 RX_ORDSET RX_ORDSET UCPD Rx Ordered Set Register 0x28 0x20 read-only 0x00000000 RXORDSET RXORDSET 0 3 RXSOP3OF4 RXSOP3OF4 3 1 RXSOPKINVALID RXSOPKINVALID 4 3 RX_PAYSZ RX_PAYSZ UCPD Rx Paysize Register 0x2C 0x20 read-only 0x00000000 RXPAYSZ RXPAYSZ 0 10 RXDR RXDR UCPD Receive Data Register 0x30 0x20 read-only 0x00000000 RXDATA RXDATA 0 8 RX_ORDEXT1 RX_ORDEXT1 UCPD Rx Ordered Set Extension Register 0x34 0x20 read-write 0x00000000 RXSOPX1 RXSOPX1 0 20 RX_ORDEXT2 RX_ORDEXT2 UCPD Rx Ordered Set Extension Register 0x38 0x20 read-write 0x00000000 RXSOPX2 RXSOPX2 0 20 SEC_UCPD1 !(DCB->DSCSR & (1 << 16)) 0x5000DC00 FDCAN1 FDCAN1 FDCAN 0x4000A400 0x0 0xC00 registers FDCAN1_IT0 FDCAN1 Interrupt 0 039 FDCAN1_IT1 FDCAN1 Interrupt 1 040 FDCAN_CREL FDCAN_CREL FDCAN Core Release Register 0x0 0x20 read-only 0x32141218 REL Core release 28 4 STEP Step of Core release 24 4 SUBSTEP Sub-step of Core release 20 4 YEAR Timestamp Year 16 4 MON Timestamp Month 8 8 DAY Timestamp Day 0 8 FDCAN_ENDN FDCAN_ENDN FDCAN Core Release Register 0x4 0x20 read-only 0x87654321 ETV Endiannes Test Value 0 32 FDCAN_DBTP FDCAN_DBTP FDCAN Data Bit Timing and Prescaler Register 0xC 0x20 read-write 0x00000A33 DSJW Synchronization Jump Width 0 4 DTSEG2 Data time segment after sample point 4 4 DTSEG1 Data time segment after sample point 8 5 DBRP Data BIt Rate Prescaler 16 5 TDC Transceiver Delay Compensation 23 1 FDCAN_TEST FDCAN_TEST FDCAN Test Register 0x10 0x20 0x0010 LBCK Loop Back mode 4 1 read-write TX Loop Back mode 5 2 read-write RX Control of Transmit Pin 7 1 read-only FDCAN_RWD FDCAN_RWD FDCAN RAM Watchdog Register 0x14 0x20 0x00000000 WDV Watchdog value 8 8 read-only WDC Watchdog configuration 0 8 read-write FDCAN_CCCR FDCAN_CCCR FDCAN CC Control Register 0x18 0x20 read-write 0x00000001 INIT Initialization 0 1 CCE Configuration Change Enable 1 1 ASM ASM Restricted Operation Mode 2 1 CSA Clock Stop Acknowledge 3 1 CSR Clock Stop Request 4 1 MON Bus Monitoring Mode 5 1 DAR Disable Automatic Retransmission 6 1 TEST Test Mode Enable 7 1 FDOE FD Operation Enable 8 1 BSE FDCAN Bit Rate Switching 9 1 PXHD Protocol Exception Handling Disable 12 1 EFBI Edge Filtering during Bus Integration 13 1 TXP TXP 14 1 NISO Non ISO Operation 15 1 FDCAN_NBTP FDCAN_NBTP FDCAN Nominal Bit Timing and Prescaler Register 0x1C 0x20 read-write 0x06000A03 NSJW NSJW: Nominal (Re)Synchronization Jump Width 25 7 NBRP Bit Rate Prescaler 16 9 NTSEG1 Nominal Time segment before sample point 8 8 TSEG2 Nominal Time segment after sample point 0 7 FDCAN_TSCC FDCAN_TSCC FDCAN Timestamp Counter Configuration Register 0x20 0x20 read-write 0x00000000 TCP Timestamp Counter Prescaler 16 4 TSS Timestamp Select 0 2 FDCAN_TSCV FDCAN_TSCV FDCAN Timestamp Counter Value Register 0x24 0x20 read-write 0x00000000 TSC Timestamp Counter 0 16 FDCAN_TOCC FDCAN_TOCC FDCAN Timeout Counter Configuration Register 0x28 0x20 read-write 0xFFFF0000 ETOC Enable Timeout Counter 0 1 TOS Timeout Select 1 2 TOP Timeout Period 16 16 FDCAN_TOCV FDCAN_TOCV FDCAN Timeout Counter Value Register 0x2C 0x20 read-write 0x0000FFFF TOC Timeout Counter 0 16 FDCAN_ECR FDCAN_ECR FDCAN Error Counter Register 0x40 0x20 0x00000000 CEL AN Error Logging 16 8 read-write RP Receive Error Passive 15 1 read-write REC Receive Error Counter 8 7 read-only TEC Transmit Error Counter 0 8 read-only FDCAN_PSR FDCAN_PSR FDCAN Protocol Status Register 0x44 0x20 0x00000707 LEC Last Error Code 0 3 read-write ACT Activity 3 2 read-only EP Error Passive 5 1 read-only EW Warning Status 6 1 read-only BO Bus_Off Status 7 1 read-only DLEC Data Last Error Code 8 3 read-write RESI ESI flag of last received FDCAN Message 11 1 read-write RBRS BRS flag of last received FDCAN Message 12 1 read-write REDL Received FDCAN Message 13 1 read-write PXE Protocol Exception Event 14 1 read-write TDCV Transmitter Delay Compensation Value 16 7 read-only FDCAN_TDCR FDCAN_TDCR FDCAN Transmitter Delay Compensation Register 0x48 0x20 read-write 0x00000000 TDCF Transmitter Delay Compensation Filter Window Length 0 7 TDCO Transmitter Delay Compensation Offset 8 7 FDCAN_IR FDCAN_IR FDCAN Interrupt Register 0x50 0x20 read-write 0x00000000 RF0N RF0N 0 1 RF0F RF0F 1 1 RF0L RF0L 2 1 RF1N RF1N 3 1 RF1F RF1F 4 1 RF1L RF1L 5 1 HPM HPM 6 1 TC TC 7 1 TCF TCF 8 1 TFE TFE 9 1 TEFN TEFN 10 1 TEFF TEFF 11 1 TEFL TEFL 12 1 TSW TSW 13 1 MRAF MRAF 14 1 TOO TOO 15 1 ELO ELO 16 1 EP EP 17 1 EW EW 18 1 BO BO 19 1 WDI WDI 20 1 PEA PEA 21 1 PED PED 22 1 ARA ARA 23 1 FDCAN_IE FDCAN_IE FDCAN Interrupt Enable Register 0x54 0x20 read-write 0x00000000 RF0NE Rx FIFO 0 New Message Enable 0 1 RF0FE Rx FIFO 0 Full Enable 1 1 RF0LE Rx FIFO 0 Message Lost Enable 2 1 RF1NE Rx FIFO 1 New Message Enable 3 1 RF1FE Rx FIFO 1 Watermark Reached Enable 4 1 RF1LE Rx FIFO 1 Message Lost Enable 5 1 HPME High Priority Message Enable 6 1 TCE Transmission Completed Enable 7 1 TCFE Transmission Cancellation Finished Enable 8 1 TEFE Tx FIFO Empty Enable 9 1 TEFNE Tx Event FIFO New Entry Enable 10 1 TEFFE Tx Event FIFO Full Enable 11 1 TEFLE Tx Event FIFO Element Lost Enable 12 1 MRAFE Message RAM Access Failure Enable 13 1 TOOE Timeout Occurred Enable 14 1 ELOE Error Logging Overflow Enable 15 1 EPE Error Passive Enable 16 1 EWE Warning Status Enable 17 1 BOE Bus_Off Status Enable 18 1 WDIE Watchdog Interrupt Enable 19 1 PEAE Protocol Error in Arbitration Phase Enable 20 1 PEDE Protocol Error in Data Phase Enable 21 1 ARAE Access to Reserved Address Enable 22 1 FDCAN_ILS FDCAN_ILS FDCAN Interrupt Line Select Register 0x58 0x20 read-write 0x00000000 RxFIFO0 RxFIFO0 0 1 RxFIFO1 RxFIFO1 1 1 SMSG SMSG 2 1 TFERR TFERR 3 1 MISC MISC 4 1 BERR BERR 5 1 PERR PERR 6 1 FDCAN_ILE FDCAN_ILE FDCAN Interrupt Line Enable Register 0x5C 0x20 read-write 0x00000000 EINT0 Enable Interrupt Line 0 0 1 EINT1 Enable Interrupt Line 1 1 1 FDCAN_RXGFC FDCAN_RXGFC FDCAN Global Filter Configuration Register 0x80 0x20 read-write 0x00000000 RRFE Reject Remote Frames Extended 0 1 RRFS Reject Remote Frames Standard 1 1 ANFE Accept Non-matching Frames Extended 2 2 ANFS Accept Non-matching Frames Standard 4 2 F1OM F1OM 8 1 F0OM F0OM 9 1 LSS LSS 16 5 LSE LSE 24 4 FDCAN_XIDAM FDCAN_XIDAM FDCAN Extended ID and Mask Register 0x84 0x20 read-write 0x1FFFFFFF EIDM Extended ID Mask 0 29 FDCAN_HPMS FDCAN_HPMS FDCAN High Priority Message Status Register 0x88 0x20 read-only 0x00000000 BIDX Buffer Index 0 3 MSI Message Storage Indicator 6 2 FIDX Filter Index 8 5 FLST Filter List 15 1 FDCAN_RXF0S FDCAN_RXF0S FDCAN Rx FIFO 0 Status Register 0x90 0x20 read-write 0x00000000 F0FL Rx FIFO 0 Fill Level 0 4 F0GI Rx FIFO 0 Get Index 8 2 F0PI Rx FIFO 0 Put Index 16 2 F0F Rx FIFO 0 Full 24 1 RF0L Rx FIFO 0 Message Lost 25 1 FDCAN_RXF0A FDCAN_RXF0A CAN Rx FIFO 0 Acknowledge Register 0x94 0x20 read-write 0x00000000 F0AI Rx FIFO 0 Acknowledge Index 0 3 FDCAN_RXF1S FDCAN_RXF1S FDCAN Rx FIFO 1 Status Register 0x98 0x20 0x00000000 F1FL Rx FIFO 1 Fill Level 0 4 read-write F1GI Rx FIFO 1 Get Index 8 2 read-only F1PI Rx FIFO 1 Put Index 16 2 read-only F1F Rx FIFO 1 Full 24 1 read-only RF1L Rx FIFO 1 Message Lost 25 1 read-only FDCAN_RXF1A FDCAN_RXF1A FDCAN Rx FIFO 1 Acknowledge Register 0x9C 0x20 read-write 0x00000000 F1AI Rx FIFO 1 Acknowledge Index 0 3 FDCAN_TXFQS FDCAN_TXFQS FDCAN Tx FIFO/Queue Status Register 0xC4 0x20 read-only 0x00000003 TFFL Tx FIFO Free Level 0 3 TFGI TFGI 8 2 TFQPI Tx FIFO/Queue Put Index 16 2 TFQF Tx FIFO/Queue Full 21 1 FDCAN_TXBRP FDCAN_TXBRP FDCAN Tx Buffer Request Pending Register 0xC8 0x20 read-only 0x00000000 TRP Transmission Request Pending 0 3 FDCAN_TXBAR FDCAN_TXBAR FDCAN Tx Buffer Add Request Register 0xCC 0x20 read-write 0x00000000 AR Add Request 0 3 FDCAN_TXBCR FDCAN_TXBCR FDCAN Tx Buffer Cancellation Request Register 0xD0 0x20 read-write 0x00000000 CR Cancellation Request 0 3 FDCAN_TXBTO FDCAN_TXBTO FDCAN Tx Buffer Transmission Occurred Register 0xD4 0x20 read-only 0x00000000 TO Transmission Occurred. 0 3 FDCAN_TXBCF FDCAN_TXBCF FDCAN Tx Buffer Cancellation Finished Register 0xD8 0x20 read-only 0x00000000 CF Cancellation Finished 0 3 FDCAN_TXBTIE FDCAN_TXBTIE FDCAN Tx Buffer Transmission Interrupt Enable Register 0xDC 0x20 read-write 0x00000000 TIE Transmission Interrupt Enable 0 3 FDCAN_TXBCIE FDCAN_TXBCIE FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register 0xE0 0x20 read-write 0x00000000 CF Cancellation Finished Interrupt Enable 0 3 FDCAN_TXEFS FDCAN_TXEFS FDCAN Tx Event FIFO Status Register 0xE4 0x20 read-only 0x00000000 EFFL Event FIFO Fill Level 0 3 EFGI Event FIFO Get Index. 8 2 EFF Event FIFO Full. 24 1 TEFL Tx Event FIFO Element Lost. 25 1 EFPI Event FIFO Put Index 16 2 FDCAN_TXEFA FDCAN_TXEFA FDCAN Tx Event FIFO Acknowledge Register 0xE8 0x20 read-write 0x00000000 EFAI Event FIFO Acknowledge Index 0 2 FDCAN_CKDIV FDCAN_CKDIV FDCAN TT Trigger Memory Configuration Register 0x100 0x20 read-write 0x00000000 PDIV PDIV 0 4 FDCAN_TXBC FDCAN_TXBC FDCAN Tx buffer configuration register 0xC0 0x20 read-write 0x00000000 TFQM Tx FIFO/Queue Mode 24 1 SEC_FDCAN1 !(DCB->DSCSR & (1 << 16)) 0x5000A400 CRC Cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data register bits 0 32 IDR IDR Independent data register 0x4 0x20 read-write 0x00000000 IDR General-purpose 8-bit data register bits 0 8 CR CR Control register 0x8 0x20 0x00000000 REV_OUT Reverse output data 7 1 read-write REV_IN Reverse input data 5 2 read-write POLYSIZE Polynomial size 3 2 read-write RESET RESET bit 0 1 write-only INIT INIT Initial CRC value 0x10 0x20 read-write 0xFFFFFFFF CRC_INIT Programmable initial CRC value 0 32 POL POL polynomial 0x14 0x20 read-write 0x04C11DB7 Polynomialcoefficients Programmable polynomial 0 32 SEC_CRC !(DCB->DSCSR & (1 << 16)) 0x50023000 CRS Clock recovery system CRS 0x40006000 0x0 0x400 registers CR CR control register 0x0 0x20 read-write 0x00004000 TRIM HSI48 oscillator smooth trimming 8 7 SWSYNC Generate software SYNC event 7 1 AUTOTRIMEN Automatic trimming enable 6 1 CEN Frequency error counter enable 5 1 ESYNCIE Expected SYNC interrupt enable 3 1 ERRIE Synchronization or trimming error interrupt enable 2 1 SYNCWARNIE SYNC warning interrupt enable 1 1 SYNCOKIE SYNC event OK interrupt enable 0 1 CFGR CFGR configuration register 0x4 0x20 read-write 0x2022BB7F SYNCPOL SYNC polarity selection 31 1 SYNCSRC SYNC signal source selection 28 2 SYNCDIV SYNC divider 24 3 FELIM Frequency error limit 16 8 RELOAD Counter reload value 0 16 ISR ISR interrupt and status register 0x8 0x20 read-only 0x00000000 FECAP Frequency error capture 16 16 FEDIR Frequency error direction 15 1 TRIMOVF Trimming overflow or underflow 10 1 SYNCMISS SYNC missed 9 1 SYNCERR SYNC error 8 1 ESYNCF Expected SYNC flag 3 1 ERRF Error flag 2 1 SYNCWARNF SYNC warning flag 1 1 SYNCOKF SYNC event OK flag 0 1 ICR ICR interrupt flag clear register 0xC 0x20 read-write 0x00000000 ESYNCC Expected SYNC clear flag 3 1 ERRC Error clear flag 2 1 SYNCWARNC SYNC warning clear flag 1 1 SYNCOKC SYNC event OK clear flag 0 1 SEC_CRS !(DCB->DSCSR & (1 << 16)) 0x50006000 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 061 CR1 CR1 Control register 1 0x0 0x20 read-write 0x0000 M1 Word length 28 1 EOBIE End of Block interrupt enable 27 1 RTOIE Receiver timeout interrupt enable 26 1 DEAT4 Driver Enable assertion time 25 1 DEAT3 DEAT3 24 1 DEAT2 DEAT2 23 1 DEAT1 DEAT1 22 1 DEAT0 DEAT0 21 1 DEDT4 Driver Enable de-assertion time 20 1 DEDT3 DEDT3 19 1 DEDT2 DEDT2 18 1 DEDT1 DEDT1 17 1 DEDT0 DEDT0 16 1 OVER8 Oversampling mode 15 1 CMIE Character match interrupt enable 14 1 MME Mute mode enable 13 1 M0 Word length 12 1 WAKE Receiver wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXEIE interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXNEIE RXNE interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 UESM USART enable in Stop mode 1 1 UE USART enable 0 1 FIFOEN FIFOEN 29 1 TXFEIE TXFEIE 30 1 RXFFIE RXFFIE 31 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x0000 ADD4_7 Address of the USART node 28 4 ADD0_3 Address of the USART node 24 4 RTOEN Receiver timeout enable 23 1 ABRMOD1 Auto baud rate mode 22 1 ABRMOD0 ABRMOD0 21 1 ABREN Auto baud rate enable 20 1 MSBFIRST Most significant bit first 19 1 DATAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 RXINV RX pin active level inversion 16 1 SWAP Swap TX/RX pins 15 1 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CLKEN Clock enable 11 1 CPOL Clock polarity 10 1 CPHA Clock phase 9 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 SLVEN SLVEN 0 1 DIS_NSS DIS_NSS 3 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x0000 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 SCARCNT Smartcard auto-retry count 17 3 DEP Driver enable polarity selection 15 1 DEM Driver enable mode 14 1 DDRE DMA Disable on Reception Error 13 1 OVRDIS Overrun Disable 12 1 ONEBIT One sample bit method enable 11 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 SCEN Smartcard mode enable 5 1 NACK Smartcard NACK enable 4 1 HDSEL Half-duplex selection 3 1 IRLP Ir low-power 2 1 IREN Ir mode enable 1 1 EIE Error interrupt enable 0 1 TXFTIE TXFTIE 23 1 TCBGTIE TCBGTIE 24 1 RXFTCFG RXFTCFG 25 3 RXFTIE RXFTIE 28 1 TXFTCFG TXFTCFG 29 3 BRR BRR Baud rate register 0xC 0x20 read-write 0x0000 BRR BRR 0 16 GTPR GTPR Guard time and prescaler register 0x10 0x20 read-write 0x0000 GT Guard time value 8 8 PSC Prescaler value 0 8 RTOR RTOR Receiver timeout register 0x14 0x20 read-write 0x0000 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 RQR RQR Request register 0x18 0x20 write-only 0x0000 TXFRQ Transmit data flush request 4 1 RXFRQ Receive data flush request 3 1 MMRQ Mute mode request 2 1 SBKRQ Send break request 1 1 ABRRQ Auto baud rate request 0 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x00C0 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 SBKF SBKF 18 1 CMF CMF 17 1 BUSY BUSY 16 1 ABRF ABRF 15 1 ABRE ABRE 14 1 EOBF EOBF 12 1 RTOF RTOF 11 1 CTS CTS 10 1 CTSIF CTSIF 9 1 LBDF LBDF 8 1 TXE TXE 7 1 TC TC 6 1 RXNE RXNE 5 1 IDLE IDLE 4 1 ORE ORE 3 1 NF NF 2 1 FE FE 1 1 PE PE 0 1 TXFE TXFE 23 1 RXFF RXFF 24 1 TCBGT TCBGT 25 1 RXFT RXFT 26 1 TXFT TXFT 27 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x0000 WUCF Wakeup from Stop mode clear flag 20 1 CMCF Character match clear flag 17 1 EOBCF End of block clear flag 12 1 RTOCF Receiver timeout clear flag 11 1 CTSCF CTS clear flag 9 1 LBDCF LIN break detection clear flag 8 1 TCCF Transmission complete clear flag 6 1 IDLECF Idle line detected clear flag 4 1 ORECF Overrun error clear flag 3 1 NCF Noise detected clear flag 2 1 FECF Framing error clear flag 1 1 PECF Parity error clear flag 0 1 TXFECF TXFECF 5 1 TCBGTCF TCBGTCF 7 1 UDRCF UDRCF 13 1 RDR RDR Receive data register 0x24 0x20 read-only 0x0000 RDR Receive data value 0 9 TDR TDR Transmit data register 0x28 0x20 read-write 0x0000 TDR Transmit data value 0 9 PRESC PRESC PRESC 0x2C 0x20 read-write 0x0000 PRESCALER PRESCALER 0 4 SEC_USART1 !(DCB->DSCSR & (1 << 16)) 0x50013800 USART2 0x40004400 USART2 USART2 global interrupt 062 SEC_USART2 !(DCB->DSCSR & (1 << 16)) 0x50004400 USART3 0x40004800 USART3 USART3 global interrupt 063 SEC_USART3 !(DCB->DSCSR & (1 << 16)) 0x50004800 UART4 0x40004C00 UART4 UART4 global interrupt 064 UART5 0x40005000 UART5 UART5 global interrupt 065 SEC_UART4 !(DCB->DSCSR & (1 << 16)) 0x50004C00 SEC_UART5 !(DCB->DSCSR & (1 << 16)) 0x50005000 ADC_Common Analog-to-Digital Converter ADC 0x42028300 0x0 0x100 registers ADC1_2 ADC1_2 global interrupt 037 CSR CSR ADC Common status register 0x0 0x20 read-only 0x00000000 ADDRDY_MST ADDRDY_MST 0 1 EOSMP_MST EOSMP_MST 1 1 EOC_MST EOC_MST 2 1 EOS_MST EOS_MST 3 1 OVR_MST OVR_MST 4 1 JEOC_MST JEOC_MST 5 1 JEOS_MST JEOS_MST 6 1 AWD1_MST AWD1_MST 7 1 AWD2_MST AWD2_MST 8 1 AWD3_MST AWD3_MST 9 1 JQOVF_MST JQOVF_MST 10 1 ADRDY_SLV ADRDY_SLV 16 1 EOSMP_SLV EOSMP_SLV 17 1 EOC_SLV EOC_SLV 18 1 EOS_SLV EOS_SLV 19 1 OVR_SLV OVR_SLV 20 1 JEOC_SLV JEOC_SLV 21 1 JEOS_SLV JEOS_SLV 22 1 AWD1_SLV AWD1_SLV 23 1 AWD2_SLV AWD2_SLV 24 1 AWD3_SLV AWD3_SLV 25 1 JQOVF_SLV JQOVF_SLV 26 1 CCR CCR ADC common control register 0x8 0x20 read-write 0x00000000 CKMODE ADC clock mode 16 2 PRESC ADC prescaler 18 4 VREFEN VREFINT enable 22 1 CH17SEL CH17SEL 23 1 CH18SEL CH18SEL 24 1 MDMA MDMA 14 2 DMACFG DMACFG 13 1 DELAY DELAY 8 3 DUAL DUAL 0 5 CDR CDR Common regular data register for dual mode 0xC 0x20 read-only 0x00000000 RDATA_MST RDATA_MST 0 16 RDATA_SLV RDATA_SLV 16 16 SEC_ADC_Common !(DCB->DSCSR & (1 << 16)) 0x52028300 ADC Analog-to-Digital Converter ADC 0x42028000 0x0 0x2FD registers ISR ISR interrupt and status register 0x0 0x20 read-write 0x00000000 JQOVF JQOVF 10 1 AWD3 AWD3 9 1 AWD2 AWD2 8 1 AWD1 AWD1 7 1 JEOS JEOS 6 1 JEOC JEOC 5 1 OVR OVR 4 1 EOS EOS 3 1 EOC EOC 2 1 EOSMP EOSMP 1 1 ADRDY ADRDY 0 1 IER IER interrupt enable register 0x4 0x20 read-write 0x00000000 JQOVFIE JQOVFIE 10 1 AWD3IE AWD3IE 9 1 AWD2IE AWD2IE 8 1 AWD1IE AWD1IE 7 1 JEOSIE JEOSIE 6 1 JEOCIE JEOCIE 5 1 OVRIE OVRIE 4 1 EOSIE EOSIE 3 1 EOCIE EOCIE 2 1 EOSMPIE EOSMPIE 1 1 ADRDYIE ADRDYIE 0 1 CR CR control register 0x8 0x20 read-write 0x00000000 ADCAL ADCAL 31 1 ADCALDIF ADCALDIF 30 1 DEEPPWD DEEPPWD 29 1 ADVREGEN ADVREGEN 28 1 JADSTP JADSTP 5 1 ADSTP ADSTP 4 1 JADSTART JADSTART 3 1 ADSTART ADSTART 2 1 ADDIS ADDIS 1 1 ADEN ADEN 0 1 CFGR CFGR configuration register 0xC 0x20 read-write 0x00000000 JQDIS JQDIS 31 1 AWDCH1CH AWDCH1CH 26 5 JAUTO JAUTO 25 1 JAWD1EN JAWD1EN 24 1 AWD1EN AWD1EN 23 1 AWD1SGL AWD1SGL 22 1 JQM JQM 21 1 JDISCEN JDISCEN 20 1 DISCNUM DISCNUM 17 3 DISCEN DISCEN 16 1 AUTDLY AUTDLY 14 1 CONT CONT 13 1 OVRMOD OVRMOD 12 1 EXTEN EXTEN 10 2 EXTSEL EXTSEL 6 4 ALIGN ALIGN 5 1 RES RES 3 2 DMACFG DMACFG 1 1 DMAEN DMAEN 0 1 CFGR2 CFGR2 configuration register 0x10 0x20 read-write 0x00000000 ROVSM EXTEN 10 1 TOVS EXTSEL 9 1 OVSS ALIGN 5 4 OVSR RES 2 3 JOVSE DMACFG 1 1 ROVSE DMAEN 0 1 SMPR1 SMPR1 sample time register 1 0x14 0x20 read-write 0x00000000 SMP9 SMP9 27 3 SMP8 SMP8 24 3 SMP7 SMP7 21 3 SMP6 SMP6 18 3 SMP5 SMP5 15 3 SMP4 SMP4 12 3 SMP3 SMP3 9 3 SMP2 SMP2 6 3 SMP1 SMP1 3 3 SMP0 SMP0 0 3 SMPR2 SMPR2 sample time register 2 0x18 0x20 read-write 0x00000000 SMP18 SMP18 24 3 SMP17 SMP17 21 3 SMP16 SMP16 18 3 SMP15 SMP15 15 3 SMP14 SMP14 12 3 SMP13 SMP13 9 3 SMP12 SMP12 6 3 SMP11 SMP11 3 3 SMP10 SMP10 0 3 TR1 TR1 watchdog threshold register 1 0x20 0x20 read-write 0x0FFF0000 HT1 HT1 16 12 LT1 LT1 0 12 TR2 TR2 watchdog threshold register 0x24 0x20 read-write 0x0FFF0000 HT2 HT2 16 8 LT2 LT2 0 8 TR3 TR3 watchdog threshold register 3 0x28 0x20 read-write 0x0FFF0000 HT3 HT3 16 8 LT3 LT3 0 8 SQR1 SQR1 regular sequence register 1 0x30 0x20 read-write 0x00000000 SQ4 SQ4 24 5 SQ3 SQ3 18 5 SQ2 SQ2 12 5 SQ1 SQ1 6 5 L L 0 4 SQR2 SQR2 regular sequence register 2 0x34 0x20 read-write 0x00000000 SQ9 SQ9 24 5 SQ8 SQ8 18 5 SQ7 SQ7 12 5 SQ6 SQ6 6 5 SQ5 SQ5 0 5 SQR3 SQR3 regular sequence register 3 0x38 0x20 read-write 0x00000000 SQ14 SQ14 24 5 SQ13 SQ13 18 5 SQ12 SQ12 12 5 SQ11 SQ11 6 5 SQ10 SQ10 0 5 SQR4 SQR4 regular sequence register 4 0x3C 0x20 read-write 0x00000000 SQ16 SQ16 6 5 SQ15 SQ15 0 5 DR DR regular Data Register 0x40 0x20 read-only 0x00000000 RDATA regularDATA 0 16 JSQR JSQR injected sequence register 0x4C 0x20 read-write 0x00000000 JSQ4 JSQ4 26 5 JSQ3 JSQ3 20 5 JSQ2 JSQ2 14 5 JSQ1 JSQ1 8 5 JEXTEN JEXTEN 6 2 JEXTSEL JEXTSEL 2 4 JL JL 0 2 OFR1 OFR1 offset register 1 0x60 0x20 read-write 0x00000000 OFFSET1_EN OFFSET1_EN 31 1 OFFSET1_CH OFFSET1_CH 26 5 OFFSET1 OFFSET1 0 12 OFR2 OFR2 offset register 2 0x64 0x20 read-write 0x00000000 OFFSET2_EN OFFSET2_EN 31 1 OFFSET2_CH OFFSET2_CH 26 5 OFFSET2 OFFSET2 0 12 OFR3 OFR3 offset register 3 0x68 0x20 read-write 0x00000000 OFFSET3_EN OFFSET3_EN 31 1 OFFSET3_CH OFFSET3_CH 26 5 OFFSET3 OFFSET3 0 12 OFR4 OFR4 offset register 4 0x6C 0x20 read-write 0x00000000 OFFSET4_EN OFFSET4_EN 31 1 OFFSET4_CH OFFSET4_CH 26 5 OFFSET4 OFFSET4 0 12 JDR1 JDR1 injected data register 1 0x80 0x20 read-only 0x00000000 JDATA JDATA1 0 16 JDR2 JDR2 injected data register 2 0x84 0x20 read-only 0x00000000 JDATA JDATA2 0 16 JDR3 JDR3 injected data register 3 0x88 0x20 read-only 0x00000000 JDATA JDATA3 0 16 JDR4 JDR4 injected data register 4 0x8C 0x20 read-only 0x00000000 JDATA JDATA4 0 16 AWD2CR AWD2CR Analog Watchdog 2 Configuration Register 0xA0 0x20 read-write 0x00000000 AWD2CH AWD2CH 0 19 AWD3CR AWD3CR Analog Watchdog 3 Configuration Register 0xA4 0x20 read-write 0x00000000 AWD3CH AWD3CH 0 19 DIFSEL DIFSEL Differential Mode Selection Register 2 0xB0 0x20 0x00000000 DIFSEL_0 Differential mode for channel 0 0 1 read-only DIFSEL_1_15 Differential mode for channels 15 to 1 1 15 read-write DIFSEL_16_18 Differential mode for channels 18 to 16 16 3 read-only CALFACT CALFACT Calibration Factors 0xB4 0x20 read-write 0x00000000 CALFACT_D CALFACT_D 16 7 CALFACT_S CALFACT_S 0 7 SEC_ADC !(DCB->DSCSR & (1 << 16)) 0x52028000 NVIC Nested Vectored Interrupt Controller NVIC 0xE000E100 0x0 0x37D registers ISER0 ISER0 Interrupt Set-Enable Register 0x0 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER1 ISER1 Interrupt Set-Enable Register 0x4 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER2 ISER2 Interrupt Set-Enable Register 0x8 0x20 read-write 0x00000000 SETENA SETENA 0 32 ICER0 ICER0 Interrupt Clear-Enable Register 0x80 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER1 ICER1 Interrupt Clear-Enable Register 0x84 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER2 ICER2 Interrupt Clear-Enable Register 0x88 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ISPR0 ISPR0 Interrupt Set-Pending Register 0x100 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR1 ISPR1 Interrupt Set-Pending Register 0x104 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR2 ISPR2 Interrupt Set-Pending Register 0x108 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ICPR0 ICPR0 Interrupt Clear-Pending Register 0x180 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR1 ICPR1 Interrupt Clear-Pending Register 0x184 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR2 ICPR2 Interrupt Clear-Pending Register 0x188 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 IABR0 IABR0 Interrupt Active Bit Register 0x200 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR1 IABR1 Interrupt Active Bit Register 0x204 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR2 IABR2 Interrupt Active Bit Register 0x208 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IPR0 IPR0 Interrupt Priority Register 0x300 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR1 IPR1 Interrupt Priority Register 0x304 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR2 IPR2 Interrupt Priority Register 0x308 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR3 IPR3 Interrupt Priority Register 0x30C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR4 IPR4 Interrupt Priority Register 0x310 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR5 IPR5 Interrupt Priority Register 0x314 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR6 IPR6 Interrupt Priority Register 0x318 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR7 IPR7 Interrupt Priority Register 0x31C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR8 IPR8 Interrupt Priority Register 0x320 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR9 IPR9 Interrupt Priority Register 0x324 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR10 IPR10 Interrupt Priority Register 0x328 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR11 IPR11 Interrupt Priority Register 0x32C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR12 IPR12 Interrupt Priority Register 0x330 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR13 IPR13 Interrupt Priority Register 0x334 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR14 IPR14 Interrupt Priority Register 0x338 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR15 IPR15 Interrupt Priority Register 0x33C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR16 IPR16 Interrupt Priority Register 0x340 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR17 IPR17 Interrupt Priority Register 0x344 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR18 IPR18 Interrupt Priority Register 0x348 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR19 IPR19 Interrupt Priority Register 0x34C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR20 IPR20 Interrupt Priority Register 0x350 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 ISER3 ISER3 Interrupt Set-Enable Register 0xC 0x20 read-write 0x00000000 ICER3 ICER3 Interrupt Clear-Enable Register 0x8C 0x20 read-write 0x00000000 ISPR3 ISPR3 Interrupt Set-Pending Register 0x10C 0x20 read-write 0x00000000 ICPR3 ICPR3 Interrupt Clear-Pending Register 0x18C 0x20 read-write 0x00000000 IABR3 IABR3 Interrupt Active Bit Register 0x20C 0x20 read-write 0x00000000 IPR21 IPR21 IPR21 0x354 0x20 read-write 0x00000000 IPR22 IPR22 IPR22 0x358 0x20 read-write 0x00000000 IPR23 IPR23 IPR23 0x35C 0x20 read-write 0x00000000 IPR24 IPR24 IPR24 0x360 0x20 read-write 0x00000000 IPR25 IPR25 IPR25 0x364 0x20 read-write 0x00000000 IPR26 IPR26 IPR26 0x368 0x20 read-write 0x00000000 IPR27 IPR27 IPR27 0x36C 0x20 read-write 0x00000000 IPR28 IPR28 IPR28 0x370 0x20 read-write 0x00000000 IPR29 IPR29 IPR29 0x374 0x20 read-write 0x00000000 NVIC_STIR Nested vectored interrupt controller NVIC 0xE000EF00 0x0 0x5 registers STIR STIR Software trigger interrupt register 0x0 0x20 read-write 0x00000000 INTID Software generated interrupt ID 0 9 FMC FMC FMC 0x44020000 0x0 0x400 registers FMC FMC global interrupt 75 FMC_BCR1 FMC_BCR1 FMC_BCR1 0x0 0x20 read-write 0x000030DB MBKEN Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus. 0 1 MUXEN Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories: 1 1 MTYP Memory type These bits define the type of external memory attached to the corresponding memory bank: 2 2 MWID Memory data bus width Defines the external memory device width, valid for all type of memories. 4 2 FACCEN Flash access enable This bit enables NOR Flash memory access operations. 6 1 BURSTEN Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode: 8 1 WAITPOL Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode: 9 1 WAITCFG Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 11 1 WREN Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC: 12 1 WAITEN Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode. 13 1 EXTMOD Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). 14 1 ASYNCWAIT Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. 15 1 CPSIZE CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved. 16 3 CBURSTRW Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. 19 1 CCLKEN Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.) 20 1 WFDIS Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. 21 1 NBLSET NBLSET 22 2 FMC_BCR2 FMC_BCR2 FMC_BCR2 0x8 0x20 read-write 0x000030D2 MBKEN Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus. 0 1 MUXEN Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories: 1 1 MTYP Memory type These bits define the type of external memory attached to the corresponding memory bank: 2 2 MWID Memory data bus width Defines the external memory device width, valid for all type of memories. 4 2 FACCEN Flash access enable This bit enables NOR Flash memory access operations. 6 1 BURSTEN Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode: 8 1 WAITPOL Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode: 9 1 WAITCFG Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 11 1 WREN Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC: 12 1 WAITEN Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode. 13 1 EXTMOD Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). 14 1 ASYNCWAIT Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. 15 1 CPSIZE CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved. 16 3 CBURSTRW Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. 19 1 CCLKEN Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.) 20 1 WFDIS Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. 21 1 NBLSET NBLSET 22 2 FMC_BCR3 FMC_BCR3 >FMC_BCR3 0x10 0x20 read-write 0x000030D2 MBKEN Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus. 0 1 MUXEN Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories: 1 1 MTYP Memory type These bits define the type of external memory attached to the corresponding memory bank: 2 2 MWID Memory data bus width Defines the external memory device width, valid for all type of memories. 4 2 FACCEN Flash access enable This bit enables NOR Flash memory access operations. 6 1 BURSTEN Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode: 8 1 WAITPOL Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode: 9 1 WAITCFG Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 11 1 WREN Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC: 12 1 WAITEN Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode. 13 1 EXTMOD Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). 14 1 ASYNCWAIT Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. 15 1 CPSIZE CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved. 16 3 CBURSTRW Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. 19 1 CCLKEN Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.) 20 1 WFDIS Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. 21 1 NBLSET NBLSET 22 2 FMC_BCR4 FMC_BCR4 >FMC_BCR4 0x18 0x20 read-write 0x000030D2 MBKEN Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus. 0 1 MUXEN Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories: 1 1 MTYP Memory type These bits define the type of external memory attached to the corresponding memory bank: 2 2 MWID Memory data bus width Defines the external memory device width, valid for all type of memories. 4 2 FACCEN Flash access enable This bit enables NOR Flash memory access operations. 6 1 BURSTEN Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode: 8 1 WAITPOL Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode: 9 1 WAITCFG Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 11 1 WREN Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC: 12 1 WAITEN Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode. 13 1 EXTMOD Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). 14 1 ASYNCWAIT Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. 15 1 CPSIZE CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved. 16 3 CBURSTRW Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. 19 1 CCLKEN Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.) 20 1 WFDIS Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. 21 1 NBLSET NBLSET 22 2 FMC_BTR1 FMC_BTR1 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). 0x4 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1. 0 4 ADDHLD Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration. 4 4 DATAST Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care. 8 8 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. ... 16 4 CLKDIV Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula) 20 4 DATLAT Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles 24 4 ACCMOD Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 DATAHLD DATAHLD 30 2 FMC_BTR2 FMC_BTR2 FMC_BTR2 0xC 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1. 0 4 ADDHLD Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration. 4 4 DATAST Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care. 8 8 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. ... 16 4 CLKDIV Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula) 20 4 DATLAT Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles 24 4 ACCMOD Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 DATAHLD DATAHLD 30 2 FMC_BTR3 FMC_BTR3 FMC_BTR3 0x14 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1. 0 4 ADDHLD Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration. 4 4 DATAST Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care. 8 8 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. ... 16 4 CLKDIV Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula) 20 4 DATLAT Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles 24 4 ACCMOD Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 DATAHLD DATAHLD 30 2 FMC_BTR4 FMC_BTR4 FMC_BTR4 0x1C 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1. 0 4 ADDHLD Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration. 4 4 DATAST Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care. 8 8 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. ... 16 4 CLKDIV Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula) 20 4 DATLAT Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles 24 4 ACCMOD Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 DATAHLD DATAHLD 30 2 FMC_PCR FMC_PCR NAND Flash control registers 0x80 0x20 read-write 0x00000018 PWAITEN Wait feature enable bit. This bit enables the Wait feature for the NAND Flash memory bank: 1 1 PBKEN NAND Flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus 2 1 PTYP Memory type 3 1 PWID Data bus width. These bits define the external memory device width. 4 2 ECCEN ECC computation logic enable bit 6 1 TCLR CLE to RE delay. These bits set time from CLE low to RE low in number of KCK_FMC clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is the KCK_FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space. 9 4 TAR ALE to RE delay. These bits set time from ALE low to RE low in number of KCK_FMC clock cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC where TKCK_FMC is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space. 13 4 ECCPS ECC page size. These bits define the page size for the extended ECC: 17 3 FMC_SR FMC_SR This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty. 0x84 0x20 0x00000040 IRS Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set. 0 1 read-write ILS Interrupt high-level status The flag is set by hardware and reset by software. 1 1 read-write IFS Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set. 2 1 read-write IREN Interrupt rising edge detection enable bit 3 1 read-write ILEN Interrupt high-level detection enable bit 4 1 read-write IFEN Interrupt falling edge detection enable bit 5 1 read-write FEMPT FIFO empty. Read-only bit that provides the status of the FIFO 6 1 read-only FMC_PMEM FMC_PMEM The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access. 0x88 0x20 read-write 0xFCFCFCFC MEMSET Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space: 0 8 MEMWAIT Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC: 8 8 MEMHOLD Common memory hold time These bits define the number of KCK_FMC clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is de-asserted (NWE, NOE), for NAND Flash read or write access to common memory space: 16 8 MEMHIZ Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space. This is only valid for write transactions: 24 8 FMC_PATT FMC_PATT The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature). 0x8C 0x20 read-write 0xFCFCFCFC ATTSET Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space: 0 8 ATTWAIT Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC: 8 8 ATTHOLD Attribute memory hold time These bits define the number of KCK_FMC clock cycles during which the address is held (and data for write access) after the command de-assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space: 16 8 ATTHIZ Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction: 24 8 FMC_ECCR FMC_ECCR This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1. 0x94 0x20 read-only 0x00000000 ECC ECC result This field contains the value computed by the ECC computation logic. Table167 describes the contents of these bit fields. 0 32 FMC_BWTR1 FMC_BWTR1 This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 0x104 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1. 0 4 ADDHLD Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. 4 4 DATAST Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: 8 8 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ... 16 4 ACCMOD Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 FMC_BWTR2 FMC_BWTR2 This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 0x10C 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1. 0 4 ADDHLD Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. 4 4 DATAST Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: 8 8 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ... 16 4 ACCMOD Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 FMC_BWTR3 FMC_BWTR3 This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 0x114 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1. 0 4 ADDHLD Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. 4 4 DATAST Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: 8 8 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ... 16 4 ACCMOD Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 FMC_BWTR4 FMC_BWTR4 This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 0x11C 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1. 0 4 ADDHLD Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. 4 4 DATAST Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: 8 8 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ... 16 4 ACCMOD Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 PCSCNTR PCSCNTR PCSCNTR 0x20 0x20 read-write 0x00000000 CSCOUNT Chip select counter 0 16 CNTB1EN Counter Bank 1 enable 16 1 CNTB2EN Counter Bank 2 enable 17 1 CNTB3EN Counter Bank 3 enable 18 1 CNTB4EN Counter Bank 4 enable 19 1 SEC_FMC !(DCB->DSCSR & (1 << 16)) 0x54020000 RNG RNG RNG 0x420C0800 0x0 0x400 registers RNG RNG global interrupt 94 RNG_CR RNG_CR RNG control register 0x0 0x20 read-write 0x00000000 RNGEN Random number generator enable 2 1 IE Interrupt enable 3 1 CED Clock error detection Note: The clock error detection can be used only when ck_rc48 or ck_pll1_q (ck_pll1_q = 48MHz) source is selected otherwise, CED bit must be equal to 1. The clock error detection cannot be enabled nor disabled on the fly when RNG peripheral is enabled, to enable or disable CED the RNG must be disabled. 5 1 RNG_CONFIG3 RNG configuration 3 8 4 NISTC Non NIST compliant 12 1 RNG_CONFIG2 RNG configuration 2 13 3 CLKDIV Clock divider factor 16 4 RNG_CONFIG1 RNG configuration 1 20 6 CONDRST Conditioning soft reset 30 1 CONFIGLOCK RNG Config Lock 31 1 RNG_SR RNG_SR RNG status register 0x4 0x20 0x00000000 DRDY Data ready Note: If IE=1 in RNG_CR, an interrupt is generated when DRDY=1. It can rise when the peripheral is disabled. When the output buffer becomes empty (after reading RNG_DR), this bit returns to 0 until a new random value is generated. 0 1 read-only CECS Clock error current status Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1. 1 1 read-only SECS Seed error current status ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01) 2 1 read-only CEIS Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing it to 0. An interrupt is pending if IE = 1 in the RNG_CR register. Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1. 5 1 read-write SEIS Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing it to 0. ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01) An interrupt is pending if IE = 1 in the RNG_CR register. 6 1 read-write RNG_DR RNG_DR The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0. 0x8 0x20 read-only 0x00000000 RNDATA Random data 32-bit random data which are valid when DRDY=1. 0 32 RNG_HTCR RNG_HTCR The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0. 0x10 0x20 read-write 0x000CAA74 HTCFG health test configuration 0 32 SEC_RNG !(DCB->DSCSR & (1 << 16)) 0x520C0800 SDMMC1 SDMMC1 SDMMC 0x420C8000 0x0 0x3FD registers SDMMC1 SDMMC1 global interrupt 78 SDMMC_POWER SDMMC_POWER SDMMC power control register 0x0 0x20 read-write 0x00000000 PWRCTRL SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11. 0 2 VSWITCH Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence: 2 1 VSWITCHEN Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response: 3 1 DIRPOL Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00). 4 1 SDMMC_CLKCR SDMMC_CLKCR The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width. 0x4 0x20 read-write 0x00000000 CLKDIV Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.. 0 10 PWRSAV Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV: 12 1 WIDBUS Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 14 2 NEGEDGE SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division &gt;1 (CLKDIV &gt; 0) &amp; DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. 16 1 HWFC_EN Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11. 17 1 DDR Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS &gt; 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division &gt;1. (CLKDIV &gt; 0) 18 1 BUSSPEED Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 19 1 SELCLKRX Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 20 2 SDMMC_ARGR SDMMC_ARGR The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message. 0x8 0x20 read-write 0x00000000 CMDARG Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register. 0 32 SDMMC_CMDR SDMMC_CMDR The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). 0xC 0x20 read-write 0x00000000 CMDINDEX Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message. 0 6 CMDTRANS The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent. 6 1 CMDSTOP The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent. 7 1 WAITRESP Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response. 8 2 WAITINT CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode. 10 1 WAITPEND CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card. 11 1 CPSMEN Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0. 12 1 DTHOLD Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state. 13 1 BOOTMODE Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0) 14 1 BOOTEN Enable boot mode procedure. 15 1 CMDSUSPEND The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1. 16 1 SDMMC_RESP1R SDMMC_RESP1R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x14 0x20 read-only 0x00000000 CARDSTATUS1 see Table 432 0 32 SDMMC_RESP2R SDMMC_RESP2R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x18 0x20 read-only 0x00000000 CARDSTATUS2 see Table404. 0 32 SDMMC_RESP3R SDMMC_RESP3R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x1C 0x20 read-only 0x00000000 CARDSTATUS3 see Table404. 0 32 SDMMC_RESP4R SDMMC_RESP4R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x20 0x20 read-only 0x00000000 CARDSTATUS4 see Table404. 0 32 SDMMC_DTIMER SDMMC_DTIMER The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. 0x24 0x20 read-write 0x00000000 DATATIME Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods. 0 32 SDMMC_DLENR SDMMC_DLENR The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. 0x28 0x20 read-write 0x00000000 DATALENGTH Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0. 0 25 SDMMC_DCTRL SDMMC_DCTRL The SDMMC_DCTRL register control the data path state machine (DPSM). 0x2C 0x20 read-write 0x00000000 DTEN Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards. 0 1 DTDIR Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 1 1 DTMODE Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 2 2 DBLOCKSIZE Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered) 4 4 RWSTART Read wait start. If this bit is set, read wait operation starts. 8 1 RWSTOP Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state. 9 1 RWMOD Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 10 1 SDIOEN SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation. 11 1 BOOTACKEN Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 12 1 FIFORST FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs. 13 1 SDMMC_DCNTR SDMMC_DCNTR The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set. 0x30 0x20 read-only 0x00000000 DATACOUNT Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect. 0 25 SDMMC_STAR SDMMC_STAR The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO) 0x34 0x20 read-only 0x00000000 CCRCFAIL Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 0 1 DCRCFAIL Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 1 1 CTIMEOUT Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods. 2 1 DTIMEOUT Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 3 1 TXUNDERR Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 4 1 RXOVERR Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 5 1 CMDREND Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 6 1 CMDSENT Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 7 1 DATAEND Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 8 1 DHOLD Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 9 1 DBCKEND Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 10 1 DABORT Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 11 1 DPSMACT Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. 12 1 CPSMACT Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. 13 1 TXFIFOHE Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full. 14 1 RXFIFOHF Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty. 15 1 TXFIFOF Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty. 16 1 RXFIFOF Receive FIFO full This bit is cleared when one FIFO location becomes empty. 17 1 TXFIFOE Transmit FIFO empty This bit is cleared when one FIFO location becomes full. 18 1 RXFIFOE Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full. 19 1 BUSYD0 Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt. 20 1 BUSYD0END end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 21 1 SDIOIT SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 22 1 ACKFAIL Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 23 1 ACKTIMEOUT Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 24 1 VSWEND Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 25 1 CKSTOP SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 26 1 IDMATE IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 27 1 IDMABTC IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 28 1 SDMMC_ICR SDMMC_ICR The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register. 0x38 0x20 read-write 0x00000000 CCRCFAILC CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag. 0 1 DCRCFAILC DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag. 1 1 CTIMEOUTC CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag. 2 1 DTIMEOUTC DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag. 3 1 TXUNDERRC TXUNDERR flag clear bit Set by software to clear TXUNDERR flag. 4 1 RXOVERRC RXOVERR flag clear bit Set by software to clear the RXOVERR flag. 5 1 CMDRENDC CMDREND flag clear bit Set by software to clear the CMDREND flag. 6 1 CMDSENTC CMDSENT flag clear bit Set by software to clear the CMDSENT flag. 7 1 DATAENDC DATAEND flag clear bit Set by software to clear the DATAEND flag. 8 1 DHOLDC DHOLD flag clear bit Set by software to clear the DHOLD flag. 9 1 DBCKENDC DBCKEND flag clear bit Set by software to clear the DBCKEND flag. 10 1 DABORTC DABORT flag clear bit Set by software to clear the DABORT flag. 11 1 BUSYD0ENDC BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag. 21 1 SDIOITC SDIOIT flag clear bit Set by software to clear the SDIOIT flag. 22 1 ACKFAILC ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag. 23 1 ACKTIMEOUTC ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag. 24 1 VSWENDC VSWEND flag clear bit Set by software to clear the VSWEND flag. 25 1 CKSTOPC CKSTOP flag clear bit Set by software to clear the CKSTOP flag. 26 1 IDMATEC IDMA transfer error clear bit Set by software to clear the IDMATE flag. 27 1 IDMABTCC IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag. 28 1 SDMMC_MASKR SDMMC_MASKR The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1. 0x3C 0x20 read-write 0x00000000 CCRCFAILIE Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure. 0 1 DCRCFAILIE Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure. 1 1 CTIMEOUTIE Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout. 2 1 DTIMEOUTIE Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout. 3 1 TXUNDERRIE Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error. 4 1 RXOVERRIE Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error. 5 1 CMDRENDIE Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. 6 1 CMDSENTIE Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command. 7 1 DATAENDIE Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end. 8 1 DHOLDIE Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state. 9 1 DBCKENDIE Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end. 10 1 DABORTIE Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted. 11 1 TXFIFOHEIE Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty. 14 1 RXFIFOHFIE Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full. 15 1 RXFIFOFIE Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full. 17 1 TXFIFOEIE Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty. 18 1 BUSYD0ENDIE BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response. 21 1 SDIOITIE SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt. 22 1 ACKFAILIE Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail. 23 1 ACKTIMEOUTIE Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout. 24 1 VSWENDIE Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion. 25 1 CKSTOPIE Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped. 26 1 IDMABTCIE IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer. 28 1 SDMMC_ACKTIMER SDMMC_ACKTIMER The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set. 0x40 0x20 read-write 0x00000000 ACKTIME Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods. 0 25 SDMMC_IDMACTRLR SDMMC_IDMACTRLR The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. 0x50 0x20 read-write 0x00000000 IDMAEN IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0 1 IDMABMODE Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 1 1 IDMABACT Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware. 2 1 SDMMC_IDMABSIZER SDMMC_IDMABSIZER The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration. 0x54 0x20 read-write 0x00000000 IDMABNDT Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0). 5 8 SDMMC_IDMABASE0R SDMMC_IDMABASE0R The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration. 0x58 0x20 read-write 0x00000000 IDMABASE0 Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1). 0 32 SDMMC_IDMABASE1R SDMMC_IDMABASE1R The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address. 0x5C 0x20 read-write 0x00000000 IDMABASE1 Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0). 0 32 SDMMC_FIFOR SDMMC_FIFOR The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x80 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words. 0 32 SDMMC_VER SDMMC_VER SDMMC IP version register 0x3F4 0x20 read-only 0x00000010 MINREV IP minor revision number. 0 4 MAJREV IP major revision number. 4 4 SDMMC_ID SDMMC_ID SDMMC IP identification register 0x3F8 0x20 read-only 0x00140022 IP_ID SDMMC IP identification. 0 32 SDMMC_RESPCMDR SDMMC_RESPCMDR SDMMC command response register 0x10 0x20 read-only 0xA3C5DD01 RESPCMD Response command index 0 6 SEC_SDMMC1 !(DCB->DSCSR & (1 << 16)) 0x520C8000