STM32G070 1.6 STM32G070 CM0 r0p1 little true false 4 false 8 32 0x20 0x0 0xFFFFFFFF ADC Analog to Digital ConverteR ADC 0x40012400 0x0 0x400 registers ADC ADC interrupt (ADC combined with EXTI 17 and 18) 12 ADC_ISR ADC_ISR ADC interrupt and status register 0x0 0x20 0x00000000 0xFFFFFFFF ADRDY ADC ready This bit is set by hardware after the ADC has been enabled (ADEN=1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it. 0 1 read-write B_0x0 ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software) 0x0 B_0x1 ADC is ready to start conversion 0x1 EOSMP End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to '1’. 1 1 read-write B_0x0 Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software) 0x0 B_0x1 End of sampling phase reached 0x1 EOC End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register. 2 1 read-write B_0x0 Channel conversion not complete (or the flag event was already acknowledged and cleared by software) 0x0 B_0x1 Channel conversion complete 0x1 EOS End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it. 3 1 read-write B_0x0 Conversion sequence not complete (or the flag event was already acknowledged and cleared by software) 0x0 B_0x1 Conversion sequence complete 0x1 OVR ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it. 4 1 read-write B_0x0 No overrun occurred (or the flag event was already acknowledged and cleared by software) 0x0 B_0x1 Overrun has occurred 0x1 AWD1 Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1. 7 1 read-write B_0x0 No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) 0x0 B_0x1 Analog watchdog event occurred 0x1 AWD2 Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it. 8 1 read-write B_0x0 No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) 0x0 B_0x1 Analog watchdog event occurred 0x1 AWD3 Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1. 9 1 read-write B_0x0 No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) 0x0 B_0x1 Analog watchdog event occurred 0x1 EOCAL End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it. 11 1 read-write B_0x0 Calibration is not complete 0x0 B_0x1 Calibration is complete 0x1 CCRDY Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration. 13 1 read-write B_0x0 Channel configuration update not applied. 0x0 B_0x1 Channel configuration update is applied. 0x1 ADC_IER ADC_IER ADC interrupt enable register 0x4 0x20 0x00000000 0xFFFFFFFF ADRDYIE ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 0 1 read-write B_0x0 ADRDY interrupt disabled. 0x0 B_0x1 ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set. 0x1 EOSMPIE End of sampling flag interrupt enable This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 1 1 read-write B_0x0 EOSMP interrupt disabled. 0x0 B_0x1 EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set. 0x1 EOCIE End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 2 1 read-write B_0x0 EOC interrupt disabled 0x0 B_0x1 EOC interrupt enabled. An interrupt is generated when the EOC bit is set. 0x1 EOSIE End of conversion sequence interrupt enable This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 3 1 read-write B_0x0 EOS interrupt disabled 0x0 B_0x1 EOS interrupt enabled. An interrupt is generated when the EOS bit is set. 0x1 OVRIE Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 4 1 read-write B_0x0 Overrun interrupt disabled 0x0 B_0x1 Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. 0x1 AWD1IE Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 7 1 read-write B_0x0 Analog watchdog interrupt disabled 0x0 B_0x1 Analog watchdog interrupt enabled 0x1 AWD2IE Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 8 1 read-write B_0x0 Analog watchdog interrupt disabled 0x0 B_0x1 Analog watchdog interrupt enabled 0x1 AWD3IE Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 9 1 read-write B_0x0 Analog watchdog interrupt disabled 0x0 B_0x1 Analog watchdog interrupt enabled 0x1 EOCALIE End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 11 1 read-write B_0x0 End of calibration interrupt disabled 0x0 B_0x1 End of calibration interrupt enabled 0x1 CCRDYIE Channel Configuration Ready Interrupt enable This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 13 1 read-write B_0x0 Channel configuration ready interrupt disabled 0x0 B_0x1 Channel configuration ready interrupt enabled 0x1 ADC_CR ADC_CR ADC control register 0x8 0x20 0x00000000 0xFFFFFFFF ADEN ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0) 0 1 read-write B_0x0 ADC is disabled (OFF state) 0x0 B_0x1 Write 1 to enable the ADC. 0x1 ADDIS ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1’ is only effective when ADEN=1 and ADSTART=0 (which ensures that no conversion is ongoing) 1 1 read-write B_0x0 No ADDIS command ongoing 0x0 B_0x1 Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress. 0x1 ADSTART ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT=0, DISCEN=0), when software trigger is selected (EXTEN=00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored. 2 1 read-write B_0x0 No ADC conversion is ongoing. 0x0 B_0x1 Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting. 0x1 ADSTP ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1’ is only effective when ADSTART=1 and ADDIS=0 (ADC is enabled and may be converting and there is no pending request to disable the ADC) 4 1 read-write B_0x0 No ADC stop conversion command ongoing 0x0 B_0x1 Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress. 0x1 ADVREGEN ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). 28 1 read-write B_0x0 ADC voltage regulator disabled 0x0 B_0x1 ADC voltage regulator enabled 0x1 ADCAL ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 (ADC enabled and no conversion is ongoing). 31 1 read-write B_0x0 Calibration complete 0x0 B_0x1 Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress. 0x1 ADC_CFGR1 ADC_CFGR1 ADC configuration register 1 0xc 0x20 0x00000000 0xFFFFFFFF DMAEN Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to . Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 0 1 read-write B_0x0 DMA disabled 0x0 B_0x1 DMA enabled 0x1 DMACFG Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN=1. For more details, refer to page351 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 1 1 read-write B_0x0 DMA one shot mode selected 0x0 B_0x1 DMA circular mode selected 0x1 SCANDIR Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared to 0. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 2 1 read-write B_0x0 Upward scan (from CHSEL0 to CHSEL18) 0x0 B_0x1 Backward scan (from CHSEL18 to CHSEL0) 0x1 RES Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADEN=0. 3 2 read-write B_0x0 12 bits 0x0 B_0x1 10 bits 0x1 B_0x2 8 bits 0x2 B_0x3 6 bits 0x3 ALIGN Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Data alignment and resolution (oversampling disabled: OVSE = 0) on page349 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 5 1 read-write B_0x0 Right alignment 0x0 B_0x1 Left alignment 0x1 EXTSEL External trigger selection These bits select the external event used to trigger the start of conversion (refer to External triggers for details): Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 6 3 read-write B_0x0 TRG0 0x0 B_0x1 TRG1 0x1 B_0x2 TRG2 0x2 B_0x3 TRG3 0x3 B_0x4 TRG4 0x4 B_0x5 TRG5 0x5 B_0x6 TRG6 0x6 B_0x7 TRG7 0x7 EXTEN External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 10 2 read-write B_0x0 Hardware trigger detection disabled (conversions can be started by software) 0x0 B_0x1 Hardware trigger detection on the rising edge 0x1 B_0x2 Hardware trigger detection on the falling edge 0x2 B_0x3 Hardware trigger detection on both the rising and falling edges 0x3 OVRMOD Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 12 1 read-write B_0x0 ADC_DR register is preserved with the old data when an overrun is detected. 0x0 B_0x1 ADC_DR register is overwritten with the last conversion result when an overrun is detected. 0x1 CONT Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN=1 and CONT=1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 13 1 read-write B_0x0 Single conversion mode 0x0 B_0x1 Continuous conversion mode 0x1 WAIT Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 14 1 read-write B_0x0 Wait conversion mode off 0x0 B_0x1 Wait conversion mode on 0x1 AUTOFF Auto-off mode This bit is set and cleared by software to enable/disable auto-off mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 15 1 read-write B_0x0 Auto-off mode disabled 0x0 B_0x1 Auto-off mode enabled 0x1 DISCEN Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN=1 and CONT=1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 16 1 read-write B_0x0 Discontinuous mode disabled 0x0 B_0x1 Discontinuous mode enabled 0x1 CHSELRMOD Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 21 1 read-write B_0x0 Each bit of the ADC_CHSELR register enables an input 0x0 B_0x1 ADC_CHSELR register is able to sequence up to 8 channels 0x1 AWD1SGL Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 22 1 read-write B_0x0 Analog watchdog 1 enabled on all channels 0x0 B_0x1 Analog watchdog 1 enabled on a single channel 0x1 AWD1EN Analog watchdog enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 23 1 read-write B_0x0 Analog watchdog 1 disabled 0x0 B_0x1 Analog watchdog 1 enabled 0x1 AWD1CH Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 26 5 read-write B_0x0 ADC analog input Channel 0 monitored by AWD 0x0 B_0x1 ADC analog input Channel 1 monitored by AWD 0x1 B_0x11 ADC analog input Channel 17 monitored by AWD 0x11 B_0x12 ADC analog input Channel 18 monitored by AWD 0x12 ADC_CFGR2 ADC_CFGR2 ADC configuration register 2 0x10 0x20 0x00000000 0xFFFFFFFF OVSE Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 1 read-write B_0x0 Oversampler disabled 0x0 B_0x1 Oversampler enabled 0x1 OVSR Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 2 3 read-write B_0x0 2x 0x0 B_0x1 4x 0x1 B_0x2 8x 0x2 B_0x3 16x 0x3 B_0x4 32x 0x4 B_0x5 64x 0x5 B_0x6 128x 0x6 B_0x7 256x 0x7 OVSS Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 5 4 read-write B_0x0 No shift 0x0 B_0x1 Shift 1-bit 0x1 B_0x2 Shift 2-bits 0x2 B_0x3 Shift 3-bits 0x3 B_0x4 Shift 4-bits 0x4 B_0x5 Shift 5-bits 0x5 B_0x6 Shift 6-bits 0x6 B_0x7 Shift 7-bits 0x7 B_0x8 Shift 8-bits 0x8 TOVS Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 9 1 read-write B_0x0 All oversampled conversions for a channel are done consecutively after a trigger 0x0 B_0x1 Each oversampled conversion for a channel needs a trigger 0x1 LFTRIG Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 29 1 read-write B_0x0 Low Frequency Trigger Mode disabled 0x0 B_0x1 Low Frequency Trigger Mode enabled 0x1 CKMODE ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). 30 2 read-write B_0x0 ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section) 0x0 B_0x1 PCLK/2 (Synchronous clock mode) 0x1 B_0x2 PCLK/4 (Synchronous clock mode) 0x2 B_0x3 PCLK (Synchronous clock mode). This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle) 0x3 ADC_SMPR ADC_SMPR ADC sampling time register 0x14 0x20 0x00000000 0xFFFFFFFF SMP1 Sampling time selection 1 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 3 read-write B_0x0 1.5 ADC clock cycles 0x0 B_0x1 3.5 ADC clock cycles 0x1 B_0x2 7.5 ADC clock cycles 0x2 B_0x3 12.5 ADC clock cycles 0x3 B_0x4 19.5 ADC clock cycles 0x4 B_0x5 39.5 ADC clock cycles 0x5 B_0x6 79.5 ADC clock cycles 0x6 B_0x7 160.5 ADC clock cycles 0x7 SMP2 Sampling time selection 2 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 4 3 read-write B_0x0 1.5 ADC clock cycles 0x0 B_0x1 3.5 ADC clock cycles 0x1 B_0x2 7.5 ADC clock cycles 0x2 B_0x3 12.5 ADC clock cycles 0x3 B_0x4 19.5 ADC clock cycles 0x4 B_0x5 39.5 ADC clock cycles 0x5 B_0x6 79.5 ADC clock cycles 0x6 B_0x7 160.5 ADC clock cycles 0x7 SMPSEL0 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 8 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL1 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 9 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL2 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 10 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL3 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 11 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL4 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 12 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL5 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 13 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL6 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 14 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL7 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 15 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL8 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 16 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL9 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 17 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL10 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 18 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL11 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 19 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL12 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 20 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL13 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 21 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL14 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 22 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL15 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 23 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL16 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 24 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL17 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 25 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL18 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 26 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 ADC_AWD1TR ADC_AWD1TR ADC watchdog threshold register 0x20 0x20 0x0FFF0000 0xFFFFFFFF LT1 Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page355. 0 12 read-write HT1 Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page355. 16 12 read-write ADC_AWD2TR ADC_AWD2TR ADC watchdog threshold register 0x24 0x20 0x0FFF0000 0xFFFFFFFF LT2 Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page355. 0 12 read-write HT2 Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page355. 16 12 read-write ADC_CHSELR_0 ADC_CHSELR_0 ADC channel selection register [alternate] 0x28 0x20 0x00000000 0xFFFFFFFF CHSEL0 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 0 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL1 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 1 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL2 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 2 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL3 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 3 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL4 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 4 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL5 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 5 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL6 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 6 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL7 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 7 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL8 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 8 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL9 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 9 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL10 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 10 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL11 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 11 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL12 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 12 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL13 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 13 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL14 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 14 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL15 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 15 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL16 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 16 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL17 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 17 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL18 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 18 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 ADC_CHSELR_1 ADC_CHSELR_1 channel selection register CHSELRMOD = 1 in ADC_CFGR1 ADC_CHSELR_0 0x28 0x20 read-write 0x00000000 SQ1 1st conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 4 read-write SQ2 2nd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 4 4 read-write SQ3 3rd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 8 4 read-write SQ4 4th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 12 4 read-write SQ5 5th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 16 4 read-write SQ6 6th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 20 4 read-write SQ7 7th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 24 4 read-write SQ8 8th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates the end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. ... Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 28 4 read-write B_0x0 CH0 0x0 B_0x1 CH1 0x1 B_0xC CH12 0xC B_0xD CH13 0xD B_0xE CH14 0xE B_0xF No channel selected (End of sequence) 0xF ADC_AWD3TR ADC_AWD3TR ADC watchdog threshold register 0x2c 0x20 0x0FFF0000 0xFFFFFFFF LT3 Analog watchdog 3lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page355. 0 12 read-write HT3 Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page355. 16 12 read-write ADC_DR ADC_DR ADC data register 0x40 0x20 0x00000000 0xFFFFFFFF DATA Converted data These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in OVSE = 0) on page349. Just after a calibration is complete, DATA[6:0] contains the calibration factor. 0 16 read-only ADC_AWD2CR ADC_AWD2CR ADC Analog Watchdog 2 Configuration register 0xa0 0x20 0x00000000 0xFFFFFFFF AWD2CH0 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH1 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 1 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH2 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 2 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH3 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 3 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH4 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 4 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH5 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 5 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH6 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 6 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH7 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 7 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH8 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 8 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH9 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 9 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH10 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 10 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH11 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 11 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH12 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 12 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH13 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 13 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH14 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 14 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH15 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 15 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH16 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 16 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH17 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 17 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH18 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 18 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 ADC_AWD3CR ADC_AWD3CR ADC Analog Watchdog 3 Configuration register 0xa4 0x20 0x00000000 0xFFFFFFFF AWD3CH0 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH1 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 1 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH2 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 2 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH3 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 3 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH4 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 4 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH5 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 5 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH6 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 6 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH7 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 7 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH8 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 8 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH9 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 9 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH10 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 10 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH11 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 11 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH12 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 12 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH13 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 13 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH14 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 14 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH15 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 15 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH16 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 16 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH17 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 17 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH18 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 18 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 ADC_CALFACT ADC_CALFACT ADC Calibration factor 0xb4 0x20 0x00000000 0xFFFFFFFF CALFACT Calibration factor These bits are written by hardware or by software. Once a calibration is complete,they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new calibration is launched. Just after a calibration is complete, DATA[6:0] contains the calibration factor. Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). Refer to SQ8[3:0] for a definition of channel selection. 0 7 read-write ADC_CCR ADC_CCR ADC common configuration register 0x308 0x20 0x00000000 0xFFFFFFFF PRESC ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). 18 4 read-write B_0x0 input ADC clock not divided 0x0 B_0x1 input ADC clock divided by 2 0x1 B_0x2 input ADC clock divided by 4 0x2 B_0x3 input ADC clock divided by 6 0x3 B_0x4 input ADC clock divided by 8 0x4 B_0x5 input ADC clock divided by 10 0x5 B_0x6 input ADC clock divided by 12 0x6 B_0x7 input ADC clock divided by 16 0x7 B_0x8 input ADC clock divided by 32 0x8 B_0x9 input ADC clock divided by 64 0x9 B_0xA input ADC clock divided by 128 0xA B_0xB input ADC clock divided by 256 0xB VREFEN VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 22 1 read-write B_0x0 VREFINT disabled 0x0 B_0x1 VREFINT enabled 0x1 TSEN Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 23 1 read-write B_0x0 Temperature sensor disabled 0x0 B_0x1 Temperature sensor enabled 0x1 VBATEN VBAT enable This bit is set and cleared by software to enable/disable the VBAT channel. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing) 24 1 read-write B_0x0 VBAT channel disabled 0x0 B_0x1 VBAT channel enabled 0x1 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register 0x0 0x20 write-only 0x00000000 KEY Key value (write only, read 0x0000) 0 16 PR PR Prescaler register 0x4 0x20 read-write 0x00000000 PR Prescaler divider 0 3 RLR RLR Reload register 0x8 0x20 read-write 0x00000FFF RL Watchdog counter reload value 0 12 SR SR Status register 0xC 0x20 read-only 0x00000000 WVU Watchdog counter window value update 2 1 RVU Watchdog counter reload value update 1 1 PVU Watchdog prescaler value update 0 1 WINR WINR Window register 0x10 0x20 read-write 0x00000FFF WIN Watchdog counter window value 0 12 HWCFGR HWCFGR hardware configuration register 0x3F0 0x20 read-write 0x00000071 WINDOW Support of Window function 0 4 PR_DEFAULT Prescaler default value 4 4 VERR VERR EXTI IP Version register 0x3F4 0x20 read-only 0x00000023 MINREV Minor Revision number 0 4 MAJREV Major Revision number 4 4 IPIDR IPIDR EXTI Identification register 0x3F8 0x20 read-only 0x00120041 IPID IP Identification 0 32 SIDR SIDR EXTI Size ID register 0x3FC 0x20 read-only 0xA3C5DD01 SID Size Identification 0 32 WWDG System window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window watchdog interrupt 0 CR CR Control register 0x0 0x20 read-write 0x0000007F WDGA Activation bit 7 1 T 7-bit counter (MSB to LSB) 0 7 CFR CFR Configuration register 0x4 0x20 read-write 0x0000007F WDGTB Timer base 11 3 EWI Early wakeup interrupt 9 1 W 7-bit window value 0 7 SR SR Status register 0x8 0x20 read-write 0x00000000 EWIF Early wakeup interrupt flag 0 1 FLASH Flash Flash 0x40022000 0x0 0x400 registers FLASH Flash global interrupt 3 ACR ACR Access control register 0x0 0x20 read-write 0x00000600 LATENCY Latency 0 3 PRFTEN Prefetch enable 8 1 ICEN Instruction cache enable 9 1 ICRST Instruction cache reset 11 1 EMPTY Flash User area empty 16 1 KEYR KEYR Flash key register 0x8 0x20 write-only 0x00000000 KEYR KEYR 0 32 OPTKEYR OPTKEYR Option byte key register 0xC 0x20 write-only 0x00000000 OPTKEYR Option byte key 0 32 SR SR Status register 0x10 0x20 read-write 0x00000000 EOP End of operation 0 1 OPERR Operation error 1 1 PROGERR Programming error 3 1 WRPERR Write protected error 4 1 PGAERR Programming alignment error 5 1 SIZERR Size error 6 1 PGSERR Programming sequence error 7 1 MISERR Fast programming data miss error 8 1 FASTERR Fast programming error 9 1 OPTVERR Option and Engineering bits loading validity error 15 1 BSY1 BSY1 16 1 BSY2 BSY2 17 1 CFGBSY Programming or erase configuration busy. 18 1 CR CR Flash control register 0x14 0x20 read-write 0xC0000000 PG Programming 0 1 PER Page erase 1 1 MER1 Mass erase 2 1 PNB Page number 3 10 BKER BKER 13 1 MER2 MER2 15 1 STRT Start 16 1 OPTSTRT Options modification start 17 1 FSTPG Fast programming 18 1 EOPIE End of operation interrupt enable 24 1 ERRIE Error interrupt enable 25 1 OBL_LAUNCH Force the option byte loading 27 1 OPTLOCK Options Lock 30 1 LOCK FLASH_CR Lock 31 1 ECCR ECCR Flash ECC register 0x18 0x20 0x00000000 ADDR_ECC ECC fail address 0 14 read-only SYSF_ECC ECC fail for Corrected ECC Error or Double ECC Error in info block 20 1 read-only ECCIE ECC correction interrupt enable 24 1 read-write ECCC ECC correction 30 1 read-write ECCD ECC detection 31 1 read-write OPTR OPTR Flash option register 0x20 0x20 read-write 0xF0000000 RDP Read protection level 0 8 nRST_STOP nRST_STOP 13 1 nRST_STDBY nRST_STDBY 14 1 IDWG_SW Independent watchdog selection 16 1 IWDG_STOP Independent watchdog counter freeze in Stop mode 17 1 IWDG_STDBY Independent watchdog counter freeze in Standby mode 18 1 WWDG_SW Window watchdog selection 19 1 nSWAP_BANK nSWAP_BANK 20 1 DUAL_BANK DUAL_BANK 21 1 RAM_PARITY_CHECK SRAM parity check control 22 1 nBOOT_SEL nBOOT_SEL 24 1 nBOOT1 Boot configuration 25 1 nBOOT0 nBOOT0 option bit 26 1 WRP1AR WRP1AR Flash WRP area A address register 0x2C 0x20 read-only 0xF0000000 WRP1A_STRT WRP area A start offset 0 7 WRP1A_END WRP area A end offset 16 7 WRP1BR WRP1BR Flash WRP area B address register 0x30 0x20 read-only 0xF0000000 WRP1B_STRT WRP area B start offset 0 7 WRP1B_END WRP area B end offset 16 7 WRP2AR WRP2AR FLASH WRP2 area A address register 0x4C 0x20 read-write 0x00000000 WRP2A_STRT WRP2A_STRT 0 7 WRP2A_END WRP2A_END 16 7 WRP2BR WRP2BR FLASH WRP2 area B address register 0x50 0x20 read-write 0x00000000 WRP2B_STRT WRP2B_STRT 0 7 WRP2B_END WRP2B_END 16 7 DBG Debug support DBG 0x40015800 0x0 0x400 registers IDCODE IDCODE MCU Device ID Code Register 0x0 0x20 read-only 0x0 DEV_ID Device Identifier 0 16 REV_ID Revision Identifier 16 16 CR CR Debug MCU Configuration Register 0x4 0x20 read-write 0x0 DBG_STOP Debug Stop Mode 1 1 DBG_STANDBY Debug Standby Mode 2 1 APB_FZ1 APB_FZ1 DBG APB freeze register 1 0x8 0x20 read-write 0x0 DBG_TIMER2_STOP Debug Timer 2 stopped when Core is halted 0 1 DBG_TIM3_STOP TIM3 counter stopped when core is halted 1 1 DBG_TIMER6_STOP Debug Timer 6 stopped when Core is halted 4 1 DBG_TIM7_STOP TIM7 counter stopped when core is halted 5 1 DBG_RTC_STOP Debug RTC stopped when Core is halted 10 1 DBG_WWDG_STOP Debug Window Wachdog stopped when Core is halted 11 1 DBG_IWDG_STOP Debug Independent Wachdog stopped when Core is halted 12 1 DBG_I2C1_STOP I2C1 SMBUS timeout mode stopped when core is halted 21 1 DBG_LPTIM2_STOP Clocking of LPTIMER2 counter when the core is halted 30 1 DBG_LPTIM1_STOP Clocking of LPTIMER1 counter when the core is halted 31 1 APB_FZ2 APB_FZ2 DBG APB freeze register 2 0xC 0x20 read-write 0x0 DBG_TIM1_STOP DBG_TIM1_STOP 11 1 DBG_TIM14_STOP DBG_TIM14_STOP 15 1 DBG_TIM15_STOP DBG_TIM15_STOP 16 1 DBG_TIM16_STOP DBG_TIM16_STOP 17 1 DBG_TIM17_STOP DBG_TIM17_STOP 18 1 RCC Reset and clock control RCC 0x40021000 0x0 0x400 registers RCC RCC global interrupt 4 CR CR Clock control register 0x0 0x20 read-write 0x00000063 HSION HSI16 clock enable 8 1 HSIKERON HSI16 always enable for peripheral kernels 9 1 HSIRDY HSI16 clock ready flag 10 1 HSIDIV HSI16 clock division factor 11 3 HSEON HSE clock enable 16 1 HSERDY HSE clock ready flag 17 1 HSEBYP HSE crystal oscillator bypass 18 1 CSSON Clock security system enable 19 1 PLLON PLL enable 24 1 PLLRDY PLL clock ready flag 25 1 ICSCR ICSCR Internal clock sources calibration register 0x4 0x20 0x10000000 HSICAL HSI16 clock calibration 0 8 read-only HSITRIM HSI16 clock trimming 8 7 read-write CFGR CFGR Clock configuration register 0x8 0x20 0x00000000 MCOPRE Microcontroller clock output prescaler 28 4 read-only MCOSEL Microcontroller clock output 24 4 read-write MCO2PRE MCO2PRE 20 4 read-write MCO2SEL MCO2SEL 16 4 read-write PPRE APB prescaler 12 3 read-write HPRE AHB prescaler 8 4 read-write SWS System clock switch status 3 3 read-only SW System clock switch 0 3 read-write PLLSYSCFGR PLLSYSCFGR PLL configuration register 0xC 0x20 read-write 0x00001000 PLLSRC PLL input clock source 0 2 PLLM Division factor M of the PLL input clock divider 4 3 PLLN PLL frequency multiplication factor N 8 8 PLLPEN PLLPCLK clock output enable 16 1 PLLP PLL VCO division factor P for PLLPCLK clock output 17 5 PLLQEN PLLQCLK clock output enable 24 1 PLLQ PLL VCO division factor Q for PLLQCLK clock output 25 3 PLLREN PLLRCLK clock output enable 28 1 PLLR PLL VCO division factor R for PLLRCLK clock output 29 3 CIER CIER Clock interrupt enable register 0x18 0x20 read-write 0x00000000 LSIRDYIE LSI ready interrupt enable 0 1 LSERDYIE LSE ready interrupt enable 1 1 HSIRDYIE HSI ready interrupt enable 3 1 HSERDYIE HSE ready interrupt enable 4 1 PLLSYSRDYIE PLL ready interrupt enable 5 1 CIFR CIFR Clock interrupt flag register 0x1C 0x20 read-only 0x00000000 LSIRDYF LSI ready interrupt flag 0 1 LSERDYF LSE ready interrupt flag 1 1 HSIRDYF HSI ready interrupt flag 3 1 HSERDYF HSE ready interrupt flag 4 1 PLLSYSRDYF PLL ready interrupt flag 5 1 CSSF Clock security system interrupt flag 8 1 LSECSSF LSE Clock security system interrupt flag 9 1 CICR CICR Clock interrupt clear register 0x20 0x20 write-only 0x00000000 LSIRDYC LSI ready interrupt clear 0 1 LSERDYC LSE ready interrupt clear 1 1 HSIRDYC HSI ready interrupt clear 3 1 HSERDYC HSE ready interrupt clear 4 1 PLLSYSRDYC PLL ready interrupt clear 5 1 CSSC Clock security system interrupt clear 8 1 LSECSSC LSE Clock security system interrupt clear 9 1 IOPRSTR IOPRSTR I/O port reset register 0x24 0x20 read-write 0x00000000 GPIOARST GPIOARST 0 1 GPIOBRST GPIOBRST 1 1 GPIOCRST GPIOCRST 2 1 GPIODRST GPIODRST 3 1 GPIOERST GPIOERST 4 1 GPIOFRST GPIOFRST 5 1 AHBRSTR AHBRSTR AHB peripheral reset register 0x28 0x20 read-write 0x00000000 DMA1RST DMA1 reset 0 1 DMA2RST DMA1 reset 1 1 FLASHRST FLITF reset 8 1 CRCRST CRC reset 12 1 APBRSTR1 APBRSTR1 APB peripheral reset register 1 0x2C 0x20 read-write 0x00000000 TIM3RST TIM3 timer reset 1 1 TIM4RST TIM4 timer reset 2 1 TIM6RST TIM6 timer reset 4 1 TIM7RST TIM7 timer reset 5 1 USART5RST USART5RST 8 1 USART6RST USART6RST 9 1 USBRST USBRST 13 1 SPI2RST SPI2 reset 14 1 SPI3RST SPI3 reset 15 1 USART2RST USART2 reset 17 1 USART3RST USART3 reset 18 1 USART4RST USART4 reset 19 1 I2C1RST I2C1 reset 21 1 I2C2RST I2C2 reset 22 1 I2C3RST I2C3RST reset 23 1 DBGRST Debug support reset 27 1 PWRRST Power interface reset 28 1 APBRSTR2 APBRSTR2 APB peripheral reset register 2 0x30 0x20 read-write 0x00000000 SYSCFGRST SYSCFG, COMP and VREFBUF reset 0 1 TIM1RST TIM1 timer reset 11 1 SPI1RST SPI1 reset 12 1 USART1RST USART1 reset 14 1 TIM14RST TIM14 timer reset 15 1 TIM15RST TIM15 timer reset 16 1 TIM16RST TIM16 timer reset 17 1 TIM17RST TIM17 timer reset 18 1 ADCRST ADC reset 20 1 IOPENR IOPENR GPIO clock enable register 0x34 0x20 read-write 0x00000000 GPIOAEN I/O port A clock enable during Sleep mode 0 1 GPIOBEN I/O port B clock enable during Sleep mode 1 1 GPIOCEN I/O port C clock enable during Sleep mode 2 1 GPIODEN I/O port D clock enable during Sleep mode 3 1 GPIOEEN I/O port E clock enable during Sleep mode 4 1 GPIOFEN I/O port F clock enable during Sleep mode 5 1 AHBENR AHBENR AHB peripheral clock enable register 0x38 0x20 read-write 0x00000100 DMA1EN DMA1 clock enable 0 1 DMA2EN DMA2 clock enable 1 1 FLASHEN Flash memory interface clock enable 8 1 CRCEN CRC clock enable 12 1 APBENR1 APBENR1 APB peripheral clock enable register 1 0x3C 0x20 read-write 0x00000000 TIM3EN TIM3 timer clock enable 1 1 TIM4EN TIM4 timer clock enable 2 1 TIM6EN TIM6 timer clock enable 4 1 TIM7EN TIM7 timer clock enable 5 1 USART5EN USART5EN 8 1 USART6EN USART6EN 9 1 RTCAPBEN RTC APB clock enable 10 1 WWDGEN WWDG clock enable 11 1 USBEN USBEN 13 1 SPI2EN SPI2 clock enable 14 1 SPI3EN SPI3 clock enable 15 1 USART2EN USART2 clock enable 17 1 USART3EN USART3 clock enable 18 1 USART4EN USART4 clock enable 19 1 I2C1EN I2C1 clock enable 21 1 I2C2EN I2C2 clock enable 22 1 I2C3EN I2C3 clock enable 23 1 DBGEN Debug support clock enable 27 1 PWREN Power interface clock enable 28 1 APBENR2 APBENR2 APB peripheral clock enable register 2 0x40 0x20 read-write 0x00000000 SYSCFGEN SYSCFG, COMP and VREFBUF clock enable 0 1 TIM1EN TIM1 timer clock enable 11 1 SPI1EN SPI1 clock enable 12 1 USART1EN USART1 clock enable 14 1 TIM14EN TIM14 timer clock enable 15 1 TIM15EN TIM15 timer clock enable 16 1 TIM16EN TIM16 timer clock enable 17 1 TIM17EN TIM16 timer clock enable 18 1 ADCEN ADC clock enable 20 1 IOPSMENR IOPSMENR GPIO in Sleep mode clock enable register 0x44 0x20 read-write 0x0000003F GPIOASMEN I/O port A clock enable during Sleep mode 0 1 GPIOBSMEN I/O port B clock enable during Sleep mode 1 1 GPIOCSMEN I/O port C clock enable during Sleep mode 2 1 GPIODSMEN I/O port D clock enable during Sleep mode 3 1 GPIOESMEN I/O port E clock enable during Sleep mode 4 1 GPIOFSMEN I/O port F clock enable during Sleep mode 5 1 AHBSMENR AHBSMENR AHB peripheral clock enable in Sleep mode register 0x48 0x20 read-write 0x00051303 DMA1SMEN DMA1 clock enable during Sleep mode 0 1 DMA2SMEN DMA2 clock enable during Sleep mode 1 1 FLASHSMEN Flash memory interface clock enable during Sleep mode 8 1 SRAMSMEN SRAM clock enable during Sleep mode 9 1 CRCSMEN CRC clock enable during Sleep mode 12 1 APBSMENR1 APBSMENR1 APB peripheral clock enable in Sleep mode register 1 0x4C 0x20 read-write 0xFFFFFFB7 TIM3SMEN TIM3 timer clock enable during Sleep mode 1 1 TIM4SMEN TIM4 timer clock enable during Sleep mode 2 1 TIM6SMEN TIM6 timer clock enable during Sleep mode 4 1 TIM7SMEN TIM7 timer clock enable during Sleep mode 5 1 USART5SMEN USART5 clock enable 8 1 USART6SMEN USART6 clock enable 9 1 RTCAPBSMEN RTC APB clock enable during Sleep mode 10 1 WWDGSMEN WWDG clock enable during Sleep mode 11 1 USBSMEN USB clock enable during Sleep mode 13 1 SPI2SMEN SPI2 clock enable during Sleep mode 14 1 SPI3SMEN SPI3 clock enable during Sleep mode 15 1 USART2SMEN USART2 clock enable during Sleep mode 17 1 USART3SMEN USART3 clock enable during Sleep mode 18 1 USART4SMEN USART4 clock enable during Sleep mode 19 1 I2C1SMEN I2C1 clock enable during Sleep mode 21 1 I2C2SMEN I2C2 clock enable during Sleep mode 22 1 I2C3SMEN I2C3 clock enable during Sleep mode 23 1 DBGSMEN Debug support clock enable during Sleep mode 27 1 PWRSMEN Power interface clock enable during Sleep mode 28 1 APBSMENR2 APBSMENR2 APB peripheral clock enable in Sleep mode register 2 0x50 0x20 read-write 0x0017D801 SYSCFGSMEN SYSCFG, COMP and VREFBUF clock enable during Sleep mode 0 1 TIM1SMEN TIM1 timer clock enable during Sleep mode 11 1 SPI1SMEN SPI1 clock enable during Sleep mode 12 1 USART1SMEN USART1 clock enable during Sleep mode 14 1 TIM14SMEN TIM14 timer clock enable during Sleep mode 15 1 TIM15SMEN TIM15 timer clock enable during Sleep mode 16 1 TIM16SMEN TIM16 timer clock enable during Sleep mode 17 1 TIM17SMEN TIM16 timer clock enable during Sleep mode 18 1 ADCSMEN ADC clock enable during Sleep mode 20 1 CCIPR CCIPR Peripherals independent clock configuration register 0x54 0x20 read-write 0x00000000 USART1SEL USART1 clock source selection 0 2 USART2SEL USART2 clock source selection 2 2 USART3SEL USART3 clock source selection 4 2 I2C1SEL I2C1 clock source selection 12 2 I2S2SEL I2S1 clock source selection 14 2 TIM1SEL TIM1 clock source selection 22 1 TIM15SEL TIM15 clock source selection 24 1 ADCSEL ADCs clock source selection 30 2 CCIPR2 CCIPR2 Peripherals independent clock configuration register 2 0x58 0x20 read-write 0x00000000 I2S1SEL 2S1SEL 0 2 I2S2SEL I2S2SEL 2 2 USBSEL USBSEL 12 2 BDCR BDCR RTC domain control register 0x5C 0x20 read-write 0x00000000 LSEON LSE oscillator enable 0 1 LSERDY LSE oscillator ready 1 1 read-only LSEBYP LSE oscillator bypass 2 1 LSEDRV LSE oscillator drive capability 3 2 LSECSSON CSS on LSE enable 5 1 LSECSSD CSS on LSE failure Detection 6 1 read-only RTCSEL RTC clock source selection 8 2 RTCEN RTC clock enable 15 1 BDRST RTC domain software reset 16 1 LSCOEN Low-speed clock output (LSCO) enable 24 1 LSCOSEL Low-speed clock output selection 25 1 CSR CSR Control/status register 0x60 0x20 read-write 0x00000000 LSION LSI oscillator enable 0 1 LSIRDY LSI oscillator ready 1 1 read-only RMVF Remove reset flags 23 1 OBLRSTF Option byte loader reset flag 25 1 read-only PINRSTF Pin reset flag 26 1 read-only PWRRSTF BOR or POR/PDR flag 27 1 read-only SFTRSTF Software reset flag 28 1 read-only IWDGRSTF Independent window watchdog reset flag 29 1 read-only WWDGRSTF Window watchdog reset flag 30 1 read-only LPWRRSTF Low-power reset flag 31 1 read-only PWR Power control PWR 0x40007000 0x0 0x400 registers CR1 CR1 Power control register 1 0x0 0x20 read-write 0x00000208 LPR Low-power run 14 1 VOS Voltage scaling range selection 9 2 DBP Disable backup domain write protection 8 1 FPD_LPSLP Flash memory powered down during Low-power sleep mode 5 1 FPD_LPRUN Flash memory powered down during Low-power run mode 4 1 FPD_STOP Flash memory powered down during Stop mode 3 1 LPMS Low-power mode selection 0 3 CR2 CR2 Power control register 2 0x4 0x20 read-write 0x00000000 USV USV 10 1 CR3 CR3 Power control register 3 0x8 0x20 read-write 0X00008000 EWUP1 Enable Wakeup pin WKUP1 0 1 EWUP2 Enable Wakeup pin WKUP2 1 1 EWUP3 Enable Wakeup pin WKUP3 2 1 EWUP4 Enable Wakeup pin WKUP4 3 1 EWUP5 Enable WKUP5 wakeup pin 4 1 EWUP6 Enable WKUP6 wakeup pin 5 1 APC Apply pull-up and pull-down configuration 10 1 EIWUL Enable internal wakeup line 15 1 CR4 CR4 Power control register 4 0xC 0x20 read-write 0x00000000 WP1 Wakeup pin WKUP1 polarity 0 1 WP2 Wakeup pin WKUP2 polarity 1 1 WP3 Wakeup pin WKUP3 polarity 2 1 WP4 Wakeup pin WKUP4 polarity 3 1 WP5 Wakeup pin WKUP5 polarity 4 1 WP6 WKUP6 wakeup pin polarity 5 1 VBE VBAT battery charging enable 8 1 VBRS VBAT battery charging resistor selection 9 1 SR1 SR1 Power status register 1 0x10 0x20 read-only 0x00000000 WUF1 Wakeup flag 1 0 1 WUF2 Wakeup flag 2 1 1 WUF3 Wakeup flag 3 2 1 WUF4 Wakeup flag 4 3 1 WUF5 Wakeup flag 5 4 1 WUF6 Wakeup flag 6 5 1 SBF Standby flag 8 1 WUFI Wakeup flag internal 15 1 SR2 SR2 Power status register 2 0x14 0x20 read-only 0x00000000 VOSF Voltage scaling flag 10 1 REGLPF Low-power regulator flag 9 1 REGLPS Low-power regulator started 8 1 FLASH_RDY Flash ready flag 7 1 SCR SCR Power status clear register 0x18 0x20 write-only 0x00000000 CSBF Clear standby flag 8 1 CWUF6 Clear wakeup flag 6 5 1 CWUF5 Clear wakeup flag 5 4 1 CWUF4 Clear wakeup flag 4 3 1 CWUF3 Clear wakeup flag 3 2 1 CWUF2 Clear wakeup flag 2 1 1 CWUF1 Clear wakeup flag 1 0 1 PUCRA PUCRA Power Port A pull-up control register 0x20 0x20 read-write 0x00000000 PU15 Port A pull-up bit y (y=0..15) 15 1 PU14 Port A pull-up bit y (y=0..15) 14 1 PU13 Port A pull-up bit y (y=0..15) 13 1 PU12 Port A pull-up bit y (y=0..15) 12 1 PU11 Port A pull-up bit y (y=0..15) 11 1 PU10 Port A pull-up bit y (y=0..15) 10 1 PU9 Port A pull-up bit y (y=0..15) 9 1 PU8 Port A pull-up bit y (y=0..15) 8 1 PU7 Port A pull-up bit y (y=0..15) 7 1 PU6 Port A pull-up bit y (y=0..15) 6 1 PU5 Port A pull-up bit y (y=0..15) 5 1 PU4 Port A pull-up bit y (y=0..15) 4 1 PU3 Port A pull-up bit y (y=0..15) 3 1 PU2 Port A pull-up bit y (y=0..15) 2 1 PU1 Port A pull-up bit y (y=0..15) 1 1 PU0 Port A pull-up bit y (y=0..15) 0 1 PDCRA PDCRA Power Port A pull-down control register 0x24 0x20 read-write 0x00000000 PD15 Port A pull-down bit y (y=0..15) 15 1 PD14 Port A pull-down bit y (y=0..15) 14 1 PD13 Port A pull-down bit y (y=0..15) 13 1 PD12 Port A pull-down bit y (y=0..15) 12 1 PD11 Port A pull-down bit y (y=0..15) 11 1 PD10 Port A pull-down bit y (y=0..15) 10 1 PD9 Port A pull-down bit y (y=0..15) 9 1 PD8 Port A pull-down bit y (y=0..15) 8 1 PD7 Port A pull-down bit y (y=0..15) 7 1 PD6 Port A pull-down bit y (y=0..15) 6 1 PD5 Port A pull-down bit y (y=0..15) 5 1 PD4 Port A pull-down bit y (y=0..15) 4 1 PD3 Port A pull-down bit y (y=0..15) 3 1 PD2 Port A pull-down bit y (y=0..15) 2 1 PD1 Port A pull-down bit y (y=0..15) 1 1 PD0 Port A pull-down bit y (y=0..15) 0 1 PUCRB PUCRB Power Port B pull-up control register 0x28 0x20 read-write 0x00000000 PU15 Port B pull-up bit y (y=0..15) 15 1 PU14 Port B pull-up bit y (y=0..15) 14 1 PU13 Port B pull-up bit y (y=0..15) 13 1 PU12 Port B pull-up bit y (y=0..15) 12 1 PU11 Port B pull-up bit y (y=0..15) 11 1 PU10 Port B pull-up bit y (y=0..15) 10 1 PU9 Port B pull-up bit y (y=0..15) 9 1 PU8 Port B pull-up bit y (y=0..15) 8 1 PU7 Port B pull-up bit y (y=0..15) 7 1 PU6 Port B pull-up bit y (y=0..15) 6 1 PU5 Port B pull-up bit y (y=0..15) 5 1 PU4 Port B pull-up bit y (y=0..15) 4 1 PU3 Port B pull-up bit y (y=0..15) 3 1 PU2 Port B pull-up bit y (y=0..15) 2 1 PU1 Port B pull-up bit y (y=0..15) 1 1 PU0 Port B pull-up bit y (y=0..15) 0 1 PDCRB PDCRB Power Port B pull-down control register 0x2C 0x20 read-write 0x00000000 PD15 Port B pull-down bit y (y=0..15) 15 1 PD14 Port B pull-down bit y (y=0..15) 14 1 PD13 Port B pull-down bit y (y=0..15) 13 1 PD12 Port B pull-down bit y (y=0..15) 12 1 PD11 Port B pull-down bit y (y=0..15) 11 1 PD10 Port B pull-down bit y (y=0..15) 10 1 PD9 Port B pull-down bit y (y=0..15) 9 1 PD8 Port B pull-down bit y (y=0..15) 8 1 PD7 Port B pull-down bit y (y=0..15) 7 1 PD6 Port B pull-down bit y (y=0..15) 6 1 PD5 Port B pull-down bit y (y=0..15) 5 1 PD4 Port B pull-down bit y (y=0..15) 4 1 PD3 Port B pull-down bit y (y=0..15) 3 1 PD2 Port B pull-down bit y (y=0..15) 2 1 PD1 Port B pull-down bit y (y=0..15) 1 1 PD0 Port B pull-down bit y (y=0..15) 0 1 PUCRC PUCRC Power Port C pull-up control register 0x30 0x20 read-write 0x00000000 PU15 Port C pull-up bit y (y=0..15) 15 1 PU14 Port C pull-up bit y (y=0..15) 14 1 PU13 Port C pull-up bit y (y=0..15) 13 1 PU12 Port C pull-up bit y (y=0..15) 12 1 PU11 Port C pull-up bit y (y=0..15) 11 1 PU10 Port C pull-up bit y (y=0..15) 10 1 PU9 Port C pull-up bit y (y=0..15) 9 1 PU8 Port C pull-up bit y (y=0..15) 8 1 PU7 Port C pull-up bit y (y=0..15) 7 1 PU6 Port C pull-up bit y (y=0..15) 6 1 PU5 Port C pull-up bit y (y=0..15) 5 1 PU4 Port C pull-up bit y (y=0..15) 4 1 PU3 Port C pull-up bit y (y=0..15) 3 1 PU2 Port C pull-up bit y (y=0..15) 2 1 PU1 Port C pull-up bit y (y=0..15) 1 1 PU0 Port C pull-up bit y (y=0..15) 0 1 PDCRC PDCRC Power Port C pull-down control register 0x34 0x20 read-write 0x00000000 PD15 Port C pull-down bit y (y=0..15) 15 1 PD14 Port C pull-down bit y (y=0..15) 14 1 PD13 Port C pull-down bit y (y=0..15) 13 1 PD12 Port C pull-down bit y (y=0..15) 12 1 PD11 Port C pull-down bit y (y=0..15) 11 1 PD10 Port C pull-down bit y (y=0..15) 10 1 PD9 Port C pull-down bit y (y=0..15) 9 1 PD8 Port C pull-down bit y (y=0..15) 8 1 PD7 Port C pull-down bit y (y=0..15) 7 1 PD6 Port C pull-down bit y (y=0..15) 6 1 PD5 Port C pull-down bit y (y=0..15) 5 1 PD4 Port C pull-down bit y (y=0..15) 4 1 PD3 Port C pull-down bit y (y=0..15) 3 1 PD2 Port C pull-down bit y (y=0..15) 2 1 PD1 Port C pull-down bit y (y=0..15) 1 1 PD0 Port C pull-down bit y (y=0..15) 0 1 PUCRD PUCRD Power Port D pull-up control register 0x38 0x20 read-write 0x00000000 PU15 Port D pull-up bit y (y=0..15) 15 1 PU14 Port D pull-up bit y (y=0..15) 14 1 PU13 Port D pull-up bit y (y=0..15) 13 1 PU12 Port D pull-up bit y (y=0..15) 12 1 PU11 Port D pull-up bit y (y=0..15) 11 1 PU10 Port D pull-up bit y (y=0..15) 10 1 PU9 Port D pull-up bit y (y=0..15) 9 1 PU8 Port D pull-up bit y (y=0..15) 8 1 PU7 Port D pull-up bit y (y=0..15) 7 1 PU6 Port D pull-up bit y (y=0..15) 6 1 PU5 Port D pull-up bit y (y=0..15) 5 1 PU4 Port D pull-up bit y (y=0..15) 4 1 PU3 Port D pull-up bit y (y=0..15) 3 1 PU2 Port D pull-up bit y (y=0..15) 2 1 PU1 Port D pull-up bit y (y=0..15) 1 1 PU0 Port D pull-up bit y (y=0..15) 0 1 PDCRD PDCRD Power Port D pull-down control register 0x3C 0x20 read-write 0x00000000 PD15 Port D pull-down bit y (y=0..15) 15 1 PD14 Port D pull-down bit y (y=0..15) 14 1 PD13 Port D pull-down bit y (y=0..15) 13 1 PD12 Port D pull-down bit y (y=0..15) 12 1 PD11 Port D pull-down bit y (y=0..15) 11 1 PD10 Port D pull-down bit y (y=0..15) 10 1 PD9 Port D pull-down bit y (y=0..15) 9 1 PD8 Port D pull-down bit y (y=0..15) 8 1 PD7 Port D pull-down bit y (y=0..15) 7 1 PD6 Port D pull-down bit y (y=0..15) 6 1 PD5 Port D pull-down bit y (y=0..15) 5 1 PD4 Port D pull-down bit y (y=0..15) 4 1 PD3 Port D pull-down bit y (y=0..15) 3 1 PD2 Port D pull-down bit y (y=0..15) 2 1 PD1 Port D pull-down bit y (y=0..15) 1 1 PD0 Port D pull-down bit y (y=0..15) 0 1 PUCRE PUCRE Power Port E pull-UP control register 0x40 0x20 read-write 0x00000000 PU15 Port E pull-up bit y (y=0..15) 15 1 PU14 Port E pull-up bit y (y=0..15) 14 1 PU13 Port E pull-up bit y (y=0..15) 13 1 PU12 Port E pull-up bit y (y=0..15) 12 1 PU11 Port E pull-up bit y (y=0..15) 11 1 PU10 Port E pull-up bit y (y=0..15) 10 1 PU9 Port E pull-up bit y (y=0..15) 9 1 PU8 Port E pull-up bit y (y=0..15) 8 1 PU7 Port E pull-up bit y (y=0..15) 7 1 PU6 Port E pull-up bit y (y=0..15) 6 1 PU5 Port E pull-up bit y (y=0..15) 5 1 PU4 Port E pull-up bit y (y=0..15) 4 1 PU3 Port E pull-up bit y (y=0..15) 3 1 PU2 Port E pull-up bit y (y=0..15) 2 1 PU1 Port E pull-up bit y (y=0..15) 1 1 PU0 Port E pull-up bit y (y=0..15) 0 1 PDCRE PDCRE Power Port E pull-down control register 0x44 0x20 read-write 0x00000000 PD15 Port E pull-down bit y (y=0..15) 15 1 PD14 Port E pull-down bit y (y=0..15) 14 1 PD13 Port E pull-down bit y (y=0..15) 13 1 PD12 Port E pull-down bit y (y=0..15) 12 1 PD11 Port E pull-down bit y (y=0..15) 11 1 PD10 Port E pull-down bit y (y=0..15) 10 1 PD9 Port E pull-down bit y (y=0..15) 9 1 PD8 Port E pull-down bit y (y=0..15) 8 1 PD7 Port E pull-down bit y (y=0..15) 7 1 PD6 Port E pull-down bit y (y=0..15) 6 1 PD5 Port E pull-down bit y (y=0..15) 5 1 PD4 Port E pull-down bit y (y=0..15) 4 1 PD3 Port E pull-down bit y (y=0..15) 3 1 PD2 Port E pull-down bit y (y=0..15) 2 1 PD1 Port E pull-down bit y (y=0..15) 1 1 PD0 Port E pull-down bit y (y=0..15) 0 1 PUCRF PUCRF Power Port F pull-up control register 0x48 0x20 read-write 0x00000000 PU13 Port F pull-up bit y (y=0..15) 13 1 PU12 Port F pull-up bit y (y=0..15) 12 1 PU11 Port F pull-up bit y (y=0..15) 11 1 PU10 Port F pull-up bit y (y=0..15) 10 1 PU9 Port F pull-up bit y (y=0..15) 9 1 PU8 Port F pull-up bit y (y=0..15) 8 1 PU7 Port F pull-up bit y (y=0..15) 7 1 PU6 Port F pull-up bit y (y=0..15) 6 1 PU5 Port F pull-up bit y (y=0..15) 5 1 PU4 Port F pull-up bit y (y=0..15) 4 1 PU3 Port F pull-up bit y (y=0..15) 3 1 PU2 Port F pull-up bit y (y=0..15) 2 1 PU1 Port F pull-up bit y (y=0..15) 1 1 PU0 Port F pull-up bit y (y=0..15) 0 1 PDCRF PDCRF Power Port F pull-down control register 0x4C 0x20 read-write 0x00000000 PD13 Port F pull-down bit y (y=0..15) 13 1 PD12 Port F pull-down bit y (y=0..15) 12 1 PD11 Port F pull-down bit y (y=0..15) 11 1 PD10 Port F pull-down bit y (y=0..15) 10 1 PD9 Port F pull-down bit y (y=0..15) 9 1 PD8 Port F pull-down bit y (y=0..15) 8 1 PD7 Port F pull-down bit y (y=0..15) 7 1 PD6 Port F pull-down bit y (y=0..15) 6 1 PD5 Port F pull-down bit y (y=0..15) 5 1 PD4 Port F pull-down bit y (y=0..15) 4 1 PD3 Port F pull-down bit y (y=0..15) 3 1 PD2 Port F pull-down bit y (y=0..15) 2 1 PD1 Port F pull-down bit y (y=0..15) 1 1 PD0 Port F pull-down bit y (y=0..15) 0 1 DMA DMA controller DMA 0x40020000 0x0 0x400 registers DMA_Channel1 DMA channel 1 interrupt 9 DMA_Channel2_3 DMA channel 2 and 3 interrupts 10 DMA_ISR DMA_ISR DMA interrupt status register 0x0 0x20 0x00000000 0xFFFFFFFF GIF1 global interrupt flag for channel 1 0 1 read-only B_0x0 no TE, HT or TC event 0x0 B_0x1 a TE, HT or TC event occurred 0x1 TCIF1 transfer complete (TC) flag for channel 1 1 1 read-only B_0x0 no TC event 0x0 B_0x1 a TC event occurred 0x1 HTIF1 half transfer (HT) flag for channel 1 2 1 read-only B_0x0 no HT event 0x0 B_0x1 a HT event occurred 0x1 TEIF1 transfer error (TE) flag for channel 1 3 1 read-only B_0x0 no TE event 0x0 B_0x1 a TE event occurred 0x1 GIF2 global interrupt flag for channel 2 4 1 read-only B_0x0 no TE, HT or TC event 0x0 B_0x1 a TE, HT or TC event occurred 0x1 TCIF2 transfer complete (TC) flag for channel 2 5 1 read-only B_0x0 no TC event 0x0 B_0x1 a TC event occurred 0x1 HTIF2 half transfer (HT) flag for channel 2 6 1 read-only B_0x0 no HT event 0x0 B_0x1 a HT event occurred 0x1 TEIF2 transfer error (TE) flag for channel 2 7 1 read-only B_0x0 no TE event 0x0 B_0x1 a TE event occurred 0x1 GIF3 global interrupt flag for channel 3 8 1 read-only B_0x0 no TE, HT or TC event 0x0 B_0x1 a TE, HT or TC event occurred 0x1 TCIF3 transfer complete (TC) flag for channel 3 9 1 read-only B_0x0 no TC event 0x0 B_0x1 a TC event occurred 0x1 HTIF3 half transfer (HT) flag for channel 3 10 1 read-only B_0x0 no HT event 0x0 B_0x1 a HT event occurred 0x1 TEIF3 transfer error (TE) flag for channel 3 11 1 read-only B_0x0 no TE event 0x0 B_0x1 a TE event occurred 0x1 GIF4 global interrupt flag for channel 4 12 1 read-only B_0x0 no TE, HT or TC event 0x0 B_0x1 a TE, HT or TC event occurred 0x1 TCIF4 transfer complete (TC) flag for channel 4 13 1 read-only B_0x0 no TC event 0x0 B_0x1 a TC event occurred 0x1 HTIF4 half transfer (HT) flag for channel 4 14 1 read-only B_0x0 no HT event 0x0 B_0x1 a HT event occurred 0x1 TEIF4 transfer error (TE) flag for channel 4 15 1 read-only B_0x0 no TE event 0x0 B_0x1 a TE event occurred 0x1 GIF5 global interrupt flag for channel 5 16 1 read-only B_0x0 no TE, HT or TC event 0x0 B_0x1 a TE, HT or TC event occurred 0x1 TCIF5 transfer complete (TC) flag for channel 5 17 1 read-only B_0x0 no TC event 0x0 B_0x1 a TC event occurred 0x1 HTIF5 half transfer (HT) flag for channel 5 18 1 read-only B_0x0 no HT event 0x0 B_0x1 a HT event occurred 0x1 TEIF5 transfer error (TE) flag for channel 5 19 1 read-only B_0x0 no TE event 0x0 B_0x1 a TE event occurred 0x1 GIF6 global interrupt flag for channel 6 20 1 read-only B_0x0 no TE, HT or TC event 0x0 B_0x1 a TE, HT or TC event occurred 0x1 TCIF6 transfer complete (TC) flag for channel 6 21 1 read-only B_0x0 no TC event 0x0 B_0x1 a TC event occurred 0x1 HTIF6 half transfer (HT) flag for channel 6 22 1 read-only B_0x0 no HT event 0x0 B_0x1 a HT event occurred 0x1 TEIF6 transfer error (TE) flag for channel 6 23 1 read-only B_0x0 no TE event 0x0 B_0x1 a TE event occurred 0x1 GIF7 global interrupt flag for channel 7 24 1 read-only B_0x0 no TE, HT or TC event 0x0 B_0x1 a TE, HT or TC event occurred 0x1 TCIF7 transfer complete (TC) flag for channel 7 25 1 read-only B_0x0 no TC event 0x0 B_0x1 a TC event occurred 0x1 HTIF7 half transfer (HT) flag for channel 7 26 1 read-only B_0x0 no HT event 0x0 B_0x1 a HT event occurred 0x1 TEIF7 transfer error (TE) flag for channel 7 27 1 read-only B_0x0 no TE event 0x0 B_0x1 a TE event occurred 0x1 DMA_IFCR DMA_IFCR DMA interrupt flag clear register 0x4 0x20 0x00000000 0xFFFFFFFF CGIF1 global interrupt flag clear for channel 1 0 1 write-only CTCIF1 transfer complete flag clear for channel 1 1 1 write-only CHTIF1 half transfer flag clear for channel 1 2 1 write-only CTEIF1 transfer error flag clear for channel 1 3 1 write-only CGIF2 global interrupt flag clear for channel 2 4 1 write-only CTCIF2 transfer complete flag clear for channel 2 5 1 write-only CHTIF2 half transfer flag clear for channel 2 6 1 write-only CTEIF2 transfer error flag clear for channel 2 7 1 write-only CGIF3 global interrupt flag clear for channel 3 8 1 write-only CTCIF3 transfer complete flag clear for channel 3 9 1 write-only CHTIF3 half transfer flag clear for channel 3 10 1 write-only CTEIF3 transfer error flag clear for channel 3 11 1 write-only CGIF4 global interrupt flag clear for channel 4 12 1 write-only CTCIF4 transfer complete flag clear for channel 4 13 1 write-only CHTIF4 half transfer flag clear for channel 4 14 1 write-only CTEIF4 transfer error flag clear for channel 4 15 1 write-only CGIF5 global interrupt flag clear for channel 5 16 1 write-only CTCIF5 transfer complete flag clear for channel 5 17 1 write-only CHTIF5 half transfer flag clear for channel 5 18 1 write-only CTEIF5 transfer error flag clear for channel 5 19 1 write-only CGIF6 global interrupt flag clear for channel 6 20 1 write-only CTCIF6 transfer complete flag clear for channel 6 21 1 write-only CHTIF6 half transfer flag clear for channel 6 22 1 write-only CTEIF6 transfer error flag clear for channel 6 23 1 write-only CGIF7 global interrupt flag clear for channel 7 24 1 write-only CTCIF7 transfer complete flag clear for channel 7 25 1 write-only CHTIF7 half transfer flag clear for channel 7 26 1 write-only CTEIF7 transfer error flag clear for channel 7 27 1 write-only DMA_CCR1 DMA_CCR1 DMA channel 1 configuration register 0x8 0x20 0x00000000 0xFFFFFFFF EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software. 0 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TCIE transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 1 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 HTIE half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 2 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TEIE transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 3 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 4 1 read-write B_0x0 read from peripheral 0x0 B_0x1 read from memory 0x1 CIRC circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 5 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 6 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 7 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 8 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 10 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 PL priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 12 2 read-write B_0x0 low 0x0 B_0x1 medium 0x1 B_0x2 high 0x2 B_0x3 very high 0x3 MEM2MEM memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 14 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DMA_CNDTR1 DMA_CNDTR1 DMA channel x number of data register 0xc 0x20 0x00000000 0xFFFFFFFF NDT number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write’ transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 0 16 read-write DMA_CPAR1 DMA_CPAR1 DMA channel x peripheral address register 0x10 0x20 0x00000000 0xFFFFFFFF PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CMAR1 DMA_CMAR1 DMA channel x memory address register 0x14 0x20 0x00000000 0xFFFFFFFF MA peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CCR2 DMA_CCR2 DMA channel 2 configuration register 0x1c 0x20 0x00000000 0xFFFFFFFF EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software. 0 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TCIE transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 1 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 HTIE half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 2 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TEIE transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 3 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 4 1 read-write B_0x0 read from peripheral 0x0 B_0x1 read from memory 0x1 CIRC circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 5 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 6 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 7 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 8 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 10 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 PL priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 12 2 read-write B_0x0 low 0x0 B_0x1 medium 0x1 B_0x2 high 0x2 B_0x3 very high 0x3 MEM2MEM memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 14 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DMA_CNDTR2 DMA_CNDTR2 DMA channel x number of data register 0x20 0x20 0x00000000 0xFFFFFFFF NDT number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write’ transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 0 16 read-write DMA_CPAR2 DMA_CPAR2 DMA channel x peripheral address register 0x24 0x20 0x00000000 0xFFFFFFFF PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CMAR2 DMA_CMAR2 DMA channel x memory address register 0x28 0x20 0x00000000 0xFFFFFFFF MA peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CCR3 DMA_CCR3 DMA channel 3 configuration register 0x30 0x20 0x00000000 0xFFFFFFFF EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software. 0 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TCIE transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 1 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 HTIE half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 2 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TEIE transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 3 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 4 1 read-write B_0x0 read from peripheral 0x0 B_0x1 read from memory 0x1 CIRC circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 5 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 6 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 7 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 8 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 10 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 PL priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 12 2 read-write B_0x0 low 0x0 B_0x1 medium 0x1 B_0x2 high 0x2 B_0x3 very high 0x3 MEM2MEM memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 14 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DMA_CNDTR3 DMA_CNDTR3 DMA channel x configuration register 0x34 0x20 0x00000000 0xFFFFFFFF NDT number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write’ transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 0 16 read-write DMA_CPAR3 DMA_CPAR3 DMA channel x peripheral address register 0x38 0x20 0x00000000 0xFFFFFFFF PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CMAR3 DMA_CMAR3 DMA channel x memory address register 0x3c 0x20 0x00000000 0xFFFFFFFF MA peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CCR4 DMA_CCR4 DMA channel 4 configuration register 0x44 0x20 0x00000000 0xFFFFFFFF EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software. 0 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TCIE transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 1 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 HTIE half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 2 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TEIE transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 3 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 4 1 read-write B_0x0 read from peripheral 0x0 B_0x1 read from memory 0x1 CIRC circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 5 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 6 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 7 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 8 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 10 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 PL priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 12 2 read-write B_0x0 low 0x0 B_0x1 medium 0x1 B_0x2 high 0x2 B_0x3 very high 0x3 MEM2MEM memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 14 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DMA_CNDTR4 DMA_CNDTR4 DMA channel x configuration register 0x48 0x20 0x00000000 0xFFFFFFFF NDT number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write’ transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 0 16 read-write DMA_CPAR4 DMA_CPAR4 DMA channel x peripheral address register 0x4c 0x20 0x00000000 0xFFFFFFFF PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CMAR4 DMA_CMAR4 DMA channel x memory address register 0x50 0x20 0x00000000 0xFFFFFFFF MA peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CCR5 DMA_CCR5 DMA channel 5 configuration register 0x58 0x20 0x00000000 0xFFFFFFFF EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software. 0 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TCIE transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 1 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 HTIE half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 2 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TEIE transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 3 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 4 1 read-write B_0x0 read from peripheral 0x0 B_0x1 read from memory 0x1 CIRC circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 5 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 6 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 7 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 8 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 10 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 PL priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 12 2 read-write B_0x0 low 0x0 B_0x1 medium 0x1 B_0x2 high 0x2 B_0x3 very high 0x3 MEM2MEM memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 14 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DMA_CNDTR5 DMA_CNDTR5 DMA channel x configuration register 0x5c 0x20 0x00000000 0xFFFFFFFF NDT number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write’ transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 0 16 read-write DMA_CPAR5 DMA_CPAR5 DMA channel x peripheral address register 0x60 0x20 0x00000000 0xFFFFFFFF PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CMAR5 DMA_CMAR5 DMA channel x memory address register 0x64 0x20 0x00000000 0xFFFFFFFF MA peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CCR6 DMA_CCR6 DMA channel 6 configuration register 0x6c 0x20 0x00000000 0xFFFFFFFF EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software. 0 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TCIE transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 1 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 HTIE half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 2 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TEIE transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 3 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 4 1 read-write B_0x0 read from peripheral 0x0 B_0x1 read from memory 0x1 CIRC circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 5 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 6 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 7 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 8 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 10 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 PL priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 12 2 read-write B_0x0 low 0x0 B_0x1 medium 0x1 B_0x2 high 0x2 B_0x3 very high 0x3 MEM2MEM memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 14 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DMA_CNDTR6 DMA_CNDTR6 DMA channel x configuration register 0x70 0x20 0x00000000 0xFFFFFFFF NDT number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write’ transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 0 16 read-write DMA_CPAR6 DMA_CPAR6 DMA channel x peripheral address register 0x74 0x20 0x00000000 0xFFFFFFFF PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CMAR6 DMA_CMAR6 DMA channel x memory address register 0x78 0x20 0x00000000 0xFFFFFFFF MA peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CCR7 DMA_CCR7 DMA channel 7 configuration register 0x80 0x20 0x00000000 0xFFFFFFFF EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software. 0 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TCIE transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 1 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 HTIE half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 2 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TEIE transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 3 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 4 1 read-write B_0x0 read from peripheral 0x0 B_0x1 read from memory 0x1 CIRC circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 5 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 6 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 7 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 8 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 10 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 PL priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 12 2 read-write B_0x0 low 0x0 B_0x1 medium 0x1 B_0x2 high 0x2 B_0x3 very high 0x3 MEM2MEM memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 14 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DMA_CNDTR7 DMA_CNDTR7 DMA channel x configuration register 0x84 0x20 0x00000000 0xFFFFFFFF NDT number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write’ transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 0 16 read-write DMA_CPAR7 DMA_CPAR7 DMA channel x peripheral address register 0x88 0x20 0x00000000 0xFFFFFFFF PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CMAR7 DMA_CMAR7 DMA channel x memory address register 0x8c 0x20 0x00000000 0xFFFFFFFF MA peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMAMUX DMAMUX DMAMUX 0x40020800 0x0 0x400 registers DMA_Channel4_5_6_7 DMA channel 4, 5, 6 & 7 and DMAMUX 11 DMAMUX_C0CR DMAMUX_C0CR DMAMux - DMA request line multiplexer channel x control register 0x0 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 8 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 DMAMUX_C1CR DMAMUX_C1CR DMAMux - DMA request line multiplexer channel x control register 0x4 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 8 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 DMAMUX_C2CR DMAMUX_C2CR DMAMux - DMA request line multiplexer channel x control register 0x8 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 8 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 DMAMUX_C3CR DMAMUX_C3CR DMAMux - DMA request line multiplexer channel x control register 0xC 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 8 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 DMAMUX_C4CR DMAMUX_C4CR DMAMux - DMA request line multiplexer channel x control register 0x10 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 8 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 DMAMUX_C5CR DMAMUX_C5CR DMAMux - DMA request line multiplexer channel x control register 0x14 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 8 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 DMAMUX_C6CR DMAMUX_C6CR DMAMux - DMA request line multiplexer channel x control register 0x18 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 8 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 DMAMUX_RG0CR DMAMUX_RG0CR DMAMux - DMA request generator channel x control register 0x100 0x20 read-write 0x00000000 SIG_ID DMA request trigger input selected 0 5 OIE Interrupt enable at trigger event overrun 8 1 GE DMA request generator channel enable/disable 16 1 GPOL DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input 17 2 GNBREQ Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. 19 5 DMAMUX_RG1CR DMAMUX_RG1CR DMAMux - DMA request generator channel x control register 0x104 0x20 read-write 0x00000000 SIG_ID DMA request trigger input selected 0 5 OIE Interrupt enable at trigger event overrun 8 1 GE DMA request generator channel enable/disable 16 1 GPOL DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input 17 2 GNBREQ Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. 19 5 DMAMUX_RG2CR DMAMUX_RG2CR DMAMux - DMA request generator channel x control register 0x108 0x20 read-write 0x00000000 SIG_ID DMA request trigger input selected 0 5 OIE Interrupt enable at trigger event overrun 8 1 GE DMA request generator channel enable/disable 16 1 GPOL DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input 17 2 GNBREQ Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. 19 5 DMAMUX_RG3CR DMAMUX_RG3CR DMAMux - DMA request generator channel x control register 0x10C 0x20 read-write 0x00000000 SIG_ID DMA request trigger input selected 0 5 OIE Interrupt enable at trigger event overrun 8 1 GE DMA request generator channel enable/disable 16 1 GPOL DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input 17 2 GNBREQ Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. 19 5 DMAMUX_RGSR DMAMUX_RGSR DMAMux - DMA request generator status register 0x140 0x20 read-only 0x00000000 OF Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. 0 4 DMAMUX_RGCFR DMAMUX_RGCFR DMAMux - DMA request generator clear flag register 0x144 0x20 write-only 0x00000000 COF Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register. 0 4 DMAMUX_CSR DMAMUX_CSR DMAMUX request line multiplexer interrupt channel status register 0x80 0x20 read-only 0x00000000 SOF Synchronization overrun event flag 0 7 DMAMUX_CFR DMAMUX_CFR DMAMUX request line multiplexer interrupt clear flag register 0x84 0x20 write-only 0x00000000 CSOF Clear synchronization overrun event flag 0 7 DMAMUX_SIDR DMAMUX_SIDR DMAMUX size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SID Size identification 0 32 DMAMUX_IPIDR DMAMUX_IPIDR DMAMUX IP identification register 0x3F8 0x20 read-only 0x00100011 ID IP identification 0 32 DMAMUX_VERR DMAMUX_VERR DMAMUX version register 0x3F4 0x20 read-only 0x00000011 MINREV Minor IP revision 0 4 MAJREV Major IP revision 4 4 DMAMUX_HWCFGR1 DMAMUX_HWCFGR1 DMAMUX hardware configuration 1 register 0x3F0 0x20 read-only 0x04173907 NUM_DMA_STREAMS number of DMA request line multiplexer (output) channels 0 8 NUM_DMA_PERIPH_REQ number of DMA request lines from peripherals 8 8 NUM_DMA_TRIG number of synchronization inputs 16 8 NUM_DMA_REQGEN number of DMA request generator channels 24 8 DMAMUX_HWCFGR2 DMAMUX_HWCFGR2 DMAMUX hardware configuration 2 register 0x3EC 0x20 read-only 0x00000017 NUM_DMA_EXT_REQ Number of DMA request trigger inputs 0 8 GPIOA General-purpose I/Os GPIO 0x50000000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xEBFFFFFF MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x0C000000 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x24000000 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFSEL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFSEL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFSEL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFSEL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFSEL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFSEL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFSEL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFSEL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFSEL15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFSEL14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFSEL13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFSEL12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFSEL11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFSEL10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFSEL9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFSEL8 Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR port bit reset register 0x28 0x20 write-only 0x00000000 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 GPIOB General-purpose I/Os GPIO 0x50000400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFSEL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFSEL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFSEL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFSEL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFSEL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFSEL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFSEL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFSEL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFSEL15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFSEL14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFSEL13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFSEL12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFSEL11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFSEL10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFSEL9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFSEL8 Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR port bit reset register 0x28 0x20 write-only 0x00000000 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 GPIOC 0x50000800 GPIOD 0x50000C00 GPIOF 0x50001400 RNG Random number generator RNG 0x40025000 0x0 0x400 registers CR CR control register 0x0 0x20 read-write 0x00000000 RNGEN Random number generator enable 2 1 IE Interrupt enable 3 1 CED Clock error detection 5 1 BYP Bypass mode enable 6 1 SR SR status register 0x4 0x20 0x00000000 SEIS Seed error interrupt status 6 1 read-write CEIS Clock error interrupt status 5 1 read-write SECS Seed error current status 2 1 read-only CECS Clock error current status 1 1 read-only DRDY Data ready 0 1 read-only DR DR data register 0x8 0x20 read-only 0x00000000 RNDATA Random data 0 32 CRC Cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers CEC CEC global interrupt 30 DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data register bits 0 32 IDR IDR Independent data register 0x4 0x20 read-write 0x00000000 IDR General-purpose 32-bit data register bits 0 32 CR CR Control register 0x8 0x20 0x00000000 REV_OUT Reverse output data 7 1 read-write REV_IN Reverse input data 5 2 read-write POLYSIZE Polynomial size 3 2 read-write RESET RESET bit 0 1 write-only INIT INIT Initial CRC value 0x10 0x20 read-write 0xFFFFFFFF CRC_INIT Programmable initial CRC value 0 32 POL POL polynomial 0x14 0x20 read-write 0x04C11DB7 POL Programmable polynomial 0 32 EXTI External interrupt/event controller EXTI 0x40021800 0x0 0x400 registers EXTI0_1 EXTI line 0 and 1 interrupt 5 EXTI2_3 EXTI line 2 and 3 interrupt 6 EXTI4_15 EXTI line 4 to 15 interrupt 7 RTSR1 RTSR1 EXTI rising trigger selection register 0x0 0x20 read-write 0x00000000 RT0 Rising trigger event configuration bit of Configurable Event line 0 1 RT1 Rising trigger event configuration bit of Configurable Event line 1 1 RT2 Rising trigger event configuration bit of Configurable Event line 2 1 RT3 Rising trigger event configuration bit of Configurable Event line 3 1 RT4 Rising trigger event configuration bit of Configurable Event line 4 1 RT5 Rising trigger event configuration bit of Configurable Event line 5 1 RT6 Rising trigger event configuration bit of Configurable Event line 6 1 RT7 Rising trigger event configuration bit of Configurable Event line 7 1 RT8 Rising trigger event configuration bit of Configurable Event line 8 1 RT9 Rising trigger event configuration bit of Configurable Event line 9 1 RT10 Rising trigger event configuration bit of Configurable Event line 10 1 RT11 Rising trigger event configuration bit of Configurable Event line 11 1 RT12 Rising trigger event configuration bit of Configurable Event line 12 1 RT13 Rising trigger event configuration bit of Configurable Event line 13 1 RT14 Rising trigger event configuration bit of Configurable Event line 14 1 RT15 Rising trigger event configuration bit of Configurable Event line 15 1 FTSR1 FTSR1 EXTI falling trigger selection register 0x4 0x20 read-write 0x00000000 FT0 Falling trigger event configuration bit of configurable line 0 1 FT1 Falling trigger event configuration bit of configurable line 1 1 FT2 Falling trigger event configuration bit of configurable line 2 1 FT3 Falling trigger event configuration bit of configurable line 3 1 FT4 Falling trigger event configuration bit of configurable line 4 1 FT5 Falling trigger event configuration bit of configurable line 5 1 FT6 Falling trigger event configuration bit of configurable line 6 1 FT7 Falling trigger event configuration bit of configurable line 7 1 FT8 Falling trigger event configuration bit of configurable line 8 1 FT9 Falling trigger event configuration bit of configurable line 9 1 FT10 Falling trigger event configuration bit of configurable line 10 1 FT11 Falling trigger event configuration bit of configurable line 11 1 FT12 Falling trigger event configuration bit of configurable line 12 1 FT13 Falling trigger event configuration bit of configurable line 13 1 FT14 Falling trigger event configuration bit of configurable line 14 1 FT15 Falling trigger event configuration bit of configurable line 15 1 SWIER1 SWIER1 EXTI software interrupt event register 0x8 0x20 read-write 0x00000000 SWI0 Software rising edge event trigger on line 0 1 SWI1 Software rising edge event trigger on line 1 1 SWI2 Software rising edge event trigger on line 2 1 SWI3 Software rising edge event trigger on line 3 1 SWI4 Software rising edge event trigger on line 4 1 SWI5 Software rising edge event trigger on line 5 1 SWI6 Software rising edge event trigger on line 6 1 SWI7 Software rising edge event trigger on line 7 1 SWI8 Software rising edge event trigger on line 8 1 SWI9 Software rising edge event trigger on line 9 1 SWI10 Software rising edge event trigger on line 10 1 SWI11 Software rising edge event trigger on line 11 1 SWI12 Software rising edge event trigger on line 12 1 SWI13 Software rising edge event trigger on line 13 1 SWI14 Software rising edge event trigger on line 14 1 SWI15 Software rising edge event trigger on line 15 1 RPR1 RPR1 EXTI rising edge pending register 0xC 0x20 read-write 0x00000000 RPIF0 Rising edge event pending for configurable line 0 1 RPIF1 Rising edge event pending for configurable line 1 1 RPIF2 Rising edge event pending for configurable line 2 1 RPIF3 Rising edge event pending for configurable line 3 1 RPIF4 Rising edge event pending for configurable line 4 1 RPIF5 configurable event inputs x rising edge Pending bit 5 1 RPIF6 Rising edge event pending for configurable line 6 1 RPIF7 Rising edge event pending for configurable line 7 1 RPIF8 Rising edge event pending for configurable line 8 1 RPIF9 Rising edge event pending for configurable line 9 1 RPIF10 Rising edge event pending for configurable line 10 1 RPIF11 Rising edge event pending for configurable line 11 1 RPIF12 Rising edge event pending for configurable line 12 1 RPIF13 Rising edge event pending for configurable line 13 1 RPIF14 Rising edge event pending for configurable line 14 1 RPIF15 Rising edge event pending for configurable line 15 1 FPR1 FPR1 EXTI falling edge pending register 0x10 0x20 read-write 0x00000000 FPIF0 Falling edge event pending for configurable line 0 1 FPIF1 Falling edge event pending for configurable line 1 1 FPIF2 Falling edge event pending for configurable line 2 1 FPIF3 Falling edge event pending for configurable line 3 1 FPIF4 Falling edge event pending for configurable line 4 1 FPIF5 Falling edge event pending for configurable line 5 1 FPIF6 Falling edge event pending for configurable line 6 1 FPIF7 Falling edge event pending for configurable line 7 1 FPIF8 Falling edge event pending for configurable line 8 1 FPIF9 Falling edge event pending for configurable line 9 1 FPIF10 Falling edge event pending for configurable line 10 1 FPIF11 Falling edge event pending for configurable line 11 1 FPIF12 Falling edge event pending for configurable line 12 1 FPIF13 Falling edge event pending for configurable line 13 1 FPIF14 Falling edge event pending for configurable line 14 1 FPIF15 Falling edge event pending for configurable line 15 1 EXTICR1 EXTICR1 EXTI external interrupt selection register 0x60 0x20 read-write 0x00000000 EXTI0_7 GPIO port selection 0 8 EXTI8_15 GPIO port selection 8 8 EXTI16_23 GPIO port selection 16 8 EXTI24_31 GPIO port selection 24 8 EXTICR2 EXTICR2 EXTI external interrupt selection register 0x64 0x20 read-write 0x00000000 EXTI0_7 GPIO port selection 0 8 EXTI8_15 GPIO port selection 8 8 EXTI16_23 GPIO port selection 16 8 EXTI24_31 GPIO port selection 24 8 EXTICR3 EXTICR3 EXTI external interrupt selection register 0x68 0x20 read-write 0x00000000 EXTI0_7 GPIO port selection 0 8 EXTI8_15 GPIO port selection 8 8 EXTI16_23 GPIO port selection 16 8 EXTI24_31 GPIO port selection 24 8 EXTICR4 EXTICR4 EXTI external interrupt selection register 0x6C 0x20 read-write 0x00000000 EXTI0_7 GPIO port selection 0 8 EXTI8_15 GPIO port selection 8 8 EXTI16_23 GPIO port selection 16 8 EXTI24_31 GPIO port selection 24 8 IMR1 IMR1 EXTI CPU wakeup with interrupt mask register 0x80 0x20 read-write 0xFFF80000 IM0 CPU wakeup with interrupt mask on event input 0 1 IM1 CPU wakeup with interrupt mask on event input 1 1 IM2 CPU wakeup with interrupt mask on event input 2 1 IM3 CPU wakeup with interrupt mask on event input 3 1 IM4 CPU wakeup with interrupt mask on event input 4 1 IM5 CPU wakeup with interrupt mask on event input 5 1 IM6 CPU wakeup with interrupt mask on event input 6 1 IM7 CPU wakeup with interrupt mask on event input 7 1 IM8 CPU wakeup with interrupt mask on event input 8 1 IM9 CPU wakeup with interrupt mask on event input 9 1 IM10 CPU wakeup with interrupt mask on event input 10 1 IM11 CPU wakeup with interrupt mask on event input 11 1 IM12 CPU wakeup with interrupt mask on event input 12 1 IM13 CPU wakeup with interrupt mask on event input 13 1 IM14 CPU wakeup with interrupt mask on event input 14 1 IM15 CPU wakeup with interrupt mask on event input 15 1 IM19 CPU wakeup with interrupt mask on event input 19 1 IM21 CPU wakeup with interrupt mask on event input 21 1 IM22 CPU wakeup with interrupt mask on event input 22 1 IM23 CPU wakeup with interrupt mask on event input 23 1 IM24 CPU wakeup with interrupt mask on event input 24 1 IM25 CPU wakeup with interrupt mask on event input 25 1 IM26 CPU wakeup with interrupt mask on event input 26 1 IM31 CPU wakeup with interrupt mask on event input 31 1 EMR1 EMR1 EXTI CPU wakeup with event mask register IMR1 0x84 0x20 read-write 0x00000000 EM0 CPU wakeup with event mask on event input 0 1 EM1 CPU wakeup with event mask on event input 1 1 EM2 CPU wakeup with event mask on event input 2 1 EM3 CPU wakeup with event mask on event input 3 1 EM4 CPU wakeup with event mask on event input 4 1 EM5 CPU wakeup with event mask on event input 5 1 EM6 CPU wakeup with event mask on event input 6 1 EM7 CPU wakeup with event mask on event input 7 1 EM8 CPU wakeup with event mask on event input 8 1 EM9 CPU wakeup with event mask on event input 9 1 EM10 CPU wakeup with event mask on event input 10 1 EM11 CPU wakeup with event mask on event input 11 1 EM12 CPU wakeup with event mask on event input 12 1 EM13 CPU wakeup with event mask on event input 13 1 EM14 CPU wakeup with event mask on event input 14 1 EM15 CPU wakeup with event mask on event input 15 1 EM19 CPU wakeup with event mask on event input 19 1 EM21 CPU wakeup with event mask on event input 21 1 EM23 CPU wakeup with event mask on event input 23 1 EM25 CPU wakeup with event mask on event input 25 1 EM26 CPU wakeup with event mask on event input 26 1 EM31 CPU wakeup with event mask on event input 31 1 TIM15 General purpose timers TIM 0x40014000 0x0 0x400 registers TIM15 Timer 15 global interrupt 20 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CEN Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write B_0x0 Counter disabled 0x0 B_0x1 Counter enabled 0x1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write B_0x0 UEV enabled. The Update (UEV) event is generated by one of the following events: 0x0 B_0x1 UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. 0x1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write B_0x0 Any of the following events generate an update interrupt if enabled. These events can be: 0x0 B_0x1 Only counter overflow/underflow generates an update interrupt if enabled 0x1 OPM One-pulse mode 3 1 read-write B_0x0 Counter is not stopped at update event 0x0 B_0x1 Counter stops counting at the next update event (clearing the bit CEN) 0x1 ARPE Auto-reload preload enable 7 1 read-write B_0x0 TIMx_ARR register is not buffered 0x0 B_0x1 TIMx_ARR register is buffered 0x1 CKD Clock division This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx) 8 2 read-write B_0x0 tDTS = tCK_INT 0x0 B_0x1 tDTS = 2*tCK_INT 0x1 B_0x2 tDTS = 4*tCK_INT 0x2 B_0x3 Reserved, do not program this value 0x3 UIFREMAP UIF status bit remapping 11 1 read-write B_0x0 No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 0x0 B_0x1 Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. 0x1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 CCPC Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output. 0 1 read-write B_0x0 CCxE, CCxNE and OCxM bits are not preloaded 0x0 B_0x1 CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). 0x1 CCUS Capture/compare control update selection Note: This bit acts only on channels that have a complementary output. 2 1 read-write B_0x0 When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. 0x0 B_0x1 When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. 0x1 CCDS Capture/compare DMA selection 3 1 read-write B_0x0 CCx DMA request sent when CCx event occurs 0x0 B_0x1 CCx DMA requests sent when update event occurs 0x1 MMS Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 4 3 read-write B_0x0 Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 0x0 B_0x1 Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 0x1 B_0x2 Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 0x2 B_0x3 Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). 0x3 B_0x4 Compare - OC1REFC signal is used as trigger output (TRGO). 0x4 B_0x5 Compare - OC2REFC signal is used as trigger output (TRGO). 0x5 TI1S TI1 selection 7 1 read-write B_0x0 The TIMx_CH1 pin is connected to TI1 input 0x0 B_0x1 The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination) 0x1 OIS1 Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register). 8 1 read-write B_0x0 OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 0x0 B_0x1 OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 0x1 OIS1N Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register). 9 1 read-write B_0x0 OC1N=0 after a dead-time when MOE=0 0x0 B_0x1 OC1N=1 after a dead-time when MOE=0 0x1 OIS2 Output idle state 2 (OC2 output) Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in the TIM15_BDTR register). 10 1 read-write B_0x0 OC2=0 when MOE=0 0x0 B_0x1 OC2=1 when MOE=0 0x1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 SMS1 Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write B_0x0 Slave mode disabled - if CEN = '1’ then the prescaler is clocked directly by the internal clock. 0x0 B_0x4 Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0x4 B_0x5 Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0x5 B_0x6 Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0x6 B_0x7 External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 0x7 B_0x8 Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 0x8 TS1 Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write B_0x0 Internal Trigger 0 (ITR0) 0x0 B_0x1 Internal Trigger 1 (ITR1) 0x1 B_0x2 Internal Trigger 2 (ITR2) 0x2 B_0x3 Internal Trigger 3 (ITR3) 0x3 B_0x4 TI1 Edge Detector (TI1F_ED) 0x4 B_0x5 Filtered Timer Input 1 (TI1FP1) 0x5 B_0x6 Filtered Timer Input 2 (TI2FP2) 0x6 MSM Master/slave mode 7 1 read-write B_0x0 No action 0x0 B_0x1 The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 0x1 SMS2 Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 16 1 read-write B_0x0 Slave mode disabled - if CEN = '1’ then the prescaler is clocked directly by the internal clock. 0x0 B_0x4 Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0x4 B_0x5 Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0x5 B_0x6 Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0x6 B_0x7 External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 0x7 B_0x8 Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 0x8 TS2 Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 20 2 read-write B_0x0 Internal Trigger 0 (ITR0) 0x0 B_0x1 Internal Trigger 1 (ITR1) 0x1 B_0x2 Internal Trigger 2 (ITR2) 0x2 B_0x3 Internal Trigger 3 (ITR3) 0x3 B_0x4 TI1 Edge Detector (TI1F_ED) 0x4 B_0x5 Filtered Timer Input 1 (TI1FP1) 0x5 B_0x6 Filtered Timer Input 2 (TI2FP2) 0x6 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 UIE Update interrupt enable 0 1 read-write B_0x0 Update interrupt disabled 0x0 B_0x1 Update interrupt enabled 0x1 CC1IE Capture/Compare 1 interrupt enable 1 1 read-write B_0x0 CC1 interrupt disabled 0x0 B_0x1 CC1 interrupt enabled 0x1 CC2IE Capture/Compare 2 interrupt enable 2 1 read-write B_0x0 CC2 interrupt disabled 0x0 B_0x1 CC2 interrupt enabled 0x1 COMIE COM interrupt enable 5 1 read-write B_0x0 COM interrupt disabled 0x0 B_0x1 COM interrupt enabled 0x1 TIE Trigger interrupt enable 6 1 read-write B_0x0 Trigger interrupt disabled 0x0 B_0x1 Trigger interrupt enabled 0x1 BIE Break interrupt enable 7 1 read-write B_0x0 Break interrupt disabled 0x0 B_0x1 Break interrupt enabled 0x1 UDE Update DMA request enable 8 1 read-write B_0x0 Update DMA request disabled 0x0 B_0x1 Update DMA request enabled 0x1 CC1DE Capture/Compare 1 DMA request enable 9 1 read-write B_0x0 CC1 DMA request disabled 0x0 B_0x1 CC1 DMA request enabled 0x1 CC2DE Capture/Compare 2 DMA request enable 10 1 read-write B_0x0 CC2 DMA request disabled 0x0 B_0x1 CC2 DMA request enabled 0x1 COMDE COM DMA request enable 13 1 read-write B_0x0 COM DMA request disabled 0x0 B_0x1 COM DMA request enabled 0x1 TDE Trigger DMA request enable 14 1 read-write B_0x0 Trigger DMA request disabled 0x0 B_0x1 Trigger DMA request enabled 0x1 SR SR status register 0x10 0x20 read-write 0x0000 UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write B_0x0 No update occurred. 0x0 B_0x1 Update interrupt pending. This bit is set by hardware when the registers are updated: 0x1 CC1IF Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). 1 1 read-write B_0x0 No compare match / No input capture occurred 0x0 B_0x1 A compare match or an input capture occurred 0x1 CC2IF Capture/Compare 2 interrupt flag refer to CC1IF description 2 1 read-write COMIF COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software. 5 1 read-write B_0x0 No COM event occurred 0x0 B_0x1 COM interrupt pending 0x1 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write B_0x0 No trigger event occurred 0x0 B_0x1 Trigger interrupt pending 0x1 BIF Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 7 1 read-write B_0x0 No break event occurred 0x0 B_0x1 An active level has been detected on the break input 0x1 CC1OF Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’. 9 1 read-write B_0x0 No overcapture has been detected 0x0 B_0x1 The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set 0x1 CC2OF Capture/Compare 2 overcapture flag Refer to CC1OF description 10 1 read-write EGR EGR event generation register 0x14 0x20 write-only 0x0000 UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only B_0x0 No action 0x0 B_0x1 Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). 0x1 CC1G Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. 1 1 write-only B_0x0 No action 0x0 B_0x1 A capture/compare event is generated on channel 1: 0x1 CC2G Capture/Compare 2 generation Refer to CC1G description 2 1 write-only COMG Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output. 5 1 read-write B_0x0 No action 0x0 B_0x1 When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits 0x1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only B_0x0 No action 0x0 B_0x1 The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled 0x1 BG Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 7 1 write-only B_0x0 No action 0x0 B_0x1 A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. 0x1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER). 0 2 read-write B_0x0 CC1 channel is configured as output. 0x0 B_0x1 CC1 channel is configured as input, IC1 is mapped on TI1. 0x1 B_0x2 CC1 channel is configured as input, IC1 is mapped on TI2. 0x2 B_0x3 CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 OC1FE Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. 2 1 read-write B_0x0 CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 0x0 B_0x1 An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. 0x1 OC1PE Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. 3 1 read-write B_0x0 Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 0x0 B_0x1 Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. 0x1 OC1M1 Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16. 4 3 read-write B_0x0 Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 0x0 B_0x1 Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x1 B_0x2 Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x2 B_0x3 Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0x3 B_0x4 Force inactive level - OC1REF is forced low. 0x4 B_0x5 Force active level - OC1REF is forced high. 0x5 B_0x6 PWM mode 1 - Channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. 0x6 B_0x7 PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. 0x7 B_0x8 Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 0x8 B_0x9 Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 0x9 B_0xC Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 0xC B_0xD Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 0xD CC2S Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER). 8 2 read-write B_0x0 CC2 channel is configured as output. 0x0 B_0x1 CC2 channel is configured as input, IC2 is mapped on TI2. 0x1 B_0x2 CC2 channel is configured as input, IC2 is mapped on TI1. 0x2 B_0x3 CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) 0x3 OC2FE Output Compare 2 fast enable 10 1 read-write OC2PE Output Compare 2 preload enable 11 1 read-write OC2M1 Output Compare 2 mode 12 3 read-write OC1M2 Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16. 16 1 read-write B_0x0 Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 0x0 B_0x1 Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x1 B_0x2 Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x2 B_0x3 Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0x3 B_0x4 Force inactive level - OC1REF is forced low. 0x4 B_0x5 Force active level - OC1REF is forced high. 0x5 B_0x6 PWM mode 1 - Channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. 0x6 B_0x7 PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. 0x7 B_0x8 Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 0x8 B_0x9 Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 0x9 B_0xC Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 0xC B_0xD Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 0xD OC2M2 Output Compare 2 mode 24 1 read-write CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 CC1S Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER). 0 2 read-write B_0x0 CC1 channel is configured as output 0x0 B_0x1 CC1 channel is configured as input, IC1 is mapped on TI1 0x1 B_0x2 CC1 channel is configured as input, IC1 is mapped on TI2 0x2 B_0x3 CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 IC1PSC Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 2 2 read-write B_0x0 no prescaler, capture is done each time an edge is detected on the capture input 0x0 B_0x1 capture is done once every 2 events 0x1 B_0x2 capture is done once every 4 events 0x2 B_0x3 capture is done once every 8 events 0x3 IC1F Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 4 4 read-write B_0x0 No filter, sampling is done at fDTS 0x0 B_0x1 fSAMPLING=fCK_INT, N=2 0x1 B_0x2 fSAMPLING=fCK_INT, N=4 0x2 B_0x3 fSAMPLING=fCK_INT, N=8 0x3 B_0x4 fSAMPLING=fDTS/2, N=6 0x4 B_0x5 fSAMPLING=fDTS/2, N=8 0x5 B_0x6 fSAMPLING=fDTS/4, N=6 0x6 B_0x7 fSAMPLING=fDTS/4, N=8 0x7 B_0x8 fSAMPLING=fDTS/8, N=6 0x8 B_0x9 fSAMPLING=fDTS/8, N=8 0x9 B_0xA fSAMPLING=fDTS/16, N=5 0xA B_0xB fSAMPLING=fDTS/16, N=6 0xB B_0xC fSAMPLING=fDTS/16, N=8 0xC B_0xD fSAMPLING=fDTS/32, N=5 0xD B_0xE fSAMPLING=fDTS/32, N=6 0xE B_0xF fSAMPLING=fDTS/32, N=8 0xF CC2S Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER). 8 2 read-write B_0x0 CC2 channel is configured as output 0x0 B_0x1 CC2 channel is configured as input, IC2 is mapped on TI2 0x1 B_0x2 CC2 channel is configured as input, IC2 is mapped on TI1 0x2 B_0x3 CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 IC2PSC Input capture 2 prescaler 10 2 read-write IC2F Input capture 2 filter 12 4 read-write CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1E Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details. 0 1 read-write B_0x0 Capture mode disabled / OC1 is not active (see below) 0x0 B_0x1 Capture mode enabled / OC1 signal is output on the corresponding output pin 0x1 CC1P Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. 1 1 read-write B_0x0 OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) 0x0 B_0x1 OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) 0x1 CC1NE Capture/Compare 1 complementary output enable 2 1 read-write B_0x0 Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 0x0 B_0x1 On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 0x1 CC1NP Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated. 3 1 read-write B_0x0 OC1N active high 0x0 B_0x1 OC1N active low 0x1 CC2E Capture/Compare 2 output enable Refer to CC1E description 4 1 read-write CC2P Capture/Compare 2 output polarity Refer to CC1P description 5 1 read-write CC2NP Capture/Compare 2 complementary output polarity Refer to CC1NP description 7 1 read-write CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2 Capture/Compare 2 value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 DTG Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 8 read-write LOCK Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. 8 2 read-write B_0x0 LOCK OFF - No bit is write protected 0x0 B_0x1 LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written 0x1 B_0x2 LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 0x2 B_0x3 LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. 0x3 OSSI Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write B_0x0 When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) 0x0 B_0x1 When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1) 0x1 OSSR Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write B_0x0 When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state) 0x0 B_0x1 When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). 0x1 BKE Break enable 1; Break inputs (BRK and CCS clock failure event) enabled This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 12 1 read-write B_0x0 Break inputs (BRK and CCS clock failure event) disabled 0x0 BKP Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 13 1 read-write B_0x0 Break input BRK is active low 0x0 B_0x1 Break input BRK is active high 0x1 AOE Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 1 read-write B_0x0 MOE can be set only by software 0x0 B_0x1 MOE can be set by software or automatically at the next update event (if the break input is not be active) 0x1 MOE Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). 15 1 read-write B_0x0 OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. 0x0 B_0x1 OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register) 0x1 BKF Break filter This bit-field defines the frequency used to sample the BRK input signal and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 4 read-write B_0x0 No filter, BRK acts asynchronously 0x0 B_0x1 fSAMPLING=fCK_INT, N=2 0x1 B_0x2 fSAMPLING=fCK_INT, N=4 0x2 B_0x3 fSAMPLING=fCK_INT, N=8 0x3 B_0x4 fSAMPLING=fDTS/2, N=6 0x4 B_0x5 fSAMPLING=fDTS/2, N=8 0x5 B_0x6 fSAMPLING=fDTS/4, N=6 0x6 B_0x7 fSAMPLING=fDTS/4, N=8 0x7 B_0x8 fSAMPLING=fDTS/8, N=6 0x8 B_0x9 fSAMPLING=fDTS/8, N=8 0x9 B_0xA fSAMPLING=fDTS/16, N=5 0xA B_0xB fSAMPLING=fDTS/16, N=6 0xB B_0xC fSAMPLING=fDTS/16, N=8 0xC B_0xD fSAMPLING=fDTS/32, N=5 0xD B_0xE fSAMPLING=fDTS/32, N=6 0xE B_0xF fSAMPLING=fDTS/32, N=8 0xF BKDSRM Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 26 1 read-write B_0x0 Break input BRK is armed 0x0 B_0x1 Break input BRK is disarmed 0x1 BKBID Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 28 1 read-write B_0x0 Break input BRK in input mode 0x0 B_0x1 Break input BRK in bidirectional mode 0x1 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBA DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... 0 5 read-write B_0x0 TIMx_CR1, 0x0 B_0x1 TIMx_CR2, 0x1 B_0x2 TIMx_SMCR, 0x2 DBL DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ... 8 5 read-write B_0x0 1 transfer, 0x0 B_0x1 2 transfers, 0x1 B_0x2 3 transfers, 0x2 B_0x11 18 transfers. 0x11 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 TIM16 General purpose timers TIM 0x40014400 0x0 0x400 registers TIM16 TIM16 global interrupt 21 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CEN Counter enable 0 1 UDIS Update disable 1 1 URS Update request source 2 1 OPM One-pulse mode 3 1 ARPE Auto-reload preload enable 7 1 CKD Clock division 8 2 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 COMDE COM DMA request enable 13 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 BIE Break interrupt enable 7 1 COMIE COM interrupt enable 5 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC1OF Capture/Compare 1 overcapture flag 9 1 BIF Break interrupt flag 7 1 COMIF COM interrupt flag 5 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 BG Break generation 7 1 COMG Capture/Compare control update generation 5 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 OC1M_2 Output Compare 1 mode 16 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 BKE Break enable 12 1 BKP Break polarity 13 1 AOE Automatic output enable 14 1 MOE Main output enable 15 1 BKF Break filter 16 4 BKDSRM Break Disarm 26 1 BKBID Break Bidirectional 28 1 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 AF1 AF1 TIM17 option register 1 0x60 0x20 read-write 0x0000 BKINE BRK BKIN input enable 0 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP2E BRK COMP2 enable 2 1 BKDFBK1E BRK DFSDM_BREAK1 enable 8 1 BKINP BRK BKIN input polarity 9 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2P BRK COMP2 input polarit 11 1 TISEL TISEL input selection register 0x68 0x20 read-write 0x0000 TI1SEL selects input 0 4 TIM17 0x40014800 TIM17 TIM17 global interrupt 22 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 27 CR1 CR1 Control register 1 0x0 0x20 read-write 0x0000 RXFFIE RXFIFO Full interrupt enable 31 1 TXFEIE TXFIFO empty interrupt enable 30 1 FIFOEN FIFO mode enable 29 1 M1 Word length 28 1 EOBIE End of Block interrupt enable 27 1 RTOIE Receiver timeout interrupt enable 26 1 DEAT DEAT 21 5 DEDT DEDT 16 5 OVER8 Oversampling mode 15 1 CMIE Character match interrupt enable 14 1 MME Mute mode enable 13 1 M0 Word length 12 1 WAKE Receiver wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXEIE interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXNEIE RXNE interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 UESM USART enable in Stop mode 1 1 UE USART enable 0 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x0000 ADD4_7 Address of the USART node 28 4 ADD0_3 Address of the USART node 24 4 RTOEN Receiver timeout enable 23 1 ABRMOD Auto baud rate mode 21 2 ABREN Auto baud rate enable 20 1 MSBFIRST Most significant bit first 19 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 RXINV RX pin active level inversion 16 1 SWAP Swap TX/RX pins 15 1 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CLKEN Clock enable 11 1 CPOL Clock polarity 10 1 CPHA Clock phase 9 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 SLVEN Synchronous Slave mode enable 0 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x0000 TXFTCFG TXFIFO threshold configuration 29 3 RXFTIE RXFIFO threshold interrupt enable 28 1 RXFTCFG Receive FIFO threshold configuration 25 3 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 SCARCNT Smartcard auto-retry count 17 3 DEP Driver enable polarity selection 15 1 DEM Driver enable mode 14 1 DDRE DMA Disable on Reception Error 13 1 OVRDIS Overrun Disable 12 1 ONEBIT One sample bit method enable 11 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 SCEN Smartcard mode enable 5 1 NACK Smartcard NACK enable 4 1 HDSEL Half-duplex selection 3 1 IRLP Ir low-power 2 1 IREN Ir mode enable 1 1 EIE Error interrupt enable 0 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x0000 BRR_4_15 BRR_4_15 4 12 BRR_0_3 BRR_0_3 0 4 GTPR GTPR Guard time and prescaler register 0x10 0x20 read-write 0x0000 GT Guard time value 8 8 PSC Prescaler value 0 8 RTOR RTOR Receiver timeout register 0x14 0x20 read-write 0x0000 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 RQR RQR Request register 0x18 0x20 write-only 0x0000 TXFRQ Transmit data flush request 4 1 RXFRQ Receive data flush request 3 1 MMRQ Mute mode request 2 1 SBKRQ Send break request 1 1 ABRRQ Auto baud rate request 0 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x00C0 TXFT TXFIFO threshold flag 27 1 RXFT RXFIFO threshold flag 26 1 TCBGT Transmission complete before guard time flag 25 1 RXFF RXFIFO Full 24 1 TXFE TXFIFO Empty 23 1 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 SBKF SBKF 18 1 CMF CMF 17 1 BUSY BUSY 16 1 ABRF ABRF 15 1 ABRE ABRE 14 1 UDR SPI slave underrun error flag 13 1 EOBF EOBF 12 1 RTOF RTOF 11 1 CTS CTS 10 1 CTSIF CTSIF 9 1 LBDF LBDF 8 1 TXE TXE 7 1 TC TC 6 1 RXNE RXNE 5 1 IDLE IDLE 4 1 ORE ORE 3 1 NF NF 2 1 FE FE 1 1 PE PE 0 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x0000 WUCF Wakeup from Stop mode clear flag 20 1 CMCF Character match clear flag 17 1 UDRCF SPI slave underrun clear flag 13 1 EOBCF End of block clear flag 12 1 RTOCF Receiver timeout clear flag 11 1 CTSCF CTS clear flag 9 1 LBDCF LIN break detection clear flag 8 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 IDLECF Idle line detected clear flag 4 1 ORECF Overrun error clear flag 3 1 NCF Noise detected clear flag 2 1 FECF Framing error clear flag 1 1 PECF Parity error clear flag 0 1 RDR RDR Receive data register 0x24 0x20 read-only 0x0000 RDR Receive data value 0 9 TDR TDR Transmit data register 0x28 0x20 read-write 0x0000 TDR Transmit data value 0 9 PRESC PRESC Prescaler register 0x2C 0x20 read-write 0x0000 PRESCALER Clock prescaler 0 4 USART2 0x40004400 USART2 USART2 global interrupt 28 USART3 0x40004800 USART3_USART4_LPUART1 USART3 + USART4 + LPUART1 29 USART4 0x40004C00 SPI1 Serial peripheral interface/Inter-IC sound SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 25 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 RXONLY Receive only 10 1 SSM Software slave management 9 1 SSI Internal slave select 8 1 LSBFIRST Frame format 7 1 SPE SPI enable 6 1 BR Baud rate control 3 3 MSTR Master selection 2 1 CPOL Clock polarity 1 1 CPHA Clock phase 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 RXDMAEN Rx buffer DMA enable 0 1 TXDMAEN Tx buffer DMA enable 1 1 SSOE SS output enable 2 1 NSSP NSS pulse management 3 1 FRF Frame format 4 1 ERRIE Error interrupt enable 5 1 RXNEIE RX buffer not empty interrupt enable 6 1 TXEIE Tx buffer empty interrupt enable 7 1 DS Data size 8 4 FRXTH FIFO reception threshold 12 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_TX Last DMA transfer for transmission 14 1 SR SR status register 0x8 0x20 0x0002 RXNE Receive buffer not empty 0 1 read-only TXE Transmit buffer empty 1 1 read-only CHSIDE Channel side 2 1 read-only UDR Underrun flag 3 1 read-only CRCERR CRC error flag 4 1 read-write MODF Mode fault 5 1 read-only OVR Overrun flag 6 1 read-only BSY Busy flag 7 1 read-only TIFRFE TI frame format error 8 1 read-only FRLVL FIFO reception level 9 2 read-only FTLVL FIFO transmission level 11 2 read-only DR DR data register 0xC 0x20 read-write 0x0000 DR Data register 0 16 CRCPR CRCPR CRC polynomial register 0x10 0x20 read-write 0x0007 CRCPOLY CRC polynomial register 0 16 RXCRCR RXCRCR RX CRC register 0x14 0x20 read-only 0x0000 RxCRC Rx CRC register 0 16 TXCRCR TXCRCR TX CRC register 0x18 0x20 read-only 0x0000 TxCRC Tx CRC register 0 16 I2SCFGR I2SCFGR configuration register 0x1C 0x20 read-write 0x0000 CHLEN Channel length (number of bits per audio channel) 0 1 DATLEN Data length to be transferred 1 2 CKPOL Inactive state clock polarity 3 1 I2SSTD standard selection 4 2 PCMSYNC PCM frame synchronization 7 1 I2SCFG I2S configuration mode 8 2 SE2 I2S enable 10 1 I2SMOD I2S mode selection 11 1 I2SPR I2SPR prescaler register 0x20 0x20 read-write 0x0000 I2SDIV linear prescaler 0 8 ODD Odd factor for the prescaler 8 1 MCKOE Master clock output enable 9 1 HWCFGR HWCFGR hardware configuration register 0x3F0 0x20 read-only 0x0000 CRCCFG CRC capable at SPI mode 0 4 I2SCFG I2S mode implementation 4 4 I2SCKCFG I2S master clock generator at I2S mode 8 4 DSCFG SPI data size configuration 12 4 NSSCFG NSS pulse feature enhancement at SPI master 16 4 VERR VERR EXTI IP Version register 0x3F4 0x20 read-only 0x00000000 MINREV Minor Revision number 0 4 MAJREV Major Revision number 4 4 IPIDR IPIDR EXTI Identification register 0x3F8 0x20 read-only 0x00000000 IPID IP Identification 0 32 SIDR SIDR EXTI Size ID register 0x3FC 0x20 read-only 0x00000000 SID Size Identification 0 32 SPI2 0x40003800 SPI2 SPI2 global interrupt 26 TIM1 Advanced-timers TIM 0x40012C00 0x0 0x400 registers TIM1_BRK_UP_TRG_COMP TIM1 break, update, trigger 13 TIM1_CC TIM1 Capture Compare interrupt 14 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CEN Counter enable 0 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 URS Update request source 2 1 DIR Direction 4 1 CMS Center-aligned mode selection 5 2 ARPE Auto-reload preload enable 7 1 CKD Clock division 8 2 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 MMS2 Master mode selection 2 20 4 OIS6 Output Idle state 6 (OC6 output) 18 1 OIS5 Output Idle state 5 (OC5 output) 16 1 OIS4 Output Idle state 4 14 1 OIS3N Output Idle state 3 13 1 OIS3 Output Idle state 3 12 1 OIS2N Output Idle state 2 11 1 OIS2 Output Idle state 2 10 1 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 SMS Slave mode selection 0 3 OCCS OCREF clear selection 3 1 TS_4 Trigger selection 4 3 MSM Master/Slave mode 7 1 ETF External trigger filter 8 4 ETPS External trigger prescaler 12 2 ECE External clock enable 14 1 ETP External trigger polarity 15 1 SMS_3 Slave mode selection - bit 3 16 1 TS Trigger selection 20 2 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 UIE Update interrupt enable 0 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMIE COM interrupt enable 5 1 TIE Trigger interrupt enable 6 1 BIE Break interrupt enable 7 1 UDE Update DMA request enable 8 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC4DE Capture/Compare 4 DMA request enable 12 1 COMDE COM DMA request enable 13 1 TDE Trigger DMA request enable 14 1 SR SR status register 0x10 0x20 read-write 0x0000 UIF Update interrupt flag 0 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC4IF Capture/Compare 4 interrupt flag 4 1 COMIF COM interrupt flag 5 1 TIF Trigger interrupt flag 6 1 BIF Break interrupt flag 7 1 B2IF Break 2 interrupt flag 8 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4OF Capture/Compare 4 overcapture flag 12 1 SBIF System Break interrupt flag 13 1 CC5IF Compare 5 interrupt flag 16 1 CC6IF Compare 6 interrupt flag 17 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 UG Update generation 0 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 COMG Capture/Compare control update generation 5 1 TG Trigger generation 6 1 BG Break generation 7 1 B2G Break 2 generation 8 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 CC1S Capture/Compare 1 selection 0 2 OC1FE Output Compare 1 fast enable 2 1 OC1PE Output Compare 1 preload enable 3 1 OC1M Output Compare 1 mode 4 3 OC1CE Output Compare 1 clear enable 7 1 CC2S Capture/Compare 2 selection 8 2 OC2FE Output Compare 2 fast enable 10 1 OC2PE Output Compare 2 preload enable 11 1 OC2M Output Compare 2 mode 12 3 OC2CE Output Compare 2 clear enable 15 1 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC2M_3 Output Compare 2 mode - bit 3 24 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (output mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 CC1S Capture/Compare 1 selection 0 2 OC1FE Output Compare 1 fast enable 2 1 OC1PE Output Compare 1 preload enable 3 1 OC1M Output Compare 1 mode 4 3 OC1CE Output Compare 1 clear enable 7 1 CC2S Capture/Compare 2 selection 8 2 OC2FE Output Compare 2 fast enable 10 1 OC2PE Output Compare 2 preload enable 11 1 OC2M Output Compare 2 mode 12 3 OC2CE Output Compare 2 clear enable 15 1 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 CC3S Capture/Compare 3 selection 0 2 OC3FE Output compare 3 fast enable 2 1 OC3PE Output compare 3 preload enable 3 1 OC3M Output compare 3 mode 4 3 OC3CE Output compare 3 clear enable 7 1 CC4S Capture/Compare 4 selection 8 2 OC4FE Output compare 4 fast enable 10 1 OC4PE Output compare 4 preload enable 11 1 OC4M Output compare 4 mode 12 3 OC4CE Output compare 4 clear enable 15 1 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC4M_3 Output Compare 4 mode - bit 3 24 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (output mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 CC3S Capture/Compare 3 selection 0 2 OC3FE Output compare 3 fast enable 2 1 OC3PE Output compare 3 preload enable 3 1 OC3M Output compare 3 mode 4 3 OC3CE Output compare 3 clear enable 7 1 CC4S Capture/Compare 4 selection 8 2 OC4FE Output compare 4 fast enable 10 1 OC4PE Output compare 4 preload enable 11 1 OC4M Output compare 4 mode 12 3 OC4CE Output compare 4 clear enable 15 1 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1E Capture/Compare 1 output enable 0 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC2E Capture/Compare 2 output enable 4 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC3E Capture/Compare 3 output enable 8 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC4E Capture/Compare 4 output enable 12 1 CC4P Capture/Compare 3 output Polarity 13 1 CC4NP Capture/Compare 4 complementary output polarity 15 1 CC5E Capture/Compare 5 output enable 16 1 CC5P Capture/Compare 5 output polarity 17 1 CC6E Capture/Compare 6 output enable 20 1 CC6P Capture/Compare 6 output polarity 21 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write UIFCPY UIF copy 31 1 read-only PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2 Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3 Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4 Capture/Compare value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 BKE Break enable 12 1 BKP Break polarity 13 1 AOE Automatic output enable 14 1 MOE Main output enable 15 1 BKF Break filter 16 4 BK2F Break 2 filter 20 4 BK2E Break 2 enable 24 1 BK2P Break 2 polarity 25 1 BKDSRM Break Disarm 26 1 BK2DSRM Break2 Disarm 27 1 BKBID Break Bidirectional 28 1 BK2ID Break2 bidirectional 29 1 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 OR1 OR1 option register 1 0x50 0x20 read-write 0x0000 OCREF_CLR Ocref_clr source selection 0 1 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x54 0x20 read-write 0x00000000 OC6M_bit3 Output Compare 6 mode bit 3 24 1 OC5M_bit3 Output Compare 5 mode bit 3 16 1 OC6CE Output compare 6 clear enable 15 1 OC6M Output compare 6 mode 12 3 OC6PE Output compare 6 preload enable 11 1 OC6FE Output compare 6 fast enable 10 1 OC5CE Output compare 5 clear enable 7 1 OC5M Output compare 5 mode 4 3 OC5PE Output compare 5 preload enable 3 1 OC5FE Output compare 5 fast enable 2 1 CCR5 CCR5 capture/compare register 4 0x58 0x20 read-write 0x00000000 CCR5 Capture/Compare value 0 16 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 4 0x5C 0x20 read-write 0x00000000 CCR6 Capture/Compare value 0 16 AF1 AF1 DMA address for full transfer 0x60 0x20 read-write 0x00000001 BKINE BRK BKIN input enable 0 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP2E BRK COMP2 enable 2 1 BKINP BRK BKIN input polarity 9 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2P BRK COMP2 input polarity 11 1 ETRSEL ETR source selection 14 3 AF2 AF2 DMA address for full transfer 0x64 0x20 read-write 0x00000001 BK2INE BRK2 BKIN input enable 0 1 BK2CMP1E BRK2 COMP1 enable 1 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2DFBK0E BRK2 DFSDM_BREAK0 enable 8 1 BK2INP BRK2 BKIN input polarity 9 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 COMP COMP1 COMP1 0x40010200 0x0 0x200 registers COMP1_CSR COMP1_CSR Comparator 1 control and status register 0x0 0x20 read-write 0x00000000 EN COMP channel 1 enable bit 0 1 INMSEL Comparator 2 signal selector for inverting input INM 4 4 INPSEL Comparator 2 signal selector for non-inverting input 8 2 WINMODE Comparator 2 non-inverting input selector for window mode 11 1 WINOUT Comparator 2 output selector 14 1 POLARITY Comparator 2 polarity selector 15 1 HYST Comparator 2 hysteresis selector 16 2 PWRMODE Comparator 2 power mode selector 18 2 BLANKSEL Comparator 2 blanking source selector 20 5 VALUE Comparator 2 output status 30 1 LOCK COMP2_CSR register lock 31 1 COMP2_CSR COMP2_CSR Comparator 2 control and status register 0x4 0x20 read-write 0x00000000 EN COMP channel 1 enable bit 0 1 INMSEL Comparator 2 signal selector for inverting input INM 4 4 INPSEL Comparator 2 signal selector for non-inverting input 8 2 WINMODE Comparator 2 non-inverting input selector for window mode 11 1 WINOUT Comparator 2 output selector 14 1 POLARITY Comparator 2 polarity selector 15 1 HYST Comparator 2 hysteresis selector 16 2 PWRMODE Comparator 2 power mode selector 18 2 BLANKSEL Comparator 2 blanking source selector 20 5 VALUE Comparator 2 output status 30 1 LOCK COMP2_CSR register lock 31 1 SYSCFG System configuration controller SYSCFG 0x40010000 0x0 0x100 registers CFGR1 CFGR1 SYSCFG configuration register 1 0x0 0x20 read-write 0x00000000 I2C3_FMP I2C3_FMP 24 1 I2C_PA10_FMP Fast Mode Plus (FM+) driving capability activation bits 23 1 I2C_PA9_FMP Fast Mode Plus (FM+) driving capability activation bits 22 1 I2C2_FMP FM+ driving capability activation for I2C2 21 1 I2C1_FMP FM+ driving capability activation for I2C1 20 1 I2C_PB9_FMP I2C_PB9_FMP 19 4 I2C_PB8_FMP I2C_PB8_FMP 18 4 I2C_PB7_FMP I2C_PB7_FMP 17 4 I2C_PBx_FMP Fast Mode Plus (FM+) driving capability activation bits 16 4 UCPD2_STROBE Strobe signal bit for UCPD2 10 1 UCPD1_STROBE Strobe signal bit for UCPD1 9 1 BOOSTEN I/O analog switch voltage booster enable 8 1 IR_MOD IR Modulation Envelope signal selection. 6 2 IR_POL IR output polarity selection 5 1 PA12_RMP PA11 and PA12 remapping bit. 4 1 PA11_RMP PA11_RMP 3 1 MEM_MODE Memory mapping selection bits 0 2 CFGR2 CFGR2 SYSCFG configuration register 1 0x18 0x20 read-write 0x00000000 LOCKUP_LOCK Cortex-M0+ LOCKUP bit enable bit 0 1 SRAM_PARITY_LOCK SRAM parity lock bit 1 1 ECC_LOCK ECC error lock bit 3 1 SRAM_PEF SRAM parity error flag 8 1 ITLINE0 ITLINE0 interrupt line 0 status register 0x80 0x20 read-only 0x00000000 WWDG Window watchdog interrupt pending flag 0 1 ITLINE2 ITLINE2 interrupt line 2 status register 0x88 0x20 read-only 0x00000000 TAMP TAMP 0 1 RTC RTC 1 1 ITLINE3 ITLINE3 interrupt line 3 status register 0x8C 0x20 read-only 0x00000000 FLASH_ITF FLASH_ITF 0 1 FLASH_ECC FLASH_ECC 1 1 ITLINE4 ITLINE4 interrupt line 4 status register 0x90 0x20 read-only 0x00000000 RCC RCC 0 1 ITLINE5 ITLINE5 interrupt line 5 status register 0x94 0x20 read-only 0x00000000 EXTI0 EXTI0 0 1 EXTI1 EXTI1 1 1 ITLINE6 ITLINE6 interrupt line 6 status register 0x98 0x20 read-only 0x00000000 EXTI2 EXTI2 0 1 EXTI3 EXTI3 1 1 ITLINE7 ITLINE7 interrupt line 7 status register 0x9C 0x20 read-only 0x00000000 EXTI4 EXTI4 0 1 EXTI5 EXTI5 1 1 EXTI6 EXTI6 2 1 EXTI7 EXTI7 3 1 EXTI8 EXTI8 4 1 EXTI9 EXTI9 5 1 EXTI10 EXTI10 6 1 EXTI11 EXTI11 7 1 EXTI12 EXTI12 8 1 EXTI13 EXTI13 9 1 EXTI14 EXTI14 10 1 EXTI15 EXTI15 11 1 ITLINE8 ITLINE8 interrupt line 8 status register 0xA0 0x20 read-only 0x00000000 USB USB 2 1 ITLINE9 ITLINE9 interrupt line 9 status register 0xA4 0x20 read-only 0x00000000 DMA1_CH1 DMA1_CH1 0 1 ITLINE10 ITLINE10 interrupt line 10 status register 0xA8 0x20 read-only 0x00000000 DMA1_CH2 DMA1_CH1 0 1 DMA1_CH3 DMA1_CH3 1 1 ITLINE11 ITLINE11 interrupt line 11 status register 0xAC 0x20 read-only 0x00000000 DMAMUX DMAMUX 0 1 DMA1_CH4 DMA1_CH4 1 1 DMA1_CH5 DMA1_CH5 2 1 DMA1_CH6 DMA1_CH6 3 1 DMA1_CH7 DMA1_CH7 4 1 DMA2_CH1 DMA2_CH1 5 1 DMA2_CH2 DMA2_CH2 6 1 DMA2_CH3 DMA2_CH3 7 1 DMA2_CH4 DMA2_CH4 8 1 DMA2_CH5 DMA2_CH5 9 1 ITLINE12 ITLINE12 interrupt line 12 status register 0xB0 0x20 read-only 0x00000000 ADC ADC 0 1 ITLINE13 ITLINE13 interrupt line 13 status register 0xB4 0x20 read-only 0x00000000 TIM1_CCU TIM1_CCU 0 1 TIM1_TRG TIM1_TRG 1 1 TIM1_UPD TIM1_UPD 2 1 TIM1_BRK TIM1_BRK 3 1 ITLINE14 ITLINE14 interrupt line 14 status register 0xB8 0x20 read-only 0x00000000 TIM1_CC TIM1_CC 0 1 ITLINE16 ITLINE16 interrupt line 16 status register 0xC0 0x20 read-only 0x00000000 TIM3 TIM3 0 1 TIM4 TIM4 1 1 ITLINE17 ITLINE17 interrupt line 17 status register 0xC4 0x20 read-only 0x00000000 TIM6 TIM6 0 1 ITLINE18 ITLINE18 interrupt line 18 status register 0xC8 0x20 read-only 0x00000000 TIM7 TIM7 0 1 ITLINE19 ITLINE19 interrupt line 19 status register 0xCC 0x20 read-only 0x00000000 TIM14 TIM14 0 1 ITLINE20 ITLINE20 interrupt line 20 status register 0xD0 0x20 read-only 0x00000000 TIM15 TIM15 0 1 ITLINE21 ITLINE21 interrupt line 21 status register 0xD4 0x20 read-only 0x00000000 TIM16 TIM16 0 1 ITLINE22 ITLINE22 interrupt line 22 status register 0xD8 0x20 read-only 0x00000000 TIM17 TIM17 0 1 ITLINE23 ITLINE23 interrupt line 23 status register 0xDC 0x20 read-only 0x00000000 I2C1 I2C1 0 1 ITLINE24 ITLINE24 interrupt line 24 status register 0xE0 0x20 read-only 0x00000000 I2C2 I2C2 0 1 I2C3 I2C3 1 1 ITLINE25 ITLINE25 interrupt line 25 status register 0xE4 0x20 read-only 0x00000000 SPI1 SPI1 0 1 ITLINE26 ITLINE26 interrupt line 26 status register 0xE8 0x20 read-only 0x00000000 SPI2 SPI2 0 1 SPI3 SPI3 14 1 ITLINE27 ITLINE27 interrupt line 27 status register 0xEC 0x20 read-only 0x00000000 USART1 USART1 0 1 ITLINE28 ITLINE28 interrupt line 28 status register 0xF0 0x20 read-only 0x00000000 USART2 USART2 0 1 ITLINE29 ITLINE29 interrupt line 29 status register 0xF4 0x20 read-only 0x00000000 USART3 USART3 0 1 USART4 USART4 1 1 USART5 USART5 3 1 USART6 USART6 4 1 TAMP Tamper and backup registers TAMP 0x4000B000 0x0 0x400 registers TAMP_CR1 TAMP_CR1 TAMP control register 1 0x0 0x20 0xFFFF0000 0xFFFFFFFF TAMP1E Tamper detection on TAMP_IN1 enable 0 1 read-write B_0x0 Tamper detection on TAMP_IN1 is disabled. 0x0 B_0x1 Tamper detection on TAMP_IN1 is enabled. 0x1 TAMP2E Tamper detection on TAMP_IN2 enable 1 1 read-write B_0x0 Tamper detection on TAMP_IN2 is disabled. 0x0 B_0x1 Tamper detection on TAMP_IN2 is enabled. 0x1 TAMP3E Tamper detection on TAMP_IN3 enable 2 1 read-write B_0x0 Tamper detection on TAMP_IN3 is disabled. 0x0 B_0x1 Tamper detection on TAMP_IN3 is enabled. 0x1 ITAMP3E Internal tamper 3 enable: LSE monitoring 18 1 read-write B_0x0 Internal tamper 3 disabled. 0x0 B_0x1 Internal tamper 3 enabled: a tamper is generated when the LSE frequency is below or above thresholds. 0x1 ITAMP4E Internal tamper 4 enable: HSE monitoring 19 1 read-write B_0x0 Internal tamper 4 disabled. 0x0 B_0x1 Internal tamper 4 enabled. a tamper is generated when the HSE frequency is below or above thresholds. 0x1 ITAMP5E Internal tamper 5 enable: RTC calendar overflow 20 1 read-write B_0x0 Internal tamper 5 disabled. 0x0 B_0x1 Internal tamper 5 enabled: a tamper is generated when the RTC calendar reaches its maximum value, on the 31st of December 99, at 23:59:59. The calendar is then frozen and cannot overflow. 0x1 ITAMP6E Internal tamper 6 enable: ST manufacturer readout 21 1 read-write B_0x0 Internal tamper 6 disabled. 0x0 B_0x1 Internal tamper 6 enabled: a tamper is generated in case of ST manufacturer readout. 0x1 TAMP_CR2 TAMP_CR2 TAMP control register 2 0x4 0x20 0x00000000 0xFFFFFFFF TAMP1NOER Tamper 1 no erase 0 1 read-write B_0x0 Tamper 1 event erases the backup registers. 0x0 B_0x1 Tamper 1 event does not erase the backup registers. 0x1 TAMP2NOER Tamper 2 no erase 1 1 read-write B_0x0 Tamper 2 event erases the backup registers. 0x0 B_0x1 Tamper 2 event does not erase the backup registers. 0x1 TAMP3NOER Tamper 3 no erase 2 1 read-write B_0x0 Tamper 3 event erases the backup registers. 0x0 B_0x1 Tamper 3 event does not erase the backup registers. 0x1 TAMP1MSK Tamper 1 mask The tamper 1 interrupt must not be enabled when TAMP1MSK is set. 16 1 read-write B_0x0 Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection. 0x0 B_0x1 Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers are not erased. 0x1 TAMP2MSK Tamper 2 mask The tamper 2 interrupt must not be enabled when TAMP2MSK is set. 17 1 read-write B_0x0 Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to allow next tamper event detection. 0x0 B_0x1 Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. 0x1 TAMP3MSK Tamper 3 mask The tamper 3 interrupt must not be enabled when TAMP3MSK is set. 18 1 read-write B_0x0 Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to allow next tamper event detection. 0x0 B_0x1 Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased. 0x1 TAMP1TRG Active level for tamper 1 input (active mode disabled) If TAMPFLT = 00 Tamper 1 input rising edge and high level triggers a tamper detection event. If TAMPFLT = 00 Tamper 1 input falling edge and low level triggers a tamper detection event. 24 1 read-write B_0x0 If TAMPFLT ≠ 00 Tamper 1 input staying low triggers a tamper detection event. 0x0 B_0x1 If TAMPFLT ≠ 00 Tamper 1 input staying high triggers a tamper detection event. 0x1 TAMP2TRG Active level for tamper 2 input (active mode disabled) If TAMPFLT = 00 Tamper 2 input rising edge and high level triggers a tamper detection event. If TAMPFLT = 00 Tamper 2 input falling edge and low level triggers a tamper detection event. 25 1 read-write B_0x0 If TAMPFLT ≠ 00 Tamper 2 input staying low triggers a tamper detection event. 0x0 B_0x1 If TAMPFLT ≠ 00 Tamper 2 input staying high triggers a tamper detection event. 0x1 TAMP3TRG Active level for tamper 3 input (active mode disabled) If TAMPFLT = 00 Tamper 3 input rising edge and high level triggers a tamper detection event. If TAMPFLT = 00 Tamper 3 input falling edge and low level triggers a tamper detection event. 26 1 read-write B_0x0 If TAMPFLT ≠ 00 Tamper 3 input staying low triggers a tamper detection event. 0x0 B_0x1 If TAMPFLT ≠ 00 Tamper 3 input staying high triggers a tamper detection event. 0x1 TAMP_FLTCR TAMP_FLTCR TAMP filter control register 0xc 0x20 0x00000000 0xFFFFFFFF TAMPFREQ Tamper sampling frequency Determines the frequency at which each of the TAMP_INx inputs are sampled. 0 3 read-write B_0x0 RTCCLK / 32768 (1Hz when RTCCLK = 32768Hz) 0x0 B_0x1 RTCCLK / 16384 (2Hz when RTCCLK = 32768Hz) 0x1 B_0x2 RTCCLK / 8192 (4Hz when RTCCLK = 32768Hz) 0x2 B_0x3 RTCCLK / 4096 (8Hz when RTCCLK = 32768Hz) 0x3 B_0x4 RTCCLK / 2048 (16Hz when RTCCLK = 32768Hz) 0x4 B_0x5 RTCCLK / 1024 (32Hz when RTCCLK = 32768Hz) 0x5 B_0x6 RTCCLK / 512 (64Hz when RTCCLK = 32768Hz) 0x6 B_0x7 RTCCLK / 256 (128Hz when RTCCLK = 32768Hz) 0x7 TAMPFLT TAMP_INx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the TAMP_INx inputs. 3 2 read-write B_0x0 Tamper event is activated on edge of TAMP_INx input transitions to the active level (no internal pull-up on TAMP_INx input). 0x0 B_0x1 Tamper event is activated after 2 consecutive samples at the active level. 0x1 B_0x2 Tamper event is activated after 4 consecutive samples at the active level. 0x2 B_0x3 Tamper event is activated after 8 consecutive samples at the active level. 0x3 TAMPPRCH TAMP_INx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the TAMP_INx inputs. 5 2 read-write B_0x0 1 RTCCLK cycle 0x0 B_0x1 2 RTCCLK cycles 0x1 B_0x2 4 RTCCLK cycles 0x2 B_0x3 8 RTCCLK cycles 0x3 TAMPPUDIS TAMP_INx pull-up disable This bit determines if each of the TAMPx pins are precharged before each sample. 7 1 read-write B_0x0 Precharge TAMP_INx pins before sampling (enable internal pull-up) 0x0 B_0x1 Disable precharge of TAMP_INx pins. 0x1 TAMP_IER TAMP_IER TAMP interrupt enable register 0x2c 0x20 0x00000000 0xFFFFFFFF TAMP1IE Tamper 1 interrupt enable 0 1 read-write B_0x0 Tamper 1 interrupt disabled. 0x0 B_0x1 Tamper 1 interrupt enabled. 0x1 TAMP2IE Tamper 2 interrupt enable 1 1 read-write B_0x0 Tamper 2 interrupt disabled. 0x0 B_0x1 Tamper 2 interrupt enabled. 0x1 TAMP3IE Tamper 3 interrupt enable 2 1 read-write B_0x0 Tamper 3 interrupt disabled. 0x0 B_0x1 Tamper 3 interrupt enabled.. 0x1 ITAMP3IE Internal tamper 3 interrupt enable: LSE monitoring 18 1 read-write B_0x0 Internal tamper 3 interrupt disabled. 0x0 B_0x1 Internal tamper 3 interrupt enabled. 0x1 ITAMP4IE Internal tamper 4 interrupt enable: HSE monitoring 19 1 read-write B_0x0 Internal tamper 4 interrupt disabled. 0x0 B_0x1 Internal tamper 4 interrupt enabled. 0x1 ITAMP5IE Internal tamper 5 interrupt enable: RTC calendar overflow 20 1 read-write B_0x0 Internal tamper 5 interrupt disabled. 0x0 B_0x1 Internal tamper 5 interrupt enabled. 0x1 ITAMP6IE Internal tamper 6 interrupt enable: ST manufacturer readout 21 1 read-write B_0x0 Internal tamper 6 interrupt disabled. 0x0 B_0x1 Internal tamper 6 interrupt enabled. 0x1 TAMP_SR TAMP_SR TAMP status register 0x30 0x20 0x00000000 0xFFFFFFFF TAMP1F TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP1 input. 0 1 read-only TAMP2F TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP2 input. 1 1 read-only TAMP3F TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP3 input. 2 1 read-only ITAMP3F LSE monitoring tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 3. 18 1 read-only ITAMP4F HSE monitoring tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 4. 19 1 read-only ITAMP5F RTC calendar overflow tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 5. 20 1 read-only ITAMP6F ST manufacturer readout tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 6. 21 1 read-only TAMP_MISR TAMP_MISR TAMP masked interrupt status register 0x34 0x20 0x00000000 0xFFFFFFFF TAMP1MF TAMP1 interrupt masked flag This flag is set by hardware when the tamper 1 interrupt is raised. 0 1 read-only TAMP2MF TAMP2 interrupt masked flag This flag is set by hardware when the tamper 2 interrupt is raised. 1 1 read-only TAMP3MF TAMP3 interrupt masked flag This flag is set by hardware when the tamper 3 interrupt is raised. 2 1 read-only ITAMP3MF LSE monitoring tamper interrupt masked flag This flag is set by hardware when the internal tamper 3 interrupt is raised. 18 1 read-only ITAMP4MF HSE monitoring tamper interrupt masked flag This flag is set by hardware when the internal tamper 4 interrupt is raised. 19 1 read-only ITAMP5MF RTC calendar overflow tamper interrupt masked flag This flag is set by hardware when the internal tamper 5 interrupt is raised. 20 1 read-only ITAMP6MF ST manufacturer readout tamper interrupt masked flag This flag is set by hardware when the internal tamper 6 interrupt is raised. 21 1 read-only TAMP_SCR TAMP_SCR TAMP status clear register 0x3c 0x20 0x00000000 0xFFFFFFFF CTAMP1F Clear TAMP1 detection flag Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register. 0 1 write-only CTAMP2F Clear TAMP2 detection flag Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register. 1 1 write-only CTAMP3F Clear TAMP3 detection flag Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register. 2 1 write-only CITAMP3F Clear ITAMP3 detection flag Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register. 18 1 write-only CITAMP4F Clear ITAMP4 detection flag Writing 1 in this bit clears the ITAMP4F bit in the TAMP_SR register. 19 1 write-only CITAMP5F Clear ITAMP5 detection flag Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register. 20 1 write-only CITAMP6F Clear ITAMP6 detection flag Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register. 21 1 write-only TAMP_BKP0R TAMP_BKP0R TAMP backup 0 register 0x100 0x20 0x00000000 0xFFFFFFFF BKP The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. 0 32 read-write TAMP_BKP1R TAMP_BKP1R TAMP backup 1 register 0x104 0x20 0x00000000 0xFFFFFFFF BKP The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. 0 32 read-write TAMP_BKP2R TAMP_BKP2R TAMP backup 2 register 0x108 0x20 0x00000000 0xFFFFFFFF BKP The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. 0 32 read-write TAMP_BKP3R TAMP_BKP3R TAMP backup 3 register 0x10c 0x20 0x00000000 0xFFFFFFFF BKP The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. 0 32 read-write TAMP_BKP4R TAMP_BKP4R TAMP backup 4 register 0x110 0x20 0x00000000 0xFFFFFFFF BKP The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. 0 32 read-write UCPD1 USB Power Delivery interface UCPD 0x4000A000 0x0 0x400 registers UCPD1_UCPD2 UCPD global interrupt 8 CFG1 CFG1 UCPD configuration register 0x0 0x20 read-write 0x00000000 HBITCLKDIV HBITCLKDIV 0 6 IFRGAP IFRGAP 6 5 TRANSWIN TRANSWIN 11 5 PSC_USBPDCLK PSC_USBPDCLK 17 3 RXORDSETEN RXORDSETEN 20 9 TXDMAEN TXDMAEN 29 1 RXDMAEN RXDMAEN: 30 1 UCPDEN UCPDEN 31 1 CFG2 CFG2 UCPD configuration register 2 0x4 0x20 read-write 0x00000000 RXFILTDIS RXFILTDIS 0 1 RXFILT2N3 RXFILT2N3 1 1 FORCECLK FORCECLK 2 1 WUPEN WUPEN 3 1 CFG3 CFG3 UCPD configuration register 3 0x8 0x20 read-write 0x00000000 TRIM1_NG_CCRPD TRIM1_NG_CCRPD 0 4 TRIM1_NG_CC1A5 TRIM1_NG_CC1A5 4 5 TRIM1_NG_CC3A0 TRIM1_NG_CC3A0 9 4 TRIM2_NG_CCRPD TRIM2_NG_CCRPD 16 4 TRIM2_NG_CC1A5 TRIM2_NG_CC1A5 20 5 TRIM2_NG_CC3A0 TRIM2_NG_CC3A0 25 4 CR CR UCPD control register 0xC 0x20 read-write 0x00000000 TXMODE TXMODE 0 2 TXSEND TXSEND 2 1 TXHRST TXHRST 3 1 RXMODE RXMODE 4 1 PHYRXEN PHYRXEN 5 1 PHYCCSEL PHYCCSEL 6 1 ANASUBMODE ANASUBMODE 7 2 ANAMODE ANAMODE 9 1 CCENABLE CCENABLE 10 2 DBATTEN DBATTEN 15 1 FRSRXEN FRSRXEN 16 1 FRSTX FRSTX 17 1 RDCH RDCH 18 1 CC1TCDIS CC1TCDIS 20 1 CC2TCDIS CC2TCDIS 21 1 IMR IMR UCPD Interrupt Mask Register 0x10 0x20 read-write 0x00000000 TXISIE TXISIE 0 1 TXMSGDISCIE TXMSGDISCIE 1 1 TXMSGSENTIE TXMSGSENTIE 2 1 TXMSGABTIE TXMSGABTIE 3 1 HRSTDISCIE HRSTDISCIE 4 1 HRSTSENTIE HRSTSENTIE 5 1 TXUNDIE TXUNDIE 6 1 RXNEIE RXNEIE 8 1 RXORDDETIE RXORDDETIE 9 1 RXHRSTDETIE RXHRSTDETIE 10 1 RXOVRIE RXOVRIE 11 1 RXMSGENDIE RXMSGENDIE 12 1 TYPECEVT1IE TYPECEVT1IE 14 1 TYPECEVT2IE TYPECEVT2IE 15 1 FRSEVTIE FRSEVTIE 20 1 SR SR UCPD Status Register 0x14 0x20 read-only 0x00000000 TXIS TXIS 0 1 TXMSGDISC TXMSGDISC 1 1 TXMSGSENT TXMSGSENT 2 1 TXMSGABT TXMSGABT 3 1 HRSTDISC HRSTDISC 4 1 HRSTSENT HRSTSENT 5 1 TXUND TXUND 6 1 RXNE RXNE 8 1 RXORDDET RXORDDET 9 1 RXHRSTDET RXHRSTDET 10 1 RXOVR RXOVR 11 1 RXMSGEND RXMSGEND 12 1 RXERR RXERR 13 1 TYPECEVT1 TYPECEVT1 14 1 TYPECEVT2 TYPECEVT2 15 1 TYPEC_VSTATE_CC1 TYPEC_VSTATE_CC1 16 2 TYPEC_VSTATE_CC2 TYPEC_VSTATE_CC2 18 2 FRSEVT FRSEVT 20 1 ICR ICR UCPD Interrupt Clear Register 0x18 0x20 read-write 0x00000000 TXMSGDISCCF TXMSGDISCCF 1 1 TXMSGSENTCF TXMSGSENTCF 2 1 TXMSGABTCF TXMSGABTCF 3 1 HRSTDISCCF HRSTDISCCF 4 1 HRSTSENTCF HRSTSENTCF 5 1 TXUNDCF TXUNDCF 6 1 RXORDDETCF RXORDDETCF 9 1 RXHRSTDETCF RXHRSTDETCF 10 1 RXOVRCF RXOVRCF 11 1 RXMSGENDCF RXMSGENDCF 12 1 TYPECEVT1CF TYPECEVT1CF 14 1 TYPECEVT2CF TYPECEVT2CF 15 1 FRSEVTCF FRSEVTCF 20 1 TX_ORDSET TX_ORDSET UCPD Tx Ordered Set Type Register 0x1C 0x20 read-write 0x00000000 TXORDSET TXORDSET 0 20 TX_PAYSZ TX_PAYSZ UCPD Tx Paysize Register 0x20 0x20 read-write 0x00000000 TXPAYSZ TXPAYSZ 0 10 TXDR TXDR UCPD Tx Data Register 0x24 0x20 read-write 0x00000000 TXDATA TXDATA 0 8 RX_ORDSET RX_ORDSET UCPD Rx Ordered Set Register 0x28 0x20 read-only 0x00000000 RXORDSET RXORDSET 0 3 RXSOP3OF4 RXSOP3OF4 3 1 RXSOPKINVALID RXSOPKINVALID 4 3 RX_PAYSZ RX_PAYSZ UCPD Rx Paysize Register 0x2C 0x20 read-write 0x00000000 RXPAYSZ RXPAYSZ 0 10 RXDR RXDR UCPD Receive Data Register 0x30 0x20 read-only 0x00000000 RXDATA RXDATA 0 8 RX_ORDEXT1 RX_ORDEXT1 UCPD Rx Ordered Set Extension Register 0x34 0x20 read-write 0x00000000 RXSOPX1 RXSOPX1 0 20 RX_ORDEXT2 RX_ORDEXT2 UCPD Rx Ordered Set Extension Register 0x38 0x20 read-write 0x00000000 RXSOPX2 RXSOPX2 0 20 IPVER IPVER UCPD IP ID register 0x3F4 0x20 read-only 0x00000010 IPVER IPVER 0 32 IPID IPID UCPD IP ID register 0x3F8 0x20 read-only 0x00150021 IPID IPID 0 32 MID MID UCPD IP ID register 0x3FC 0x20 read-only 0xA3C5DD01 IPID IPID 0 32 UCPD2 0x4000A400 LPTIM1 Low power timer LPTIM 0x40007C00 0x0 0x400 registers ISR ISR Interrupt and Status Register 0x0 0x20 read-only 0x00000000 DOWN Counter direction change up to down 6 1 UP Counter direction change down to up 5 1 ARROK Autoreload register update OK 4 1 CMPOK Compare register update OK 3 1 EXTTRIG External trigger edge event 2 1 ARRM Autoreload match 1 1 CMPM Compare match 0 1 ICR ICR Interrupt Clear Register 0x4 0x20 write-only 0x00000000 DOWNCF Direction change to down Clear Flag 6 1 UPCF Direction change to UP Clear Flag 5 1 ARROKCF Autoreload register update OK Clear Flag 4 1 CMPOKCF Compare register update OK Clear Flag 3 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 ARRMCF Autoreload match Clear Flag 1 1 CMPMCF compare match Clear Flag 0 1 IER IER Interrupt Enable Register 0x8 0x20 read-write 0x00000000 DOWNIE Direction change to down Interrupt Enable 6 1 UPIE Direction change to UP Interrupt Enable 5 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 CMPOKIE Compare register update OK Interrupt Enable 3 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 ARRMIE Autoreload match Interrupt Enable 1 1 CMPMIE Compare match Interrupt Enable 0 1 CFGR CFGR Configuration Register 0xC 0x20 read-write 0x00000000 ENC Encoder mode enable 24 1 COUNTMODE counter mode enabled 23 1 PRELOAD Registers update mode 22 1 WAVPOL Waveform shape polarity 21 1 WAVE Waveform shape 20 1 TIMOUT Timeout enable 19 1 TRIGEN Trigger enable and polarity 17 2 TRIGSEL Trigger selector 13 3 PRESC Clock prescaler 9 3 TRGFLT Configurable digital filter for trigger 6 2 CKFLT Configurable digital filter for external clock 3 2 CKPOL Clock Polarity 1 2 CKSEL Clock selector 0 1 CR CR Control Register 0x10 0x20 read-write 0x00000000 RSTARE Reset after read enable 4 1 COUNTRST Counter reset 3 1 CNTSTRT Timer start in continuous mode 2 1 SNGSTRT LPTIM start in single mode 1 1 ENABLE LPTIM Enable 0 1 CMP CMP Compare Register 0x14 0x20 read-write 0x00000000 CMP Compare value 0 16 ARR ARR Autoreload Register 0x18 0x20 read-write 0x00000001 ARR Auto reload value 0 16 CNT CNT Counter Register 0x1C 0x20 read-only 0x00000000 CNT Counter value 0 16 CFGR2 CFGR2 LPTIM configuration register 2 0x24 0x20 read-write 0x00000000 IN2SEL LPTIM1 Input 2 selection 4 2 IN1SEL LPTIMx Input 1 selection 0 2 LPTIM2 0x40009400 LPUART Universal synchronous asynchronous receiver transmitter USART 0x40008000 0x0 0x400 registers CR1 CR1 Control register 1 0x0 0x20 read-write 0x0000 RXFFIE RXFIFO Full interrupt enable 31 1 TXFEIE TXFIFO empty interrupt enable 30 1 FIFOEN FIFO mode enable 29 1 M1 Word length 28 1 DEAT DEAT0 21 5 DEDT0 DEDT0 16 5 CMIE Character match interrupt enable 14 1 MME Mute mode enable 13 1 M0 Word length 12 1 WAKE Receiver wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXEIE interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXNEIE RXNE interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 UESM USART enable in Stop mode 1 1 UE USART enable 0 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x0000 ADD4_7 Address of the USART node 28 4 ADD0_3 Address of the USART node 24 4 MSBFIRST Most significant bit first 19 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 RXINV RX pin active level inversion 16 1 SWAP Swap TX/RX pins 15 1 STOP STOP bits 12 2 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x0000 TXFTCFG TXFIFO threshold configuration 29 3 RXFTIE RXFIFO threshold interrupt enable 28 1 RXFTCFG Receive FIFO threshold configuration 25 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 DEP Driver enable polarity selection 15 1 DEM Driver enable mode 14 1 DDRE DMA Disable on Reception Error 13 1 OVRDIS Overrun Disable 12 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 HDSEL Half-duplex selection 3 1 EIE Error interrupt enable 0 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x0000 BRR BRR 0 20 RQR RQR Request register 0x18 0x20 write-only 0x0000 TXFRQ Transmit data flush request 4 1 RXFRQ Receive data flush request 3 1 MMRQ Mute mode request 2 1 SBKRQ Send break request 1 1 ABRRQ Auto baud rate request 0 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x00C0 TXFT TXFIFO threshold flag 27 1 RXFT RXFIFO threshold flag 26 1 RXFF RXFIFO Full 24 1 TXFE TXFIFO Empty 23 1 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 SBKF SBKF 18 1 CMF CMF 17 1 BUSY BUSY 16 1 CTS CTS 10 1 CTSIF CTSIF 9 1 TXE TXE 7 1 TC TC 6 1 RXNE RXNE 5 1 IDLE IDLE 4 1 ORE ORE 3 1 NF NF 2 1 FE FE 1 1 PE PE 0 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x0000 WUCF Wakeup from Stop mode clear flag 20 1 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 TCCF Transmission complete clear flag 6 1 IDLECF Idle line detected clear flag 4 1 ORECF Overrun error clear flag 3 1 NCF Noise detected clear flag 2 1 FECF Framing error clear flag 1 1 PECF Parity error clear flag 0 1 RDR RDR Receive data register 0x24 0x20 read-only 0x0000 RDR Receive data value 0 9 TDR TDR Transmit data register 0x28 0x20 read-write 0x0000 TDR Transmit data value 0 9 PRESC PRESC Prescaler register 0x2C 0x20 read-write 0x0000 PRESCALER Clock prescaler 0 4 HWCFGR2 HWCFGR2 LPUART Hardware Configuration register 2 0x3EC 0x20 read-write 0x00000013 CFG1 LUART hardware configuration 1 0 4 CFG2 LUART hardware configuration 2 4 4 HWCFGR1 HWCFGR1 LPUART Hardware Configuration register 1 0x3F0 0x20 read-write 0x31100000 CFG1 LUART hardware configuration 1 0 4 CFG2 LUART hardware configuration 2 4 4 CFG3 LUART hardware configuration 1 8 4 CFG4 LUART hardware configuration 2 12 4 CFG5 LUART hardware configuration 2 16 4 CFG6 LUART hardware configuration 2 20 4 CFG7 LUART hardware configuration 2 24 4 CFG8 LUART hardware configuration 2 28 4 VERR VERR EXTI IP Version register 0x3F4 0x20 read-only 0x00000023 MINREV Minor Revision number 0 4 MAJREV Major Revision number 4 4 IPIDR IPIDR EXTI Identification register 0x3F8 0x20 read-only 0x00130003 IPID IP Identification 0 32 SIDR SIDR EXTI Size ID register 0x3FC 0x20 read-only 0xA3C5DD01 SID Size Identification 0 32 HDMI_CEC HDMI-CEC CEC 0x40007800 0x0 0x400 registers CEC_CR CEC_CR CEC control register 0x0 0x20 read-write 0x00000000 CECEN CEC Enable The CECEN bit is set and cleared by software. CECEN=1 starts message reception and enables the TXSOM control. CECEN=0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission. 0 1 TXSOM Tx Start Of Message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-Bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission will start after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND=1), in case of transmission underrun (TXUDR=1), negative acknowledge (TXACKE=1), and transmission error (TXERR=1). It is also cleared by CECEN=0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST=1). TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. Note: TXSOM must be set when CECEN=1 TXSOM must be set when transmission data is available into TXDR HEADERs first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR which is used only for reception 1 1 TXEOM Tx End Of Message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. Note: TXEOM must be set when CECEN=1 TXEOM must be set before writing transmission data to TXDR If TXEOM is set when TXSOM=0, transmitted message will consist of 1 byte (HEADER) only (PING message) 2 1 CEC_CFGR CEC_CFGR This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0. 0x4 0x20 read-write 0x00000000 SFT Signal Free Time SFT bits are set by software. In the SFT=0x0 configuration the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. * 0x0 ** 2.5 Data-Bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST=1, TXERR=1, TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is the new bus initiator ** 6 Data-Bit periods if CEC is the last bus initiator with successful transmission (TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2: 1.5 nominal data bit periods * 0x3: 2.5 nominal data bit periods * 0x4: 3.5 nominal data bit periods * 0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal data bit periods * 0x7: 6.5 nominal data bit periods 0 3 RXTOL Rx-Tolerance The RXTOL bit is set and cleared by software. ** Start-Bit, +/- 200 s rise, +/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350 s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall ** Data-Bit: +/-300 s rise, +/- 500 s fall 3 1 BRESTP Rx-Stop on Bit Rising Error The BRESTP bit is set and cleared by software. 4 1 BREGEN Generate Error-Bit on Bit Rising Error The BREGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon BRE detection with BRESTP=1 in broadcast even if BREGEN=0 5 1 LBPEGEN Generate Error-Bit on Long Bit Period Error The LBPEGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon LBPE detection in broadcast even if LBPEGEN=0 6 1 BRDNOGEN Avoid Error-Bit Generation in Broadcast The BRDNOGEN bit is set and cleared by software. 7 1 SFTOPT SFT Option Bit The SFTOPT bit is set and cleared by software. 8 1 OAR Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN=1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received. 16 15 LSTN Listen mode LSTN bit is set and cleared by software. 31 1 CEC_TXDR CEC_TXDR CEC Tx data register 0x8 0x20 write-only 0x00000000 TXD Tx Data register. TXD is a write-only register containing the data byte to be transmitted. Note: TXD must be written when TXSTART=1 0 8 CEC_RXDR CEC_RXDR CEC Rx Data Register 0xC 0x20 read-only 0x00000000 RXD Rx Data register. RXD is read-only and contains the last data byte which has been received from the CEC line. 0 8 CEC_ISR CEC_ISR CEC Interrupt and Status Register 0x10 0x20 read-write 0x00000000 RXBR Rx-Byte Received The RXBR bit is set by hardware to inform application that a new byte has been received from the CEC line and stored into the RXD buffer. RXBR is cleared by software write at 1. 0 1 RXEND End Of Reception RXEND is set by hardware to inform application that the last byte of a CEC message is received from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR. RXEND is cleared by software write at 1. 1 1 RXOVR Rx-Overrun RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. RXOVR is cleared by software write at 1. 2 1 BRE Rx-Bit Rising Error BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP=1. BRE generates an Error-Bit on the CEC line if BREGEN=1. BRE is cleared by software write at 1. 3 1 SBPE Rx-Short Bit Period Error SBPE is set by hardware in case a Data-Bit waveform is detected with Short Bit Period Error. SBPE is set at the time the anticipated falling edge occurs. SBPE generates an Error-Bit on the CEC line. SBPE is cleared by software write at 1. 4 1 LBPE Rx-Long Bit Period Error LBPE is set by hardware in case a Data-Bit waveform is detected with Long Bit Period Error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an Error-Bit on the CEC line if LBPEGEN=1. In case of broadcast, Error-Bit is generated even in case of LBPEGEN=0. LBPE is cleared by software write at 1. 5 1 RXACKE Rx-Missing Acknowledge In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. RXACKE is cleared by software write at 1. 6 1 ARBLST Arbitration Lost ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. ARBLST is cleared by software write at 1. 7 1 TXBR Tx-Byte Request TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within 6 nominal data-bit periods before transmission underrun error occurs (TXUDR). TXBR is cleared by software write at 1. 8 1 TXEND End of Transmission TXEND is set by hardware to inform application that the last byte of the CEC message has been successfully transmitted. TXEND clears the TXSOM and TXEOM control bits. TXEND is cleared by software write at 1. 9 1 TXUDR Tx-Buffer Underrun In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM control bits. TXUDR is cleared by software write at 1 10 1 TXERR Tx-Error In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM controls. TXERR is cleared by software write at 1. 11 1 TXACKE Tx-Missing Acknowledge Error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. TXACKE is cleared by software write at 1. 12 1 CEC_IER CEC_IER CEC interrupt enable register 0x14 0x20 read-write 0x00000000 RXBRIE Rx-Byte Received Interrupt Enable The RXBRIE bit is set and cleared by software. 0 1 RXENDIE End Of Reception Interrupt Enable The RXENDIE bit is set and cleared by software. 1 1 RXOVRIE Rx-Buffer Overrun Interrupt Enable The RXOVRIE bit is set and cleared by software. 2 1 BREIE Bit Rising Error Interrupt Enable The BREIE bit is set and cleared by software. 3 1 SBPEIE Short Bit Period Error Interrupt Enable The SBPEIE bit is set and cleared by software. 4 1 LBPEIE Long Bit Period Error Interrupt Enable The LBPEIE bit is set and cleared by software. 5 1 RXACKIE Rx-Missing Acknowledge Error Interrupt Enable The RXACKIE bit is set and cleared by software. 6 1 ARBLSTIE Arbitration Lost Interrupt Enable The ARBLSTIE bit is set and cleared by software. 7 1 TXBRIE Tx-Byte Request Interrupt Enable The TXBRIE bit is set and cleared by software. 8 1 TXENDIE Tx-End Of Message Interrupt Enable The TXENDIE bit is set and cleared by software. 9 1 TXUDRIE Tx-Underrun Interrupt Enable The TXUDRIE bit is set and cleared by software. 10 1 TXERRIE Tx-Error Interrupt Enable The TXERRIE bit is set and cleared by software. 11 1 TXACKIE Tx-Missing Acknowledge Error Interrupt Enable The TXACKEIE bit is set and cleared by software. 12 1 DAC DAC DAC 0x40007400 0x0 0x400 registers DAC_CR DAC_CR DAC control register 0x0 0x20 read-write 0x00000000 EN1 DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1. 0 1 TEN1 DAC channel1 trigger enable 1 1 TSEL1 DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). 2 4 WAVE1 DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). 6 2 MAMP1 DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 8 4 DMAEN1 DAC channel1 DMA enable This bit is set and cleared by software. 12 1 DMAUDRIE1 DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software. 13 1 CEN1 DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 14 1 EN2 DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. 16 1 TEN2 DAC channel2 trigger enable 17 1 TSEL2 DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). 18 4 WAVE2 DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) 22 2 MAMP2 DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 24 4 DMAEN2 DAC channel2 DMA enable This bit is set and cleared by software. 28 1 DMAUDRIE2 DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. 29 1 CEN2 DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 30 1 DAC_SWTRGR DAC_SWTRGR DAC software trigger register 0x4 0x20 write-only 0x00000000 SWTRIG1 DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register. 0 1 SWTRIG2 DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. 1 1 DAC_DHR12R1 DAC_DHR12R1 DAC channel1 12-bit right-aligned data holding register 0x8 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 0 12 DAC_DHR12L1 DAC_DHR12L1 DAC channel1 12-bit left aligned data holding register 0xC 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 4 12 DAC_DHR8R1 DAC_DHR8R1 DAC channel1 8-bit right aligned data holding register 0x10 0x20 read-write 0x00000000 DACC1DHR DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 0 8 DAC_DHR12R2 DAC_DHR12R2 DAC channel2 12-bit right aligned data holding register 0x14 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 0 12 DAC_DHR12L2 DAC_DHR12L2 DAC channel2 12-bit left aligned data holding register 0x18 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. 4 12 DAC_DHR8R2 DAC_DHR8R2 DAC channel2 8-bit right-aligned data holding register 0x1C 0x20 read-write 0x00000000 DACC2DHR DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. 0 8 DAC_DHR12RD DAC_DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 0 12 DACC2DHR DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 16 12 DAC_DHR12LD DAC_DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 4 12 DACC2DHR DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 20 12 DAC_DHR8RD DAC_DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 0x20 read-write 0x00000000 DACC1DHR DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 0 8 DACC2DHR DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. 8 8 DAC_DOR1 DAC_DOR1 DAC channel1 data output register 0x2C 0x20 read-only 0x00000000 DACC1DOR DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. 0 12 DAC_DOR2 DAC_DOR2 DAC channel2 data output register 0x30 0x20 read-only 0x00000000 DACC2DOR DAC channel2 data output These bits are read-only, they contain data output for DAC channel2. 0 12 DAC_SR DAC_SR DAC status register 0x34 0x20 0x00000000 DMAUDR1 DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 13 1 read-write CAL_FLAG1 DAC Channel 1 calibration offset status This bit is set and cleared by hardware 14 1 read-only BWST1 DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization). 15 1 read-only DMAUDR2 DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 29 1 read-write CAL_FLAG2 DAC Channel 2 calibration offset status This bit is set and cleared by hardware 30 1 read-only BWST2 DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). 31 1 read-only DAC_CCR DAC_CCR DAC calibration control register 0x38 0x20 read-write 0x00000000 OTRIM1 DAC Channel 1 offset trimming value 0 5 OTRIM2 DAC Channel 2 offset trimming value 16 5 DAC_MCR DAC_MCR DAC mode control register 0x3C 0x20 read-write 0x00000000 MODE1 DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample &amp; hold mode 0 3 MODE2 DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample &amp; hold mode 16 3 DAC_SHSR1 DAC_SHSR1 DAC Sample and Hold sample time register 1 0x40 0x20 read-write 0x00000000 TSAMPLE1 DAC Channel 1 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored. 0 10 DAC_SHSR2 DAC_SHSR2 DAC Sample and Hold sample time register 2 0x44 0x20 read-write 0x00000000 TSAMPLE2 DAC Channel 2 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored. 0 10 DAC_SHHR DAC_SHHR DAC Sample and Hold hold time register 0x48 0x20 read-write 0x00010001 THOLD1 DAC Channel 1 hold Time (only valid in sample &amp; hold mode) Hold time= (THOLD[9:0]) x T LSI 0 10 THOLD2 DAC Channel 2 hold time (only valid in sample &amp; hold mode). Hold time= (THOLD[9:0]) x T LSI 16 10 DAC_SHRR DAC_SHRR DAC Sample and Hold refresh time register 0x4C 0x20 read-write 0x00010001 TREFRESH1 DAC Channel 1 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI 0 8 TREFRESH2 DAC Channel 2 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI 16 8 IP_HWCFGR0 IP_HWCFGR0 DAC IP Hardware Configuration Register 0x3F0 0x20 read-write 0x00001111 DUAL Dual DAC capability 0 4 LFSR Pseudonoise wave generation capability 4 4 TRIANGLE Triangle wave generation capability 8 4 SAMPLE Sample and hold mode capability 12 4 OR_CFG option register bit width 16 8 VERR VERR EXTI IP Version register 0x3F4 0x20 read-only 0x00000031 MINREV Minor Revision number 0 4 MAJREV Major Revision number 4 4 IPIDR IPIDR EXTI Identification register 0x3F8 0x20 read-only 0x00110011 IPID IP Identification 0 32 SIDR SIDR EXTI Size ID register 0x3FC 0x20 read-only 0xA3C5DD01 SID Size Identification 0 32 I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1 I2C1 global interrupt 23 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 PE Peripheral enable 0 1 TXIE TX Interrupt enable 1 1 RXIE RX Interrupt enable 2 1 ADDRIE Address match interrupt enable (slave only) 3 1 NACKIE Not acknowledge received interrupt enable 4 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 ERRIE Error interrupts enable 7 1 DNF Digital noise filter 8 4 ANFOFF Analog noise filter OFF 12 1 TXDMAEN DMA transmission requests enable 14 1 RXDMAEN DMA reception requests enable 15 1 SBC Slave byte control 16 1 NOSTRETCH Clock stretching disable 17 1 WUPEN Wakeup from STOP enable 18 1 GCEN General call enable 19 1 SMBHEN SMBus Host address enable 20 1 SMBDEN SMBus Device Default address enable 21 1 ALERTEN SMBUS alert enable 22 1 PECEN PEC enable 23 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 PECBYTE Packet error checking byte 26 1 AUTOEND Automatic end mode (master mode) 25 1 RELOAD NBYTES reload mode 24 1 NBYTES Number of bytes 16 8 NACK NACK generation (slave mode) 15 1 STOP Stop generation (master mode) 14 1 START Start generation 13 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 ADD10 10-bit addressing mode (master mode) 11 1 RD_WRN Transfer direction (master mode) 10 1 SADD Slave address bit (master mode) 0 10 OAR1 OAR1 Own address register 1 0x8 0x20 read-write 0x00000000 OA1_0 Interface address 0 1 OA1_7_1 Interface address 1 7 OA1_8_9 Interface address 8 2 OA1MODE Own Address 1 10-bit mode 10 1 OA1EN Own Address 1 enable 15 1 OAR2 OAR2 Own address register 2 0xC 0x20 read-write 0x00000000 OA2 Interface address 1 7 OA2MSK Own Address 2 masks 8 3 OA2EN Own Address 2 enable 15 1 TIMINGR TIMINGR Timing register 0x10 0x20 read-write 0x00000000 SCLL SCL low period (master mode) 0 8 SCLH SCL high period (master mode) 8 8 SDADEL Data hold time 16 4 SCLDEL Data setup time 20 4 PRESC Timing prescaler 28 4 TIMEOUTR TIMEOUTR Status register 1 0x14 0x20 read-write 0x00000000 TIMEOUTA Bus timeout A 0 12 TIDLE Idle clock timeout detection 12 1 TIMOUTEN Clock timeout enable 15 1 TIMEOUTB Bus timeout B 16 12 TEXTEN Extended clock timeout enable 31 1 ISR ISR Interrupt and Status register 0x18 0x20 0x00000001 ADDCODE Address match code (Slave mode) 17 7 read-only DIR Transfer direction (Slave mode) 16 1 read-only BUSY Bus busy 15 1 read-only ALERT SMBus alert 13 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only PECERR PEC Error in reception 11 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only TCR Transfer Complete Reload 7 1 read-only TC Transfer Complete (master mode) 6 1 read-only STOPF Stop detection flag 5 1 read-only NACKF Not acknowledge received flag 4 1 read-only ADDR Address matched (slave mode) 3 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only TXIS Transmit interrupt status (transmitters) 1 1 read-write TXE Transmit data register empty (transmitters) 0 1 read-write ICR ICR Interrupt clear register 0x1C 0x20 write-only 0x00000000 ALERTCF Alert flag clear 13 1 TIMOUTCF Timeout detection flag clear 12 1 PECCF PEC Error flag clear 11 1 OVRCF Overrun/Underrun flag clear 10 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 STOPCF Stop detection flag clear 5 1 NACKCF Not Acknowledge flag clear 4 1 ADDRCF Address Matched flag clear 3 1 PECR PECR PEC register 0x20 0x20 read-only 0x00000000 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 0x20 read-only 0x00000000 RXDATA 8-bit receive data 0 8 TXDR TXDR Transmit data register 0x28 0x20 read-write 0x00000000 TXDATA 8-bit transmit data 0 8 I2C2 0x40005800 I2C2 I2C2 global interrupt 24 RTC Real-time clock RTC 0x40002800 0x0 0x400 registers RTC_STAMP RTC and TAMP interrupts 2 RTC_TR RTC_TR RTC time register 0x0 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format 0 4 read-write ST Second tens in BCD format 4 3 read-write MNU Minute units in BCD format 8 4 read-write MNT Minute tens in BCD format 12 3 read-write HU Hour units in BCD format 16 4 read-write HT Hour tens in BCD format 20 2 read-write PM AM/PM notation 22 1 read-write B_0x0 AM or 24-hour format 0x0 B_0x1 PM 0x1 RTC_DR RTC_DR RTC date register 0x4 0x20 0x00002101 0xFFFFFFFF DU Date units in BCD format 0 4 read-write DT Date tens in BCD format 4 2 read-write MU Month units in BCD format 8 4 read-write MT Month tens in BCD format 12 1 read-write WDU Week day units ... 13 3 read-write B_0x0 forbidden 0x0 B_0x1 Monday 0x1 B_0x7 Sunday 0x7 YU Year units in BCD format 16 4 read-write YT Year tens in BCD format 20 4 read-write RTC_SSR RTC_SSR RTC sub second register 0x8 0x20 0x00000000 0xFFFFFFFF SS Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR. 0 16 read-only RTC_ICSR RTC_ICSR RTC initialization control and status register 0xc 0x20 0x00000007 0xFFFFFFFF ALRAWF Alarm A write flag This bit is set by hardware when alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 0 1 read-only B_0x0 Alarm A update not allowed 0x0 B_0x1 Alarm A update allowed 0x1 ALRBWF Alarm B write flag This bit is set by hardware when alarm B values can be changed, after the ALRBE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 1 1 read-only B_0x0 Alarm B update not allowed 0x0 B_0x1 Alarm B update allowed 0x1 WUTWF Wakeup timer write flag This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 2 1 read-only B_0x0 Wakeup timer configuration update not allowed except in initialization mode 0x0 B_0x1 Wakeup timer configuration update allowed 0x1 SHPF Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. 3 1 read-only B_0x0 No shift operation is pending 0x0 B_0x1 A shift operation is pending 0x1 INITS Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state). 4 1 read-only B_0x0 Calendar has not been initialized 0x0 B_0x1 Calendar has been initialized 0x1 RSF Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode. 5 1 read-write B_0x0 Calendar shadow registers not yet synchronized 0x0 B_0x1 Calendar shadow registers synchronized 0x1 INITF Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. 6 1 read-only B_0x0 Calendar registers update is not allowed 0x0 B_0x1 Calendar registers update is allowed 0x1 INIT Initialization mode 7 1 read-write B_0x0 Free running mode 0x0 B_0x1 Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. 0x1 RECALPF Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to . 16 1 read-only RTC_PRER RTC_PRER RTC prescaler register 0x10 0x20 0x007F00FF 0xFFFFFFFF PREDIV_S Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1) 0 15 read-write PREDIV_A Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) 16 7 read-write RTC_WUTR RTC_WUTR RTC wakeup timer register 0x14 0x20 0x0000FFFF 0xFFFFFFFF WUT Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0]+1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register. When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs between WUT and (WUT + 1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden. 0 16 read-write RTC_CR RTC_CR control register 0x18 0x20 0x00000000 0xFFFFFFFF WUCKSEL ck_wut wakeup clock selection 10x: ck_spre (usually 1Hz) clock is selected 11x: ck_spre (usually 1Hz) clock is selected and 216is added to the WUT counter value 0 3 read-write B_0x0 RTC/16 clock is selected 0x0 B_0x1 RTC/8 clock is selected 0x1 B_0x2 RTC/4 clock is selected 0x2 B_0x3 RTC/2 clock is selected 0x3 TSEDGE Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting. 3 1 read-write B_0x0 RTC_TS input rising edge generates a timestamp event 0x0 B_0x1 RTC_TS input falling edge generates a timestamp event 0x1 REFCKON RTC_REFIN reference clock detection enable (50 or 60Hz) Note: PREDIV_S must be 0x00FF. 4 1 read-write B_0x0 RTC_REFIN detection disabled 0x0 B_0x1 RTC_REFIN detection enabled 0x1 BYPSHAD Bypass the shadow registers Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1. 5 1 read-write B_0x0 Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. 0x0 B_0x1 Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters. 0x1 FMT Hour format 6 1 read-write B_0x0 24 hour/day format 0x0 B_0x1 AM/PM hour format 0x1 ALRAE Alarm A enable 8 1 read-write B_0x0 Alarm A disabled 0x0 B_0x1 Alarm A enabled 0x1 ALRBE Alarm B enable 9 1 read-write B_0x0 Alarm B disabled 0x0 B_0x1 Alarm B enabled 0x1 WUTE Wakeup timer enable Note: When the wakeup timer is disabled, wait for WUTWF=1 before enabling it again. 10 1 read-write B_0x0 Wakeup timer disabled 0x0 B_0x1 Wakeup timer enabled 0x1 TSE timestamp enable 11 1 read-write B_0x0 timestamp disable 0x0 B_0x1 timestamp enable 0x1 ALRAIE Alarm A interrupt enable 12 1 read-write B_0x0 Alarm A interrupt disabled 0x0 B_0x1 Alarm A interrupt enabled 0x1 ALRBIE Alarm B interrupt enable 13 1 read-write B_0x0 Alarm B interrupt disable 0x0 B_0x1 Alarm B interrupt enable 0x1 WUTIE Wakeup timer interrupt enable 14 1 read-write B_0x0 Wakeup timer interrupt disabled 0x0 B_0x1 Wakeup timer interrupt enabled 0x1 TSIE Timestamp interrupt enable 15 1 read-write B_0x0 Timestamp interrupt disable 0x0 B_0x1 Timestamp interrupt enable 0x1 ADD1H Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 16 1 write-only B_0x0 No effect 0x0 B_0x1 Adds 1 hour to the current time. This can be used for summer time change 0x1 SUB1H Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0. 17 1 write-only B_0x0 No effect 0x0 B_0x1 Subtracts 1 hour to the current time. This can be used for winter time change. 0x1 BKP Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. 18 1 read-write COSEL Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to . 19 1 read-write B_0x0 Calibration output is 512Hz 0x0 B_0x1 Calibration output is 1Hz 0x1 POL Output polarity This bit is used to configure the polarity of TAMPALRM output. 20 1 read-write B_0x0 The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1). 0x0 B_0x1 The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1). 0x1 OSEL Output selection These bits are used to select the flag to be routed to TAMPALRM output. 21 2 read-write B_0x0 Output disabled 0x0 B_0x1 Alarm A output enabled 0x1 B_0x2 Alarm B output enabled 0x2 B_0x3 Wakeup output enabled 0x3 COE Calibration output enable This bit enables the CALIB output 23 1 read-write B_0x0 Calibration output disabled 0x0 B_0x1 Calibration output enabled 0x1 ITSE timestamp on internal event enable 24 1 read-write B_0x0 internal event timestamp disabled 0x0 B_0x1 internal event timestamp enabled 0x1 TAMPTS Activate timestamp on tamper detection event TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set after the tamper flags, therefore if TAMPTS and TSIE are set, it is recommended to disable the tamper interrupts in order to avoid servicing 2 interrupts. 25 1 read-write B_0x0 Tamper detection event does not cause a RTC timestamp to be saved 0x0 B_0x1 Save RTC timestamp on tamper detection event 0x1 TAMPOE Tamper detection output enable on TAMPALRM 26 1 read-write B_0x0 The tamper flag is not routed on TAMPALRM 0x0 B_0x1 The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL. 0x1 TAMPALRM_PU TAMPALRM pull-up enable 29 1 read-write B_0x0 No pull-up is applied on TAMPALRM output 0x0 B_0x1 A pull-up is applied on TAMPALRM output 0x1 TAMPALRM_TYPE TAMPALRM output type 30 1 read-write B_0x0 TAMPALRM is push-pull output 0x0 B_0x1 TAMPALRM is open-drain output 0x1 OUT2EN RTC_OUT2 output enable Setting this bit allows to remap the RTC outputs on RTC_OUT2 as follows: OUT2EN = 0: RTC output 2 disable If OSEL ≠ 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL ≠ 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2 If (OSEL≠ 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and TAMPALRM is output on RTC_OUT1. 31 1 read-write RTC_WPR RTC_WPR write protection register 0x24 0x20 0x00000000 0xFFFFFFFF KEY Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to for a description of how to unlock RTC register write protection. 0 8 write-only RTC_CALR RTC_CALR RTC calibration register 0x28 0x20 0x00000000 0xFFFFFFFF CALM Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768Hz). This decreases the frequency of the calendar with a resolution of 0.9537ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See . 0 9 read-write CALW16 Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1. Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to calibration. 13 1 read-write CALW8 Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to digital calibration. 14 1 read-write CALP Increase frequency of RTC by 488.5ppm This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 × CALP) - CALM. Refer to . 15 1 read-write B_0x0 No RTCCLK pulses are added. 0x0 B_0x1 One RTCCLK pulse is effectively inserted every 211 pulses (frequency increased by 488.5ppm). 0x1 RTC_SHIFTR RTC_SHIFTR RTC shift control register 0x2c 0x20 0x00000000 0xFFFFFFFF SUBFS Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time. 0 15 write-only ADD1S Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. 31 1 write-only B_0x0 No effect 0x0 B_0x1 Add one second to the clock/calendar 0x1 RTC_TSTR RTC_TSTR RTC timestamp time register 0x30 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format. 0 4 read-only ST Second tens in BCD format. 4 3 read-only MNU Minute units in BCD format. 8 4 read-only MNT Minute tens in BCD format. 12 3 read-only HU Hour units in BCD format. 16 4 read-only HT Hour tens in BCD format. 20 2 read-only PM AM/PM notation 22 1 read-only B_0x0 AM or 24-hour format 0x0 B_0x1 PM 0x1 RTC_TSDR RTC_TSDR RTC timestamp date register 0x34 0x20 0x00000000 0xFFFFFFFF DU Date units in BCD format 0 4 read-only DT Date tens in BCD format 4 2 read-only MU Month units in BCD format 8 4 read-only MT Month tens in BCD format 12 1 read-only WDU Week day units 13 3 read-only RTC_TSSSR RTC_TSSSR RTC timestamp sub second register 0x38 0x20 0x00000000 0xFFFFFFFF SS Sub second value SS[15:0] is the value of the synchronous prescaler counter when the timestamp event occurred. 0 16 read-only RTC_ALRMAR RTC_ALRMAR RTC alarm A register 0x40 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format. 0 4 read-write ST Second tens in BCD format. 4 3 read-write MSK1 Alarm A seconds mask 7 1 read-write B_0x0 Alarm A set if the seconds match 0x0 B_0x1 Seconds don't care in alarm A comparison 0x1 MNU Minute units in BCD format 8 4 read-write MNT Minute tens in BCD format 12 3 read-write MSK2 Alarm A minutes mask 15 1 read-write B_0x0 Alarm A set if the minutes match 0x0 B_0x1 Minutes don't care in alarm A comparison 0x1 HU Hour units in BCD format 16 4 read-write HT Hour tens in BCD format 20 2 read-write PM AM/PM notation 22 1 read-write B_0x0 AM or 24-hour format 0x0 B_0x1 PM 0x1 MSK3 Alarm A hours mask 23 1 read-write B_0x0 Alarm A set if the hours match 0x0 B_0x1 Hours don't care in alarm A comparison 0x1 DU Date units or day in BCD format 24 4 read-write DT Date tens in BCD format 28 2 read-write WDSEL Week day selection 30 1 read-write B_0x0 DU[3:0] represents the date units 0x0 B_0x1 DU[3:0] represents the week day. DT[1:0] is don't care. 0x1 MSK4 Alarm A date mask 31 1 read-write B_0x0 Alarm A set if the date/day match 0x0 B_0x1 Date/day don't care in alarm A comparison 0x1 RTC_ALRMASSR RTC_ALRMASSR RTC alarm A sub second register 0x44 0x20 0x00000000 0xFFFFFFFF SS Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. 0 15 read-write MASKSS Mask the most-significant bits starting at this bit 2: SS[14:2] are don't care in alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are don't care in alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are don't care in alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are don't care in alarm A comparison. SS[12:0] are compared. 14: SS[14] is don't care in alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. 24 4 read-write B_0x0 No comparison on sub seconds for alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). 0x0 B_0x1 SS[14:1] are don't care in alarm A comparison. Only SS[0] is compared. 0x1 RTC_ALRMBR RTC_ALRMBR RTC alarm B register 0x48 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format 0 4 read-write ST Second tens in BCD format 4 3 read-write MSK1 Alarm B seconds mask 7 1 read-write B_0x0 Alarm B set if the seconds match 0x0 B_0x1 Seconds don't care in alarm B comparison 0x1 MNU Minute units in BCD format 8 4 read-write MNT Minute tens in BCD format 12 3 read-write MSK2 Alarm B minutes mask 15 1 read-write B_0x0 Alarm B set if the minutes match 0x0 B_0x1 Minutes don't care in alarm B comparison 0x1 HU Hour units in BCD format 16 4 read-write HT Hour tens in BCD format 20 2 read-write PM AM/PM notation 22 1 read-write B_0x0 AM or 24-hour format 0x0 B_0x1 PM 0x1 MSK3 Alarm B hours mask 23 1 read-write B_0x0 Alarm B set if the hours match 0x0 B_0x1 Hours don't care in alarm B comparison 0x1 DU Date units or day in BCD format 24 4 read-write DT Date tens in BCD format 28 2 read-write WDSEL Week day selection 30 1 read-write B_0x0 DU[3:0] represents the date units 0x0 B_0x1 DU[3:0] represents the week day. DT[1:0] is don't care. 0x1 MSK4 Alarm B date mask 31 1 read-write B_0x0 Alarm B set if the date and day match 0x0 B_0x1 Date and day don't care in alarm B comparison 0x1 RTC_ALRMBSSR RTC_ALRMBSSR RTC alarm B sub second register 0x4c 0x20 0x00000000 0xFFFFFFFF SS Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared. 0 15 read-write MASKSS Mask the most-significant bits starting at this bit ... The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. 24 4 read-write B_0x0 No comparison on sub seconds for alarm B. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). 0x0 B_0x1 SS[14:1] are don't care in alarm B comparison. Only SS[0] is compared. 0x1 B_0x2 SS[14:2] are don't care in alarm B comparison. Only SS[1:0] are compared. 0x2 B_0x3 SS[14:3] are don't care in alarm B comparison. Only SS[2:0] are compared. 0x3 B_0xC SS[14:12] are don't care in alarm B comparison. SS[11:0] are compared. 0xC B_0xD SS[14:13] are don't care in alarm B comparison. SS[12:0] are compared. 0xD B_0xE SS[14] is don't care in alarm B comparison. SS[13:0] are compared. 0xE B_0xF All 15 SS bits are compared and must match to activate alarm. 0xF RTC_SR RTC_SR RTC status register 0x50 0x20 0x00000000 0xFFFFFFFF ALRAF Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm A register (RTC_ALRMAR). 0 1 read-only ALRBF Alarm B flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm B register (RTC_ALRMBR). 1 1 read-only WUTF Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. 2 1 read-only TSF Timestamp flag This flag is set by hardware when a timestamp event occurs. If ITSF flag is set, TSF must be cleared together with ITSF. 3 1 read-only TSOVF Timestamp overflow flag This flag is set by hardware when a timestamp event occurs while TSF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. 4 1 read-only ITSF Internal timestamp flag This flag is set by hardware when a timestamp on the internal event occurs. 5 1 read-only RTC_MISR RTC_MISR RTC masked interrupt status register 0x54 0x20 0x00000000 0xFFFFFFFF ALRAMF Alarm A masked flag This flag is set by hardware when the alarm A interrupt occurs. 0 1 read-only ALRBMF Alarm B masked flag This flag is set by hardware when the alarm B interrupt occurs. 1 1 read-only WUTMF Wakeup timer masked flag This flag is set by hardware when the wakeup timer interrupt occurs. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. 2 1 read-only TSMF Timestamp masked flag This flag is set by hardware when a timestamp interrupt occurs. If ITSF flag is set, TSF must be cleared together with ITSF. 3 1 read-only TSOVMF Timestamp overflow masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. 4 1 read-only ITSMF Internal timestamp masked flag This flag is set by hardware when a timestamp on the internal event occurs and timestampinterrupt is raised. 5 1 read-only RTC_SCR RTC_SCR RTC status clear register 0x5c 0x20 0x00000000 0xFFFFFFFF CALRAF Clear alarm A flag Writing 1 in this bit clears the ALRAF bit in the RTC_SR register. 0 1 write-only CALRBF Clear alarm B flag Writing 1 in this bit clears the ALRBF bit in the RTC_SR register. 1 1 write-only CWUTF Clear wakeup timer flag Writing 1 in this bit clears the WUTF bit in the RTC_SR register. 2 1 write-only CTSF Clear timestamp flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. If ITSF flag is set, TSF must be cleared together with ITSF by setting CRSF and CITSF. 3 1 write-only CTSOVF Clear timestamp overflow flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. 4 1 write-only CITSF Clear internal timestamp flag Writing 1 in this bit clears the ITSF bit in the RTC_SR register. 5 1 write-only TIM14 General purpose timers TIM 0x40002000 0x0 0x400 registers TIM14 TIM14 global interrupt 19 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 UIFREMAP UIF status bit remapping 11 1 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC1OF Capture/Compare 1 overcapture flag 9 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 CC1S CC1S 0 2 OC1FE OC1FE 2 1 OC1PE OC1PE 3 1 OC1M OC1M 4 3 OC1CE OC1CE 7 1 OC1M_3 Output Compare 1 mode - bit 3 16 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC1F Input capture 1 filter 4 4 ICPCS Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT low counter value 0 16 UIFCPY UIF Copy 31 1 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Low Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Low Capture/Compare 1 value 0 16 TISEL TISEL TIM timer input selection register 0x68 0x20 read-write 0x0000 TISEL TI1[0] to TI1[15] input selection 0 4 TIM6 Basic timers TIM 0x40001000 0x0 0x400 registers TIM6_DAC_LPTIM1 TIM6 + LPTIM1 and DAC global interrupt 17 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 UIFREMAP UIF status bit remapping 11 1 ARPE Auto-reload preload enable 7 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 MMS Master mode selection 4 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 UG Update generation 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT Low counter value 0 16 UIFCPY UIF Copy 31 1 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Low Auto-reload value 0 16 TIM7 0x40001400 TIM7_LPTIM2 TIM7 + LPTIM2 global interrupt 18 TIM2 General-purpose-timers TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global interrupt 15 TIM3 TIM3 global interrupt 16 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 UIFREMAP UIF status bit remapping 11 1 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 TS_4_3 Trigger selection 20 2 SMS_3 Slave mode selection - bit 3 16 1 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 TIF Trigger interrupt flag 6 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 TG Trigger generation 6 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC2CE Output compare 2 clear enable 15 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 OC2FE Output compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC1FE Output compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 OC4M_3 Output Compare 4 mode - bit 3 24 1 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/Compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT_H High counter value (TIM2 only) 16 16 CNT_L Low counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR_H High Auto-reload value (TIM2 only) 16 16 ARR_L Low Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1_H High Capture/Compare 1 value (TIM2 only) 16 16 CCR1_L Low Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2_H High Capture/Compare 2 value (TIM2 only) 16 16 CCR2_L Low Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3_H High Capture/Compare value (TIM2 only) 16 16 CCR3_L Low Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4_H High Capture/Compare value (TIM2 only) 16 16 CCR4_L Low Capture/Compare value 0 16 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 OR1 OR1 TIM option register 0x50 0x20 read-write 0x0000 IOCREF_CLR IOCREF_CLR 0 1 AF1 AF1 TIM alternate function option register 1 0x60 0x20 read-write 0x0000 ETRSEL External trigger source selection 14 4 TISEL TISEL TIM alternate function option register 1 0x68 0x20 read-write 0x0000 TI1SEL TI1SEL 0 4 TI2SEL TI2SEL 8 4 TIM3 0x40000400