<?xml version="1.0" encoding="utf-8" standalone="no"?> <device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> <name>STM32F410</name> <version>1.1</version> <description>STM32F410</description> <!-- details about the cpu embedded in the device --> <cpu> <name>CM4</name> <revision>r1p0</revision> <endian>little</endian> <mpuPresent>false</mpuPresent> <fpuPresent>false</fpuPresent> <nvicPrioBits>3</nvicPrioBits> <vendorSystickConfig>false</vendorSystickConfig> </cpu> <!--Bus Interface Properties--> <!--Cortex-M4 is byte addressable--> <addressUnitBits>8</addressUnitBits> <!--the maximum data bit width accessible within a single transfer--> <width>32</width> <!--Register Default Properties--> <size>0x20</size> <resetValue>0x0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <peripherals> <peripheral> <name>ADC_Common</name> <description>ADC common registers</description> <groupName>ADC</groupName> <baseAddress>0x40012300</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x9</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CSR</name> <displayName>CSR</displayName> <description>ADC Common status register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OVR3</name> <description>Overrun flag of ADC3</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STRT3</name> <description>Regular channel Start flag of ADC 3</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JSTRT3</name> <description>Injected channel Start flag of ADC 3</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JEOC3</name> <description>Injected channel end of conversion of ADC 3</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOC3</name> <description>End of conversion of ADC 3</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWD3</name> <description>Analog watchdog flag of ADC 3</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVR2</name> <description>Overrun flag of ADC 2</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STRT2</name> <description>Regular channel Start flag of ADC 2</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JSTRT2</name> <description>Injected channel Start flag of ADC 2</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JEOC2</name> <description>Injected channel end of conversion of ADC 2</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOC2</name> <description>End of conversion of ADC 2</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWD2</name> <description>Analog watchdog flag of ADC 2</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVR1</name> <description>Overrun flag of ADC 1</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STRT1</name> <description>Regular channel Start flag of ADC 1</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JSTRT1</name> <description>Injected channel Start flag of ADC 1</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JEOC1</name> <description>Injected channel end of conversion of ADC 1</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOC1</name> <description>End of conversion of ADC 1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWD1</name> <description>Analog watchdog flag of ADC 1</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCR</name> <displayName>CCR</displayName> <description>ADC common control register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TSVREFE</name> <description>Temperature sensor and VREFINT enable</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VBATE</name> <description>VBAT enable</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADCPRE</name> <description>ADC prescaler</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DMA</name> <description>Direct memory access mode for multi ADC mode</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DDS</name> <description>DMA disable selection for multi-ADC mode</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DELAY</name> <description>Delay between 2 sampling phases</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>ADC1</name> <description>Analog-to-digital converter</description> <groupName>ADC</groupName> <baseAddress>0x40012000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x51</size> <usage>registers</usage> </addressBlock> <interrupt> <name>ADC</name> <description>ADC1 global interrupt</description> <value>18</value> </interrupt> <registers> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OVR</name> <description>Overrun</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STRT</name> <description>Regular channel start flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JSTRT</name> <description>Injected channel start flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JEOC</name> <description>Injected channel end of conversion</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOC</name> <description>Regular channel end of conversion</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWD</name> <description>Analog watchdog flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OVRIE</name> <description>Overrun interrupt enable</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RES</name> <description>Resolution</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>AWDEN</name> <description>Analog watchdog enable on regular channels</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JAWDEN</name> <description>Analog watchdog enable on injected channels</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DISCNUM</name> <description>Discontinuous mode channel count</description> <bitOffset>13</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>JDISCEN</name> <description>Discontinuous mode on injected channels</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DISCEN</name> <description>Discontinuous mode on regular channels</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JAUTO</name> <description>Automatic injected group conversion</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWDSGL</name> <description>Enable the watchdog on a single channel in scan mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SCAN</name> <description>Scan mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JEOCIE</name> <description>Interrupt enable for injected channels</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWDIE</name> <description>Analog watchdog interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOCIE</name> <description>Interrupt enable for EOC</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWDCH</name> <description>Analog watchdog channel select bits</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>control register 2</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SWSTART</name> <description>Start conversion of regular channels</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTEN</name> <description>External trigger enable for regular channels</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>EXTSEL</name> <description>External event select for regular group</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>JSWSTART</name> <description>Start conversion of injected channels</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JEXTEN</name> <description>External trigger enable for injected channels</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>JEXTSEL</name> <description>External event select for injected group</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ALIGN</name> <description>Data alignment</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOCS</name> <description>End of conversion selection</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DDS</name> <description>DMA disable selection (for single ADC mode)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMA</name> <description>Direct memory access mode (for single ADC mode)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CONT</name> <description>Continuous conversion</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADON</name> <description>A/D Converter ON / OFF</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SMPR1</name> <displayName>SMPR1</displayName> <description>sample time register 1</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SMPx_x</name> <description>Sample time bits</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>SMPR2</name> <displayName>SMPR2</displayName> <description>sample time register 2</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SMPx_x</name> <description>Sample time bits</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>JOFR1</name> <displayName>JOFR1</displayName> <description>injected channel data offset register x</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>JOFFSET1</name> <description>Data offset for injected channel x</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>JOFR2</name> <displayName>JOFR2</displayName> <description>injected channel data offset register x</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>JOFFSET2</name> <description>Data offset for injected channel x</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>JOFR3</name> <displayName>JOFR3</displayName> <description>injected channel data offset register x</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>JOFFSET3</name> <description>Data offset for injected channel x</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>JOFR4</name> <displayName>JOFR4</displayName> <description>injected channel data offset register x</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>JOFFSET4</name> <description>Data offset for injected channel x</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>HTR</name> <displayName>HTR</displayName> <description>watchdog higher threshold register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000FFF</resetValue> <fields> <field> <name>HT</name> <description>Analog watchdog higher threshold</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>LTR</name> <displayName>LTR</displayName> <description>watchdog lower threshold register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LT</name> <description>Analog watchdog lower threshold</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>SQR1</name> <displayName>SQR1</displayName> <description>regular sequence register 1</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>L</name> <description>Regular channel sequence length</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>SQ16</name> <description>16th conversion in regular sequence</description> <bitOffset>15</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ15</name> <description>15th conversion in regular sequence</description> <bitOffset>10</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ14</name> <description>14th conversion in regular sequence</description> <bitOffset>5</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ13</name> <description>13th conversion in regular sequence</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>SQR2</name> <displayName>SQR2</displayName> <description>regular sequence register 2</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SQ12</name> <description>12th conversion in regular sequence</description> <bitOffset>25</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ11</name> <description>11th conversion in regular sequence</description> <bitOffset>20</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ10</name> <description>10th conversion in regular sequence</description> <bitOffset>15</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ9</name> <description>9th conversion in regular sequence</description> <bitOffset>10</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ8</name> <description>8th conversion in regular sequence</description> <bitOffset>5</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ7</name> <description>7th conversion in regular sequence</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>SQR3</name> <displayName>SQR3</displayName> <description>regular sequence register 3</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SQ6</name> <description>6th conversion in regular sequence</description> <bitOffset>25</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ5</name> <description>5th conversion in regular sequence</description> <bitOffset>20</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ4</name> <description>4th conversion in regular sequence</description> <bitOffset>15</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ3</name> <description>3rd conversion in regular sequence</description> <bitOffset>10</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ2</name> <description>2nd conversion in regular sequence</description> <bitOffset>5</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ1</name> <description>1st conversion in regular sequence</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>JSQR</name> <displayName>JSQR</displayName> <description>injected sequence register</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>JL</name> <description>Injected sequence length</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>JSQ4</name> <description>4th conversion in injected sequence</description> <bitOffset>15</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>JSQ3</name> <description>3rd conversion in injected sequence</description> <bitOffset>10</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>JSQ2</name> <description>2nd conversion in injected sequence</description> <bitOffset>5</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>JSQ1</name> <description>1st conversion in injected sequence</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>JDR1</name> <displayName>JDR1</displayName> <description>injected data register x</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>JDATA</name> <description>Injected data</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>JDR2</name> <displayName>JDR2</displayName> <description>injected data register x</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>JDATA</name> <description>Injected data</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>JDR3</name> <displayName>JDR3</displayName> <description>injected data register x</description> <addressOffset>0x44</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>JDATA</name> <description>Injected data</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>JDR4</name> <displayName>JDR4</displayName> <description>injected data register x</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>JDATA</name> <description>Injected data</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>DR</name> <displayName>DR</displayName> <description>regular data register</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATA</name> <description>Regular data</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>CRC</name> <description>Cryptographic processor</description> <groupName>CRC</groupName> <baseAddress>0x40023000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>DR</name> <displayName>DR</displayName> <description>Data register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFFFFFFFF</resetValue> <fields> <field> <name>DR</name> <description>Data Register</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>IDR</name> <displayName>IDR</displayName> <description>Independent Data register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IDR</name> <description>Independent Data register</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>CR</name> <displayName>CR</displayName> <description>Control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CR</name> <description>Control regidter</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>DBG</name> <description>Debug support</description> <groupName>DBG</groupName> <baseAddress>0xE0042000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>DBGMCU_IDCODE</name> <displayName>DBGMCU_IDCODE</displayName> <description>IDCODE</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x10006411</resetValue> <fields> <field> <name>DEV_ID</name> <description>DEV_ID</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>REV_ID</name> <description>REV_ID</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>DBGMCU_CR</name> <displayName>DBGMCU_CR</displayName> <description>Control Register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DBG_SLEEP</name> <description>DBG_SLEEP</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_STOP</name> <description>DBG_STOP</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_STANDBY</name> <description>DBG_STANDBY</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TRACE_IOEN</name> <description>TRACE_IOEN</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TRACE_MODE</name> <description>TRACE_MODE</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>DBGMCU_APB1_FZ</name> <displayName>DBGMCU_APB1_FZ</displayName> <description>Debug MCU APB1 Freeze registe</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DBG_TIM2_STOP</name> <description>DBG_TIM2_STOP</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM3_STOP</name> <description>DBG_TIM3 _STOP</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM4_STOP</name> <description>DBG_TIM4_STOP</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM5_STOP</name> <description>DBG_TIM5_STOP</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_RTC_Stop</name> <description>RTC stopped when Core is halted</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_WWDG_STOP</name> <description>DBG_WWDG_STOP</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_IWDEG_STOP</name> <description>DBG_IWDEG_STOP</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_I2C1_SMBUS_TIMEOUT</name> <description>DBG_J2C1_SMBUS_TIMEOUT</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_I2C2_SMBUS_TIMEOUT</name> <description>DBG_J2C2_SMBUS_TIMEOUT</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_I2C3SMBUS_TIMEOUT</name> <description>DBG_J2C3SMBUS_TIMEOUT</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DBGMCU_APB2_FZ</name> <displayName>DBGMCU_APB2_FZ</displayName> <description>Debug MCU APB2 Freeze registe</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DBG_TIM1_STOP</name> <description>TIM1 counter stopped when core is halted</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM9_STOP</name> <description>TIM9 counter stopped when core is halted</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM10_STOP</name> <description>TIM10 counter stopped when core is halted</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM11_STOP</name> <description>TIM11 counter stopped when core is halted</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>EXTI</name> <description>External interrupt/event controller</description> <groupName>EXTI</groupName> <baseAddress>0x40013C00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>TAMP_STAMP</name> <description>Tamper and TimeStamp interrupts through the EXTI line</description> <value>2</value> </interrupt> <interrupt> <name>EXTI0</name> <description>EXTI Line0 interrupt</description> <value>6</value> </interrupt> <interrupt> <name>EXTI1</name> <description>EXTI Line1 interrupt</description> <value>7</value> </interrupt> <interrupt> <name>EXTI2</name> <description>EXTI Line2 interrupt</description> <value>8</value> </interrupt> <interrupt> <name>EXTI3</name> <description>EXTI Line3 interrupt</description> <value>9</value> </interrupt> <interrupt> <name>EXTI4</name> <description>EXTI Line4 interrupt</description> <value>10</value> </interrupt> <interrupt> <name>EXTI9_5</name> <description>EXTI Line[9:5] interrupts</description> <value>23</value> </interrupt> <interrupt> <name>EXTI15_10</name> <description>EXTI Line[15:10] interrupts</description> <value>40</value> </interrupt> <registers> <register> <name>IMR</name> <displayName>IMR</displayName> <description>Interrupt mask register (EXTI_IMR)</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MR0</name> <description>Interrupt Mask on line 0</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR1</name> <description>Interrupt Mask on line 1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR2</name> <description>Interrupt Mask on line 2</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR3</name> <description>Interrupt Mask on line 3</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR4</name> <description>Interrupt Mask on line 4</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR5</name> <description>Interrupt Mask on line 5</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR6</name> <description>Interrupt Mask on line 6</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR7</name> <description>Interrupt Mask on line 7</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR8</name> <description>Interrupt Mask on line 8</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR9</name> <description>Interrupt Mask on line 9</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR10</name> <description>Interrupt Mask on line 10</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR11</name> <description>Interrupt Mask on line 11</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR12</name> <description>Interrupt Mask on line 12</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR13</name> <description>Interrupt Mask on line 13</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR14</name> <description>Interrupt Mask on line 14</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR15</name> <description>Interrupt Mask on line 15</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR16</name> <description>Interrupt Mask on line 16</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR17</name> <description>Interrupt Mask on line 17</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR18</name> <description>Interrupt Mask on line 18</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR19</name> <description>Interrupt Mask on line 19</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR20</name> <description>Interrupt Mask on line 20</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR21</name> <description>Interrupt Mask on line 21</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR22</name> <description>Interrupt Mask on line 22</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EMR</name> <displayName>EMR</displayName> <description>Event mask register (EXTI_EMR)</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MR0</name> <description>Event Mask on line 0</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR1</name> <description>Event Mask on line 1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR2</name> <description>Event Mask on line 2</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR3</name> <description>Event Mask on line 3</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR4</name> <description>Event Mask on line 4</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR5</name> <description>Event Mask on line 5</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR6</name> <description>Event Mask on line 6</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR7</name> <description>Event Mask on line 7</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR8</name> <description>Event Mask on line 8</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR9</name> <description>Event Mask on line 9</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR10</name> <description>Event Mask on line 10</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR11</name> <description>Event Mask on line 11</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR12</name> <description>Event Mask on line 12</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR13</name> <description>Event Mask on line 13</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR14</name> <description>Event Mask on line 14</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR15</name> <description>Event Mask on line 15</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR16</name> <description>Event Mask on line 16</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR17</name> <description>Event Mask on line 17</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR18</name> <description>Event Mask on line 18</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR19</name> <description>Event Mask on line 19</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR20</name> <description>Event Mask on line 20</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR21</name> <description>Event Mask on line 21</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR22</name> <description>Event Mask on line 22</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>RTSR</name> <displayName>RTSR</displayName> <description>Rising Trigger selection register (EXTI_RTSR)</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TR0</name> <description>Rising trigger event configuration of line 0</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR1</name> <description>Rising trigger event configuration of line 1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR2</name> <description>Rising trigger event configuration of line 2</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR3</name> <description>Rising trigger event configuration of line 3</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR4</name> <description>Rising trigger event configuration of line 4</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR5</name> <description>Rising trigger event configuration of line 5</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR6</name> <description>Rising trigger event configuration of line 6</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR7</name> <description>Rising trigger event configuration of line 7</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR8</name> <description>Rising trigger event configuration of line 8</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR9</name> <description>Rising trigger event configuration of line 9</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR10</name> <description>Rising trigger event configuration of line 10</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR11</name> <description>Rising trigger event configuration of line 11</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR12</name> <description>Rising trigger event configuration of line 12</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR13</name> <description>Rising trigger event configuration of line 13</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR14</name> <description>Rising trigger event configuration of line 14</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR15</name> <description>Rising trigger event configuration of line 15</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR16</name> <description>Rising trigger event configuration of line 16</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR17</name> <description>Rising trigger event configuration of line 17</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR18</name> <description>Rising trigger event configuration of line 18</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR19</name> <description>Rising trigger event configuration of line 19</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR20</name> <description>Rising trigger event configuration of line 20</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR21</name> <description>Rising trigger event configuration of line 21</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR22</name> <description>Rising trigger event configuration of line 22</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FTSR</name> <displayName>FTSR</displayName> <description>Falling Trigger selection register (EXTI_FTSR)</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TR0</name> <description>Falling trigger event configuration of line 0</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR1</name> <description>Falling trigger event configuration of line 1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR2</name> <description>Falling trigger event configuration of line 2</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR3</name> <description>Falling trigger event configuration of line 3</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR4</name> <description>Falling trigger event configuration of line 4</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR5</name> <description>Falling trigger event configuration of line 5</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR6</name> <description>Falling trigger event configuration of line 6</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR7</name> <description>Falling trigger event configuration of line 7</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR8</name> <description>Falling trigger event configuration of line 8</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR9</name> <description>Falling trigger event configuration of line 9</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR10</name> <description>Falling trigger event configuration of line 10</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR11</name> <description>Falling trigger event configuration of line 11</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR12</name> <description>Falling trigger event configuration of line 12</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR13</name> <description>Falling trigger event configuration of line 13</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR14</name> <description>Falling trigger event configuration of line 14</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR15</name> <description>Falling trigger event configuration of line 15</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR16</name> <description>Falling trigger event configuration of line 16</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR17</name> <description>Falling trigger event configuration of line 17</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR18</name> <description>Falling trigger event configuration of line 18</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR19</name> <description>Falling trigger event configuration of line 19</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR20</name> <description>Falling trigger event configuration of line 20</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR21</name> <description>Falling trigger event configuration of line 21</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR22</name> <description>Falling trigger event configuration of line 22</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SWIER</name> <displayName>SWIER</displayName> <description>Software interrupt event register (EXTI_SWIER)</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SWIER0</name> <description>Software Interrupt on line 0</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER1</name> <description>Software Interrupt on line 1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER2</name> <description>Software Interrupt on line 2</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER3</name> <description>Software Interrupt on line 3</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER4</name> <description>Software Interrupt on line 4</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER5</name> <description>Software Interrupt on line 5</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER6</name> <description>Software Interrupt on line 6</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER7</name> <description>Software Interrupt on line 7</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER8</name> <description>Software Interrupt on line 8</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER9</name> <description>Software Interrupt on line 9</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER10</name> <description>Software Interrupt on line 10</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER11</name> <description>Software Interrupt on line 11</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER12</name> <description>Software Interrupt on line 12</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER13</name> <description>Software Interrupt on line 13</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER14</name> <description>Software Interrupt on line 14</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER15</name> <description>Software Interrupt on line 15</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER16</name> <description>Software Interrupt on line 16</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER17</name> <description>Software Interrupt on line 17</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER18</name> <description>Software Interrupt on line 18</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER19</name> <description>Software Interrupt on line 19</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER20</name> <description>Software Interrupt on line 20</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER21</name> <description>Software Interrupt on line 21</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER22</name> <description>Software Interrupt on line 22</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PR</name> <displayName>PR</displayName> <description>Pending register (EXTI_PR)</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PR0</name> <description>Pending bit 0</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR1</name> <description>Pending bit 1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR2</name> <description>Pending bit 2</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR3</name> <description>Pending bit 3</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR4</name> <description>Pending bit 4</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR5</name> <description>Pending bit 5</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR6</name> <description>Pending bit 6</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR7</name> <description>Pending bit 7</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR8</name> <description>Pending bit 8</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR9</name> <description>Pending bit 9</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR10</name> <description>Pending bit 10</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR11</name> <description>Pending bit 11</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR12</name> <description>Pending bit 12</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR13</name> <description>Pending bit 13</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR14</name> <description>Pending bit 14</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR15</name> <description>Pending bit 15</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR16</name> <description>Pending bit 16</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR17</name> <description>Pending bit 17</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR18</name> <description>Pending bit 18</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR19</name> <description>Pending bit 19</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR20</name> <description>Pending bit 20</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR21</name> <description>Pending bit 21</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR22</name> <description>Pending bit 22</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>FLASH</name> <description>FLASH</description> <groupName>FLASH</groupName> <baseAddress>0x40023C00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>FLASH</name> <description>FLASH global interrupt</description> <value>4</value> </interrupt> <registers> <register> <name>ACR</name> <displayName>ACR</displayName> <description>Flash access control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>LATENCY</name> <description>Latency</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> <field> <name>PRFTEN</name> <description>Prefetch enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ICEN</name> <description>Instruction cache enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>DCEN</name> <description>Data cache enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ICRST</name> <description>Instruction cache reset</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>DCRST</name> <description>Data cache reset</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>KEYR</name> <displayName>KEYR</displayName> <description>Flash key register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>KEY</name> <description>FPEC key</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OPTKEYR</name> <displayName>OPTKEYR</displayName> <description>Flash option key register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OPTKEY</name> <description>Option byte key</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>Status register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>EOP</name> <description>End of operation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>OPERR</name> <description>Operation error</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>WRPERR</name> <description>Write protection error</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PGAERR</name> <description>Programming alignment error</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PGPERR</name> <description>Programming parallelism error</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PGSERR</name> <description>Programming sequence error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BSY</name> <description>Busy</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>CR</name> <displayName>CR</displayName> <description>Control register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x80000000</resetValue> <fields> <field> <name>PG</name> <description>Programming</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SER</name> <description>Sector Erase</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MER</name> <description>Mass Erase</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SNB</name> <description>Sector number</description> <bitOffset>3</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>PSIZE</name> <description>Program size</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>STRT</name> <description>Start</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOPIE</name> <description>End of operation interrupt enable</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ERRIE</name> <description>Error interrupt enable</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LOCK</name> <description>Lock</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OPTCR</name> <displayName>OPTCR</displayName> <description>Flash option control register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x7FFFAAED</resetValue> <fields> <field> <name>OPTLOCK</name> <description>Option lock</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPTSTRT</name> <description>Option start</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BOR_LEV</name> <description>BOR reset Level</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>WDG_SW</name> <description>WDG_SW User option bytes</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>nRST_STOP</name> <description>nRST_STOP User option bytes</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>nRST_STDBY</name> <description>nRST_STDBY User option bytes</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RDP</name> <description>Read protect</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>nWRP</name> <description>Not write protect</description> <bitOffset>16</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SPRMOD</name> <description>SPRMOD</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>IWDG</name> <description>Independent watchdog</description> <groupName>IWDG</groupName> <baseAddress>0x40003000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>KR</name> <displayName>KR</displayName> <description>Key register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>KEY</name> <description>Key value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>PR</name> <displayName>PR</displayName> <description>Prescaler register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PR</name> <description>Prescaler divider</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>RLR</name> <displayName>RLR</displayName> <description>Reload register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000FFF</resetValue> <fields> <field> <name>RL</name> <description>Watchdog counter reload value</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>Status register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RVU</name> <description>Watchdog counter reload value update</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PVU</name> <description>Watchdog prescaler value update</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>PWR</name> <description>Power control</description> <groupName>PWR</groupName> <baseAddress>0x40007000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>PVD</name> <description>PVD through EXTI line detection interrupt</description> <value>1</value> </interrupt> <registers> <register> <name>CR</name> <displayName>CR</displayName> <description>power control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>VOS</name> <description>Regulator voltage scaling output selection</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ADCDC1</name> <description>ADCDC1</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPDS</name> <description>Flash power down in Stop mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBP</name> <description>Disable backup domain write protection</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLS</name> <description>PVD level selection</description> <bitOffset>5</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>PVDE</name> <description>Power voltage detector enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CSBF</name> <description>Clear standby flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CWUF</name> <description>Clear wakeup flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PDDS</name> <description>Power down deepsleep</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LPDS</name> <description>Low-power deep sleep</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CSR</name> <displayName>CSR</displayName> <description>power control/status register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>WUF</name> <description>Wakeup flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>SBF</name> <description>Standby flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>PVDO</name> <description>PVD output</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>BRR</name> <description>Backup regulator ready</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EWUP3</name> <description>Enable WKUP3 pin</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EWUP2</name> <description>Enable WKUP2 pin</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EWUP1</name> <description>Enable WKUP1 pin</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BRE</name> <description>Backup regulator enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>VOSRDY</name> <description>Regulator voltage scaling output selection ready bit</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>RCC</name> <description>Reset and clock control</description> <groupName>RCC</groupName> <baseAddress>0x40023800</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>RCC</name> <description>RCC global interrupt</description> <value>5</value> </interrupt> <registers> <register> <name>CR</name> <displayName>CR</displayName> <description>clock control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <resetValue>0x00000083</resetValue> <fields> <field> <name>PLLRDY</name> <description>Main PLL (PLL) clock ready flag</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>PLLON</name> <description>Main PLL (PLL) enable</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>CSSON</name> <description>Clock security system enable</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HSEBYP</name> <description>HSE clock bypass</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HSERDY</name> <description>HSE clock ready flag</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>HSEON</name> <description>HSE clock enable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HSICAL</name> <description>Internal high-speed clock calibration</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-only</access> </field> <field> <name>HSITRIM</name> <description>Internal high-speed clock trimming</description> <bitOffset>3</bitOffset> <bitWidth>5</bitWidth> <access>read-write</access> </field> <field> <name>HSIRDY</name> <description>Internal high-speed clock ready flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>HSION</name> <description>Internal high-speed clock enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>PLLCFGR</name> <displayName>PLLCFGR</displayName> <description>PLL configuration register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x7F003010</resetValue> <fields> <field> <name>PLLM0</name> <description>Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLM1</name> <description>Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLM2</name> <description>Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLM3</name> <description>Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLM4</name> <description>Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLM5</name> <description>Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLN0</name> <description>Main PLL (PLL) multiplication factor for VCO</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLN1</name> <description>Main PLL (PLL) multiplication factor for VCO</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLN2</name> <description>Main PLL (PLL) multiplication factor for VCO</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLN3</name> <description>Main PLL (PLL) multiplication factor for VCO</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLN4</name> <description>Main PLL (PLL) multiplication factor for VCO</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLN5</name> <description>Main PLL (PLL) multiplication factor for VCO</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLN6</name> <description>Main PLL (PLL) multiplication factor for VCO</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLN7</name> <description>Main PLL (PLL) multiplication factor for VCO</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLN8</name> <description>Main PLL (PLL) multiplication factor for VCO</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLP0</name> <description>Main PLL (PLL) division factor for main system clock</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLP1</name> <description>Main PLL (PLL) division factor for main system clock</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLSRC</name> <description>Main PLL(PLL) and audio PLL (PLLI2S) entry clock source</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLQ0</name> <description>Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLQ1</name> <description>Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLQ2</name> <description>Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLQ3</name> <description>Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLR1</name> <description>PLLR1</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLR2</name> <description>PLLR2</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLR3</name> <description>PLLR3</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CFGR</name> <displayName>CFGR</displayName> <description>clock configuration register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>SW0</name> <description>System clock switch</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SW1</name> <description>System clock switch</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SWS0</name> <description>System clock switch status</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>SWS1</name> <description>System clock switch status</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>HPRE</name> <description>AHB prescaler</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>MCO1EN</name> <description>MCO output enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>MCO2EN</name> <description>MCO output enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PPRE1</name> <description>APB Low speed prescaler (APB1)</description> <bitOffset>10</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> <field> <name>PPRE2</name> <description>APB high-speed prescaler (APB2)</description> <bitOffset>13</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> <field> <name>RTCPRE</name> <description>HSE division factor for RTC clock</description> <bitOffset>16</bitOffset> <bitWidth>5</bitWidth> <access>read-write</access> </field> <field> <name>MCO1</name> <description>Microcontroller clock output 1</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>MCO1PRE</name> <description>MCO1 prescaler</description> <bitOffset>24</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> <field> <name>MCO2PRE</name> <description>MCO2 prescaler</description> <bitOffset>27</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> <field> <name>MCO2</name> <description>Microcontroller clock output 2</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>CIR</name> <displayName>CIR</displayName> <description>clock interrupt register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSSC</name> <description>Clock security system interrupt clear</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>PLLI2SRDYC</name> <description>PLLI2S ready interrupt clear</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>PLLRDYC</name> <description>Main PLL(PLL) ready interrupt clear</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>HSERDYC</name> <description>HSE ready interrupt clear</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>HSIRDYC</name> <description>HSI ready interrupt clear</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>LSERDYC</name> <description>LSE ready interrupt clear</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>LSIRDYC</name> <description>LSI ready interrupt clear</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>PLLRDYIE</name> <description>Main PLL (PLL) ready interrupt enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HSERDYIE</name> <description>HSE ready interrupt enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HSIRDYIE</name> <description>HSI ready interrupt enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>LSERDYIE</name> <description>LSE ready interrupt enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>LSIRDYIE</name> <description>LSI ready interrupt enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>CSSF</name> <description>Clock security system interrupt flag</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>PLLRDYF</name> <description>Main PLL (PLL) ready interrupt flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>HSERDYF</name> <description>HSE ready interrupt flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>HSIRDYF</name> <description>HSI ready interrupt flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>LSERDYF</name> <description>LSE ready interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>LSIRDYF</name> <description>LSI ready interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>AHB1RSTR</name> <displayName>AHB1RSTR</displayName> <description>AHB1 peripheral reset register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>GPIOARST</name> <description>IO port A reset</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOBRST</name> <description>IO port B reset</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOCRST</name> <description>IO port C reset</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOHRST</name> <description>IO port H reset</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CRCRST</name> <description>CRC reset</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMA1RST</name> <description>DMA2 reset</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMA2RST</name> <description>DMA2 reset</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RNGRST</name> <description>RNGRST</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APB1RSTR</name> <displayName>APB1RSTR</displayName> <description>APB1 peripheral reset register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIM5RST</name> <description>TIM5 reset</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM6RST</name> <description>TIM6 reset</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LPTIM1RST</name> <description>LPTIM1 reset</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WWDGRST</name> <description>Window watchdog reset</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI2RST</name> <description>SPI 2 reset</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UART2RST</name> <description>USART 2 reset</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C1RST</name> <description>I2C 1 reset</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C2RST</name> <description>I2C 2 reset</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C4RST</name> <description>I2C4 reset</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PWRRST</name> <description>Power interface reset</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DACRST</name> <description>DAC reset</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APB2RSTR</name> <displayName>APB2RSTR</displayName> <description>APB2 peripheral reset register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIM11RST</name> <description>TIM11 reset</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM9RST</name> <description>TIM9 reset</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SYSCFGRST</name> <description>System configuration controller reset</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI1RST</name> <description>SPI 1 reset</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADCRST</name> <description>ADC interface reset (common to all ADCs)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART6RST</name> <description>USART6 reset</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART1RST</name> <description>USART1 reset</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM1RST</name> <description>TIM1 reset</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AHB1ENR</name> <displayName>AHB1ENR</displayName> <description>AHB1 peripheral clock register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00100000</resetValue> <fields> <field> <name>GPIOAEN</name> <description>IO port A clock enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOBEN</name> <description>IO port B clock enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOCEN</name> <description>IO port C clock enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOHEN</name> <description>IO port H clock enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CRCEN</name> <description>CRC clock enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMA1EN</name> <description>DMA1 clock enable</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMA2EN</name> <description>DMA2 clock enable</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RNGEN</name> <description>RNG clock enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APB1ENR</name> <displayName>APB1ENR</displayName> <description>APB1 peripheral clock enable register</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIM5EN</name> <description>TIM5 clock enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM6EN</name> <description>TIM6 clock enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LPTIM1EN</name> <description>LPTIM1 clock enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RTCAPBEN</name> <description>RTC APB clock enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WWDGEN</name> <description>Window watchdog clock enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI2EN</name> <description>SPI2 clock enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART2EN</name> <description>USART 2 clock enable</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C1EN</name> <description>I2C1 clock enable</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C2EN</name> <description>I2C2 clock enable</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C4EN</name> <description>I2C4 clock enable</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PWREN</name> <description>Power interface clock enable</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DACEN</name> <description>DAC interface clock enable</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APB2ENR</name> <displayName>APB2ENR</displayName> <description>APB2 peripheral clock enable register</description> <addressOffset>0x44</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIM1EN</name> <description>TIM1 clock enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART1EN</name> <description>USART1 clock enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART6EN</name> <description>USART6 clock enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADC1EN</name> <description>ADC1 clock enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI1EN</name> <description>SPI1 clock enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SYSCFGEN</name> <description>System configuration controller clock enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTITEN</name> <description>EXTI ans external IT clock enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM9EN</name> <description>TIM9 clock enable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM11EN</name> <description>TIM11 clock enable</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI5EN</name> <description>SPI5 clock enable</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AHB1LPENR</name> <displayName>AHB1LPENR</displayName> <description>AHB1 peripheral clock enable in low power mode register</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x7E6791FF</resetValue> <fields> <field> <name>GPIOALPEN</name> <description>IO port A clock enable during sleep mode</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOBLPEN</name> <description>IO port B clock enable during Sleep mode</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOCLPEN</name> <description>IO port C clock enable during Sleep mode</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOHLPEN</name> <description>IO port H clock enable during Sleep mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CRCLPEN</name> <description>CRC clock enable during Sleep mode</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FLITFLPEN</name> <description>Flash interface clock enable during Sleep mode</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SRAM1LPEN</name> <description>SRAM 1interface clock enable during Sleep mode</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMA1LPEN</name> <description>DMA1 clock enable during Sleep mode</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMA2LPEN</name> <description>DMA2 clock enable during Sleep mode</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RNGLPEN</name> <description>RNG clock enable during sleep mode</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APB1LPENR</name> <displayName>APB1LPENR</displayName> <description>APB1 peripheral clock enable in low power mode register</description> <addressOffset>0x60</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x36FEC9FF</resetValue> <fields> <field> <name>TIM5LPEN</name> <description>TIM5 clock enable during Sleep mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM6LPEN</name> <description>TIM6 clock enable during Sleep mode</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LPTIM1LPEN</name> <description>LPTIM1 clock enable during sleep mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RTCAPBLPEN</name> <description>RTC APB clock enable during sleep mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WWDGLPEN</name> <description>Window watchdog clock enable during Sleep mode</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI2LPEN</name> <description>SPI2 clock enable during Sleep mode</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART2LPEN</name> <description>USART2 clock enable during Sleep mode</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C1LPEN</name> <description>I2C1 clock enable during Sleep mode</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C2LPEN</name> <description>I2C2 clock enable during Sleep mode</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C4LPEN</name> <description>I2C4 clock enable during Sleep mode</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PWRLPEN</name> <description>Power interface clock enable during Sleep mode</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DACLPEN</name> <description>DAC interface clock enable during sleep mode</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APB2LPENR</name> <displayName>APB2LPENR</displayName> <description>APB2 peripheral clock enabled in low power mode register</description> <addressOffset>0x64</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00075F33</resetValue> <fields> <field> <name>TIM1LPEN</name> <description>TIM1 clock enable during Sleep mode</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART1LPEN</name> <description>USART1 clock enable during Sleep mode</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART6LPEN</name> <description>USART6 clock enable during Sleep mode</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADC1LPEN</name> <description>ADC1 clock enable during Sleep mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SDIOLPEN</name> <description>SDIO clock enable during Sleep mode</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI1LPEN</name> <description>SPI 1 clock enable during Sleep mode</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SYSCFGLPEN</name> <description>System configuration controller clock enable during Sleep mode</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTITLPEN</name> <description>EXTI and External IT clock enable during sleep mode</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM9LPEN</name> <description>TIM9 clock enable during sleep mode</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM11LPEN</name> <description>TIM11 clock enable during Sleep mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BDCR</name> <displayName>BDCR</displayName> <description>Backup domain control register</description> <addressOffset>0x70</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>BDRST</name> <description>Backup domain software reset</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RTCEN</name> <description>RTC clock enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RTCSEL1</name> <description>RTC clock source selection</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RTCSEL0</name> <description>RTC clock source selection</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>LSEBYP</name> <description>External low-speed oscillator bypass</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>LSERDY</name> <description>External low-speed oscillator ready</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>LSEON</name> <description>External low-speed oscillator enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>CSR</name> <displayName>CSR</displayName> <description>clock control & status register</description> <addressOffset>0x74</addressOffset> <size>0x20</size> <resetValue>0x0E000000</resetValue> <fields> <field> <name>LPWRRSTF</name> <description>Low-power reset flag</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>WWDGRSTF</name> <description>Window watchdog reset flag</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>WDGRSTF</name> <description>Independent watchdog reset flag</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SFTRSTF</name> <description>Software reset flag</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PORRSTF</name> <description>POR/PDR reset flag</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PADRSTF</name> <description>PIN reset flag</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BORRSTF</name> <description>BOR reset flag</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RMVF</name> <description>Remove reset flag</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>LSIRDY</name> <description>Internal low-speed oscillator ready</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>LSION</name> <description>Internal low-speed oscillator enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>SSCGR</name> <displayName>SSCGR</displayName> <description>spread spectrum clock generation register</description> <addressOffset>0x80</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SSCGEN</name> <description>Spread spectrum modulation enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPREADSEL</name> <description>Spread Select</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>INCSTEP</name> <description>Incrementation step</description> <bitOffset>13</bitOffset> <bitWidth>15</bitWidth> </field> <field> <name>MODPER</name> <description>Modulation period</description> <bitOffset>0</bitOffset> <bitWidth>13</bitWidth> </field> </fields> </register> <register> <name>DCKCFGR</name> <displayName>DCKCFGR</displayName> <description>DCKCFGR register</description> <addressOffset>0x8C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIMPRE</name> <description>TIMPRE</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2SSRC</name> <description>I2SSRC</description> <bitOffset>25</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>DCKCFGR2</name> <displayName>DCKCFGR2</displayName> <description>DCKCFGR2 register</description> <addressOffset>0x94</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>I2C4SEL</name> <description>I2C4SEL</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>LPTIM1SEL</name> <description>LPTIM1SEL</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>RTC</name> <description>Real-time clock</description> <groupName>RTC</groupName> <baseAddress>0x40002800</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>RTC_WKUP</name> <description>RTC Wakeup interrupt through the EXTI line</description> <value>3</value> </interrupt> <registers> <register> <name>TR</name> <displayName>TR</displayName> <description>time register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PM</name> <description>AM/PM notation</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HT</name> <description>Hour tens in BCD format</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>HU</name> <description>Hour units in BCD format</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MNT</name> <description>Minute tens in BCD format</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MNU</name> <description>Minute units in BCD format</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ST</name> <description>Second tens in BCD format</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SU</name> <description>Second units in BCD format</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>DR</name> <displayName>DR</displayName> <description>date register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00002101</resetValue> <fields> <field> <name>YT</name> <description>Year tens in BCD format</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>YU</name> <description>Year units in BCD format</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>WDU</name> <description>Week day units</description> <bitOffset>13</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MT</name> <description>Month tens in BCD format</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MU</name> <description>Month units in BCD format</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>DT</name> <description>Date tens in BCD format</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DU</name> <description>Date units in BCD format</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>CR</name> <displayName>CR</displayName> <description>control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>COE</name> <description>Calibration output enable</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OSEL</name> <description>Output selection</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>POL</name> <description>Output polarity</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COSEL</name> <description>Calibration Output selection</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKP</name> <description>Backup</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SUB1H</name> <description>Subtract 1 hour (winter time change)</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADD1H</name> <description>Add 1 hour (summer time change)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSIE</name> <description>Time-stamp interrupt enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WUTIE</name> <description>Wakeup timer interrupt enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALRBIE</name> <description>Alarm B interrupt enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALRAIE</name> <description>Alarm A interrupt enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSE</name> <description>Time stamp enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WUTE</name> <description>Wakeup timer enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALRBE</name> <description>Alarm B enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALRAE</name> <description>Alarm A enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DCE</name> <description>Coarse digital calibration enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FMT</name> <description>Hour format</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BYPSHAD</name> <description>Bypass the shadow registers</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>REFCKON</name> <description>Reference clock detection enable (50 or 60 Hz)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSEDGE</name> <description>Time-stamp event active edge</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WCKSEL</name> <description>Wakeup clock selection</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>ISR</name> <displayName>ISR</displayName> <description>initialization and status register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <resetValue>0x00000007</resetValue> <fields> <field> <name>ALRAWF</name> <description>Alarm A write flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ALRBWF</name> <description>Alarm B write flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>WUTWF</name> <description>Wakeup timer write flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>SHPF</name> <description>Shift operation pending</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>INITS</name> <description>Initialization status flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>RSF</name> <description>Registers synchronization flag</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>INITF</name> <description>Initialization flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>INIT</name> <description>Initialization mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ALRAF</name> <description>Alarm A flag</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ALRBF</name> <description>Alarm B flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>WUTF</name> <description>Wakeup timer flag</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TSF</name> <description>Time-stamp flag</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TSOVF</name> <description>Time-stamp overflow flag</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TAMP1F</name> <description>Tamper detection flag</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TAMP2F</name> <description>TAMPER2 detection flag</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RECALPF</name> <description>Recalibration pending Flag</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>PRER</name> <displayName>PRER</displayName> <description>prescaler register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x007F00FF</resetValue> <fields> <field> <name>PREDIV_A</name> <description>Asynchronous prescaler factor</description> <bitOffset>16</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>PREDIV_S</name> <description>Synchronous prescaler factor</description> <bitOffset>0</bitOffset> <bitWidth>15</bitWidth> </field> </fields> </register> <register> <name>WUTR</name> <displayName>WUTR</displayName> <description>wakeup timer register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000FFFF</resetValue> <fields> <field> <name>WUT</name> <description>Wakeup auto-reload value bits</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CALIBR</name> <displayName>CALIBR</displayName> <description>calibration register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DCS</name> <description>Digital calibration sign</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DC</name> <description>Digital calibration</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>ALRMAR</name> <displayName>ALRMAR</displayName> <description>alarm A register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MSK4</name> <description>Alarm A date mask</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WDSEL</name> <description>Week day selection</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DT</name> <description>Date tens in BCD format</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DU</name> <description>Date units or day in BCD format</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSK3</name> <description>Alarm A hours mask</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PM</name> <description>AM/PM notation</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HT</name> <description>Hour tens in BCD format</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>HU</name> <description>Hour units in BCD format</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSK2</name> <description>Alarm A minutes mask</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MNT</name> <description>Minute tens in BCD format</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MNU</name> <description>Minute units in BCD format</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSK1</name> <description>Alarm A seconds mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ST</name> <description>Second tens in BCD format</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SU</name> <description>Second units in BCD format</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>ALRMBR</name> <displayName>ALRMBR</displayName> <description>alarm B register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MSK4</name> <description>Alarm B date mask</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WDSEL</name> <description>Week day selection</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DT</name> <description>Date tens in BCD format</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DU</name> <description>Date units or day in BCD format</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSK3</name> <description>Alarm B hours mask</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PM</name> <description>AM/PM notation</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HT</name> <description>Hour tens in BCD format</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>HU</name> <description>Hour units in BCD format</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSK2</name> <description>Alarm B minutes mask</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MNT</name> <description>Minute tens in BCD format</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MNU</name> <description>Minute units in BCD format</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSK1</name> <description>Alarm B seconds mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ST</name> <description>Second tens in BCD format</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SU</name> <description>Second units in BCD format</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>WPR</name> <displayName>WPR</displayName> <description>write protection register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>KEY</name> <description>Write protection key</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>SSR</name> <displayName>SSR</displayName> <description>sub second register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SS</name> <description>Sub second value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>SHIFTR</name> <displayName>SHIFTR</displayName> <description>shift control register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ADD1S</name> <description>Add one second</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SUBFS</name> <description>Subtract a fraction of a second</description> <bitOffset>0</bitOffset> <bitWidth>15</bitWidth> </field> </fields> </register> <register> <name>TSTR</name> <displayName>TSTR</displayName> <description>time stamp time register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PM</name> <description>AM/PM notation</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HT</name> <description>Hour tens in BCD format</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>HU</name> <description>Hour units in BCD format</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MNT</name> <description>Minute tens in BCD format</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MNU</name> <description>Minute units in BCD format</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ST</name> <description>Second tens in BCD format</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SU</name> <description>Second units in BCD format</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>TSDR</name> <displayName>TSDR</displayName> <description>time stamp date register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>WDU</name> <description>Week day units</description> <bitOffset>13</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MT</name> <description>Month tens in BCD format</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MU</name> <description>Month units in BCD format</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>DT</name> <description>Date tens in BCD format</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DU</name> <description>Date units in BCD format</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>TSSSR</name> <displayName>TSSSR</displayName> <description>timestamp sub second register</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SS</name> <description>Sub second value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CALR</name> <displayName>CALR</displayName> <description>calibration register</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CALP</name> <description>Increase frequency of RTC by 488.5 ppm</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CALW8</name> <description>Use an 8-second calibration cycle period</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CALW16</name> <description>Use a 16-second calibration cycle period</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CALM</name> <description>Calibration minus</description> <bitOffset>0</bitOffset> <bitWidth>9</bitWidth> </field> </fields> </register> <register> <name>TAFCR</name> <displayName>TAFCR</displayName> <description>tamper and alternate function configuration register</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ALARMOUTTYPE</name> <description>AFO_ALARM output type</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSINSEL</name> <description>TIMESTAMP mapping</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP1INSEL</name> <description>TAMPER1 mapping</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMPPUDIS</name> <description>TAMPER pull-up disable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMPPRCH</name> <description>Tamper precharge duration</description> <bitOffset>13</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>TAMPFLT</name> <description>Tamper filter count</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>TAMPFREQ</name> <description>Tamper sampling frequency</description> <bitOffset>8</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>TAMPTS</name> <description>Activate timestamp on tamper detection event</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP2TRG</name> <description>Active level for tamper 2</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP2E</name> <description>Tamper 2 detection enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMPIE</name> <description>Tamper interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP1TRG</name> <description>Active level for tamper 1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP1E</name> <description>Tamper 1 detection enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ALRMASSR</name> <displayName>ALRMASSR</displayName> <description>alarm A sub second register</description> <addressOffset>0x44</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MASKSS</name> <description>Mask the most-significant bits starting at this bit</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>SS</name> <description>Sub seconds value</description> <bitOffset>0</bitOffset> <bitWidth>15</bitWidth> </field> </fields> </register> <register> <name>ALRMBSSR</name> <displayName>ALRMBSSR</displayName> <description>alarm B sub second register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MASKSS</name> <description>Mask the most-significant bits starting at this bit</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>SS</name> <description>Sub seconds value</description> <bitOffset>0</bitOffset> <bitWidth>15</bitWidth> </field> </fields> </register> <register> <name>BKP0R</name> <displayName>BKP0R</displayName> <description>backup register</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP1R</name> <displayName>BKP1R</displayName> <description>backup register</description> <addressOffset>0x54</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP2R</name> <displayName>BKP2R</displayName> <description>backup register</description> <addressOffset>0x58</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP3R</name> <displayName>BKP3R</displayName> <description>backup register</description> <addressOffset>0x5C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP4R</name> <displayName>BKP4R</displayName> <description>backup register</description> <addressOffset>0x60</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP5R</name> <displayName>BKP5R</displayName> <description>backup register</description> <addressOffset>0x64</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP6R</name> <displayName>BKP6R</displayName> <description>backup register</description> <addressOffset>0x68</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP7R</name> <displayName>BKP7R</displayName> <description>backup register</description> <addressOffset>0x6C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP8R</name> <displayName>BKP8R</displayName> <description>backup register</description> <addressOffset>0x70</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP9R</name> <displayName>BKP9R</displayName> <description>backup register</description> <addressOffset>0x74</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP10R</name> <displayName>BKP10R</displayName> <description>backup register</description> <addressOffset>0x78</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP11R</name> <displayName>BKP11R</displayName> <description>backup register</description> <addressOffset>0x7C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP12R</name> <displayName>BKP12R</displayName> <description>backup register</description> <addressOffset>0x80</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP13R</name> <displayName>BKP13R</displayName> <description>backup register</description> <addressOffset>0x84</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP14R</name> <displayName>BKP14R</displayName> <description>backup register</description> <addressOffset>0x88</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP15R</name> <displayName>BKP15R</displayName> <description>backup register</description> <addressOffset>0x8C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP16R</name> <displayName>BKP16R</displayName> <description>backup register</description> <addressOffset>0x90</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP17R</name> <displayName>BKP17R</displayName> <description>backup register</description> <addressOffset>0x94</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP18R</name> <displayName>BKP18R</displayName> <description>backup register</description> <addressOffset>0x98</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP19R</name> <displayName>BKP19R</displayName> <description>backup register</description> <addressOffset>0x9C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>SYSCFG</name> <description>System configuration controller</description> <groupName>SYSCFG</groupName> <baseAddress>0x40013800</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>MEMRM</name> <displayName>MEMRM</displayName> <description>memory remap register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MEM_MODE</name> <description>MEM_MODE</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>PMC</name> <displayName>PMC</displayName> <description>peripheral mode configuration register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ADC1DC2</name> <description>ADC1DC2</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EXTICR1</name> <displayName>EXTICR1</displayName> <description>external interrupt configuration register 1</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>EXTI3</name> <description>EXTI x configuration (x = 0 to 3)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI2</name> <description>EXTI x configuration (x = 0 to 3)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI1</name> <description>EXTI x configuration (x = 0 to 3)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI0</name> <description>EXTI x configuration (x = 0 to 3)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>EXTICR2</name> <displayName>EXTICR2</displayName> <description>external interrupt configuration register 2</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>EXTI7</name> <description>EXTI x configuration (x = 4 to 7)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI6</name> <description>EXTI x configuration (x = 4 to 7)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI5</name> <description>EXTI x configuration (x = 4 to 7)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI4</name> <description>EXTI x configuration (x = 4 to 7)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>EXTICR3</name> <displayName>EXTICR3</displayName> <description>external interrupt configuration register 3</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>EXTI11</name> <description>EXTI x configuration (x = 8 to 11)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI10</name> <description>EXTI10</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI9</name> <description>EXTI x configuration (x = 8 to 11)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI8</name> <description>EXTI x configuration (x = 8 to 11)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>EXTICR4</name> <displayName>EXTICR4</displayName> <description>external interrupt configuration register 4</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>EXTI15</name> <description>EXTI x configuration (x = 12 to 15)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI14</name> <description>EXTI x configuration (x = 12 to 15)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI13</name> <description>EXTI x configuration (x = 12 to 15)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI12</name> <description>EXTI x configuration (x = 12 to 15)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>CMPCR</name> <displayName>CMPCR</displayName> <description>Compensation cell control register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>READY</name> <description>READY</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMP_PD</name> <description>Compensation cell power-down</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CFGR</name> <displayName>CFGR</displayName> <description>Configuration register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FMPI2C1_SCL</name> <description>FMPI2C1_SCL</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FMPI2C1_SDA</name> <description>FMPI2C1_SDA</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>TIM1</name> <description>Advanced-timers</description> <groupName>TIM</groupName> <baseAddress>0x40010000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>TIM1_BRK_TIM9</name> <description>TIM1 Break interrupt and TIM9 global interrupt</description> <value>24</value> </interrupt> <interrupt> <name>PWM1_UP</name> <description>Timer1 Update interrupt</description> <value>25</value> </interrupt> <interrupt> <name>TIM1_TRG_COM_TIM11</name> <description>TIM1 Trigger and Commutation interrupts and TIM11 global interrupt</description> <value>26</value> </interrupt> <interrupt> <name>TIM1_CC</name> <description>TIM1 Capture Compare interrupt</description> <value>27</value> </interrupt> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CKD</name> <description>Clock division</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ARPE</name> <description>Auto-reload preload enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMS</name> <description>Center-aligned mode selection</description> <bitOffset>5</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DIR</name> <description>Direction</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPM</name> <description>One-pulse mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>URS</name> <description>Update request source</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDIS</name> <description>Update disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CEN</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>OIS4</name> <description>Output Idle state 4</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS3N</name> <description>Output Idle state 3</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS3</name> <description>Output Idle state 3</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS2N</name> <description>Output Idle state 2</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS2</name> <description>Output Idle state 2</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS1N</name> <description>Output Idle state 1</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS1</name> <description>Output Idle state 1</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TI1S</name> <description>TI1 selection</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MMS</name> <description>Master mode selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>CCDS</name> <description>Capture/compare DMA selection</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CCUS</name> <description>Capture/compare control update selection</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CCPC</name> <description>Capture/compare preloaded control</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SMCR</name> <displayName>SMCR</displayName> <description>slave mode control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>ETP</name> <description>External trigger polarity</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ECE</name> <description>External clock enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETPS</name> <description>External trigger prescaler</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ETF</name> <description>External trigger filter</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSM</name> <description>Master/Slave mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TS</name> <description>Trigger selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SMS</name> <description>Slave mode selection</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>DIER</name> <displayName>DIER</displayName> <description>DMA/Interrupt enable register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TDE</name> <description>Trigger DMA request enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COMDE</name> <description>COM DMA request enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4DE</name> <description>Capture/Compare 4 DMA request enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3DE</name> <description>Capture/Compare 3 DMA request enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2DE</name> <description>Capture/Compare 2 DMA request enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1DE</name> <description>Capture/Compare 1 DMA request enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDE</name> <description>Update DMA request enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BIE</name> <description>Break interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIE</name> <description>Trigger interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COMIE</name> <description>COM interrupt enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4IE</name> <description>Capture/Compare 4 interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3IE</name> <description>Capture/Compare 3 interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IE</name> <description>Capture/Compare 2 interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IE</name> <description>Capture/Compare 1 interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIE</name> <description>Update interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC4OF</name> <description>Capture/Compare 4 overcapture flag</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3OF</name> <description>Capture/Compare 3 overcapture flag</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2OF</name> <description>Capture/compare 2 overcapture flag</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1OF</name> <description>Capture/Compare 1 overcapture flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BIF</name> <description>Break interrupt flag</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIF</name> <description>Trigger interrupt flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COMIF</name> <description>COM interrupt flag</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4IF</name> <description>Capture/Compare 4 interrupt flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3IF</name> <description>Capture/Compare 3 interrupt flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IF</name> <description>Capture/Compare 2 interrupt flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IF</name> <description>Capture/compare 1 interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIF</name> <description>Update interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EGR</name> <displayName>EGR</displayName> <description>event generation register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>BG</name> <description>Break generation</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TG</name> <description>Trigger generation</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COMG</name> <description>Capture/Compare control update generation</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4G</name> <description>Capture/compare 4 generation</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3G</name> <description>Capture/compare 3 generation</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2G</name> <description>Capture/compare 2 generation</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1G</name> <description>Capture/compare 1 generation</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UG</name> <description>Update generation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Output</name> <displayName>CCMR1_Output</displayName> <description>capture/compare mode register 1 (output mode)</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OC2CE</name> <description>Output Compare 2 clear enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2M</name> <description>Output Compare 2 mode</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC2PE</name> <description>Output Compare 2 preload enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2FE</name> <description>Output Compare 2 fast enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2S</name> <description>Capture/Compare 2 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC1CE</name> <description>Output Compare 1 clear enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1M</name> <description>Output Compare 1 mode</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC1PE</name> <description>Output Compare 1 preload enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1FE</name> <description>Output Compare 1 fast enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Input</name> <displayName>CCMR1_Input</displayName> <description>capture/compare mode register 1 (input mode)</description> <alternateRegister>CCMR1_Output</alternateRegister> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC2F</name> <description>Input capture 2 filter</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC2PCS</name> <description>Input capture 2 prescaler</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC2S</name> <description>Capture/Compare 2 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>IC1F</name> <description>Input capture 1 filter</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ICPCS</name> <description>Input capture 1 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR2_Output</name> <displayName>CCMR2_Output</displayName> <description>capture/compare mode register 2 (output mode)</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OC4CE</name> <description>Output compare 4 clear enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4M</name> <description>Output compare 4 mode</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC4PE</name> <description>Output compare 4 preload enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4FE</name> <description>Output compare 4 fast enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4S</name> <description>Capture/Compare 4 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC3CE</name> <description>Output compare 3 clear enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3M</name> <description>Output compare 3 mode</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC3PE</name> <description>Output compare 3 preload enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3FE</name> <description>Output compare 3 fast enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3S</name> <description>Capture/Compare 3 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR2_Input</name> <displayName>CCMR2_Input</displayName> <description>capture/compare mode register 2 (input mode)</description> <alternateRegister>CCMR2_Output</alternateRegister> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC4F</name> <description>Input capture 4 filter</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC4PSC</name> <description>Input capture 4 prescaler</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC4S</name> <description>Capture/Compare 4 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>IC3F</name> <description>Input capture 3 filter</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC3PSC</name> <description>Input capture 3 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC3S</name> <description>Capture/compare 3 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCER</name> <displayName>CCER</displayName> <description>capture/compare enable register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC4P</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4E</name> <description>Capture/Compare 4 output enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3NP</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3NE</name> <description>Capture/Compare 3 complementary output enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3P</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3E</name> <description>Capture/Compare 3 output enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2NP</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2NE</name> <description>Capture/Compare 2 complementary output enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2P</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2E</name> <description>Capture/Compare 2 output enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1NP</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1NE</name> <description>Capture/Compare 1 complementary output enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1P</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1E</name> <description>Capture/Compare 1 output enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CNT</name> <displayName>CNT</displayName> <description>counter</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CNT</name> <description>counter value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>PSC</name> <displayName>PSC</displayName> <description>prescaler</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ARR</name> <displayName>ARR</displayName> <description>auto-reload register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ARR</name> <description>Auto-reload value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR1</name> <displayName>CCR1</displayName> <description>capture/compare register 1</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR1</name> <description>Capture/Compare 1 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR2</name> <displayName>CCR2</displayName> <description>capture/compare register 2</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR2</name> <description>Capture/Compare 2 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR3</name> <displayName>CCR3</displayName> <description>capture/compare register 3</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR3</name> <description>Capture/Compare value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR4</name> <displayName>CCR4</displayName> <description>capture/compare register 4</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR4</name> <description>Capture/Compare value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>DCR</name> <displayName>DCR</displayName> <description>DMA control register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DBL</name> <description>DMA burst length</description> <bitOffset>8</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>DBA</name> <description>DMA base address</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>DMAR</name> <displayName>DMAR</displayName> <description>DMA address for full transfer</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DMAB</name> <description>DMA register for burst accesses</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>RCR</name> <displayName>RCR</displayName> <description>repetition counter register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>REP</name> <description>Repetition counter value</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>BDTR</name> <displayName>BDTR</displayName> <description>break and dead-time register</description> <addressOffset>0x44</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>MOE</name> <description>Main output enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AOE</name> <description>Automatic output enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKP</name> <description>Break polarity</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKE</name> <description>Break enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OSSR</name> <description>Off-state selection for Run mode</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OSSI</name> <description>Off-state selection for Idle mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LOCK</name> <description>Lock configuration</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DTG</name> <description>Dead-time generator setup</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="TIM1"> <name>TIM8</name> <baseAddress>0x40010400</baseAddress> </peripheral> <peripheral> <name>TIM11</name> <description>General-purpose-timers</description> <groupName>TIM</groupName> <baseAddress>0x40014800</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CKD</name> <description>Clock division</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ARPE</name> <description>Auto-reload preload enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>URS</name> <description>Update request source</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDIS</name> <description>Update disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CEN</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DIER</name> <displayName>DIER</displayName> <description>DMA/Interrupt enable register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC1IE</name> <description>Capture/Compare 1 interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIE</name> <description>Update interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC1OF</name> <description>Capture/Compare 1 overcapture flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IF</name> <description>Capture/compare 1 interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIF</name> <description>Update interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EGR</name> <displayName>EGR</displayName> <description>event generation register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC1G</name> <description>Capture/compare 1 generation</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UG</name> <description>Update generation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Output</name> <displayName>CCMR1_Output</displayName> <description>capture/compare mode register 1 (output mode)</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OC1M</name> <description>Output Compare 1 mode</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC1PE</name> <description>Output Compare 1 preload enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1FE</name> <description>Output Compare 1 fast enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Input</name> <displayName>CCMR1_Input</displayName> <description>capture/compare mode register 1 (input mode)</description> <alternateRegister>CCMR1_Output</alternateRegister> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC1F</name> <description>Input capture 1 filter</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ICPCS</name> <description>Input capture 1 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCER</name> <displayName>CCER</displayName> <description>capture/compare enable register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC1NP</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1P</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1E</name> <description>Capture/Compare 1 output enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CNT</name> <displayName>CNT</displayName> <description>counter</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CNT</name> <description>counter value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>PSC</name> <displayName>PSC</displayName> <description>prescaler</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ARR</name> <displayName>ARR</displayName> <description>auto-reload register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ARR</name> <description>Auto-reload value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR1</name> <displayName>CCR1</displayName> <description>capture/compare register 1</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR1</name> <description>Capture/Compare 1 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OR</name> <displayName>OR</displayName> <description>option register</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RMP</name> <description>Input 1 remapping capability</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>TIM5</name> <description>General-purpose-timers</description> <groupName>TIM</groupName> <baseAddress>0x40000C00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CKD</name> <description>Clock division</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ARPE</name> <description>Auto-reload preload enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMS</name> <description>Center-aligned mode selection</description> <bitOffset>5</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DIR</name> <description>Direction</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPM</name> <description>One-pulse mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>URS</name> <description>Update request source</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDIS</name> <description>Update disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CEN</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TI1S</name> <description>TI1 selection</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MMS</name> <description>Master mode selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>CCDS</name> <description>Capture/compare DMA selection</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SMCR</name> <displayName>SMCR</displayName> <description>slave mode control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>ETP</name> <description>External trigger polarity</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ECE</name> <description>External clock enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETPS</name> <description>External trigger prescaler</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ETF</name> <description>External trigger filter</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSM</name> <description>Master/Slave mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TS</name> <description>Trigger selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SMS</name> <description>Slave mode selection</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>DIER</name> <displayName>DIER</displayName> <description>DMA/Interrupt enable register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TDE</name> <description>Trigger DMA request enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4DE</name> <description>Capture/Compare 4 DMA request enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3DE</name> <description>Capture/Compare 3 DMA request enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2DE</name> <description>Capture/Compare 2 DMA request enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1DE</name> <description>Capture/Compare 1 DMA request enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDE</name> <description>Update DMA request enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIE</name> <description>Trigger interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4IE</name> <description>Capture/Compare 4 interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3IE</name> <description>Capture/Compare 3 interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IE</name> <description>Capture/Compare 2 interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IE</name> <description>Capture/Compare 1 interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIE</name> <description>Update interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC4OF</name> <description>Capture/Compare 4 overcapture flag</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3OF</name> <description>Capture/Compare 3 overcapture flag</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2OF</name> <description>Capture/compare 2 overcapture flag</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1OF</name> <description>Capture/Compare 1 overcapture flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIF</name> <description>Trigger interrupt flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4IF</name> <description>Capture/Compare 4 interrupt flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3IF</name> <description>Capture/Compare 3 interrupt flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IF</name> <description>Capture/Compare 2 interrupt flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IF</name> <description>Capture/compare 1 interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIF</name> <description>Update interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EGR</name> <displayName>EGR</displayName> <description>event generation register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TG</name> <description>Trigger generation</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4G</name> <description>Capture/compare 4 generation</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3G</name> <description>Capture/compare 3 generation</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2G</name> <description>Capture/compare 2 generation</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1G</name> <description>Capture/compare 1 generation</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UG</name> <description>Update generation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Output</name> <displayName>CCMR1_Output</displayName> <description>capture/compare mode register 1 (output mode)</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OC2CE</name> <description>OC2CE</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2M</name> <description>OC2M</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC2PE</name> <description>OC2PE</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2FE</name> <description>OC2FE</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2S</name> <description>CC2S</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC1CE</name> <description>OC1CE</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1M</name> <description>OC1M</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC1PE</name> <description>OC1PE</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1FE</name> <description>OC1FE</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1S</name> <description>CC1S</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Input</name> <displayName>CCMR1_Input</displayName> <description>capture/compare mode register 1 (input mode)</description> <alternateRegister>CCMR1_Output</alternateRegister> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC2F</name> <description>Input capture 2 filter</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC2PCS</name> <description>Input capture 2 prescaler</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC2S</name> <description>Capture/Compare 2 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>IC1F</name> <description>Input capture 1 filter</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ICPCS</name> <description>Input capture 1 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR2_Output</name> <displayName>CCMR2_Output</displayName> <description>capture/compare mode register 2 (output mode)</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>O24CE</name> <description>O24CE</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4M</name> <description>OC4M</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC4PE</name> <description>OC4PE</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4FE</name> <description>OC4FE</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4S</name> <description>CC4S</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC3CE</name> <description>OC3CE</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3M</name> <description>OC3M</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC3PE</name> <description>OC3PE</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3FE</name> <description>OC3FE</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3S</name> <description>CC3S</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR2_Input</name> <displayName>CCMR2_Input</displayName> <description>capture/compare mode register 2 (input mode)</description> <alternateRegister>CCMR2_Output</alternateRegister> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC4F</name> <description>Input capture 4 filter</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC4PSC</name> <description>Input capture 4 prescaler</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC4S</name> <description>Capture/Compare 4 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>IC3F</name> <description>Input capture 3 filter</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC3PSC</name> <description>Input capture 3 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC3S</name> <description>Capture/compare 3 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCER</name> <displayName>CCER</displayName> <description>capture/compare enable register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC4NP</name> <description>Capture/Compare 4 output Polarity</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4P</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4E</name> <description>Capture/Compare 4 output enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3NP</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3P</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3E</name> <description>Capture/Compare 3 output enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2NP</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2P</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2E</name> <description>Capture/Compare 2 output enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1NP</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1P</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1E</name> <description>Capture/Compare 1 output enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CNT</name> <displayName>CNT</displayName> <description>counter</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CNT_H</name> <description>High counter value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CNT_L</name> <description>Low counter value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>PSC</name> <displayName>PSC</displayName> <description>prescaler</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ARR</name> <displayName>ARR</displayName> <description>auto-reload register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ARR_H</name> <description>High Auto-reload value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>ARR_L</name> <description>Low Auto-reload value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR1</name> <displayName>CCR1</displayName> <description>capture/compare register 1</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR1_H</name> <description>High Capture/Compare 1 value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR1_L</name> <description>Low Capture/Compare 1 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR2</name> <displayName>CCR2</displayName> <description>capture/compare register 2</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR2_H</name> <description>High Capture/Compare 2 value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR2_L</name> <description>Low Capture/Compare 2 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR3</name> <displayName>CCR3</displayName> <description>capture/compare register 3</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR3_H</name> <description>High Capture/Compare value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR3_L</name> <description>Low Capture/Compare value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR4</name> <displayName>CCR4</displayName> <description>capture/compare register 4</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR4_H</name> <description>High Capture/Compare value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR4_L</name> <description>Low Capture/Compare value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>DCR</name> <displayName>DCR</displayName> <description>DMA control register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DBL</name> <description>DMA burst length</description> <bitOffset>8</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>DBA</name> <description>DMA base address</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>DMAR</name> <displayName>DMAR</displayName> <description>DMA address for full transfer</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DMAB</name> <description>DMA register for burst accesses</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OR</name> <displayName>OR</displayName> <description>TIM5 option register</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>IT4_RMP</name> <description>Timer Input 4 remap</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>TIM9</name> <description>General purpose timers</description> <groupName>TIM</groupName> <baseAddress>0x40014000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CKD</name> <description>Clock division</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ARPE</name> <description>Auto-reload preload enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPM</name> <description>One-pulse mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>URS</name> <description>Update request source</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDIS</name> <description>Update disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CEN</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>MMS</name> <description>Master mode selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>SMCR</name> <displayName>SMCR</displayName> <description>slave mode control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>MSM</name> <description>Master/Slave mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TS</name> <description>Trigger selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SMS</name> <description>Slave mode selection</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>DIER</name> <displayName>DIER</displayName> <description>DMA/Interrupt enable register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TIE</name> <description>Trigger interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IE</name> <description>Capture/Compare 2 interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IE</name> <description>Capture/Compare 1 interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIE</name> <description>Update interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC2OF</name> <description>Capture/compare 2 overcapture flag</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1OF</name> <description>Capture/Compare 1 overcapture flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIF</name> <description>Trigger interrupt flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IF</name> <description>Capture/Compare 2 interrupt flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IF</name> <description>Capture/compare 1 interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIF</name> <description>Update interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EGR</name> <displayName>EGR</displayName> <description>event generation register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TG</name> <description>Trigger generation</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2G</name> <description>Capture/compare 2 generation</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1G</name> <description>Capture/compare 1 generation</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UG</name> <description>Update generation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Output</name> <displayName>CCMR1_Output</displayName> <description>capture/compare mode register 1 (output mode)</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OC2M</name> <description>Output Compare 2 mode</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC2PE</name> <description>Output Compare 2 preload enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2FE</name> <description>Output Compare 2 fast enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2S</name> <description>Capture/Compare 2 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC1M</name> <description>Output Compare 1 mode</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC1PE</name> <description>Output Compare 1 preload enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1FE</name> <description>Output Compare 1 fast enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Input</name> <displayName>CCMR1_Input</displayName> <description>capture/compare mode register 1 (input mode)</description> <alternateRegister>CCMR1_Output</alternateRegister> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC2F</name> <description>Input capture 2 filter</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>IC2PCS</name> <description>Input capture 2 prescaler</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC2S</name> <description>Capture/Compare 2 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>IC1F</name> <description>Input capture 1 filter</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>ICPCS</name> <description>Input capture 1 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCER</name> <displayName>CCER</displayName> <description>capture/compare enable register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC2NP</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2P</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2E</name> <description>Capture/Compare 2 output enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1NP</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1P</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1E</name> <description>Capture/Compare 1 output enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CNT</name> <displayName>CNT</displayName> <description>counter</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CNT</name> <description>counter value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>PSC</name> <displayName>PSC</displayName> <description>prescaler</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ARR</name> <displayName>ARR</displayName> <description>auto-reload register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ARR</name> <description>Auto-reload value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR1</name> <displayName>CCR1</displayName> <description>capture/compare register 1</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR1</name> <description>Capture/Compare 1 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR2</name> <displayName>CCR2</displayName> <description>capture/compare register 2</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR2</name> <description>Capture/Compare 2 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>USART1</name> <description>Universal synchronous asynchronous receiver transmitter</description> <groupName>USART</groupName> <baseAddress>0x40011000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>SR</name> <displayName>SR</displayName> <description>Status register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <resetValue>0x00C00000</resetValue> <fields> <field> <name>CTS</name> <description>CTS flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>LBD</name> <description>LIN break detection flag</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXE</name> <description>Transmit data register empty</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TC</name> <description>Transmission complete</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RXNE</name> <description>Read data register not empty</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IDLE</name> <description>IDLE line detected</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ORE</name> <description>Overrun error</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NF</name> <description>Noise detected flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>FE</name> <description>Framing error</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>PE</name> <description>Parity error</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>DR</name> <displayName>DR</displayName> <description>Data register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DR</name> <description>Data value</description> <bitOffset>0</bitOffset> <bitWidth>9</bitWidth> </field> </fields> </register> <register> <name>BRR</name> <displayName>BRR</displayName> <description>Baud rate register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DIV_Mantissa</name> <description>mantissa of USARTDIV</description> <bitOffset>4</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>DIV_Fraction</name> <description>fraction of USARTDIV</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>CR1</name> <displayName>CR1</displayName> <description>Control register 1</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>OVER8</name> <description>Oversampling mode</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UE</name> <description>USART enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>M</name> <description>Word length</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAKE</name> <description>Wakeup method</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PCE</name> <description>Parity control enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PS</name> <description>Parity selection</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PEIE</name> <description>PE interrupt enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXEIE</name> <description>TXE interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transmission complete interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXNEIE</name> <description>RXNE interrupt enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDLEIE</name> <description>IDLE interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TE</name> <description>Transmitter enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RE</name> <description>Receiver enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RWU</name> <description>Receiver wakeup</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SBK</name> <description>Send break</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>Control register 2</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>LINEN</name> <description>LIN mode enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STOP</name> <description>STOP bits</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CLKEN</name> <description>Clock enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CPOL</name> <description>Clock polarity</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CPHA</name> <description>Clock phase</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LBCL</name> <description>Last bit clock pulse</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LBDIE</name> <description>LIN break detection interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LBDL</name> <description>lin break detection length</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADD</name> <description>Address of the USART node</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>CR3</name> <displayName>CR3</displayName> <description>Control register 3</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>ONEBIT</name> <description>One sample bit method enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTSIE</name> <description>CTS interrupt enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTSE</name> <description>CTS enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RTSE</name> <description>RTS enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAT</name> <description>DMA enable transmitter</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAR</name> <description>DMA enable receiver</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SCEN</name> <description>Smartcard mode enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NACK</name> <description>Smartcard NACK enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HDSEL</name> <description>Half-duplex selection</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IRLP</name> <description>IrDA low-power</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IREN</name> <description>IrDA mode enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EIE</name> <description>Error interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>GTPR</name> <displayName>GTPR</displayName> <description>Guard time and prescaler register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>GT</name> <description>Guard time value</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="USART1"> <name>USART2</name> <baseAddress>0x40004400</baseAddress> </peripheral> <peripheral derivedFrom="USART1"> <name>USART6</name> <baseAddress>0x40011400</baseAddress> </peripheral> <peripheral> <name>WWDG</name> <description>Window watchdog</description> <groupName>WWDG</groupName> <baseAddress>0x40002C00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CR</name> <displayName>CR</displayName> <description>Control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x7F</resetValue> <fields> <field> <name>WDGA</name> <description>Activation bit</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>T</name> <description>7-bit counter (MSB to LSB)</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> </fields> </register> <register> <name>CFR</name> <displayName>CFR</displayName> <description>Configuration register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x7F</resetValue> <fields> <field> <name>EWI</name> <description>Early wakeup interrupt</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WDGTB1</name> <description>Timer base</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WDGTB0</name> <description>Timer base</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>W</name> <description>7-bit window value</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>Status register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00</resetValue> <fields> <field> <name>EWIF</name> <description>Early wakeup interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>DMA2</name> <description>DMA controller</description> <groupName>DMA</groupName> <baseAddress>0x40026400</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>LISR</name> <displayName>LISR</displayName> <description>low interrupt status register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TCIF3</name> <description>Stream x transfer complete interrupt flag (x = 3..0)</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF3</name> <description>Stream x half transfer interrupt flag (x=3..0)</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF3</name> <description>Stream x transfer error interrupt flag (x=3..0)</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIF3</name> <description>Stream x direct mode error interrupt flag (x=3..0)</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FEIF3</name> <description>Stream x FIFO error interrupt flag (x=3..0)</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF2</name> <description>Stream x transfer complete interrupt flag (x = 3..0)</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF2</name> <description>Stream x half transfer interrupt flag (x=3..0)</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF2</name> <description>Stream x transfer error interrupt flag (x=3..0)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIF2</name> <description>Stream x direct mode error interrupt flag (x=3..0)</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FEIF2</name> <description>Stream x FIFO error interrupt flag (x=3..0)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF1</name> <description>Stream x transfer complete interrupt flag (x = 3..0)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF1</name> <description>Stream x half transfer interrupt flag (x=3..0)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF1</name> <description>Stream x transfer error interrupt flag (x=3..0)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIF1</name> <description>Stream x direct mode error interrupt flag (x=3..0)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FEIF1</name> <description>Stream x FIFO error interrupt flag (x=3..0)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF0</name> <description>Stream x transfer complete interrupt flag (x = 3..0)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF0</name> <description>Stream x half transfer interrupt flag (x=3..0)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF0</name> <description>Stream x transfer error interrupt flag (x=3..0)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIF0</name> <description>Stream x direct mode error interrupt flag (x=3..0)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FEIF0</name> <description>Stream x FIFO error interrupt flag (x=3..0)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>HISR</name> <displayName>HISR</displayName> <description>high interrupt status register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TCIF7</name> <description>Stream x transfer complete interrupt flag (x=7..4)</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF7</name> <description>Stream x half transfer interrupt flag (x=7..4)</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF7</name> <description>Stream x transfer error interrupt flag (x=7..4)</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIF7</name> <description>Stream x direct mode error interrupt flag (x=7..4)</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FEIF7</name> <description>Stream x FIFO error interrupt flag (x=7..4)</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF6</name> <description>Stream x transfer complete interrupt flag (x=7..4)</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF6</name> <description>Stream x half transfer interrupt flag (x=7..4)</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF6</name> <description>Stream x transfer error interrupt flag (x=7..4)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIF6</name> <description>Stream x direct mode error interrupt flag (x=7..4)</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FEIF6</name> <description>Stream x FIFO error interrupt flag (x=7..4)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF5</name> <description>Stream x transfer complete interrupt flag (x=7..4)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF5</name> <description>Stream x half transfer interrupt flag (x=7..4)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF5</name> <description>Stream x transfer error interrupt flag (x=7..4)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIF5</name> <description>Stream x direct mode error interrupt flag (x=7..4)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FEIF5</name> <description>Stream x FIFO error interrupt flag (x=7..4)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF4</name> <description>Stream x transfer complete interrupt flag (x=7..4)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF4</name> <description>Stream x half transfer interrupt flag (x=7..4)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF4</name> <description>Stream x transfer error interrupt flag (x=7..4)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIF4</name> <description>Stream x direct mode error interrupt flag (x=7..4)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FEIF4</name> <description>Stream x FIFO error interrupt flag (x=7..4)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>LIFCR</name> <displayName>LIFCR</displayName> <description>low interrupt flag clear register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CTCIF3</name> <description>Stream x clear transfer complete interrupt flag (x = 3..0)</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF3</name> <description>Stream x clear half transfer interrupt flag (x = 3..0)</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF3</name> <description>Stream x clear transfer error interrupt flag (x = 3..0)</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CDMEIF3</name> <description>Stream x clear direct mode error interrupt flag (x = 3..0)</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CFEIF3</name> <description>Stream x clear FIFO error interrupt flag (x = 3..0)</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF2</name> <description>Stream x clear transfer complete interrupt flag (x = 3..0)</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF2</name> <description>Stream x clear half transfer interrupt flag (x = 3..0)</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF2</name> <description>Stream x clear transfer error interrupt flag (x = 3..0)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CDMEIF2</name> <description>Stream x clear direct mode error interrupt flag (x = 3..0)</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CFEIF2</name> <description>Stream x clear FIFO error interrupt flag (x = 3..0)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF1</name> <description>Stream x clear transfer complete interrupt flag (x = 3..0)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF1</name> <description>Stream x clear half transfer interrupt flag (x = 3..0)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF1</name> <description>Stream x clear transfer error interrupt flag (x = 3..0)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CDMEIF1</name> <description>Stream x clear direct mode error interrupt flag (x = 3..0)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CFEIF1</name> <description>Stream x clear FIFO error interrupt flag (x = 3..0)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF0</name> <description>Stream x clear transfer complete interrupt flag (x = 3..0)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF0</name> <description>Stream x clear half transfer interrupt flag (x = 3..0)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF0</name> <description>Stream x clear transfer error interrupt flag (x = 3..0)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CDMEIF0</name> <description>Stream x clear direct mode error interrupt flag (x = 3..0)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CFEIF0</name> <description>Stream x clear FIFO error interrupt flag (x = 3..0)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>HIFCR</name> <displayName>HIFCR</displayName> <description>high interrupt flag clear register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CTCIF7</name> <description>Stream x clear transfer complete interrupt flag (x = 7..4)</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF7</name> <description>Stream x clear half transfer interrupt flag (x = 7..4)</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF7</name> <description>Stream x clear transfer error interrupt flag (x = 7..4)</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CDMEIF7</name> <description>Stream x clear direct mode error interrupt flag (x = 7..4)</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CFEIF7</name> <description>Stream x clear FIFO error interrupt flag (x = 7..4)</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF6</name> <description>Stream x clear transfer complete interrupt flag (x = 7..4)</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF6</name> <description>Stream x clear half transfer interrupt flag (x = 7..4)</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF6</name> <description>Stream x clear transfer error interrupt flag (x = 7..4)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CDMEIF6</name> <description>Stream x clear direct mode error interrupt flag (x = 7..4)</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CFEIF6</name> <description>Stream x clear FIFO error interrupt flag (x = 7..4)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF5</name> <description>Stream x clear transfer complete interrupt flag (x = 7..4)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF5</name> <description>Stream x clear half transfer interrupt flag (x = 7..4)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF5</name> <description>Stream x clear transfer error interrupt flag (x = 7..4)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CDMEIF5</name> <description>Stream x clear direct mode error interrupt flag (x = 7..4)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CFEIF5</name> <description>Stream x clear FIFO error interrupt flag (x = 7..4)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF4</name> <description>Stream x clear transfer complete interrupt flag (x = 7..4)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF4</name> <description>Stream x clear half transfer interrupt flag (x = 7..4)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF4</name> <description>Stream x clear transfer error interrupt flag (x = 7..4)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CDMEIF4</name> <description>Stream x clear direct mode error interrupt flag (x = 7..4)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CFEIF4</name> <description>Stream x clear FIFO error interrupt flag (x = 7..4)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>S0CR</name> <displayName>S0CR</displayName> <description>stream x configuration register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CHSEL</name> <description>Channel selection</description> <bitOffset>25</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MBURST</name> <description>Memory burst transfer configuration</description> <bitOffset>23</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PBURST</name> <description>Peripheral burst transfer configuration</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CT</name> <description>Current target (only in double buffer mode)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBM</name> <description>Double buffer mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PL</name> <description>Priority level</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PINCOS</name> <description>Peripheral increment offset size</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory data size</description> <bitOffset>13</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral data size</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PFCTRL</name> <description>Peripheral flow controller</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIE</name> <description>Direct mode error interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN</name> <description>Stream enable / flag stream ready when read low</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>S0NDTR</name> <displayName>S0NDTR</displayName> <description>stream x number of data register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data items to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>S0PAR</name> <displayName>S0PAR</displayName> <description>stream x peripheral address register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S0M0AR</name> <displayName>S0M0AR</displayName> <description>stream x memory 0 address register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M0A</name> <description>Memory 0 address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S0M1AR</name> <displayName>S0M1AR</displayName> <description>stream x memory 1 address register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M1A</name> <description>Memory 1 address (used in case of Double buffer mode)</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S0FCR</name> <displayName>S0FCR</displayName> <description>stream x FIFO control register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <resetValue>0x00000021</resetValue> <fields> <field> <name>FEIE</name> <description>FIFO error interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FS</name> <description>FIFO status</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>DMDIS</name> <description>Direct mode disable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FTH</name> <description>FIFO threshold selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>S1CR</name> <displayName>S1CR</displayName> <description>stream x configuration register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CHSEL</name> <description>Channel selection</description> <bitOffset>25</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MBURST</name> <description>Memory burst transfer configuration</description> <bitOffset>23</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PBURST</name> <description>Peripheral burst transfer configuration</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ACK</name> <description>ACK</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CT</name> <description>Current target (only in double buffer mode)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBM</name> <description>Double buffer mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PL</name> <description>Priority level</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PINCOS</name> <description>Peripheral increment offset size</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory data size</description> <bitOffset>13</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral data size</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PFCTRL</name> <description>Peripheral flow controller</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIE</name> <description>Direct mode error interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN</name> <description>Stream enable / flag stream ready when read low</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>S1NDTR</name> <displayName>S1NDTR</displayName> <description>stream x number of data register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data items to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>S1PAR</name> <displayName>S1PAR</displayName> <description>stream x peripheral address register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S1M0AR</name> <displayName>S1M0AR</displayName> <description>stream x memory 0 address register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M0A</name> <description>Memory 0 address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S1M1AR</name> <displayName>S1M1AR</displayName> <description>stream x memory 1 address register</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M1A</name> <description>Memory 1 address (used in case of Double buffer mode)</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S1FCR</name> <displayName>S1FCR</displayName> <description>stream x FIFO control register</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <resetValue>0x00000021</resetValue> <fields> <field> <name>FEIE</name> <description>FIFO error interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FS</name> <description>FIFO status</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>DMDIS</name> <description>Direct mode disable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FTH</name> <description>FIFO threshold selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>S2CR</name> <displayName>S2CR</displayName> <description>stream x configuration register</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CHSEL</name> <description>Channel selection</description> <bitOffset>25</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MBURST</name> <description>Memory burst transfer configuration</description> <bitOffset>23</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PBURST</name> <description>Peripheral burst transfer configuration</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ACK</name> <description>ACK</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CT</name> <description>Current target (only in double buffer mode)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBM</name> <description>Double buffer mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PL</name> <description>Priority level</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PINCOS</name> <description>Peripheral increment offset size</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory data size</description> <bitOffset>13</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral data size</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PFCTRL</name> <description>Peripheral flow controller</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIE</name> <description>Direct mode error interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN</name> <description>Stream enable / flag stream ready when read low</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>S2NDTR</name> <displayName>S2NDTR</displayName> <description>stream x number of data register</description> <addressOffset>0x44</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data items to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>S2PAR</name> <displayName>S2PAR</displayName> <description>stream x peripheral address register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S2M0AR</name> <displayName>S2M0AR</displayName> <description>stream x memory 0 address register</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M0A</name> <description>Memory 0 address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S2M1AR</name> <displayName>S2M1AR</displayName> <description>stream x memory 1 address register</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M1A</name> <description>Memory 1 address (used in case of Double buffer mode)</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S2FCR</name> <displayName>S2FCR</displayName> <description>stream x FIFO control register</description> <addressOffset>0x54</addressOffset> <size>0x20</size> <resetValue>0x00000021</resetValue> <fields> <field> <name>FEIE</name> <description>FIFO error interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FS</name> <description>FIFO status</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>DMDIS</name> <description>Direct mode disable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FTH</name> <description>FIFO threshold selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>S3CR</name> <displayName>S3CR</displayName> <description>stream x configuration register</description> <addressOffset>0x58</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CHSEL</name> <description>Channel selection</description> <bitOffset>25</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MBURST</name> <description>Memory burst transfer configuration</description> <bitOffset>23</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PBURST</name> <description>Peripheral burst transfer configuration</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ACK</name> <description>ACK</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CT</name> <description>Current target (only in double buffer mode)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBM</name> <description>Double buffer mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PL</name> <description>Priority level</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PINCOS</name> <description>Peripheral increment offset size</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory data size</description> <bitOffset>13</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral data size</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PFCTRL</name> <description>Peripheral flow controller</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIE</name> <description>Direct mode error interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN</name> <description>Stream enable / flag stream ready when read low</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>S3NDTR</name> <displayName>S3NDTR</displayName> <description>stream x number of data register</description> <addressOffset>0x5C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data items to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>S3PAR</name> <displayName>S3PAR</displayName> <description>stream x peripheral address register</description> <addressOffset>0x60</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S3M0AR</name> <displayName>S3M0AR</displayName> <description>stream x memory 0 address register</description> <addressOffset>0x64</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M0A</name> <description>Memory 0 address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S3M1AR</name> <displayName>S3M1AR</displayName> <description>stream x memory 1 address register</description> <addressOffset>0x68</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M1A</name> <description>Memory 1 address (used in case of Double buffer mode)</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S3FCR</name> <displayName>S3FCR</displayName> <description>stream x FIFO control register</description> <addressOffset>0x6C</addressOffset> <size>0x20</size> <resetValue>0x00000021</resetValue> <fields> <field> <name>FEIE</name> <description>FIFO error interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FS</name> <description>FIFO status</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>DMDIS</name> <description>Direct mode disable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FTH</name> <description>FIFO threshold selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>S4CR</name> <displayName>S4CR</displayName> <description>stream x configuration register</description> <addressOffset>0x70</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CHSEL</name> <description>Channel selection</description> <bitOffset>25</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MBURST</name> <description>Memory burst transfer configuration</description> <bitOffset>23</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PBURST</name> <description>Peripheral burst transfer configuration</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ACK</name> <description>ACK</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CT</name> <description>Current target (only in double buffer mode)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBM</name> <description>Double buffer mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PL</name> <description>Priority level</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PINCOS</name> <description>Peripheral increment offset size</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory data size</description> <bitOffset>13</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral data size</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PFCTRL</name> <description>Peripheral flow controller</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIE</name> <description>Direct mode error interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN</name> <description>Stream enable / flag stream ready when read low</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>S4NDTR</name> <displayName>S4NDTR</displayName> <description>stream x number of data register</description> <addressOffset>0x74</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data items to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>S4PAR</name> <displayName>S4PAR</displayName> <description>stream x peripheral address register</description> <addressOffset>0x78</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S4M0AR</name> <displayName>S4M0AR</displayName> <description>stream x memory 0 address register</description> <addressOffset>0x7C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M0A</name> <description>Memory 0 address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S4M1AR</name> <displayName>S4M1AR</displayName> <description>stream x memory 1 address register</description> <addressOffset>0x80</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M1A</name> <description>Memory 1 address (used in case of Double buffer mode)</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S4FCR</name> <displayName>S4FCR</displayName> <description>stream x FIFO control register</description> <addressOffset>0x84</addressOffset> <size>0x20</size> <resetValue>0x00000021</resetValue> <fields> <field> <name>FEIE</name> <description>FIFO error interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FS</name> <description>FIFO status</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>DMDIS</name> <description>Direct mode disable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FTH</name> <description>FIFO threshold selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>S5CR</name> <displayName>S5CR</displayName> <description>stream x configuration register</description> <addressOffset>0x88</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CHSEL</name> <description>Channel selection</description> <bitOffset>25</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MBURST</name> <description>Memory burst transfer configuration</description> <bitOffset>23</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PBURST</name> <description>Peripheral burst transfer configuration</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ACK</name> <description>ACK</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CT</name> <description>Current target (only in double buffer mode)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBM</name> <description>Double buffer mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PL</name> <description>Priority level</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PINCOS</name> <description>Peripheral increment offset size</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory data size</description> <bitOffset>13</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral data size</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PFCTRL</name> <description>Peripheral flow controller</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIE</name> <description>Direct mode error interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN</name> <description>Stream enable / flag stream ready when read low</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>S5NDTR</name> <displayName>S5NDTR</displayName> <description>stream x number of data register</description> <addressOffset>0x8C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data items to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>S5PAR</name> <displayName>S5PAR</displayName> <description>stream x peripheral address register</description> <addressOffset>0x90</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S5M0AR</name> <displayName>S5M0AR</displayName> <description>stream x memory 0 address register</description> <addressOffset>0x94</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M0A</name> <description>Memory 0 address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S5M1AR</name> <displayName>S5M1AR</displayName> <description>stream x memory 1 address register</description> <addressOffset>0x98</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M1A</name> <description>Memory 1 address (used in case of Double buffer mode)</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S5FCR</name> <displayName>S5FCR</displayName> <description>stream x FIFO control register</description> <addressOffset>0x9C</addressOffset> <size>0x20</size> <resetValue>0x00000021</resetValue> <fields> <field> <name>FEIE</name> <description>FIFO error interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FS</name> <description>FIFO status</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>DMDIS</name> <description>Direct mode disable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FTH</name> <description>FIFO threshold selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>S6CR</name> <displayName>S6CR</displayName> <description>stream x configuration register</description> <addressOffset>0xA0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CHSEL</name> <description>Channel selection</description> <bitOffset>25</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MBURST</name> <description>Memory burst transfer configuration</description> <bitOffset>23</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PBURST</name> <description>Peripheral burst transfer configuration</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ACK</name> <description>ACK</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CT</name> <description>Current target (only in double buffer mode)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBM</name> <description>Double buffer mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PL</name> <description>Priority level</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PINCOS</name> <description>Peripheral increment offset size</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory data size</description> <bitOffset>13</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral data size</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PFCTRL</name> <description>Peripheral flow controller</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIE</name> <description>Direct mode error interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN</name> <description>Stream enable / flag stream ready when read low</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>S6NDTR</name> <displayName>S6NDTR</displayName> <description>stream x number of data register</description> <addressOffset>0xA4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data items to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>S6PAR</name> <displayName>S6PAR</displayName> <description>stream x peripheral address register</description> <addressOffset>0xA8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S6M0AR</name> <displayName>S6M0AR</displayName> <description>stream x memory 0 address register</description> <addressOffset>0xAC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M0A</name> <description>Memory 0 address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S6M1AR</name> <displayName>S6M1AR</displayName> <description>stream x memory 1 address register</description> <addressOffset>0xB0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M1A</name> <description>Memory 1 address (used in case of Double buffer mode)</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S6FCR</name> <displayName>S6FCR</displayName> <description>stream x FIFO control register</description> <addressOffset>0xB4</addressOffset> <size>0x20</size> <resetValue>0x00000021</resetValue> <fields> <field> <name>FEIE</name> <description>FIFO error interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FS</name> <description>FIFO status</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>DMDIS</name> <description>Direct mode disable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FTH</name> <description>FIFO threshold selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>S7CR</name> <displayName>S7CR</displayName> <description>stream x configuration register</description> <addressOffset>0xB8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CHSEL</name> <description>Channel selection</description> <bitOffset>25</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MBURST</name> <description>Memory burst transfer configuration</description> <bitOffset>23</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PBURST</name> <description>Peripheral burst transfer configuration</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ACK</name> <description>ACK</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CT</name> <description>Current target (only in double buffer mode)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBM</name> <description>Double buffer mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PL</name> <description>Priority level</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PINCOS</name> <description>Peripheral increment offset size</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory data size</description> <bitOffset>13</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral data size</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PFCTRL</name> <description>Peripheral flow controller</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIE</name> <description>Direct mode error interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN</name> <description>Stream enable / flag stream ready when read low</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>S7NDTR</name> <displayName>S7NDTR</displayName> <description>stream x number of data register</description> <addressOffset>0xBC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data items to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>S7PAR</name> <displayName>S7PAR</displayName> <description>stream x peripheral address register</description> <addressOffset>0xC0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S7M0AR</name> <displayName>S7M0AR</displayName> <description>stream x memory 0 address register</description> <addressOffset>0xC4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M0A</name> <description>Memory 0 address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S7M1AR</name> <displayName>S7M1AR</displayName> <description>stream x memory 1 address register</description> <addressOffset>0xC8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M1A</name> <description>Memory 1 address (used in case of Double buffer mode)</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S7FCR</name> <displayName>S7FCR</displayName> <description>stream x FIFO control register</description> <addressOffset>0xCC</addressOffset> <size>0x20</size> <resetValue>0x00000021</resetValue> <fields> <field> <name>FEIE</name> <description>FIFO error interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FS</name> <description>FIFO status</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>DMDIS</name> <description>Direct mode disable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FTH</name> <description>FIFO threshold selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="DMA2"> <name>DMA1</name> <baseAddress>0x40026000</baseAddress> <interrupt> <name>RTC_Alarm</name> <description>RTC Alarms (A and B) through EXTI line interrupt</description> <value>41</value> </interrupt> </peripheral> <peripheral> <name>GPIOH</name> <description>General-purpose I/Os</description> <groupName>GPIO</groupName> <baseAddress>0x40021C00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>MODER</name> <displayName>MODER</displayName> <description>GPIO port mode register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MODER15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTYPER</name> <displayName>OTYPER</displayName> <description>GPIO port output type register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OT15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OSPEEDR</name> <displayName>OSPEEDR</displayName> <description>GPIO port output speed register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OSPEEDR15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>PUPDR</name> <displayName>PUPDR</displayName> <description>GPIO port pull-up/pull-down register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PUPDR15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>IDR</name> <displayName>IDR</displayName> <description>GPIO port input data register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IDR15</name> <description>Port input data (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR14</name> <description>Port input data (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR13</name> <description>Port input data (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR12</name> <description>Port input data (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR11</name> <description>Port input data (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR10</name> <description>Port input data (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR9</name> <description>Port input data (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR8</name> <description>Port input data (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR7</name> <description>Port input data (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR6</name> <description>Port input data (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR5</name> <description>Port input data (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR4</name> <description>Port input data (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR3</name> <description>Port input data (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR2</name> <description>Port input data (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR1</name> <description>Port input data (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR0</name> <description>Port input data (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ODR</name> <displayName>ODR</displayName> <description>GPIO port output data register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ODR15</name> <description>Port output data (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR14</name> <description>Port output data (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR13</name> <description>Port output data (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR12</name> <description>Port output data (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR11</name> <description>Port output data (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR10</name> <description>Port output data (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR9</name> <description>Port output data (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR8</name> <description>Port output data (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR7</name> <description>Port output data (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR6</name> <description>Port output data (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR5</name> <description>Port output data (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR4</name> <description>Port output data (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR3</name> <description>Port output data (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR2</name> <description>Port output data (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR1</name> <description>Port output data (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR0</name> <description>Port output data (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BSRR</name> <displayName>BSRR</displayName> <description>GPIO port bit set/reset register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BR15</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR14</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR13</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR12</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR11</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR10</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR9</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR8</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR7</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR6</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR5</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR4</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR3</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR2</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR1</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR0</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS15</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS14</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS13</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS12</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS11</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS10</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS9</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS8</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS7</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS6</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS5</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS4</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS3</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS2</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS1</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS0</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>LCKR</name> <displayName>LCKR</displayName> <description>GPIO port configuration lock register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LCKK</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK15</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK14</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK13</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK12</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK11</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK10</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK9</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK8</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK7</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK6</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK5</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK4</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK3</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK2</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK1</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK0</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AFRL</name> <displayName>AFRL</displayName> <description>GPIO alternate function low register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AFRL7</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL6</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL5</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL4</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL3</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL2</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL1</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL0</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>AFRH</name> <displayName>AFRH</displayName> <description>GPIO alternate function high register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AFRH15</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH14</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH13</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH12</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH11</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH10</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH9</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH8</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="GPIOH"> <name>GPIOC</name> <baseAddress>0x40020800</baseAddress> </peripheral> <peripheral> <name>GPIOB</name> <description>General-purpose I/Os</description> <groupName>GPIO</groupName> <baseAddress>0x40020400</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>MODER</name> <displayName>MODER</displayName> <description>GPIO port mode register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000280</resetValue> <fields> <field> <name>MODER15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTYPER</name> <displayName>OTYPER</displayName> <description>GPIO port output type register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OT15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OSPEEDR</name> <displayName>OSPEEDR</displayName> <description>GPIO port output speed register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x000000C0</resetValue> <fields> <field> <name>OSPEEDR15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>PUPDR</name> <displayName>PUPDR</displayName> <description>GPIO port pull-up/pull-down register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000100</resetValue> <fields> <field> <name>PUPDR15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>IDR</name> <displayName>IDR</displayName> <description>GPIO port input data register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IDR15</name> <description>Port input data (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR14</name> <description>Port input data (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR13</name> <description>Port input data (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR12</name> <description>Port input data (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR11</name> <description>Port input data (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR10</name> <description>Port input data (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR9</name> <description>Port input data (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR8</name> <description>Port input data (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR7</name> <description>Port input data (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR6</name> <description>Port input data (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR5</name> <description>Port input data (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR4</name> <description>Port input data (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR3</name> <description>Port input data (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR2</name> <description>Port input data (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR1</name> <description>Port input data (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR0</name> <description>Port input data (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ODR</name> <displayName>ODR</displayName> <description>GPIO port output data register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ODR15</name> <description>Port output data (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR14</name> <description>Port output data (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR13</name> <description>Port output data (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR12</name> <description>Port output data (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR11</name> <description>Port output data (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR10</name> <description>Port output data (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR9</name> <description>Port output data (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR8</name> <description>Port output data (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR7</name> <description>Port output data (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR6</name> <description>Port output data (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR5</name> <description>Port output data (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR4</name> <description>Port output data (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR3</name> <description>Port output data (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR2</name> <description>Port output data (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR1</name> <description>Port output data (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR0</name> <description>Port output data (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BSRR</name> <displayName>BSRR</displayName> <description>GPIO port bit set/reset register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BR15</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR14</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR13</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR12</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR11</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR10</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR9</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR8</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR7</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR6</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR5</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR4</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR3</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR2</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR1</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR0</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS15</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS14</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS13</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS12</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS11</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS10</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS9</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS8</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS7</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS6</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS5</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS4</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS3</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS2</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS1</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS0</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>LCKR</name> <displayName>LCKR</displayName> <description>GPIO port configuration lock register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LCKK</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK15</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK14</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK13</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK12</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK11</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK10</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK9</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK8</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK7</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK6</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK5</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK4</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK3</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK2</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK1</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK0</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AFRL</name> <displayName>AFRL</displayName> <description>GPIO alternate function low register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AFRL7</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL6</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL5</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL4</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL3</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL2</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL1</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL0</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>AFRH</name> <displayName>AFRH</displayName> <description>GPIO alternate function high register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AFRH15</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH14</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH13</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH12</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH11</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH10</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH9</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH8</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>GPIOA</name> <description>General-purpose I/Os</description> <groupName>GPIO</groupName> <baseAddress>0x40020000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>MODER</name> <displayName>MODER</displayName> <description>GPIO port mode register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xA8000000</resetValue> <fields> <field> <name>MODER15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTYPER</name> <displayName>OTYPER</displayName> <description>GPIO port output type register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OT15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OSPEEDR</name> <displayName>OSPEEDR</displayName> <description>GPIO port output speed register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OSPEEDR15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>PUPDR</name> <displayName>PUPDR</displayName> <description>GPIO port pull-up/pull-down register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x64000000</resetValue> <fields> <field> <name>PUPDR15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>IDR</name> <displayName>IDR</displayName> <description>GPIO port input data register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IDR15</name> <description>Port input data (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR14</name> <description>Port input data (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR13</name> <description>Port input data (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR12</name> <description>Port input data (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR11</name> <description>Port input data (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR10</name> <description>Port input data (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR9</name> <description>Port input data (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR8</name> <description>Port input data (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR7</name> <description>Port input data (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR6</name> <description>Port input data (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR5</name> <description>Port input data (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR4</name> <description>Port input data (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR3</name> <description>Port input data (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR2</name> <description>Port input data (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR1</name> <description>Port input data (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR0</name> <description>Port input data (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ODR</name> <displayName>ODR</displayName> <description>GPIO port output data register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ODR15</name> <description>Port output data (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR14</name> <description>Port output data (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR13</name> <description>Port output data (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR12</name> <description>Port output data (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR11</name> <description>Port output data (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR10</name> <description>Port output data (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR9</name> <description>Port output data (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR8</name> <description>Port output data (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR7</name> <description>Port output data (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR6</name> <description>Port output data (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR5</name> <description>Port output data (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR4</name> <description>Port output data (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR3</name> <description>Port output data (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR2</name> <description>Port output data (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR1</name> <description>Port output data (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR0</name> <description>Port output data (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BSRR</name> <displayName>BSRR</displayName> <description>GPIO port bit set/reset register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BR15</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR14</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR13</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR12</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR11</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR10</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR9</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR8</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR7</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR6</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR5</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR4</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR3</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR2</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR1</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR0</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS15</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS14</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS13</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS12</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS11</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS10</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS9</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS8</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS7</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS6</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS5</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS4</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS3</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS2</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS1</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS0</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>LCKR</name> <displayName>LCKR</displayName> <description>GPIO port configuration lock register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LCKK</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK15</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK14</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK13</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK12</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK11</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK10</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK9</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK8</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK7</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK6</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK5</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK4</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK3</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK2</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK1</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK0</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AFRL</name> <displayName>AFRL</displayName> <description>GPIO alternate function low register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AFRL7</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL6</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL5</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL4</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL3</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL2</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL1</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL0</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>AFRH</name> <displayName>AFRH</displayName> <description>GPIO alternate function high register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AFRH15</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH14</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH13</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH12</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH11</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH10</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH9</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH8</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>I2C2</name> <description>Inter-integrated circuit</description> <groupName>I2C</groupName> <baseAddress>0x40005800</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>I2C2_EV</name> <description>I2C2 event interrupt</description> <value>33</value> </interrupt> <interrupt> <name>I2C2_ER</name> <description>I2C2 error interrupt</description> <value>34</value> </interrupt> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>Control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>SWRST</name> <description>Software reset</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALERT</name> <description>SMBus alert</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PEC</name> <description>Packet error checking</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>POS</name> <description>Acknowledge/PEC Position (for data reception)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>Acknowledge enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STOP</name> <description>Stop generation</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>START</name> <description>Start generation</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NOSTRETCH</name> <description>Clock stretching disable (Slave mode)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ENGC</name> <description>General call enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ENPEC</name> <description>PEC enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ENARP</name> <description>ARP enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SMBTYPE</name> <description>SMBus type</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SMBUS</name> <description>SMBus mode</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PE</name> <description>Peripheral enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>Control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>LAST</name> <description>DMA last transfer</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAEN</name> <description>DMA requests enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITBUFEN</name> <description>Buffer interrupt enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITEVTEN</name> <description>Event interrupt enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITERREN</name> <description>Error interrupt enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FREQ</name> <description>Peripheral clock frequency</description> <bitOffset>0</bitOffset> <bitWidth>6</bitWidth> </field> </fields> </register> <register> <name>OAR1</name> <displayName>OAR1</displayName> <description>Own address register 1</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>ADDMODE</name> <description>Addressing mode (slave mode)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADD10</name> <description>Interface address</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ADD7</name> <description>Interface address</description> <bitOffset>1</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ADD0</name> <description>Interface address</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OAR2</name> <displayName>OAR2</displayName> <description>Own address register 2</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>ADD2</name> <description>Interface address</description> <bitOffset>1</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ENDUAL</name> <description>Dual addressing mode enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DR</name> <displayName>DR</displayName> <description>Data register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DR</name> <description>8-bit data register</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>SR1</name> <displayName>SR1</displayName> <description>Status register 1</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <resetValue>0x0000</resetValue> <fields> <field> <name>SMBALERT</name> <description>SMBus alert</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TIMEOUT</name> <description>Timeout or Tlow error</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PECERR</name> <description>PEC Error in reception</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>OVR</name> <description>Overrun/Underrun</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>AF</name> <description>Acknowledge failure</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ARLO</name> <description>Arbitration lost (master mode)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BERR</name> <description>Bus error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TxE</name> <description>Data register empty (transmitters)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>RxNE</name> <description>Data register not empty (receivers)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>STOPF</name> <description>Stop detection (slave mode)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ADD10</name> <description>10-bit header sent (Master mode)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>BTF</name> <description>Byte transfer finished</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ADDR</name> <description>Address sent (master mode)/matched (slave mode)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>SB</name> <description>Start bit (Master mode)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>SR2</name> <displayName>SR2</displayName> <description>Status register 2</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PEC</name> <description>acket error checking register</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DUALF</name> <description>Dual flag (Slave mode)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SMBHOST</name> <description>SMBus host header (Slave mode)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SMBDEFAULT</name> <description>SMBus device default address (Slave mode)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GENCALL</name> <description>General call address (Slave mode)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TRA</name> <description>Transmitter/receiver</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BUSY</name> <description>Bus busy</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSL</name> <description>Master/slave</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCR</name> <displayName>CCR</displayName> <description>Clock control register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>F_S</name> <description>I2C master mode selection</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DUTY</name> <description>Fast mode duty cycle</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CCR</name> <description>Clock control register in Fast/Standard mode (Master mode)</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>TRISE</name> <displayName>TRISE</displayName> <description>TRISE register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0002</resetValue> <fields> <field> <name>TRISE</name> <description>Maximum rise time in Fast/Standard mode (Master mode)</description> <bitOffset>0</bitOffset> <bitWidth>6</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="I2C2"> <name>I2C1</name> <baseAddress>0x40005400</baseAddress> <interrupt> <name>I2C1_EV</name> <description>I2C1 event interrupt</description> <value>31</value> </interrupt> <interrupt> <name>I2C1_ER</name> <description>I2C1 error interrupt</description> <value>32</value> </interrupt> </peripheral> <peripheral> <name>SPI1</name> <description>Serial peripheral interface</description> <groupName>SPI</groupName> <baseAddress>0x40013000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>SPI1</name> <description>SPI1 global interrupt</description> <value>35</value> </interrupt> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>BIDIMODE</name> <description>Bidirectional data mode enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BIDIOE</name> <description>Output enable in bidirectional mode</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CRCEN</name> <description>Hardware CRC calculation enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CRCNEXT</name> <description>CRC transfer next</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DFF</name> <description>Data frame format</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXONLY</name> <description>Receive only</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SSM</name> <description>Software slave management</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SSI</name> <description>Internal slave select</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSBFIRST</name> <description>Frame format</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPE</name> <description>SPI enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR</name> <description>Baud rate control</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MSTR</name> <description>Master selection</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CPOL</name> <description>Clock polarity</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CPHA</name> <description>Clock phase</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TXEIE</name> <description>Tx buffer empty interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXNEIE</name> <description>RX buffer not empty interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ERRIE</name> <description>Error interrupt enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRF</name> <description>Frame format</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SSOE</name> <description>SS output enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXDMAEN</name> <description>Tx buffer DMA enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXDMAEN</name> <description>Rx buffer DMA enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <resetValue>0x0002</resetValue> <fields> <field> <name>TIFRFE</name> <description>TI frame format error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>BSY</name> <description>Busy flag</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>OVR</name> <description>Overrun flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>MODF</name> <description>Mode fault</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>CRCERR</name> <description>CRC error flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>UDR</name> <description>Underrun flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>CHSIDE</name> <description>Channel side</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TXE</name> <description>Transmit buffer empty</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>RXNE</name> <description>Receive buffer not empty</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>DR</name> <displayName>DR</displayName> <description>data register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DR</name> <description>Data register</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CRCPR</name> <displayName>CRCPR</displayName> <description>CRC polynomial register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0007</resetValue> <fields> <field> <name>CRCPOLY</name> <description>CRC polynomial register</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>RXCRCR</name> <displayName>RXCRCR</displayName> <description>RX CRC register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>RxCRC</name> <description>Rx CRC register</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>TXCRCR</name> <displayName>TXCRCR</displayName> <description>TX CRC register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TxCRC</name> <description>Tx CRC register</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>I2SCFGR</name> <displayName>I2SCFGR</displayName> <description>I2S configuration register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>I2SMOD</name> <description>I2S mode selection</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2SE</name> <description>I2S Enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2SCFG</name> <description>I2S configuration mode</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PCMSYNC</name> <description>PCM frame synchronization</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2SSTD</name> <description>I2S standard selection</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CKPOL</name> <description>Steady state clock polarity</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DATLEN</name> <description>Data length to be transferred</description> <bitOffset>1</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CHLEN</name> <description>Channel length (number of bits per audio channel)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>I2SPR</name> <displayName>I2SPR</displayName> <description>I2S prescaler register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>00000010</resetValue> <fields> <field> <name>MCKOE</name> <description>Master clock output enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODD</name> <description>Odd factor for the prescaler</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2SDIV</name> <description>I2S Linear prescaler</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="SPI1"> <name>SPI2</name> <baseAddress>0x40003800</baseAddress> <interrupt> <name>SPI2</name> <description>SPI2 global interrupt</description> <value>36</value> </interrupt> </peripheral> <peripheral derivedFrom="SPI1"> <name>SPI5</name> <baseAddress>0x40015000</baseAddress> </peripheral> <peripheral> <name>NVIC</name> <description>Nested Vectored Interrupt Controller</description> <groupName>NVIC</groupName> <baseAddress>0xE000E100</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x351</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>ISER0</name> <displayName>ISER0</displayName> <description>Interrupt Set-Enable Register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SETENA</name> <description>SETENA</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ISER1</name> <displayName>ISER1</displayName> <description>Interrupt Set-Enable Register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SETENA</name> <description>SETENA</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ISER2</name> <displayName>ISER2</displayName> <description>Interrupt Set-Enable Register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SETENA</name> <description>SETENA</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ICER0</name> <displayName>ICER0</displayName> <description>Interrupt Clear-Enable Register</description> <addressOffset>0x80</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CLRENA</name> <description>CLRENA</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ICER1</name> <displayName>ICER1</displayName> <description>Interrupt Clear-Enable Register</description> <addressOffset>0x84</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CLRENA</name> <description>CLRENA</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ICER2</name> <displayName>ICER2</displayName> <description>Interrupt Clear-Enable Register</description> <addressOffset>0x88</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CLRENA</name> <description>CLRENA</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ISPR0</name> <displayName>ISPR0</displayName> <description>Interrupt Set-Pending Register</description> <addressOffset>0x100</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SETPEND</name> <description>SETPEND</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ISPR1</name> <displayName>ISPR1</displayName> <description>Interrupt Set-Pending Register</description> <addressOffset>0x104</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SETPEND</name> <description>SETPEND</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ISPR2</name> <displayName>ISPR2</displayName> <description>Interrupt Set-Pending Register</description> <addressOffset>0x108</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SETPEND</name> <description>SETPEND</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ICPR0</name> <displayName>ICPR0</displayName> <description>Interrupt Clear-Pending Register</description> <addressOffset>0x180</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CLRPEND</name> <description>CLRPEND</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ICPR1</name> <displayName>ICPR1</displayName> <description>Interrupt Clear-Pending Register</description> <addressOffset>0x184</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CLRPEND</name> <description>CLRPEND</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ICPR2</name> <displayName>ICPR2</displayName> <description>Interrupt Clear-Pending Register</description> <addressOffset>0x188</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CLRPEND</name> <description>CLRPEND</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>IABR0</name> <displayName>IABR0</displayName> <description>Interrupt Active Bit Register</description> <addressOffset>0x200</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ACTIVE</name> <description>ACTIVE</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>IABR1</name> <displayName>IABR1</displayName> <description>Interrupt Active Bit Register</description> <addressOffset>0x204</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ACTIVE</name> <description>ACTIVE</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>IABR2</name> <displayName>IABR2</displayName> <description>Interrupt Active Bit Register</description> <addressOffset>0x208</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ACTIVE</name> <description>ACTIVE</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>IPR0</name> <displayName>IPR0</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x300</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR1</name> <displayName>IPR1</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x304</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR2</name> <displayName>IPR2</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x308</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR3</name> <displayName>IPR3</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x30C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR4</name> <displayName>IPR4</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x310</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR5</name> <displayName>IPR5</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x314</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR6</name> <displayName>IPR6</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x318</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR7</name> <displayName>IPR7</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x31C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR8</name> <displayName>IPR8</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x320</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR9</name> <displayName>IPR9</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x324</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR10</name> <displayName>IPR10</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x328</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR11</name> <displayName>IPR11</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x32C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR12</name> <displayName>IPR12</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x330</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR13</name> <displayName>IPR13</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x334</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR14</name> <displayName>IPR14</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x338</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR15</name> <displayName>IPR15</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x33C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR16</name> <displayName>IPR16</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x340</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR17</name> <displayName>IPR17</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x344</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR18</name> <displayName>IPR18</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x348</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR19</name> <displayName>IPR19</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x34C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>TIM6</name> <description>Basic timers</description> <groupName>TIM</groupName> <baseAddress>0x40001000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>TIM6_DAC1</name> <description>Timer6 and DAC1 global interrupt</description> <value>54</value> </interrupt> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>ARPE</name> <description>Auto-reload preload enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPM</name> <description>One-pulse mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>URS</name> <description>Update request source</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDIS</name> <description>Update disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CEN</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>MMS</name> <description>Master mode selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>DIER</name> <displayName>DIER</displayName> <description>DMA/Interrupt enable register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>UDE</name> <description>Update DMA request enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIE</name> <description>Update interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>UIF</name> <description>Update interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EGR</name> <displayName>EGR</displayName> <description>event generation register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>UG</name> <description>Update generation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CNT</name> <displayName>CNT</displayName> <description>counter</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CNT</name> <description>Low counter value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>PSC</name> <displayName>PSC</displayName> <description>prescaler</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ARR</name> <displayName>ARR</displayName> <description>auto-reload register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ARR</name> <description>Low Auto-reload value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>RNG</name> <description>Random number generator</description> <groupName>RNG</groupName> <baseAddress>0x40080000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>RNG</name> <description>RNG global interrupt</description> <value>80</value> </interrupt> <registers> <register> <name>CR</name> <displayName>CR</displayName> <description>control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IE</name> <description>Interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RNGEN</name> <description>Random number generator enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>SEIS</name> <description>Seed error interrupt status</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>CEIS</name> <description>Clock error interrupt status</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SECS</name> <description>Seed error current status</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>CECS</name> <description>Clock error current status</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>DRDY</name> <description>Data ready</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>DR</name> <displayName>DR</displayName> <description>data register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RNDATA</name> <description>Random data</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>DAC</name> <description>Digital-to-analog converter</description> <groupName>DAC</groupName> <baseAddress>0x40007400</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CR</name> <displayName>CR</displayName> <description>control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DMAUDRIE2</name> <description>DAC channel2 DMA underrun interrupt enable</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAEN2</name> <description>DAC channel2 DMA enable</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MAMP2</name> <description>DAC channel2 mask/amplitude selector</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>WAVE2</name> <description>DAC channel2 noise/triangle wave generation enable</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>TSEL2</name> <description>DAC channel2 trigger selection</description> <bitOffset>19</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>TEN2</name> <description>DAC channel2 trigger enable</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BOFF2</name> <description>DAC channel2 output buffer disable</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN2</name> <description>DAC channel2 enable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAUDRIE1</name> <description>DAC channel1 DMA Underrun Interrupt enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAEN1</name> <description>DAC channel1 DMA enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MAMP1</name> <description>DAC channel1 mask/amplitude selector</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>WAVE1</name> <description>DAC channel1 noise/triangle wave generation enable</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>TSEL1</name> <description>DAC channel1 trigger selection</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>TEN1</name> <description>DAC channel1 trigger enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BOFF1</name> <description>DAC channel1 output buffer disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN1</name> <description>DAC channel1 enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SWTRIGR</name> <displayName>SWTRIGR</displayName> <description>software trigger register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SWTRIG2</name> <description>DAC channel2 software trigger</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWTRIG1</name> <description>DAC channel1 software trigger</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DHR12R1</name> <displayName>DHR12R1</displayName> <description>channel1 12-bit right-aligned data holding register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC1DHR</name> <description>DAC channel1 12-bit right-aligned data</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>DHR12L1</name> <displayName>DHR12L1</displayName> <description>channel1 12-bit left aligned data holding register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC1DHR</name> <description>DAC channel1 12-bit left-aligned data</description> <bitOffset>4</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>DHR8R1</name> <displayName>DHR8R1</displayName> <description>channel1 8-bit right aligned data holding register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC1DHR</name> <description>DAC channel1 8-bit right-aligned data</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>DHR12R2</name> <displayName>DHR12R2</displayName> <description>channel2 12-bit right aligned data holding register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC2DHR</name> <description>DAC channel2 12-bit right-aligned data</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>DHR12L2</name> <displayName>DHR12L2</displayName> <description>channel2 12-bit left aligned data holding register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC2DHR</name> <description>DAC channel2 12-bit left-aligned data</description> <bitOffset>4</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>DHR8R2</name> <displayName>DHR8R2</displayName> <description>channel2 8-bit right-aligned data holding register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC2DHR</name> <description>DAC channel2 8-bit right-aligned data</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>DHR12RD</name> <displayName>DHR12RD</displayName> <description>Dual DAC 12-bit right-aligned data holding register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC2DHR</name> <description>DAC channel2 12-bit right-aligned data</description> <bitOffset>16</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>DACC1DHR</name> <description>DAC channel1 12-bit right-aligned data</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>DHR12LD</name> <displayName>DHR12LD</displayName> <description>DUAL DAC 12-bit left aligned data holding register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC2DHR</name> <description>DAC channel2 12-bit left-aligned data</description> <bitOffset>20</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>DACC1DHR</name> <description>DAC channel1 12-bit left-aligned data</description> <bitOffset>4</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>DHR8RD</name> <displayName>DHR8RD</displayName> <description>DUAL DAC 8-bit right aligned data holding register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC2DHR</name> <description>DAC channel2 8-bit right-aligned data</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DACC1DHR</name> <description>DAC channel1 8-bit right-aligned data</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>DOR1</name> <displayName>DOR1</displayName> <description>channel1 data output register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC1DOR</name> <description>DAC channel1 data output</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>DOR2</name> <displayName>DOR2</displayName> <description>channel2 data output register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC2DOR</name> <description>DAC channel2 data output</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DMAUDR2</name> <description>DAC channel2 DMA underrun flag</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAUDR1</name> <description>DAC channel1 DMA underrun flag</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>LPTIM1</name> <description>Low power timer</description> <groupName>LPTIM</groupName> <baseAddress>0x40002400</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>LPTIM1</name> <description>LPTimer global interrupt</description> <value>97</value> </interrupt> <registers> <register> <name>ISR</name> <displayName>ISR</displayName> <description>Interrupt and Status Register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DOWN</name> <description>Counter direction change up to down</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UP</name> <description>Counter direction change down to up</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ARROK</name> <description>Autoreload register update OK</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMPOK</name> <description>Compare register update OK</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTTRIG</name> <description>External trigger edge event</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ARRM</name> <description>Autoreload match</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMPM</name> <description>Compare match</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ICR</name> <displayName>ICR</displayName> <description>Interrupt Clear Register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DOWNCF</name> <description>Direction change to down Clear Flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UPCF</name> <description>Direction change to UP Clear Flag</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ARROKCF</name> <description>Autoreload register update OK Clear Flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMPOKCF</name> <description>Compare register update OK Clear Flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTTRIGCF</name> <description>External trigger valid edge Clear Flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ARRMCF</name> <description>Autoreload match Clear Flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMPMCF</name> <description>compare match Clear Flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>IER</name> <displayName>IER</displayName> <description>Interrupt Enable Register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DOWNIE</name> <description>Direction change to down Interrupt Enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UPIE</name> <description>Direction change to UP Interrupt Enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ARROKIE</name> <description>Autoreload register update OK Interrupt Enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMPOKIE</name> <description>Compare register update OK Interrupt Enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTTRIGIE</name> <description>External trigger valid edge Interrupt Enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ARRMIE</name> <description>Autoreload match Interrupt Enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMPMIE</name> <description>Compare match Interrupt Enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CFGR</name> <displayName>CFGR</displayName> <description>Configuration Register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ENC</name> <description>Encoder mode enable</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COUNTMODE</name> <description>counter mode enabled</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PRELOAD</name> <description>Registers update mode</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAVPOL</name> <description>Waveform shape polarity</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAVE</name> <description>Waveform shape</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIMOUT</name> <description>Timeout enable</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TRIGEN</name> <description>Trigger enable and polarity</description> <bitOffset>17</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>TRIGSEL</name> <description>Trigger selector</description> <bitOffset>13</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>PRESC</name> <description>Clock prescaler</description> <bitOffset>9</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>TRGFLT</name> <description>Configurable digital filter for trigger</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CKFLT</name> <description>Configurable digital filter for external clock</description> <bitOffset>3</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CKPOL</name> <description>Clock Polarity</description> <bitOffset>1</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CKSEL</name> <description>Clock selector</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR</name> <displayName>CR</displayName> <description>Control Register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CNTSTRT</name> <description>Timer start in continuous mode</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SNGSTRT</name> <description>LPTIM start in single mode</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ENABLE</name> <description>LPTIM Enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CMP</name> <displayName>CMP</displayName> <description>Compare Register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CMP</name> <description>Compare value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ARR</name> <displayName>ARR</displayName> <description>Autoreload Register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000001</resetValue> <fields> <field> <name>ARR</name> <description>Auto reload value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CNT</name> <displayName>CNT</displayName> <description>Counter Register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CNT</name> <description>Counter value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OPTR</name> <displayName>OPTR</displayName> <description>Option Register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OR</name> <description>OR</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>I2C4</name> <description>Inter-integrated circuit</description> <groupName>I2C</groupName> <baseAddress>0x40006000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>I2C4_EV</name> <description>I2C4 event interrupt</description> <value>95</value> </interrupt> <interrupt> <name>I2C4_ER</name> <description>I2C2 error interrupt</description> <value>96</value> </interrupt> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>Control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PE</name> <description>Peripheral enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXIE</name> <description>TX Interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXIE</name> <description>RX Interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADDRIE</name> <description>Address match interrupt enable (slave only)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NACKIE</name> <description>Not acknowledge received interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STOPIE</name> <description>STOP detection Interrupt enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer Complete interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ERRIE</name> <description>Error interrupts enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DNF</name> <description>Digital noise filter</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ANFOFF</name> <description>Analog noise filter OFF</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXDMAEN</name> <description>DMA transmission requests enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXDMAEN</name> <description>DMA reception requests enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SBC</name> <description>Slave byte control</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NOSTRETCH</name> <description>Clock stretching disable</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WUPEN</name> <description>Wakeup from STOP enable</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GCEN</name> <description>General call enable</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SMBHEN</name> <description>SMBus Host address enable</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SMBDEN</name> <description>SMBus Device Default address enable</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALERTEN</name> <description>SMBUS alert enable</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PECEN</name> <description>PEC enable</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>Control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PECBYTE</name> <description>Packet error checking byte</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AUTOEND</name> <description>Automatic end mode (master mode)</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RELOAD</name> <description>NBYTES reload mode</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NBYTES</name> <description>Number of bytes</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>NACK</name> <description>NACK generation (slave mode)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STOP</name> <description>Stop generation (master mode)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>START</name> <description>Start generation</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HEAD10R</name> <description>10-bit address header only read direction (master receiver mode)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADD10</name> <description>10-bit addressing mode (master mode)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RD_WRN</name> <description>Transfer direction (master mode)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SADD</name> <description>Slave address bit (master mode)</description> <bitOffset>0</bitOffset> <bitWidth>10</bitWidth> </field> </fields> </register> <register> <name>OAR1</name> <displayName>OAR1</displayName> <description>Own address register 1</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OA1</name> <description>Interface address</description> <bitOffset>0</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>OA1MODE</name> <description>Own Address 1 10-bit mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OA1EN</name> <description>Own Address 1 enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OAR2</name> <displayName>OAR2</displayName> <description>Own address register 2</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OA2</name> <description>Interface address</description> <bitOffset>1</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>OA2MSK</name> <description>Own Address 2 masks</description> <bitOffset>8</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OA2EN</name> <description>Own Address 2 enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>TIMINGR</name> <displayName>TIMINGR</displayName> <description>Timing register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SCLL</name> <description>SCL low period (master mode)</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>SCLH</name> <description>SCL high period (master mode)</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>SDADEL</name> <description>Data hold time</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>SCLDEL</name> <description>Data setup time</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>PRESC</name> <description>Timing prescaler</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>TIMEOUTR</name> <displayName>TIMEOUTR</displayName> <description>Status register 1</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIMEOUTA</name> <description>Bus timeout A</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>TIDLE</name> <description>Idle clock timeout detection</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIMOUTEN</name> <description>Clock timeout enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIMEOUTB</name> <description>Bus timeout B</description> <bitOffset>16</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>TEXTEN</name> <description>Extended clock timeout enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ISR</name> <displayName>ISR</displayName> <description>Interrupt and Status register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <resetValue>0x00000001</resetValue> <fields> <field> <name>ADDCODE</name> <description>Address match code (Slave mode)</description> <bitOffset>17</bitOffset> <bitWidth>7</bitWidth> <access>read-only</access> </field> <field> <name>DIR</name> <description>Transfer direction (Slave mode)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>BUSY</name> <description>Bus busy</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ALERT</name> <description>SMBus alert</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TIMEOUT</name> <description>Timeout or t_low detection flag</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>PECERR</name> <description>PEC Error in reception</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>OVR</name> <description>Overrun/Underrun (slave mode)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ARLO</name> <description>Arbitration lost</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>BERR</name> <description>Bus error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TCR</name> <description>Transfer Complete Reload</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TC</name> <description>Transfer Complete (master mode)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>STOPF</name> <description>Stop detection flag</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NACKF</name> <description>Not acknowledge received flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ADDR</name> <description>Address matched (slave mode)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>RXNE</name> <description>Receive data register not empty (receivers)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TXIS</name> <description>Transmit interrupt status (transmitters)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXE</name> <description>Transmit data register empty (transmitters)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>ICR</name> <displayName>ICR</displayName> <description>Interrupt clear register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ALERTCF</name> <description>Alert flag clear</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIMOUTCF</name> <description>Timeout detection flag clear</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PECCF</name> <description>PEC Error flag clear</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVRCF</name> <description>Overrun/Underrun flag clear</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ARLOCF</name> <description>Arbitration lost flag clear</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BERRCF</name> <description>Bus error flag clear</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STOPCF</name> <description>Stop detection flag clear</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NACKCF</name> <description>Not Acknowledge flag clear</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADDRCF</name> <description>Address Matched flag clear</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PECR</name> <displayName>PECR</displayName> <description>PEC register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PEC</name> <description>Packet error checking register</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>RXDR</name> <displayName>RXDR</displayName> <description>Receive data register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RXDATA</name> <description>8-bit receive data</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>TXDR</name> <displayName>TXDR</displayName> <description>Transmit data register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TXDATA</name> <description>8-bit transmit data</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>FPU</name> <description>Floting point unit</description> <groupName>FPU</groupName> <baseAddress>0xE000EF34</baseAddress> <addressBlock> <offset>0x0</offset> <size>0xD</size> <usage>registers</usage> </addressBlock> <interrupt> <name>FPU</name> <description>Floating point unit interrupt</description> <value>81</value> </interrupt> <interrupt> <name>FPU</name> <description>Floating point interrupt</description> <value>81</value> </interrupt> <registers> <register> <name>FPCCR</name> <displayName>FPCCR</displayName> <description>Floating-point context control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LSPACT</name> <description>LSPACT</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USER</name> <description>USER</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>THREAD</name> <description>THREAD</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HFRDY</name> <description>HFRDY</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MMRDY</name> <description>MMRDY</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BFRDY</name> <description>BFRDY</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MONRDY</name> <description>MONRDY</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSPEN</name> <description>LSPEN</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ASPEN</name> <description>ASPEN</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FPCAR</name> <displayName>FPCAR</displayName> <description>Floating-point context address register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ADDRESS</name> <description>Location of unpopulated floating-point</description> <bitOffset>3</bitOffset> <bitWidth>29</bitWidth> </field> </fields> </register> <register> <name>FPSCR</name> <displayName>FPSCR</displayName> <description>Floating-point status control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IOC</name> <description>Invalid operation cumulative exception bit</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DZC</name> <description>Division by zero cumulative exception bit.</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OFC</name> <description>Overflow cumulative exception bit</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UFC</name> <description>Underflow cumulative exception bit</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IXC</name> <description>Inexact cumulative exception bit</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDC</name> <description>Input denormal cumulative exception bit.</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RMode</name> <description>Rounding Mode control field</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>FZ</name> <description>Flush-to-zero mode control bit:</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DN</name> <description>Default NaN mode control bit</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHP</name> <description>Alternative half-precision control bit</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>V</name> <description>Overflow condition code flag</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>C</name> <description>Carry condition code flag</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>Z</name> <description>Zero condition code flag</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>N</name> <description>Negative condition code flag</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>MPU</name> <description>Memory protection unit</description> <groupName>MPU</groupName> <baseAddress>0xE000ED90</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x15</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>MPU_TYPER</name> <displayName>MPU_TYPER</displayName> <description>MPU type register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0X00000800</resetValue> <fields> <field> <name>SEPARATE</name> <description>Separate flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DREGION</name> <description>Number of MPU data regions</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IREGION</name> <description>Number of MPU instruction regions</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>MPU_CTRL</name> <displayName>MPU_CTRL</displayName> <description>MPU control register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>ENABLE</name> <description>Enables the MPU</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HFNMIENA</name> <description>Enables the operation of MPU during hard fault</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PRIVDEFENA</name> <description>Enable priviliged software access to default memory map</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MPU_RNR</name> <displayName>MPU_RNR</displayName> <description>MPU region number register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>REGION</name> <description>MPU region</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>MPU_RBAR</name> <displayName>MPU_RBAR</displayName> <description>MPU region base address register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>REGION</name> <description>MPU region field</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>VALID</name> <description>MPU region number valid</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADDR</name> <description>Region base address field</description> <bitOffset>5</bitOffset> <bitWidth>27</bitWidth> </field> </fields> </register> <register> <name>MPU_RASR</name> <displayName>MPU_RASR</displayName> <description>MPU region attribute and size register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>ENABLE</name> <description>Region enable bit.</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SIZE</name> <description>Size of the MPU protection region</description> <bitOffset>1</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SRD</name> <description>Subregion disable bits</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>B</name> <description>memory attribute</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>C</name> <description>memory attribute</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>S</name> <description>Shareable memory attribute</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEX</name> <description>memory attribute</description> <bitOffset>19</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>AP</name> <description>Access permission</description> <bitOffset>24</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>XN</name> <description>Instruction access disable bit</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>STK</name> <description>SysTick timer</description> <groupName>STK</groupName> <baseAddress>0xE000E010</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x11</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CTRL</name> <displayName>CTRL</displayName> <description>SysTick control and status register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>ENABLE</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TICKINT</name> <description>SysTick exception request enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CLKSOURCE</name> <description>Clock source selection</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COUNTFLAG</name> <description>COUNTFLAG</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>LOAD</name> <displayName>LOAD</displayName> <description>SysTick reload value register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>RELOAD</name> <description>RELOAD value</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> </field> </fields> </register> <register> <name>VAL</name> <displayName>VAL</displayName> <description>SysTick current value register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>CURRENT</name> <description>Current counter value</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> </field> </fields> </register> <register> <name>CALIB</name> <displayName>CALIB</displayName> <description>SysTick calibration value register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>TENMS</name> <description>Calibration value</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> </field> <field> <name>SKEW</name> <description>SKEW flag: Indicates whether the TENMS value is exact</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NOREF</name> <description>NOREF flag. Reads as zero</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>SCB</name> <description>System control block</description> <groupName>SCB</groupName> <baseAddress>0xE000ED00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x41</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CPUID</name> <displayName>CPUID</displayName> <description>CPUID base register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x410FC241</resetValue> <fields> <field> <name>Revision</name> <description>Revision number</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>PartNo</name> <description>Part number of the processor</description> <bitOffset>4</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>Constant</name> <description>Reads as 0xF</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>Variant</name> <description>Variant number</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>Implementer</name> <description>Implementer code</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>ICSR</name> <displayName>ICSR</displayName> <description>Interrupt control and state register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>VECTACTIVE</name> <description>Active vector</description> <bitOffset>0</bitOffset> <bitWidth>9</bitWidth> </field> <field> <name>RETTOBASE</name> <description>Return to base level</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VECTPENDING</name> <description>Pending vector</description> <bitOffset>12</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ISRPENDING</name> <description>Interrupt pending flag</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PENDSTCLR</name> <description>SysTick exception clear-pending bit</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PENDSTSET</name> <description>SysTick exception set-pending bit</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PENDSVCLR</name> <description>PendSV clear-pending bit</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PENDSVSET</name> <description>PendSV set-pending bit</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NMIPENDSET</name> <description>NMI set-pending bit.</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>VTOR</name> <displayName>VTOR</displayName> <description>Vector table offset register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TBLOFF</name> <description>Vector table base offset field</description> <bitOffset>9</bitOffset> <bitWidth>21</bitWidth> </field> </fields> </register> <register> <name>AIRCR</name> <displayName>AIRCR</displayName> <description>Application interrupt and reset control register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>VECTRESET</name> <description>VECTRESET</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VECTCLRACTIVE</name> <description>VECTCLRACTIVE</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SYSRESETREQ</name> <description>SYSRESETREQ</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PRIGROUP</name> <description>PRIGROUP</description> <bitOffset>8</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>ENDIANESS</name> <description>ENDIANESS</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VECTKEYSTAT</name> <description>Register key</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>SCR</name> <displayName>SCR</displayName> <description>System control register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SLEEPONEXIT</name> <description>SLEEPONEXIT</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SLEEPDEEP</name> <description>SLEEPDEEP</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SEVEONPEND</name> <description>Send Event on Pending bit</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCR</name> <displayName>CCR</displayName> <description>Configuration and control register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NONBASETHRDENA</name> <description>Configures how the processor enters Thread mode</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USERSETMPEND</name> <description>USERSETMPEND</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UNALIGN__TRP</name> <description>UNALIGN_ TRP</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIV_0_TRP</name> <description>DIV_0_TRP</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BFHFNMIGN</name> <description>BFHFNMIGN</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STKALIGN</name> <description>STKALIGN</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SHPR1</name> <displayName>SHPR1</displayName> <description>System handler priority registers</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PRI_4</name> <description>Priority of system handler 4</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_5</name> <description>Priority of system handler 5</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_6</name> <description>Priority of system handler 6</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>SHPR2</name> <displayName>SHPR2</displayName> <description>System handler priority registers</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PRI_11</name> <description>Priority of system handler 11</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>SHPR3</name> <displayName>SHPR3</displayName> <description>System handler priority registers</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PRI_14</name> <description>Priority of system handler 14</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_15</name> <description>Priority of system handler 15</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>SHCRS</name> <displayName>SHCRS</displayName> <description>System handler control and state register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MEMFAULTACT</name> <description>Memory management fault exception active bit</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BUSFAULTACT</name> <description>Bus fault exception active bit</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USGFAULTACT</name> <description>Usage fault exception active bit</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SVCALLACT</name> <description>SVC call active bit</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MONITORACT</name> <description>Debug monitor active bit</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PENDSVACT</name> <description>PendSV exception active bit</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SYSTICKACT</name> <description>SysTick exception active bit</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USGFAULTPENDED</name> <description>Usage fault exception pending bit</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MEMFAULTPENDED</name> <description>Memory management fault exception pending bit</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BUSFAULTPENDED</name> <description>Bus fault exception pending bit</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SVCALLPENDED</name> <description>SVC call pending bit</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MEMFAULTENA</name> <description>Memory management fault enable bit</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BUSFAULTENA</name> <description>Bus fault enable bit</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USGFAULTENA</name> <description>Usage fault enable bit</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CFSR_UFSR_BFSR_MMFSR</name> <displayName>CFSR_UFSR_BFSR_MMFSR</displayName> <description>Configurable fault status register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IACCVIOL</name> <description>Instruction access violation flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MUNSTKERR</name> <description>Memory manager fault on unstacking for a return from exception</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSTKERR</name> <description>Memory manager fault on stacking for exception entry.</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MLSPERR</name> <description>MLSPERR</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MMARVALID</name> <description>Memory Management Fault Address Register (MMAR) valid flag</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IBUSERR</name> <description>Instruction bus error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PRECISERR</name> <description>Precise data bus error</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IMPRECISERR</name> <description>Imprecise data bus error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UNSTKERR</name> <description>Bus fault on unstacking for a return from exception</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STKERR</name> <description>Bus fault on stacking for exception entry</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSPERR</name> <description>Bus fault on floating-point lazy state preservation</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BFARVALID</name> <description>Bus Fault Address Register (BFAR) valid flag</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UNDEFINSTR</name> <description>Undefined instruction usage fault</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>INVSTATE</name> <description>Invalid state usage fault</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>INVPC</name> <description>Invalid PC load usage fault</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NOCP</name> <description>No coprocessor usage fault.</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UNALIGNED</name> <description>Unaligned access usage fault</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIVBYZERO</name> <description>Divide by zero usage fault</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>HFSR</name> <displayName>HFSR</displayName> <description>Hard fault status register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>VECTTBL</name> <description>Vector table hard fault</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FORCED</name> <description>Forced hard fault</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DEBUG_VT</name> <description>Reserved for Debug use</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MMFAR</name> <displayName>MMFAR</displayName> <description>Memory management fault address register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MMFAR</name> <description>Memory management fault address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BFAR</name> <displayName>BFAR</displayName> <description>Bus fault address register</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BFAR</name> <description>Bus fault address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>AFSR</name> <displayName>AFSR</displayName> <description>Auxiliary fault status register</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IMPDEF</name> <description>Implementation defined</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>NVIC_STIR</name> <description>Nested vectored interrupt controller</description> <groupName>NVIC</groupName> <baseAddress>0xE000EF00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x5</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>STIR</name> <displayName>STIR</displayName> <description>Software trigger interrupt register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>INTID</name> <description>Software generated interrupt ID</description> <bitOffset>0</bitOffset> <bitWidth>9</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>FPU_CPACR</name> <description>Floating point unit CPACR</description> <groupName>FPU</groupName> <baseAddress>0xE000ED88</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x5</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CPACR</name> <displayName>CPACR</displayName> <description>Coprocessor access control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000000</resetValue> <fields> <field> <name>CP</name> <description>CP</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>SCB_ACTRL</name> <description>System control block ACTLR</description> <groupName>SCB</groupName> <baseAddress>0xE000E008</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x5</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>ACTRL</name> <displayName>ACTRL</displayName> <description>Auxiliary control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DISMCYCINT</name> <description>DISMCYCINT</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DISDEFWBUF</name> <description>DISDEFWBUF</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DISFOLD</name> <description>DISFOLD</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DISFPCA</name> <description>DISFPCA</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DISOOFP</name> <description>DISOOFP</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> </peripherals> </device>