Renesas Electronics Corporation Renesas R7FA4T1BB RA4 1.10.02 Arm Cortex-M33 based Microcontroller RA4T1 group This software is supplied by Renesas Electronics Corporation and is only intended for \n use with Renesas products. No other uses are authorized. This software is owned by \n Renesas Electronics Corporation and is protected under all applicable laws, including \n copyright laws. \n \n THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING \n THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO \n WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. \n ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. 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By using this software, you agree to \n the additional terms and conditions found by accessing the following link: \n http://www.renesas.com/disclaimer \n \n CM33 r0p4 little true true true 4 false 96 system_RA4 8 32 32 read-write 0 0xffffffff RMPU Renesas Memory Protection Unit 0x40000000 0x00 2 registers 0x04 2 registers 0x100 2 registers 0x104 2 registers 0x108 2 registers 0x10C 2 registers 0x200 136 registers MMPUOAD MMPU Operation After Detection Register 0x0000 16 read-write 0x0000 0xffff OAD Operation after detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 KEY This bit enables or disables writes to the OAD bit. 8 15 write-only MMPUOADPT MMPU Operation After Detection Protect Register 0x0004 16 read-write 0x0000 0xffff PROTECT Protection of register 0 0 read-write 0 MMPUOAD register writes are possible. #0 1 MMPUOAD register writes are protected. Read is possible. #1 KEY Key code 8 15 write-only MMPUENDMAC MMPU Enable Register for DMAC 0x0100 16 read-write 0x0000 0xffff ENABLE Bus Master MPU of DMAC enable 0 0 read-write 0 Bus Master MPU of DMAC is disabled. #0 1 Bus Master MPU of DMAC is enabled. #1 KEY These bits enable or disable writes to the ENABLE bit. 8 15 write-only MMPUENPTDMAC MMPU Enable Protect Register for DMAC 0x0104 16 read-write 0x0000 0xffff PROTECT Protection of register 0 0 read-write 0 MMPUENDMAC register writes are possible. #0 1 MMPUENDMAC register writes are protected. Read is possible. #1 KEY These bits enable or disable writes to the PROTECT bit. 8 15 write-only MMPURPTDMAC MMPU Regions Protect Register for DMAC 0x0108 16 read-write 0x0000 0xffff PROTECT Protection of register 0 0 read-write 0 Bus Master MPU register for DMAC writing is possible. #0 1 Bus Master MPU register for DMAC writing is protected. Read is possible. #1 KEY These bits enable or disable writes to the PROTECT bit. 8 15 write-only MMPURPTDMAC_SEC MMPU Regions Protect register for DMAC Secure 0x010C 16 read-write 0x0000 0xffff PROTECT Protection of register 0 0 read-write 0 Bus master MPU register for DMAC secure writes are possible. #0 1 Bus master MPU register for DMAC secure writes are protected. Read is possible. #1 KEY These bits enable or disable writes to the PROTECT bit. 8 15 write-only 8 0x010 0-7 MMPUACDMAC%s MMPU Access Control Register for DMAC 0x0200 16 read-write 0x0000 0xffff ENABLE Region enable 0 0 read-write 0 DMAC Region n unit is disabled #0 1 DMAC Region n unit is enabled #1 RP Read protection 1 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 2 read-write 0 Write permission #0 1 Write protection #1 8 0x010 0-7 MMPUSDMAC%s MMPU Start Address Register for DMAC 0x0204 32 read-write 0x00000000 0x0000001f MMPUS Region start address register 5 31 read-write 8 0x010 0-7 MMPUEDMAC%s MMPU End Address Register for DMAC 0x0208 32 read-write 0x0000001f 0x0000001f MMPUE Region end address register 5 31 read-write TZF TrustZone Filter 0x40000E00 0x00 2 registers 0x04 2 registers TZFOAD TrustZone Filter Operation After Detection Register 0x00 16 read-write 0x0000 0xffff OAD Operation after detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 KEY KeyCode 8 15 write-only TZFPT TrustZone Filter Protect Register 0x04 16 read-write 0x0000 0xffff PROTECT Protection of register 0 0 read-write 0 All Bus TrustZone Filter register writing is protected. Read is possible. #0 1 All Bus TrustZone Filter register writing is possible. #1 KEY KeyCode 8 15 write-only SRAM SRAM Control 0x40002000 0x00 1 registers 0x04 1 registers 0x08 1 registers 0x0C 1 registers 0xC0 5 registers 0xD0 1 registers 0xD4 1 registers 0xD8 1 registers PARIOAD SRAM Parity Error Operation After Detection Register 0x00 8 read-write 0x00 0xff OAD Operation After Detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 SRAMPRCR SRAM Protection Register 0x04 8 read-write 0x00 0xff SRAMPRCR Register Write Control 0 0 read-write 0 Disable writes to protected registers #0 1 Enable writes to protected registers #1 KW Write Key Code 1 7 write-only SRAMWTSC SRAM Wait State Control Register 0x08 8 read-write 0x01 0xff SRAM0WTEN SRAM0 wait enable 0 0 read-write 0 No wait #0 1 Add wait state in read access cycle to SRAM0 #1 SRAMPRCR2 SRAM Protection Register 2 0x0C 8 read-write 0x00 0xff SRAMPRCR2 Register Write Control 0 0 read-write 0 Disable writes to the protectedregisters #0 1 Enable writes to the protected registers #1 KW Write Key Code 1 7 write-only ECCMODE ECC Operating Mode Control Register 0xC0 8 read-write 0x00 0xff ECCMOD ECC Operating Mode Select 0 1 read-write 00 Disable ECC function #00 01 Setting prohibited #01 10 Enable ECC function without error checking #10 11 Enable ECC function with error checking #11 ECC2STS ECC 2-Bit Error Status Register 0xC1 8 read-write 0x00 0xff ECC2ERR ECC 2-Bit Error Status 0 0 read-write 0 No 2-bit ECC error occurred #0 1 2-bit ECC error occurred #1 ECC1STSEN ECC 1-Bit Error Information Update Enable Register 0xC2 8 read-write 0x00 0xff E1STSEN ECC 1-Bit Error Information Update Enable 0 0 read-write 0 Disable updating of 1-bit ECC error information #0 1 Enable updating of 1-bit ECC error information #1 ECC1STS ECC 1-Bit Error Status Register 0xC3 8 read-write 0x00 0xff ECC1ERR ECC 1-Bit Error Status 0 0 read-write 0 No 1-bit ECC error occurred #0 1 1-bit ECC error occurred #1 ECCPRCR ECC Protection Register 0xC4 8 read-write 0x00 0xff ECCPRCR Register Write Control 0 0 read-write 0 Disable writes to the protected registers #0 1 Enable writes to the protected registers #1 KW Write Key Code 1 7 write-only 0x78 Enable write to the ECCPRCR bit 0x78 Others Disable write to the ECCPRCR bit true ECCPRCR2 ECC Protection Register 2 0xD0 8 read-write 0x00 0xff ECCPRCR2 Register Write Control 0 0 read-write 0 Disable writes to the protected registers #0 1 Enable writes to the protected registers #1 KW2 Write Key Code 1 7 write-only 0x78 Enable write to the ECCPRCR2 bit 0x78 Others Disable write to the ECCPRCR2 bit true ECCETST ECC Test Control Register 0xD4 8 read-write 0x00 0xff TSTBYP ECC Bypass Select 0 0 read-write 0 Disable ECC bypass #0 1 Enable ECC bypass #1 ECCOAD SRAM ECC Error Operation After Detection Register 0xD8 8 read-write 0x00 0xff OAD Operation After Detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 BUS Bus Control 0x40003000 0x1100 2 registers 0x1104 2 registers 0x1110 2 registers 0x1120 2 registers 0x1130 2 registers 0x1134 2 registers 0x1800 52 registers 0x1900 52 registers 0x1A00 56 registers BUSSCNTFHBIU Slave Bus Control Register 0x1100 16 read-write 0x0000 0xffff ARBS Arbitration Select for two masters 0 1 read-write 00 DMAC/DTC > CPU #00 01 DMAC/DTC ↔ CPU #01 Others Setting prohibited true BUSSCNTFLBIU Slave Bus Control Register 0x1104 16 read-write 0x0000 0xffff ARBS Arbitration Select for two masters 0 1 read-write 00 DMAC/DTC > CPU #00 01 DMAC/DTC ↔ CPU #01 Others Setting prohibited true BUSSCNTS0BIU Slave Bus Control Register 0x1110 16 read-write 0x0000 0xffff ARBS Arbitration Select for two masters 0 1 read-write 00 DMAC/DTC > CPU #00 01 DMAC/DTC ↔ CPU #01 Others Setting prohibited true BUSSCNTPSBIU Slave Bus Control Register 0x1120 16 read-write 0x0000 0xffff ARBS Arbitration Select for two masters 0 0 read-write 0 DMAC/DTC > CPU #0 1 DMAC/DTC ↔ CPU #1 BUSSCNTPLBIU Slave Bus Control Register 0x1130 16 read-write 0x0000 0xffff ARBS Arbitration Select for two masters 0 0 read-write 0 DMAC/DTC > CPU #0 1 DMAC/DTC ↔ CPU #1 BUSSCNTPHBIU Slave Bus Control Register 0x1134 16 read-write 0x0000 0xffff ARBS Arbitration Select for two masters 0 0 read-write 0 DMAC/DTC > CPU #0 1 DMAC/DTC ↔ CPU #1 3 0x10 1-3 BUS%sERRADD BUS Error Address Register 0x1800 32 read-only 0x00000000 0xffffffff BERAD Bus Error Address 0 31 read-only 3 0x10 1-3 BUS%sERRRW BUS Error Read Write Register 0x1804 8 read-write 0x00 0xff RWSTAT Error Access Read/Write Status 0 0 read-only 0 Read access #0 1 Write access #1 3 0x10 1-3 BTZF%sERRADD BUS TZF Error Address Register 0x1900 32 read-only 0x00000000 0xffffffff BTZFERAD Bus TrustZone Filter Error Address 0 31 read-only 3 0x10 1-3 BTZF%sERRRW BUS TZF Error Read Write Register 0x1904 8 read-write 0x00 0xff TRWSTAT TrustZone filter error access Read/Write Status 0 0 read-only 0 Read access #0 1 Write access #1 3 0x10 1-3 BUS%sERRSTAT BUS Error Status Register %s 0x1A00 8 read-only 0x00 0xff SLERRSTAT Slave bus Error Status 0 0 read-only 0 No error occurred #0 1 Error occurred #1 STERRSTAT Slave TrustZone filter Error Status 1 1 read-only 0 No error occurred #0 1 Error occurred #1 MMERRSTAT Master MPU Error Status 3 3 read-only 0 No error occurred #0 1 Error occurred #1 ILERRSTAT Illegal address access Error Status 4 4 read-only 0 No error occurred #0 1 Error occurred #1 3 0x10 1-3 BUS%sERRCLR BUS Error Clear Register %s 0x1A08 8 read-write 0x00 0xff SLERRCLR Slave bus Error Clear 0 0 read-write STERRCLR Slave TrustZone filter Error Clear 1 1 read-write MMERRCLR Master MPU Error Clear 3 3 read-write ILERRCLR Illegal Address Access Error Clear 4 4 read-write DMACDTCERRSTAT DMAC/DTC Error Status Register 0x1A24 8 read-only 0x00 0xff MTERRSTAT Master TrustZone Filter Error Status 0 0 read-only 0 No error occurred #0 1 Error occurred #1 DMACDTCERRCLR DMAC/DTC Error Clear Register 0x1A2C 8 read-write 0x00 0xff MTERRCLR Master TrustZone filter Error Clear 0 0 read-write DMAC0 Direct memory access controller 0 0x40005000 0x00 18 registers 0x13 3 registers 0x18 7 registers 0x20 16 registers DMSAR DMA Source Address Register 0x00 32 read-write 0x00000000 0xffffffff DMDAR DMA Destination Address Register 0x04 32 read-write 0x00000000 0xffffffff DMCRA DMA Transfer Count Register 0x08 32 read-write 0x00000000 0xffffffff DMCRAL Lower bits of transfer count 0 15 read-write DMCRAH Upper bits of transfer count 16 25 read-write DMCRB DMA Block Transfer Count Register 0x0C 32 read-write 0x00000000 0xffffffff DMCRBL Functions as a number of block, repeat or repeat-block transfer counter. 0 15 read-write DMCRBH Specifies the number of block, repeat or repeat-block transfer operations. 16 31 read-write DMTMD DMA Transfer Mode Register 0x10 16 read-write 0x0000 0xffff DCTG Transfer Request Source Select 0 1 read-write 00 Software request #00 01 Hardware request #01 10 Setting prohibited #10 11 Setting prohibited #11 SZ Transfer Data Size Select 8 9 read-write 00 8 bits #00 01 16 bits #01 10 32 bits #10 11 Setting prohibited #11 TKP Transfer Keeping 10 10 read-write 0 Transfer is stopped by completion of specified total number of transfer operations. #0 1 Transfer is not stopped by completion of specified total number of transfer operations (free-running). #1 DTS Repeat Area Select 12 13 read-write 00 The destination is specified as the repeat area or block area. #00 01 The source is specified as the repeat area or block area. #01 10 The repeat area or block area is not specified. #10 11 Setting prohibited. #11 MD Transfer Mode Select 14 15 read-write 00 Normal transfer #00 01 Repeat transfer #01 10 Block transfer #10 11 Repeat-block transfer #11 DMINT DMA Interrupt Setting Register 0x13 8 read-write 0x00 0xff DARIE Destination Address Extended Repeat Area Overflow Interrupt Enable 0 0 read-write 0 Disables an interrupt request for an extended repeat area overflow on the destination address. #0 1 Enables an interrupt request for an extended repeat area overflow on the destination address. #1 SARIE Source Address Extended Repeat Area Overflow Interrupt Enable 1 1 read-write 0 Disables an interrupt request for an extended repeat area overflow on the source address. #0 1 Enables an interrupt request for an extended repeat area overflow on the source address. #1 RPTIE Repeat Size End Interrupt Enable 2 2 read-write 0 Disables the repeat size end interrupt request. #0 1 Enables the repeat size end interrupt request. #1 ESIE Transfer Escape End Interrupt Enable 3 3 read-write 0 Disables the transfer escape end interrupt request. #0 1 Enables the transfer escape end interrupt request. #1 DTIE Transfer End Interrupt Enable 4 4 read-write 0 Disables the transfer end interrupt request. #0 1 Enables the transfer end interrupt request. #1 DMAMD DMA Address Mode Register 0x14 16 read-write 0x0000 0xffff DARA Destination Address Extended Repeat Area 0 4 read-write DADR Destination Address Update Select After Reload 5 5 read-write 0 Only reloading. #0 1 Add index after reloading. #1 DM Destination Address Update Mode 6 7 read-write 00 Destination address is fixed. #00 01 Offset addition. #01 10 Destination address is incremented. #10 11 Destination address is decremented. #11 SARA Source Address Extended Repeat Area 8 12 read-write SADR Source Address Update Select After Reload 13 13 read-write 0 Only reloading. #0 1 Add index after reloading. #1 SM Source Address Update Mode 14 15 read-write 00 Source address is fixed. #00 01 Offset addition. #01 10 Source address is incremented. #10 11 Source address is decremented. #11 DMOFR DMA Offset Register 0x18 32 read-write 0x00000000 0xffffffff DMCNT DMA Transfer Enable Register 0x1C 8 read-write 0x00 0xff DTE DMA Transfer Enable 0 0 read-write 0 Disables DMA transfer. #0 1 Enables DMA transfer. #1 DMREQ DMA Software Start Register 0x1D 8 read-write 0x00 0xff SWREQ DMA Software Start 0 0 read-write 0 DMA transfer is not requested. #0 1 DMA transfer is requested. #1 CLRS DMA Software Start Bit Auto Clear Select 4 4 read-write 0 SWREQ bit is cleared after DMA transfer is started by software. #0 1 SWREQ bit is not cleared after DMA transfer is started by software. #1 DMSTS DMA Status Register 0x1E 8 read-write 0x00 0xff ESIF Transfer Escape End Interrupt Flag 0 0 read-write 0 A transfer escape end interrupt has not been generated. #0 1 A transfer escape end interrupt has been generated. #1 DTIF Transfer End Interrupt Flag 4 4 read-write 0 A transfer end interrupt has not been generated. #0 1 A transfer end interrupt has been generated. #1 ACT DMAC Active Flag 7 7 read-only 0 DMAC is in the idle state. #0 1 DMAC is operating. #1 DMSRR DMA Source Reload Address Register 0x20 32 read-write 0x00000000 0xffffffff DMDRR DMA Destination Reload Address Register 0x24 32 read-write 0x00000000 0xffffffff DMSBS DMA Source Buffer Size Register 0x28 32 read-write 0x00000000 0xffffffff DMSBSL Functions as data transfer counter in repeat-block transfer mode 0 15 read-write DMSBSH Specifies the repeat-area size in repeat-block transfer mode 16 31 read-write DMDBS DMA Destination Buffer Size Register 0x2C 32 read-write 0x00000000 0xffffffff DMDBSL Functions as data transfer counter in repeat-block transfer mode. 0 15 read-write DMDBSH Specifies the repeat-area size in repeat-block transfer mode. 16 31 read-write DMAC1 Direct memory access controller 1 0x40005040 DMAC2 Direct memory access controller 2 0x40005080 DMAC3 Direct memory access controller 3 0x400050C0 DMAC4 Direct memory access controller 4 0x40005100 DMAC5 Direct memory access controller 5 0x40005140 DMAC6 Direct memory access controller 6 0x40005180 DMAC7 Direct memory access controller 7 0x400051C0 DMA DMAC Module Activation 0x40005200 0x00 1 registers 0x40 4 registers DMAST DMA Module Activation Register 0x00 8 read-write 0x00 0xff DMST DMAC Operation Enable 0 0 read-write 0 DMAC activation is disabled. #0 1 DMAC activation is enabled. #1 DMECHR DMAC Error Channel Register 0x40 32 read-write 0x00000000 0xffffffff DMECH DMAC Error channel 0 2 read-only DMECHSAM DMAC Error channel Security Attribution Monitor 8 8 read-only 0 secure channel #0 1 non-secure channel #1 DMESTA DMAC Error Status 16 16 read-write 0 No DMA transfer error occurred #0 1 DMA transfer error occurred #1 DTC Data Transfer Controller 0x40005400 0x00 1 registers 0x04 4 registers 0x0C 1 registers 0x0E 3 registers 0x14 4 registers 0x20 4 registers DTCCR DTC Control Register 0x00 8 read-write 0x08 0xff RRS DTC Transfer Information Read Skip Enable 4 4 read-write 0 Transfer information read is not skipped #0 1 Transfer information read is skipped when vector numbers match #1 DTCVBR DTC Vector Base Register 0x04 32 read-write 0x00000000 0xffffffff DTCST DTC Module Start Register 0x0C 8 read-write 0x00 0xff DTCST DTC Module Start 0 0 read-write 0 DTC module stopped. #0 1 DTC module started. #1 DTCSTS DTC Status Register 0x0E 16 read-only 0x0000 0xffff VECN DTC-Activating Vector Number Monitoring 0 7 read-only ACT DTC Active Flag 15 15 read-only 0 DTC transfer operation is not in progress. #0 1 DTC transfer operation is in progress. #1 DTCCR_SEC DTC Control Register for secure Region 0x10 8 read-write 0x08 0xff RRS DTC Transfer Information Read Skip Enable for Secure 4 4 read-write 0 Transfer information read is not skipped. #0 1 Transfer information read is skipped when vector numbers match. #1 DTCVBR_SEC DTC Vector Base Register for secure Region 0x14 32 read-write 0x00000000 0xffffffff DTEVR DTC Error Vector Register 0x20 32 read-write 0x00000000 0xffffffff DTEV DTC Error Vector Number 0 7 read-only DTEVSAM DTC Error Vector Number SA Monitor 8 8 read-only 0 Secure vector number #0 1 Non-Secure vector number #1 DTESTA DTC Error Status Flag 16 16 read-write 0 No DTC transfer error occurred #0 1 DTC transfer error occurred #1 ICU Interrupt Controller 0x40006000 0x00 15 registers 0x100 1 registers 0x120 2 registers 0x130 2 registers 0x140 2 registers 0x1A0 8 registers 0x200 2 registers 0x280 32 registers 0x300 384 registers IEL0 ICU Interrupt 0 0 IEL1 ICU Interrupt 1 1 IEL2 ICU Interrupt 2 2 IEL3 ICU Interrupt 3 3 IEL4 ICU Interrupt 4 4 IEL5 ICU Interrupt 5 5 IEL6 ICU Interrupt 6 6 IEL7 ICU Interrupt 7 7 IEL8 ICU Interrupt 8 8 IEL9 ICU Interrupt 9 9 IEL10 ICU Interrupt 10 10 IEL11 ICU Interrupt 11 11 IEL12 ICU Interrupt 12 12 IEL13 ICU Interrupt 13 13 IEL14 ICU Interrupt 14 14 IEL15 ICU Interrupt 15 15 IEL16 ICU Interrupt 16 16 IEL17 ICU Interrupt 17 17 IEL18 ICU Interrupt 18 18 IEL19 ICU Interrupt 19 19 IEL20 ICU Interrupt 20 20 IEL21 ICU Interrupt 21 21 IEL22 ICU Interrupt 22 22 IEL23 ICU Interrupt 23 23 IEL24 ICU Interrupt 24 24 IEL25 ICU Interrupt 25 25 IEL26 ICU Interrupt 26 26 IEL27 ICU Interrupt 27 27 IEL28 ICU Interrupt 28 28 IEL29 ICU Interrupt 29 29 IEL30 ICU Interrupt 30 30 IEL31 ICU Interrupt 31 31 IEL32 ICU Interrupt 32 32 IEL33 ICU Interrupt 33 33 IEL34 ICU Interrupt 34 34 IEL35 ICU Interrupt 35 35 IEL36 ICU Interrupt 36 36 IEL37 ICU Interrupt 37 37 IEL38 ICU Interrupt 38 38 IEL39 ICU Interrupt 39 39 IEL40 ICU Interrupt 40 40 IEL41 ICU Interrupt 41 41 IEL42 ICU Interrupt 42 42 IEL43 ICU Interrupt 43 43 IEL44 ICU Interrupt 44 44 IEL45 ICU Interrupt 45 45 IEL46 ICU Interrupt 46 46 IEL47 ICU Interrupt 47 47 IEL48 ICU Interrupt 48 48 IEL49 ICU Interrupt 49 49 IEL50 ICU Interrupt 50 50 IEL51 ICU Interrupt 51 51 IEL52 ICU Interrupt 52 52 IEL53 ICU Interrupt 53 53 IEL54 ICU Interrupt 54 54 IEL55 ICU Interrupt 55 55 IEL56 ICU Interrupt 56 56 IEL57 ICU Interrupt 57 57 IEL58 ICU Interrupt 58 58 IEL59 ICU Interrupt 59 59 IEL60 ICU Interrupt 60 60 IEL61 ICU Interrupt 61 61 IEL62 ICU Interrupt 62 62 IEL63 ICU Interrupt 63 63 IEL64 ICU Interrupt 64 64 IEL65 ICU Interrupt 65 65 IEL66 ICU Interrupt 66 66 IEL67 ICU Interrupt 67 67 IEL68 ICU Interrupt 68 68 IEL69 ICU Interrupt 69 69 IEL70 ICU Interrupt 70 70 IEL71 ICU Interrupt 71 71 IEL72 ICU Interrupt 72 72 IEL73 ICU Interrupt 73 73 IEL74 ICU Interrupt 74 74 IEL75 ICU Interrupt 75 75 IEL76 ICU Interrupt 76 76 IEL77 ICU Interrupt 77 77 IEL78 ICU Interrupt 78 78 IEL79 ICU Interrupt 79 79 IEL80 ICU Interrupt 80 80 IEL81 ICU Interrupt 81 81 IEL82 ICU Interrupt 82 82 IEL83 ICU Interrupt 83 83 IEL84 ICU Interrupt 84 84 IEL85 ICU Interrupt 85 85 IEL86 ICU Interrupt 86 86 IEL87 ICU Interrupt 87 87 IEL88 ICU Interrupt 88 88 IEL89 ICU Interrupt 89 89 IEL90 ICU Interrupt 90 90 IEL91 ICU Interrupt 91 91 IEL92 ICU Interrupt 92 92 IEL93 ICU Interrupt 93 93 IEL94 ICU Interrupt 94 94 IEL95 ICU Interrupt 95 95 15 0x1 0-14 IRQCR%s IRQ Control Register %s 0x000 8 read-write 0x00 0xff IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 5 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQi Digital Filter Enable 7 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 NMICR NMI Pin Interrupt Control Register 0x100 8 read-write 0x00 0xff NMIMD NMI Detection Set 0 0 read-write 0 Falling edge #0 1 Rising edge #1 NFCLKSEL NMI Digital Filter Sampling Clock Select 4 5 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 NFLTEN NMI Digital Filter Enable 7 7 read-write 0 Disabled. #0 1 Enabled. #1 NMIER Non-Maskable Interrupt Enable Register 0x120 16 read-write 0x0000 0xffff IWDTEN IWDT Underflow/Refresh Error Interrupt Enable 0 0 read-write 0 Disabled #0 1 Enabled. #1 WDTEN WDT Underflow/Refresh Error Interrupt Enable 1 1 read-write 0 Disabled #0 1 Enabled #1 LVD1EN Voltage monitor 1 Interrupt Enable 2 2 read-write 0 Disabled #0 1 Enabled #1 LVD2EN Voltage monitor 2 Interrupt Enable 3 3 read-write 0 Disabled #0 1 Enabled #1 OSTEN Main Clock Oscillation Stop Detection Interrupt Enable 6 6 read-write 0 Disabled #0 1 Enabled #1 NMIEN NMI Pin Interrupt Enable 7 7 read-write 0 Disabled #0 1 Enabled #1 RPEEN SRAM Parity Error Interrupt Enable 8 8 read-write 0 Disabled #0 1 Enabled #1 RECCEN SRAM ECC Error Interrupt Enable 9 9 read-write 0 Disabled #0 1 Enabled #1 BUSMEN Bus Master MPU Error Interrupt Enable 11 11 read-write 0 Disabled #0 1 Enabled #1 TZFEN 13 13 read-write 0 Disabled #0 1 Enabled #1 CPEEN 15 15 read-write 0 Disabled #0 1 Enabled #1 NMICLR Non-Maskable Interrupt Status Clear Register 0x130 16 read-write 0x0000 0xffff IWDTCLR IWDT Underflow/Refresh Error Interrupt Status Flag Clear 0 0 read-write 0 No effect #0 1 Clear the NMISR.IWDTST flag #1 WDTCLR WDT Underflow/Refresh Error Interrupt Status Flag Clear 1 1 read-write 0 No effect #0 1 Clear the NMISR.WDTST flag #1 LVD1CLR Voltage Monitor 1 Interrupt Status Flag Clear 2 2 read-write 0 No effect #0 1 Clear the NMISR.LVD1ST flag #1 LVD2CLR Voltage Monitor 2 Interrupt Status Flag Clear 3 3 read-write 0 No effect #0 1 Clear the NMISR.LVD2ST flag. #1 OSTCLR Oscillation Stop Detection Interrupt Status Flag Clear 6 6 read-write 0 No effect #0 1 Clear the NMISR.OSTST flag #1 NMICLR NMI Pin Interrupt Status Flag Clear 7 7 read-write 0 No effect #0 1 Clear the NMISR.NMIST flag #1 RPECLR SRAM Parity Error Interrupt Status Flag Clear 8 8 read-write 0 No effect #0 1 Clear the NMISR.RPEST flag #1 RECCCLR SRAM ECC Error Interrupt Status Flag Clear 9 9 read-write 0 No effect #0 1 Clear the NMISR.RECCST flag #1 BUSMCLR Bus Master MPU Error Interrupt Status Flag Clear 11 11 read-write 0 No effect #0 1 Clear the NMISR.BUSMST flag #1 TZFCLR 13 13 read-write 0 No effect #0 1 Clear the NMISR.TZFCLR flag #1 CPECLR 15 15 read-write 0 No effect #0 1 Clear the NMISR.CPECLR flag #1 NMISR Non-Maskable Interrupt Status Register 0x140 16 read-only 0x0000 0xffff IWDTST IWDT Underflow/Refresh Error Interrupt Status Flag 0 0 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 WDTST WDT Underflow/Refresh Error Interrupt Status Flag 1 1 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 LVD1ST Voltage Monitor 1 Interrupt Status Flag 2 2 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 LVD2ST Voltage Monitor 2 Interrupt Status Flag 3 3 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 OSTST Main Clock Oscillation Stop Detection Interrupt Status Flag 6 6 read-only 0 Interrupt not requested for main clock oscillation stop #0 1 Interrupt requested for main clock oscillation stop #1 NMIST NMI Pin Interrupt Status Flag 7 7 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 RPEST SRAM Parity Error Interrupt Status Flag 8 8 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 RECCST SRAM ECC Error Interrupt Status Flag 9 9 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 BUSMST Bus Master MPU Error Interrupt Status Flag 11 11 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 TZFST 13 13 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 CPEST 15 15 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 WUPEN0 Wake Up Interrupt Enable Register 0 0x1A0 32 read-write 0x00000000 0xffffffff IRQWUPEN IRQn Interrupt Software Standby/Snooze Mode Returns Enable bit (n = 0 to 15) 0 14 read-write 0 Software Standby/Snooze Mode returns by IRQn interrupt is disabled #0 1 Software Standby/Snooze Mode returns by IRQn interrupt is enabled #1 IWDTWUPEN IWDT Interrupt Software Standby/Snooze Mode Returns Enable bit 16 16 read-write 0 Software Standby/Snooze Mode returns by IWDT interrupt is disabled #0 1 Software Standby/Snooze Mode returns by IWDT interrupt is enabled #1 LVD1WUPEN LVD1 Interrupt Software Standby/Snooze Mode Returns Enable bit 18 18 read-write 0 Software Standby/Snooze Mode returns by LVD1 interrupt is disabled #0 1 Software Standby/Snooze Mode returns by LVD1 interrupt is enabled #1 LVD2WUPEN LVD2 Interrupt Software Standby/Snooze Mode Returns Enable bit 19 19 read-write 0 Software Standby/Snooze Mode returns by LVD2 interrupt is disabled #0 1 Software Standby/Snooze Mode returns by LVD2 interrupt is enabled #1 AGT1UDWUPEN AGT1 Underflow Interrupt Software Standby/Snooze Mode Returns Enable bit 28 28 read-write 0 Software Standby/Snooze Mode returns by AGT1 underflow interrupt is disabled #0 1 Software Standby/Snooze Mode returns by AGT1 underflow interrupt is enabled #1 AGT1CAWUPEN AGT1 Compare Match A Interrupt Software Standby/Snooze Mode Returns Enable bit 29 29 read-write 0 Software Standby/Snooze Mode returns by AGT1 compare match A interrupt is disabled #0 1 Software Standby/Snooze Mode returns by AGT1 compare match A interrupt is enabled #1 AGT1CBWUPEN AGT1 Compare Match B Interrupt Software Standby/Snooze Mode Returns Enable bit 30 30 read-write 0 Software Standby/Snooze Mode returns by AGT1 compare match B interrupt is disabled #0 1 Software Standby/Snooze Mode returns by AGT1 compare match B interrupt is enabled #1 WUPEN1 Wake Up Interrupt Enable Register 1 0x1A4 32 read-write 0x00000000 0xffffffff I3CWUPEN I3C Address Match Interrupt Software Standby/Snooze Mode Returns Enable bit 11 11 read-write 0 Software Standby/Snooze Mode returns by I3C address match interrupt is disabled #0 1 Software Standby/Snooze Mode returns by I3C address match interrupt is enabled #1 SELSR0 SYS Event Link Setting Register 0x200 16 read-write 0x0000 0xffff 8 0x4 0-7 DELSR%s DMAC Event Link Setting Register %s 0x280 32 read-write 0x00000000 0xffffffff DELS DMAC Event Link Select 0 8 read-write 0x00 Disable interrupts to the associated DMAC module. 0x00 Others Event signal number to be linked. For details, see . true IR DMAC Activation Request Status Flag 16 16 read-write 0 No DMAC activation request occurred. #0 1 DMAC activation request occurred. #1 96 0x4 0-95 IELSR%s ICU Event Link Setting Register %s 0x300 32 read-write 0x00000000 0xffffffff CACHE CACHE 0x40007000 0x00 12 registers 0x40 12 registers 0x200 8 registers CCACTL C-Cache Control Register 0x000 32 read-write 0x00000000 0xffffffff ENC C-Cache Enable 0 0 read-write 0 Disable C-cache #0 1 Enable C-cache #1 CCAFCT C-Cache Flush Control Register 0x004 32 read-write 0x00000000 0xffffffff FC C-Cache Flush 0 0 read-write 0 No action #0 1 C-cache line flush (all lines invalidated) #1 CCALCF C-Cache Line Configuration Register 0x008 32 read-write 0x00000001 0xffffffff CC C-Cache Line Size 0 1 read-write 00 Prohibited #00 01 Cache line size 32 bytes #01 10 Cache line size 64 bytes #10 11 Prohibited #11 SCACTL S-Cache Control Register 0x040 32 read-write 0x00000000 0xffffffff ENS S-Cache Enable 0 0 read-write 0 Disable S-cache #0 1 Enable S-cache #1 SCAFCT S-Cache Flush Control Register 0x044 32 read-write 0x00000000 0xffffffff FS S-Cache Flush 0 0 read-write 0 No action #0 1 S-cache line flush (all lines invalidated) #1 SCALCF S-Cache Line Configuration Register 0x048 32 read-write 0x00000001 0xffffffff CS S-Cache Line Size 0 1 read-write 00 Prohibited #00 01 Cache line size 32 bytes #01 10 Cache line size 64 bytes #10 11 Prohibited #11 CAPOAD Cache Parity Error Operation After Detection Register 0x200 32 read-write 0x00000000 0xffffffff OAD Operation after Detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 CAPRCR Cache Protection Register 0x204 32 read-write 0x00000000 0xffffffff PRCR Register Write Control 0 0 read-write 0 Disable writes to protected registers #0 1 Enable writes to protected registers #1 KW Write key code 1 7 read-write CPSCU CPU System Security Control Unit 0x40008000 0x00 4 registers 0x10 4 registers 0x30 8 registers 0x40 16 registers 0x54 4 registers 0x70 12 registers 0x100 8 registers 0x130 8 registers 0x180 4 registers 0x1B0 4 registers CSAR Cache Security Attribution Register 0x000 32 read-write 0xffffffff 0xffffffff CACHESA Security Attributes of Registers for Cache Control 0 0 read-write 0 Secure #0 1 Non-secure #1 CACHELSA Security Attributes of Registers for Cache Line Configuration 1 1 read-write 0 Secure #0 1 Non-secure #1 CACHEESA Security Attributes of Registers for Cache Error 2 2 read-write 0 Secure #0 1 Non-secure #1 SRAMSAR SRAM Security Attribution Register 0x10 32 read-write 0xffffffff 0xffffffff SRAMSA0 Security attributes of registers for SRAM Protection 0 0 read-write 0 Secure #0 1 Non-Secure #1 SRAMSA1 Security attributes of registers for SRAM Protection 2 1 1 read-write 0 Secure #0 1 Non-Secure #1 SRAMSA2 Security attributes of registers for ECC Relation 2 2 read-write 0 Secure #0 1 Non-Secure #1 DTCSAR DTC Controller Security Attribution Register 0x30 32 read-write 0xffffffff 0xffffffff DTCSTSA DTC Security Attribution 0 0 read-write 0 Secure. #0 1 Non-Secure. #1 DMACSAR DMAC Controller Security Attribution Register 0x34 32 read-write 0xffffffff 0xffffffff DMASTSA DMAST Security Attribution 0 0 read-write 0 Secure #0 1 Non-secure #1 ICUSARA Interrupt Controller Unit Security Attribution Register A 0x40 32 read-write 0xffffffff 0xffffffff SAIRQCR00 Security attributes of registers for the IRQCRn register 0 0 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR01 Security attributes of registers for the IRQCRn register 1 1 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR02 Security attributes of registers for the IRQCRn register 2 2 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR03 Security attributes of registers for the IRQCRn register 3 3 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR04 Security attributes of registers for the IRQCRn register 4 4 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR05 Security attributes of registers for the IRQCRn register 5 5 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR06 Security attributes of registers for the IRQCRn register 6 6 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR07 Security attributes of registers for the IRQCRn register 7 7 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR08 Security attributes of registers for the IRQCRn register 8 8 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR09 Security attributes of registers for the IRQCRn register 9 9 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR10 Security attributes of registers for the IRQCRn register 10 10 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR11 Security attributes of registers for the IRQCRn register 11 11 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR12 Security attributes of registers for the IRQCRn register 12 12 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR13 Security attributes of registers for the IRQCRn register 13 13 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR14 Security attributes of registers for the IRQCRn register 14 14 read-write 0 Secure #0 1 Non-secure #1 ICUSARB Interrupt Controller Unit Security Attribution Register B 0x44 32 read-write 0xffffffff 0xffffffff SANMI Security attributes of registers for nonmaskable interrupt 0 0 read-write 0 Secure #0 1 Non-secure #1 ICUSARC Interrupt Controller Unit Security Attribution Register C 0x48 32 read-write 0xffffffff 0xffffffff SADMAC0 Security attributes of registers for DMAC channel 0 0 read-write 0 Secure #0 1 Non-secure #1 SADMAC1 Security attributes of registers for DMAC channel 1 1 read-write 0 Secure #0 1 Non-secure #1 SADMAC2 Security attributes of registers for DMAC channel 2 2 read-write 0 Secure #0 1 Non-secure #1 SADMAC3 Security attributes of registers for DMAC channel 3 3 read-write 0 Secure #0 1 Non-secure #1 SADMAC4 Security attributes of registers for DMAC channel 4 4 read-write 0 Secure #0 1 Non-secure #1 SADMAC5 Security attributes of registers for DMAC channel 5 5 read-write 0 Secure #0 1 Non-secure #1 SADMAC6 Security attributes of registers for DMAC channel 6 6 read-write 0 Secure #0 1 Non-secure #1 SADMAC7 Security attributes of registers for DMAC channel 7 7 read-write 0 Secure #0 1 Non-secure #1 ICUSARD Interrupt Controller Unit Security Attribution Register D 0x4C 32 read-write 0xffffffff 0xffffffff SASELSR0 Security attributes of registers for SELSR0 0 0 read-write 0 Secure #0 1 Non-secure #1 ICUSARF Interrupt Controller Unit Security Attribution Register F 0x54 32 read-write 0xffffffff 0xffffffff SAI3CWUP Security attributes of registers for WUPEN1.b11 11 11 read-write 0 Secure #0 1 Non-secure #1 ICUSARG Interrupt Controller Unit Security Attribution Register G 0x70 32 read-write 0xffffffff 0xffffffff SAIELSR00 Security attributes of registers for IELSR31 to IELSR0 0 0 read-write 0 Secure #0 1 Non-secure #1 SAIELSR01 Security attributes of registers for IELSR31 to IELSR0 1 1 read-write 0 Secure #0 1 Non-secure #1 SAIELSR02 Security attributes of registers for IELSR31 to IELSR0 2 2 read-write 0 Secure #0 1 Non-secure #1 SAIELSR03 Security attributes of registers for IELSR31 to IELSR0 3 3 read-write 0 Secure #0 1 Non-secure #1 SAIELSR04 Security attributes of registers for IELSR31 to IELSR0 4 4 read-write 0 Secure #0 1 Non-secure #1 SAIELSR05 Security attributes of registers for IELSR31 to IELSR0 5 5 read-write 0 Secure #0 1 Non-secure #1 SAIELSR06 Security attributes of registers for IELSR31 to IELSR0 6 6 read-write 0 Secure #0 1 Non-secure #1 SAIELSR07 Security attributes of registers for IELSR31 to IELSR0 7 7 read-write 0 Secure #0 1 Non-secure #1 SAIELSR08 Security attributes of registers for IELSR31 to IELSR0 8 8 read-write 0 Secure #0 1 Non-secure #1 SAIELSR09 Security attributes of registers for IELSR31 to IELSR0 9 9 read-write 0 Secure #0 1 Non-secure #1 SAIELSR10 Security attributes of registers for IELSR31 to IELSR0 10 10 read-write 0 Secure #0 1 Non-secure #1 SAIELSR11 Security attributes of registers for IELSR31 to IELSR0 11 11 read-write 0 Secure #0 1 Non-secure #1 SAIELSR12 Security attributes of registers for IELSR31 to IELSR0 12 12 read-write 0 Secure #0 1 Non-secure #1 SAIELSR13 Security attributes of registers for IELSR31 to IELSR0 13 13 read-write 0 Secure #0 1 Non-secure #1 SAIELSR14 Security attributes of registers for IELSR31 to IELSR0 14 14 read-write 0 Secure #0 1 Non-secure #1 SAIELSR15 Security attributes of registers for IELSR31 to IELSR0 15 15 read-write 0 Secure #0 1 Non-secure #1 SAIELSR16 Security attributes of registers for IELSR31 to IELSR0 16 16 read-write 0 Secure #0 1 Non-secure #1 SAIELSR17 Security attributes of registers for IELSR31 to IELSR0 17 17 read-write 0 Secure #0 1 Non-secure #1 SAIELSR18 Security attributes of registers for IELSR31 to IELSR0 18 18 read-write 0 Secure #0 1 Non-secure #1 SAIELSR19 Security attributes of registers for IELSR31 to IELSR0 19 19 read-write 0 Secure #0 1 Non-secure #1 SAIELSR20 Security attributes of registers for IELSR31 to IELSR0 20 20 read-write 0 Secure #0 1 Non-secure #1 SAIELSR21 Security attributes of registers for IELSR31 to IELSR0 21 21 read-write 0 Secure #0 1 Non-secure #1 SAIELSR22 Security attributes of registers for IELSR31 to IELSR0 22 22 read-write 0 Secure #0 1 Non-secure #1 SAIELSR23 Security attributes of registers for IELSR31 to IELSR0 23 23 read-write 0 Secure #0 1 Non-secure #1 SAIELSR24 Security attributes of registers for IELSR31 to IELSR0 24 24 read-write 0 Secure #0 1 Non-secure #1 SAIELSR25 Security attributes of registers for IELSR31 to IELSR0 25 25 read-write 0 Secure #0 1 Non-secure #1 SAIELSR26 Security attributes of registers for IELSR31 to IELSR0 26 26 read-write 0 Secure #0 1 Non-secure #1 SAIELSR27 Security attributes of registers for IELSR31 to IELSR0 27 27 read-write 0 Secure #0 1 Non-secure #1 SAIELSR28 Security attributes of registers for IELSR31 to IELSR0 28 28 read-write 0 Secure #0 1 Non-secure #1 SAIELSR29 Security attributes of registers for IELSR31 to IELSR0 29 29 read-write 0 Secure #0 1 Non-secure #1 SAIELSR30 Security attributes of registers for IELSR31 to IELSR0 30 30 read-write 0 Secure #0 1 Non-secure #1 SAIELSR31 Security attributes of registers for IELSR31 to IELSR0 31 31 read-write 0 Secure #0 1 Non-secure #1 ICUSARH Interrupt Controller Unit Security Attribution Register H 0x74 32 read-write 0xffffffff 0xffffffff SAIELSR32 Security attributes of registers for IELSR63 to IELSR32 0 0 read-write 0 Secure #0 1 Non-secure #1 SAIELSR33 Security attributes of registers for IELSR63 to IELSR32 1 1 read-write 0 Secure #0 1 Non-secure #1 SAIELSR34 Security attributes of registers for IELSR63 to IELSR32 2 2 read-write 0 Secure #0 1 Non-secure #1 SAIELSR35 Security attributes of registers for IELSR63 to IELSR32 3 3 read-write 0 Secure #0 1 Non-secure #1 SAIELSR36 Security attributes of registers for IELSR63 to IELSR32 4 4 read-write 0 Secure #0 1 Non-secure #1 SAIELSR37 Security attributes of registers for IELSR63 to IELSR32 5 5 read-write 0 Secure #0 1 Non-secure #1 SAIELSR38 Security attributes of registers for IELSR63 to IELSR32 6 6 read-write 0 Secure #0 1 Non-secure #1 SAIELSR39 Security attributes of registers for IELSR63 to IELSR32 7 7 read-write 0 Secure #0 1 Non-secure #1 SAIELSR40 Security attributes of registers for IELSR63 to IELSR32 8 8 read-write 0 Secure #0 1 Non-secure #1 SAIELSR41 Security attributes of registers for IELSR63 to IELSR32 9 9 read-write 0 Secure #0 1 Non-secure #1 SAIELSR42 Security attributes of registers for IELSR63 to IELSR32 10 10 read-write 0 Secure #0 1 Non-secure #1 SAIELSR43 Security attributes of registers for IELSR63 to IELSR32 11 11 read-write 0 Secure #0 1 Non-secure #1 SAIELSR44 Security attributes of registers for IELSR63 to IELSR32 12 12 read-write 0 Secure #0 1 Non-secure #1 SAIELSR45 Security attributes of registers for IELSR63 to IELSR32 13 13 read-write 0 Secure #0 1 Non-secure #1 SAIELSR46 Security attributes of registers for IELSR63 to IELSR32 14 14 read-write 0 Secure #0 1 Non-secure #1 SAIELSR47 Security attributes of registers for IELSR63 to IELSR32 15 15 read-write 0 Secure #0 1 Non-secure #1 SAIELSR48 Security attributes of registers for IELSR63 to IELSR32 16 16 read-write 0 Secure #0 1 Non-secure #1 SAIELSR49 Security attributes of registers for IELSR63 to IELSR32 17 17 read-write 0 Secure #0 1 Non-secure #1 SAIELSR50 Security attributes of registers for IELSR63 to IELSR32 18 18 read-write 0 Secure #0 1 Non-secure #1 SAIELSR51 Security attributes of registers for IELSR63 to IELSR32 19 19 read-write 0 Secure #0 1 Non-secure #1 SAIELSR52 Security attributes of registers for IELSR63 to IELSR32 20 20 read-write 0 Secure #0 1 Non-secure #1 SAIELSR53 Security attributes of registers for IELSR63 to IELSR32 21 21 read-write 0 Secure #0 1 Non-secure #1 SAIELSR54 Security attributes of registers for IELSR63 to IELSR32 22 22 read-write 0 Secure #0 1 Non-secure #1 SAIELSR55 Security attributes of registers for IELSR63 to IELSR32 23 23 read-write 0 Secure #0 1 Non-secure #1 SAIELSR56 Security attributes of registers for IELSR63 to IELSR32 24 24 read-write 0 Secure #0 1 Non-secure #1 SAIELSR57 Security attributes of registers for IELSR63 to IELSR32 25 25 read-write 0 Secure #0 1 Non-secure #1 SAIELSR58 Security attributes of registers for IELSR63 to IELSR32 26 26 read-write 0 Secure #0 1 Non-secure #1 SAIELSR59 Security attributes of registers for IELSR63 to IELSR32 27 27 read-write 0 Secure #0 1 Non-secure #1 SAIELSR60 Security attributes of registers for IELSR63 to IELSR32 28 28 read-write 0 Secure #0 1 Non-secure #1 SAIELSR61 Security attributes of registers for IELSR63 to IELSR32 29 29 read-write 0 Secure #0 1 Non-secure #1 SAIELSR62 Security attributes of registers for IELSR63 to IELSR32 30 30 read-write 0 Secure #0 1 Non-secure #1 SAIELSR63 Security attributes of registers for IELSR63 to IELSR32 31 31 read-write 0 Secure #0 1 Non-secure #1 ICUSARI Interrupt Controller Unit Security Attribution Register I 0x78 32 read-write 0xffffffff 0xffffffff SAIELSR64 Security attributes of registers for IELSR95 to IELSR64 0 0 read-write 0 Secure #0 1 Non-secure #1 SAIELSR65 Security attributes of registers for IELSR95 to IELSR64 1 1 read-write 0 Secure #0 1 Non-secure #1 SAIELSR66 Security attributes of registers for IELSR95 to IELSR64 2 2 read-write 0 Secure #0 1 Non-secure #1 SAIELSR67 Security attributes of registers for IELSR95 to IELSR64 3 3 read-write 0 Secure #0 1 Non-secure #1 SAIELSR68 Security attributes of registers for IELSR95 to IELSR64 4 4 read-write 0 Secure #0 1 Non-secure #1 SAIELSR69 Security attributes of registers for IELSR95 to IELSR64 5 5 read-write 0 Secure #0 1 Non-secure #1 SAIELSR70 Security attributes of registers for IELSR95 to IELSR64 6 6 read-write 0 Secure #0 1 Non-secure #1 SAIELSR71 Security attributes of registers for IELSR95 to IELSR64 7 7 read-write 0 Secure #0 1 Non-secure #1 SAIELSR72 Security attributes of registers for IELSR95 to IELSR64 8 8 read-write 0 Secure #0 1 Non-secure #1 SAIELSR73 Security attributes of registers for IELSR95 to IELSR64 9 9 read-write 0 Secure #0 1 Non-secure #1 SAIELSR74 Security attributes of registers for IELSR95 to IELSR64 10 10 read-write 0 Secure #0 1 Non-secure #1 SAIELSR75 Security attributes of registers for IELSR95 to IELSR64 11 11 read-write 0 Secure #0 1 Non-secure #1 SAIELSR76 Security attributes of registers for IELSR95 to IELSR64 12 12 read-write 0 Secure #0 1 Non-secure #1 SAIELSR77 Security attributes of registers for IELSR95 to IELSR64 13 13 read-write 0 Secure #0 1 Non-secure #1 SAIELSR78 Security attributes of registers for IELSR95 to IELSR64 14 14 read-write 0 Secure #0 1 Non-secure #1 SAIELSR79 Security attributes of registers for IELSR95 to IELSR64 15 15 read-write 0 Secure #0 1 Non-secure #1 SAIELSR80 Security attributes of registers for IELSR95 to IELSR64 16 16 read-write 0 Secure #0 1 Non-secure #1 SAIELSR81 Security attributes of registers for IELSR95 to IELSR64 17 17 read-write 0 Secure #0 1 Non-secure #1 SAIELSR82 Security attributes of registers for IELSR95 to IELSR64 18 18 read-write 0 Secure #0 1 Non-secure #1 SAIELSR83 Security attributes of registers for IELSR95 to IELSR64 19 19 read-write 0 Secure #0 1 Non-secure #1 SAIELSR84 Security attributes of registers for IELSR95 to IELSR64 20 20 read-write 0 Secure #0 1 Non-secure #1 SAIELSR85 Security attributes of registers for IELSR95 to IELSR64 21 21 read-write 0 Secure #0 1 Non-secure #1 SAIELSR86 Security attributes of registers for IELSR95 to IELSR64 22 22 read-write 0 Secure #0 1 Non-secure #1 SAIELSR87 Security attributes of registers for IELSR95 to IELSR64 23 23 read-write 0 Secure #0 1 Non-secure #1 SAIELSR88 Security attributes of registers for IELSR95 to IELSR64 24 24 read-write 0 Secure #0 1 Non-secure #1 SAIELSR89 Security attributes of registers for IELSR95 to IELSR64 25 25 read-write 0 Secure #0 1 Non-secure #1 SAIELSR90 Security attributes of registers for IELSR95 to IELSR64 26 26 read-write 0 Secure #0 1 Non-secure #1 SAIELSR91 Security attributes of registers for IELSR95 to IELSR64 27 27 read-write 0 Secure #0 1 Non-secure #1 SAIELSR92 Security attributes of registers for IELSR95 to IELSR64 28 28 read-write 0 Secure #0 1 Non-secure #1 SAIELSR93 Security attributes of registers for IELSR95 to IELSR64 29 29 read-write 0 Secure #0 1 Non-secure #1 SAIELSR94 Security attributes of registers for IELSR95 to IELSR64 30 30 read-write 0 Secure #0 1 Non-secure #1 SAIELSR95 Security attributes of registers for IELSR95 to IELSR64 31 31 read-write 0 Secure #0 1 Non-secure #1 BUSSARA BUS Security Attribution Register A 0x0100 32 read-write 0xffffffff 0xffffffff BUSSA0 BUS Security Attribution A0 0 0 read-write 0 Secure #0 1 Non-Secure #1 BUSSARB BUS Security Attribution Register B 0x0104 32 read-write 0xffffffff 0xffffffff BUSSB0 BUS Security Attribution B0 0 0 read-write 0 Secure #0 1 Non-Secure #1 MMPUSARA Master Memory Protection Unit Security Attribution Register A 0x130 32 read-write 0xffffffff 0xffffffff MMPUASAn MMPUA Security Attribution (n = 0 to 7) 0 7 read-write 0 Secure #0 1 Non-Secure #1 MMPUSARB Master Memory Protection Unit Security Attribution Register B 0x134 32 read-write 0xffffffff 0xffffffff MMPUBSA0 MMPUB Security Attribution 0 0 read-write 0 Secure #0 1 Non-Secure #1 TZFSAR TrustZone Filter Security Attribution Register 0x180 32 read-write 0xfffffffe 0xffffffff TZFSA0 Security attributes of registers for TrustZone Filter 0 0 read-write 0 Secure #0 1 Non-secure #1 CPUDSAR CPU Debug Security Attribution Register 0x1B0 32 read-write 0xfffffffe 0xffffffff CPUDSA0 CPU Debug Security Attribution 0 0 0 read-write 0 Secure #0 1 Non-secure #1 DBG Debug Function 0x4001B000 0x00 4 registers 0x10 4 registers DBGSTR Debug Status Register 0x00 32 read-only 0x00000000 0xffffffff CDBGPWRUPREQ Debug power-up request 28 28 read-only 0 OCD is not requesting debug power up #0 1 OCD is requesting debug power up #1 CDBGPWRUPACK Debug power-up acknowledge 29 29 read-only 0 Debug power-up request is not acknowledged #0 1 Debug power-up request is acknowledged #1 DBGSTOPCR Debug Stop Control Register 0x10 32 read-write 0x00000003 0xffffffff DBGSTOP_IWDT Mask bit for IWDT reset/interrupt in the OCD run mode 0 0 read-write 0 Enable IWDT reset/interrupt #0 1 Mask IWDT reset/interrupt and stop IWDT counter #1 DBGSTOP_WDT Mask bit for WDT reset/interrupt in the OCD run mode 1 1 read-write 0 Enable WDT reset/interrupt #0 1 Mask WDT reset/interrupt and stop WDT counter #1 DBGSTOP_LVD0 Mask bit for LVD0 reset 16 16 read-write 0 Enable LVD0 reset #0 1 Mask LVD0 reset #1 DBGSTOP_LVD1 Mask bit for LVD1 reset/interrupt 17 17 read-write 0 Enable LVD1 reset/interrupt #0 1 Mask LVD1 reset/interrupt #1 DBGSTOP_LVD2 Mask bit for LVD2 reset/interrupt 18 18 read-write 0 Enable LVD2 reset/interrupt #0 1 Mask LVD2 reset/interrupt #1 DBGSTOP_RPER Mask bit for SRAM parity error reset/interrupt 24 24 read-write 0 Enable SRAM parity error reset/interrupt #0 1 Mask SRAM parity error reset/interrupt #1 DBGSTOP_RECCR Mask bit for SRAM ECC error reset/interrupt 25 25 read-write 0 Enable SRAM ECC error reset/interrupt #0 1 Mask SRAM ECC error reset/interrupt #1 DBGSTOP_CPER Mask bit for Cache SRAM parity error reset/interrupt 31 31 read-write 0 Enable Cache SRAM parity error reset/interrupt #0 1 Mask Cache SRAM parity error reset/interrupt #1 FCACHE SYSTEM/FLASH 0x4001C100 0x00 2 registers 0x04 2 registers 0x1C 1 registers 0x40 2 registers FCACHEE Flash Cache Enable Register 0x000 16 read-write 0x0000 0xffff FCACHEEN Flash Cache Enable 0 0 read-write 0 FCACHE is disabled #0 1 FCACHE is enabled #1 FCACHEIV Flash Cache Invalidate Register 0x004 16 read-write 0x0000 0xffff FCACHEIV Flash Cache Invalidate 0 0 read-write 0 Read: Do not invalidate. Write: The setting is ignored. #0 1 Invalidate FCACHE is invalidated. #1 FLWT Flash Wait Cycle Register 0x01C 8 read-write 0x00 0xff FLWT Flash Wait Cycle 0 2 read-write 000 0 wait (ICLK ≤ 50 MHz) #000 001 1 wait (ICLK > 50 MHz) #001 010 2 wait Not specified #010 011 3 wait Not specified #011 Others Setting prohibited true FSAR Flash Security Attribution Register 0x040 16 read-write 0xffff 0xffff FLWTSA FLWT Security Attribution 0 0 read-write 0 Secure #0 1 Non-Secure #1 FCKMHZSA FCKMHZ Security Attribution 8 8 read-write 0 Secure #0 1 Non-Secure #1 SYSC System Control 0x4001E000 0x0C 2 registers 0x20 4 registers 0x26 1 registers 0x28 3 registers 0x32 1 registers 0x36 1 registers 0x38 5 registers 0x3E 1 registers 0x40 2 registers 0x61 2 registers 0x6E 1 registers 0x71 1 registers 0x76 1 registers 0x79 1 registers 0x92 1 registers 0x94 1 registers 0x98 4 registers 0xA0 1 registers 0xA2 1 registers 0xAA 1 registers 0xC0 2 registers 0xE0 4 registers 0x3C0 16 registers 0x3E0 4 registers 0x3FE 15 registers 0x40E 1 registers 0x410 2 registers 0x413 1 registers 0x416 3 registers 0x41A 2 registers 0x480 2 registers 0x490 1 registers 0x492 1 registers SBYCR Standby Control Register 0x00C 16 read-write 0x4000 0xffff SSBY Software Standby Mode Select 15 15 read-write 0 Sleep mode #0 1 Software Standby mode. #1 SCKDIVCR System Clock Division Control Register 0x020 32 read-write 0x22002222 0xffffffff PCKD Peripheral Module Clock D (PCLKD) Select 0 2 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Setting prohibited. true PCKC Peripheral Module Clock C (PCLKC) Select 4 6 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Setting prohibited. true PCKB Peripheral Module Clock B (PCLKB) Select 8 10 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Setting prohibited. true PCKA Peripheral Module Clock A (PCLKA) Select 12 14 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Setting prohibited. true ICK System Clock (ICLK) Select 24 26 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Setting prohibited. true FCK FlashIF Clock (FCLK) Select 28 30 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Setting prohibited. true SCKSCR System Clock Source Control Register 0x026 8 read-write 0x01 0xff CKSEL Clock Source Select 0 2 read-write 000 HOCO #000 001 MOCO #001 010 LOCO #010 011 Main clock oscillator (MOSC) #011 100 Sub-clock oscillator (SOSC) #100 101 PLL #101 110 Setting prohibited #110 111 Setting prohibited #111 PLLCCR PLL Clock Control Register 0x028 16 read-write 0x1300 0xffff PLIDIV PLL Input Frequency Division Ratio Select 0 1 read-write 00 /1 #00 01 /2 #01 10 /3 #10 Others Setting prohibited. true PLSRCSEL PLL Clock Source Select 4 4 read-write 0 Main clock oscillator #0 1 HOCO #1 PLLMUL PLL Frequency Multiplication Factor Select 8 13 read-write 0x13 0x3B PLLCR PLL Control Register 0x02A 8 read-write 0x01 0xff PLLSTP PLL Stop Control 0 0 read-write 0 PLL is operating #0 1 PLL is stopped. #1 MOSCCR Main Clock Oscillator Control Register 0x032 8 read-write 0x01 0xff MOSTP Main Clock Oscillator Stop 0 0 read-write 0 Operate the main clock oscillator #0 1 Stop the main clock oscillator #1 HOCOCR High-Speed On-Chip Oscillator Control Register 0x036 8 read-write 0x00 0xfe HCSTP HOCO Stop 0 0 read-write 0 Operate the HOCO clock #0 1 Stop the HOCO clock #1 MOCOCR Middle-Speed On-Chip Oscillator Control Register 0x038 8 read-write 0x00 0xff MCSTP MOCO Stop 0 0 read-write 0 MOCO clock is operating #0 1 MOCO clock is stopped #1 FLLCR1 FLL Control Register1 0x039 8 read-write 0x00 0xff FLLEN FLL Enable 0 0 read-write 0 FLL function is disabled #0 1 FLL function is enabled. #1 FLLCR2 FLL Control Register2 0x03A 16 read-write 0x0000 0xffff FLLCNTL FLL Multiplication Control 0 10 read-write OSCSF Oscillation Stabilization Flag Register 0x03C 8 read-only 0x00 0xfe HOCOSF HOCO Clock Oscillation Stabilization Flag 0 0 read-only 0 The HOCO clock is stopped or is not yet stable #0 1 The HOCO clock is stable, so is available for use as the system clock #1 MOSCSF Main Clock Oscillation Stabilization Flag 3 3 read-only 0 The main clock oscillator is stopped (MOSTP = 1) or is not yet stable #0 1 The main clock oscillator is stable, so is available for use as the system clock #1 PLLSF PLL Clock Oscillation Stabilization Flag 5 5 read-only 0 The PLL clock is stopped, or oscillation of the PLL clock is not stable yet #0 1 The PLL clock is stable, so is available for use as the system clock #1 CKOCR Clock Out Control Register 0x03E 8 read-write 0x00 0xff CKOSEL Clock Out Source Select 0 2 read-write 000 HOCO (value after reset) #000 001 MOCO #001 010 LOCO #010 011 MOSC #011 100 SOSC #100 101 Setting prohibited #101 Others Setting prohibited true CKODIV Clock Output Frequency Division Ratio 4 6 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 111 x 1/128 #111 CKOEN Clock Out Enable 7 7 read-write 0 Disable clock out #0 1 Enable clock out #1 OSTDCR Oscillation Stop Detection Control Register 0x040 8 read-write 0x00 0xff OSTDIE Oscillation Stop Detection Interrupt Enable 0 0 read-write 0 Disable oscillation stop detection interrupt (do not notify the POEG) #0 1 Enable oscillation stop detection interrupt (notify the POEG) #1 OSTDE Oscillation Stop Detection Function Enable 7 7 read-write 0 Disable oscillation stop detection function #0 1 Enable oscillation stop detection function #1 OSTDSR Oscillation Stop Detection Status Register 0x041 8 read-write 0x00 0xff OSTDF Oscillation Stop Detection Flag 0 0 read-write 0 Main clock oscillation stop not detected #0 1 Main clock oscillation stop detected #1 MOCOUTCR MOCO User Trimming Control Register 0x061 8 read-write 0x00 0xff MOCOUTRM MOCO User Trimming 0 7 read-write HOCOUTCR HOCO User Trimming Control Register 0x062 8 read-write 0x00 0xff HOCOUTRM HOCO User Trimming 0 7 read-write CANFDCKDIVCR CANFD Clock Division Control Register 0x06E 8 read-write 0x00 0xff CANFDCKDIV CANFD clock (CANFDCLK) Division Select 0 2 read-write 000 /1 (value after reset) /2 /4 /6 /8 /3 /5 #000 I3CCKDIVCR I3C Clock Division Control Register 0x071 8 read-write 0x00 0xff I3CCKDIV I3C clock (I3CCLK) division select 0 2 read-write 000 /1 (value after reset) #000 001 /2 #001 010 /4 #010 011 /6 #011 100 /8 #100 Others Setting prohibited true CANFDCKCR CANFD Clock Control Register 0x076 8 read-write 0x01 0xff CANFDCKSEL CANFD clock (CANFDCLK) Source Select 0 2 read-write 101 PLL #101 Others Setting prohibited true CANFDCKSREQ CANFD clock (CANFDCLK) Switching Request 6 6 read-write 0 No request #0 1 Request switching #1 CANFDCKSRDY CANFD clock (CANFDCLK) Switching Ready state flag 7 7 read-only 0 Impossible to Switch #0 1 Possible to Switch #1 I3CCKCR I3C Clock Control Register 0x079 8 read-write 0x00 0xff I3CCKSEL I3C clock (I3CCLK) source select 0 2 read-write 000 HOCO #000 001 MOCO (value after reset) #001 010 LOCO #010 011 Main clock oscillator #011 100 Sub-clock oscillator #100 101 PLL #101 Others Setting prohibited true I3CCKSREQ I3C clock (I3CCLK) switching request 6 6 read-write 0 No request #0 1 Request switching #1 I3CCKSRDY I3C clock (I3CCLK) switching ready state flag 7 7 read-only 0 Impossible to Switch #0 1 Possible to Switch #1 SNZCR Snooze Control Register 0x092 8 read-write 0x00 0xff RXDREQEN RXD0 Snooze Request Enable 0 0 read-write 0 Ignore RXD0 falling edge in Software Standby mode #0 1 Detect RXD0 falling edge in Software Standby mode #1 SNZDTCEN DTC Enable in Snooze mode 1 1 read-write 0 Disable DTC operation #0 1 Enable DTC operation #1 SNZE Snooze mode Enable 7 7 read-write 0 Disable Snooze mode #0 1 Enable Snooze mode #1 SNZEDCR0 Snooze End Control Register 0 0x094 8 read-write 0x00 0xff AGTUNFED AGT1 Underflow Snooze End Enable 0 0 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 DTCZRED Last DTC Transmission Completion Snooze End Enable 1 1 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 DTCNZRED Not Last DTC Transmission Completion Snooze End Enable 2 2 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 AD0MATED ADC120 Compare Match Snooze End Enable 3 3 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 AD0UMTED ADC120 Compare Mismatch Snooze End Enable 4 4 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 SCI0UMTED SCI0 Address Mismatch Snooze End Enable 7 7 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 SNZREQCR0 Snooze Request Control Register 0 0x098 32 read-write 0x00000000 0xffffffff SNZREQEN0 Enable IRQ0 pin snooze request 0 0 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN1 Enable IRQ1 pin snooze request 1 1 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN2 Enable IRQ2 pin snooze request 2 2 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN3 Enable IRQ3 pin snooze request 3 3 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN4 Enable IRQ4 pin snooze request 4 4 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN5 Enable IRQ5 pin snooze request 5 5 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN6 Enable IRQ6 pin snooze request 6 6 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN7 Enable IRQ7 pin snooze request 7 7 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN8 Enable IRQ8 pin snooze request 8 8 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN9 Enable IRQ9 pin snooze request 9 9 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN10 Enable IRQ10 pin snooze request 10 10 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN11 Enable IRQ11 pin snooze request 11 11 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN12 Enable IRQ12 pin snooze request 12 12 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN13 Enable IRQ13 pin snooze request 13 13 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN14 Enable IRQ14 pin snooze request 14 14 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN22 Enable ACMPHS0 alarm snooze request 22 22 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN28 Enable AGT1 underflow snooze request 28 28 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN29 Enable AGT1 compare match A snooze request 29 29 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN30 Enable AGT1 compare match B snooze request 30 30 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 OPCCR Operating Power Control Register 0x0A0 8 read-write 0x00 0xff OPCM Operating Power Control Mode Select 0 1 read-write 00 High-speed mode #00 01 Setting prohibited #01 10 Setting prohibited #10 11 Low-speed mode #11 OPCMTSF Operating Power Control Mode Transition Status Flag 4 4 read-only 0 Transition completed #0 1 During transition #1 MOSCWTCR Main Clock Oscillator Wait Control Register 0x0A2 8 read-write 0x05 0xff MSTS Main Clock Oscillator Wait Time Setting 0 3 read-write 0x0 Wait time = 3 cycles (11.4 us) 0x0 0x1 Wait time = 35 cycles (133.5 us) 0x1 0x2 Wait time = 67 cycles (255.6 us) 0x2 0x3 Wait time = 131 cycles (499.7 us) 0x3 0x4 Wait time = 259 cycles (988.0 us) 0x4 0x5 Wait time = 547 cycles (2086.6 us) 0x5 0x6 Wait time = 1059 cycles (4039.8 us) 0x6 0x7 Wait time = 2147 cycles (8190.2 us) 0x7 0x8 Wait time = 4291 cycles (16368.9 us) 0x8 0x9 Wait time = 8163 cycles (31139.4 us) 0x9 Others Setting prohibited true SOPCCR Sub Operating Power Control Register 0x0AA 8 read-write 0x00 0xff SOPCM Sub Operating Power Control Mode Select 0 0 read-write 0 Other than Subosc-speed mode #0 1 Subosc-speed mode #1 SOPCMTSF Operating Power Control Mode Transition Status Flag 4 4 read-only 0 Transition completed #0 1 During transition #1 RSTSR1 Reset Status Register 1 0x0C0 16 read-write 0x0000 0x54f8 IWDTRF Independent Watchdog Timer Reset Detect Flag 0 0 read-write 0 Independent watchdog timer reset not detected #0 1 Independent watchdog timer reset detected #1 WDTRF Watchdog Timer Reset Detect Flag 1 1 read-write 0 Watchdog timer reset not detected #0 1 Watchdog timer reset detected #1 SWRF Software Reset Detect Flag 2 2 read-write 0 Software reset not detected #0 1 Software reset detected #1 RPERF SRAM Parity Error Reset Detect Flag 8 8 read-write 0 SRAM parity error reset not detected #0 1 SRAM parity error reset detected #1 REERF SRAM ECC Error Reset Detect Flag 9 9 read-write 0 SRAM ECC error reset not detected #0 1 SRAM ECC error reset detected #1 BUSMRF Bus Master MPU Error Reset Detect Flag 11 11 read-write 0 Bus master MPU error reset not detected #0 1 Bus master MPU error reset detected #1 TZERF TrustZone Error Reset Detect Flag 13 13 read-write 0 TrustZone error reset not detected. #0 1 TrustZone error reset detected. #1 CPERF Cache Parity Error Reset Detect Flag 15 15 read-write 0 Cache Parity error reset not detected. #0 1 Cache Parity error reset detected. #1 LVD1CR1 Voltage Monitor 1 Circuit Control Register 0x0E0 8 read-write 0x01 0xff IDTSEL Voltage Monitor 1 Interrupt Generation Condition Select 0 1 read-write 00 When VCC >= Vdet1 (rise) is detected #00 01 When VCC < Vdet1 (fall) is detected #01 10 When fall and rise are detected #10 11 Settings prohibited #11 IRQSEL Voltage Monitor 1 Interrupt Type Select 2 2 read-write 0 Non-maskable interrupt #0 1 Maskable interrupt #1 LVD1SR Voltage Monitor 1 Circuit Status Register 0x0E1 8 read-write 0x02 0xff DET Voltage Monitor 1 Voltage Variation Detection Flag 0 0 read-write 0 Not detected #0 1 Vdet1 crossing is detected #1 MON Voltage Monitor 1 Signal Monitor Flag 1 1 read-only 0 VCC < Vdet1 #0 1 VCC >= Vdet1 or MON is disabled #1 LVD2CR1 Voltage Monitor 2 Circuit Control Register 1 0x0E2 8 read-write 0x01 0xff IDTSEL Voltage Monitor 2 Interrupt Generation Condition Select 0 1 read-write 00 When VCC>= Vdet2 (rise) is detected #00 01 When VCC < Vdet2 (fall) is detected #01 10 When fall and rise are detected #10 11 Settings prohibited #11 IRQSEL Voltage Monitor 2 Interrupt Type Select 2 2 read-write 0 Non-maskable interrupt #0 1 Maskable interrupt #1 LVD2SR Voltage Monitor 2 Circuit Status Register 0x0E3 8 read-write 0x02 0xff DET Voltage Monitor 2 Voltage Variation Detection Flag 0 0 read-write 0 Not detected #0 1 Vdet2 crossing is detected #1 MON Voltage Monitor 2 Signal Monitor Flag 1 1 read-only 0 VCC < Vdet2 #0 1 VCC>= Vdet2 or MON is disabled #1 CGFSAR Clock Generation Function Security Attribute Register 0x3C0 32 read-write 0xffffffff 0xffffffff NONSEC00 Non Secure Attribute bit 00 0 0 read-write 0 Secure #0 1 Non Secure #1 NONSEC02 Non Secure Attribute bit 02 2 2 read-write 0 Secure #0 1 Non Secure #1 NONSEC03 Non Secure Attribute bit 03 3 3 read-write 0 Secure #0 1 Non Secure #1 NONSEC04 Non Secure Attribute bit 04 4 4 read-write 0 Secure #0 1 Non Secure #1 NONSEC05 Non Secure Attribute bit 05 5 5 read-write 0 Secure #0 1 Non Secure #1 NONSEC06 Non Secure Attribute bit 06 6 6 read-write 0 Secure #0 1 Non Secure #1 NONSEC07 Non Secure Attribute bit 07 7 7 read-write 0 Secure #0 1 Non Secure #1 NONSEC08 Non Secure Attribute bit 08 8 8 read-write 0 Secure #0 1 Non Secure #1 NONSEC11 Non Secure Attribute bit 11 11 11 read-write 0 Secure #0 1 Non Secure #1 NONSEC18 Non Secure Attribute bit 18 18 18 read-write 0 Secure #0 1 Non Secure #1 RSTSAR Reset Security Attribution Register 0x3C4 32 read-write 0xffffffff 0xffffffff NONSEC0 Non Secure Attribute bit 0 0 0 read-write 0 Secure #0 1 Non Secure #1 NONSEC1 Non Secure Attribute bit 1 1 1 read-write 0 Secure #0 1 Non Secure #1 NONSEC2 Non Secure Attribute bit 2 2 2 read-write 0 Secure #0 1 Non Secure #1 LPMSAR Low Power Mode Security Attribution Register 0x3C8 32 read-write 0xffffffff 0xffffffff NONSEC0 Non Secure Attribute bit 0 0 0 read-write 0 Secure #0 1 Non Secure #1 NONSEC2 Non Secure Attribute bit 2 2 2 read-write 0 Secure #0 1 Non Secure #1 NONSEC4 Non Secure Attribute bit 4 4 4 read-write 0 Secure #0 1 Non Secure #1 NONSEC8 Non Secure Attribute bit 8 8 8 read-write 0 Secure #0 1 Non Secure #1 NONSEC9 Non Secure Attribute bit 9 9 9 read-write 0 Secure #0 1 Non Secure #1 LVDSAR Low Voltage Detection Security Attribution Register 0x3CC 32 read-write 0xffffffff 0xffffffff NONSEC0 Non Secure Attribute bit 0 0 0 read-write 0 Secure #0 1 Non Secure #1 NONSEC1 Non Secure Attribute bit 1 1 1 read-write 0 Secure #0 1 Non Secure #1 DPFSAR Deep Standby Interrupt Factor Security Attribution Register 0x3E0 32 read-write 0xffffffff 0xffffffff DPFSA0 Deep Standby Interrupt Factor Security Attribute bit 0 0 0 read-write 0 Secure #0 1 Non Secure #1 DPFSA1 Deep Standby Interrupt Factor Security Attribute bit 1 1 1 read-write 0 Secure #0 1 Non Secure #1 DPFSA04 Deep Standby Interrupt Factor Security Attribute bit n (n = 4 to 12) 4 4 read-write 0 Secure #0 1 Non Secure #1 DPFSA05 Deep Standby Interrupt Factor Security Attribute bit n (n = 4 to 12) 5 5 read-write 0 Secure #0 1 Non Secure #1 DPFSA06 Deep Standby Interrupt Factor Security Attribute bit n (n = 4 to 12) 6 6 read-write 0 Secure #0 1 Non Secure #1 DPFSA07 Deep Standby Interrupt Factor Security Attribute bit n (n = 4 to 12) 7 7 read-write 0 Secure #0 1 Non Secure #1 DPFSA08 Deep Standby Interrupt Factor Security Attribute bit n (n = 4 to 12) 8 8 read-write 0 Secure #0 1 Non Secure #1 DPFSA09 Deep Standby Interrupt Factor Security Attribute bit n (n = 4 to 12) 9 9 read-write 0 Secure #0 1 Non Secure #1 DPFSA10 Deep Standby Interrupt Factor Security Attribute bit n (n = 4 to 12) 10 10 read-write 0 Secure #0 1 Non Secure #1 DPFSA11 Deep Standby Interrupt Factor Security Attribute bit n (n = 4 to 12) 11 11 read-write 0 Secure #0 1 Non Secure #1 DPFSA12 Deep Standby Interrupt Factor Security Attribute bit n (n = 4 to 12) 12 12 read-write 0 Secure #0 1 Non Secure #1 DPFSA14 Deep Standby Interrupt Factor Security Attribute bit 14 14 14 read-write 0 Secure #0 1 Non Secure #1 DPFSA16 Deep Standby Interrupt Factor Security Attribute bit 16 16 16 read-write 0 Secure #0 1 Non Secure #1 DPFSA17 Deep Standby Interrupt Factor Security Attribute bit 17 17 17 read-write 0 Secure #0 1 Non Secure #1 DPFSA20 Deep Standby Interrupt Factor Security Attribute bit 20 20 20 read-write 0 Secure #0 1 Non Secure #1 DPFSA26 Deep Standby Interrupt Factor Security Attribute bit 26 26 26 read-write 0 Secure #0 1 Non Secure #1 PRCR Protect Register 0x3FE 16 read-write 0x0000 0xffff PRC0 Enable writing to the registers related to the clock generation circuit 0 0 read-write 0 Disable writes #0 1 Enable writes #1 PRC1 Enable writing to the registers related to the low power modes 1 1 read-write 0 Disable writes #0 1 Enable writes #1 PRC3 Enable writing to the registers related to the LVD 3 3 read-write 0 Disable writes #0 1 Enable writes #1 PRC4 4 4 read-write 0 Disable writes #0 1 Enable writes #1 PRKEY PRC Key Code 8 15 write-only DPSBYCR Deep Standby Control Register 0x400 8 read-write 0x01 0xff DEEPCUT Power-Supply Control 0 1 read-write 00 Power to the Low-speed on-chip oscillator, and AGTn (n = 0, 1) is supplied in Deep Software Standby mode. #00 01 Power to the Low-speed on-chip oscillator, and AGT is not supplied in Deep Software Standby mode. #01 10 Setting prohibited #10 11 Power to the Low-speed on-chip oscillator, and AGT is not supplied in Deep Software Standby mode. In addition, LVD is disabled and the low power function in a power-on reset circuit is enabled. #11 IOKEEP I/O Port Rentention 6 6 read-write 0 When the Deep Software Standby mode is canceled, the I/O ports are in the reset state. #0 1 When the Deep Software Standby mode is canceled, the I/O ports are in the same state as in the Deep Software Standby mode. #1 DPSBY Deep Software Standby 7 7 read-write 0 Sleep mode (SBYCR.SSBY=0) / Software Standby mode (SBYCR.SSBY=1) #0 1 Sleep mode (SBYCR.SSBY=0) / Deep Software Standby mode (SBYCR.SSBY=1) #1 DPSWCR Deep Standby Wait Control Register 0x401 8 read-write 0x19 0xff WTSTS Deep Software Wait Standby Time Setting Bit 0 5 read-write 0x0E Wait cycle for fast recovery 0x0e 0x19 Wait cycle for slow recovery 0x19 Others Setting prohibited true DPSIER0 Deep Standby Interrupt Enable Register 0 0x402 8 read-write 0x00 0xff DIRQ0E IRQ0-DS Pin Enable 0 0 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ1E IRQ1-DS Pin Enable 1 1 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ4E IRQ4-DS Pin Enable 4 4 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ5E IRQ5-DS Pin Enable 5 5 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ6E IRQ6-DS Pin Enable 6 6 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ7E IRQ7-DS Pin Enable 7 7 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DPSIER1 Deep Standby Interrupt Enable Register 1 0x403 8 read-write 0x00 0xff DIRQ8E IRQ8-DS Pin Enable 0 0 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ9E IRQ9-DS Pin Enable 1 1 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ10E IRQ10-DS Pin Enable 2 2 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ11E IRQ11-DS Pin Enable 3 3 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ12E IRQ12-DS Pin Enable 4 4 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ14E IRQ14-DS Pin Enable 6 6 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DPSIER2 Deep Software Standby Interrupt Enable Register 2 0x404 8 read-write 0x00 0xff DLVD1IE LVD1 Deep Software Standby Cancel Signal Enable 0 0 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DLVD2IE LVD2 Deep Software Standby Cancel Signal Enable 1 1 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DNMIE NMI Pin Enable 4 4 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DPSIER3 Deep Standby Interrupt Enable Register 3 0x405 8 read-write 0x00 0xff DAGT1IE AGT1 Underflow Deep Standby Cancel Signal Enable 2 2 read-write 0 Cancelling deep standby mode is disabled #0 1 Cancelling deep standby mode is enabled #1 DPSIFR0 Deep Standby Interrupt Flag Register 0 0x406 8 read-write 0x00 0xff DIRQ0F IRQ0-DS Pin Deep Standby Cancel Flag 0 0 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ1F IRQ1-DS Pin Deep Standby Cancel Flag 1 1 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ4F IRQ4-DS Pin Deep Standby Cancel Flag 4 4 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ5F IRQ5-DS Pin Deep Standby Cancel Flag 5 5 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ6F IRQ6-DS Pin Deep Standby Cancel Flag 6 6 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ7F IRQ7-DS Pin Deep Standby Cancel Flag 7 7 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DPSIFR1 Deep Standby Interrupt Flag Register 1 0x407 8 read-write 0x00 0xff DIRQ8F IRQ8-DS Pin Deep Standby Cancel Flag 0 0 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ9F IRQ9-DS Pin Deep Standby Cancel Flag 1 1 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ10F IRQ10-DS Pin Deep Standby Cancel Flag 2 2 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ11F IRQ11-DS Pin Deep Standby Cancel Flag 3 3 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ12F IRQ12-DS Pin Deep Standby Cancel Flag 4 4 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ14F IRQ14-DS Pin Deep Standby Cancel Flag 6 6 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DPSIFR2 Deep Software Standby Interrupt Flag Register 2 0x408 8 read-write 0x00 0xff DLVD1IF LVD1 Deep Software Standby Cancel Flag 0 0 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DLVD2IF LVD2 Deep Software Standby Cancel Flag 1 1 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DNMIF NMI Pin Deep Software Standby Cancel Flag 4 4 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DPSIFR3 Deep Standby Interrupt Flag Register 3 0x409 8 read-write 0x00 0xff DAGT1IF AGT1 Underflow Deep Standby Cancel Flag 2 2 read-write 0 The cancel request is not generated. #0 1 The cancel request is generated. #1 DPSIEGR0 Deep Standby Interrupt Edge Register 0 0x40A 8 read-write 0x00 0xff DIRQ0EG IRQ0-DS Pin Edge Select 0 0 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ1EG IRQ1-DS Pin Edge Select 1 1 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ4EG IRQ4-DS Pin Edge Select 4 4 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ5EG IRQ5-DS Pin Edge Select 5 5 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ6EG IRQ6-DS Pin Edge Select 6 6 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ7EG IRQ7-DS Pin Edge Select 7 7 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DPSIEGR1 Deep Standby Interrupt Edge Register 1 0x40B 8 read-write 0x00 0xff DIRQ8EG IRQ8-DS Pin Edge Select 0 0 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ9EG IRQ9-DS Pin Edge Select 1 1 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ10EG IRQ10-DS Pin Edge Select 2 2 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge #1 DIRQ11EG IRQ11-DS Pin Edge Select 3 3 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ12EG IRQ12-DS Pin Edge Select 4 4 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ14EG IRQ14-DS Pin Edge Select 6 6 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DPSIEGR2 Deep Software Standby Interrupt Edge Register 2 0x40C 8 read-write 0x00 0xff DLVD1EG LVD1 Edge Select 0 0 read-write 0 A cancel request is generated when VCC < Vdet1 (fall) is detected #0 1 A cancel request is generated when VCC ≥ Vdet1 (rise) is detected #1 DLVD2EG LVD2 Edge Select 1 1 read-write 0 A cancel request is generated when VCC < Vdet2 (fall) is detected #0 1 A cancel request is generated when VCC ≥ Vdet2 (rise) is detected #1 DNMIEG NMI Pin Edge Select 4 4 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 SYOCDCR System Control OCD Control Register 0x040E 8 read-write 0x00 0xfe DOCDF Deep Software Standby OCD flag 0 0 read-write 0 DBIRQ is not generated #0 1 DBIRQ is generated #1 DBGEN Debugger Enable bit 7 7 read-write 0 On-chip debugger is disabled #0 1 On-chip debugger is enabled #1 RSTSR0 Reset Status Register 0 0x410 8 read-write 0x00 0x70 PORF Power-On Reset Detect Flag 0 0 read-write 0 Power-on reset not detected #0 1 Power-on reset detected #1 LVD0RF Voltage Monitor 0 Reset Detect Flag 1 1 read-write 0 Voltage monitor 0 reset not detected #0 1 Voltage monitor 0 reset detected #1 LVD1RF Voltage Monitor 1 Reset Detect Flag 2 2 read-write 0 Voltage monitor 1 reset not detected #0 1 Voltage monitor 1 reset detected #1 LVD2RF Voltage Monitor 2 Reset Detect Flag 3 3 read-write 0 Voltage monitor 2 reset not detected #0 1 Voltage monitor 2 reset detected #1 DPSRSTF Deep Software Standby Reset Detect Flag 7 7 read-write 0 Deep software standby mode cancellation not requested by an interrupt. #0 1 Deep software standby mode cancellation requested by an interrupt. #1 RSTSR2 Reset Status Register 2 0x411 8 read-write 0x00 0xfe CWSF Cold/Warm Start Determination Flag 0 0 read-write 0 Cold start #0 1 Warm start #1 MOMCR Main Clock Oscillator Mode Oscillation Control Register 0x413 8 read-write 0x00 0xff MODRV Main Clock Oscillator Drive Capability 0 Switching 4 5 read-write 00 20 MHz to 24 MHz #00 01 16 MHz to 20 MHz #01 10 8 MHz to 16 MHz #10 11 8 MHz #11 MOSEL Main Clock Oscillator Switching 6 6 read-write 0 Resonator #0 1 External clock input #1 FWEPROR Flash P/E Protect Register 0x416 8 read-write 0x02 0xff FLWE Flash Programming and Erasure 0 1 read-write 00 Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing. #00 01 Permits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing. #01 10 Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing. #10 11 Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing. #11 LVD1CMPCR Voltage Monitoring 1 Comparator Control Register 0x417 8 read-write 0x13 0xff LVD1LVL Voltage Detection 1 Level Select (Standard voltage during drop in voltage) 0 4 read-write 0x11 2.99 V (Vdet1_1) 0x11 0x12 2.92 V (Vdet1_2) 0x12 0x13 2.85 V (Vdet1_3) 0x13 Others Setting prohibited true LVD1E Voltage Detection 1 Enable 7 7 read-write 0 Voltage detection 1 circuit disabled #0 1 Voltage detection 1 circuit enabled #1 LVD2CMPCR Voltage Monitoring 2 Comparator Control Register 0x418 8 read-write 0x07 0xff LVD2LVL Voltage Detection 2 Level Select (Standard voltage during drop in voltage) 0 2 read-write 101 2.99 V (Vdet2_1) #101 110 2.92 V (Vdet2_2) #110 111 2.85 V (Vdet2_3) #111 Others Setting prohibited true LVD2E Voltage Detection 2 Enable 7 7 read-write 0 Voltage detection 2 circuit disabled #0 1 Voltage detection 2 circuit enabled #1 LVD1CR0 Voltage Monitor 1 Circuit Control Register 0 0x41A 8 read-write 0x82 0xf7 RIE Voltage Monitor 1 Interrupt/Reset Enable 0 0 read-write 0 Disable #0 1 Enable #1 DFDIS Voltage monitor 1 Digital Filter Disabled Mode Select 1 1 read-write 0 Enable the digital filter #0 1 Disable the digital filter #1 CMPE Voltage Monitor 1 Circuit Comparison Result Output Enable 2 2 read-write 0 Disable voltage monitor 1 circuit comparison result output #0 1 Enable voltage monitor 1 circuit comparison result output #1 FSAMP Sampling Clock Select 4 5 read-write 00 1/2 LOCO frequency #00 01 1/4 LOCO frequency #01 10 1/8 LOCO frequency #10 11 1/16 LOCO frequency #11 RI Voltage Monitor 1 Circuit Mode Select 6 6 read-write 0 Generate voltage monitor 1 interrupt on Vdet1 crossing #0 1 Enable voltage monitor 1 reset when the voltage falls to and below Vdet1 #1 RN Voltage Monitor 1 Reset Negate Select 7 7 read-write 0 Negate after a stabilization time (tLVD1) when VCC > Vdet1 is detected #0 1 Negate after a stabilization time (tLVD1) on assertion of the LVD1 reset #1 LVD2CR0 Voltage Monitor 2 Circuit Control Register 0 0x41B 8 read-write 0x82 0xf7 RIE Voltage Monitor 2 Interrupt/Reset Enable 0 0 read-write 0 Disable #0 1 Enable #1 DFDIS Voltage monitor 2 Digital Filter Disabled Mode Select 1 1 read-write 0 Enable the digital filter #0 1 Disable the digital filter #1 CMPE Voltage Monitor 2 Circuit Comparison Result Output Enable 2 2 read-write 0 Disable voltage monitor 2 circuit comparison result output #0 1 Enable voltage monitor 2 circuit comparison result output #1 FSAMP Sampling Clock Select 4 5 read-write 00 1/2 LOCO frequency #00 01 1/4 LOCO frequency #01 10 1/8 LOCO frequency #10 11 1/16 LOCO frequency #11 RI Voltage Monitor 2 Circuit Mode Select 6 6 read-write 0 Generate voltage monitor 2 interrupt on Vdet2 crossing #0 1 Enable voltage monitor 2 reset when the voltage falls to and below Vdet2 #1 RN Voltage Monitor 2 Reset Negate Select 7 7 read-write 0 Negate after a stabilization time (tLVD2) when VCC > Vdet2 is detected #0 1 Negate after a stabilization time (tLVD2) on assertion of the LVD2 reset #1 SOSCCR Sub-Clock Oscillator Control Register 0x480 8 read-write 0x00 0xff SOSTP Sub Clock Oscillator Stop 0 0 read-write 0 Operate the sub-clock oscillator #0 1 Stop the sub-clock oscillator #1 SOMCR Sub-Clock Oscillator Mode Control Register 0x481 8 read-write 0x00 0xff SODRV Sub-Clock Oscillator Drive Capability Switching 1 1 read-write 0 Standard #0 1 Low #1 LOCOCR Low-Speed On-Chip Oscillator Control Register 0x490 8 read-write 0x00 0xff LCSTP LOCO Stop 0 0 read-write 0 Operate the LOCO clock #0 1 Stop the LOCO clock #1 LOCOUTCR LOCO User Trimming Control Register 0x492 8 read-write 0x00 0xff LOCOUTRM LOCO User Trimming 0 7 read-write TFU Trigonometric Function Unit 0x40021000 0x08 1 registers 0x10 16 registers TRGSTS Trigonometric Status Register 0x08 8 read-only 0x00 0xff BSYF Calculation in progress flag 0 0 read-only 0 No calculating #0 1 Calculating #1 ERRF Input error flag 1 1 read-only 0 No input error occurred #0 1 Input error occurred #1 SCDT0 Sine Cosine Data Register 0 0x10 32 read-write 0x00000000 0xffffffff SCDT0 Sine Cosine Data Register 0 (single-precision floating-point) 0 31 read-write SCDT1 Sine Cosine Data Register 1 0x14 32 read-write 0x00000000 0xffffffff SCDT1 Sine Cosine Data Register 1 (single-precision floating-point) 0 31 read-write ATDT0 Arctangent Data Register 0 0x18 32 read-write 0x00000000 0xffffffff ATDT0 Arctangent Data Register 0 (single-precision floating-point) 0 31 read-write ATDT1 Arctangent Data Register 1 0x1C 32 read-write 0x00000000 0xffffffff ATDT1 Arctangent Data Register 1 (single-precision floating-point) 0 31 read-write PORT0 Pmn Pin FunctionPort 0 Control RegistersPmn Pin Function Control Register 0x40080000 0x00 12 registers PCNTR1 Port Control Register 1 0x000 32 read-write 0x00000000 0xffffffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 31 read-write 0 Low output #0 1 High output #1 PODR Port Control Register 1 PCNTR1 0x000 16 read-write 0x0000 0xffff PODR00 Pmn Output Data 0 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 15 read-write 0 Low output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x002 16 read-write 0x0000 0xffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCNTR2 Port Control Register 2 0x004 32 read-only 0x00000000 0xffff0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 PIDR Port Control Register 2 PCNTR2 0x006 16 read-only 0x0000 0x0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 PCNTR3 Port Control Register 3 0x008 32 write-only 0x00000000 0xffffffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR00 Pmn Output Reset 16 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 31 write-only 0 No effect on output #0 1 Low output #1 PORR Port Control Register 3 PCNTR3 0x008 16 write-only 0x0000 0xffff PORR00 Pmn Output Reset 0 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 15 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0x00A 16 write-only 0x0000 0xffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORT1 Pmn Pin FunctionPort 1 Control RegistersPmn Pin Function Control Register 0x40080020 0x00 16 registers PCNTR1 Port Control Register 1 0x000 32 read-write 0x00000000 0xffffffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 31 read-write 0 Low output #0 1 High output #1 PODR Port Control Register 1 PCNTR1 0x000 16 read-write 0x0000 0xffff PODR00 Pmn Output Data 0 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 15 read-write 0 Low output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x002 16 read-write 0x0000 0xffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCNTR2 Port Control Register 2 0x004 32 read-only 0x00000000 0xffff0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 EIDR00 Port Event Input Data 16 16 read-only 0 Low input #0 1 High input #1 EIDR01 Port Event Input Data 17 17 read-only 0 Low input #0 1 High input #1 EIDR02 Port Event Input Data 18 18 read-only 0 Low input #0 1 High input #1 EIDR03 Port Event Input Data 19 19 read-only 0 Low input #0 1 High input #1 EIDR04 Port Event Input Data 20 20 read-only 0 Low input #0 1 High input #1 EIDR05 Port Event Input Data 21 21 read-only 0 Low input #0 1 High input #1 EIDR06 Port Event Input Data 22 22 read-only 0 Low input #0 1 High input #1 EIDR07 Port Event Input Data 23 23 read-only 0 Low input #0 1 High input #1 EIDR08 Port Event Input Data 24 24 read-only 0 Low input #0 1 High input #1 EIDR09 Port Event Input Data 25 25 read-only 0 Low input #0 1 High input #1 EIDR10 Port Event Input Data 26 26 read-only 0 Low input #0 1 High input #1 EIDR11 Port Event Input Data 27 27 read-only 0 Low input #0 1 High input #1 EIDR12 Port Event Input Data 28 28 read-only 0 Low input #0 1 High input #1 EIDR13 Port Event Input Data 29 29 read-only 0 Low input #0 1 High input #1 EIDR14 Port Event Input Data 30 30 read-only 0 Low input #0 1 High input #1 EIDR15 Port Event Input Data 31 31 read-only 0 Low input #0 1 High input #1 EIDR Port Control Register 2 PCNTR2 0x004 16 read-only 0x0000 0xffff EIDR00 Port Event Input Data 0 0 read-only 0 Low input #0 1 High input #1 EIDR01 Port Event Input Data 1 1 read-only 0 Low input #0 1 High input #1 EIDR02 Port Event Input Data 2 2 read-only 0 Low input #0 1 High input #1 EIDR03 Port Event Input Data 3 3 read-only 0 Low input #0 1 High input #1 EIDR04 Port Event Input Data 4 4 read-only 0 Low input #0 1 High input #1 EIDR05 Port Event Input Data 5 5 read-only 0 Low input #0 1 High input #1 EIDR06 Port Event Input Data 6 6 read-only 0 Low input #0 1 High input #1 EIDR07 Port Event Input Data 7 7 read-only 0 Low input #0 1 High input #1 EIDR08 Port Event Input Data 8 8 read-only 0 Low input #0 1 High input #1 EIDR09 Port Event Input Data 9 9 read-only 0 Low input #0 1 High input #1 EIDR10 Port Event Input Data 10 10 read-only 0 Low input #0 1 High input #1 EIDR11 Port Event Input Data 11 11 read-only 0 Low input #0 1 High input #1 EIDR12 Port Event Input Data 12 12 read-only 0 Low input #0 1 High input #1 EIDR13 Port Event Input Data 13 13 read-only 0 Low input #0 1 High input #1 EIDR14 Port Event Input Data 14 14 read-only 0 Low input #0 1 High input #1 EIDR15 Port Event Input Data 15 15 read-only 0 Low input #0 1 High input #1 PIDR Port Control Register 2 PCNTR2 0x006 16 read-only 0x0000 0x0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 PCNTR3 Port Control Register 3 0x008 32 write-only 0x00000000 0xffffffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR00 Pmn Output Reset 16 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 31 write-only 0 No effect on output #0 1 Low output #1 PORR Port Control Register 3 PCNTR3 0x008 16 write-only 0x0000 0xffff PORR00 Pmn Output Reset 0 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 15 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0x00A 16 write-only 0x0000 0xffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PCNTR4 Port Control Register 4 0x00C 32 read-write 0x00000000 0xffffffff EOSR00 Pmn Event Output Set 0 0 read-write 0 No effect on output #0 1 High output #1 EOSR01 Pmn Event Output Set 1 1 read-write 0 No effect on output #0 1 High output #1 EOSR02 Pmn Event Output Set 2 2 read-write 0 No effect on output #0 1 High output #1 EOSR03 Pmn Event Output Set 3 3 read-write 0 No effect on output #0 1 High output #1 EOSR04 Pmn Event Output Set 4 4 read-write 0 No effect on output #0 1 High output #1 EOSR05 Pmn Event Output Set 5 5 read-write 0 No effect on output #0 1 High output #1 EOSR06 Pmn Event Output Set 6 6 read-write 0 No effect on output #0 1 High output #1 EOSR07 Pmn Event Output Set 7 7 read-write 0 No effect on output #0 1 High output #1 EOSR08 Pmn Event Output Set 8 8 read-write 0 No effect on output #0 1 High output #1 EOSR09 Pmn Event Output Set 9 9 read-write 0 No effect on output #0 1 High output #1 EOSR10 Pmn Event Output Set 10 10 read-write 0 No effect on output #0 1 High output #1 EOSR11 Pmn Event Output Set 11 11 read-write 0 No effect on output #0 1 High output #1 EOSR12 Pmn Event Output Set 12 12 read-write 0 No effect on output #0 1 High output #1 EOSR13 Pmn Event Output Set 13 13 read-write 0 No effect on output #0 1 High output #1 EOSR14 Pmn Event Output Set 14 14 read-write 0 No effect on output #0 1 High output #1 EOSR15 Pmn Event Output Set 15 15 read-write 0 No effect on output #0 1 High output #1 EORR00 Pmn Event Output Reset 16 16 read-write 0 No effect on output #0 1 Low output #1 EORR01 Pmn Event Output Reset 17 17 read-write 0 No effect on output #0 1 Low output #1 EORR02 Pmn Event Output Reset 18 18 read-write 0 No effect on output #0 1 Low output #1 EORR03 Pmn Event Output Reset 19 19 read-write 0 No effect on output #0 1 Low output #1 EORR04 Pmn Event Output Reset 20 20 read-write 0 No effect on output #0 1 Low output #1 EORR05 Pmn Event Output Reset 21 21 read-write 0 No effect on output #0 1 Low output #1 EORR06 Pmn Event Output Reset 22 22 read-write 0 No effect on output #0 1 Low output #1 EORR07 Pmn Event Output Reset 23 23 read-write 0 No effect on output #0 1 Low output #1 EORR08 Pmn Event Output Reset 24 24 read-write 0 No effect on output #0 1 Low output #1 EORR09 Pmn Event Output Reset 25 25 read-write 0 No effect on output #0 1 Low output #1 EORR10 Pmn Event Output Reset 26 26 read-write 0 No effect on output #0 1 Low output #1 EORR11 Pmn Event Output Reset 27 27 read-write 0 No effect on output #0 1 Low output #1 EORR12 Pmn Event Output Reset 28 28 read-write 0 No effect on output #0 1 Low output #1 EORR13 Pmn Event Output Reset 29 29 read-write 0 No effect on output #0 1 Low output #1 EORR14 Pmn Event Output Reset 30 30 read-write 0 No effect on output #0 1 Low output #1 EORR15 Pmn Event Output Reset 31 31 read-write 0 No effect on output #0 1 Low output #1 EORR Port Control Register 4 PCNTR4 0x00C 16 read-write 0x0000 0xffff EORR00 Pmn Event Output Reset 0 0 read-write 0 No effect on output #0 1 Low output #1 EORR01 Pmn Event Output Reset 1 1 read-write 0 No effect on output #0 1 Low output #1 EORR02 Pmn Event Output Reset 2 2 read-write 0 No effect on output #0 1 Low output #1 EORR03 Pmn Event Output Reset 3 3 read-write 0 No effect on output #0 1 Low output #1 EORR04 Pmn Event Output Reset 4 4 read-write 0 No effect on output #0 1 Low output #1 EORR05 Pmn Event Output Reset 5 5 read-write 0 No effect on output #0 1 Low output #1 EORR06 Pmn Event Output Reset 6 6 read-write 0 No effect on output #0 1 Low output #1 EORR07 Pmn Event Output Reset 7 7 read-write 0 No effect on output #0 1 Low output #1 EORR08 Pmn Event Output Reset 8 8 read-write 0 No effect on output #0 1 Low output #1 EORR09 Pmn Event Output Reset 9 9 read-write 0 No effect on output #0 1 Low output #1 EORR10 Pmn Event Output Reset 10 10 read-write 0 No effect on output #0 1 Low output #1 EORR11 Pmn Event Output Reset 11 11 read-write 0 No effect on output #0 1 Low output #1 EORR12 Pmn Event Output Reset 12 12 read-write 0 No effect on output #0 1 Low output #1 EORR13 Pmn Event Output Reset 13 13 read-write 0 No effect on output #0 1 Low output #1 EORR14 Pmn Event Output Reset 14 14 read-write 0 No effect on output #0 1 Low output #1 EORR15 Pmn Event Output Reset 15 15 read-write 0 No effect on output #0 1 Low output #1 EOSR Port Control Register 4 PCNTR4 0x00E 16 read-write 0x0000 0xffff EOSR00 Pmn Event Output Set 0 0 read-write 0 No effect on output #0 1 High output #1 EOSR01 Pmn Event Output Set 1 1 read-write 0 No effect on output #0 1 High output #1 EOSR02 Pmn Event Output Set 2 2 read-write 0 No effect on output #0 1 High output #1 EOSR03 Pmn Event Output Set 3 3 read-write 0 No effect on output #0 1 High output #1 EOSR04 Pmn Event Output Set 4 4 read-write 0 No effect on output #0 1 High output #1 EOSR05 Pmn Event Output Set 5 5 read-write 0 No effect on output #0 1 High output #1 EOSR06 Pmn Event Output Set 6 6 read-write 0 No effect on output #0 1 High output #1 EOSR07 Pmn Event Output Set 7 7 read-write 0 No effect on output #0 1 High output #1 EOSR08 Pmn Event Output Set 8 8 read-write 0 No effect on output #0 1 High output #1 EOSR09 Pmn Event Output Set 9 9 read-write 0 No effect on output #0 1 High output #1 EOSR10 Pmn Event Output Set 10 10 read-write 0 No effect on output #0 1 High output #1 EOSR11 Pmn Event Output Set 11 11 read-write 0 No effect on output #0 1 High output #1 EOSR12 Pmn Event Output Set 12 12 read-write 0 No effect on output #0 1 High output #1 EOSR13 Pmn Event Output Set 13 13 read-write 0 No effect on output #0 1 High output #1 EOSR14 Pmn Event Output Set 14 14 read-write 0 No effect on output #0 1 High output #1 EOSR15 Pmn Event Output Set 15 15 read-write 0 No effect on output #0 1 High output #1 PORT2 Pmn Pin FunctionPort 2 Control RegistersPmn Pin Function Control Register 0x40080040 PORT3 Pmn Pin FunctionPort 3 Control RegistersPmn Pin Function Control Register 0x40080060 PORT4 Pmn Pin FunctionPort 4 Control RegistersPmn Pin Function Control Register 0x40080080 PORT5 Pmn Pin FunctionPort 5 Control RegistersPmn Pin Function Control Register 0x400800A0 PORT8 Pmn Pin FunctionPort 8 Control RegistersPmn Pin Function Control Register 0x40080100 PFS Control Register 0x40080800 0x00 31 registers 0x20 4 registers 0x34 71 registers 0x80 8 registers 0x94 19 registers 0xB0 11 registers 0xC0 23 registers 0x100 19 registers 0x11C 23 registers 0x140 4 registers 0x200 11 registers 0x503 1 registers 0x505 1 registers 0x50C 1 registers 0x510 12 registers 0x520 2 registers 4 0x4 0-3 P00%sPFS Port 00%s Pin Function Select Register 0x000 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 4 0x4 0-3 P00%sPFS_HA Port 00%s Pin Function Select Register P00%sPFS 0x002 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 4 0x4 0-3 P00%sPFS_BY Port 00%s Pin Function Select Register P00%sPFS 0x003 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 3 0x4 4-6 P00%sPFS Port 00%s Pin Function Select Register 0x010 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 3 0x4 4-6 P00%sPFS_HA Port 00%s Pin Function Select Register P00%sPFS 0x012 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 3 0x4 4-6 P00%sPFS_BY Port 00%s Pin Function Select Register P00%sPFS 0x013 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 P008PFS Port 008 Pin Function Select Register 0x020 32 read-write 0x00010410 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P008PFS_HA Port 008 Pin Function Select Register P008PFS 0x022 16 read-write 0x0410 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 P008PFS_BY Port 008 Pin Function Select Register P008PFS 0x023 8 read-write 0x10 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 3 0x4 13-15 P0%sPFS Port 0%s Pin Function Select Register 0x034 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 3 0x4 13-15 P0%sPFS_HA Port 0%s Pin Function Select Register P0%sPFS 0x036 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 3 0x4 13-15 P0%sPFS_BY Port 0%s Pin Function Select Register P0%sPFS 0x037 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 2 0x4 0-1 P10%sPFS Port 10%s Pin Function Select Register 0x040 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 2 0x4 0-1 P10%sPFS_HA Port 10%s Pin Function Select Register P10%sPFS 0x042 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 2 0x4 0-1 P10%sPFS_BY Port 10%s Pin Function Select Register P10%sPFS 0x043 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 8 0x4 2-9 P10%sPFS Port 10%s Pin Function Select Register 0x048 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 8 0x4 2-9 P10%sPFS_HA Port 10%s Pin Function Select Register P10%sPFS 0x04A 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 8 0x4 2-9 P10%sPFS_BY Port 10%s Pin Function Select Register P10%sPFS 0x04B 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 4 0x4 10-13 P1%sPFS Port 1%s Pin Function Select Register 0x068 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 4 0x4 10-13 P1%sPFS_HA Port 1%s Pin Function Select Register P1%sPFS 0x06A 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 4 0x4 10-13 P1%sPFS_BY Port 1%s Pin Function Select Register P1%sPFS 0x06B 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 P200PFS Port 200 Pin Function Select Register 0x080 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P200PFS_HA Port 200 Pin Function Select Register P200PFS 0x082 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 P200PFS_BY Port 200 Pin Function Select Register P200PFS 0x083 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 P201PFS Port 201 Pin Function Select Register 0x084 32 read-write 0x00000010 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P201PFS_HA Port 201 Pin Function Select Register P201PFS 0x086 16 read-write 0x0010 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 P201PFS_BY Port 201 Pin Function Select Register P201PFS 0x087 8 read-write 0x10 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 4 0x4 5-8 P20%sPFS Port 20%s Pin Function Select Register 0x094 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 4 0x4 5-8 P20%sPFS_HA Port 20%s Pin Function Select Register P20%sPFS 0x096 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 4 0x4 5-8 P20%sPFS_BY Port 20%s Pin Function Select Register P20%sPFS 0x097 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 2 0x4 12-13 P2%sPFS Port 2%s Pin Function Select Register 0x0B0 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 2 0x4 12-13 P2%sPFS_HA Port 2%s Pin Function Select Register P2%sPFS 0x0B2 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 2 0x4 12-13 P2%sPFS_BY Port 2%s Pin Function Select Register P2%sPFS 0x0B3 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 P300PFS Port 300 Pin Function Select Register 0x0C0 32 read-write 0x00010010 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P300PFS_HA Port 300 Pin Function Select Register P300PFS 0x0C2 16 read-write 0x0010 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 P300PFS_BY Port 300 Pin Function Select Register P300PFS 0x0C3 8 read-write 0x10 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 4 0x4 1-4 P30%sPFS Port 30%s Pin Function Select Register 0x0C4 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 4 0x4 1-4 P30%sPFS_HA Port 30%s Pin Function Select Register P30%sPFS 0x0C6 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 4 0x4 1-4 P30%sPFS_BY Port 30%s Pin Function Select Register P30%sPFS 0x0C7 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 4 0x4 0-3 P40%sPFS Port 40%s Pin Function Select Register 0x100 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 4 0x4 0-3 P40%sPFS_HA Port 40%s Pin Function Select Register P40%sPFS 0x102 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 4 0x4 0-3 P40%sPFS_BY Port 40%s Pin Function Select Register P40%sPFS 0x103 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 3 0x4 7-9 P40%sPFS Port 40%s Pin Function Select Register 0x11C 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 3 0x4 7-9 P40%sPFS_HA Port 40%s Pin Function Select Register P40%sPFS 0x11E 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 3 0x4 7-9 P40%sPFS_BY Port 40%s Pin Function Select Register P40%sPFS 0x11F 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 2 0x4 10-11 P4%sPFS Port 4%s Pin Function Select Register 0x128 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 2 0x4 10-11 P4%sPFS_HA Port 4%s Pin Function Select Register P4%sPFS 0x12A 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 2 0x4 10-11 P4%sPFS_BY Port 4%s Pin Function Select Register P4%sPFS 0x12B 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 P500PFS Port 500 Pin Function Select Register 0x140 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P500PFS_HA Port 500 Pin Function Select Register P500PFS 0x142 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 P500PFS_BY Port 500 Pin Function Select Register P500PFS 0x143 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 2 0x4 14-15 P80%sPFS Port 80%s Pin Function Select Register 0x200 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 2 0x4 14-15 P80%sPFS_HA Port 80%s Pin Function Select Register P80%sPFS 0x202 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 2 0x4 14-15 P80%sPFS_BY Port 80%s Pin Function Select Register P80%sPFS 0x203 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PWPR Write-Protect Register 0x503 8 read-write 0x80 0xff PFSWE PmnPFS Register Write Enable 6 6 read-write 0 Writing to the PmnPFS register is disabled #0 1 Writing to the PmnPFS register is enabled #1 B0WI PFSWE Bit Write Disable 7 7 read-write 0 Writing to the PFSWE bit is enabled #0 1 Writing to the PFSWE bit is disabled #1 PWPRS Write-Protect Register for Secure 0x505 8 read-write 0x80 0xff PFSWE PmnPFS Register Write Enable 6 6 read-write 0 Disable writes to the PmnPFS register #0 1 Enable writes to the PmnPFS register #1 B0WI PFSWE Bit Write Disable 7 7 read-write 0 Enable writes the PFSWE bit #0 1 Disable writes to the PFSWE bit #1 PFI3C RI3C Slope Control Register 0x50C 8 read-write 0x00 0xff I3CSLOPE0 I3C mode slope control bit 0 0 read-write 0 I3C mode slope control disable #0 1 I3C mode slope control enable #1 6 0x002 0-5 P%sSAR Port Security Attribution register 0x510 16 read-write 0xffff 0xffff PMNSA Pmn Security Attribution 0 15 read-write 0 Secure #0 1 Non Secure #1 P8SAR Port Security Attribution register 0x520 16 read-write 0xffff 0xffff PMNSA Pmn Security Attribution 0 15 read-write 0 Secure #0 1 Non Secure #1 ELC Event Link Controller 0x40082000 0x00 1 registers 0x02 4 registers 0x10 40 registers 0x40 24 registers 0x6C 2 registers 0x74 2 registers 0x78 2 registers 0x7C 2 registers ELCR Event Link Controller Register 0x00 8 read-write 0x00 0xff ELCON All Event Link Enable 7 7 read-write 0 ELC function is disabled. #0 1 ELC function is enabled. #1 2 0x02 0-1 ELSEGR%s Event Link Software Event Generation Register %s 0x02 8 read-write 0x80 0xff SEG Software Event Generation 0 0 write-only 0 Normal operation #0 1 Software event is generated. #1 WE SEG Bit Write Enable 6 6 read-write 0 Write to SEG bit disabled. #0 1 Write to SEG bit enabled. #1 WI ELSEGR Register Write Disable 7 7 write-only 0 Write to ELSEGR register enabled. #0 1 Write to ELSEGR register disabled. #1 10 0x04 0-9 ELSR%s Event Link Setting Register %s 0x10 16 read-write 0x0000 0xffff ELS Event Link Select 0 8 read-write 6 0x04 12-17 ELSR%s Event Link Setting Register %s 0x40 16 read-write 0x0000 0xffff ELS Event Link Select 0 8 read-write ELSR23 Event Link Setting Register 23 0x6C 16 read-write 0x0000 0xffff ELS Event Link Select 0 8 read-write ELCSARA Event Link Controller Security Attribution Register A 0x74 16 read-write 0xffff 0xffff ELCR Event Link Controller Register Security Attribution 0 0 read-write 0 Secure #0 1 Non-secure #1 ELSEGR0 Event Link Software Event Generation Register 0 Security Attribution 1 1 read-write 0 Secure #0 1 Non-secure #1 ELSEGR1 Event Link Software Event Generation Register 1 Security Attribution 2 2 read-write 0 Secure #0 1 Non-secure #1 ELCSARB Event Link Controller Security Attribution Register B 0x78 16 read-write 0xffff 0xffff ELSR Event Link Setting Register n Security Attribution 0 15 read-write 0 Secure #0 1 Non-secure #1 ELCSARC Event Link Controller Security Attribution Register C 0x7C 16 read-write 0xffff 0xffff ELSR Event Link Setting Register n Security Attribution (n = 16 to 23) 0 7 read-write 0 Secure #0 1 Non-secure #1 RTC Realtime Clock 0x40083000 0x22 1 registers 0x24 1 registers 0x28 1 registers 0x40 4 registers RCR1 Reset Control Register 1 0x22 8 read-write 0x00 0x0a RCR2 Reset Control Register 2 0x24 8 read-write 0x00 0x0e RESET Software Reset 1 1 read-write 0 In writing: Invalid (writing 0 has no effect) In reading: Software reset has completed. #0 1 In writing: The target registers for software reset are initialized. In reading: Software reset in progress. #1 RCR4 Reset Control Register 4 0x28 8 read-write 0x00 0xfe RCKSEL Count Source Select 0 0 read-write 0 Sub-clock oscillator is selected #0 1 LOCO is selected #1 2 0x02 0-1 RTCCR%s Time Capture Control Register %s 0x40 8 read-write 0x00 0x48 TCEN P402/AGTIO and P403/AGTIO input enable 7 7 read-write 0 AGTIO input disable #0 1 AGTIO input enable #1 IWDT Independent Watchdog Timer 0x40083200 0x00 1 registers 0x04 2 registers IWDTRR IWDT Refresh Register 0x00 8 read-write 0xff 0xff IWDTSR IWDT Status Register 0x04 16 read-write 0x0000 0xffff CNTVAL Down-counter Value 0 13 read-only UNDFF Underflow Flag 14 14 read-write 0 No underflow occurred #0 1 Underflow occurred #1 REFEF Refresh Error Flag 15 15 read-write 0 No refresh error occurred #0 1 Refresh error occurred #1 WDT Watchdog Timer 0x40083400 0x00 1 registers 0x02 5 registers 0x08 1 registers WDTRR WDT Refresh Register 0x00 8 read-write 0xff 0xff WDTCR WDT Control Register 0x02 16 read-write 0x33f3 0xffff TOPS Timeout Period Select 0 1 read-write 00 1024 cycles (0x03FF) #00 01 4096 cycles (0x0FFF) #01 10 8192 cycles (0x1FFF) #10 11 16384 cycles (0x3FFF) #11 CKS Clock Division Ratio Select 4 7 read-write 0x1 PCLKB/4 0x1 0x4 PCLKB/64 0x4 0xF PCLKB/128 0xf 0x6 PCLKB/512 0x6 0x7 PCLKB/2048 0x7 0x8 PCLKB/8192 0x8 Others Setting prohibited true RPES Window End Position Select 8 9 read-write 00 75% #00 01 50% #01 10 25% #10 11 0% (do not specify window end position). #11 RPSS Window Start Position Select 12 13 read-write 00 25% #00 01 50% #01 10 75% #10 11 100% (do not specify window start position). #11 WDTSR WDT Status Register 0x04 16 read-write 0x0000 0xffff CNTVAL Down-Counter Value 0 13 read-only UNDFF Underflow Flag 14 14 read-write 0 No underflow occurred #0 1 Underflow occurred #1 REFEF Refresh Error Flag 15 15 read-write 0 No refresh error occurred #0 1 Refresh error occurred #1 WDTRCR WDT Reset Control Register 0x06 8 read-write 0x80 0xff RSTIRQS WDT Behavior Selection 7 7 read-write 0 Interrupt #0 1 Reset #1 WDTCSTPR WDT Count Stop Control Register 0x08 8 read-write 0x80 0xff SLCSTP Sleep-Mode Count Stop Control Register 7 7 read-write 0 Disable count stop #0 1 Stop count on transition to Sleep mode #1 CAC Clock Frequency Accuracy Measurement Circuit 0x40083600 0x00 5 registers 0x06 6 registers CACR0 CAC Control Register 0 0x00 8 read-write 0x00 0xff CFME Clock Frequency Measurement Enable 0 0 read-write 0 Disable #0 1 Enable #1 CACR1 CAC Control Register 1 0x01 8 read-write 0x00 0xff CACREFE CACREF Pin Input Enable 0 0 read-write 0 Disable #0 1 Enable #1 FMCS Measurement Target Clock Select 1 3 read-write 000 Main clock oscillator #000 001 Sub-clock oscillator #001 010 HOCO clock #010 011 MOCO clock #011 100 LOCO clock #100 101 Peripheral module clock B (PCLKB) #101 110 IWDT-dedicated clock #110 111 Setting prohibited #111 TCSS Timer Count Clock Source Select 4 5 read-write 00 No division #00 01 x 1/4 clock #01 10 x 1/8 clock #10 11 x 1/32 clock #11 EDGES Valid Edge Select 6 7 read-write 00 Rising edge #00 01 Falling edge #01 10 Both rising and falling edges #10 11 Setting prohibited #11 CACR2 CAC Control Register 2 0x02 8 read-write 0x00 0xff RPS Reference Signal Select 0 0 read-write 0 CACREF pin input #0 1 Internal clock (internally generated signal) #1 RSCS Measurement Reference Clock Select 1 3 read-write 000 Main clock oscillator #000 001 Sub-clock oscillator #001 010 HOCO clock #010 011 MOCO clock #011 100 LOCO clock #100 101 Peripheral module clock B (PCLKB) #101 110 IWDT-dedicated clock #110 111 Setting prohibited #111 RCDS Measurement Reference Clock Frequency Division Ratio Select 4 5 read-write 00 x 1/32 clock #00 01 x 1/128 clock #01 10 x 1/1024 clock #10 11 x 1/8192 clock #11 DFS Digital Filter Select 6 7 read-write 00 Disable digital filtering #00 01 Use sampling clock for the digital filter as the frequency measuring clock #01 10 Use sampling clock for the digital filter as the frequency measuring clock divided by 4 #10 11 Use sampling clock for the digital filter as the frequency measuring clock divided by 16. #11 CAICR CAC Interrupt Control Register 0x03 8 read-write 0x00 0xff FERRIE Frequency Error Interrupt Request Enable 0 0 read-write 0 Disable #0 1 Enable #1 MENDIE Measurement End Interrupt Request Enable 1 1 read-write 0 Disable #0 1 Enable #1 OVFIE Overflow Interrupt Request Enable 2 2 read-write 0 Disable #0 1 Enable #1 FERRFCL FERRF Clear 4 4 write-only 0 No effect #0 1 The CASTR.FERRF flag is cleared #1 MENDFCL MENDF Clear 5 5 write-only 0 No effect #0 1 The CASTR.MENDF flag is cleared #1 OVFFCL OVFF Clear 6 6 write-only 0 No effect #0 1 The CASTR.OVFF flag is cleared. #1 CASTR CAC Status Register 0x04 8 read-only 0x00 0xff FERRF Frequency Error Flag 0 0 read-only 0 Clock frequency is within the allowable range #0 1 Clock frequency has deviated beyond the allowable range (frequency error). #1 MENDF Measurement End Flag 1 1 read-only 0 Measurement is in progress #0 1 Measurement ended #1 OVFF Overflow Flag 2 2 read-only 0 Counter has not overflowed #0 1 Counter overflowed #1 CAULVR CAC Upper-Limit Value Setting Register 0x06 16 read-write 0x0000 0xffff CALLVR CAC Lower-Limit Value Setting Register 0x08 16 read-write 0x0000 0xffff CACNTBR CAC Counter Buffer Register 0x0A 16 read-only 0x0000 0xffff MSTP Module Stop Control 0x40084000 0x00 20 registers MSTPCRA Module Stop Control Register A 0x000 32 read-write 0xffbfff7e 0xffffffff MSTPA0 SRAM0 Module Stop 0 0 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPA22 DMA Controller/Data Transfer Controller Module Stop 22 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRB Module Stop Control Register B 0x004 32 read-write 0xffffffff 0xffffffff MSTPB4 I3C Bus Interface 0 Module Stop 4 4 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB18 Serial Peripheral Interface 1 Module Stop 18 18 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB19 Serial Peripheral Interface 0 Module Stop 19 19 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB22 Serial Communication Interface 9 Module Stop 22 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB31 Serial Communication Interface 0 Module Stop 31 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRC Module Stop Control Register C 0x008 32 read-write 0xffffffff 0xffffffff MSTPC0 Clock Frequency Accuracy Measurement Circuit Module Stop 0 0 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC1 Cyclic Redundancy Check Calculator Module Stop 1 1 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC13 Data Operation Circuit Module Stop 13 13 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC14 Event Link Controller Module Stop 14 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC20 Trigonometric Function Unit Module Stop 20 20 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC27 CANFD Module Stop 27 27 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC28 Random Number Generator Module Stop 28 28 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRD Module Stop Control Register D 0x00C 32 read-write 0xffffffff 0xffffffff MSTPD2 Low Power Asynchronous General Purpose Timer 1 Module Stop 2 2 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD3 Low Power Asynchronous General Purpose Timer 0 Module Stop 3 3 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD11 Port Output Enable for GPT Group D Module Stop 11 11 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD12 Port Output Enable for GPT Group C Module Stop 12 12 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD13 Port Output Enable for GPT Group B Module Stop 13 13 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD14 Port Output Enable for GPT Group A Module Stop 14 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD16 12-bit A/D Converter 0 Module Stop 16 16 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD20 12-bit D/A Converter Module Stop 20 20 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD22 Temperature Sensor Module Stop 22 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD26 High-Speed Analog Comparator 2 Module Stop 26 26 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD27 High-Speed Analog Comparator 1 Module Stop 27 27 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD28 High-Speed Analog Comparator 0 Module Stop 28 28 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRE Module Stop Control Register E 0x010 32 read-write 0xffffffff 0xffffffff MSTPE26 GPT5 Module Stop 26 26 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE27 GPT4 Module Stop 27 27 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE28 GPT3 Module Stop 28 28 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE29 GPT2 Module Stop 29 29 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE30 GPT1 Module Stop 30 30 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE31 GPT0 Module Stop 31 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 POEG Port Output Enable Module for GPT 0x4008A000 0x00 4 registers 0x100 4 registers 0x200 4 registers 0x300 4 registers POEGGA POEG Group A Setting Register 0x000 32 read-write 0x00000000 0xffffffff PIDF Port Input Detection Flag 0 0 read-write 0 No output-disable request from the GTETRGn pin occurred #0 1 Output-disable request from the GTETRGn pin occurred. #1 IOCF Detection Flag for GPT Output-Disable Request 1 1 read-write 0 No output-disable request from GPT or comparator interrupt occurred. #0 1 Output-disable request from GPT or comparator interrupt occurred. #1 OSTPF Oscillation Stop Detection Flag 2 2 read-write 0 No output-disable request from oscillation stop detection occurred #0 1 Output-disable request from oscillation stop detection occurred #1 SSF Software Stop Flag 3 3 read-write 0 No output-disable request from software occurred #0 1 Output-disable request from software occurred #1 PIDE Port Input Detection Enable 4 4 read-write 0 Disable output-disable requests from the GTETRGn pins #0 1 Enable output-disable requests from the GTETRGn pins #1 IOCE Enable for GPT Output-Disable Request 5 5 read-write 0 Disable output-disable requests from GPT #0 1 Enable output-disable requests from GPT #1 OSTPE Oscillation Stop Detection Enable 6 6 read-write 0 Disable output-disable requests from oscillation stop detection #0 1 Enable output-disable requests from oscillation stop detection #1 CDRE0 8 8 read-write 0 Comparator 0 disable requests disabled #0 1 Comparator 0 disable requests enabled #1 CDRE1 9 9 read-write 0 Comparator 1 disable requests disabled #0 1 Comparator 1 disable requests enabled #1 CDRE2 10 10 read-write 0 Comparator 2 disable requests disabled #0 1 Comparator 2 disable requests enabled #1 ST GTETRGn Input Status Flag 16 16 read-only 0 GTETRGn input after filtering was 0 #0 1 GTETRGn input after filtering was 1 #1 INV GTETRGn Input Reverse 28 28 read-write 0 Input GTETRGn as-is #0 1 Input GTETRGn in reverse #1 NFEN Noise Filter Enable 29 29 read-write 0 Disable noise filtering #0 1 Enable noise filtering #1 NFCS Noise Filter Clock Select 30 31 read-write 00 Sample GTETRGn pin input level three times every PCLKB #00 01 Sample GTETRGn pin input level three times every PCLKB/8 #01 10 Sample GTETRGn pin input level three times every PCLKB/32 #10 11 Sample GTETRGn pin input level three times every PCLKB/128 #11 POEGGB POEG Group B Setting Register 0x100 32 read-write 0x00000000 0xffffffff PIDF Port Input Detection Flag 0 0 read-write 0 No output-disable request from the GTETRGn pin occurred #0 1 Output-disable request from the GTETRGn pin occurred. #1 IOCF Detection Flag for GPT Output-Disable Request 1 1 read-write 0 No output-disable request from GPT or comparator interrupt occurred. #0 1 Output-disable request from GPT or comparator interrupt occurred. #1 OSTPF Oscillation Stop Detection Flag 2 2 read-write 0 No output-disable request from oscillation stop detection occurred #0 1 Output-disable request from oscillation stop detection occurred #1 SSF Software Stop Flag 3 3 read-write 0 No output-disable request from software occurred #0 1 Output-disable request from software occurred #1 PIDE Port Input Detection Enable 4 4 read-write 0 Disable output-disable requests from the GTETRGn pins #0 1 Enable output-disable requests from the GTETRGn pins #1 IOCE Enable for GPT Output-Disable Request 5 5 read-write 0 Disable output-disable requests from GPT #0 1 Enable output-disable requests from GPT #1 OSTPE Oscillation Stop Detection Enable 6 6 read-write 0 Disable output-disable requests from oscillation stop detection #0 1 Enable output-disable requests from oscillation stop detection #1 CDRE0 8 8 read-write 0 Comparator 0 disable requests disabled #0 1 Comparator 0 disable requests enabled #1 CDRE1 9 9 read-write 0 Comparator 1 disable requests disabled #0 1 Comparator 1 disable requests enabled #1 CDRE2 10 10 read-write 0 Comparator 2 disable requests disabled #0 1 Comparator 2 disable requests enabled #1 ST GTETRGn Input Status Flag 16 16 read-only 0 GTETRGn input after filtering was 0 #0 1 GTETRGn input after filtering was 1 #1 INV GTETRGn Input Reverse 28 28 read-write 0 Input GTETRGn as-is #0 1 Input GTETRGn in reverse #1 NFEN Noise Filter Enable 29 29 read-write 0 Disable noise filtering #0 1 Enable noise filtering #1 NFCS Noise Filter Clock Select 30 31 read-write 00 Sample GTETRGn pin input level three times every PCLKB #00 01 Sample GTETRGn pin input level three times every PCLKB/8 #01 10 Sample GTETRGn pin input level three times every PCLKB/32 #10 11 Sample GTETRGn pin input level three times every PCLKB/128 #11 POEGGC POEG Group C Setting Register 0x200 32 read-write 0x00000000 0xffffffff PIDF Port Input Detection Flag 0 0 read-write 0 No output-disable request from the GTETRGn pin occurred #0 1 Output-disable request from the GTETRGn pin occurred. #1 IOCF Detection Flag for GPT Output-Disable Request 1 1 read-write 0 No output-disable request from GPT or comparator interrupt occurred. #0 1 Output-disable request from GPT or comparator interrupt occurred. #1 OSTPF Oscillation Stop Detection Flag 2 2 read-write 0 No output-disable request from oscillation stop detection occurred #0 1 Output-disable request from oscillation stop detection occurred #1 SSF Software Stop Flag 3 3 read-write 0 No output-disable request from software occurred #0 1 Output-disable request from software occurred #1 PIDE Port Input Detection Enable 4 4 read-write 0 Disable output-disable requests from the GTETRGn pins #0 1 Enable output-disable requests from the GTETRGn pins #1 IOCE Enable for GPT Output-Disable Request 5 5 read-write 0 Disable output-disable requests from GPT #0 1 Enable output-disable requests from GPT #1 OSTPE Oscillation Stop Detection Enable 6 6 read-write 0 Disable output-disable requests from oscillation stop detection #0 1 Enable output-disable requests from oscillation stop detection #1 CDRE0 8 8 read-write 0 Comparator 0 disable requests disabled #0 1 Comparator 0 disable requests enabled #1 CDRE1 9 9 read-write 0 Comparator 1 disable requests disabled #0 1 Comparator 1 disable requests enabled #1 CDRE2 10 10 read-write 0 Comparator 2 disable requests disabled #0 1 Comparator 2 disable requests enabled #1 ST GTETRGn Input Status Flag 16 16 read-only 0 GTETRGn input after filtering was 0 #0 1 GTETRGn input after filtering was 1 #1 INV GTETRGn Input Reverse 28 28 read-write 0 Input GTETRGn as-is #0 1 Input GTETRGn in reverse #1 NFEN Noise Filter Enable 29 29 read-write 0 Disable noise filtering #0 1 Enable noise filtering #1 NFCS Noise Filter Clock Select 30 31 read-write 00 Sample GTETRGn pin input level three times every PCLKB #00 01 Sample GTETRGn pin input level three times every PCLKB/8 #01 10 Sample GTETRGn pin input level three times every PCLKB/32 #10 11 Sample GTETRGn pin input level three times every PCLKB/128 #11 POEGGD POEG Group D Setting Register 0x300 32 read-write 0x00000000 0xffffffff PIDF Port Input Detection Flag 0 0 read-write 0 No output-disable request from the GTETRGn pin occurred #0 1 Output-disable request from the GTETRGn pin occurred. #1 IOCF Detection Flag for GPT Output-Disable Request 1 1 read-write 0 No output-disable request from GPT or comparator interrupt occurred. #0 1 Output-disable request from GPT or comparator interrupt occurred. #1 OSTPF Oscillation Stop Detection Flag 2 2 read-write 0 No output-disable request from oscillation stop detection occurred #0 1 Output-disable request from oscillation stop detection occurred #1 SSF Software Stop Flag 3 3 read-write 0 No output-disable request from software occurred #0 1 Output-disable request from software occurred #1 PIDE Port Input Detection Enable 4 4 read-write 0 Disable output-disable requests from the GTETRGn pins #0 1 Enable output-disable requests from the GTETRGn pins #1 IOCE Enable for GPT Output-Disable Request 5 5 read-write 0 Disable output-disable requests from GPT #0 1 Enable output-disable requests from GPT #1 OSTPE Oscillation Stop Detection Enable 6 6 read-write 0 Disable output-disable requests from oscillation stop detection #0 1 Enable output-disable requests from oscillation stop detection #1 CDRE0 8 8 read-write 0 Comparator 0 disable requests disabled #0 1 Comparator 0 disable requests enabled #1 CDRE1 9 9 read-write 0 Comparator 1 disable requests disabled #0 1 Comparator 1 disable requests enabled #1 CDRE2 10 10 read-write 0 Comparator 2 disable requests disabled #0 1 Comparator 2 disable requests enabled #1 ST GTETRGn Input Status Flag 16 16 read-only 0 GTETRGn input after filtering was 0 #0 1 GTETRGn input after filtering was 1 #1 INV GTETRGn Input Reverse 28 28 read-write 0 Input GTETRGn as-is #0 1 Input GTETRGn in reverse #1 NFEN Noise Filter Enable 29 29 read-write 0 Disable noise filtering #0 1 Enable noise filtering #1 NFCS Noise Filter Clock Select 30 31 read-write 00 Sample GTETRGn pin input level three times every PCLKB #00 01 Sample GTETRGn pin input level three times every PCLKB/8 #01 10 Sample GTETRGn pin input level three times every PCLKB/32 #10 11 Sample GTETRGn pin input level three times every PCLKB/128 #11 CANFD_B CANFD 0x400B0000 0x00 16 registers 0x14 160 registers 0xB8 4 registers 0xC0 16 registers 0xD8 4 registers 0x100 20 registers 0x120 268 registers 0x280 256 registers 0x520 604 registers 0x920 680 registers 0xD20 680 registers 0x1120 680 registers 0x1520 680 registers CFDC0NCFG Channel 0 Nominal Bitrate Configuration Register 0x0000 32 read-write 0x00000000 0xffffffff NBRP Channel Nominal Baud Rate Prescaler 0 9 read-write NSJW Resynchronization Jump Width 10 16 read-write NTSEG1 Timing Segment 1 17 24 read-write NTSEG2 Timing Segment 2 25 31 read-write CFDC0CTR Channel 0 Control Register 0x0004 32 read-write 0x00000005 0xffffffff CHMDC Channel Mode Control 0 1 read-write 00 Channel operation mode request #00 01 Channel reset request #01 10 Channel halt request #10 11 Keep current value #11 CSLPR Channel Sleep Request 2 2 read-write 0 Channel sleep request disabled #0 1 Channel sleep request enabled #1 RTBO Return from Bus-Off 3 3 read-write 0 Channel is not forced to return from bus-off #0 1 Channel is forced to return from bus-off #1 BEIE Bus Error Interrupt Enable 8 8 read-write 0 Bus error interrupt disabled #0 1 Bus error interrupt enabled #1 EWIE Error Warning Interrupt Enable 9 9 read-write 0 Error warning interrupt disabled #0 1 Error warning interrupt enabled #1 EPIE Error Passive Interrupt Enable 10 10 read-write 0 Error passive interrupt disabled #0 1 Error passive interrupt enabled #1 BOEIE Bus-Off Entry Interrupt Enable 11 11 read-write 0 Bus-off entry interrupt disabled #0 1 Bus-off entry interrupt enabled #1 BORIE Bus-Off Recovery Interrupt Enable 12 12 read-write 0 Bus-off recovery interrupt disabled #0 1 Bus-off recovery interrupt enabled #1 OLIE Overload Interrupt Enable 13 13 read-write 0 Overload interrupt disabled #0 1 Overload interrupt enabled #1 BLIE Bus Lock Interrupt Enable 14 14 read-write 0 Bus lock interrupt disabled #0 1 Bus lock interrupt enabled #1 ALIE Arbitration Lost Interrupt Enable 15 15 read-write 0 Arbitration lost interrupt disabled #0 1 Arbitration lost interrupt enabled #1 TAIE Transmission Abort Interrupt Enable 16 16 read-write 0 TX abort interrupt disabled #0 1 TX abort interrupt enabled #1 EOCOIE Error Occurrence Counter Overflow Interrupt Enable 17 17 read-write 0 Error occurrence counter overflow interrupt disabled #0 1 Error occurrence counter overflow interrupt enabled #1 SOCOIE Successful Occurrence Counter Overflow Interrupt Enable 18 18 read-write 0 Successful occurrence counter overflow interrupt disabled #0 1 Successful occurrence counter overflow interrupt enabled #1 TDCVFIE Transceiver Delay Compensation Violation Interrupt Enable 19 19 read-write 0 Transceiver delay compensation violation interrupt disabled #0 1 Transceiver delay compensation violation interrupt enabled #1 BOM Channel Bus-Off Mode 21 22 read-write 00 Normal mode (comply with ISO 11898-1) #00 01 Entry to Halt mode automatically at bus-off start #01 10 Entry to Halt mode automatically at bus-off end #10 11 Entry to Halt mode (during bus-off recovery period) by software #11 ERRD Channel Error Display 23 23 read-write 0 Only the first set of error codes displayed #0 1 Accumulated error codes displayed #1 CTME Channel Test Mode Enable 24 24 read-write 0 Channel test mode disabled #0 1 Channel test mode enabled #1 CTMS Channel Test Mode Select 25 26 read-write 00 Basic test mode #00 01 Listen-only mode #01 10 Self-test mode 0 (External loopback mode) #10 11 Self-test mode 1 (Internal loopback mode) #11 BFT Bit Flip Test 30 30 read-write 0 First data bit of reception stream not inverted #0 1 First data bit of reception stream inverted #1 ROM Restricted Operation Mode 31 31 read-write 0 Restricted operation mode disabled #0 1 Restricted operation mode enabled #1 CFDC0STS Channel 0 Status Register 0x0008 32 read-write 0x00000005 0xffffffff CRSTSTS Channel Reset Status 0 0 read-only 0 Channel not in Reset mode #0 1 Channel in Reset mode #1 CHLTSTS Channel Halt Status 1 1 read-only 0 Channel not in Halt mode #0 1 Channel in Halt mode #1 CSLPSTS Channel Sleep Status 2 2 read-only 0 Channel not in Sleep mode #0 1 Channel in Sleep mode #1 EPSTS Channel Error Passive Status 3 3 read-only 0 Channel not in error passive state #0 1 Channel in error passive state #1 BOSTS Channel Bus-Off Status 4 4 read-only 0 Channel not in bus-off state #0 1 Channel in bus-off state #1 TRMSTS Channel Transmit Status 5 5 read-only 0 Channel is not transmitting #0 1 Channel is transmitting #1 RECSTS Channel Receive Status 6 6 read-only 0 Channel is not receiving #0 1 Channel is receiving #1 COMSTS Channel Communication Status 7 7 read-only 0 Channel is not ready for communication #0 1 Channel is ready for communication #1 ESIF Error State Indication Flag 8 8 read-write 0 No CANFD message has been received when the ESI flag was set #0 1 At least one CANFD message was received when the ESI flag was set #1 REC Reception Error Count 16 23 read-only TEC Transmission Error Count 24 31 read-only CFDC0ERFL Channel 0 Error Flag Register 0x000C 32 read-write 0x00000000 0xffffffff BEF Bus Error Flag 0 0 read-write 0 Channel bus error not detected #0 1 Channel bus error detected #1 EWF Error Warning Flag 1 1 read-write 0 Channel error warning not detected #0 1 Channel error warning detected #1 EPF Error Passive Flag 2 2 read-write 0 Channel error passive not detected #0 1 Channel error passive detected #1 BOEF Bus-Off Entry Flag 3 3 read-write 0 Channel bus-off entry not detected #0 1 Channel bus-off entry detected #1 BORF Bus-Off Recovery Flag 4 4 read-write 0 Channel bus-off recovery not detected #0 1 Channel bus-off recovery detected #1 OVLF Overload Flag 5 5 read-write 0 Channel overload not detected #0 1 Channel overload detected #1 BLF Bus Lock Flag 6 6 read-write 0 Channel bus lock not detected #0 1 Channel bus lock detected #1 ALF Arbitration Lost Flag 7 7 read-write 0 Channel arbitration lost not detected #0 1 Channel arbitration lost detected #1 SERR Stuff Error 8 8 read-write 0 Channel stuff error not detected #0 1 Channel stuff error detected #1 FERR Form Error 9 9 read-write 0 Channel form error not detected #0 1 Channel form error detected #1 AERR Acknowledge Error 10 10 read-write 0 Channel acknowledge error not detected #0 1 Channel acknowledge error detected #1 CERR CRC Error 11 11 read-write 0 Channel CRC error not detected #0 1 Channel CRC error detected #1 B1ERR Bit 1 Error 12 12 read-write 0 Channel bit 1 error not detected #0 1 Channel bit 1 error detected #1 B0ERR Bit 0 Error 13 13 read-write 0 Channel bit 0 error not detected #0 1 Channel bit 0 error detected #1 ADERR Acknowledge Delimiter Error 14 14 read-write 0 Channel acknowledge delimiter error not detected #0 1 Channel acknowledge delimiter error detected #1 CRCREG CRC Register value 16 30 read-only CFDGCFG Global Configuration Register 0x0014 32 read-write 0x00000000 0xffffffff TPRI Transmission Priority 0 0 read-write 0 ID priority #0 1 Message buffer number priority #1 DCE DLC Check Enable 1 1 read-write 0 DLC check disabled #0 1 DLC check enabled #1 DRE DLC Replacement Enable 2 2 read-write 0 DLC replacement disabled #0 1 DLC replacement enabled #1 MME Mirror Mode Enable 3 3 read-write 0 Mirror mode disabled #0 1 Mirror mode enabled #1 DCS Data Link Controller Clock Select 4 4 read-write 0 Internal clean clock #0 1 External clock source connected to CANMCLK pin #1 CMPOC CANFD Message Payload Overflow Configuration 5 5 read-write 0 Message is rejected #0 1 Message payload is cut to fit to configured message size #1 TSP Timestamp Prescaler 8 11 read-write TSSS Timestamp Source Select 12 12 read-write 0 Source clock for timestamp counter is peripheral clock #0 1 Source clock for timestamp counter is bit time clock #1 ITRCP Interval Timer Reference Clock Prescaler 16 31 read-write CFDGCTR Global Control Register 0x0018 32 read-write 0x00000005 0xffffffff GMDC Global Mode Control 0 1 read-write 00 Global operation mode request #00 01 Global reset mode request #01 10 Global halt mode request #10 11 Keep current value #11 GSLPR Global Sleep Request 2 2 read-write 0 Global sleep request disabled #0 1 Global sleep request enabled #1 DEIE DLC Check Interrupt Enable 8 8 read-write 0 DLC check interrupt disabled #0 1 DLC check interrupt enabled #1 MEIE Message Lost Error Interrupt Enable 9 9 read-write 0 Message lost error interrupt disabled #0 1 Message lost error interrupt enabled #1 THLEIE TX History List Entry Lost Interrupt Enable 10 10 read-write 0 TX history list entry lost interrupt disabled #0 1 TX history list entry lost interrupt enabled #1 CMPOFIE CANFD Message Payload Overflow Flag Interrupt Enable 11 11 read-write 0 CANFD message payload overflow flag interrupt disabled #0 1 CANFD message payload overflow flag interrupt enabled #1 TSRST Timestamp Reset 16 16 read-write 0 Timestamp not reset #0 1 Timestamp reset #1 CFDGSTS Global Status Register 0x001C 32 read-only 0x0000000d 0xffffffff GRSTSTS Global Reset Status 0 0 read-only 0 Not in Reset mode #0 1 In Reset mode #1 GHLTSTS Global Halt Status 1 1 read-only 0 Not in Halt mode #0 1 In Halt mode #1 GSLPSTS Global Sleep Status 2 2 read-only 0 Not in Sleep mode #0 1 In Sleep mode #1 GRAMINIT Global RAM Initialization 3 3 read-only 0 RAM initialization is complete #0 1 RAM initialization is ongoing #1 CFDGERFL Global Error Flag Register 0x0020 32 read-write 0x00000000 0xffffffff DEF DLC Error Flag 0 0 read-write 0 DLC error not detected #0 1 DLC error detected #1 MES Message Lost Error Status 1 1 read-only 0 Message lost error not detected #0 1 Message lost error detected #1 THLES TX History List Entry Lost Error Status 2 2 read-only 0 TX history list entry lost error not detected #0 1 TX history list entry lost error detected #1 CMPOF CANFD Message Payload Overflow Flag 3 3 read-write 0 CANFD message payload overflow not detected #0 1 CANFD message payload overflow detected #1 EEF0 ECC Error Flag 16 16 read-write 0 ECC error not detected during TX-SCAN #0 1 ECC error detected during TX-SCAN #1 CFDGTSC Global Timestamp Counter Register 0x0024 32 read-only 0x00000000 0xffffffff TS Timestamp value 0 15 read-only CFDGAFLECTR Global Acceptance Filter List Entry Control Register 0x0028 32 read-write 0x00000000 0xffffffff AFLPN Acceptance Filter List Page Number 0 0 read-write AFLDAE Acceptance Filter List Data Access Enable 8 8 read-write 0 Acceptance Filter List data access disabled #0 1 Acceptance Filter List data access enabled #1 CFDGAFLCFG Global Acceptance Filter List Configuration Register 0x002C 32 read-write 0x00000000 0xffffffff RNC0 Rule Number 16 21 read-write CFDRMNB RX Message Buffer Number Register 0x0030 32 read-write 0x00000000 0xffffffff NRXMB Number of RX Message Buffers 0 5 read-write RMPLS Reception Message Buffer Payload Data Size 8 10 read-write 000 8 bytes #000 001 12 bytes #001 010 16 bytes #010 011 20 bytes #011 100 24 bytes #100 101 32 bytes #101 110 48 bytes #110 111 64 bytes #111 CFDRMND RX Message Buffer New Data Register 0x0034 32 read-write 0x00000000 0xffffffff RMNS RX Message Buffer New Data Status 0 31 read-write 0 New data not stored in corresponding RX message buffer #0 1 New data stored in corresponding RX message buffer #1 CFDRMIEC RX Message Buffer Interrupt Enable Configuration Register 0x0038 32 read-write 0x00000000 0xffffffff RMIEg RX Message Buffer Interrupt Enable 0 31 read-write 0 RX Message Buffer Interrupt disabled for corresponding RX message buffer #0 1 RX Message Buffer Interrupt enabled for corresponding RX message buffer #1 2 0x04 0-1 CFDRFCC%s RX FIFO Configuration/Control Registers %s 0x003C 32 read-write 0x00000000 0xffffffff RFE RX FIFO Enable 0 0 read-write 0 FIFO disabled #0 1 FIFO enabled #1 RFIE RX FIFO Interrupt Enable 1 1 read-write 0 FIFO interrupt generation disabled #0 1 FIFO interrupt generation enabled #1 RFPLS Rx FIFO Payload Data Size Configuration 4 6 read-write 000 8 bytes #000 001 12 bytes #001 010 16 bytes #010 011 20 bytes #011 100 24 bytes #100 101 32 bytes #101 110 48 bytes #110 111 64 bytes #111 RFDC RX FIFO Depth Configuration 8 10 read-write 000 FIFO Depth = 0 message #000 001 FIFO Depth = 4 messages #001 010 FIFO Depth = 8 messages #010 011 FIFO Depth = 16 messages #011 100 FIFO Depth = 32 essages #100 101 FIFO Depth = 48 messages #101 110 Reserved #110 111 Reserved #111 RFIM RX FIFO Interrupt Mode 12 12 read-write 0 Interrupt generated when RX FIFO counter reaches RFIGCV value from values smaller than RFIGCV #0 1 Interrupt generated at the end of every received message storage #1 RFIGCV RX FIFO Interrupt Generation Counter Value 13 15 read-write 000 Interrupt generated when FIFO is 1/8th full #000 001 Interrupt generated when FIFO is 1/4th full #001 010 Interrupt generated when FIFO is 3/8th full #010 011 Interrupt generated when FIFO is 1/2 full #011 100 Interrupt generated when FIFO is 5/8th full #100 101 Interrupt generated when FIFO is 3/4th full #101 110 Interrupt generated when FIFO is 7/8th full #110 111 Interrupt generated when FIFO is full #111 2 0x04 0-1 CFDRFSTS%s RX FIFO Status Registers %s 0x0044 32 read-write 0x00000001 0xffffffff RFEMP RX FIFO Empty 0 0 read-only 0 FIFO not empty #0 1 FIFO empty #1 RFFLL RX FIFO Full 1 1 read-only 0 FIFO not full #0 1 FIFO full #1 RFMLT RX FIFO Message Lost 2 2 read-write 0 No message lost in FIFO #0 1 FIFO message lost #1 RFIF RX FIFO Interrupt Flag 3 3 read-write 0 FIFO interrupt condition not satisfied #0 1 FIFO interrupt condition satisfied #1 RFMC RX FIFO Message Count 8 13 read-only 2 0x04 0-1 CFDRFPCTR%s RX FIFO Pointer Control Registers %s 0x004C 32 write-only 0x00000000 0xffffffff RFPC RX FIFO Pointer Control 0 7 write-only CFDCFCC Common FIFO Configuration/Control Register 0x0054 32 read-write 0x00000000 0xffffffff CFE Common FIFO Enable 0 0 read-write 0 FIFO disabled #0 1 FIFO enabled #1 CFRXIE Common FIFO RX Interrupt Enable 1 1 read-write 0 FIFO interrupt generation disabled for Frame RX #0 1 FIFO interrupt generation enabled for Frame RX #1 CFTXIE Common FIFO TX Interrupt Enable 2 2 read-write 0 FIFO interrupt generation disabled for Frame TX #0 1 FIFO interrupt generation enabled for Frame TX #1 CFPLS Common FIFO Payload Data Size Configuration 4 6 read-write 000 8 bytes #000 001 12 bytes #001 010 16 bytes #010 011 20 bytes #011 100 24 bytes #100 101 32 bytes #101 110 48 bytes #110 111 64 bytes #111 CFM Common FIFO Mode 8 8 read-write 0 RX FIFO mode #0 1 TX FIFO mode #1 CFITSS Common FIFO Interval Timer Source Select 10 10 read-write 0 Reference clock (× 1 / × 10 period) #0 1 Bit time clock of related channel (FIFO is linked to fixed channel) #1 CFITR Common FIFO Interval Timer Resolution 11 11 read-write 0 Reference clock period × 1 #0 1 Reference clock period × 10 #1 CFIM Common FIFO Interrupt Mode 12 12 read-write 0 RX FIFO mode: RX interrupt generated when Common FIFO counter reaches CFIGCV value from a lower value TX FIFO mode: TX interrupt generated when Common FIFO transmits the last message successfully #0 1 RX FIFO mode: RX interrupt generated at the end of every received message storage TX FIFO mode: interrupt generated for every successfully transmitted message #1 CFIGCV Common FIFO Interrupt Generation Counter Value 13 15 read-write 000 Interrupt generated when FIFO is 1/8th full #000 001 Interrupt generated when FIFO is 1/4th full #001 010 Interrupt generated when FIFO is 3/8th full #010 011 Interrupt generated when FIFO is 1/2 full #011 100 Interrupt generated when FIFO is 5/8th full #100 101 Interrupt generated when FIFO is 3/4th full #101 110 Interrupt generated when FIFO is 7/8th full #110 111 Interrupt generated when FIFO is full #111 CFTML Common FIFO TX Message Buffer Link 16 17 read-write CFDC Common FIFO Depth Configuration 21 23 read-write 000 FIFO Depth = 0 message #000 001 FIFO Depth = 4 messages #001 010 FIFO Depth = 8 messages #010 011 FIFO Depth = 16 messages #011 100 FIFO Depth = 32 messages #100 101 FIFO Depth = 48 messages #101 110 FIFO Depth = Reserved #110 111 FIFO Depth = Reserved #111 CFITT Common FIFO Interval Transmission Time 24 31 read-write CFDCFSTS Common FIFO Status Register 0x0058 32 read-write 0x00000001 0xffffffff CFEMP Common FIFO Empty 0 0 read-only 0 FIFO not empty #0 1 FIFO empty #1 CFFLL Common FIFO Full 1 1 read-only 0 FIFO not full #0 1 FIFO full #1 CFMLT Common FIFO Message Lost 2 2 read-write 0 Number of message lost in FIFO #0 1 FIFO message lost #1 CFRXIF Common RX FIFO Interrupt Flag 3 3 read-write 0 FIFO interrupt condition not satisfied after frame reception #0 1 FIFO interrupt condition satisfied after frame reception #1 CFTXIF Common TX FIFO Interrupt Flag 4 4 read-write 0 FIFO interrupt condition not satisfied after frame transmission #0 1 FIFO Interrupt condition satisfied after frame transmission #1 CFMC Common FIFO Message Count 8 13 read-only CFDCFPCTR Common FIFO Pointer Control Register 0x005C 32 write-only 0x00000000 0xffffffff CFPC Common FIFO Pointer Control 0 7 write-only CFDFESTS FIFO Empty Status Register 0x0060 32 read-only 0x00000103 0xffffffff RFXEMP RX FIFO Empty Status 0 1 read-only 0 Corresponding FIFO not empty #0 1 Corresponding FIFO empty #1 CFEMP Common FIFO Empty Status 8 8 read-only 0 Corresponding FIFO not empty #0 1 Corresponding FIFO empty #1 CFDFFSTS FIFO Full Status Register 0x0064 32 read-only 0x00000000 0xffffffff RFXFLL RX FIF0 Full Status 0 1 read-only 0 Corresponding FIFO not full #0 1 Corresponding FIFO full #1 CFFLL Common FIF0 Full Status 8 8 read-only 0 Corresponding FIFO not full #0 1 Corresponding FIFO full #1 CFDFMSTS FIFO Message Lost Status Register 0x0068 32 read-only 0x00000000 0xffffffff RFXMLT RX FIFO Message Lost Status 0 1 read-only 0 Corresponding FIFO Message Lost flag not set #0 1 Corresponding FIFO Message Lost flag set #1 CFMLT Common FIFO Message Lost Status 8 8 read-only 0 Corresponding FIFO Message Lost flag not set #0 1 Corresponding FIFO Message Lost flag set #1 CFDRFISTS RX FIFO Interrupt Flag Status Register 0x006C 32 read-only 0x00000000 0xffffffff RFXIF RX FIFO[x] Interrupt Flag Status 0 1 read-only 0 Corresponding RX FIFO Interrupt flag not set #0 1 Corresponding RX FIFO Interrupt flag set #1 4 0x01 0-3 CFDTMC%s TX Message Buffer Control Registers %s 0x0070 8 read-write 0x00 0xff TMTR TX Message Buffer Transmission Request 0 0 read-write 0 TX Message buffer transmission not requested #0 1 TX message buffer transmission requested #1 TMTAR TX Message Buffer Transmission Abort Request 1 1 read-write 0 TX message buffer transmission request abort not requested #0 1 TX message buffer transmission request abort requested #1 TMOM TX Message Buffer One-shot Mode 2 2 read-write 0 TX message buffer not configured in one-shot mode #0 1 TX message buffer configured in one-shot mode #1 4 0x01 0-3 CFDTMSTS%s TX Message Buffer Status Registers %s 0x0074 8 read-write 0x00 0xff TMTSTS TX Message Buffer Transmission Status 0 0 read-only 0 No on-going transmission #0 1 On-going transmission #1 TMTRF TX Message Buffer Transmission Result Flag 1 2 read-write 00 No result #00 01 Transmission aborted from the TX message buffer #01 10 Transmission successful from the TX message buffer and transmission abort was not requested #10 11 Transmission successful from the TX message buffer and transmission abort was requested #11 TMTRM TX Message Buffer Transmission Request Mirrored 3 3 read-only 0 TX message buffer transmission not requested #0 1 TX message buffer transmission requested #1 TMTARM TX Message Buffer Transmission Abort Request Mirrored 4 4 read-only 0 TX message buffer transmission request abort not requested #0 1 TX message buffer transmission request abort requested #1 CFDTMTRSTS TX Message Buffer Transmission Request Status Register 0x0078 32 read-only 0x00000000 0xffffffff CFDTMTRSTS TX Message Buffer Transmission Request Status 0 3 read-only 0 Transmission not requested for corresponding TX message buffer #0 1 Transmission requested for corresponding TX message buffer #1 CFDTMTARSTS TX Message Buffer Transmission Abort Request Status Register 0x007C 32 read-only 0x00000000 0xffffffff CFDTMTARSTS TX Message Buffer Transmission Abort Request Status 0 3 read-only 0 Transmission abort not requested for corresponding TX message buffer #0 1 Transmission abort requested for corresponding TX message buffer #1 CFDTMTCSTS TX Message Buffer Transmission Completion Status Register 0x0080 32 read-only 0x00000000 0xffffffff CFDTMTCSTS TX Message Buffer Transmission Completion Status 0 3 read-only 0 Transmission not complete for corresponding TX message buffer #0 1 Transmission completed for corresponding TX message buffer #1 CFDTMTASTS TX Message Buffer Transmission Abort Status Register 0x0084 32 read-only 0x00000000 0xffffffff CFDTMTASTS TX Message Buffer Transmission Abort Status 0 3 read-only 0 Transmission not aborted for corresponding TX message buffer #0 1 Transmission aborted for corresponding TX message buffer #1 CFDTMIEC TX Message Buffer Interrupt Enable Configuration Register 0x0088 32 read-write 0x00000000 0xffffffff TMIEg TX Message Buffer Interrupt Enable 0 3 read-write 0 TX message buffer interrupt disabled for corresponding TX message buffer #0 1 TX message buffer interrupt enabled for corresponding TX message buffer #1 CFDTXQCC TX Queue Configuration/Control Register 0x008C 32 read-write 0x00000000 0xffffffff TXQE TX Queue Enable 0 0 read-write 0 TX Queue disabled #0 1 TX Queue enabled #1 TXQTXIE TX Queue TX Interrupt Enable 5 5 read-write 0 TX Queue TX interrupt disabled #0 1 TX Queue TX interrupt enabled #1 TXQIM TX Queue Interrupt Mode 7 7 read-write 0 When the last message is successfully transmitted #0 1 At every successful transmission #1 TXQDC TX Queue Depth Configuration 8 9 read-write 0x00 0 messages 0x00 0x01 Reserved 0x01 0x10 3 messages 0x10 0x11 4 messages 0x11 CFDTXQSTS TX Queue Status Register 0x0090 32 read-write 0x00000001 0xffffffff TXQEMP TX Queue Empty 0 0 read-only 0 TX Queue not empty #0 1 TX Queue empty #1 TXQFLL TX Queue Full 1 1 read-only 0 TX Queue not full #0 1 TX Queue full #1 TXQTXIF TX Queue TX Interrupt Flag 2 2 read-write 0 TX Queue interrupt condition not satisfied after a frame TX #0 1 TX Queue interrupt condition satisfied after a frame TX #1 TXQMC TX Queue Message Count 8 10 read-only CFDTXQPCTR TX Queue Pointer Control Register 0x0094 32 read-write 0x00000000 0xffffffff TXQPC TX Queue Pointer Control 0 7 write-only CFDTHLCC TX History List Configuration/Control Register 0x0098 32 read-write 0x00000000 0xffffffff THLE TX History List Enable 0 0 read-write 0 TX History List disabled #0 1 TX History List enabled #1 THLIE TX History List Interrupt Enable 8 8 read-write 0 TX History List Interrupt disabled #0 1 TX History List Interrupt enabled #1 THLIM TX History List Interrupt Mode 9 9 read-write 0 Interrupt generated if TX History List level reaches ¾ of the TX History List depth #0 1 Interrupt generated for every successfully stored entry #1 THLDTE TX History List Dedicated TX Enable 10 10 read-write 0 TX FIFO + TX Queue #0 1 Flat TX MB + TX FIFO + TX Queue #1 CFDTHLSTS TX History List Status Register 0x009C 32 read-write 0x00000001 0xffffffff THLEMP TX History List Empty 0 0 read-only 0 TX History List not empty #0 1 TX History List empty #1 THLFLL TX History List Full 1 1 read-only 0 TX History List not full #0 1 TX History List full #1 THLELT TX History List Entry Lost 2 2 read-write 0 No entry lost in TX History List #0 1 TX History List entry Lost #1 THLIF TX History List Interrupt Flag 3 3 read-write 0 TX History List interrupt condition not satisfied #0 1 TX History List interrupt condition satisfied #1 THLMC TX History List Message Count 8 11 read-only CFDTHLPCTR TX History List Pointer Control Register 0x00A0 32 write-only 0x00000000 0xffffffff THLPC TX History List Pointer Control 0 7 write-only CFDGTINTSTS Global TX Interrupt Status Register 0x00A4 32 read-only 0x00000000 0xffffffff TSIF0 TX Successful Interrupt Flag 0 0 read-only 0 Channel n TX Successful Interrupt flag not set #0 1 Channel n TX Successful Interrupt flag set #1 TAI0 TX Abort Interrupt Flag 1 1 read-only 0 Channel n TX Abort Interrupt flag not set #0 1 Channel n TX Abort Interrupt flag set #1 TQIF0 TX Queue Interrupt Flag 2 2 read-only 0 Channel n TX Queue Interrupt flag not set #0 1 Channel n TX Queue Interrupt flag set #1 CFTIF0 COM FIFO TX Mode Interrupt Flag 3 3 read-only 0 Channel n COM FIFO TX Mode Interrupt flag not set #0 1 Channel n COM FIFO TX Mode Interrupt flag set #1 THIF0 TX History List Interrupt 4 4 read-only 0 Channel n TX History List Interrupt flag not set #0 1 Channel n TX History List Interrupt flag set #1 CFDGTSTCFG Global Test Configuration Register 0x00A8 32 read-write 0x00000000 0xffffffff RTMPS RAM Test Mode Page Select 16 19 read-write CFDGTSTCTR Global Test Control Register 0x00AC 32 read-write 0x00000000 0xffffffff RTME RAM Test Mode Enable 2 2 read-write 0 RAM test mode disabled #0 1 RAM test mode enabled #1 CFDGFDCFG Global FD Configuration Register 0x00B0 32 read-write 0x00000000 0xffffffff RPED RES Bit Protocol Exception Disable 0 0 read-write 0 Protocol exception event detection enabled #0 1 Protocol exception event detection disabled #1 TSCCFG Timestamp Capture Configuration 8 9 read-write 00 Timestamp capture at the sample point of SOF (start of frame) #00 01 Timestamp capture at frame valid indication #01 10 Timestamp capture at the sample point of RES bit #10 11 Reserved #11 CFDGLOCKK Global Lock Key Register 0x00B8 32 write-only 0x00000000 0xffffffff LOCK Lock Key 0 15 write-only CFDGAFLIGNENT Global AFL Ignore Entry Register 0x00C0 32 read-write 0x00000000 0xffffffff IRN Ignore Rule Number 0 4 read-write CFDGAFLIGNCTR Global AFL Ignore Control Register 0x00C4 32 read-write 0x00000000 0xffffffff IREN Ignore Rule Enable 0 0 read-write 0 AFL entry number is not ignored #0 1 AFL entry number is ignored #1 KEY Key Code 8 15 write-only CFDCDTCT DMA Transfer Control Register 0x00C8 32 read-write 0x00000000 0xffffffff RFDMAE0 DMA Transfer Enable for RXFIFO 0 0 0 read-write 0 DMA transfer request disabled #0 1 DMA transfer request enabled #1 RFDMAE1 DMA Transfer Enable for RXFIFO 1 1 1 read-write 0 DMA transfer request disabled #0 1 DMA transfer request enabled #1 CFDMAE DMA Transfer Enable for Common FIFO 0 8 8 read-write 0 DMA transfer request disabled #0 1 DMA transfer request enabled #1 CFDCDTSTS DMA Transfer Status Register 0x00CC 32 read-only 0x00000000 0xffffffff RFDMASTS0 DMA Transfer Status for RX FIFO 0 0 0 read-only 0 DMA transfer stopped #0 1 DMA transfer on going #1 RFDMASTS1 DMA Transfer Status for RX FIFO 1 1 1 read-only 0 DMA transfer stopped #0 1 DMA transfer on going #1 CFDMASTS DMA Transfer Status only for Common FIFO 8 8 read-only 0 DMA transfer stopped #0 1 DMA transfer on going #1 CFDGRSTC Global SW reset Register 0x00D8 32 read-write 0x00000000 0xffffffff SRST SW Reset 0 0 read-write 0 Normal state #0 1 SW reset state #1 KEY Key Code 8 15 write-only CFDC0DCFG Channel 0 Data Bitrate Configuration Register 0x0100 32 read-write 0x00000000 0xffffffff DBRP Channel Data Baud Rate Prescaler 0 7 read-write DTSEG1 Timing Segment 1 8 12 read-write DTSEG2 Timing Segment 2 16 19 read-write DSJW Resynchronization Jump Width 24 27 read-write CFDC0FDCFG Channel 0 CANFD Configuration Register 0x0104 32 read-write 0x00000000 0xffffffff EOCCFG Error Occurrence Counter Configuration 0 2 read-write 000 All transmitter or receiver CAN frames #000 001 All transmitter CAN frames #001 010 All receiver CAN frames #010 011 Reserved #011 100 Only transmitter or receiver CANFD data-phase (fast bits) #100 101 Only transmitter CANFD data-phase (fast bits) #101 110 Only receiver CANFD data-phase (fast bits) #110 111 Reserved #111 TDCOC Transceiver Delay Compensation Offset Configuration 8 8 read-write 0 Measured + offset #0 1 Offset-only #1 TDCE Transceiver Delay Compensation Enable 9 9 read-write 0 Transceiver delay compensation disabled #0 1 Transceiver delay compensation enabled #1 ESIC Error State Indication Configuration 10 10 read-write 0 The ESI bit in the frame represents the error state of the node itself #0 1 The ESI bit in the frame represents the error state of the message buffer if the node itself is not in error passive. If the node is in error passive, then the ESI bit is driven by the node itself. #1 TDCO Transceiver Delay Compensation Offset 16 23 read-write FDOE FD-Only Enable 28 28 read-write 0 FD-only mode disabled #0 1 FD-only mode enabled #1 REFE RX Edge Filter Enable 29 29 read-write 0 RX edge filter disabled #0 1 RX edge filter enabled #1 CLOE Classical CAN Enable 30 30 read-write 0 Classical CAN mode disabled #0 1 Classical CAN mode enabled #1 CFDC0FDCTR Channel 0 CANFD Control Register 0x0108 32 read-write 0x00000000 0xffffffff EOCCLR Error Occurrence Counter Clear 0 0 read-write 0 No error occurrence counter clear #0 1 Clear error occurrence counter #1 SOCCLR Successful Occurrence Counter Clear 1 1 read-write 0 No successful occurrence counter clear #0 1 Clear successful occurrence counter #1 CFDC0FDSTS Channel 0 CANFD Status Register 0x010C 32 read-write 0x00000000 0xffffffff TDCR Transceiver Delay Compensation Result 0 7 read-only EOCO Error Occurrence Counter Overflow 8 8 read-write 0 Error occurrence counter has not overflowed #0 1 Error occurrence counter has overflowed #1 SOCO Successful Occurrence Counter Overflow 9 9 read-write 0 Successful occurrence counter has not overflowed #0 1 Successful occurrence counter has overflowed #1 TDCVF Transceiver Delay Compensation Violation Flag 15 15 read-write 0 Transceiver delay compensation violation has not occurred #0 1 Transceiver delay compensation violation has occurred #1 EOC Error Occurrence Counter 16 23 read-only SOC Successful occurrence counter 24 31 read-only CFDC0FDCRC Channel 0 CANFD CRC Register 0x0110 32 read-write 0x00000000 0xffffffff CRCREG CRC Register value 0 20 read-only SCNT Stuff bit count 24 27 read-only 16 0x0010 1-16 CFDGAFLID%s Global Acceptance Filter List ID Registers 0x0120 32 read-write 0x00000000 0xffffffff GAFLID Global Acceptance Filter List Entry ID Field 0 28 read-write GAFLLB Global Acceptance Filter List Entry Loopback Configuration 29 29 read-write 0 Global Acceptance Filter List entry ID for acceptance filtering with attribute RX #0 1 Global Acceptance Filter List entry ID for acceptance filtering with attribute TX #1 GAFLRTR Global Acceptance Filter List Entry RTR Field 30 30 read-write 0 Data frame #0 1 Remote frame #1 GAFLIDE Global Acceptance Filter List Entry IDE Field 31 31 read-write 0 Standard identifier of rule entry ID is valid for acceptance filtering #0 1 Extended identifier of rule entry ID is valid for acceptance filtering #1 16 0x0010 1-16 CFDGAFLM%s Global Acceptance Filter List Mask Registers 0x0124 32 read-write 0x00000000 0xffffffff GAFLIDM Global Acceptance Filter List ID Mask Field 0 28 read-write GAFLIFL1 Global Acceptance Filter List Information Label 1 29 29 read-write GAFLRTRM Global Acceptance Filter List Entry RTR Mask 30 30 read-write 0 RTR bit is not used for ID matching #0 1 RTR bit is used for ID matching #1 GAFLIDEM Global Acceptance Filter List IDE Mask 31 31 read-write 0 IDE bit is not used for ID matching #0 1 IDE bit is used for ID matching #1 16 0x0010 1-16 CFDGAFLP0%s Global Acceptance Filter List Pointer 0 Registers 0x0128 32 read-write 0x00000000 0xffffffff GAFLDLC Global Acceptance Filter List DLC Field 0 3 read-write GAFLIFL0 Global Acceptance Filter List Information Label 0 7 7 read-write GAFLRMDP Global Acceptance Filter List RX Message Buffer Direction Pointer 8 12 read-write GAFLRMV Global Acceptance Filter List RX Message Buffer Valid 15 15 read-write 0 Single message buffer direction pointer is invalid #0 1 Single message buffer direction pointer is valid #1 GAFLPTR Global Acceptance Filter List Pointer 16 31 read-write 16 0x0010 1-16 CFDGAFLP1%s Global Acceptance Filter List Pointer 1 Registers 0x012C 32 read-write 0x00000000 0xffffffff GAFLFDP0 Global Acceptance Filter List FIFO Direction Pointer 0 0 read-write 0 Disable RX FIFO 0 as target for reception #0 1 Enable RX FIFO 0 as target for reception #1 GAFLFDP1 Global Acceptance Filter List FIFO Direction Pointer 1 1 read-write 0 Disable RX FIFO 1 as target for reception #0 1 Enable RX FIFO 1 as target for reception #1 GAFLFDP8 Global Acceptance Filter List FIFO Direction Pointer 8 8 read-write 0 Disable Common FIFO as target for reception #0 1 Enable Common FIFO as target for reception #1 64 0x0004 0-63 CFDRPGACC%s RAM Test Page Access Registers %s 0x0280 32 read-write 0x00000000 0xffffffff RDTA RAM Data Test Access 0 31 read-write 2 0x004C 0-1 CFDRFID%s RX FIFO Access ID Register %s 0x0520 32 read-only 0x00000000 0xffffffff RFID RX FIFO Buffer ID Field 0 28 read-only RFRTR RX FIFO Buffer RTR bit 30 30 read-only 0 Data frame #0 1 Remote frame #1 RFIDE RX FIFO Buffer IDE bit 31 31 read-only 0 STD-ID has been received #0 1 EXT-ID has been received #1 2 0x004C 0-1 CFDRFPTR%s RX FIFO Access Pointer Register %s 0x0524 32 read-only 0x00000000 0xffffffff RFTS RX FIFO Timestamp Value 0 15 read-only RFDLC RX FIFO Buffer DLC Field 28 31 read-only 2 0x004C 0-1 CFDRFFDSTS%s RX FIFO Access CANFD Status Register %s 0x0528 32 read-only 0x00000000 0xffffffff RFESI Error State Indicator bit 0 0 read-only 0 CANFD frame received from error active node #0 1 CANFD frame received from error passive node #1 RFBRS Bit Rate Switch bit 1 1 read-only 0 CANFD frame received with no bit rate switch #0 1 CANFD frame received with bit rate switch #1 RFFDF CAN FD Format bit 2 2 read-only 0 Non CANFD frame received #0 1 CANFD frame received #1 RFIFL RX FIFO Buffer Information Label Field 8 9 read-only CFDRFPTR RX FIFO Buffer Pointer Field 16 31 read-only 2 0x04C 0-1 CFDRFDF%s_0 RX FIFO Access Data Field 0 Register %s 0x052C 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_1 RX FIFO Access Data Field 1 Register %s 0x0530 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_2 RX FIFO Access Data Field 2 Register %s 0x0534 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_3 RX FIFO Access Data Field 3 Register %s 0x0538 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_4 RX FIFO Access Data Field 4 Register %s 0x053C 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_5 RX FIFO Access Data Field 5 Register %s 0x0540 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_6 RX FIFO Access Data Field 6 Register %s 0x0544 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_7 RX FIFO Access Data Field 7 Register %s 0x0548 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_8 RX FIFO Access Data Field 8 Register %s 0x054C 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_9 RX FIFO Access Data Field 9 Register %s 0x0550 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_10 RX FIFO Access Data Field 10 Register %s 0x0554 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_11 RX FIFO Access Data Field 11 Register %s 0x0558 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_12 RX FIFO Access Data Field 12 Register %s 0x055C 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_13 RX FIFO Access Data Field 13 Register %s 0x0560 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_14 RX FIFO Access Data Field 14 Register %s 0x0564 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_15 RX FIFO Access Data Field 15 Register %s 0x0568 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only CFDCFID Common FIFO Access ID Register 0x05B8 32 read-write 0x00000000 0xffffffff CFID Common FIFO Buffer ID Field 0 28 read-write THLEN THL Entry enable 29 29 read-write 0 Entry will not be stored in THL after successful TX. #0 1 Entry will be stored in THL after successful TX. #1 CFRTR Common FIFO Buffer RTR Bit 30 30 read-write 0 Data Frame #0 1 Remote Frame #1 CFIDE Common FIFO Buffer IDE Bit 31 31 read-write 0 STD-ID will be transmitted or has been received #0 1 EXT-ID will be transmitted or has been received #1 CFDCFPTR Common FIFO Access Pointer Register 0x05BC 32 read-write 0x00000000 0xffffffff CFTS Common FIFO Timestamp Value 0 15 read-write CFDLC Common FIFO Buffer DLC Field 28 31 read-write CFDCFFDCSTS Common FIFO Access CANFD Control/Status Register 0x05C0 32 read-write 0x00000000 0xffffffff CFESI Error State Indicator bit 0 0 read-write 0 CANFD frame received or to transmit by error active node #0 1 CANFD frame received or to transmit by error passive node #1 CFBRS Bit Rate Switch bit 1 1 read-write 0 CANFD frame received or to transmit with no bit rate switch #0 1 CANFD frame received or to transmit with bit rate switch #1 CFFDF CAN FD Format bit 2 2 read-write 0 Non CANFD frame received or to transmit #0 1 CANFD frame received or to transmit #1 CFIFL COMMON FIFO Buffer Information Label Field 8 9 read-write CFPTR Common FIFO Buffer Pointer Field 16 31 read-write 16 0x004 0-15 CFDCFDF%s Common FIFO Access Data Field %s Registers 0x05C4 32 read-write 0x00000000 0xffffffff CFDB_LL Common FIFO Buffer Data Bytes (p × 4) 0 7 read-write CFDB_LH Common FIFO Buffer Data Bytes ((p × 4) + 1) 8 15 read-write CFDB_HL Common FIFO Buffer Data Bytes ((p × 4) + 2) 16 23 read-write CFDB_HH Common FIFO Buffer Data Bytes ((p × 4) + 3) 24 31 read-write 4 0x004C 0-3 CFDTMID%s TX Message Buffer ID Registers 0x0604 32 read-write 0x00000000 0xffffffff TMID TX Message Buffer ID Field 0 28 read-write THLEN Tx History List Entry 29 29 read-write 0 Entry not stored in THL after successful TX #0 1 Entry stored in THL after successful TX #1 TMRTR TX Message Buffer RTR bit 30 30 read-write 0 Data frame #0 1 Remote frame #1 TMIDE TX Message Buffer IDE bit 31 31 read-write 0 STD-ID is transmitted #0 1 EXT-ID is transmitted #1 4 0x004C 0-3 CFDTMPTR%s TX Message Buffer Pointer Register 0x0608 32 read-write 0x00000000 0xffffffff TMDLC TX Message Buffer DLC Field 28 31 read-write 4 0x004C 0-3 CFDTMFDCTR%s TX Message Buffer CANFD Control Register 0x060C 32 read-write 0x00000000 0xffffffff TMESI Error State Indicator bit 0 0 read-write 0 CANFD frame to transmit by error active node #0 1 CANFD frame to transmit by error passive node #1 TMBRS Bit Rate Switch bit 1 1 read-write 0 CANFD frame to transmit with no bit rate switch #0 1 CANFD frame to transmit with bit rate switch #1 TMFDF CAN FD Format bit 2 2 read-write 0 Non CANFD frame to transmit #0 1 CANFD frame to transmit #1 TMIFL TX Message Buffer Information Label Field 8 9 read-write TMPTR TX Message Buffer Pointer Field 16 31 read-write 4 0x04c 0-3 CFDTMDF%s_0 TX Message Buffer Data Field Register 0x0610 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_1 TX Message Buffer Data Field Register 0x0614 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_2 TX Message Buffer Data Field Register 0x0618 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_3 TX Message Buffer Data Field Register 0x061C 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_4 TX Message Buffer Data Field Register 0x0620 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_5 TX Message Buffer Data Field Register 0x0624 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_6 TX Message Buffer Data Field Register 0x0628 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_7 TX Message Buffer Data Field Register 0x062C 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_8 TX Message Buffer Data Field Register 0x0630 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_9 TX Message Buffer Data Field Register 0x0634 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_10 TX Message Buffer Data Field Register 0x0638 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_11 TX Message Buffer Data Field Register 0x063C 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_12 TX Message Buffer Data Field Register 0x0640 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_13 TX Message Buffer Data Field Register 0x0644 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_14 TX Message Buffer Data Field Register 0x0648 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_15 TX Message Buffer Data Field Register 0x064C 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write CFDTHLACC0 TX History List Access Register 0 0x0740 32 read-only 0x00000000 0xffffffff BT Buffer Type 0 2 read-only 001 Flat TX message buffer #001 010 TX FIFO message buffer number #010 100 TX Queue message buffer number #100 BN Buffer Number 3 4 read-only TMTS Transmit Timestamp 16 31 read-only CFDTHLACC1 TX History List Access Register 1 0x0744 32 read-only 0x00000000 0xffffffff TID Transmit ID 0 15 read-only TIFL Transmit Information Label 16 17 read-only 8 0x004C 0-7 CFDRMID%s RX Message Buffer ID Registers 0x0920 32 read-only 0x00000000 0xffffffff RMID RX Message Buffer ID Field 0 28 read-only RMRTR RX Message Buffer RTR Bit 30 30 read-only 0 Data frame #0 1 Remote frame #1 RMIDE RX Message Buffer IDE Bit 31 31 read-only 0 STD-ID is stored #0 1 EXT-ID is stored #1 8 0x004C 0-7 CFDRMPTR%s RX Message Buffer Pointer Registers 0x0924 32 read-only 0x00000000 0xffffffff RMTS RX Message Buffer Timestamp Field 0 15 read-only RMDLC RX Message Buffer DLC Field 28 31 read-only 8 0x004C 0-7 CFDRMFDSTS%s RX Message Buffer CANFD Status Registers 0x0928 32 read-only 0x00000000 0xffffffff RMESI Error State Indicator bit 0 0 read-only 0 CANFD frame received from error active node #0 1 CANFD frame received from error passive node #1 RMBRS Bit Rate Switch bit 1 1 read-only 0 CANFD frame received with no bit rate switch #0 1 CANFD frame received with bit rate switch #1 RMFDF CAN FD Format bit 2 2 read-only 0 Non CANFD frame received #0 1 CANFD frame received #1 RMIFL RX Message Buffer Information Label Field 8 9 read-only RMPTR RX Message Buffer Pointer Field 16 31 read-only 8 0x004C 0-7 CFDRMDF%s_0 RX Message Buffer Data Field 0 Registers 0x092C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_1 RX Message Buffer Data Field 1 Registers 0x0930 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_2 RX Message Buffer Data Field 2 Registers 0x0934 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_3 RX Message Buffer Data Field 3 Registers 0x0938 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_4 RX Message Buffer Data Field 4 Registers 0x093C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_5 RX Message Buffer Data Field 5 Registers 0x0940 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_6 RX Message Buffer Data Field 6 Registers 0x0944 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_7 RX Message Buffer Data Field 7 Registers 0x0948 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_8 RX Message Buffer Data Field 8 Registers 0x094C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_9 RX Message Buffer Data Field 9 Registers 0x0950 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_10 RX Message Buffer Data Field 10 Registers 0x0954 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_11 RX Message Buffer Data Field 11 Registers 0x0958 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_12 RX Message Buffer Data Field 12 Registers 0x095C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_13 RX Message Buffer Data Field 13 Registers 0x0960 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_14 RX Message Buffer Data Field 14 Registers 0x0964 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_15 RX Message Buffer Data Field 15 Registers 0x0968 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMID%s RX Message Buffer ID Registers 0x0D20 32 read-only 0x00000000 0xffffffff RMID RX Message Buffer ID Field 0 28 read-only RMRTR RX Message Buffer RTR Bit 30 30 read-only 0 Data frame #0 1 Remote frame #1 RMIDE RX Message Buffer IDE Bit 31 31 read-only 0 STD-ID is stored #0 1 EXT-ID is stored #1 8 0x004C 8-15 CFDRMPTR%s RX Message Buffer Pointer Registers 0x0D24 32 read-only 0x00000000 0xffffffff RMTS RX Message Buffer Timestamp Field 0 15 read-only RMDLC RX Message Buffer DLC Field 28 31 read-only 8 0x004C 8-15 CFDRMFDSTS%s RX Message Buffer CANFD Status Registers 0x0D28 32 read-only 0x00000000 0xffffffff RMESI Error State Indicator bit 0 0 read-only 0 CANFD frame received from error active node #0 1 CANFD frame received from error passive node #1 RMBRS Bit Rate Switch bit 1 1 read-only 0 CANFD frame received with no bit rate switch #0 1 CANFD frame received with bit rate switch #1 RMFDF CAN FD Format bit 2 2 read-only 0 Non CANFD frame received #0 1 CANFD frame received #1 RMIFL RX Message Buffer Information Label Field 8 9 read-only RMPTR RX Message Buffer Pointer Field 16 31 read-only 8 0x004C 8-15 CFDRMDF%s_0 RX Message Buffer Data Field 0 Registers 0x0D2C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_1 RX Message Buffer Data Field 1 Registers 0x0D30 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_2 RX Message Buffer Data Field 2 Registers 0x0D34 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_3 RX Message Buffer Data Field 3 Registers 0x0D38 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_4 RX Message Buffer Data Field 4 Registers 0x0D3C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_5 RX Message Buffer Data Field 5 Registers 0x0D40 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_6 RX Message Buffer Data Field 6 Registers 0x0D44 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_7 RX Message Buffer Data Field 7 Registers 0x0D48 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_8 RX Message Buffer Data Field 8 Registers 0x0D4C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_9 RX Message Buffer Data Field 9 Registers 0x0D50 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_10 RX Message Buffer Data Field 10 Registers 0x0D54 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_11 RX Message Buffer Data Field 11 Registers 0x0D58 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_12 RX Message Buffer Data Field 12 Registers 0x0D5C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_13 RX Message Buffer Data Field 13 Registers 0x0D60 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_14 RX Message Buffer Data Field 14 Registers 0x0D64 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_15 RX Message Buffer Data Field 15 Registers 0x0D68 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMID%s RX Message Buffer ID Registers 0x01120 32 read-only 0x00000000 0xffffffff RMID RX Message Buffer ID Field 0 28 read-only RMRTR RX Message Buffer RTR Bit 30 30 read-only 0 Data frame #0 1 Remote frame #1 RMIDE RX Message Buffer IDE Bit 31 31 read-only 0 STD-ID is stored #0 1 EXT-ID is stored #1 8 0x004C 16-23 CFDRMPTR%s RX Message Buffer Pointer Registers 0x01124 32 read-only 0x00000000 0xffffffff RMTS RX Message Buffer Timestamp Field 0 15 read-only RMDLC RX Message Buffer DLC Field 28 31 read-only 8 0x004C 16-23 CFDRMFDSTS%s RX Message Buffer CANFD Status Registers 0x01128 32 read-only 0x00000000 0xffffffff RMESI Error State Indicator bit 0 0 read-only 0 CANFD frame received from error active node #0 1 CANFD frame received from error passive node #1 RMBRS Bit Rate Switch bit 1 1 read-only 0 CANFD frame received with no bit rate switch #0 1 CANFD frame received with bit rate switch #1 RMFDF CAN FD Format bit 2 2 read-only 0 Non CANFD frame received #0 1 CANFD frame received #1 RMIFL RX Message Buffer Information Label Field 8 9 read-only RMPTR RX Message Buffer Pointer Field 16 31 read-only 8 0x004C 16-23 CFDRMDF%s_0 RX Message Buffer Data Field 0 Registers 0x112C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_1 RX Message Buffer Data Field 1 Registers 0x1130 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_2 RX Message Buffer Data Field 2 Registers 0x1134 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_3 RX Message Buffer Data Field 3 Registers 0x1138 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_4 RX Message Buffer Data Field 4 Registers 0x113C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_5 RX Message Buffer Data Field 5 Registers 0x1140 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_6 RX Message Buffer Data Field 6 Registers 0x1144 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_7 RX Message Buffer Data Field 7 Registers 0x1148 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_8 RX Message Buffer Data Field 8 Registers 0x114C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_9 RX Message Buffer Data Field 9 Registers 0x1150 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_10 RX Message Buffer Data Field 10 Registers 0x1154 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_11 RX Message Buffer Data Field 11 Registers 0x1158 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_12 RX Message Buffer Data Field 12 Registers 0x115C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_13 RX Message Buffer Data Field 13 Registers 0x1160 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_14 RX Message Buffer Data Field 14 Registers 0x1164 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_15 RX Message Buffer Data Field 15 Registers 0x1168 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMID%s RX Message Buffer ID Registers 0x01520 32 read-only 0x00000000 0xffffffff RMID RX Message Buffer ID Field 0 28 read-only RMRTR RX Message Buffer RTR Bit 30 30 read-only 0 Data frame #0 1 Remote frame #1 RMIDE RX Message Buffer IDE Bit 31 31 read-only 0 STD-ID is stored #0 1 EXT-ID is stored #1 8 0x004C 24-31 CFDRMPTR%s RX Message Buffer Pointer Registers 0x01524 32 read-only 0x00000000 0xffffffff RMTS RX Message Buffer Timestamp Field 0 15 read-only RMDLC RX Message Buffer DLC Field 28 31 read-only 8 0x004C 24-31 CFDRMFDSTS%s RX Message Buffer CANFD Status Registers 0x01528 32 read-only 0x00000000 0xffffffff RMESI Error State Indicator bit 0 0 read-only 0 CANFD frame received from error active node #0 1 CANFD frame received from error passive node #1 RMBRS Bit Rate Switch bit 1 1 read-only 0 CANFD frame received with no bit rate switch #0 1 CANFD frame received with bit rate switch #1 RMFDF CAN FD Format bit 2 2 read-only 0 Non CANFD frame received #0 1 CANFD frame received #1 RMIFL RX Message Buffer Information Label Field 8 9 read-only RMPTR RX Message Buffer Pointer Field 16 31 read-only 8 0x004C 24-31 CFDRMDF%s_0 RX Message Buffer Data Field 0 Registers 0x152C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_1 RX Message Buffer Data Field 1 Registers 0x1530 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_2 RX Message Buffer Data Field 2 Registers 0x1534 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_3 RX Message Buffer Data Field 3 Registers 0x1538 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_4 RX Message Buffer Data Field 4 Registers 0x153C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_5 RX Message Buffer Data Field 5 Registers 0x1540 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_6 RX Message Buffer Data Field 6 Registers 0x1544 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_7 RX Message Buffer Data Field 7 Registers 0x1548 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_8 RX Message Buffer Data Field 8 Registers 0x154C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_9 RX Message Buffer Data Field 9 Registers 0x1550 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_10 RX Message Buffer Data Field 10 Registers 0x1554 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_11 RX Message Buffer Data Field 11 Registers 0x1558 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_12 RX Message Buffer Data Field 12 Registers 0x155C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_13 RX Message Buffer Data Field 13 Registers 0x1560 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_14 RX Message Buffer Data Field 14 Registers 0x1564 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_15 RX Message Buffer Data Field 15 Registers 0x1568 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only PSCU Peripheral Security Control Unit 0x400E0000 0x04 40 registers PSARB Peripheral Security Attribution Register B 0x04 32 read-write 0xffffffff 0xffffffff PSARB4 I3C and the MSTPCRB.MSTPB4 bit security attribution 4 4 read-write 0 Secure #0 1 Non-secure #1 PSARB18 SPI1 and the MSTPCRB.MSTPB18 bit security attribution 18 18 read-write 0 Secure #0 1 Non-secure #1 PSARB19 SPI0 and the MSTPCRB.MSTPB19 bit security attribution 19 19 read-write 0 Secure #0 1 Non-secure #1 PSARB22 SCI9 and the MSTPCRB.MSTPB22 bit security attribution 22 22 read-write 0 Secure #0 1 Non-secure #1 PSARB31 SCI0 and the MSTPCRB.MSTPB31 bit security attribution 31 31 read-write 0 Secure #0 1 Non-secure #1 PSARC Peripheral Security Attribution Register C 0x08 32 read-write 0xffffffff 0xffffffff PSARC0 CAC and the MSTPCRC.MSTPC0 bit security attribution 0 0 read-write 0 Secure #0 1 Non-secure #1 PSARC1 CRC and the MSTPCRC.MSTPC1 bit security attribution 1 1 read-write 0 Secure #0 1 Non-secure #1 PSARC13 DOC and the MSTPCRC.MSTPC13 bit security attribution 13 13 read-write 0 Secure #0 1 Non-secure #1 PSARC20 TFU and the MSTPCRC.MSTPC20 bit security attribution 20 20 read-write 0 Secure #0 1 Non-secure #1 PSARC27 CANFD0 and the MSTPCRC.MSTPC27 bit security attribution 27 27 read-write 0 Secure #0 1 Non-secure #1 PSARC28 TRNG and the MSTPCRC.MSTPC28 bit security attribution 28 28 read-write 0 Secure #0 1 Non-secure #1 PSARD Peripheral Security Attribution Register D 0x0C 32 read-write 0xffffffff 0xffffffff PSARD2 AGT1 and the MSTPCRD.MSTPD2 bit security attribution 2 2 read-write 0 Secure #0 1 Non-secure #1 PSARD3 AGT0 and the MSTPCRD.MSTPD3 bit security attribution 3 3 read-write 0 Secure #0 1 Non-secure #1 PSARD11 POEG Group D and the MSTPCRD.MSTPD11 bit security attribution 11 11 read-write 0 Secure #0 1 Non-secure #1 PSARD12 POEG Group C and the MSTPCRD.MSTPD12 bit security attribution 12 12 read-write 0 Secure #0 1 Non-secure #1 PSARD13 POEG Group B and the MSTPCRD.MSTPD13 bit security attribution 13 13 read-write 0 Secure #0 1 Non-secure #1 PSARD14 POEG Group A and the MSTPCRD.MSTPD14 bit security attribution 14 14 read-write 0 Secure #0 1 Non-secure #1 PSARD16 ADC120 and the MSTPCRD.MSTPD16 bit security attribution 16 16 read-write 0 Secure #0 1 Non-secure #1 PSARD20 DAC12 and the MSTPCRD.MSTPD20 bit security attribution 20 20 read-write 0 Secure #0 1 Non-secure #1 PSARD22 TSN and the MSTPCRD.MSTPD22 bit security attribution 22 22 read-write 0 Secure #0 1 Non-secure #1 PSARD26 ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution 26 26 read-write 0 Secure #0 1 Non-secure #1 PSARD27 ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution 27 27 read-write 0 Secure #0 1 Non-secure #1 PSARD28 ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution 28 28 read-write 0 Secure #0 1 Non-secure #1 PSARE Peripheral Security Attribution Register E 0x10 32 read-write 0xffffffff 0xffffffff PSARE0 WDT security attribution 0 0 read-write 0 Secure #0 1 Non-secure #1 PSARE1 IWDT security attribution 1 1 read-write 0 Secure #0 1 Non-secure #1 PSARE26 GPT5 and the MSTPCRE.MSTPE26 bit security attribution 26 26 read-write 0 Secure #0 1 Non-secure #1 PSARE27 GPT4 and the MSTPCRE.MSTPE27 bit security attribution 27 27 read-write 0 Secure #0 1 Non-secure #1 PSARE28 GPT3 and the MSTPCRE.MSTPE28 bit security attribution 28 28 read-write 0 Secure #0 1 Non-secure #1 PSARE29 GPT2 and the MSTPCRE.MSTPE29 bit security attribution 29 29 read-write 0 Secure #0 1 Non-secure #1 PSARE30 GPT1 and the MSTPCRE.MSTPE30 bit security attribution 30 30 read-write 0 Secure #0 1 Non-secure #1 PSARE31 GPT0, GPT_OPS and the MSTPCRE.MSTPE31 bit security attribution 31 31 read-write 0 Secure #0 1 Non-secure #1 MSSAR Module Stop Security Attribution Register 0x14 32 read-write 0xffffffff 0xffffffff MSSAR0 The MSTPCRC.MSTPC14 bit security attribution 0 0 read-write 0 Secure #0 1 Non-secure #1 MSSAR1 The MSTPCRA.MSTPA22 bit security attribution 1 1 read-write 0 Secure #0 1 Non-secure #1 MSSAR3 The MSTPCRA.MSTPA0 bit security attribution 3 3 read-write 0 Secure #0 1 Non-secure #1 CFSAMONA Code Flash Security Attribution Register A 0x18 32 read-write 0x00000000 0xff007fff CFS2 Code Flash Secure area 2 15 23 read-write CFSAMONB Code Flash Security Attribution Register B 0x1C 32 read-write 0x00000000 0xff0003ff CFS1 Code Flash Secure area 1 10 23 read-write DFSAMON Data Flash Security Attribution Register 0x20 32 read-write 0x0000fc00 0xffffffff DFS Data flash Secure area 10 15 read-write 0x00 0 KB 0x00 0x01 1 KB 0x01 0x02 2 KB 0x02 0x03 3 KB 0x03 0x04 4 KB 0x04 Others Setting prohibited true SSAMONA SRAM Security Attribution Register A 0x24 32 read-write 0x001fe000 0xffffffff SS2 SRAM Secure area 2 13 20 read-write 0x000 0 KB 0x000 0x001 8 KB 0x001 0x002 16 KB 0x002 0x003 24 KB 0x003 0x004 32 KB 0x004 0x005 40 KB 0x005 Others Setting prohibited true SSAMONB SRAM Security Attribution Register B 0x28 32 read-write 0x001ffc00 0xffffffff SS1 SRAM secure area 1 10 20 read-write AGTW0 Low Power Asynchronous General Purpose Timer 0 0x400E8000 0x00 15 registers 0x10 4 registers AGT AGT Counter Register 0x00 32 read-write 0xffffffff 0xffffffff AGTCMA AGT CounterCompare Match A Register 0x04 32 read-write 0xffffffff 0xffffffff AGTCMB AGT CounterCompare Match B Register 0x08 32 read-write 0xffffffff 0xffffffff AGTCR AGT Control Register 0x0C 8 read-write 0x00 0xff TSTART AGT Count Start 0 0 read-write 0 Count stops #0 1 Count starts #1 TCSTF AGT Count Status Flag 1 1 read-only 0 Count stopped #0 1 Count in progress #1 TSTOP AGT Count Forced Stop 2 2 write-only 0 Writing is invalid #0 1 The count is forcibly stopped #1 TEDGF Active Edge Judgment Flag 4 4 read-write 0 No active edge received #0 1 Active edge received #1 TUNDF Underflow Flag 5 5 read-write 0 No underflow #0 1 Underflow #1 TCMAF Compare Match A Flag 6 6 read-write 0 No match #0 1 Match #1 TCMBF Compare Match B Flag 7 7 read-write 0 No match #0 1 Match #1 AGTMR1 AGT Mode Register 1 0x0D 8 read-write 0x40 0xff TMOD Operating Mode 0 2 read-write 000 Timer mode #000 001 Pulse output mode #001 010 Event counter mode #010 011 Pulse width measurement mode #011 100 Pulse period measurement mode #100 Others Setting prohibited true TEDGPL Edge Polarity 3 3 read-write 0 Single-edge #0 1 Both-edge #1 TCK Count Source 4 6 read-write 000 PCLKB #000 001 PCLKB/8 #001 011 PCLKB/2 #011 100 Divided clock AGTLCLK specified by CKS[2:0] bits in the AGTMR2 register #100 101 Underflow event signal from AGT0 #101 110 Divided clock AGTSCLK specified by CKS[2:0] bits in the AGTMR2 register #110 Others Setting prohibited true AGTMR2 AGT Mode Register 2 0x0E 8 read-write 0x00 0xff CKS AGTLCLK or AGTSCLK Count Source Clock Frequency Division Ratio 0 2 read-write 000 1/1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 111 1/128 #111 LPM Low Power Mode 7 7 read-write 0 Normal mode #0 1 Low power mode #1 AGTIOC AGT I/O Control Register 0x10 8 read-write 0x00 0xff TEDGSEL I/O Polarity Switch 0 0 read-write TOE AGTOn pin Output Enable 2 2 read-write 0 AGTOn pin output disabled #0 1 AGTOn pin output enabled #1 TIPF Input Filter 4 5 read-write 00 No filter #00 01 Filter sampled at PCLKB #01 10 Filter sampled at PCLKB/8 #10 11 Filter sampled at PCLKB/32 #11 TIOGT Count Control 6 7 read-write 00 Event is always counted #00 01 Event is counted during polarity period specified for AGTEEn pin #01 Others Setting prohibited true AGTISR AGT Event Pin Select Register 0x11 8 read-write 0x00 0xff EEPS AGTEEn Polarity Selection 2 2 read-write 0 An event is counted during the low-level period #0 1 An event is counted during the high-level period #1 AGTCMSR AGT Compare Match Function Select Register 0x12 8 read-write 0x00 0xff TCMEA AGT Compare Match A Register Enable 0 0 read-write 0 AGT Compare match A register disabled #0 1 AGT Compare match A register enabled #1 TOEA AGTOAn Pin Output Enable 1 1 read-write 0 AGTOAn pin output disabled #0 1 AGTOAn pin output enabled #1 TOPOLA AGTOAn Pin Polarity Select 2 2 read-write 0 AGTOAn pin output is started on low. i.e. normal output #0 1 AGTOAn pin output is started on high. i.e. inverted output #1 TCMEB AGT Compare Match B Register Enable 4 4 read-write 0 Compare match B register disabled #0 1 Compare match B register enabled #1 TOEB AGTOBn Pin Output Enable 5 5 read-write 0 AGTOBn pin output disabled #0 1 AGTOBn pin output enabled #1 TOPOLB AGTOBn Pin Polarity Select 6 6 read-write 0 AGTOBn pin output is started on low. i.e. normal output #0 1 AGTOBn pin output is started on high. i.e. inverted output #1 AGTIOSEL AGT Pin Select Register 0x13 8 read-write 0x00 0xff SEL AGTIOn Pin Select 0 1 read-write 00 Select Pm/AGTIO as AGTIO. Pm/AGTIO can not be used as AGTIO input pin in Deep Software Standby mode. (m = 100, 301, and 407 (AGT0), m = P104, 207 and 400 (AGT1).) #00 01 Setting prohibited #01 10 Select P402/AGTIO as AGTIO. P402/AGTIO can be used as AGTIO input pin in Deep Software Standby mode. P402/AGTIOn is input only. It cannot be used for output. #10 11 Select P403/AGTIO as AGTIO. P403/AGTIO can be used as AGTIO input pin in Deep Software Standby mode. P403/AGTIOn is input only. It cannot be used for output. #11 TIES AGTIOn Pin Input Enable 4 4 read-write 0 External event input is disabled during Software Standby mode #0 1 External event input is enabled during Software Standby mode #1 AGTW1 Low Power Asynchronous General Purpose Timer 1 0x400E8100 TSN Temperature Sensor 0x400F3000 0x00 1 registers TSCR Temperature Sensor Control Register 0x00 8 read-write 0x00 0xff TSOE Temperature Sensor Output Enable 4 4 read-write 0 Disable output from the temperature sensor to the ADC12 #0 1 Enable output from the temperature sensor to the ADC12 #1 TSEN Temperature Sensor Enable 7 7 read-write 0 Stop the temperature sensor #0 1 Start the temperature sensor. #1 ACMPHS0 High-Speed Analog Comparator 0 0x400F4000 0x00 1 registers 0x04 1 registers 0x08 1 registers 0x0C 1 registers 0x10 1 registers CMPCTL Comparator Control Register 0x000 8 read-write 0x00 0xff CINV Comparator Output Polarity Selection 0 0 read-write 0 Do not invert comparator output #0 1 Invert comparator output #1 COE Comparator Output Enable 1 1 read-write 0 Disable comparator output (output signal is low level) #0 1 Enable comparator output #1 CSTEN Interrupt Select 2 2 read-write 0 Output through the edge selector #0 1 Output directly #1 CEG Selection of Valid Edge (Edge Selector) 3 4 read-write 00 Do not detect edge #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 CDFS Noise Filter Selection 5 6 read-write 00 Do not use noise filter #00 01 Use noise filter sampling frequency of PCLKB/23 #01 10 Use noise filter sampling frequency of PCLKB/24 #10 11 Use noise filter sampling frequency of PCLKB/25 #11 HCMPON Comparator Operation Control 7 7 read-write 0 Stop operation (comparator outputs a low-level signal) #0 1 Enable operation (enables input to the comparator pins) #1 CMPSEL0 Comparator Input Select Register 0x004 8 read-write 0x00 0xff CMPSEL Comparator Input Selection 0 3 read-write 0x0 Do not input 0x0 0x1 Select IVCMP0 0x1 0x2 Select IVCMP1 0x2 0x4 Select IVCMP2 0x4 0x8 Select IVCMP3 0x8 Others Setting prohibited true CMPSEL1 Comparator Reference Voltage Select Register 0x008 8 read-write 0x00 0xff CRVS Reference Voltage Selection 0 3 read-write 0x0 Do not input 0x0 0x1 Select IVREF0 0x1 0x2 Select IVREF1 0x2 0x4 Select IVREF2 0x4 0x8 Select IVREF3 0x8 Others Setting prohibited true CMPMON Comparator Output Monitor Register 0x00C 8 read-only 0x00 0xff CMPMON Comparator Output Monitor 0 0 read-only 0 Comparator output is low #0 1 Comparator output is high #1 CPIOC Comparator Output Control Register 0x010 8 read-write 0x00 0xff CPOE Comparator Output Selection 0 0 read-write 0 Disable CMPOUTn pin output of the comparator (output signal is low fixed) #0 1 Enable CMPOUTn pin output of the comparator #1 VREFEN VREFEN Internal Vref Enable 7 7 read-write 0 Disable internal Vref #0 1 Enable internal Vref #1 ACMPHS1 High-Speed Analog Comparator 1 0x400F4100 ACMPHS2 High-Speed Analog Comparator 2 0x400F4200 CRC Cyclic Redundancy Check Calculator 0x40108000 0x00 1 registers 0x04 4 registers 0x08 4 registers CRCCR0 CRC Control Register 0 0x00 8 read-write 0x00 0xff GPS CRC Generating Polynomial Switching 0 2 read-write 001 8-bit CRC-8 (X8 + X2 + X + 1) #001 010 16-bit CRC-16 (X16 + X15 + X2 + 1) #010 011 16-bit CRC-CCITT (X16 + X12 + X5 + 1) #011 100 32-bit CRC-32 (X32 + X26 + X23 + X22 + X16 + X12 + X11 +X10 + X8 + X7 + X5 + X4 + X2 + X + 1) #100 101 32-bit CRC-32C (X32 + X28 + X27 + X26 + X25 + X23 + X22 + X20 + X19 + X18 + X14 + X13 + X11 + X10 + X9 + X8 + X6 + 1) #101 Others No calculation is executed true LMS CRC Calculation Switching 6 6 read-write 0 Generate CRC code for LSB-first communication #0 1 Generate CRC code for MSB-first communication #1 DORCLR CRCDOR/CRCDOR_HA/CRCDOR_BY Register Clear 7 7 write-only 0 No effect #0 1 Clear the CRCDOR/CRCDOR_HA/CRCDOR_BY register #1 CRCDIR CRC Data Input Register 0x04 32 read-write 0x00000000 0xffffffff CRCDIR_BY CRC Data Input Register CRCDIR 0x04 8 read-write 0x00 0xff CRCDOR CRC Data Output Register 0x08 32 read-write 0x00000000 0xffffffff CRCDOR_HA CRC Data Output Register CRCDOR 0x08 16 read-write 0x0000 0xffff CRCDOR_BY CRC Data Output Register CRCDOR 0x08 8 read-write 0x00 0xff DOC Data Operation Circuit 0x40109000 0x00 1 registers 0x02 4 registers DOCR DOC Control Register 0x00 8 read-write 0x00 0xff OMS Operating Mode Select 0 1 read-write 00 Data comparison mode #00 01 Data addition mode #01 10 Data subtraction mode #10 11 Setting prohibited #11 DCSEL Detection Condition Select 2 2 read-write 0 Set DOPCF flag when data mismatch is detected #0 1 Set DOPCF flag when data match is detected #1 DOPCF DOC Flag 5 5 read-only DOPCFCL DOPCF Clear 6 6 read-write 0 Retain DOPCF flag state #0 1 Clear DOPCF flag #1 DODIR DOC Data Input Register 0x02 16 read-write 0x0000 0xffff DODSR DOC Data Setting Register 0x04 16 read-write 0x0000 0xffff SCI0 Serial Communication Interface 0x40118000 0x00 30 registers 0x20 1 registers 0x22 4 registers SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x00 8 read-write 0x00 0xff CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 MP Multi-Processor Mode 2 2 read-write 0 Disable multi-processor communications function #0 1 Enable multi-processor communications function #1 STOP Stop Bit Length 3 3 read-write 0 1 stop bit #0 1 2 stop bits #1 PM Parity Mode 4 4 read-write 0 Even parity #0 1 Odd parity #1 PE Parity Enable 5 5 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 CHR Character Length 6 6 read-write 0 SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value) #0 1 SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 7-bit data length #1 CM Communication Mode 7 7 read-write 0 Asynchronous mode or simple IIC mode #0 1 Clock synchronous mode or simple SPI mode #1 SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) SMR 0x00 8 read-write 0x00 0xff CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 BCP Base Clock Pulse 2 3 read-write PM Parity Mode 4 4 read-write 0 Even parity #0 1 Odd parity #1 PE Parity Enable 5 5 read-write BLK Block Transfer Mode 6 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 GM GSM Mode 7 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 BRR Bit Rate Register 0x01 8 read-write 0xff 0xff SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x02 8 read-write 0x00 0xff CKE Clock Enable 0 1 read-write 00 In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. #00 01 In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin. #01 Others In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency 8 times the bit rate when the SEMR.ABCS bit is 1. In clock synchronous mode, the SCKn pin functions as the clock input pin. true TEIE Transmit End Interrupt Enable 2 2 read-write 0 Disable SCIn_TEI interrupt requests #0 1 Enable SCIn_TEI interrupt requests #1 MPIE Multi-Processor Interrupt Enable 3 3 read-write 0 Normal reception #0 1 When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 and the status flags SYER, PFER, and SBER in MESR are disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed. #1 RE Receive Enable 4 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 TE Transmit Enable 5 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 RIE Receive Interrupt Enable 6 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TIE Transmit Interrupt Enable 7 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) SCR 0x02 8 read-write 0x00 0xff CKE Clock Enable 0 1 read-write 00 When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low #00 01 When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock #01 10 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high #10 11 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock #11 TEIE Transmit End Interrupt Enable 2 2 read-write MPIE Multi-Processor Interrupt Enable 3 3 read-write RE Receive Enable 4 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 TE Transmit Enable 5 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 RIE Receive Interrupt Enable 6 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TIE Transmit Interrupt Enable 7 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 TDR Transmit Data Register 0x03 8 read-write 0xff 0xff SSR Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0, FCR.FM = 0, and MMR.MANEN = 0) 0x04 8 read-write 0x84 0xff MPBT Multi-Processor Bit Transfer 0 0 read-write 0 Data transmission cycle #0 1 ID transmission cycle #1 MPB Multi-Processor 1 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TEND Transmit End Flag 2 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 PER Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 FER Framing Error Flag 4 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 RDRF Receive Data Full Flag 6 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 SSR_FIFO Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0, FCR.FM = 1, and MMR.MANEN = 0) SSR 0x04 8 read-write 0x80 0xfd DR Receive Data Ready Flag 0 0 read-write 0 Receiving is in progress, or no received data remains in FRDRHL after successfully completed reception (receive FIFO empty) #0 1 Next receive data is not received for a period after normal receiving is complete, when the amount of data stored in the FIFO is equal to or less than the receive triggering number #1 TEND Transmit End Flag 2 2 read-write 0 A character is being transmitted #0 1 Character transfer is complete #1 PER Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 FER Framing Error Flag 4 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 RDF Receive FIFO Data Full Flag 6 6 read-write 0 The amount of receive data written in FRDRHL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRHL is equal to or greater than the specified receive triggering number #1 TDFE Transmit FIFO Data Empty Flag 7 7 read-write 0 The amount of transmit data written in FTDRHL exceeds the specified transmit triggering number #0 1 The amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering number #1 SSR_MANC Serial Status Register for Manchester Mode (SCMR.SMIF = 0, and MMR.MANEN = 1) SSR 0x04 8 read-write 0x84 0xff MER Manchester Error Flag 0 0 read-write 0 No Manchester error occurred #0 1 Manchester error has occurred #1 MPB Multi-Processor 1 1 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 TEND Transmit End Flag 2 2 read-only 0 A character is being transmitted #0 1 Character transfer has been completed. #1 PER Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 A parity error has occurred #1 FER Framing Error Flag 4 4 read-write 0 No framing error occurred #0 1 A framing error has occurred #1 ORER Overrun Error Flag 5 5 read-write 0 No overrun error occurred #0 1 An overrun error has occurred #1 RDRF Receive Data Full Flag 6 6 read-write 0 No received data is in RDR register #0 1 Received data is in RDR register #1 TDRE Transmit Data Empty Flag 7 7 read-write 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 SSR_SMCI Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1, and MMR.MANEN = 0) SSR 0x04 8 read-write 0x84 0xff MPBT Multi-Processor Bit Transfer 0 0 read-write MPB Multi-Processor 1 1 read-only TEND Transmit End Flag 2 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 PER Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 ERS Error Signal Status Flag 4 4 read-write 0 No low error signal response #0 1 Low error signal response occurred #1 ORER Overrun Error Flag 5 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 RDRF Receive Data Full Flag 6 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 RDR Receive Data Register 0x05 8 read-only 0x00 0xff SCMR Smart Card Mode Register 0x06 8 read-write 0xf2 0xff SMIF Smart Card Interface Mode Select 0 0 read-write 0 Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode) #0 1 Smart card interface mode #1 SINV Transmitted/Received Data Invert 2 2 read-write 0 TDR contents are transmitted as they are. Received data is stored as received in the RDR register. #0 1 TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register. #1 SDIR Transmitted/Received Data Transfer Direction 3 3 read-write 0 Transfer LSB-first #0 1 Transfer MSB-first #1 CHR1 Character Length 1 4 4 read-write 0 SMR.CHR = 0: Transmit/receive in 9-bit data length SMR.CHR = 1: Transmit/receive in 9-bit data length #0 1 SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) SMR.CHR = 1: Transmit/receive in 7-bit data length #1 BCP2 Base Clock Pulse 2 7 7 read-write SEMR Serial Extended Mode Register 0x07 8 read-write 0x00 0xff PADIS Preamble function Disable 1 1 read-write 0 Preamble output function is enabled #0 1 Preamble output function is disabled #1 BRME Bit Rate Modulation Enable 2 2 read-write 0 Disable bit rate modulation function #0 1 Enable bit rate modulation function #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 3 3 read-write 0 Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register #0 1 Baud rate is 6 base clock cycles for 1-bit period #1 ABCS Asynchronous Mode Base Clock Select 4 4 read-write 0 Select 16 base clock cycles for 1-bit period #0 1 Select 8 base clock cycles for 1-bit period #1 NFEN Digital Noise Filter Function Enable 5 5 read-write 0 In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple I2C mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple I2C mode: Enable noise cancellation function for SCLn and SDAn input signals #1 BGDM Baud Rate Generator Double-Speed Mode Select 6 6 read-write 0 Output clock from baud rate generator with normal frequency #0 1 Output clock from baud rate generator with doubled frequency #1 RXDESEL Asynchronous Start Bit Edge Detection Select 7 7 read-write 0 Detect low level on RXDn pin as start bit #0 1 Detect falling edge of RXDn pin as start bit #1 SNFR Noise Filter Setting Register 0x08 8 read-write 0x00 0xff NFCS Noise Filter Clock Select 0 2 read-write 000 In asynchronous mode: Use clock signal divided by 1 with noise filter In simple I2C mode: Setting prohibited #000 001 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 1 with noise filter #001 010 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 2 with noise filter #010 011 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 4 with noise filter #011 100 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 8 with noise filter #100 Others Setting prohibited true SIMR1 IIC Mode Register 1 0x09 8 read-write 0x00 0xff IICM Simple IIC Mode Select 0 0 read-write 0 SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode #0 1 SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited #1 IICDL SDAn Delay Output Select 3 7 read-write 0x00 No output delay 0x00 Others (IICDL - 1) to (IICDL) cycles true SIMR2 IIC Mode Register 2 0x0A 8 read-write 0x00 0xff IICINTM IIC Interrupt Mode Select 0 0 read-write 0 Use ACK/NACK interrupts #0 1 Use reception and transmission interrupts #1 IICCSC Clock Synchronization 1 1 read-write 0 Do not synchronize with clock signal #0 1 Synchronize with clock signal #1 IICACKT ACK Transmission Data 5 5 read-write 0 ACK transmission #0 1 NACK transmission and ACK/NACK reception #1 SIMR3 IIC Mode Register 3 0x0B 8 read-write 0x00 0xff IICSTAREQ Start Condition Generation 0 0 read-write 0 Do not generate start condition #0 1 Generate start condition #1 IICRSTAREQ Restart Condition Generation 1 1 read-write 0 Do not generate restart condition #0 1 Generate restart condition #1 IICSTPREQ Stop Condition Generation 2 2 read-write 0 Do not generate stop condition #0 1 Generate stop condition #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 3 read-write 0 No requests are being made for generating conditions, or a condition is being generated #0 1 Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0 #1 IICSDAS SDAn Output Select 4 5 read-write 00 Output serial data #00 01 Generate start, restart, or stop condition #01 10 Output low on SDAn pin #10 11 Drive SDAn pin to high-impedance state #11 IICSCLS SCLn Output Select 6 7 read-write 00 Output serial clock #00 01 Generate start, restart, or stop condition #01 10 Output low on SCLn pin #10 11 Drive SCLn pin to high-impedance state #11 SISR IIC Status Register 0x0C 8 read-only 0x00 0xcb IICACKR ACK Reception Data Flag 0 0 read-only 0 ACK received #0 1 NACK received #1 SPMR SPI Mode Register 0x0D 8 read-write 0x00 0xff SSE SSn Pin Function Enable 0 0 read-write 0 Disable SSn pin function #0 1 Enable SSn pin function #1 CTSE CTS Enable 1 1 read-write 0 Disable CTS function (enable RTS output function) #0 1 Enable CTS function #1 MSS Master Slave Select 2 2 read-write 0 Transmit through TXDn pin and receive through RXDn pin (master mode) #0 1 Receive through TXDn pin and transmit through RXDn pin (slave mode) #1 CTSPEN CTS external pin Enable 3 3 read-write 0 Alternate setting to use CTS and RTS functions as either one terminal #0 1 Dedicated setting for separately using CTS and RTS functions with 2 terminals #1 MFF Mode Fault Flag 4 4 read-write 0 No mode fault error #0 1 Mode fault error #1 CKPOL Clock Polarity Select 6 6 read-write 0 Do not invert clock polarity #0 1 Invert clock polarity #1 CKPH Clock Phase Select 7 7 read-write 0 Do not delay clock #0 1 Delay clock #1 FTDRHL Transmit FIFO Data Register 0x0E 16 write-only 0xffff 0xffff TDAT Serial transmit data 0 8 write-only MPBT Multi-Processor Transfer Bit Flag 9 9 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TDRHL Transmit Data Register for Non-Manchester mode (MMR.MANEN = 0) FTDRHL 0x0E 16 read-write 0xffff 0xffff TDAT Serial Transmit Data 0 8 read-write TDRHL_MAN Transmit Data Register for Manchester mode (MMR.MANEN = 1) FTDRHL 0x0E 16 read-write 0xffff 0xffff TDAT Serial transmit data 0 8 read-write MPBT Multi-processor transfer bit flag 9 9 read-write 0 Data transmission cycles #0 1 ID transmission cycles #1 TSYNC Transmit SYNC data bit 12 12 read-write 0 The Start Bit is transmitted as DATA SYNC. #0 1 The Start Bit is transmitted as COMMAND SYNC. #1 FTDRH Transmit FIFO Data Register FTDRHL 0x0E 8 write-only 0xff 0xff MPBT Multi-Processor Transfer Bit Flag 1 1 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 FTDRL Transmit FIFO Data Register FTDRHL 0x0F 8 write-only 0xff 0xff TDAT Serial transmit data 0 7 write-only FRDRHL Receive FIFO Data Register 0x10 16 read-only 0x0000 0xffff RDAT Serial receive data 0 8 read-only MPB Multi-Processor Bit Flag 9 9 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 DR Receive Data Ready Flag 10 10 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 PER Parity Error Flag 11 11 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 FER Framing Error Flag 12 12 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 ORER Overrun Error Flag 13 13 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 RDF Receive FIFO Data Full Flag 14 14 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 RDRHL Receive Data Register for Non-Manchester mode (MMR.MANEN = 0) FRDRHL 0x10 16 read-only 0x0000 0xffff RDAT Serial Receive Data 0 8 read-only RDRHL_MAN Receive Data Register for Manchester mode (MMR.MANEN = 1) FRDRHL 0x10 16 read-only 0x0000 0xffff RDAT Serial receive data 0 8 read-only MPB Multi-processor bit 9 9 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 RSYNC Receive SYNC data bit 12 12 read-only 0 The received the Start Bit is DATA SYNC #0 1 The received the Start Bit is COMMAND SYNC #1 FRDRH Receive FIFO Data Register FRDRHL 0x10 8 read-only 0x00 0xff MPB Multi-Processor Bit Flag 1 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 DR Receive Data Ready Flag 2 2 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 PER Parity Error Flag 3 3 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 FER Framing Error Flag 4 4 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 ORER Overrun Error Flag 5 5 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 RDF Receive FIFO Data Full Flag 6 6 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRL Receive FIFO Data Register FRDRHL 0x11 8 read-only 0x00 0xff RDAT Serial receive data 0 7 read-only MDDR Modulation Duty Register 0x12 8 read-write 0xff 0xff DCCR Data Compare Match Control Register 0x13 8 read-write 0x40 0xff DCMF Data Compare Match Flag 0 0 read-write 0 Not matched #0 1 Matched #1 DPER Data Compare Match Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 DFER Data Compare Match Framing Error Flag 4 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 IDSEL ID Frame Select 6 6 read-write 0 Always compare data regardless of the MPB bit value #0 1 Only compare data when MPB bit = 1 (ID frame) #1 DCME Data Compare Match Enable 7 7 read-write 0 Disable address match function #0 1 Enable address match function #1 FCR FIFO Control Register 0x14 16 read-write 0xf800 0xffff FM FIFO Mode Select 0 0 read-write 0 Non-FIFO mode. Selects TDR/RDR or TDRHL/RDRHL for communication. #0 1 FIFO mode. Selects FTDRHL/FRDRHL for communication. #1 RFRST Receive FIFO Data Register Reset 1 1 read-write 0 Do not reset FRDRHL #0 1 Reset FRDRHL #1 TFRST Transmit FIFO Data Register Reset 2 2 read-write 0 Do not reset FTDRHL #0 1 Reset FTDRHL #1 DRES Receive Data Ready Error Select 3 3 read-write 0 Receive data full interrupt (SCIn_RXI) #0 1 Receive error interrupt (SCIn_ERI) #1 TTRG Transmit FIFO Data Trigger Number 4 7 read-write RTRG Receive FIFO Data Trigger Number 8 11 read-write RSTRG RTS Output Active Trigger Number Select 12 15 read-write FDR FIFO Data Count Register 0x16 16 read-only 0x0000 0xffff R Receive FIFO Data Count 0 4 read-only T Transmit FIFO Data Count 8 12 read-only LSR Line Status Register 0x18 16 read-only 0x0000 0xffff ORER Overrun Error Flag 0 0 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 FNUM Framing Error Count 2 6 read-only PNUM Parity Error Count 8 12 read-only CDR Compare Match Data Register 0x1A 16 read-write 0x0000 0xffff CMPD Compare Match Data 0 8 read-write SPTR Serial Port Register 0x1C 8 read-write 0x03 0xff RXDMON Serial Input Data Monitor 0 0 read-only 0 When RINV is 0, RXDn terminal is the low level. When RINV is 1, RXDn terminal is the High level. #0 1 When RINV is 0, RXDn terminal is the High level. When RINV is 1, RXDn terminal is the Low level. #1 SPB2DT Serial Port Break Data Select 1 1 read-write 0 When TINV is 0, Low level is output in TXDn terminal. When TINV is 1, High level is output in TXDn terminal. #0 1 When TINV is 0, High level is output in TXDn terminal. When TINV is 1, Low level is output in TXDn terminal. #1 SPB2IO Serial Port Break I/O 2 2 read-write 0 Do not output value of SPB2DT bit on TXDn pin #0 1 Output value of SPB2DT bit on TXDn pin #1 RINV RXD invert bit 4 4 read-write 0 Received data from RXDn is not inverted and input. #0 1 Received data from RXDn is inverted and input. #1 TINV TXD invert bit 5 5 read-write 0 Transmit data is not inverted and output to TXDn. #0 1 Transmit data is inverted and output to TXDn. #1 ASEN Adjust receive sampling timing enable 6 6 read-write 0 Adjust sampling timing disable. #0 1 Adjust sampling timing enable. #1 ATEN Adjust transmit timing enable 7 7 read-write 0 Adjust transmit timing disable. #0 1 Adjust transmit timing enable. #1 ACTR Adjustment Communication Timing Register 0x1D 8 read-write 0x00 0xff AST Adjustment value for receive Sampling Timing 0 2 read-write AJD Adjustment Direction for receive sampling timing 3 3 read-write 0 The sampling timing is adjusted backward to the middle of bit. #0 1 The sampling timing is adjusted forward to the middle of bit. #1 ATT Adjustment value for Transmit timing 4 6 read-write AET Adjustment edge for transmit timing 7 7 read-write 0 Adjust the rising edge timing. #0 1 Adjust the falling edge timing. #1 MMR Manchester Mode Register 0x20 8 read-write 0x00 0xff RMPOL Polarity of Received Manchester Code 0 0 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 TMPOL Polarity of Transmit Manchester Code 1 1 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 ERTEN Manchester Edge Retiming Enable 2 2 read-write 0 Disables the receive retiming function #0 1 Enables the receive retiming function #1 SYNVAL SYNC value Setting 4 4 read-write 0 The start bit is added as a zero-to-one transition. #0 1 The start bit is added as a one-to-zero transition. #1 SYNSEL SYNC Select 5 5 read-write 0 The start bit pattern is set with the SYNVAL bit #0 1 The start bit pattern is set with the TSYNC bit. #1 SBSEL Start Bit Select 6 6 read-write 0 The start bit area consists of one bit. #0 1 The start bit area consists of three bits (COMMAND SYNC or DATA SYNC) #1 MANEN Manchester Mode Enable 7 7 read-write 0 Disables the Manchester mode #0 1 Enables the Manchester mode #1 TMPR Transmit Manchester Preface Setting Register 0x22 8 read-write 0x00 0xff TPLEN Transmit preface length 0 3 read-write 0x0 Disables the transmit preface generation 0x0 Others Transmit preface length (bit length) true TPPAT Transmit preface pattern 4 5 read-write 00 ALL ZERO #00 01 ZERO ONE #01 10 ONE ZERO #10 11 ALL ONE #11 RMPR Receive Manchester Preface Setting Register 0x23 8 read-write 0x00 0xff RPLEN Receive Preface Length 0 3 read-write 0 Disables the receive preface generation #0 Others Receive preface length (bit length) true RPPAT Receive Preface Pattern 4 5 read-write 00 ALL ZERO #00 01 ZERO ONE #01 10 ONE ZERO #10 11 ALL ONE #11 MESR Manchester Extended Error Status Register 0x24 8 read-write 0x00 0xff PFER Preface Error flag 0 0 read-write 0 No preface error detected #0 1 Preface error detected #1 SYER SYNC Error flag 1 1 read-write 0 No receive SYNC error detected #0 1 Receive SYNC error detected #1 SBER Start Bit Error flag 2 2 read-write 0 No start bit error detected #0 1 Start bit error detected #1 MECR Manchester Extended Error Control Register 0x25 8 read-write 0x00 0xff PFEREN Preface Error Enable 0 0 read-write 0 Does not handle a preface error as an interrupt source #0 1 Handles a preface error as an interrupt source #1 SYEREN Receive SYNC Error Enable 1 1 read-write 0 Does not handle a receive SYNC error as an interrupt source #0 1 Handles a receive SYNC error as an interrupt source #1 SBEREN Start Bit Error Enable 2 2 read-write 0 Does not handle a start bit error as an interrupt source #0 1 Handles a start bit error as an interrupt source #1 SCI9 Serial Communication Interface 0x40118900 SPI0 Serial Peripheral Interface 0 0x4011A000 0x00 8 registers 0x08 26 registers SPCR SPI Control Register 0x00 8 read-write 0x00 0xff SPMS SPI Mode Select 0 0 read-write 0 Select SPI operation (4-wire method) #0 1 Select clock synchronous operation (3-wire method) #1 TXMD Communications Operating Mode Select 1 1 read-write 0 Select full-duplex synchronous serial communications #0 1 Select serial communications with transmit-only #1 MODFEN Mode Fault Error Detection Enable 2 2 read-write 0 Disable detection of mode fault errors #0 1 Enable detection of mode fault errors #1 MSTR SPI Master/Slave Mode Select 3 3 read-write 0 Select slave mode #0 1 Select master mode #1 SPEIE SPI Error Interrupt Enable 4 4 read-write 0 Disable SPI error interrupt requests #0 1 Enable SPI error interrupt requests #1 SPTIE Transmit Buffer Empty Interrupt Enable 5 5 read-write 0 Disable transmit buffer empty interrupt requests #0 1 Enable transmit buffer empty interrupt requests #1 SPE SPI Function Enable 6 6 read-write 0 Disable SPI function #0 1 Enable SPI function #1 SPRIE SPI Receive Buffer Full Interrupt Enable 7 7 read-write 0 Disable SPI receive buffer full interrupt requests #0 1 Enable SPI receive buffer full interrupt requests #1 SSLP SPI Slave Select Polarity Register 0x01 8 read-write 0x00 0xff SSL0P SSLn0 Signal Polarity Setting 0 0 read-write 0 Set SSLn0 signal to active-low #0 1 Set SSLn0 signal to active-high #1 SSL1P SSLn1 Signal Polarity Setting 1 1 read-write 0 Set SSLn1 signal to active-low #0 1 Set SSLn1 signal to active-high #1 SSL2P SSLn2 Signal Polarity Setting 2 2 read-write 0 Set SSLn2 signal to active-low #0 1 Set SSLn2 signal to active-high #1 SSL3P SSLn3 Signal Polarity Setting 3 3 read-write 0 Set SSLn3 signal to active-low #0 1 Set SSLn3 signal to active-high #1 SPPCR SPI Pin Control Register 0x02 8 read-write 0x00 0xff SPLP SPI Loopback 0 0 read-write 0 Normal mode #0 1 Loopback mode (receive data = inverted transmit data) #1 SPLP2 SPI Loopback 2 1 1 read-write 0 Normal mode #0 1 Loopback mode (receive data = transmit data) #1 MOIFV MOSI Idle Fixed Value 4 4 read-write 0 Set level output on MOSIn pin during MOSI idling to low #0 1 Set level output on MOSIn pin during MOSI idling to high #1 MOIFE MOSI Idle Value Fixing Enable 5 5 read-write 0 Set MOSI output value to equal final data from previous transfer #0 1 Set MOSI output value to equal value set in the MOIFV bit #1 SPSR SPI Status Register 0x03 8 read-write 0x20 0xff OVRF Overrun Error Flag 0 0 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 IDLNF SPI Idle Flag 1 1 read-only 0 SPI is in the idle state #0 1 SPI is in the transfer state #1 MODF Mode Fault Error Flag 2 2 read-write 0 No mode fault or underrun error occurred #0 1 Mode fault error or underrun error occurred #1 PERF Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 UDRF Underrun Error Flag 4 4 read-write 0 Mode fault error occurred (MODF = 1) #0 1 Underrun error occurred (MODF = 1) #1 SPTEF SPI Transmit Buffer Empty Flag 5 5 read-write 0 Data is in the transmit buffer #0 1 No data is in the transmit buffer #1 CENDF Communication End Flag 6 6 read-write 0 Not communicating or communicating #0 1 Communication completed #1 SPRF SPI Receive Buffer Full Flag 7 7 read-write 0 No valid data is in SPDR/SPDR_HA #0 1 Valid data is in SPDR/SPDR_HA #1 SPDR SPI Data Register 0x04 32 read-write 0x00000000 0xffffffff SPDR_HA SPI Data Register SPDR 0x04 16 read-write 0x0000 0xffff SPDR_BY SPI Data Register SPDR 0x04 8 read-write 0x00 0xff SPSCR SPI Sequence Control Register 0x08 8 read-write 0x00 0xff SPSLN SPI Sequence Length Specification 0 2 read-write 000 Sequence Length is 1 (Referenced SPCMDn, n = 0→0→…) #000 001 Sequence Length is 2 (Referenced SPCMDn, n = 0→1→0→…) #001 010 Sequence Length is 3 (Referenced SPCMDn, n = 0→1→2→0→…) #010 011 Sequence Length is 4 (Referenced SPCMDn, n = 0→1→2→3→0→…) #011 100 Sequence Length is 5 (Referenced SPCMDn, n = 0→1→2→3→4→0→…) #100 101 Sequence Length is 6 (Referenced SPCMDn, n = 0→1→2→3→4→5→0→…) #101 110 Sequence Length is 7 (Referenced SPCMDn, n = 0→1→2→3→4→5→6→0→…) #110 111 Sequence Length is 8 (Referenced SPCMDn, n = 0→1→2→3→4→5→6→7→0→…) #111 SPSSR SPI Sequence Status Register 0x09 8 read-only 0x00 0xff SPCP SPI Command Pointer 0 2 read-only 000 SPCMD0 #000 001 SPCMD1 #001 010 SPCMD2 #010 011 SPCMD3 #011 100 SPCMD4 #100 101 SPCMD5 #101 110 SPCMD6 #110 111 SPCMD7 #111 SPECM SPI Error Command 4 6 read-only 000 SPCMD0 #000 001 SPCMD1 #001 010 SPCMD2 #010 011 SPCMD3 #011 100 SPCMD4 #100 101 SPCMD5 #101 110 SPCMD6 #110 111 SPCMD7 #111 SPBR SPI Bit Rate Register 0x0A 8 read-write 0xff 0xff SPDCR SPI Data Control Register 0x0B 8 read-write 0x00 0xff SPFC Number of Frames Specification 0 1 read-write 00 1 frame #00 01 2 frames #01 10 3 frames #10 11 4 frames #11 SPRDTD SPI Receive/Transmit Data Select 4 4 read-write 0 Read SPDR/SPDR_HA values from receive buffer #0 1 Read SPDR/SPDR_HA values from transmit buffer, but only if the transmit buffer is empty #1 SPLW SPI Word Access/Halfword Access Specification 5 5 read-write 0 Set SPDR_HA to valid for halfword access #0 1 Set SPDR to valid for word access #1 SPBYT SPI Byte Access Specification 6 6 read-write 0 SPDR/SPDR_HA is accessed in halfword or word (SPLW is valid) #0 1 SPDR_BY is accessed in byte (SPLW is invalid) #1 SPCKD SPI Clock Delay Register 0x0C 8 read-write 0x00 0xff SCKDL RSPCK Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SSLND SPI Slave Select Negation Delay Register 0x0D 8 read-write 0x00 0xff SLNDL SSL Negation Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SPND SPI Next-Access Delay Register 0x0E 8 read-write 0x00 0xff SPNDL SPI Next-Access Delay Setting 0 2 read-write 000 1 RSPCK + 2 PCLKA #000 001 2 RSPCK + 2 PCLKA #001 010 3 RSPCK + 2 PCLKA #010 011 4 RSPCK + 2 PCLKA #011 100 5 RSPCK + 2 PCLKA #100 101 6 RSPCK + 2 PCLKA #101 110 7 RSPCK + 2 PCLKA #110 111 8 RSPCK + 2 PCLKA #111 SPCR2 SPI Control Register 2 0x0F 8 read-write 0x00 0xff SPPE Parity Enable 0 0 read-write 0 Do not add parity bit to transmit data and do not check parity bit of receive data #0 1 When SPCR.TXMD = 0: Add parity bit to transmit data and check parity bit of receive data When SPCR.TXMD = 1: Add parity bit to transmit data but do not check parity bit of receive data #1 SPOE Parity Mode 1 1 read-write 0 Select even parity for transmission and reception #0 1 Select odd parity for transmission and reception #1 SPIIE SPI Idle Interrupt Enable 2 2 read-write 0 Disable idle interrupt requests #0 1 Enable idle interrupt requests #1 PTE Parity Self-Testing 3 3 read-write 0 Disable self-diagnosis function of the parity circuit #0 1 Enable self-diagnosis function of the parity circuit #1 SCKASE RSPCK Auto-Stop Function Enable 4 4 read-write 0 Disable RSPCK auto-stop function #0 1 Enable RSPCK auto-stop function #1 8 0x02 0-7 SPCMD%s SPI Command Register %s 0x10 16 read-write 0x070d 0xffff CPHA RSPCK Phase Setting 0 0 read-write 0 Select data sampling on leading edge, data change on trailing edge #0 1 Select data change on leading edge, data sampling on trailing edge #1 CPOL RSPCK Polarity Setting 1 1 read-write 0 Set RSPCK low during idle #0 1 Set RSPCK high during idle #1 BRDV Bit Rate Division Setting 2 3 read-write 00 Base bit rate #00 01 Base bit rate divided by 2 #01 10 Base bit rate divided by 4 #10 11 Base bit rate divided by 8 #11 SSLA SSL Signal Assertion Setting 4 6 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 Others Setting prohibited true SSLKP SSL Signal Level Keeping 7 7 read-write 0 Negate all SSL signals on completion of transfer #0 1 Keep SSL signal level from the end of transfer until the beginning of the next access #1 SPB SPI Data Length Setting 8 11 read-write 0x0 20 bits 0x0 0x1 24 bits 0x1 0x2 32 bits 0x2 0x3 32 bits 0x3 0x8 9 bits 0x8 0x9 10 bits 0x9 0xA 11 bits 0xa 0xB 12 bits 0xb 0xC 13 bits 0xc 0xD 14 bits 0xd 0xE 15 bits 0xe 0xF 16 bits 0xf Others 8 bits true LSBF SPI LSB First 12 12 read-write 0 MSB-first #0 1 LSB-first #1 SPNDEN SPI Next-Access Delay Enable 13 13 read-write 0 Select next-access delay of 1 RSPCK + 2 PCLKA #0 1 Select next-access delay equal to the setting in the SPI Next-Access Delay Register (SPND) #1 SLNDEN SSL Negation Delay Setting Enable 14 14 read-write 0 Select SSL negation delay of 1 RSPCK #0 1 Select SSL negation delay equal to the setting in the SPI Slave Select Negation Delay Register (SSLND) #1 SCKDEN RSPCK Delay Setting Enable 15 15 read-write 0 Select RSPCK delay of 1 RSPCK #0 1 Select RSPCK delay equal to the setting in the SPI Clock Delay Register (SPCKD) #1 SPDCR2 SPI Data Control Register 2 0x20 8 read-write 0x00 0xff BYSW Byte Swap Operating Mode Select 0 0 read-write 0 Byte Swap OFF #0 1 Byte Swap ON #1 SINV Serial Data Invert Bit 1 1 read-write 0 Not invert serial data #0 1 Invert serial data #1 SPCR3 SPI Control Register 3 0x21 8 read-write 0x00 0xff ETXMD Extended Communication Mode Select 0 0 read-write 0 Full-duplex synchronous or transmit-only serial communications. [the SPCR.TXMD bit is enabled] #0 1 Receive-only serial communications in slave mode (SPCR.MSTR bit = 0). [the SPCR.TXMD bit is disabled] Setting is prohibited in master mode (SPCR.MSTR bit = 1). #1 BFDS Between Burst Transfer Frames Delay Select 1 1 read-write 0 Delay (RSPCK delay, SSL negation delay and next-access delay) between frames is inserted in burst transfer. #0 1 Delay between frames is not inserted in burst transfer. #1 CENDIE SPI Communication End Interrupt Enable 4 4 read-write 0 Communication end interrupt request is disabled. #0 1 Communication end interrupt request is enabled. #1 SPI1 Serial Peripheral Interface 1 0x4011A100 I3C I3C Bus Interface 0x4011F000 0x00 4 registers 0x10 12 registers 0x20 8 registers 0x30 16 registers 0x44 4 registers 0x58 4 registers 0x60 8 registers 0x70 36 registers 0x98 4 registers 0xA0 8 registers 0xB0 4 registers 0xC0 4 registers 0x120 16 registers 0x140 4 registers 0x150 12 registers 0x17C 28 registers 0x1C0 12 registers 0x1D0 32 registers 0x200 32 registers 0x224 64 registers 0x2A0 4 registers 0x2B0 4 registers 0x2D0 32 registers 0x320 12 registers 0x330 12 registers 0x350 44 registers 0x380 4 registers 0x394 8 registers 0x3C0 20 registers 0x3E0 8 registers PRTS Protocol Selection Register 0x000 32 read-write 0x00000001 0xffffffff PRTMD Protocol Mode 0 0 read-write 0 I3C protocol mode #0 1 I2C protocol mode #1 CECTL Clock Enable Control Resisters 0x010 32 read-write 0x00000000 0xffffffff CLKE Clock Enable 0 0 read-write 0 Clock disable #0 1 Clock enable #1 BCTL Bus Control Register 0x014 32 read-write 0x00000000 0xffffffff INCBA Include I3C Broadcast Address 0 0 read-write 0 Do not include I3C broadcast address for private transfers #0 1 Include I3C broadcast address for private transfers #1 ABT Abort 29 29 read-write 0 I3C is running. #0 1 I3C has aborted a transfer. #1 RSM Resume 30 30 read-write 0 I3C is running. #0 1 I3C is suspended. #1 BUSE Bus Enable 31 31 read-write 0 I3C bus operation is disabled. #0 1 I3C bus operation is enabled. #1 MSDVAD Master Device Address Register 0x018 32 read-write 0x00000000 0xffffffff MDYAD Master Dynamic Address 16 22 read-write MDYADV Master Dynamic Address Valid 31 31 read-write 0 The master dynamic address field is not valid. #0 1 The master dynamic address field is valid. #1 RSTCTL Reset Control Register 0x020 32 read-write 0x00000000 0xffffffff RI3CRST I3C Software Reset 0 0 read-write 0 Release I3C reset. #0 1 Initiate I3C reset. #1 CMDQRST Command Queue Software Reset 1 1 read-write 0 The Command Queues in I3C is not flushed. #0 1 The Command Queues in I3C is flushed. #1 RSPQRST Response Queue Software Reset 2 2 read-write 0 The Response Queues in I3C is not flushed. #0 1 The Response Queues in I3C is flushed. #1 TDBRST Transmit Data Buffer Software Reset 3 3 read-write 0 The Transmit Queues in I3C is not flushed. #0 1 The Transmit Queues in I3C is flushed. #1 RDBRST Receive Data Buffer Software Reset 4 4 read-write 0 The Receive Queues in I3C is not flushed. #0 1 The Receive Queues in I3C is flushed. #1 IBIQRST IBI Queue Software Reset 5 5 read-write 0 The IBI Queues in I3C is not flushed. #0 1 The IBI Queues in I3C is flushed. #1 RSQRST Receive Status Queue Software Reset 6 6 read-write 0 The Receive Status Queue in I3C is not flushed. #0 1 The Receive Status Queue in I3C is flushed. #1 HCMDQRST High Priority Command Queue Software Reset 9 9 read-write 0 The High Priority Command Queues in I3C is not flushed. #0 1 The High Priority Command Queues in I3C is flushed. #1 HRSPQRST High Priority Response Queue Software Reset 10 10 read-write 0 The High Priority Response Queues in I3C is not flushed. #0 1 The High Priority Response Queues in I3C is flushed. #1 HTDBRST High Priority Transmit Data Buffer Software Reset 11 11 read-write 0 The High Priority Transmit Queues in I3C is not flushed. #0 1 The High Priority Transmit Queues in I3C is flushed. #1 HRDBRST High Priority Receive Data Buffer Software Reset 12 12 read-write 0 The High Priority Receive Queues in I3C is not flushed. #0 1 The High Priority Receive Queues in I3C is flushed. #1 INTLRST Internal Software Reset 16 16 read-write 0 Releases of some registers and internal state. #0 1 Resets of some registers and internal state. #1 PRSST Present State Register 0x024 32 read-write 0x00000000 0xffffffff CRMS Current Master 2 2 read-write 0 The Master is not the Current Master, and must request and acquire bus ownership before initiating any transfer. #0 1 The Master is the Current Master, and as a result can initiate transfers. #1 TRMD Transmit/Receive Mode 4 4 read-only 0 Receive mode #0 1 Transmit mode #1 PRSSTWP Present State Write Protect 7 7 write-only 0 CRMS bit is protected. #0 1 CRMS bit can be written when writing simultaneously with the value of the target bit. #1 INST Internal Status Register 0x030 32 read-write 0x00000000 0xffffffff INEF Internal Error Flag 10 10 read-write 0 I3C Internal Error has not detected. #0 1 I3C Internal Error has detected. #1 INSTE Internal Status Enable Register 0x034 32 read-write 0x00000000 0xffffffff INEE Internal Error Enable 10 10 read-write 0 Disable INST.INEF #0 1 Enable INST.INEF #1 INIE Internal Interrupt Enable Register 0x038 32 read-write 0x00000000 0xffffffff INEIE Internal Error Interrupt Enable 10 10 read-write 0 Disables Non-recoverable Internal Error Interrupt Signal. #0 1 Enables Non-recoverable Internal Error Interrupt Signal. #1 INSTFC Internal Status Force Register 0x03C 32 write-only 0x00000000 0xffffffff INEFC Internal Error Force 10 10 write-only 0 Not force a specific interrupt #0 1 Force a specific interrupt #1 DVCT Device Characteristic Table Register 0x044 32 read-only 0x00000000 0xffffffff IDX DCT Table Index 19 23 read-only IBINCTL IBI Notify Control Register 0x058 32 read-write 0x00000000 0xffffffff NRMRCTL Notify Rejected Master Request Control 1 1 read-write 0 Do not pass rejected IBI Status to IBI Queue/Ring, if the incoming Master Request is NACKed and is auto-disabled based on DVMRRJ field in relevant DAT entry. #0 1 Pass rejected IBI Status to the IBI Queue, if the incoming Master Request is NACKed and is autodisabled based on DVMRRJ field in relevant DAT entry. #1 NRSIRCTL Notify Rejected Slave Interrupt Request Control 3 3 read-write 0 Do not pass rejected IBI Status to the IBI Queue/Rings, if the incoming SIR is NACKed and is auto-disabled based on DVSIRRJ field in relevant DAT entry. #0 1 Pass rejected IBI Status to the IBI Queue/Rings, if the incoming SIR is NACKed and is auto-disabled based on DVSIRRJ field in relevant DAT entry. #1 BFCTL Bus Function Control Register 0x060 32 read-write 0x00000101 0xffffffff MALE Master Arbitration-Lost Detection Enable 0 0 read-write 0 Master arbitration-lost detection disables. Disables the arbitration-lost detection function and does not clear the CRMS and TRMD bits in PRSST automatically when arbitration is lost. #0 1 Master arbitration-lost detection enables. Enables the arbitration-lost detection function and clears the CRMS and TRMD bits in PRSST automatically when arbitration is lost. #1 NALE NACK Transmission Arbitration-Lost Detection Enable 1 1 read-write 0 NACK transmission arbitration-lost detection disables. #0 1 NACK transmission arbitration-lost detection enables. #1 SALE Slave Arbitration-Lost Detection Enable 2 2 read-write 0 Slave arbitration-lost detection disables. #0 1 Slave arbitration-lost detection enables. #1 SCSYNE SCL Synchronous Circuit Enable 8 8 read-write 0 No SCL synchronous circuit uses. #0 1 An SCL synchronous circuit uses. #1 SMBS SMBus/I2C Bus Selection 12 12 read-write 0 The I2C bus select. #0 1 The SMBus select. #1 FMPE Fast-mode Plus Enable 14 14 read-write 0 No Fm+ slope control circuit uses for the I3C_SCL pin and I3C_SDA pin. (n = 0) #0 1 An Fm+ slope control circuit uses for the I3C_SCL pin and I3C_SDA pin. (n = 0) #1 HSME High Speed Mode Enable 15 15 read-write 0 Disable High Speed Mode. #0 1 Enable High Speed Mode. #1 SVCTL Slave Control Register 0x064 32 read-write 0x00000000 0xffffffff GCAE General Call Address Enable 0 0 read-write 0 General call address detection disables. #0 1 General call address detection enables. #1 HSMCE Hs-mode Master Code Enable 5 5 read-write 0 Hs-mode Master Code Detection disables. #0 1 Hs-mode Master Code Detection enables. #1 DVIDE Device-ID Address Enable 6 6 read-write 0 Device-ID address detection disables. #0 1 Device-ID address detection enables. #1 HOAE Host Address Enable 15 15 read-write 0 Host address detection disables. #0 1 Host address detection enables. #1 SVAE Slave Address Enable n ( n = 0 to 2 ) 16 18 read-write 0 Slave n disables #0 1 Slave n enables #1 REFCKCTL Reference Clock Control Register 0x070 32 read-write 0x00000000 0xffffffff IREFCKS Internal Reference Clock Selection 0 2 read-write 000 TCLK/1 clock #000 001 TCLK/2 clock #001 010 TCLK/4 clock #010 011 TCLK/8 clock #011 100 TCLK/16 clock #100 101 TCLK/32 clock #101 110 TCLK/64 clock #110 111 TCLK/128 clock #111 STDBR Standard Bit Rate Register 0x074 32 read-write 0x3f3fffff 0xffffffff SBRLO Standard Bit Rate Low-level Period Open-Drain 0 7 read-write SBRHO Standard Bit Rate High-level Period Open-Drain 8 15 read-write SBRLP Standard Bit Rate Low-level Period Push-Pull 16 21 read-write SBRHP Standard Bit Rate High-level Period Push-Pull 24 29 read-write DSBRPO Double the Standard Bit Rate Period for Open-Drain 31 31 read-write 0 The time period set for SBRHO[7:0] and SBRLO[7:0] is not doubled. #0 1 The time period set for SBRHO[7:0] and SBRLO[7:0] is doubled. #1 EXTBR Extended Bit Rate Register 0x078 32 read-write 0x3f3fffff 0xffffffff EBRLO Extended Bit Rate Low-level Period Open-Drain 0 7 read-write EBRHO Extended Bit Rate High-level Period Open-Drain 8 15 read-write EBRLP Extended Bit Rate Low-level Period Push-Pull 16 21 read-write EBRHP Extended Bit Rate High-level Period Push-Pull 24 29 read-write BFRECDT Bus Free Condition Detection Time Register 0x07C 32 read-write 0x00000000 0xffffffff FRECYC Bus Free Condition Detection Cycle 0 8 read-write BAVLCDT Bus Available Condition Detection Time Register 0x080 32 read-write 0x00000000 0xffffffff AVLCYC Bus Available Condition Detection Cycle 0 8 read-write BIDLCDT Bus Idle Condition Detection Time Register 0x084 32 read-write 0x00000000 0xffffffff IDLCYC Bus Idle Condition Detection Cycle 0 17 read-write OUTCTL Output Control Register 0x088 32 read-write 0x00000003 0xffffffff SDOC SDA Output Control 0 0 read-write 0 I3C drives the I3C_SDA pin low. #0 1 I3C releases the I3C_SDA pin. #1 SCOC SCL Output Control 1 1 read-write 0 I3C drives the I3C_SCL pin low. #0 1 I3C releases the I3C_SCL pin. #1 SOCWP SCL/SDA Output Control Write Protect 2 2 write-only 0 Bits SCOC and SDOC are protected. #0 1 Bits SCOC and SDOC can be written (When writing simultaneously with the value of the target bit). This bit is read as 0. #1 EXCYC Extra SCL Clock Cycle Output 4 4 read-write 0 Does not output an extra SCL clock cycle (default). #0 1 Outputs an extra SCL clock cycle. #1 SDOD SDA Output Delay 8 10 read-write 000 No output delay #000 001 1 I3Cφ cycle (When OUTCTL.SDODCS = 0 (I3Cφ)) 1 or 2 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) #001 010 2 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 3 or 4 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) #010 011 3 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 5 or 6 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) #011 100 4 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 7 or 8 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) #100 101 5 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 9 or 10 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) #101 110 6 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 11 or 12 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) #110 111 7 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 13 or 14 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) #111 SDODCS SDA Output Delay Clock Source Selection 15 15 read-write 0 The internal reference clock (I3Cφ) is selected as the clock source of the SDA output delay counter. #0 1 The internal reference clock divided by 2 (I3Cφ/2) is selected as the clock source of the SDA output delay counter. #1 INCTL Input Control Register 0x08C 32 read-write 0x000000d0 0xffffffff DNFS Digital Noise Filter Stage Selection 0 3 read-write DNFE Digital Noise Filter Circuit Enable 4 4 read-write 0 No digital noise filter circuit is used. #0 1 A digital noise filter circuit is used. #1 TMOCTL Timeout Control Register 0x090 32 read-write 0x00000030 0xffffffff TODTS Timeout Detection Time Selection 0 1 read-write 00 16bit-timeout #00 01 14bit-timeout #01 10 8bit-timeout #10 11 6bit-timeout #11 TOLCTL Timeout L Count Control 4 4 read-write 0 Count is disabled while the I3C_SCL line is at a low level. #0 1 Count is enabled while the I3C_SCL line is at a low level. #1 TOHCTL Timeout H Count Control 5 5 read-write 0 Count is disabled while the I3C_SCL line is at a high level. #0 1 Count is enabled while the I3C_SCL line is at a high level. #1 TOMDS Timeout Operation Mode Selection 6 7 read-write 00 Timeout is detected during the following conditions: The bus is busy (BCST.BFREF = 0) in master mode.I3C’s own slave address is detected and the bus is busy in slave mode.The bus is free (BCST.BFREF = 1) while generation of a START condition is requested (CNDCTL.STCND = 1). #00 01 Timeout is detected while the bus is busy. #01 10 Timeout is detected while the bus is free. #10 11 Setting prohibited #11 WUCTL Wake Up Unit Control Register 0x098 32 read-write 0x00000041 0xffffffff WUACKS Wake-Up Acknowledge Selection 0 0 read-write WUANFS Wake-Up Analog Noise Filter Selection 4 4 read-write 0 Do not add the Wake Up analog filter. #0 1 Add the Wake Up analog filter. #1 WUFSYNE Wake-Up function PCLK Synchronous Enable 6 6 read-write 0 I3C asynchronous circuit enable #0 1 I3C synchronous circuit enable #1 WUFE Wake-Up function Enable 7 7 read-write 0 Wake-up function disables #0 1 Wake-up function enables #1 ACKCTL Acknowledge Control Register 0x0A0 32 read-write 0x00000000 0xffffffff ACKR Acknowledge Reception 0 0 read-only 0 A 0 is received as the acknowledge bit (ACK reception). #0 1 A 1 is received as the acknowledge bit (NACK reception). #1 ACKT Acknowledge Transmission 1 1 read-write 0 A 0 is sent as the acknowledge bit (ACK transmission). #0 1 A 1 is sent as the acknowledge bit (NACK transmission). #1 ACKTWP ACKT Write Protect 2 2 write-only 0 The ACKT bit are protected. #0 1 The ACKT bit can be written (when writing simultaneously with the value of the target bit). This bit is read as 0. #1 SCSTRCTL SCL Stretch Control Register 0x0A4 32 read-write 0x00000000 0xffffffff ACKTWE Acknowledge Transmission Wait Enable 0 0 read-write 0 NTST.RDBFF0 is set at the rising edge of the ninth SCL clock cycle. (The I3C_SCL line is not held low at the falling edge of the eighth clock cycle.) #0 1 NTST.RDBFF0 is set at the rising edge of the eighth SCL clock cycle. (The I3C_SCL line is held low at the falling edge of the eighth clock cycle.) Low-hold is released by writing a value to the ACKCTL.ACKT bit. #1 RWE Receive Wait Enable 1 1 read-write 0 No WAIT (The period between ninth clock cycle and first clock cycle is not held low.) #0 1 WAIT (The period between ninth clock cycle and first clock cycle is held low.) Low-hold is released by reading NTDTBP0. #1 SCSTLCTL SCL Stalling Control Register 0x0B0 32 read-write 0x00000000 0xffffffff STLCYC Stalling Cycle 0 15 read-write AAPE Assigned Address Phase Enable 28 28 read-write 0 Does not stall the SCL clock during the address assignment phase. #0 1 Stall the SCL clock during address assignment phase. #1 PARPE Parity Phase Enable 30 30 read-write 0 Does not stall the SCL clock during the parity bit period. #0 1 Stall the SCL clock during the parity bit period. #1 ACKPE ACK phase Enable 31 31 read-write 0 Does not stall the SCL clock during the ACK/NACK phase. #0 1 Stall the SCL clock during the ACK/NACK phase. #1 SVTDLG0 Slave Transfer Data Length Register 0 0x0C0 32 read-write 0x00000000 0xffffffff STDLG Slave Transfer Data Length 16 31 read-write STCTL Synchronous Timing Control Register 0x120 32 read-write 0x00000000 0xffffffff STOE Synchronous Timing output Enable 0 0 read-write 0 Disable #0 1 Enable #1 ATCTL Asynchronous Timing Control Register 0x124 32 read-write 0x00000000 0xffffffff ATTRGS Asynchronous Timing Trigger Select 0 0 read-write 0 Software trigger #0 1 Hardware trigger #1 MREFOE MREF Output Enable (Capture Event / Counter Overflow) 1 1 read-write 0 Disable #0 1 Enable #1 AMEOE Additional Master-initiated bus Event Output Enable 2 2 read-write 0 Disable #0 1 Enable #1 CDIV TCLK Counter Divide Setting 8 15 read-write ATTRG Asynchronous Timing Trigger Register 0x128 32 read-write 0x00000000 0xffffffff ATSTRG Asynchronous Timing Software Trigger 0 0 write-only 0 Do nothing #0 1 Software trigger (one-shot pulse) output This bit is always read as 0. #1 ATCCNTE Asynchronous Timing Contorol Counter enable Register 0x12C 32 read-write 0x00000000 0xffffffff ATCE Asynchronous Timing Counter Enable for MREF, MC2, SC1, SC2. 0 0 read-write 0 Disable #0 1 Enable #1 CNDCTL Condition Control Register 0x140 32 read-write 0x00000000 0xffffffff STCND START (S) Condition Issuance 0 0 read-write 0 Does not request to issue a START condition. #0 1 Requests to issue a START condition. #1 SRCND Repeated START (Sr) Condition Issuance 1 1 read-write 0 Does not request to issue a Repeated START condition. #0 1 Requests to issue a Repeated START condition. #1 SPCND STOP (P) Condition Issuance 2 2 read-write 0 Does not request to issue a STOP condition. #0 1 Requests to issue a STOP condition. #1 NCMDQP Normal Command Queue Port Register 0x150 32 write-only 0x00000000 0xffffffff NRSPQP Normal Response Queue Port Register 0x154 32 read-only 0x00000000 0xffffffff NTDTBP0 Normal Transfer Data Buffer Port Register 0 0x158 32 read-write 0x00000000 0xffffffff NTDTBP0_BY Normal Transfer Data Buffer Port Register 0 NTDTBP0 0x158 8 read-write 0x00 0xff NIBIQP Normal IBI Queue Port Register 0x17C 32 read-write 0x00000000 0xffffffff NRSQP Normal Receive Status Queue Port Register 0x180 32 read-only 0x00000000 0xffffffff HCMDQP High Priority Command Queue Port Register 0x184 32 write-only 0x00000000 0xffffffff HRSPQP High Priority Response Queue Port Register 0x188 32 read-only 0x00000000 0xffffffff HTDTBP High Priority Transfer Data Buffer Port Register 0x18C 32 read-write 0x00000000 0xffffffff NQTHCTL Normal Queue Threshold Control Register 0x190 32 read-write 0x01010101 0xffffffff CMDQTH Normal Command Ready Queue Threshold 0 7 read-write 0x00 Interrupt is issued when Command Queue is completely empty. 0x00 Others Interrupt is issued when Command Queue contains N empties. (N = CMDQTH[7:0]) true RSPQTH Normal Response Queue Threshold 8 15 read-write 0x00 Interrupt is issued when Response Queue contains 1 entry (DWORD). 0x00 Others Interrupt is triggered when Response Queue contains N+1 entries (DWORD). (N = CMDQTH[7:0]) true IBIDSSZ Normal IBI Data Segment Size 16 23 read-write IBIQTH Normal IBI Queue Threshold 24 31 read-write 0x00 I3C Protocol mode (Master): Interrupt is generated when the Outstanding IBI Status count is 1 or more. I3C Protocol mode (Slave): Interrupt is issued when IBI Data Buffer is completely empty. 0x00 Others I3C Protocol mode (Master): Interrupt is generated when the Outstanding IBI Status count is N + 1 or more. (N = CMDQTH[7:0]) I3C Protocol mode (Slave): Interrupt is issued when IBI Data Buffer contains N empties. true NTBTHCTL0 Normal Transfer Data Buffer Threshold Control Register 0 0x194 32 read-write 0x01010101 0xffffffff TXDBTH Normal Transmit Data Buffer Threshold 0 2 read-write 000 Interrupt triggers at 2 Tx Buffer empties, DWORDs #000 001 Interrupt triggers at 4 Tx Buffer empties, DWORDs #001 010 Interrupt triggers at 8 Tx Buffer empties, DWORDs #010 011 Interrupt triggers at 16 Tx Buffer empties, DWORDs #011 Others Setting prohibited true RXDBTH Normal Receive Data Buffer Threshold 8 10 read-write 000 Interrupt triggers at 2 Rx Buffer entries, DWORDs #000 001 Interrupt triggers at 4 Rx Buffer entries, DWORDs #001 010 Interrupt triggers at 8 Rx Buffer entries, DWORDs #010 011 Interrupt triggers at 16 Rx Buffer entries, DWORDs #011 Others Setting prohibited true TXSTTH Normal Tx Start Threshold 16 18 read-write 000 Wait for 2 entry DWORDs #000 001 Wait for 4 entry DWORDs #001 010 Wait for 8 entry DWORDs #010 011 Wait for 16 entry DWORDs #011 Others Setting prohibited true RXSTTH Normal Rx Start Threshold 24 26 read-write 000 Wait for 2 empty DWORDs #000 001 Wait for 4 empty DWORDs #001 010 Wait for 8 empty DWORDs #010 011 Wait for 16 empty DWORDs #011 Others Setting prohibited true NRQTHCTL Normal Receive Status Queue Threshold Control Register 0x1C0 32 read-write 0x00000001 0xffffffff RSQTH Normal Receive Status Queue Threshold 0 7 read-write 0x00 Interrupt is issued when Receive Status Queue contains 1 entry (DWORD). 0x00 Others Interrupt is triggered when Receive Status Queue contains N+1 entries (DWORD). (N = RSQTH[7:0]) true HQTHCTL High Priority Queue Threshold Control Register 0x1C4 32 read-write 0x00000101 0xffffffff CMDQTH High Priority Command Ready Queue Threshold 0 7 read-write 0x00 Interrupt is issued when High Priority Command Queue is completely empty. 0x00 Others Interrupt is issued when High Priority Command Queue contains N entries. (N = CMDQTH[7:0]) true RSPQTH High Priority Response Ready Queue Threshold 8 15 read-write 0x00 Interrupt is issued when High Priority Response Queue contains 1 entry (DWORD). 0x00 Others Interrupt is triggered when High Priority Response Queue contains N+1 entries (DWORD). (N = RSPQTH[7:0]) true HTBTHCTL High Priority Transfer Data Buffer Threshold Control Register 0x1C8 32 read-write 0x01010101 0xffffffff TXDBTH High Priority Transmit Data Buffer Threshold 0 2 read-write 000 Interrupt triggers at 2 High Priority Tx Buffer empties, DWORDs #000 001 Reserved #001 Others Setting prohibited true RXDBTH High Priority Receive Data Buffer Threshold 8 10 read-write 000 Interrupt triggers at 2 High Priority Rx Buffer entries, DWORDs #000 001 Reserved #001 Others Setting prohibited true TXSTTH High Priority Tx Start Threshold 16 18 read-write 000 Wait for 2 entry DWORDs #000 001 Reserved #001 Others Setting prohibited true RXSTTH High Priority Rx Start Threshold 24 26 read-write 000 Wait for 2 empty DWORDs #000 001 Reserved #001 Others Setting prohibited true BST Bus Status Register 0x1D0 32 read-write 0x00000000 0xffffffff STCNDDF START Condition Detection Flag 0 0 read-write 0 START condition is not detected. #0 1 START condition is detected. #1 SPCNDDF STOP Condition Detection Flag 1 1 read-write 0 STOP condition is not detected. #0 1 STOP condition is detected. #1 HDREXDF HDR Exit Pattern Detection Flag 2 2 read-write 0 HDR Exit Pattern is not detected #0 1 HDR Exit Pattern is detected. #1 NACKDF NACK Detection Flag 4 4 read-write 0 NACK is not detected. #0 1 NACK is detected. #1 TENDF Transmit End Flag 8 8 read-write 0 Data is being transmitted. #0 1 Data has been transmitted. #1 ALF Arbitration Lost Flag 16 16 read-write 0 Arbitration is not lost #0 1 Arbitration is lost. #1 TODF Timeout Detection Flag 20 20 read-write 0 Timeout is not detected. #0 1 Timeout is detected. #1 WUCNDDF Wake-Up Condition Detection Flag 24 24 read-write 0 Wake-Up is not detected. #0 1 Wake-Up is detected. #1 BSTE Bus Status Enable Register 0x1D4 32 read-write 0x00000000 0xffffffff STCNDDE START Condition Detection Enable 0 0 read-write 0 Disables START condition Detection Interrupt Status logging. #0 1 Enables START condition Detection Interrupt Status logging. #1 SPCNDDE STOP Condition Detection Enable 1 1 read-write 0 Disables STOP condition Detection Interrupt Status logging. #0 1 Enables STOP condition Detection Interrupt Status logging. #1 HDREXDE HDR Exit Pattern Detection Enable 2 2 read-write 0 Disables HDR Exit Pattern Detection Interrupt Status logging. #0 1 Enables HDR Exit Pattern Detection Interrupt Status logging. #1 NACKDE NACK Detection Enable 4 4 read-write 0 Disables NACK Detection Interrupt Status logging. #0 1 Enables NACK Detection Interrupt Status logging. #1 TENDE Transmit End Enable 8 8 read-write 0 Disables Transmit End Interrupt Status logging. #0 1 Enables Transmit End Interrupt Status logging. #1 ALE Arbitration Lost Enable 16 16 read-write 0 Disables Arbitration Lost Interrupt Status logging. #0 1 Enables Arbitration Lost Interrupt Status logging. #1 TODE Timeout Detection Enable 20 20 read-write 0 Disables Timeout Detection Interrupt Status logging. #0 1 Enables Timeout Detection Interrupt Status logging. #1 WUCNDDE Wake-up Condition Detection Enable 24 24 read-write 0 Disables Wake-up Condition Detection Status logging. #0 1 Enables Wake-up Condition Detection Status logging. #1 BIE Bus Interrupt Enable Register 0x1D8 32 read-write 0x00000000 0xffffffff STCNDDIE START Condition Detection Interrupt Enable 0 0 read-write 0 Disables START condition Detection Interrupt Signal. #0 1 Enables START condition Detection Interrupt Signal. #1 SPCNDDIE STOP Condition Detection Interrupt Enable 1 1 read-write 0 Disables STOP condition Detection Interrupt Signal. #0 1 Enables STOP condition Detection Interrupt Signal. #1 HDREXDIE HDR Exit Pattern Detection Interrupt Enable 2 2 read-write 0 Disables HDR Exit Pattern Detection Interrupt Signal. #0 1 Enables HDR Exit Pattern Detection Interrupt Signal. #1 NACKDIE NACK Detection Interrupt Enable 4 4 read-write 0 Disables NACK Detection Interrupt Signal. #0 1 Enables NACK Detection Interrupt Signal. #1 TENDIE Transmit End Interrupt Enable 8 8 read-write 0 Disables Transmit End Interrupt Signal. #0 1 Enables Transmit End Interrupt Signal. #1 ALIE Arbitration Lost Interrupt Enable 16 16 read-write 0 Disables Arbitration Lost Interrupt Signal. #0 1 Enables Arbitration Lost Interrupt Signal. #1 TODIE Timeout Detection Interrupt Enable 20 20 read-write 0 Disables Timeout Detection Interrupt Signal. #0 1 Enables Timeout Detection Interrupt Signal. #1 WUCNDDIE Wake-Up Condition Detection Interrupt Enable 24 24 read-write 0 Disables Wake-Up Condition Detection Interrupt Signal. #0 1 Enables Wake-Up Condition Detection Interrupt Signal. #1 BSTFC Bus Status Force Register 0x1DC 32 read-write 0x00000000 0xffffffff STCNDDFC START condition Detection Force 0 0 write-only 0 Not Force START condition Detection Interrupt for software testing. #0 1 Force START condition Detection Interrupt for software testing. #1 SPCNDDFC STOP condition Detection Force 1 1 write-only 0 Not Force STOP condition Detection Interrupt for software testing. #0 1 Force STOP condition Detection Interrupt for software testing. #1 HDREXDFC HDR Exit Pattern Detection Force 2 2 write-only 0 Not Force HDR Exit Pattern Detection Interrupt for software testing. #0 1 Force HDR Exit Pattern Detection Interrupt for software testing. #1 NACKDFC NACK Detection Force 4 4 write-only 0 Not Force NACK Detection Interrupt for software testing. #0 1 Force NACK Detection Interrupt for software testing. #1 TENDFC Transmit End Force 8 8 write-only 0 Not Force Transmit End Interrupt for software testing. #0 1 Force Transmit End Interrupt for software testing. #1 ALFC Arbitration Lost Force 16 16 write-only 0 Not Force Arbitration Lost Interrupt for software testing. #0 1 Force Arbitration Lost Interrupt for software testing. #1 TODFC Timeout Detection Force 20 20 write-only 0 Not Force Timeout Detection Interrupt for software testing. #0 1 Force Timeout Detection Interrupt for software testing. #1 WUCNDDFC Wake-Up Condition Detection Force 24 24 write-only 0 Not Force Wake-Up Condition Detection Interrupt for software testing. #0 1 Force Wake-Up Condition Detection Interrupt for software testing. #1 NTST Normal Transfer Status Register 0x1E0 32 read-write 0x00000000 0xffffffff TDBEF0 Normal Transmit Data Buffer Empty Flag 0 0 0 read-write 0 For I2C protocol mode: PRTS.PRTMD bit = 1. Normal Transmit Data Buffer 0 contains transmit data. For I3C protocol mode: PRTS.PRTMD bit = 0. The number of empties in the Normal Transmit Data Buffer 0 is less than the NTBTHCTL0.TXDBTH[2:0] threshold. #0 1 For I2C protocol mode: PRTS.PRTMD bit = 1. Normal Transmit Data Buffer 0 contains no transmit data. For I3C protocol mode: PRTS.PRTMD bit = 0. The number of empties in the Normal Transmit Data Buffer 0 is the NTBTHCTL0.TXDBTH[2:0] threshold or more. #1 RDBFF0 Normal Receive Data Buffer Full Flag 0 1 1 read-write 0 For I2C protocol mode: PRTS.PRTMD bit = 1. Normal Receive Data Buffer0 contains no receive data. For I3C Protocol mode: PRTS.PRTMD bit = 0. The number of entries in the Normal Receive Data Buffer 0 is less than the NTBTHCTL0.RXDBTH[2:0] threshold. #0 1 For I2C protocol mode: PRTS.PRTMD bit = 1. Normal Receive Data Buffer0 contains receive data. For I3C Protocol mode: PRTS.PRTMD bit = 0. The number of entries in the Normal Receive Data Buffer 0 is the NTBTHCTL0.RXDBTH[2:0] threshold or more. #1 IBIQEFF Normal IBI Queue Empty/Full Flag 2 2 read-write 0 For I3C protocol mode (Master): PRTS.PRTMD bit = 0, PRSST.CRMS bit = 1. The number of IBI Status Queue entries is the NQTHCTL.IBIQTH threshold or less. For I3C protocol mode (Slave) : PRTS.PRTMD bit = 0, PRSST.CRMS bit = 0. If the NQTHCTL.IBIQTH = 0: The number of IBI Data Buffer empties is less than the IBI Data Buffer size. If the NQTHCTL.IBIQTH is other than 0: The number of IBI Data Buffer empties is less than the NQTHCTL.IBIQTH threshold. #0 1 For I3C protocol mode (Master): PRTS.PRTMD bit = 0, PRSST.CRMS bit = 1. The number of IBI Status Queue entries is more than the NQTHCTL.IBIQTH threshold. For I3C protocol mode (Slave) : PRTS.PRTMD bit = 0, PRSST.CRMS bit = 0. If the NQTHCTL.IBIQTH = 0: The number of IBI Data Buffer empties is the IBI Data Buffer size. If the NQTHCTL.IBIQTH is other than 0: The number of IBI Data Buffer empties is the NQTHCTL.IBIQTH threshold or more. #1 CMDQEF Normal Command Queue Empty Flag 3 3 read-write 0 If the NQTHCTL.CMDQTH = 0: The number of Command Queue empties is less than the Command Queue size. If the NQTHCTL.CMDQTH is other than 0: The number of Command Queue empties is less than the NQTHCTL.CMDQTH threshold. #0 1 If the NQTHCTL.CMDQTH = 0: The number of Command Queue empties is the Command Queue size. If the NQTHCTL.CMDQTH is other than 0: 1: The number of Command Queue empties is the NQTHCTL.CMDQTH threshold or more. #1 RSPQFF Normal Response Queue Full Flag 4 4 read-write 0 The number of Response Queue entries is the NQTHCTL.RSPQTH threshold or less. #0 1 The number of Response Queue entries is more than the NQTHCTL.RSPQTH threshold. #1 TABTF Normal Transfer Abort Flag 5 5 read-write 0 Transfer Abort does not occur. #0 1 Transfer Abort occur. To clear, write 0 to this bit after 1 state is read. #1 TEF Normal Transfer Error Flag 9 9 read-write 0 Transfer Error does not occur. #0 1 Transfer Error occurs. To clear, write 0 to this bit after 1 state is read. #1 RSQFF Normal Receive Status Queue Full Flag 20 20 read-write 0 The number of Receive Status Queue entries is the NRQTHCTL.RSQTH threshold or less. #0 1 The number of Receive Status Queue entries is more than the NRQTHCTL.RSQTH threshold. #1 NTSTE Normal Transfer Status Enable Register 0x1E4 32 read-write 0x00000000 0xffffffff TDBEE0 Normal Transmit Data Buffer Empty Enable 0 0 0 read-write 0 Disables Tx0 Data Buffer Empty Interrupt Status logging. #0 1 Enables Tx0 Data Buffer Empty Interrupt Status logging. #1 RDBFE0 Normal Receive Data Buffer Full Enable 0 1 1 read-write 0 Disables Rx0 Data Buffer Full Interrupt Status logging. #0 1 Enables Rx0 Data Buffer Full Interrupt Status logging. #1 IBIQEFE Normal IBI Queue Empty/Full Enable 2 2 read-write 0 Disables IBI Status Buffer Empty/Full Interrupt Status logging. #0 1 Enables IBI Status Buffer Empty/Full Interrupt Status logging. #1 CMDQEE Normal Command Queue Empty Enable 3 3 read-write 0 Disables Command Buffer Empty Interrupt Status logging. #0 1 Enables Command Buffer Empty Interrupt Status logging. #1 RSPQFE Normal Response Queue Full Enable 4 4 read-write 0 Disables Response Buffer Full Interrupt Status logging. #0 1 Enables Response Buffer Full Interrupt Status logging. #1 TABTE Normal Transfer Abort Enable 5 5 read-write 0 Disables Transfer Abort Interrupt Status logging. #0 1 Enables Transfer Abort Interrupt Status logging. #1 TEE Normal Transfer Error Enable 9 9 read-write 0 Disables Transfer Error Interrupt Status logging. #0 1 Enables Transfer Error Interrupt Status logging. #1 RSQFE Normal Receive Status Queue Full Enable 20 20 read-write 0 Disables Receive Status Buffer Full Interrupt Status logging. #0 1 Enables Receive Status Buffer Full Interrupt Status logging. #1 NTIE Normal Transfer Interrupt Enable Register 0x1E8 32 read-write 0x00000000 0xffffffff TDBEIE0 Normal Transmit Data Buffer Empty Interrupt Enable 0 0 0 read-write 0 Disables Tx0 Data Buffer Empty Interrupt Signal. #0 1 Enables Tx0 Data Buffer Empty Interrupt Signal. #1 RDBFIE0 Normal Receive Data Buffer Full Interrupt Enable 0 1 1 read-write 0 Disables Rx0 Data Buffer Full Interrupt Signal. #0 1 Enables Rx0 Data Buffer Full Interrupt Signal. #1 IBIQEFIE Normal IBI Queue Empty/Full Interrupt Enable 2 2 read-write 0 Disables IBI Status Buffer Empty/Full Interrupt Signal. #0 1 Enables IBI Status Buffer Empty/Full Interrupt Signal. #1 CMDQEIE Normal Command Queue Empty Interrupt Enable 3 3 read-write 0 Disables Command Buffer Empty Interrupt Signal. #0 1 Enables Command Buffer Empty Interrupt Signal. #1 RSPQFIE Normal Response Queue Full Interrupt Enable 4 4 read-write 0 Disables Response Buffer Full Interrupt Signal. #0 1 Enables Response Buffer Full Interrupt Signal. #1 TABTIE Normal Transfer Abort Interrupt Enable 5 5 read-write 0 Disables Transfer Abort Interrupt Signal. #0 1 Enables Transfer Abort Interrupt Signal. #1 TEIE Normal Transfer Error Interrupt Enable 9 9 read-write 0 Disables Transfer Error Interrupt Signal. #0 1 Enables Transfer Error Interrupt Signal. #1 RSQFIE Normal Receive Status Queue Full Interrupt Enable 20 20 read-write 0 Disables Receive Status Buffer Full Interrupt Signal. #0 1 Enables Receive Status Buffer Full Interrupt Signal. #1 NTSTFC Normal Transfer Status Force Register 0x1EC 32 read-write 0x00000000 0xffffffff TDBEFC0 Normal Transmit Data Buffer Empty Force 0 0 0 write-only 0 Not Force Tx0 Data Buffer Empty Interrupt for software testing. #0 1 Force Tx0 Data Buffer Empty Interrupt for software testing. #1 RDBFFC0 Normal Receive Data Buffer Full Force 0 1 1 write-only 0 Not Force Rx0 Data Buffer Full Interrupt for software testing. #0 1 Force Rx0 Data Buffer Full Interrupt for software testing. #1 IBIQEFFC Normal IBI Queue Empty/Full Force 2 2 write-only 0 Not Force IBI Status Buffer Full Interrupt for software testing. #0 1 Force IBI Status Buffer Full Interrupt for software testing. #1 CMDQEFC Normal Command Queue Empty Force 3 3 write-only 0 Not Force Command Buffer Empty Interrupt for software testing. #0 1 Force Command Buffer Empty Interrupt for software testing. #1 RSPQFFC Normal Response Queue Full Force 4 4 write-only 0 Not Force Response Buffer Full Interrupt for software testing. #0 1 Force Response Buffer Full Interrupt for software testing. #1 TABTFC Normal Transfer Abort Force 5 5 write-only 0 Not Force Transfer Abort Interrupt for software testing. #0 1 Force Transfer Abort Interrupt for software testing. #1 TEFC Normal Transfer Error Force 9 9 write-only 0 Not Force Transfer Error Interrupt for software testing. #0 1 Force Transfer Error Interrupt for software testing. #1 RSQFFC Normal Receive Status Queue Full Force 20 20 write-only 0 Not Force Receive Status Buffer Full Interrupt for software testing. #0 1 Force Receive Status Buffer Full Interrupt for software testing. #1 HTST High Priority Transfer Status Register 0x200 32 read-write 0x00000000 0xffffffff TDBEF High Priority Transmit Data Buffer Empty Flag 0 0 read-write 0 The number of empties in the High Priority Transmit Data Buffer is less than the HTBTHCTL.TXDBTH[2:0] threshold. #0 1 The number of empties in the High Priority Transmit Data Buffer is the HTBTHCTL.TXDBTH[2:0] threshold or more. #1 RDBFF High Priority Receive Data Buffer Full Flag 1 1 read-write 0 The number of entries in the High Priority Receive Data Buffer is less than the HTBTHCTL.RXDBTH[2:0] threshold. #0 1 The number of entries in the High Priority Receive Data Buffer is the HTBTHCTL.RXDBTH[2:0] threshold or more. #1 CMDQEF High Priority Command Queue Empty Flag 3 3 read-write 0 If HQTHCTL.CMDQTH is 0, the number of Command Queue empties is less than the Command Queue size. If HQTHCTL.CMDQTH is other than 0, the number of High Priority Command Queue empties is less than the HQTHCTL.CMDQTH threshold. #0 1 If HQTHCTL.CMDQTH is 0, the number of Command Queue empties is the Command Queue size. If HQTHCTL.CMDQTH is other than 0, the number of High Priority Command Queue empties is the HQTHCTL.CMDQTH threshold or more. #1 RSPQFF High Priority Response Queue Full Flag 4 4 read-write 0 The number of High Priority Response Queue entries is less than the HQTHCTL .RSPQTH threshold. #0 1 The number of High Priority Response Queue entries is the HQTHCTL .RSPQTH threshold or more. #1 TABTF High Priority Transfer Abort Flag 5 5 read-write 0 High Priority Transfer Abort does not occur. #0 1 High Priority Transfer Abort occurs. To clear, write 0 to this bit after 1 is read. #1 TEF High Priority Transfer Error Flag 9 9 read-write 0 High Priority Transfer Error does not occur. #0 1 High Priority Transfer Error occurs. To clear, write 0 to this bit after 1 is read. #1 HTSTE High Priority Transfer Status Enable Register 0x204 32 read-write 0x00000000 0xffffffff TDBEE High Priority Transmit Data Buffer Empty Enable 0 0 read-write 0 Disables High Priority Transmit Data Buffer Empty Interrupt Status logging. #0 1 Enables High Priority Transmit Data Buffer Empty Interrupt Status logging. #1 RDBFE High Priority Receive Data Buffer Full Enable 1 1 read-write 0 Disables High Priority Receive Data Buffer Full Interrupt Status logging. #0 1 Enables High Priority Receive Data Buffer Full Interrupt Status logging. #1 CMDQEE High Priority Command Queue Empty Enable 3 3 read-write 0 Disables High Priority Command Buffer Empty Interrupt Status logging. #0 1 Enables High Priority Command Buffer Empty Interrupt Status logging. #1 RSPQFE High Priority Response Queue Full Enable 4 4 read-write 0 Disables High Priority Response Buffer Full Interrupt Status logging. #0 1 Enables High Priority Response Buffer Full Interrupt Status logging. #1 TABTE High Priority Transfer Abort Enable 5 5 read-write 0 Disables High PriorityTransfer Abort Interrupt Status logging. #0 1 Enables High Priority Transfer Abort Interrupt Status logging. #1 TEE High Priority Transfer Error Enable 9 9 read-write 0 Disables High Priority Transfer Error interrupt Stats logging. #0 1 Enables High Priority Transfer Error interrupt Stats logging. #1 HTIE High Priority Transfer Interrupt Enable Register 0x208 32 read-write 0x00000000 0xffffffff TDBEIE High Priority Transmit Data Buffer Empty Interrupt Enable 0 0 read-write 0 Disables High Priority Transmit Data Buffer Empty Interrupt Signal. #0 1 Enables High Priority Transmit Data Buffer Empty Interrupt Signal. #1 RDBFIE High Priority Receive Data Buffer Full Interrupt Enable 1 1 read-write 0 Disables High Priority Receive Data Buffer Full Interrupt Signal. #0 1 Enables High Priority Receive Data Buffer Full Interrupt Signal. #1 CMDQEIE High Priority Command Queue Empty Interrupt Enable 3 3 read-write 0 Disables High Priority Command Buffer Empty Interrupt Signal. #0 1 Enables High Priority Command Buffer Empty Interrupt Signal. #1 RSPQFIE High Priority Response Queue Full Interrupt Enable 4 4 read-write 0 Disables High Priority Response Buffer Full Interrupt Signal. #0 1 Enables High Priority Response Buffer Full Interrupt Signal. #1 TABTIE High Priority Transfer Abort Interrupt Enable 5 5 read-write 0 Disables High Priority Transfer Abort interrupt Signal. #0 1 Enables High Priority Transfer Abort interrupt Signal. #1 TEIE High Priority Transfer Error Interrupt Enable 9 9 read-write 0 Disables High Priority Transfer Error Interrupt Signal. #0 1 Enables High Priority Transfer Error Interrupt Signal. #1 HTSTFC High Priority Transfer Status Force Register 0x20C 32 read-write 0x00000000 0xffffffff TDBEFC High Priority Transmit Data Buffer Empty Force 0 0 write-only 0 Not Force High Priority Transmit Data Buffer Empty Interrupt for software testing. #0 1 Force High Priority Transmit Data Buffer Empty Interrupt for software testing. #1 RDBFFC High Priority Receive Data Buffer Full Force 1 1 write-only 0 Not Force High Priority Receive Data Buffer Full Interrupt for software testing. #0 1 Force High Priority Receive Data Buffer Full Interrupt for software testing. #1 CMDQEFC High Priority Command Queue Empty Force 3 3 write-only 0 Not Force High Priority Command Buffer Empty Interrupt for software testing. #0 1 Force High Priority Command Buffer Empty Interrupt for software testing. #1 RSPQFFC High Priority Response Queue Full Force 4 4 write-only 0 Not Force High Priority Response Buffer Full Interrupt for software testing. #0 1 Force High Priority Response Buffer Full Interrupt for software testing. #1 TABTFC High Priority Transfer Abort Force 5 5 write-only 0 Not Force High Priority Transfer Abort Interrupt for software testing. #0 1 Force High Priority Transfer Abort Interrupt for software testing. #1 TEFC High Priority Transfer Error Force 9 9 write-only 0 Not Force High Priority Transfer Error Interrupt for software testing. #0 1 Force High Priority Transfer Error Interrupt for software testing. #1 BCST Bus Condition Status Register 0x210 32 read-only 0x00000000 0xffffffff BFREF Bus Free Detection Flag 0 0 read-only 0 Have not Detected Bus Free #0 1 Have Detected Bus Free #1 BAVLF Bus Available Detection Flag 1 1 read-only 0 Have not Detected Bus Available #0 1 Have Detected Bus Available #1 BIDLF Bus Idle Detection Flag 2 2 read-only 0 Have not Detected Bus Idle #0 1 Have Detected Bus Idle #1 SVST Slave Status Register 0x214 32 read-write 0x00000000 0xffffffff GCAF General Call Address Detection Flag 0 0 read-write 0 General call address does not detect. #0 1 General call address detects. #1 HSMCF Hs-mode Master Code Detection Flag 5 5 read-write 0 Hs-mode Master Code does not detect. #0 1 Hs-mode Master Code detects. #1 DVIDF Device-ID Address Detection Flag 6 6 read-write 0 Device-ID command does not detect. #0 1 Device-ID command detects. This bit set to 1 when the first frame received immediately after a START condition is detected matches a value of (device ID (1111 100) + 0[W]). #1 HOAF Host Address Detection Flag 15 15 read-write 0 Host address does not detect. #0 1 Host address detects. This bit set to 1 when the received slave address matches the host address (0001 000). #1 SVAF Slave Address Detection Flag n ( n = 0 to 2 ) 16 18 read-write 0 Slave n does not detect #0 1 Slave n detect #1 WUST Wake Up Unit Operating Status Register 0x218 32 read-only 0x00000000 0xffffffff WUASYNF Wake-up function asynchronous operation status flag 0 0 read-only 0 I3C synchronous circuit enable condition. #0 1 I3C asynchronous circuit enable condition. #1 MRCCPT MsyncCNT Counter Capture Register 0x21C 32 read-only 0x00000000 0xffffffff 8 0x08 0-7 DATBAS%s Device Address Table Basic Register %s 0x224 32 read-write 0x00000000 0xffffffff DVSTAD Device Static Address 0 6 read-write DVIBIPL Device IBI Payload 12 12 read-write 0 IBIs from this Device do not carry a Data Payload. #0 1 IBIs from this Device do carry a Data Payload. #1 DVSIRRJ Device In-Band Slave Interrupt Request Reject 13 13 read-write 0 This Device shall ACK the SIR. #0 1 This Device shall NACK the SIR and send the auto-disable CCC. #1 DVMRRJ Device In-Band Master Request Reject 14 14 read-write 0 This Device shall ACK Master Requests. #0 1 This Device shall NACK Master Requests and send the auto-disable command. #1 DVIBITS Device IBI Time-stamp 15 15 read-write 0 The Master shall not time-stamp IBIs from this Device with Master Time-stamps. #0 1 The Master shall time-stamp IBIs for this Device with Master Time-stamps. #1 DVDYAD Device I3C Dynamic Address 16 23 read-write DVNACK Device NACK Retry Count 29 30 read-write DVTYP Device Type 31 31 read-write 0 I3C Device #0 1 I2C Device #1 EXDATBAS Extended Device Address Table Basic Register 0x2A0 32 read-write 0x00000000 0xffffffff EDSTAD Extended Device Static Address 0 6 read-write EDDYAD Extended Device I3C Dynamic Address 16 23 read-write EDNACK Extended Device NACK Retry Count 29 30 read-write EDTYP Extended Device Type 31 31 read-write 0 I3C Device #0 1 I2C Device #1 SDATBAS0 Slave Device Address Table Basic Register 0 0x2B0 32 read-write 0x00000000 0xffffffff SDSTAD Slave Device Static Address 0 9 read-write SDADLS Slave Device Address Length Selection 10 10 read-write 0 Slave device address length 7 bits selected. #0 1 Slave device address length 10 bits selected. (I2C device only) #1 SDIBIPL Slave Device IBI Payload 12 12 read-write 0 IBIs from this device do not carry a data payload. #0 1 IBIs from this device carry a data payload. #1 SDDYAD Slave Device I3C Dynamic Address 16 22 read-write SDATBAS1 Slave Device Address Table Basic Register 1 SDATBAS0 0x2B0 32 read-write 0x00000000 0xffffffff SDSTAD Slave Device Static Address 0 9 read-write SDADLS Slave Device Address Length Selection 10 10 read-write 0 Slave device address length 7 bits selected. #0 1 Slave device address length 10 bits selected. (I2C device only) #1 SDIBIPL Slave Device IBI Payload 12 12 read-write 0 IBIs from this device do not carry a data payload. #0 1 IBIs from this device carry a data payload. #1 SDDYAD Slave Device I3C Dynamic Address 16 22 read-write SDATBAS2 Slave Device Address Table Basic Register 2 SDATBAS0 0x2B0 32 read-write 0x00000000 0xffffffff SDSTAD Slave Device Static Address 0 9 read-write SDADLS Slave Device Address Length Selection 10 10 read-write 0 Slave device address length 7 bits selected. #0 1 Slave device address length 10 bits selected. (I2C device only) #1 SDIBIPL Slave Device IBI Payload 12 12 read-write 0 IBIs from this device do not carry a data payload. #0 1 IBIs from this device carry a data payload. #1 SDDYAD Slave Device I3C Dynamic Address 16 22 read-write 8 0x04 0-7 MSDCT%s Master Device Characteristic Table Register %s 0x2D0 32 read-write 0x00000000 0xffffffff RBCR0 Max Data Speed Limitation 8 8 read-write 0 No Limitation #0 1 Limitation #1 RBCR1 IBI Request Capable 9 9 read-write 0 Not Capable #0 1 Capable #1 RBCR2 IBI Payload 10 10 read-write 0 No data byte follows the accepted IBI. #0 1 Mandatory one or more data bytes follow the accepted IBI. Data byte continuation is indicated by T-Bit. #1 RBCR3 Offline Capable 11 11 read-write 0 Device will always respond to I3C bus commands. #0 1 Device will not always respond to I3C bus commands. #1 RBCR4 Bridge Identifier 12 12 read-write 0 Not a Bridge Device #0 1 A Bridge Device #1 RBCR76 Device Role 14 15 read-write 00 I3C Slave #00 01 I3C Master #01 Others Setting prohibited true SVDCT Slave Device Characteristic Table Register 0x320 32 read-write 0x00000000 0xffffffff TDCR Transfar Device Characteristic Register 0 7 read-write TBCR0 Max Data Speed Limitation 8 8 read-write 0 No Limitation #0 1 Limitation #1 TBCR1 IBI Request Capable 9 9 read-write 0 Not Capable #0 1 Capable #1 TBCR2 IBI Payload 10 10 read-write 0 No data byte follows the accepted IBI. #0 1 Mandatory one or more data bytes follow the accepted IBI. Data byte continuation is indicated by T-Bit. #1 TBCR3 Offline Capable 11 11 read-write 0 Device will always respond to I3C bus commands. #0 1 Device will not always respond to I3C bus commands. #1 TBCR4 Bridge Identifier 12 12 read-write 0 Not a Bridge Device #0 1 A Bridge Device #1 TBCR76 Device Role 14 15 read-write 00 I3C Slave #00 01 I3C Master #01 Others Setting prohibited true SDCTPIDL Slave Device Characteristic Table Provisional ID Low Register 0x324 32 read-write 0x00000000 0xffffffff SDCTPIDH Slave Device Characteristic Table Provisional ID High Register 0x328 32 read-write 0x00000000 0xffffffff 3 0x04 0-2 SVDVAD%s Slave Device Address Register %s 0x330 32 read-only 0x00000000 0xffffffff SVAD Slave Address 16 25 read-only SADLG Slave Address Length 27 27 read-only 0 The 7-bit address format is selected. #0 1 The 10-bit address format is selected. #1 SSTADV Slave Static Address Valid 30 30 read-only 0 Slave address is disabled. #0 1 Slave address is enabled. #1 SDYADV Slave Dynamic Address Valid 31 31 read-only 0 Dynamic Address is disabled. #0 1 Dynamic Address is enabled. #1 CSECMD CCC Slave Events Command Register 0x350 32 read-write 0x00000000 0xffffffff SVIRQE Slave Interrupt Requests Enable 0 0 read-write 0 DISABLED: Slave-initiated Interrupts is Disabled by the Master to control. #0 1 ENABLED: Slave-initiated Interrupts is Enabled by the Master to control. #1 MSRQE Mastership Requests Enable 1 1 read-write 0 DISABLED: Mastership requests from Secondary Masters is Disabled by the Current Master to control. #0 1 ENABLED: Mastership requests from Secondary Masters is Enabled by the Current Master to control. #1 CEACTST CCC Enter Activity State Register 0x354 32 read-write 0x00000000 0xffffffff ACTST Activity State 0 3 read-write 0x1 ENTAS0 (1µs: Latency-free operation) 0x1 0x2 ENTAS1 (100 µs) 0x2 0x4 ENTAS2 (2 ms) 0x4 0x8 ENTAS3 (50 ms: Lowest-activity operation) 0x8 Others Setting prohibited true CMWLG CCC Max Write Length Register 0x358 32 read-write 0x00000000 0xffffffff MWLG Max Write Length 0 15 read-write CMRLG CCC Max Read Length Register 0x35C 32 read-write 0x00000000 0xffffffff MRLG Max Read Length 0 15 read-write IBIPSZ IBI Payload Size 16 23 read-write CETSTMD CCC Enter Test Mode Register 0x360 32 read-only 0x00000000 0xffffffff TSTMD Test Mode 0 7 read-only 0x00 Exit Test Mode This value removes all I3C devices from Test Mode. 0x00 0x01 Vendor Test Mode This value indicates that I3C devices shall return a random 32bit value in the provisional ID during the Dynamic Address Assignment procedure. 0x01 Others Setting prohibited true CGDVST CCC Get Device Status Register 0x364 32 read-write 0x00000000 0xffffffff PNDINT Pending Interrupt 0 3 read-write PRTE Protocol Error 5 5 read-write 0 The Slave has not detected a protocol error since the last Status read. #0 1 The Slave has detected a protocol error since the last Status read. #1 ACTMD Slave Device’s current Activity Mode 6 7 read-write 00 Activity Mode 0 #00 01 Activity Mode 1 #01 10 Activity Mode 2 #10 11 Activity Mode 3 #11 VDRSV Vendor Reserved 8 15 read-write CMDSPW CCC Max Data Speed W (Write) Register 0x368 32 read-write 0x00000000 0xffffffff MSWDR Maximum Sustained Write Data Rate 0 2 read-write 000 fscl Max (default value) #000 001 8 MHz #001 010 6 MHz #010 011 4 MHz #011 100 2 MHz #100 Others Setting prohibited true CMDSPR CCC Max Data Speed R (Read) Register 0x36C 32 read-write 0x00000000 0xffffffff MSRDR Maximum Sustained Read Data Rate 0 2 read-write 000 fscl Max (default value) #000 001 8 MHz #001 010 6 MHz #010 011 4 MHz #011 100 2 MHz #100 Others Setting prohibited true CDTTIM Clock to Data Turnaround Time (TSCO) 3 5 read-write 000 8 ns or less (default value) #000 001 9 ns or less #001 010 10 ns or less #010 011 11 ns or less #011 100 12 ns or less #100 111 TSCO is more than 12 ns, and is reported by private agreement. #111 Others Setting prohibited true CMDSPT CCC Max Data Speed T (Turnaround) Register 0x370 32 read-write 0x00000000 0xffffffff MRTTIM Maximum Read Turnaround Time 0 23 read-write MRTE Maximum Read Turnaround Time Enable 31 31 read-write 0 Disables transmission of the Maximum Read Turnaround Time. (GETMXDS Format 1: Without Turnaround) #0 1 Enables transmission of the Maximum Read Turnaround Time. (GETMXDS Format 2: With Turnaround) #1 CETSM CCC Exchange Timing Support Information M (Mode) Register 0x374 32 read-write 0x00000000 0xffffffff SPTSYN Supports Sync Mode 0 0 read-write 0 Sync Mode is not supported. #0 1 Sync Mode is supported. #1 SPTASYN0 Support Async Mode 0 1 1 read-write 0 Async Mode 0 is not supported. #0 1 Async Mode 0 is supported. #1 SPTASYN1 Support Async Mode 1 2 2 read-write 0 Async Mode 1 is not supported. #0 1 Async Mode 1 is supported. #1 FREQ Frequency Byte 8 15 read-write INAC Inaccuracy Byte 16 23 read-write CETSS CCC Exchange Timing Support Information S (State) Register 0x378 32 read-write 0x00000000 0xffffffff SYNE Sync Mode Enabled 0 0 read-write 0 Sync Mode Disabled #0 1 Sync Mode Enabled #1 ASYNE Async Mode Enabled 1 2 read-write 00 All Mode Disable #00 01 Async Mode 0 Enabled #01 10 Async Mode 1 Enabled #10 Others Setting prohibited true ICOVF Internal Counter Overflow 7 7 read-write 0 Slave has not experienced a counter overflow since the most recent previous check. #0 1 Slave experienced a counter overflow since the most recent previous check. #1 BITCNT Bit Count Register 0x380 32 read-only 0x00000000 0xffffffff BCNT Bit Counter 0 4 read-only NQSTLV Normal Queue Status Level Register 0x394 32 read-only 0x00000004 0xffffffff CMDQFLV Normal Command Queue Free Level 0 7 read-only RSPQLV Normal Response Queue Level 8 15 read-only IBIQLV Normal IBI Queue Level 16 23 read-only IBISCNT Normal IBI Status Count 24 28 read-only NDBSTLV0 Normal Data Buffer Status Level Register 0 0x398 32 read-only 0x00000001 0xffffffff TDBFLV Normal Transmit Data Buffer Free Level 0 7 read-only RDBLV Normal Receive Data Buffer Level 8 15 read-only NRSQSTLV Normal Receive Status Queue Status Level Register 0x3C0 32 read-only 0x00000000 0xffffffff RSQLV Normal Receive Status Queue Level 0 7 read-only HQSTLV High Priority Queue Status Level Register 0x3C4 32 read-only 0x00000002 0xffffffff CMDQLV High Priority Command Queue Level 0 7 read-only RSPQLV High Priority Response Queue Level 8 15 read-only HDBSTLV High Priority Data Buffer Status Level Register 0x3C8 32 read-only 0x00000002 0xffffffff TDBFLV High Priority Transmit Data Buffer Free Level 0 7 read-only RDBLV High Priority Receive Data Buffer Level 8 15 read-only PRSTDBG Present State Debug Register 0x3CC 32 read-only 0x0000000f 0xffffffff SCILV SCL Line Signal Level 0 0 read-only SDILV SDA Line Signal Level 1 1 read-only SCOLV SCL Output Level 2 2 read-only 0 I3C has driven the SCL pin low. #0 1 I3C has released the SCL pin. #1 SDOLV SDA Output Level 3 3 read-only 0 I3C has driven the SDA pin low. #0 1 I3C has released the SDA pin. #1 MSERRCNT Master Error Counters Register 0x3D0 32 read-only 0x00000000 0xffffffff M2ECNT M2 Error Counter 0 7 read-only SC1CPT SC1 Capture monitor Register 0x3E0 32 read-only 0x00000000 0xffffffff SC1C SC1 Capture 0 15 read-only SC2CPT SC2 Capture monitor Register 0x3E4 32 read-only 0x00000000 0xffffffff SC2C SC2 Capture 0 15 read-only ECCMB ECCMB 0x4012F200 0x00 6 registers 0x0C 8 registers EC710CTL ECC Control Register 0x00 32 read-write 0x00000010 0xffffffff ECEMF ECC Error Message Flag 0 0 read-only 0 There is no bit error in present RAM output data #0 1 There is bit error in present RAM output data #1 ECER1F ECC Error Detection and Correction Flag 1 1 read-only 0 After clearing this bit, 1-bit error correction has not occurred #0 1 1-bit error has occurred #1 ECER2F 2-bit ECC Error Detection Flag 2 2 read-only 0 After clearing this bit, 2-bit error has not occurred #0 1 2-bit error has occurred #1 EC1EDIC ECC 1-bit Error Detection Interrupt Control 3 3 read-write 0 Disable 1-bit error detection interrupt request #0 1 Enable 1-bit error detection interrupt request #1 EC2EDIC ECC 2-bit Error Detection Interrupt Control 4 4 read-write 0 Disable 2-bit error detection interrupt request #0 1 Enable 2-bit error detection interrupt request #1 EC1ECP ECC 1-bit Error Correction Permission 5 5 read-write 0 At 1-bit error detection, the error correction is executed #0 1 At 1-bit error detection, the error correction is not executed #1 ECERVF ECC Error Judgment Enable Flag 6 6 read-write 0 Error judgment disable #0 1 Error judgment enable #1 ECER1C Accumulating ECC Error Detection and Correction Flag Clear 9 9 read-write 0 No effect #0 1 Clear accumulating ECC error detection and correction flag #1 ECER2C 2-bit ECC Error Detection Flag Clear 10 10 read-write 0 No effect #0 1 Clear 2-bit ECC error detection flag #1 ECOVFF ECC Overflow Detection Flag 11 11 read-only 0 No effect #0 1 ECC overflow detection flag #1 EMCA Access Control to ECC Mode Select bit 14 15 read-write ECSEDF0 ECC Single bit Error Address Detection Flag 16 16 read-only 0 There is no bit error in EC710EAD0 after reset or clearing ECER1F bit #0 1 Address captured in EC710EAD0 shows that 1-bit error occurred and captured #1 ECDEDF0 ECC Dual Bit Error Address Detection Flag 17 17 read-only 0 There is no bit error in EC710EAD0 after reset or clearing ECER2F bit #0 1 Address captured in EC710EAD0 shows that 2-bit error occurred and captured #1 EC710TMC ECC Test Mode Control Register 0x04 16 read-write 0x0000 0xffff ECDCS ECC Decode Input Select 1 1 read-write 0 Input lower 32 bits of RAM output data to data area of decode circuit #0 1 Input ECEDB31-0 in EC710TED register to data area of decode circuit #1 ECTMCE ECC Test Mode Control Enable 7 7 read-write 0 The access to test mode register and bit is disabled #0 1 The access to test mode register and bit is enabled #1 ETMA ECC Test Mode Bit Access Control 14 15 read-write EC710TED ECC Test Substitute Data Register 0x0C 32 read-write 0x00000000 0xffffffff ECEDB ECC Test Substitute Data 0 31 read-write EC710EAD0 ECC Error Address Register 0x10 32 read-only 0x00000000 0xffffffff ECEAD ECC Error Address 0 10 read-only GPT16E0 General PWM 16-bit Timer 0 0x40169000 0x00 168 registers 0xB8 8 registers 0xD0 8 registers GTWP General PWM Timer Write-Protection Register 0x00 32 read-write 0x00000000 0xffffffff WP Register Write Disable 0 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 STRWP GTSTR.CSTRT Bit Write Disable 1 1 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 STPWP GTSTP.CSTOP Bit Write Disable 2 2 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CLRWP GTCLR.CCLR Bit Write Disable 3 3 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CMNWP Common Register Write Disabled 4 4 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 PRKEY GTWP Key Code 8 15 write-only GTSTR General PWM Timer Software Start Register 0x04 32 read-write 0x00000000 0xffffffff CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTSTP General PWM Timer Software Stop Register 0x08 32 read-write 0xffffffff 0xffffffff CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTCLR General PWM Timer Software Clear Register 0x0C 32 write-only 0x00000000 0xffffffff CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write 0x00000000 0xffffffff SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGCR GTETRGC Pin Rising Input Source Counter Start Enable 4 4 read-write 0 Counter start disabled on the rising edge of GTETRGC input #0 1 Counter start enabled on the rising edge of GTETRGC input #1 SSGTRGCF GTETRGC Pin Falling Input Source Counter Start Enable 5 5 read-write 0 Counter start disabled on the falling edge of GTETRGC input #0 1 Counter start enabled on the falling edge of GTETRGC input #1 SSGTRGDR GTETRGD Pin Rising Input Source Counter Start Enable 6 6 read-write 0 Counter start disabled on the rising edge of GTETRGD input #0 1 Counter start enabled on the rising edge of GTETRGD input #1 SSGTRGDF GTETRGD Pin Falling Input Source Counter Start Enable 7 7 read-write 0 Counter start disabled on the falling edge of GTETRGD input #0 1 Counter start enabled on the falling edge of GTETRGD input #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 20 read-write 0 Counter start disabled at the ELC_GPTE input #0 1 Counter start enabled at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 21 read-write 0 Counter start disabled at the ELC_GPTF input #0 1 Counter start enabled at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 22 read-write 0 Counter start disabled at the ELC_GPTG input #0 1 Counter start enabled at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 23 read-write 0 Counter start disabled at the ELC_GPTH input #0 1 Counter start enabled at the ELC_GPTH input #1 CSTRT Software Source Counter Start Enable 31 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write 0x00000000 0xffffffff PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGCR GTETRGC Pin Rising Input Source Counter Stop Enable 4 4 read-write 0 Counter stop disabled on the rising edge of GTETRGC input #0 1 Counter stop enabled on the rising edge of GTETRGC input #1 PSGTRGCF GTETRGC Pin Falling Input Source Counter Stop Enable 5 5 read-write 0 Counter stop disabled on the falling edge of GTETRGC input #0 1 Counter stop enabled on the falling edge of GTETRGC input #1 PSGTRGDR GTETRGD Pin Rising Input Source Counter Stop Enable 6 6 read-write 0 Counter stop disabled on the rising edge of GTETRGD input #0 1 Counter stop enabled on the rising edge of GTETRGD input #1 PSGTRGDF GTETRGD Pin Falling Input Source Counter Stop Enable 7 7 read-write 0 Counter stop disabled on the falling edge of GTETRGD input #0 1 Counter stop enabled on the falling edge of GTETRGD input #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 20 read-write 0 Counter stop disabled at the ELC_GPTE input #0 1 Counter stop enabled at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 21 read-write 0 Counter stop disabled at the ELC_GPTF input #0 1 Counter stop enabled at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 22 read-write 0 Counter stop disabled at the ELC_GPTG input #0 1 Counter stop enabled at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 23 read-write 0 Counter stop disabled at the ELC_GPTH input #0 1 Counter stop enabled at the ELC_GPTH input #1 CSTOP Software Source Counter Stop Enable 31 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write 0x00000000 0xffffffff CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGCR GTETRGC Pin Rising Input Source Counter Clear Enable 4 4 read-write 0 Disable counter clear on the rising edge of GTETRGC input #0 1 Enable counter clear on the rising edge of GTETRGC input #1 CSGTRGCF GTETRGC Pin Falling Input Source Counter Clear Enable 5 5 read-write 0 Counter clear disabled on the falling edge of GTETRGC input #0 1 Counter clear enabled on the falling edge of GTETRGC input #1 CSGTRGDR GTETRGD Pin Rising Input Source Counter Clear Enable 6 6 read-write 0 Disable counter clear on the rising edge of GTETRGD input #0 1 Enable counter clear on the rising edge of GTETRGD input #1 CSGTRGDF GTETRGD Pin Falling Input Source Counter Clear Enable 7 7 read-write 0 Counter clear disabled on the falling edge of GTETRGD input #0 1 Counter clear enabled on the falling edge of GTETRGD input #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 20 read-write 0 Counter clear disabled at the ELC_GPTE input #0 1 Counter clear enabled at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 21 read-write 0 Counter clear disabled at the ELC_GPTF input #0 1 Counter clear enabled at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 22 read-write 0 Counter clear disabled at the ELC_GPTG input #0 1 Counter clear enabled at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 23 read-write 0 Counter clear disabled at the ELC_GPTH input #0 1 Counter clear enabled at the ELC_GPTH input #1 CCLR Software Source Counter Clear Enable 31 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write 0x00000000 0xffffffff USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGCR GTETRGC Pin Rising Input Source Counter Count Up Enable 4 4 read-write 0 Counter count up disabled on the rising edge of GTETRGC input #0 1 Counter count up enabled on the rising edge of GTETRGC input #1 USGTRGCF GTETRGC Pin Falling Input Source Counter Count Up Enable 5 5 read-write 0 Counter count up disabled on the falling edge of GTETRGC input #0 1 Counter count up enabled on the falling edge of GTETRGC input #1 USGTRGDR GTETRGD Pin Rising Input Source Counter Count Up Enable 6 6 read-write 0 Counter count up disabled on the rising edge of GTETRGD input #0 1 Counter count up enabled on the rising edge of GTETRGD input #1 USGTRGDF GTETRGD Pin Falling Input Source Counter Count Up Enable 7 7 read-write 0 Counter count up disabled on the falling edge of GTETRGD input #0 1 Counter count up enabled on the falling edge of GTETRGD input #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 20 read-write 0 Counter count up disabled at the ELC_GPTE input #0 1 Counter count up enabled at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 21 read-write 0 Counter count up disabled at the ELC_GPTF input #0 1 Counter count up enabled at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 22 read-write 0 Counter count up disabled at the ELC_GPTG input #0 1 Counter count up enabled at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 23 read-write 0 Counter count up disabled at the ELC_GPTH input #0 1 Counter count up enabled at the ELC_GPTH input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write 0x00000000 0xffffffff DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGCR GTETRGC Pin Rising Input Source Counter Count Down Enable 4 4 read-write 0 Counter count down disabled on the rising edge of GTETRGC input #0 1 Counter count down enabled on the rising edge of GTETRGC input #1 DSGTRGCF GTETRGC Pin Falling Input Source Counter Count Down Enable 5 5 read-write 0 Counter count down disabled on the falling edge of GTETRGC input #0 1 Counter count down enabled on the falling edge of GTETRGC input #1 DSGTRGDR GTETRGD Pin Rising Input Source Counter Count Down Enable 6 6 read-write 0 Counter count down disabled on the rising edge of GTETRGD input #0 1 Counter count down enabled on the rising edge of GTETRGD input #1 DSGTRGDF GTETRGD Pin Falling Input Source Counter Count Down Enable 7 7 read-write 0 Counter count down disabled on the falling edge of GTETRGD input #0 1 Counter count down enabled on the falling edge of GTETRGD input #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 20 read-write 0 Counter count down disabled at the ELC_GPTE input #0 1 Counter count down enabled at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 21 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 22 read-write 0 Counter count down disabled at the ELC_GPTG input #0 1 Counter count down enabled at the ELC_GPTG input #1 DSELCH ELC_GPTH Event Source Counter Count Down Enable 23 23 read-write 0 Counter count down disabled at the ELC_GPTH input #0 1 Counter count down enabled at the ELC_GPTH input #1 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write 0x00000000 0xffffffff ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGCR GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable 4 4 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGC input #1 ASGTRGCF GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable 5 5 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGC input #1 ASGTRGDR GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable 6 6 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGD input #1 ASGTRGDF GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable 7 7 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGD input #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 20 read-write 0 GTCCRA input capture disabled at the ELC_GPTE input #0 1 GTCCRA input capture enabled at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 21 read-write 0 GTCCRA input capture disabled at the ELC_GPTF input #0 1 GTCCRA input capture enabled at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 22 read-write 0 GTCCRA input capture disabled at the ELC_GPTG input #0 1 GTCCRA input capture enabled at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 23 read-write 0 GTCCRA input capture disabled at the ELC_GPTH input #0 1 GTCCRA input capture enabled at the ELC_GPTH input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write 0x00000000 0xffffffff BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGCR GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable 4 4 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGC input #1 BSGTRGCF GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable 5 5 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGC input #1 BSGTRGDR GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable 6 6 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGD input #1 BSGTRGDF GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable 7 7 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGD input #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 20 read-write 0 GTCCRB input capture disabled at the ELC_GPTE input #0 1 GTCCRB input capture enabled at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 21 read-write 0 GTCCRB input capture disabled at the ELC_GPTF input #0 1 GTCCRB input capture enabled at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 22 read-write 0 GTCCRB input capture disabled at the ELC_GPTG input #0 1 GTCCRB input capture enabled at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 23 read-write 0 GTCCRB input capture disabled at the ELC_GPTH input #0 1 GTCCRB input capture enabled at the ELC_GPTH input #1 GTCR General PWM Timer Control Register 0x2C 32 read-write 0x00000000 0xffffffff CST Count Start 0 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 18 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 23 26 read-write 0x0 PCLKD/1 0x0 0x1 PCLKD/2 0x1 0x2 PCLKD/4 0x2 0x3 PCLKD/8 0x3 0x4 PCLKD/16 0x4 0x5 PCLKD/32 0x5 0x6 PCLKD/64 0x6 0x7 Setting prohibited 0x7 0x8 PCLKD/256 0x8 0x9 Setting prohibited 0x9 0xA PCLKD/1024 0xa 0xB Setting prohibited 0xb 0xC GTETRGA (Via the POEG) 0xc 0xD GTETRGB (Via the POEG) 0xd 0xE GTETRGC (Via the POEG) 0xe 0xF GTETRGD (Via the POEG) 0xf GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write 0x00000001 0xffffffff UD Count Direction Setting 0 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTY GTIOCnA Output Duty Setting 16 17 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 19 read-write 0 The function selected by the GTIOA[3:2] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting. #0 1 The function selected by the GTIOA[3:2] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting. #1 OBDTY GTIOCnB Output Duty Setting 24 25 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 27 read-write 0 The function selected by the GTIOB[3:2] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting. #0 1 The function selected by the GTIOB[3:2] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting. #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write 0x00000000 0xffffffff GTIOA GTIOCnA Pin Function Select 0 4 read-write OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OAE GTIOCnA Pin Output Enable 8 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OADF GTIOCnA Pin Disable Value Setting 9 10 read-write 00 None of the below options are specified #00 01 GTIOCnA pin is set to Hi-Z in response to controlling the output negation #01 10 GTIOCnA pin is set to 0 in response to controlling the output negation #10 11 GTIOCnA pin is set to 1 in response to controlling the output negation #11 NFAEN Noise Filter A Enable 13 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 15 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 GTIOB GTIOCnB Pin Function Select 16 20 read-write OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 OBE GTIOCnB Pin Output Enable 24 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBDF GTIOCnB Pin Disable Value Setting 25 26 read-write 00 None of the below options are specified #00 01 GTIOCnB pin is set to Hi-Z in response to controlling the output negation #01 10 GTIOCnB pin is set to 0 in response to controlling the output negation #10 11 GTIOCnB pin is set to 1 in response to controlling the output negation #11 NFBEN Noise Filter B Enable 29 29 read-write 0 The noise filter for the GTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSB Noise Filter B Sampling Clock Select 30 31 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write 0x00000000 0xffffffff GRP Output Disable Source Select 24 25 read-write 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 10 Group C output disable request is selected #10 11 Group D output disable request is selected #11 GRPABH Same Time Output Level High Disable Request Enable 29 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTST General PWM Timer Status Register 0x3C 32 read-write 0x00008000 0xffffffff TCFA Input Capture/Compare Match Flag A 0 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 ITCNT GPTn_OVF/GPTn_UDF Interrupt Skipping Count Counter 8 10 read-only TUCF Count Direction Flag 15 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 ADTRAUF GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag 16 16 read-write 0 No GTADTRA register compare match has occurred in up-counting #0 1 A GTADTRA register compare match has occurred in up-counting #1 ADTRADF GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag 17 17 read-write 0 No GTADTRA register compare match has occurred in down-counting #0 1 A GTADTRA register compare match has occurred in down-counting #1 ADTRBUF GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag 18 18 read-write 0 No GTADTRB register compare match has occurred in up-counting #0 1 A GTADTRB register compare match has occurred in up-counting #1 ADTRBDF GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag 19 19 read-write 0 No GTADTRB register compare match has occurred in down-counting #0 1 A GTADTRB register compare match has occurred in down-counting #1 ODF Output Disable Flag 24 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 DTEF Dead Time Error Flag 28 28 read-only 0 No dead time error has occurred #0 1 A dead time error has occurred #1 OABHF Same Time Output Level High Flag 29 29 read-only 0 No simultaneous generation of 1 both for the GTIOCA and GTIOCB pins has occurred #0 1 A simultaneous generation of 1 both for the GTIOCA and GTIOCB pins has occurred #1 OABLF Same Time Output Level Low Flag 30 30 read-only 0 No simultaneous generation of 0 both for the GTIOCA and GTIOCB pins has occurred #0 1 A simultaneous generation of 0 both for the GTIOCA and GTIOCB pins has occurred #1 PCF Period Count Function Finish Flag 31 31 read-write 0 No period count function finish has occurred #0 1 A period count function finish has occurred #1 GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write 0x00000000 0xffffffff BD0 GTCCR Buffer Operation Disable 0 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD2 GTADTRA/GTADTRB Registers Buffer Operation Disable 2 2 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD3 GTDVU/GTDVD Registers Buffer Operation Disable 3 3 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 17 read-write 00 No buffer operation #00 01 Single buffer operation (GTCCRA ↔ GTCCRC) #01 Others Double buffer operation (GTCCRA ↔ GTCCRD) true CCRB GTCCRB Buffer Operation 18 19 read-write 00 No buffer operation #00 01 Single buffer operation (GTCCRB ↔ GTCCRE) #01 Others Double buffer operation (GTCCRB ↔ GTCCRE ↔ GTCCRF) true PR GTPR Buffer Operation 20 21 read-write 00 No buffer operation #00 01 Single buffer operation (GTPBR → GTPR) #01 Others Double buffer operation (GTPDBR → GTPBR → GTPR) true CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 22 write-only ADTTA GTADTRA Register Buffer Transfer Timing Select 24 25 read-write 00 In triangle wave, no transfer. In saw-wave mode, no transfer. #00 01 In triangle wave, transfer at crest. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing. #01 10 In triangle wave, transfer at trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing. #10 11 In triangle wave, transfer at both crest and trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing. #11 ADTDA GTADTRA Register Double Buffer Operation 26 26 read-write 0 Single buffer operation (GTADTBRA → GTADTRA) #0 1 Double buffer operation (GTADTDBRA → GTADTBRA → GTADTRA) #1 ADTTB GTADTRB Register Buffer Transfer Timing Select 28 29 read-write 00 In triangle wave, no transfer. In saw-wave mode, no transfer. #00 01 In triangle wave, transfer at crest. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing. #01 10 In triangle wave, transfer at trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing. #10 11 In triangle wave, transfer at both crest and trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing. #11 ADTDB GTADTRB Register Double Buffer Operation 30 30 read-write 0 Single buffer operation (GTADTBRB → GTADTRB) #0 1 Double buffer operation (GTADTDBRB → GTADTRB) #1 GTITC General PWM Timer Interrupt and A/D Conversion Start Request Skipping Setting Register 0x44 32 read-write 0x00000000 0xffffffff ITLA GTCCRA Register Compare Match/Input Capture Interrupt Link 0 0 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function #1 ITLB GTCCRB Register Compare Match/Input Capture Interrupt Link 1 1 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function #1 ITLC GTCCRC Register Compare Match Interrupt Link 2 2 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function #1 ITLD GTCCRD Register Compare Match Interrupt Link 3 3 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function #1 ITLE GTCCRE Register Compare Match Interrupt Link 4 4 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function #1 ITLF GTCCRF Register Compare Match Interrupt Link 5 5 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function #1 IVTC GPTn_OVF/GPTn_UDF Interrupt Skipping Function Select 6 7 read-write 00 Skipping is not performed #00 01 Both overflow and underflow for saw waves and crest for triangle waves are counted and skipped #01 10 Both overflow and underflow for saw waves and trough for triangle waves are counted and skipped #10 10 Both overflow and underflow for saw waves and both crest and trough for triangle waves are counted and skipped #10 IVTT GPTn_OVF/GPTn_UDF Interrupt Skipping Count Select 8 10 read-write 000 Skipping is not performed #000 001 Skipping count of 1 #001 010 Skipping count of 2 #010 011 Skipping count of 3 #011 100 Skipping count of 4 #100 101 Skipping count of 5 #101 110 Skipping count of 6 #110 111 Skipping count of 7 #111 ADTAL GTADTRA Register A/D Conversion Start Request Link 12 12 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function #1 ADTBL GTADTRB Register A/D Conversion Start Request Link 14 14 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function #1 GTCNT General PWM Timer Counter 0x48 32 read-write 0x00000000 0xffffffff GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write 0x0000ffff 0xffffffff GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write 0x0000ffff 0xffffffff GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write 0x0000ffff 0xffffffff GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write 0x0000ffff 0xffffffff GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write 0x0000ffff 0xffffffff GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write 0x0000ffff 0xffffffff GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write 0x0000ffff 0xffffffff GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write 0x0000ffff 0xffffffff GTPDBR General PWM Timer Period Setting Double-Buffer Register 0x6C 32 read-write 0x0000ffff 0xffffffff GTADTRA A/D Conversion Start Request Timing Register A 0x70 32 read-write 0x0000ffff 0xffffffff GTADTBRA A/D Conversion Start Request Timing Buffer Register A 0x74 32 read-write 0x0000ffff 0xffffffff GTADTDBRA A/D Conversion Start Request Timing Double-Buffer Register A 0x78 32 read-write 0x0000ffff 0xffffffff GTADTRB A/D Conversion Start Request Timing Register B 0x7C 32 read-write 0x0000ffff 0xffffffff GTADTBRB A/D Conversion Start Request Timing Buffer Register B 0x80 32 read-write 0x0000ffff 0xffffffff GTADTDBRB A/D Conversion Start Request Timing Double-Buffer Register B 0x84 32 read-write 0x0000ffff 0xffffffff GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write 0x00000000 0xffffffff TDE Negative-Phase Waveform Setting 0 0 read-write 0 GTCCRB is set without using DTDVU and GTDVD #0 1 DTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB #1 TDBUE GTDVU Register Buffer Operation Enable 4 4 read-write 0 GTDVU register buffer operation is disabled #0 1 GTDVU register buffer operation is enabled #1 TDBDE GTDVD Register Buffer Operation Enable 5 5 read-write 0 GTDVD register buffer operation is disabled #0 1 GTDVD register buffer operation is enabled #1 TDFER GTDVD Register Setting 8 8 read-write 0 GTDVU and GTDVD registers are set separately. #0 1 The value written to GTDVU register is automatically set to GTDVD register #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write 0x0000ffff 0xffffffff GTDVD General PWM Timer Dead Time Value Register D 0x90 32 read-write 0x0000ffff 0xffffffff GTDBU General PWM Timer Dead Time Buffer Register U 0x94 32 read-write 0x0000ffff 0xffffffff GTDBD General PWM Timer Dead Time Buffer Register D 0x98 32 read-write 0x0000ffff 0xffffffff GTSOS General PWM Timer Output Protection Function Status Register 0x9C 32 read-only 0x00000000 0xffffffff SOS Output Protection Function Status 0 1 read-only 00 Normal operation #00 01 Protected state (GTCCRA = 0 is set during transfer at trough or crest) #01 10 Protected state (GTCCRA ≥ GTPR is set during transfer at trough) #10 11 Protected state (GTCCRA ≥ GTPR is set during transfer at crest) #11 GTSOTR General PWM Timer Output Protection Function Temporary Release Register 0xA0 32 read-write 0x00000000 0xffffffff SOTR Output Protection Function Temporary Release 0 0 read-write 0 Protected state is not released #0 1 Protected state is released #1 GTADSMR General PWM Timer A/D Conversion Start Request Signal Monitoring Register 0xA4 32 read-write 0x00000000 0xffffffff ADSMS0 A/D Conversion Start Request Signal Monitor 0 Selection 0 1 read-write 00 A/D conversion start request signal generated by the GTADTRA register during up-counting #00 01 A/D conversion start request signal generated by the GTADTRA register during down-counting #01 10 A/D conversion start request signal generated by the GTADTRB register during up-counting #10 11 A/D conversion start request signal generated by the GTADTRB register during down-counting #11 ADSMEN0 A/D Conversion Start Request Signal Monitor 0 Output Enabling 8 8 read-write 0 Output of A/D conversion start request signal monitor 0 is disabled #0 1 Output of A/D conversion start request signal monitor 0 is enabled #1 ADSMS1 A/D Conversion Start Request Signal Monitor 1 Selection 16 17 read-write 00 A/D conversion start request signal generated by the GTADTRA register during up-counting #00 01 A/D conversion start request signal generated by the GTADTRA register during down-counting #01 10 A/D conversion start request signal generated by the GTADTRB register during up-counting #10 11 A/D conversion start request signal generated by the GTADTRB register during down-counting #11 ADSMEN1 A/D Conversion Start Request Signal Monitor 1 Output Enabling 24 24 read-write 0 Output of A/D conversion start request signal monitor 1 is disabled #0 1 Output of A/D conversion start request signal monitor 1 is enabled #1 GTICLF General PWM Timer Inter Channel Logical Operation Function Setting Register 0xB8 32 read-write 0x00000000 0xffffffff ICLFA GTIOCnA Output Logical Operation Function Select 0 2 read-write 000 A (no delay) #000 001 NOT A (no delay) #001 010 C (1PCLKD delay) #010 011 NOT C (1PCLKD delay) #011 100 A AND C (1PCLKD delay) #100 101 A OR C (1PCLKD delay) #101 110 A EXOR C (1PCLKD delay) #110 111 A NOR C (1PCLKD delay) #111 ICLFSELC Inter Channel Signal C Select 4 9 read-write 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b Others Setting prohibited true ICLFB GTIOCnB Output Logical Operation Function Select 16 18 read-write 000 B (no delay) #000 001 NOT B (no delay) #001 010 D (1PCLKD delay) #010 011 NOT D (1PCLKD delay) #011 100 B AND D (1PCLKD delay) #100 101 B OR D (1PCLKD delay) #101 110 B EXOR D (1PCLKD delay) #110 111 B NOR D (1PCLKD delay) #111 ICLFSELD Inter Channel Signal D Select 20 25 read-write 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b Others Setting prohibited true GTPC General PWM Timer Period Count Register 0xBC 32 read-write 0x00000000 0xffffffff PCEN Period Count Function Enable 0 0 read-write 0 Period count function is disabled #0 1 Period count function is enabled #1 ASTP Automatic Stop Function Enable 8 8 read-write 0 Automatic stop function is disabled #0 1 Automatic stop function is enabled #1 PCNT Period Counter 16 27 read-write GTSECSR General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register 0xD0 32 read-write 0x00000000 0xffffffff SECSEL0 Channel 0 Operation Enable Bit Simultaneous Control Channel Select 0 0 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL1 Channel 1 Operation Enable Bit Simultaneous Control Channel Select 1 1 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL2 Channel 2 Operation Enable Bit Simultaneous Control Channel Select 2 2 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL3 Channel 3 Operation Enable Bit Simultaneous Control Channel Select 3 3 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL4 Channel 4 Operation Enable Bit Simultaneous Control Channel Select 4 4 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL5 Channel 5 Operation Enable Bit Simultaneous Control Channel Select 5 5 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 GTSECR General PWM Timer Operation Enable Bit Simultaneous Control Register 0xD4 32 read-write 0x00000000 0xffffffff SBDCE GTCCR Register Buffer Operation Simultaneous Enable 0 0 read-write 0 Disable simultaneous enabling GTCCR buffer operations #0 1 Enable GTCCR register buffer operations simultaneously #1 SBDPE GTPR Register Buffer Operation Simultaneous Enable 1 1 read-write 0 Disable simultaneous enabling GTPR buffer operations #0 1 Enable GTPR register buffer operations simultaneously #1 SBDAE GTADTR Register Buffer Operation Simultaneous Enable 2 2 read-write 0 Disable simultaneous enabling GTADTR buffer operations #0 1 Enable GTADTR register buffer operations simultaneously #1 SBDDE GTDV Register Buffer Operation Simultaneous Enable 3 3 read-write 0 Disable simultaneous enabling GTDV buffer operations #0 1 Enable GTDV register buffer operations simultaneously #1 SBDCD GTCCR Register Buffer Operation Simultaneous Disable 8 8 read-write 0 Disable simultaneous disabling GTCCR buffer operations #0 1 Disable GTCCR register buffer operations simultaneously #1 SBDPD GTPR Register Buffer Operation Simultaneous Disable 9 9 read-write 0 Disable simultaneous disabling GTPR buffer operations #0 1 Disable GTPR register buffer operations simultaneously #1 SBDAD GTADTR Register Buffer Operation Simultaneous Disable 10 10 read-write 0 Disable simultaneous disabling GTADTR buffer operations #0 1 Disable GTADTR register buffer operations simultaneously #1 SBDDD GTDV Register Buffer Operation Simultaneous Disable 11 11 read-write 0 Disable simultaneous disabling GTDV buffer operations #0 1 Disable GTDV register buffer operations simultaneously #1 SPCE Period Count Function Simultaneous Enable 16 16 read-write 0 Disable simultaneous enabling period count function #0 1 Enable period count function simultaneously #1 SPCD Period Count Function Simultaneous Disable 24 24 read-write 0 Disable simultaneous disabling period count function #0 1 Disable period count function simultaneously #1 GPT16E1 General PWM 16-bit Timer 1 0x40169100 GPT16E2 General PWM 16-bit Timer 2 0x40169200 GPT16E3 General PWM 16-bit Timer 3 0x40169300 GPT16E4 General PWM 16-bit Timer 4 0x40169400 GPT16E5 General PWM 16-bit Timer 5 0x40169500 GPT_OPS Output Phase Switching Controller 0x40169A00 0x00 4 registers OPSCR Output Phase Switching Control Register 0x00 32 read-write 0x00000000 0xffffffff UF 0 0 read-write VF 1 1 read-write WF 2 2 read-write U Input U-Phase Monitor 4 4 read-only V Input V-Phase Monitor 5 5 read-only W Input W-Phase Monitor 6 6 read-only EN Output Phase Enable 8 8 read-write 0 Do not output (Hi-Z external pin) #0 1 Output #1 FB External Feedback Signal Enable 16 16 read-write 0 Select the external input #0 1 Select the soft setting (OPSCR.UF, VF, WF) #1 P Positive-Phase Output (P) Control 17 17 read-write 0 Level signal output #0 1 PWM signal output #1 N Negative-Phase Output (N) Control 18 18 read-write 0 Level signal output #0 1 PWM signal output #1 INV Output Phase Invert Control 19 19 read-write 0 Positive logic (active-high) output #0 1 Negative logic (active-low) output #1 RV Output Phase Rotation Direction Reversal Control 20 20 read-write 0 Positive rotation #0 1 Reverse rotation #1 ALIGN Input Phase Alignment 21 21 read-write 0 Input phase aligned to PCLKD #0 1 Input phase aligned to the falling edge of PWM #1 GRP Output Disabled Source Selection 24 25 read-write GODF Group Output Disable Function 26 26 read-write 0 This bit function is ignored #0 1 Group disable clears the OPSCR.EN bit #1 NFEN External Input Noise Filter Enable 29 29 read-write 0 Do not use a noise filter on the external input #0 1 Use a noise filter on the external input #1 NFCS External Input Noise Filter Clock Selection 30 31 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 ADC120 12-bit A/D Converter 0x40170000 0x00 2 registers 0x04 9 registers 0x0E 24 registers 0x28 10 registers 0x36 6 registers 0x40 2 registers 0x66 2 registers 0x7A 1 registers 0x7C 1 registers 0x80 2 registers 0x84 4 registers 0x8C 1 registers 0x90 21 registers 0xA6 1 registers 0xA8 5 registers 0xB0 33 registers 0xD2 1 registers 0xDD 6 registers 0xE4 5 registers 0xEB 3 registers 0x1A0 4 registers 0x1B0 2 registers ADCSR A/D Control Register 0x000 16 read-write 0x0000 0xffff DBLANS Double Trigger Channel Select 0 4 read-write GBADIE Group B Scan End Interrupt and ELC Event Enable 6 6 read-write 0 Disable ADC120_GBADI interrupt generation on group B scan completion. #0 1 Enable ADC120_GBADI interrupt generation on group B scan completion. #1 DBLE Double Trigger Mode Select 7 7 read-write 0 Deselect double-trigger mode. #0 1 Select double-trigger mode. #1 EXTRG Trigger Select 8 8 read-write 0 Start A/D conversion by the synchronous trigger (ELC). #0 1 Start A/D conversion by the asynchronous trigger (ADTRG0). #1 TRGE Trigger Start Enable 9 9 read-write 0 Disable A/D conversion to be started by the synchronous or asynchronous trigger #0 1 Enable A/D conversion to be started by the synchronous or asynchronous trigger #1 ADCS Scan Mode Select 13 14 read-write 00 Single scan mode #00 01 Group scan mode #01 10 Continuous scan mode #10 11 Setting prohibited #11 ADST A/D Conversion Start 15 15 read-write 0 Stop A/D conversion process. #0 1 Start A/D conversion process. #1 ADANSA0 A/D Channel Select Register A0 0x004 16 read-write 0x0000 0xffff ANSA00 A/D Conversion Channels Select 0 0 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA01 A/D Conversion Channels Select 1 1 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA02 A/D Conversion Channels Select 2 2 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA03 A/D Conversion Channels Select 3 3 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA04 A/D Conversion Channels Select 4 4 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA05 A/D Conversion Channels Select 5 5 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA06 A/D Conversion Channels Select 6 6 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA07 A/D Conversion Channels Select 7 7 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA08 A/D Conversion Channels Select 8 8 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA09 A/D Conversion Channels Select 9 9 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA10 A/D Conversion Channels Select 10 10 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA11 A/D Conversion Channels Select 11 11 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA12 A/D Conversion Channels Select 12 12 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA13 A/D Conversion Channels Select 13 13 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA14 A/D Conversion Channels Select 14 14 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA15 A/D Conversion Channels Select 15 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADANSA1 A/D Channel Select Register A1 0x006 16 read-write 0x0000 0xffff ANSA16 A/D Conversion Channels Select 0 0 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA17 A/D Conversion Channels Select 1 1 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA18 A/D Conversion Channels Select 2 2 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA19 A/D Conversion Channels Select 3 3 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA20 A/D Conversion Channels Select 4 4 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA21 A/D Conversion Channels Select 5 5 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA22 A/D Conversion Channels Select 6 6 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA23 A/D Conversion Channels Select 7 7 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA24 A/D Conversion Channels Select 8 8 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA25 A/D Conversion Channels Select 9 9 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA26 A/D Conversion Channels Select 10 10 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA27 A/D Conversion Channels Select 11 11 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA28 A/D Conversion Channels Select 12 12 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA29 A/D Conversion Channels Select 13 13 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA30 A/D Conversion Channels Select 14 14 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA31 A/D Conversion Channels Select 15 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADADS0 A/D-Converted Value Addition/Average Channel Select Register 0 0x008 16 read-write 0x0000 0xffff ADS00 A/D-Converted Value Addition/Average Channel Select 0 0 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS01 A/D-Converted Value Addition/Average Channel Select 1 1 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS02 A/D-Converted Value Addition/Average Channel Select 2 2 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS03 A/D-Converted Value Addition/Average Channel Select 3 3 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS04 A/D-Converted Value Addition/Average Channel Select 4 4 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS05 A/D-Converted Value Addition/Average Channel Select 5 5 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS06 A/D-Converted Value Addition/Average Channel Select 6 6 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS07 A/D-Converted Value Addition/Average Channel Select 7 7 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS08 A/D-Converted Value Addition/Average Channel Select 8 8 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS09 A/D-Converted Value Addition/Average Channel Select 9 9 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS10 A/D-Converted Value Addition/Average Channel Select 10 10 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS11 A/D-Converted Value Addition/Average Channel Select 11 11 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS12 A/D-Converted Value Addition/Average Channel Select 12 12 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS13 A/D-Converted Value Addition/Average Channel Select 13 13 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS14 A/D-Converted Value Addition/Average Channel Select 14 14 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS15 A/D-Converted Value Addition/Average Channel Select 15 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADADS1 A/D-Converted Value Addition/Average Channel Select Register 1 0x00A 16 read-write 0x0000 0xffff ADS16 A/D-Converted Value Addition/Average Channel Select 0 0 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS17 A/D-Converted Value Addition/Average Channel Select 1 1 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS18 A/D-Converted Value Addition/Average Channel Select 2 2 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS19 A/D-Converted Value Addition/Average Channel Select 3 3 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS20 A/D-Converted Value Addition/Average Channel Select 4 4 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS21 A/D-Converted Value Addition/Average Channel Select 5 5 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS22 A/D-Converted Value Addition/Average Channel Select 6 6 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS23 A/D-Converted Value Addition/Average Channel Select 7 7 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS24 A/D-Converted Value Addition/Average Channel Select 8 8 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS25 A/D-Converted Value Addition/Average Channel Select 9 9 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS26 A/D-Converted Value Addition/Average Channel Select 10 10 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS27 A/D-Converted Value Addition/Average Channel Select 11 11 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS28 A/D-Converted Value Addition/Average Channel Select 12 12 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS29 A/D-Converted Value Addition/Average Channel Select 13 13 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS30 A/D-Converted Value Addition/Average Channel Select 14 14 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS31 A/D-Converted Value Addition/Average Channel Select 15 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADADC A/D-Converted Value Addition/Average Count Select Register 0x00C 8 read-write 0x00 0xff ADC Addition/Average Count Select 0 2 read-write 000 1-time conversion (no addition, same as normal conversion) #000 001 2-time conversion (1 addition) #001 010 3-time conversion (2 additions) #010 011 4-time conversion (3 additions) #011 101 16-time conversion (15 additions) #101 Others Setting prohibited true AVEE Average Mode Select 7 7 read-write 0 Enable addition mode #0 1 Enable average mode #1 ADCER A/D Control Extended Register 0x00E 16 read-write 0x0000 0xffff ADPRC 1 2 read-write 00 12-bit accuracy #00 01 10-bit accuracy #01 10 8-bit accuracy #10 11 Setting prohibited #11 ACE A/D Data Register Automatic Clearing Enable 5 5 read-write 0 Disable automatic clearing #0 1 Enable automatic clearing #1 DIAGVAL Self-Diagnosis Conversion Voltage Select 8 9 read-write 00 Setting prohibited when self-diagnosis is enabled #00 01 0 volts #01 10 Reference voltage × 1/2 #10 11 Reference voltage #11 DIAGLD Self-Diagnosis Mode Select 10 10 read-write 0 Select rotation mode for self-diagnosis voltage #0 1 Select mixed mode for self-diagnosis voltage #1 DIAGM Self-Diagnosis Enable 11 11 read-write 0 Disable ADC12 self-diagnosis #0 1 Enable ADC12 self-diagnosis #1 ADRFMT A/D Data Register Format Select 15 15 read-write 0 Select right-justified for the A/D data register format #0 1 Select left-justified for the A/D data register format #1 ADSTRGR A/D Conversion Start Trigger Select Register 0x010 16 read-write 0x0000 0xffff TRSB A/D Conversion Start Trigger Select for Group B 0 5 read-write TRSA A/D Conversion Start Trigger Select 8 13 read-write ADEXICR A/D Conversion Extended Input Control Registers 0x012 16 read-write 0x0000 0xffff TSSAD Temperature Sensor Output A/D-Converted Value Addition/Average Mode Select 0 0 read-write 0 Do not select addition/average mode for temperature sensor output. #0 1 Select addition/average mode for temperature sensor output. #1 OCSAD Internal Reference Voltage A/D-Converted Value Addition/Average Mode Select 1 1 read-write 0 Do not select addition/average mode for internal reference voltage. #0 1 Select addition/average mode for internal reference voltage. #1 TSSA Temperature Sensor Output A/D Conversion Select 8 8 read-write 0 Disable A/D conversion of temperature sensor output #0 1 Enable A/D conversion of temperature sensor output #1 OCSA Internal Reference Voltage A/D Conversion Select 9 9 read-write 0 Disable A/D conversion of internal reference voltage #0 1 Enable A/D conversion of internal reference voltage #1 TSSB Temperature Sensor Output A/D Conversion Select for Group B 10 10 read-write 0 Disable A/D conversion of temperature sensor output #0 1 Enable A/D conversion of temperature sensor output #1 OCSB Internal Reference Voltage A/D Conversion Select for Group B 11 11 read-write 0 Disable A/D conversion of internal reference voltage #0 1 Enable A/D conversion of internal reference voltage #1 ADANSB0 A/D Channel Select Register B0 0x014 16 read-write 0x0000 0xffff ANSB00 A/D Conversion Channels Select 0 0 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB01 A/D Conversion Channels Select 1 1 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB02 A/D Conversion Channels Select 2 2 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB03 A/D Conversion Channels Select 3 3 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB04 A/D Conversion Channels Select 4 4 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB05 A/D Conversion Channels Select 5 5 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB06 A/D Conversion Channels Select 6 6 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB07 A/D Conversion Channels Select 7 7 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB08 A/D Conversion Channels Select 8 8 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB09 A/D Conversion Channels Select 9 9 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB10 A/D Conversion Channels Select 10 10 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB11 A/D Conversion Channels Select 11 11 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB12 A/D Conversion Channels Select 12 12 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB13 A/D Conversion Channels Select 13 13 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB14 A/D Conversion Channels Select 14 14 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB15 A/D Conversion Channels Select 15 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADANSB1 A/D Channel Select Register B1 0x016 16 read-write 0x0000 0xffff ANSB16 A/D Conversion Channels Select 0 0 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB17 A/D Conversion Channels Select 1 1 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB18 A/D Conversion Channels Select 2 2 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB19 A/D Conversion Channels Select 3 3 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB20 A/D Conversion Channels Select 4 4 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB21 A/D Conversion Channels Select 5 5 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB22 A/D Conversion Channels Select 6 6 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB23 A/D Conversion Channels Select 7 7 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB24 A/D Conversion Channels Select 8 8 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB25 A/D Conversion Channels Select 9 9 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB26 A/D Conversion Channels Select 10 10 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB27 A/D Conversion Channels Select 11 11 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB28 A/D Conversion Channels Select 12 12 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB29 A/D Conversion Channels Select 13 13 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB30 A/D Conversion Channels Select 14 14 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB31 A/D Conversion Channels Select 15 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADDBLDR A/D Data Duplexing Register 0x018 16 read-only 0x0000 0xffff ADDBLDR Converted Value 15 to 0 0 15 read-only ADTSDR A/D Temperature Sensor Data Register 0x01A 16 read-only 0x0000 0xffff ADTSDR Converted Value 15 to 0 0 15 read-only ADOCDR A/D Internal Reference Voltage Data Register 0x01C 16 read-only 0x0000 0xffff ADOCDR Converted Value 15 to 0 0 15 read-only ADRD A/D Self-Diagnosis Data Register 0x01E 16 read-only 0x0000 0xffff AD Converted Value 11 to 0 0 11 read-only DIAGST Self-Diagnosis Status 14 15 read-only 00 Self-diagnosis not executed after power-on. #00 01 Self-diagnosis was executed using the 0 V voltage. #01 10 Self-diagnosis was executed using the reference voltage × 1/2. #10 11 Self-diagnosis was executed using the reference voltage . #11 3 0x2 0-2 ADDR%s A/D Data Registers %s 0x020 16 read-only 0x0000 0xffff ADDR Converted Value 15 to 0 0 15 read-only 5 0x2 4-8 ADDR%s A/D Data Registers %s 0x028 16 read-only 0x0000 0xffff ADDR Converted Value 15 to 0 0 15 read-only 3 0x2 11-13 ADDR%s A/D Data Registers %s 0x036 16 read-only 0x0000 0xffff ADDR Converted Value 15 to 0 0 15 read-only ADDR16 A/D Data Registers 16 0x040 16 read-only 0x0000 0xffff ADDR Converted Value 15 to 0 0 15 read-only ADSHCR A/D Sample and Hold Circuit Control Register 0x066 16 read-write 0x0018 0xffff SSTSH Channel-Dedicated Sample-and-Hold Circuit Sampling Time Setting 0 7 read-write SHANS Channel-Dedicated Sample-and-Hold Circuit Bypass Select 8 10 read-write 0 Bypass the circuits #0 1 Use the circuits #1 ADDISCR A/D Disconnection Detection Control Register 0x07A 8 read-write 0x00 0xff ADNDIS Disconnection Detection Assist Setting 0 3 read-write 0x0 The disconnection detection assist function is disabled 0x0 0x1 Setting prohibited 0x1 Others The number of states for the discharge or precharge period. true PCHG Precharge/discharge select 4 4 read-write 0 Discharge #0 1 Precharge #1 ADSHMSR A/D Sample and Hold Operation Mode Selection Register 0x07C 8 read-write 0x00 0xff SHMD Sampling Operation Selection 0 0 read-write 0 Disable continuous sampling function #0 1 Enable continuous sampling function #1 ADGSPCR A/D Group Scan Priority Control Register 0x080 16 read-write 0x0000 0xffff PGS Group Priority Operation Setting 0 0 read-write 0 Operate without group priority control. #0 1 Operate with group priority control. #1 GBRSCN Lower-Priority Group Restart Setting 1 1 read-write 0 Disable rescanning of the group that was stopped in group priority operation #0 1 Enable rescanning of the group that was stopped in group priority operation. #1 LGRRS Enabled only when PGS = 1 and GBRSCN = 1. 14 14 read-write 0 Start rescanning from the first channel for scanning #0 1 Start rescanning from the channel for which A/D conversion is not completed. #1 GBRP Single Scan Continuous Start 15 15 read-write 0 Single scan is not continuously activated. #0 1 Single scan for the group with the lower-priority is continuously activated. #1 ADDBLDRA A/D Data Duplexing Register A 0x084 16 read-only 0x0000 0xffff ADDBLDR Converted Value 15 to 0 0 15 read-only ADDBLDRB A/D Data Duplexing Register B 0x086 16 read-only 0x0000 0xffff ADDBLDR Converted Value 15 to 0 0 15 read-only ADWINMON A/D Compare Function Window A/B Status Monitor Register 0x08C 8 read-only 0x00 0xff MONCOMB Combination Result Monitor 0 0 read-only 0 Window A/B composite conditions are not met. #0 1 Window A/B composite conditions are met. #1 MONCMPA Comparison Result Monitor A 4 4 read-only 0 Window A comparison conditions are not met. #0 1 Window A comparison conditions are met. #1 MONCMPB Comparison Result Monitor B 5 5 read-only 0 Window B comparison conditions are not met. #0 1 Window B comparison conditions are met. #1 ADCMPCR A/D Compare Function Control Register 0x090 16 read-write 0x0000 0xffff CMPAB Window A/B Composite Conditions Setting 0 1 read-write 00 Output ADC120_WCMPM when window A OR window B comparison conditions are met. Otherwise, output ADC120_WCMPUM. #00 01 Output ADC120_WCMPM when window A EXOR window B comparison conditions are met. Otherwise, output ADC120_WCMPUM. #01 10 Output ADC120_WCMPM when window A AND window B comparison conditions are met. Otherwise, output ADC120_WCMPUM. #10 11 Setting prohibited. #11 CMPBE Compare Window B Operation Enable 9 9 read-write 0 Disable compare window B operation. Disable ADC120_WCMPM and ADC120_WCMPUM outputs. #0 1 Enable compare window B operation. #1 CMPAE Compare Window A Operation Enable 11 11 read-write 0 Disable compare window A operation. Disable ADC120_WCMPM and ADC120_WCMPUM outputs. #0 1 Enable compare window A operation. #1 CMPBIE Compare B Interrupt Enable 13 13 read-write 0 Disable ADC120_CMPBI interrupt when comparison conditions (window B) are met. #0 1 Enable ADC120_CMPBI interrupt when comparison conditions (window B) are met. #1 WCMPE Window Function Setting 14 14 read-write 0 Disable window function Window A and window B operate as a comparator to compare the single value on the lower side with the A/D conversion result. #0 1 Enable window function Window A and window B operate as a comparator to compare the two values on the upper and lower sides with the A/D conversion result. #1 CMPAIE Compare A Interrupt Enable 15 15 read-write 0 Disable ADC120_CMPAI interrupt when comparison conditions (window A) are met. #0 1 Enable ADC120_CMPAI interrupt when comparison conditions (window A) are met. #1 ADCMPANSER A/D Compare Function Window A Extended Input Select Register 0x092 8 read-write 0x00 0xff CMPTSA Temperature Sensor Output Compare Select 0 0 read-write 0 Exclude the temperature sensor output from the compare Window A target range. #0 1 Include the temperature sensor output in the compare Window A target range. #1 CMPOCA Internal Reference Voltage Compare Select 1 1 read-write 0 Exclude the internal reference voltage from the compare Window A target range. #0 1 Include the internal reference voltage in the compare Window A target range. #1 ADCMPLER A/D Compare Function Window A Extended Input Comparison Condition Setting Register 0x093 8 read-write 0x00 0xff CMPLTSA Compare Window A Temperature Sensor Output Comparison Condition Select 0 0 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0) : ADCMPDR0 value > A/D-converted valueCompare Window A Temperature Sensor Output Comparison Condition Select When window function is enabled (ADCMPCR.WCMPE = 1) : Compare Window A Temperature Sensor Output Comparison ConditionA/D-converted value < ADCMPDR0 value, or A/D-converted value > ADCMPDR1 value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0) : ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1) : ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLOCA Compare Window A Internal Reference Voltage Comparison Condition Select 1 1 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0) : ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or A/D-converted value > ADCMPDR1 value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 ADCMPANSR0 A/D Compare Function Window A Channel Select Register 0 0x094 16 read-write 0x0000 0xffff CMPCHA00 Compare Window A Channel Select 0 0 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA01 Compare Window A Channel Select 1 1 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA02 Compare Window A Channel Select 2 2 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA03 Compare Window A Channel Select 3 3 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA04 Compare Window A Channel Select 4 4 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA05 Compare Window A Channel Select 5 5 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA06 Compare Window A Channel Select 6 6 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA07 Compare Window A Channel Select 7 7 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA08 Compare Window A Channel Select 8 8 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA09 Compare Window A Channel Select 9 9 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA10 Compare Window A Channel Select 10 10 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA11 Compare Window A Channel Select 11 11 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA12 Compare Window A Channel Select 12 12 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA13 Compare Window A Channel Select 13 13 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA14 Compare Window A Channel Select 14 14 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA15 Compare Window A Channel Select 15 15 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 ADCMPANSR1 A/D Compare Function Window A Channel Select Register 1 0x096 16 read-write 0x0000 0xffff CMPCHA16 Compare Window A Channel Select 0 0 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA17 Compare Window A Channel Select 1 1 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA18 Compare Window A Channel Select 2 2 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA19 Compare Window A Channel Select 3 3 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA20 Compare Window A Channel Select 4 4 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA21 Compare Window A Channel Select 5 5 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA22 Compare Window A Channel Select 6 6 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA23 Compare Window A Channel Select 7 7 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA24 Compare Window A Channel Select 8 8 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA25 Compare Window A Channel Select 9 9 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA26 Compare Window A Channel Select 10 10 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA27 Compare Window A Channel Select 11 11 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA28 Compare Window A Channel Select 12 12 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA29 Compare Window A Channel Select 13 13 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA30 Compare Window A Channel Select 14 14 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA31 Compare Window A Channel Select 15 15 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 ADCMPLR0 A/D Compare Function Window A Comparison Condition Setting Register 0 0x098 16 read-write 0x0000 0xffff CMPLCHA00 Compare Window A Comparison Condition Select 0 0 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA01 Compare Window A Comparison Condition Select 1 1 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA02 Compare Window A Comparison Condition Select 2 2 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA03 Compare Window A Comparison Condition Select 3 3 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA04 Compare Window A Comparison Condition Select 4 4 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA05 Compare Window A Comparison Condition Select 5 5 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA06 Compare Window A Comparison Condition Select 6 6 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA07 Compare Window A Comparison Condition Select 7 7 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA08 Compare Window A Comparison Condition Select 8 8 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA09 Compare Window A Comparison Condition Select 9 9 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA10 Compare Window A Comparison Condition Select 10 10 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA11 Compare Window A Comparison Condition Select 11 11 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA12 Compare Window A Comparison Condition Select 12 12 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA13 Compare Window A Comparison Condition Select 13 13 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA14 Compare Window A Comparison Condition Select 14 14 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA15 Compare Window A Comparison Condition Select 15 15 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 ADCMPLR1 A/D Compare Function Window A Comparison Condition Setting Register 1 0x09A 16 read-write 0x0000 0xffff CMPLCHA16 Compare Window A Comparison Condition Select 0 0 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA17 Compare Window A Comparison Condition Select 1 1 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA18 Compare Window A Comparison Condition Select 2 2 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA19 Compare Window A Comparison Condition Select 3 3 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA20 Compare Window A Comparison Condition Select 4 4 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA21 Compare Window A Comparison Condition Select 5 5 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA22 Compare Window A Comparison Condition Select 6 6 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA23 Compare Window A Comparison Condition Select 7 7 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA24 Compare Window A Comparison Condition Select 8 8 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA25 Compare Window A Comparison Condition Select 9 9 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA26 Compare Window A Comparison Condition Select 10 10 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA27 Compare Window A Comparison Condition Select 11 11 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA28 Compare Window A Comparison Condition Select 12 12 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA29 Compare Window A Comparison Condition Select 13 13 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA30 Compare Window A Comparison Condition Select 14 14 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA31 Compare Window A Comparison Condition Select 15 15 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 2 0x2 0-1 ADCMPDR%s A/D Compare Function Window A Lower-Side/Upper-Side Level Setting Register 0x09C 16 read-write 0x0000 0xffff ADCMPSR0 A/D Compare Function Window A Channel Status Register 0 0x0A0 16 read-write 0x0000 0xffff CMPSTCHA00 Compare Window A Flag 0 0 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA01 Compare Window A Flag 1 1 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA02 Compare Window A Flag 2 2 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA03 Compare Window A Flag 3 3 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA04 Compare Window A Flag 4 4 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA05 Compare Window A Flag 5 5 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA06 Compare Window A Flag 6 6 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA07 Compare Window A Flag 7 7 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA08 Compare Window A Flag 8 8 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA09 Compare Window A Flag 9 9 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA10 Compare Window A Flag 10 10 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA11 Compare Window A Flag 11 11 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA12 Compare Window A Flag 12 12 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA13 Compare Window A Flag 13 13 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA14 Compare Window A Flag 14 14 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA15 Compare Window A Flag 15 15 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPSR1 A/D Compare Function Window A Channel Status Register1 0x0A2 16 read-write 0x0000 0xffff CMPSTCHA16 Compare Window A Flag 0 0 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA17 Compare Window A Flag 1 1 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA18 Compare Window A Flag 2 2 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA19 Compare Window A Flag 3 3 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA20 Compare Window A Flag 4 4 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA21 Compare Window A Flag 5 5 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA22 Compare Window A Flag 6 6 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA23 Compare Window A Flag 7 7 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA24 Compare Window A Flag 8 8 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA25 Compare Window A Flag 9 9 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA26 Compare Window A Flag 10 10 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA27 Compare Window A Flag 11 11 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA28 Compare Window A Flag 12 12 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA29 Compare Window A Flag 13 13 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA30 Compare Window A Flag 14 14 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA31 Compare Window A Flag 15 15 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPSER A/D Compare Function Window A Extended Input Channel Status Register 0x0A4 8 read-write 0x00 0xff CMPSTTSA Compare Window A Temperature Sensor Output Compare Flag 0 0 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTOCA Compare Window A Internal Reference Voltage Compare Flag 1 1 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPBNSR A/D Compare Function Window B Channel Select Register 0x0A6 8 read-write 0x00 0xff CMPCHB Compare Window B Channel Select 0 5 read-write CMPLB Compare Window B Comparison Condition Setting 7 7 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADWINLLB value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADWINLLB value, or ADWINULB value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADWINLLB value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADWINLLB value < A/D-converted value < ADWINULB value #1 ADWINLLB A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register 0x0A8 16 read-write 0x0000 0xffff ADWINULB A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register 0x0AA 16 read-write 0x0000 0xffff ADCMPBSR A/D Compare Function Window B Status Register 0x0AC 8 read-write 0x00 0xff CMPSTB Compare Window B Flag 0 0 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 16 0x2 0-15 ADBUF%s A/D Data Buffer Registers %s 0x0B0 16 read-only 0x0000 0xffff ADBUF Converted Value 15 to 0 0 15 read-only ADBUFEN A/D Data Buffer Enable Register 0x0D0 8 read-write 0x00 0xff BUFEN Data Buffer Enable 0 0 read-write 0 The data buffer is not used. #0 1 The data buffer is used. #1 ADBUFPTR A/D Data Buffer Pointer Register 0x0D2 8 read-write 0x00 0xff BUFPTR Data Buffer Pointer 0 3 read-write PTROVF Pointer Overflow Flag 4 4 read-write 0 The data buffer pointer has not overflowed. #0 1 The data buffer pointer has overflowed. #1 ADSSTRL A/D Sampling State Register 0x0DD 8 read-write 0x0b 0xff SST Sampling Time Setting 0 7 read-write ADSSTRT A/D Sampling State Register 0x0DE 8 read-write 0x0b 0xff SST Sampling Time Setting 0 7 read-write ADSSTRO A/D Sampling State Register 0x0DF 8 read-write 0x0b 0xff SST Sampling Time Setting 0 7 read-write 3 0x1 0-2 ADSSTR%s A/D Sampling State Register 0x0E0 8 read-write 0x0b 0xff SST Sampling Time Setting 0 7 read-write 5 0x1 4-8 ADSSTR%s A/D Sampling State Register 0x0E4 8 read-write 0x0b 0xff SST Sampling Time Setting 0 7 read-write 3 0x1 11-13 ADSSTR%s A/D Sampling State Register 0x0EB 8 read-write 0x0b 0xff SST Sampling Time Setting 0 7 read-write ADPGACR A/D Programmable Gain Amplifier Control Register 0x1A0 16 read-write 0x0000 0xffff P000SEL0 0 0 read-write 0 Do not output the signal in a path bypassing the PGA amplifier #0 1 Output the signal in a path bypassing the PGA amplifier #1 P000SEL1 1 1 read-write 0 Do not output the signal in a path through the PGA amplifier #0 1 Output the signal in a path through the PGA amplifier #1 P000ENAMP 2 2 read-write 0 Do not use the PGA amplifier #0 1 Use the PGA amplifier #1 P000GEN PGA P000 Gain Setting Enable 3 3 read-write 0 Disable gain setting #0 1 Enable gain setting #1 P001SEL0 PGA P001 Amplifier Bypass Enable 4 4 read-write 0 Do not output the signal in a path bypassing the PGA amplifier #0 1 Output the signal in a path bypassing the PGA amplifier #1 P001SEL1 PGA P001 Amplifier Transit Enable 5 5 read-write 0 Do not output the signal in a path through the PGA amplifier #0 1 Output the signal in a path through the PGA amplifier #1 P001ENAMP PGA P001 Amplifier Enable 6 6 read-write 0 Do not use the PGA amplifier #0 1 Use the PGA amplifier #1 P001GEN PGA P001 Gain Setting Enable 7 7 read-write 0 Disable gain setting #0 1 Enable gain setting #1 P002SEL0 PGA P002 Amplifier Bypass Enable 8 8 read-write 0 Do not output the signal in a path bypassing the PGA amplifier #0 1 Output the signal in a path bypassing the PGA amplifier #1 P002SEL1 PGA P002 Amplifier Transit Enable 9 9 read-write 0 Do not output the signal in a path through the PGA amplifier #0 1 Output the signal in a path through the PGA amplifier #1 P002ENAMP PGA P002 Amplifier Enable 10 10 read-write 0 Do not use the PGA amplifier #0 1 Use the PGA amplifier #1 P002GEN PGA P002 Gain Setting Enable 11 11 read-write 0 Disable gain setting #0 1 Enable gain setting #1 ADPGAGS0 A/D Programmable Gain Amplifier Gain Setting Register 0 0x1A2 16 read-write 0x0000 0xffff P000GAIN PGA P000 Gain Setting 0 3 read-write 0x0 × 2.000 0x0 0x1 When pseudo-differential input is disabled (ADPGADCR0.PnDEN = 0): × 2.500 When pseudo-differential input is enabled (ADPGADCR0.PnDEN = 1): × 1.500 0x1 0x2 × 2.667 0x2 0x3 × 2.857 0x3 0x4 × 3.007 0x4 0x5 When pseudo-differential input is disabled (ADPGADCR0.PnDEN = 0): × 3.333 When pseudo-differential input is enabled (ADPGADCR0.PnDEN = 1): × 2.333 0x5 0x6 × 3.636 0x6 0x7 × 4.000 0x7 0x8 × 4.444 0x8 0x9 When pseudo-differential input is disabled (ADPGADCR0.PnDEN = 0): × 5.000 When pseudo-differential input is enabled (ADPGADCR0.PnDEN = 1): × 4.000 0x9 0xA × 5.714 0xa 0xB When pseudo-differential input is disabled (ADPGADCR0.PnDEN = 0): × 6.667 When pseudo-differential input is enabled (ADPGADCR0.PnDEN = 1): × 5.667 0xb 0xC × 8.000 0xc 0xD × 10.000 0xd 0xE × 13.333 0xe Others Settings are prohibited true P001GAIN PGA P001 Gain Setting 4 7 read-write 0x0 × 2.000 0x0 0x1 When pseudo-differential input is disabled (ADPGADCR0.PnDEN = 0): × 2.500 When pseudo-differential input is enabled (ADPGADCR0.PnDEN = 1): × 1.500 0x1 0x2 × 2.667 0x2 0x3 × 2.857 0x3 0x4 × 3.007 0x4 0x5 When pseudo-differential input is disabled (ADPGADCR0.PnDEN = 0): × 3.333 When pseudo-differential input is enabled (ADPGADCR0.PnDEN = 1): × 2.333 0x5 0x6 × 3.636 0x6 0x7 × 4.000 0x7 0x8 × 4.444 0x8 0x9 When pseudo-differential input is disabled (ADPGADCR0.PnDEN = 0): × 5.000 When pseudo-differential input is enabled (ADPGADCR0.PnDEN = 1): × 4.000 0x9 0xA × 5.714 0xa 0xB When pseudo-differential input is disabled (ADPGADCR0.PnDEN = 0): × 6.667 When pseudo-differential input is enabled (ADPGADCR0.PnDEN = 1): × 5.667 0xb 0xC × 8.000 0xc 0xD × 10.000 0xd 0xE × 13.333 0xe Others Settings are prohibited true P002GAIN PGA P002 Gain Setting 8 11 read-write 0x0 × 2.000 0x0 0x1 When pseudo-differential input is disabled (ADPGADCR0.PnDEN = 0): × 2.500 When pseudo-differential input is enabled (ADPGADCR0.PnDEN = 1): × 1.500 0x1 0x2 × 2.667 0x2 0x3 × 2.857 0x3 0x4 × 3.007 0x4 0x5 When pseudo-differential input is disabled (ADPGADCR0.PnDEN = 0): × 3.333 When pseudo-differential input is enabled (ADPGADCR0.PnDEN = 1): × 2.333 0x5 0x6 × 3.636 0x6 0x7 × 4.000 0x7 0x8 × 4.444 0x8 0x9 When pseudo-differential input is disabled (ADPGADCR0.PnDEN = 0): × 5.000 When pseudo-differential input is enabled (ADPGADCR0.PnDEN = 1): × 4.000 0x9 0xA × 5.714 0xa 0xB When pseudo-differential input is disabled (ADPGADCR0.PnDEN = 0): × 6.667 When pseudo-differential input is enabled (ADPGADCR0.PnDEN = 1): × 5.667 0xb 0xC × 8.000 0xc 0xD × 10.000 0xd 0xE × 13.333 0xe Others Settings are prohibited true ADPGADCR0 A/D Programmable Gain Amplifier Pseudo-Differential Input Control Register 0x1B0 16 read-write 0x0888 0xffff P000DG P000 Pseudo-Differential Input Gain Setting 0 1 read-write 00 × 1.5 #00 01 × 2.333 #01 10 × 4.0 #10 11 × 5.667 #11 P000DEN P000 Pseudo-Differential Input Enable 3 3 read-write 0 Disable pseudo-differential input #0 1 Enable pseudo-differential input #1 P001DG P001 Pseudo-Differential Input Gain Setting 4 5 read-write 00 × 1.5 #00 01 × 2.333 #01 10 × 4.0 #10 11 × 5.667 #11 P001DEN P001 Pseudo-Differential Input Enable 7 7 read-write 0 Disable pseudo-differential input #0 1 Enable pseudo-differential input #1 P002DG P002 Pseudo-Differential Input Gain Setting 8 9 read-write 00 × 1.5 #00 01 × 2.333 #01 10 × 4.0 #10 11 × 5.667 #11 P002DEN P002 Pseudo-Differential Input Enable 11 11 read-write 0 Disable pseudo-differential input #0 1 Enable pseudo-differential input #1 DAC12 12-bit D/A converter 0x40171000 0x00 7 registers 0x08 1 registers 0x1C 1 registers 0x10C0 1 registers 2 0x02 0-1 DADR%s D/A Data Register %s 0x00 16 read-write 0x0000 0xffff DACR D/A Control Register 0x04 8 read-write 0x1f 0xff DAE D/A Enable 5 5 read-write 0 Control D/A conversion of channels 0 and 1 individually #0 1 Control D/A conversion of channels 0 and 1 collectively #1 DAOE0 D/A Output Enable 0 6 6 read-write 0 Disable analog output of channel 0 (DA0) #0 1 Enable D/A conversion of channel 0 (DA0) #1 DAOE1 D/A Output Enable 1 7 7 read-write 0 Disable analog output of channel 1 (DA1) #0 1 Enable D/A conversion of channel 1 (DA1) #1 DADPR DADRn Format Select Register 0x05 8 read-write 0x00 0xff DPSEL DADRn Format Select 7 7 read-write 0 Right-justified format #0 1 Left-justified format #1 DAADSCR D/A A/D Synchronous Start Control Register 0x06 8 read-write 0x00 0xff DAADST D/A A/D Synchronous Conversion 7 7 read-write 0 Do not synchronize DAC12 with ADC12 operation (disable interference reduction between D/A and A/D conversion). #0 1 Synchronize DAC12 with ADC12 operation (enable interference reduction between D/A and A/D conversion). #1 DAAMPCR D/A Output Amplifier Control Register 0x08 8 read-write 0x00 0xff DAAMP0 Amplifier Control 0 6 6 read-write 0 Do not use channel 0 output amplifier #0 1 Use channel 0 output amplifier #1 DAAMP1 Amplifier Control 1 7 7 read-write 0 Do not use channel 1 output amplifier #0 1 Use channel 1 output amplifier #1 DAASWCR D/A Amplifier Stabilization Wait Control Register 0x1C 8 read-write 0x00 0xff DAASW0 D/A Amplifier Stabilization Wait 0 and D/A internal output control 6 6 read-write 0 For output to external pin: Amplifier stabilization wait off (output) for channel 0 For output to internal module: Disable output for channel 0 #0 1 For output to external pin: Amplifier stabilization wait on (high-Z) for channel 0 For output to internal module: Enable output for channel 0 #1 DAASW1 D/A Amplifier Stabilization Wait 1 and D/A internal output control 7 7 read-write 0 For output to external pin: Amplifier stabilization wait off (output) for channel 1 For output to internal module: Disable output for channel 1 #0 1 For output to external pin: Amplifier stabilization wait on (high-Z) for channel 1 For output to internal module: Enable output for channel 1 #1 DAADUSR D/A A/D Synchronous Unit Select Register 0x10C0 8 read-write 0x00 0xff AMADSEL0 A/D Unit 0 Select 0 0 read-write 0 Do not select unit 0 #0 1 Select unit 0 #1 TSD Temperature Sensor Calibration Data 0x407FB000 0x17C 4 registers TSCDR Temperature Sensor Calibration Data Register 0x017C 32 read-only 0x00000000 0xffff0000 TSCDR Temperature Sensor Calibration Data 0 15 read-only FLAD Data Flash 0x407FC000 0x40 1 registers FCKMHZ Data Flash Access Frequency Register 0x40 8 read-write 0x3c 0xff FCKMHZ Data Flash Access Frequency Register 0 7 read-write FACI Flash/CPU Interface 0x407FE000 0x10 1 registers 0x14 1 registers 0x18 1 registers 0x30 8 registers 0x44 2 registers 0x7C 2 registers 0x80 6 registers 0x8C 2 registers 0xA0 2 registers 0xD0 1 registers 0xD4 1 registers 0xD8 10 registers 0xE4 2 registers 0xE8 2 registers FASTAT Flash Access Status Register 0x10 8 read-write 0x00 0xff DFAE Data Flash Memory Access Violation Flag 3 3 read-write 0 No data flash memory access violation has occurred #0 1 A data flash memory access violation has occurred. #1 CMDLK Command Lock Flag 4 4 read-only 0 The flash sequencer is not in the command-locked state #0 1 The flash sequencer is in the command-locked state. #1 CFAE Code Flash Memory Access Violation Flag 7 7 read-write 0 No code flash memory access violation has occurred #0 1 A code flash memory access violation has occurred. #1 FAEINT Flash Access Error Interrupt Enable Register 0x14 8 read-write 0x98 0xff DFAEIE Data Flash Memory Access Violation Interrupt Enable 3 3 read-write 0 Generation of an FIFERR interrupt request is disabled when FASTAT.DFAE is set to 1 #0 1 Generation of an FIFERR interrupt request is enabled when FASTAT.DFAE is set to 1. #1 CMDLKIE Command Lock Interrupt Enable 4 4 read-write 0 Generation of an FIFERR interrupt request is disabled when FASTAT.CMDLK is set to 1 #0 1 Generation of an FIFERR interrupt request is enabled when FASTAT.CMDLK is set to 1. #1 CFAEIE Code Flash Memory Access Violation Interrupt Enable 7 7 read-write 0 Generation of an FIFERR interrupt request is disabled when FASTAT.CFAE is set to 1 #0 1 Generation of an FIFERR interrupt request is enabled when FASTAT.CFAE is set to 1. #1 FRDYIE Flash Ready Interrupt Enable Register 0x18 8 read-write 0x00 0xff FRDYIE Flash Ready Interrupt Enable 0 0 read-write 0 Generation of an FRDY interrupt request is disabled #0 1 Generation of an FRDY interrupt request is enabled. #1 FSADDR FACI Command Start Address Register 0x30 32 read-write 0x00000000 0xffffffff FEADDR FACI Command End Address Register 0x34 32 read-write 0x00000000 0xffffffff FEADDR End Address for FACI Command Processing 0 31 read-write FMEPROT Flash P/E Mode Entry Protection Register 0x44 16 read-write 0x0001 0xffff CEPROT Code Flash P/E Mode Entry Protection 0 0 read-write 0 FENTRYC bit is not protected #0 1 FENTRYC bit is protected. #1 KEY Key Code 8 15 write-only FBPROT1 Flash Block Protection for Secure Register 0x7C 16 read-write 0x0000 0xffff BPCN1 Block Protection for Secure Cancel 0 0 read-write 0 Block protection is enabled #0 1 Block protection is disabled. #1 KEY Key Code 8 15 write-only FSTATR Flash Status Register 0x80 32 read-write 0x00008000 0xffffffff FLWEERR Flash Write/Erase Protect Error Flag 6 6 read-only 0 An error has not occurred #0 1 An error has occurred. #1 PRGSPD Programming Suspend Status Flag 8 8 read-only 0 The flash sequencer is not in the programming suspension processing state or programming suspended state #0 1 The flash sequencer is in the programming suspension processing state or programming suspended state. #1 ERSSPD Erasure Suspend Status Flag 9 9 read-only 0 The flash sequencer is not in the erasure suspension processing state or the erasure suspended state #0 1 The flash sequencer is in the erasure suspension processing state or the erasure suspended state. #1 DBFULL Data Buffer Full Flag 10 10 read-only 0 The data buffer is empty #0 1 The data buffer is full. #1 SUSRDY Suspend Ready Flag 11 11 read-only 0 The flash sequencer cannot receive P/E suspend commands #0 1 The flash sequencer can receive P/E suspend commands. #1 PRGERR Programming Error Flag 12 12 read-only 0 Programming has completed successfully #0 1 An error has occurred during programming. #1 ERSERR Erasure Error Flag 13 13 read-only 0 Erasure has completed successfully #0 1 An error has occurred during erasure. #1 ILGLERR Illegal Command Error Flag 14 14 read-only 0 The flash sequencer has not detected an illegal FACI command or illegal flash memory access #0 1 The flash sequencer has detected an illegal FACI command or illegal flash memory access. #1 FRDY Flash Ready Flag 15 15 read-only 0 Program, Block Erase, Multi Block Erase, P/E suspend, P/E resume, Forced Stop, Blank Check, or Configuration set command processing is in progress #0 1 None of the above is in progress. #1 OTERR Other Error 20 20 read-only 0 A status clear or forced stop command processing is complete #0 1 An error has occurred. #1 SECERR Security Error 21 21 read-only 0 A status clear or forced stop command processing is complete #0 1 An error has occurred. #1 FESETERR FENTRY Setting Error 22 22 read-only 0 A status clear or forced stop command processing is complete #0 1 An error has occurred. #1 ILGCOMERR Illegal Command Error 23 23 read-only 0 A status clear or forced stop command processing is complete #0 1 An error has occurred. #1 FENTRYR Flash P/E Mode Entry Register 0x84 16 read-write 0x0000 0xffff FENTRYC Code Flash P/E Mode Entry 0 0 read-write 0 Code flash is in read mode #0 1 Code flash is in P/E mode. #1 FENTRYD Data Flash P/E Mode Entry 7 7 read-write 0 Data flash is in read mode #0 1 Data flash is in P/E mode. #1 KEY Key Code 8 15 write-only FSUINITR Flash Sequencer Setup Initialization Register 0x8C 16 read-write 0x0000 0xffff SUINIT Set-Up Initialization 0 0 read-write 0 The FSADDR, FEADDR, FBPROT1, FENTRYR, FBCCNT, and FCPSR flash sequencer setup registers keep their current values #0 1 The FSADDR, FEADDR, FBRPOT1, FENTRYR, FBCCNT, and FCPSR flash sequencer setup registers are initialized. #1 KEY Key Code 8 15 write-only FCMDR FACI Command Register 0xA0 16 read-only 0x0000 0xffff PCMDR Pre-command Flag 0 7 read-only CMDR Command Flag 8 15 read-only FBCCNT Blank Check Control Register 0xD0 8 read-write 0x00 0xff BCDIR Blank Check Direction 0 0 read-write 0 Blank checking is executed from the lower addresses to the higher addresses (incremental mode) #0 1 Blank checking is executed from the higher addresses to the lower addresses (decremental mode). #1 FBCSTAT Blank Check Status Register 0xD4 8 read-write 0x00 0xff BCST Blank Check Status Flag 0 0 read-only 0 The target area is in the non-programmed state, that is, the area has been erased but has not yet been reprogrammed #0 1 The target area has been programmed with 0s or 1s. #1 FPSADDR Data Flash Programming Start Address Register 0xD8 32 read-write 0x00000000 0xffffffff PSADR Programmed Area Start Address 0 16 read-only FSUASMON Flash Startup Area Select Monitor Register 0xDC 32 read-only 0x00000000 0x7fff7fff FSPR Protection Programming Flag to set Boot Flag and Startup Area Control 15 15 read-only 0 Protected state #0 1 Non-protected state. #1 BTFLG Flag of Startup Area Select for Boot Swap 31 31 read-only 0 The startup area is the alternate block (block 1) #0 1 The startup area is the default block (block 0). #1 FCPSR Flash Sequencer Processing Switching Register 0xE0 16 read-write 0x0000 0xffff ESUSPMD Erasure Suspend Mode 0 0 read-write 0 Suspension priority mode #0 1 Erasure priority mode. #1 FPCKAR Flash Sequencer Processing Clock Notification Register 0xE4 16 read-write 0x0032 0xffff PCKA Flash Sequencer Operating Clock Notification 0 7 read-write KEY Key Code 8 15 write-only FSUACR Flash Startup Area Control Register 0xE8 16 read-write 0x0000 0xffff SAS Startup Area Select 0 1 read-write 00 Startup area is selected by BTFLG bit #00 01 Startup area is selected by BTFLG bit #01 10 Startup area is temporarily switched to the default area (block 0) #10 11 Startup area is temporarily switched to the alternate area (block 1). #11 KEY Key Code 8 15 write-only