LPC15xx 0.7 LPC15xx Cortex-M3 MCU; up to 64 kB flash; up to 12 kB SRAM; USB device; USART; EEPROM CM3 r2p1 little 0 0 3 0 LPC_ 8 32 32 GPIO_PORT General Purpose I/O (GPIO) GPIO 0x1C000000 0x0 0x3FFFF registers 76 0x1 0-75 B[%s] B[%s] Byte pin registers 0x0000 8 read-write 0 0x00000000 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit. [0:0] 76 0x4 0-75 W[%s] W[%s] Word pin registers 0x1000 read-write 0 0x00000000 PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. [31:0] 3 0x4 0-2 DIR[%s] DIR[%s] Port Direction registers 0x2000 read-write 0 0xFFFFFFFF DIRP0 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [0:0] DIRP1 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [1:1] DIRP2 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [2:2] DIRP3 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [3:3] DIRP4 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [4:4] DIRP5 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [5:5] DIRP6 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [6:6] DIRP7 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [7:7] DIRP8 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [8:8] DIRP9 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [9:9] DIRP10 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [10:10] DIRP11 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [11:11] DIRP12 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [12:12] DIRP13 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [13:13] DIRP14 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [14:14] DIRP15 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [15:15] DIRP16 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [16:16] DIRP17 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [17:17] DIRP18 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [18:18] DIRP19 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [19:19] DIRP20 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [20:20] DIRP21 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [21:21] DIRP22 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [22:22] DIRP23 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [23:23] DIRP24 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [24:24] DIRP25 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [25:25] DIRP26 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [26:26] DIRP27 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [27:27] DIRP28 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [28:28] DIRP29 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [29:29] DIRP30 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [30:30] DIRP31 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [31:31] 3 0x4 0-2 MASK[%s] MASK[%s] Port Mask register 0x2080 read-write 0 0xFFFFFFFF MASKP0 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [0:0] MASKP1 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [1:1] MASKP2 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [2:2] MASKP3 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [3:3] MASKP4 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [4:4] MASKP5 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [5:5] MASKP6 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [6:6] MASKP7 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [7:7] MASKP8 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [8:8] MASKP9 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [9:9] MASKP10 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [10:10] MASKP11 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [11:11] MASKP12 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [12:12] MASKP13 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [13:13] MASKP14 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [14:14] MASKP15 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [15:15] MASKP16 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [16:16] MASKP17 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [17:17] MASKP18 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [18:18] MASKP19 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [19:19] MASKP20 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [20:20] MASKP21 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [21:21] MASKP22 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [22:22] MASKP23 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [23:23] MASKP24 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [24:24] MASKP25 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [25:25] MASKP26 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [26:26] MASKP27 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [27:27] MASKP28 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [28:28] MASKP29 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [29:29] MASKP30 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [30:30] MASKP31 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [31:31] 3 0x4 0-2 PIN[%s] PIN[%s] Port pin register 0x2100 read-write 0 0x00000000 PORT0 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [0:0] PORT1 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [1:1] PORT2 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [2:2] PORT3 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [3:3] PORT4 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [4:4] PORT5 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [5:5] PORT6 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [6:6] PORT7 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [7:7] PORT8 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [8:8] PORT9 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [9:9] PORT10 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [10:10] PORT11 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [11:11] PORT12 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [12:12] PORT13 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [13:13] PORT14 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [14:14] PORT15 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [15:15] PORT16 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [16:16] PORT17 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [17:17] PORT18 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [18:18] PORT19 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [19:19] PORT20 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [20:20] PORT21 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [21:21] PORT22 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [22:22] PORT23 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [23:23] PORT24 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [24:24] PORT25 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [25:25] PORT26 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [26:26] PORT27 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [27:27] PORT28 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [28:28] PORT29 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [29:29] PORT30 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [30:30] PORT31 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [31:31] 3 0x4 0-2 MPIN[%s] MPIN[%s] Masked port register 0x2180 read-write 0 0x00000000 MPORTP0 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [0:0] MPORTP1 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [1:1] MPORTP2 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [2:2] MPORTP3 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [3:3] MPORTP4 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [4:4] MPORTP5 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [5:5] MPORTP6 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [6:6] MPORTP7 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [7:7] MPORTP8 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [8:8] MPORTP9 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [9:9] MPORTP10 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [10:10] MPORTP11 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [11:11] MPORTP12 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [12:12] MPORTP13 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [13:13] MPORTP14 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [14:14] MPORTP15 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [15:15] MPORTP16 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [16:16] MPORTP17 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [17:17] MPORTP18 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [18:18] MPORTP19 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [19:19] MPORTP20 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [20:20] MPORTP21 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [21:21] MPORTP22 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [22:22] MPORTP23 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [23:23] MPORTP24 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [24:24] MPORTP25 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [25:25] MPORTP26 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [26:26] MPORTP27 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [27:27] MPORTP28 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [28:28] MPORTP29 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [29:29] MPORTP30 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [30:30] MPORTP31 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [31:31] 3 0x4 0-2 SET[%s] SET[%s] Write: Set port register Read: port output bits 0x2200 read-write 0 0xFFFFFFFF SETP00 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [0:0] SETP01 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [1:1] SETP02 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [2:2] SETP03 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [3:3] SETP04 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [4:4] SETP05 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [5:5] SETP06 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [6:6] SETP07 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [7:7] SETP08 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [8:8] SETP09 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [9:9] SETP010 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [10:10] SETP011 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [11:11] SETP012 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [12:12] SETP013 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [13:13] SETP014 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [14:14] SETP015 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [15:15] SETP016 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [16:16] SETP017 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [17:17] SETP018 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [18:18] SETP019 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [19:19] SETP020 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [20:20] SETP021 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [21:21] SETP022 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [22:22] SETP023 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [23:23] SETP024 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [24:24] SETP025 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [25:25] SETP026 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [26:26] SETP027 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [27:27] SETP028 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [28:28] SETP029 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [29:29] SETP030 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [30:30] SETP031 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [31:31] 3 0x4 0-2 CLR[%s] CLR[%s] Clear port 0x2280 write-only 0 0x00000000 CLRP00 Clear output bits: 0 = No operation. 1 = Clear output bit. [0:0] CLRP01 Clear output bits: 0 = No operation. 1 = Clear output bit. [1:1] CLRP02 Clear output bits: 0 = No operation. 1 = Clear output bit. [2:2] CLRP03 Clear output bits: 0 = No operation. 1 = Clear output bit. [3:3] CLRP04 Clear output bits: 0 = No operation. 1 = Clear output bit. [4:4] CLRP05 Clear output bits: 0 = No operation. 1 = Clear output bit. [5:5] CLRP06 Clear output bits: 0 = No operation. 1 = Clear output bit. [6:6] CLRP07 Clear output bits: 0 = No operation. 1 = Clear output bit. [7:7] CLRP08 Clear output bits: 0 = No operation. 1 = Clear output bit. [8:8] CLRP09 Clear output bits: 0 = No operation. 1 = Clear output bit. [9:9] CLRP010 Clear output bits: 0 = No operation. 1 = Clear output bit. [10:10] CLRP011 Clear output bits: 0 = No operation. 1 = Clear output bit. [11:11] CLRP012 Clear output bits: 0 = No operation. 1 = Clear output bit. [12:12] CLRP013 Clear output bits: 0 = No operation. 1 = Clear output bit. [13:13] CLRP014 Clear output bits: 0 = No operation. 1 = Clear output bit. [14:14] CLRP015 Clear output bits: 0 = No operation. 1 = Clear output bit. [15:15] CLRP016 Clear output bits: 0 = No operation. 1 = Clear output bit. [16:16] CLRP017 Clear output bits: 0 = No operation. 1 = Clear output bit. [17:17] CLRP018 Clear output bits: 0 = No operation. 1 = Clear output bit. [18:18] CLRP019 Clear output bits: 0 = No operation. 1 = Clear output bit. [19:19] CLRP020 Clear output bits: 0 = No operation. 1 = Clear output bit. [20:20] CLRP021 Clear output bits: 0 = No operation. 1 = Clear output bit. [21:21] CLRP022 Clear output bits: 0 = No operation. 1 = Clear output bit. [22:22] CLRP023 Clear output bits: 0 = No operation. 1 = Clear output bit. [23:23] CLRP024 Clear output bits: 0 = No operation. 1 = Clear output bit. [24:24] CLRP025 Clear output bits: 0 = No operation. 1 = Clear output bit. [25:25] CLRP026 Clear output bits: 0 = No operation. 1 = Clear output bit. [26:26] CLRP027 Clear output bits: 0 = No operation. 1 = Clear output bit. [27:27] CLRP028 Clear output bits: 0 = No operation. 1 = Clear output bit. [28:28] CLRP029 Clear output bits: 0 = No operation. 1 = Clear output bit. [29:29] CLRP030 Clear output bits: 0 = No operation. 1 = Clear output bit. [30:30] CLRP031 Clear output bits: 0 = No operation. 1 = Clear output bit. [31:31] 3 0x4 0-2 NOT[%s] NOT[%s] Toggle port 0x2300 write-only 0 0x00000000 NOTP00 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [0:0] NOTP01 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [1:1] NOTP02 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [2:2] NOTP03 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [3:3] NOTP04 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [4:4] NOTP05 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [5:5] NOTP06 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [6:6] NOTP07 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [7:7] NOTP08 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [8:8] NOTP09 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [9:9] NOTP010 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [10:10] NOTP011 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [11:11] NOTP012 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [12:12] NOTP013 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [13:13] NOTP014 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [14:14] NOTP015 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [15:15] NOTP016 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [16:16] NOTP017 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [17:17] NOTP018 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [18:18] NOTP019 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [19:19] NOTP020 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [20:20] NOTP021 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [21:21] NOTP022 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [22:22] NOTP023 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [23:23] NOTP024 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [24:24] NOTP025 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [25:25] NOTP026 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [26:26] NOTP027 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [27:27] NOTP028 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [28:28] NOTP029 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [29:29] NOTP030 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [30:30] NOTP031 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [31:31] DMA DMA controller DMA 0x1C004000 0x0 0xFFF registers DMA 4 CTRL DMA control. 0x000 read-write 0 0xFFFFFFFF ENABLE DMA controller master enable. [0:0] ENUM DISABLED Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled. 0 ENABLED Enabled. The DMA controller is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:1] INTSTAT Interrupt status. 0x004 read-only 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [0:0] ACTIVEINT Summarizes whether any enabled interrupts are pending. [1:1] ENUM NOT_PENDING Not pending. No enabled interrupts are pending. 0 PENDING Pending. At least one enabled interrupt is pending. 1 ACTIVEERRINT Summarizes whether any error interrupts are pending. [2:2] ENUM NOT_PENDING Not pending. No error interrupts are pending. 0 PENDING Pending. At least one error interrupt is pending. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:3] SRAMBASE SRAM address of the channel configuration table. 0x008 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [9:0] OFFSET Address of the beginning of the DMA descriptor table. The table must begin on a 1 kB boundary. Boundary needed for 18 channel DMA configuration: 512 bytes (bottom 9 bits = 0) [31:10] ENABLESET0 Channel Enable read and Set for all DMA channels. 0x020 read-write 0 0xFFFFFFFF ENA0 Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled. [0:0] ENA1 Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled. [1:1] ENA2 Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled. [2:2] ENA3 Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled. [3:3] ENA4 Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled. [4:4] ENA5 Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled. [5:5] ENA6 Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled. [6:6] ENA7 Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled. [7:7] ENA8 Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled. [8:8] ENA9 Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled. [9:9] ENA10 Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled. [10:10] ENA11 Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled. [11:11] ENA12 Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled. [12:12] ENA13 Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled. [13:13] ENA14 Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled. [14:14] ENA15 Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled. [15:15] ENA16 Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled. [16:16] ENA17 Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled. [17:17] RESERVED Reserved. [31:18] ENABLECLR0 Channel Enable Clear for all DMA channels. 0x028 write-only 0 0x00000000 CLR0 Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. [0:0] CLR1 Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. [1:1] CLR2 Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. [2:2] CLR3 Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. [3:3] CLR4 Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. [4:4] CLR5 Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. [5:5] CLR6 Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. [6:6] CLR7 Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. [7:7] CLR8 Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. [8:8] CLR9 Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. [9:9] CLR10 Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. [10:10] CLR11 Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. [11:11] CLR12 Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. [12:12] CLR13 Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. [13:13] CLR14 Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. [14:14] CLR15 Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. [15:15] CLR16 Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. [16:16] CLR17 Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. [17:17] RESERVED Reserved. [31:18] ACTIVE0 Channel Active status for all DMA channels. 0x030 read-only 0 0xFFFFFFFF ACT0 Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active. [0:0] ACT1 Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active. [1:1] ACT2 Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active. [2:2] ACT3 Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active. [3:3] ACT4 Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active. [4:4] ACT5 Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active. [5:5] ACT6 Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active. [6:6] ACT7 Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active. [7:7] ACT8 Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active. [8:8] ACT9 Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active. [9:9] ACT10 Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active. [10:10] ACT11 Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active. [11:11] ACT12 Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active. [12:12] ACT13 Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active. [13:13] ACT14 Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active. [14:14] ACT15 Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active. [15:15] ACT16 Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active. [16:16] ACT17 Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active. [17:17] RESERVED Reserved. [31:18] BUSY0 Channel Busy status for all DMA channels. 0x038 read-only 0 0xFFFFFFFF BSY0 Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy. [0:0] BSY1 Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy. [1:1] BSY2 Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy. [2:2] BSY3 Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy. [3:3] BSY4 Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy. [4:4] BSY5 Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy. [5:5] BSY6 Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy. [6:6] BSY7 Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy. [7:7] BSY8 Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy. [8:8] BSY9 Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy. [9:9] BSY10 Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy. [10:10] BSY11 Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy. [11:11] BSY12 Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy. [12:12] BSY13 Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy. [13:13] BSY14 Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy. [14:14] BSY15 Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy. [15:15] BSY16 Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy. [16:16] BSY17 Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy. [17:17] RESERVED Reserved. [31:18] ERRINT0 Error Interrupt status for all DMA channels. 0x040 read-write 0 0xFFFFFFFF ERR0 Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active. [0:0] ERR1 Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active. [1:1] ERR2 Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active. [2:2] ERR3 Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active. [3:3] ERR4 Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active. [4:4] ERR5 Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active. [5:5] ERR6 Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active. [6:6] ERR7 Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active. [7:7] ERR8 Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active. [8:8] ERR9 Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active. [9:9] ERR10 Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active. [10:10] ERR11 Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active. [11:11] ERR12 Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active. [12:12] ERR13 Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active. [13:13] ERR14 Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active. [14:14] ERR15 Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active. [15:15] ERR16 Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active. [16:16] ERR17 Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active. [17:17] RESERVED Reserved. [31:18] INTENSET0 Interrupt Enable read and Set for all DMA channels. 0x048 read-write 0 0xFFFFFFFF SET0 0 [0:0] SET1 0 [1:1] SET2 0 [2:2] SET3 0 [3:3] SET4 0 [4:4] SET5 0 [5:5] SET6 0 [6:6] SET7 0 [7:7] SET8 0 [8:8] SET9 0 [9:9] SET10 0 [10:10] SET11 0 [11:11] SET12 0 [12:12] SET13 0 [13:13] SET14 0 [14:14] SET15 0 [15:15] SET16 0 [16:16] SET17 0 [17:17] RESERVED Reserved. [31:18] INTENCLR0 Interrupt Enable Clear for all DMA channels. 0x050 write-only 0 0x00000000 CLR0 Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. [0:0] CLR1 Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. [1:1] CLR2 Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. [2:2] CLR3 Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. [3:3] CLR4 Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. [4:4] CLR5 Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. [5:5] CLR6 Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. [6:6] CLR7 Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. [7:7] CLR8 Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. [8:8] CLR9 Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. [9:9] CLR10 Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. [10:10] CLR11 Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. [11:11] CLR12 Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. [12:12] CLR13 Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. [13:13] CLR14 Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. [14:14] CLR15 Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. [15:15] CLR16 Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. [16:16] CLR17 Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. [17:17] RESERVED Reserved. [31:18] INTA0 Interrupt A status for all DMA channels. 0x058 read-write 0 0xFFFFFFFF IA0 Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. [0:0] IA1 Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. [1:1] IA2 Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. [2:2] IA3 Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. [3:3] IA4 Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. [4:4] IA5 Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. [5:5] IA6 Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. [6:6] IA7 Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. [7:7] IA8 Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. [8:8] IA9 Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. [9:9] IA10 Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. [10:10] IA11 Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. [11:11] IA12 Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. [12:12] IA13 Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. [13:13] IA14 Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. [14:14] IA15 Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. [15:15] IA16 Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. [16:16] IA17 Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. [17:17] RESERVED Reserved. [31:18] INTB0 Interrupt B status for all DMA channels. 0x060 read-write 0 0xFFFFFFFF IB0 Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. [0:0] IB1 Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. [1:1] IB2 Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. [2:2] IB3 Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. [3:3] IB4 Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. [4:4] IB5 Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. [5:5] IB6 Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. [6:6] IB7 Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. [7:7] IB8 Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. [8:8] IB9 Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. [9:9] IB10 Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. [10:10] IB11 Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. [11:11] IB12 Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. [12:12] IB13 Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. [13:13] IB14 Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. [14:14] IB15 Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. [15:15] IB16 Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. [16:16] IB17 Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. [17:17] RESERVED Reserved. [31:18] SETVALID0 Set ValidPending control bits for all DMA channels. 0x068 write-only 0 0x00000000 SV0 SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n. [0:0] SV1 SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n. [1:1] SV2 SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n. [2:2] SV3 SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n. [3:3] SV4 SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n. [4:4] SV5 SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n. [5:5] SV6 SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n. [6:6] SV7 SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n. [7:7] SV8 SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n. [8:8] SV9 SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n. [9:9] SV10 SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n. [10:10] SV11 SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n. [11:11] SV12 SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n. [12:12] SV13 SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n. [13:13] SV14 SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n. [14:14] SV15 SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n. [15:15] SV16 SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n. [16:16] SV17 SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n. [17:17] RESERVED Reserved. [31:18] SETTRIG0 Set Trigger control bits for all DMA channels. 0x070 write-only 0 0x00000000 SETTRIG0 Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. [0:0] SETTRIG1 Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. [1:1] SETTRIG2 Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. [2:2] SETTRIG3 Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. [3:3] SETTRIG4 Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. [4:4] SETTRIG5 Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. [5:5] SETTRIG6 Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. [6:6] SETTRIG7 Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. [7:7] SETTRIG8 Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. [8:8] SETTRIG9 Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. [9:9] SETTRIG10 Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. [10:10] SETTRIG11 Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. [11:11] SETTRIG12 Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. [12:12] SETTRIG13 Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. [13:13] SETTRIG14 Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. [14:14] SETTRIG15 Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. [15:15] SETTRIG16 Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. [16:16] SETTRIG17 Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. [17:17] RESERVED Reserved. [31:18] ABORT0 Channel Abort control for all DMA channels. 0x078 write-only 0 0x00000000 AORTCTRL0 Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. [0:0] AORTCTRL1 Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. [1:1] AORTCTRL2 Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. [2:2] AORTCTRL3 Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. [3:3] AORTCTRL4 Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. [4:4] AORTCTRL5 Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. [5:5] AORTCTRL6 Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. [6:6] AORTCTRL7 Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. [7:7] AORTCTRL8 Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. [8:8] AORTCTRL9 Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. [9:9] AORTCTRL10 Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. [10:10] AORTCTRL11 Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. [11:11] AORTCTRL12 Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. [12:12] AORTCTRL13 Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. [13:13] AORTCTRL14 Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. [14:14] AORTCTRL15 Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. [15:15] AORTCTRL16 Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. [16:16] AORTCTRL17 Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. [17:17] RESERVED Reserved. [31:18] 18 0x10 0-17 CFG%s Configuration register for DMA channel 0. 0x400 read-write 0 0x00000000 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. [0:0] ENUM DISABLED Disabled. Peripheral DMA requests are disabled. 0 ENABLED Enabled. Peripheral DMA requests are enabled. 1 HWTRIGEN Hardware Triggering Enable for this channel. [1:1] ENUM DISABLED Disabled. Hardware triggering is not used. 0 ENABLED Enabled. Use hardware triggering. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [3:2] TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. [4:4] ENUM ACTIVE_LOW__FALLING Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. 0 ACTIVE_HIGH__RISING Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. 1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. [5:5] ENUM EDGE Edge. Hardware trigger is edge triggered. 0 LEVEL Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. 1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. [6:6] ENUM SINGLE_TRANSFER Single transfer. Hardware trigger causes a single transfer. 0 BURST_TRANSFER Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. [11:8] RESERVED Reserved. Read value is undefined, only zero should be written. [13:12] SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. [14:14] ENUM DISABLED Disabled. Source burst wrapping is not enabled for this DMA channel. 0 ENABLED Enabled. Source burst wrapping is enabled for this DMA channel. 1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. [15:15] ENUM DISABLED Disabled. Destination burst wrapping is not enabled for this DMA channel. 0 ENABLED Enabled. Destination burst wrapping is enabled for this DMA channel. 1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. This description reflects a 3-bit priority field giving 8 priority levels. A specific instance of the SDMA might have anywhere from 2 to 16 priority levels (1 to 4 bits for the CH_PRIORITY field). 0x0 = highest priority. 0x7 = lowest priority. [18:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:19] 18 0x10 0-17 CTLSTAT%s Control and status register for DMA channel 0. 0x404 read-only 0 0x00000000 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. [0:0] ENUM NO_EFFECT_ON_DMA_OPE No effect on DMA operation. 0 VALID_PENDING Valid pending. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [1:1] TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. [2:2] ENUM NOT_TRIGGERED Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. 0 TRIGGERED Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:3] 18 0x10 0-17 XFERCFG%s Transfer configuration register for DMA channel 0. 0x408 read-write 0 0x00000000 CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. [0:0] ENUM NOT_VALID Not valid. The current channel descriptor is not considered valid. 0 VALID Valid. The current channel descriptor is considered valid. 1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. [1:1] ENUM DISABLED Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. 0 ENABLED Enabled. Reload the channels' control structure when the current descriptor is exhausted. 1 SWTRIG Software Trigger. [2:2] ENUM WHEN_WRITTEN_BY_SOFT When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. 0 WHEN_WRITTEN_BY_SOFT When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. 1 CLRTRIG Clear Trigger. [3:3] ENUM NOT_CLEARED Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. 0 CLEARED Cleared. The trigger is cleared when this descriptor is exhausted. 1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. [4:4] ENUM NO_EFFECT No effect. 0 SET Set. The INTA flag for this channel will be set when the current descriptor is exhausted. 1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. [5:5] ENUM NO_EFFECT No effect. 0 SET Set. The INTB flag for this channel will be set when the current descriptor is exhausted. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [7:6] WIDTH Transfer width used for this DMA channel. [9:8] ENUM 8_BIT_TRANSFERS_ARE 8-bit transfers are performed (8-bit source reads and destination writes). 0x0 16_BIT_TRANSFERS_ARE 16-bit transfers are performed (16-bit source reads and destination writes). 0x1 32_BIT_TRANSFERS_ARE 32-bit transfers are performed (32-bit source reads and destination writes). 0x2 RESERVED Reserved setting, do not use. 0x3 RESERVED Reserved. Read value is undefined, only zero should be written. [11:10] SRCINC Determines whether the source address is incremented for each DMA transfer. [13:12] ENUM NO_INCREMENT No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. 0x0 1_X_WIDTH 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. 0x1 2_X_WIDTH 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. 0x2 4_X_WIDTH 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. 0x3 DSTINC Determines whether the destination address is incremented for each DMA transfer. [15:14] ENUM NO_INCREMENT No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. 0x0 1_X_WIDTH 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. 0x1 2_X_WIDTH 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. 0x2 4_X_WIDTH 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. 0x3 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed. [25:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:26] USB USB device controller USB 0x1C00C000 0x0 0xFFF registers USB_IRQ 28 USB_FIQ 29 USBWAKEUP 30 DEVCMDSTAT USB Device Command/Status register 0x000 read-write 0x00000800 0xFFFFFFFF DEV_ADDR USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request. [6:0] DEV_EN USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. [7:7] SETUP SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. [8:8] PLL_ON USB Clock/PLL control. [9:9] ENUM USB_NEEDCLK_FUNCTION USB_NeedClk functional 0 USB_NEEDCLK_ALWAYS_1 USB_NeedClk always 1. Clock will not be stopped in case of suspend. 1 RESERVED Reserved. [10:10] LPM_SUP LPM Support. [11:11] ENUM LPM_NOT_SUPPORTED LPM not supported. 0 LPM_SUPPORTED LPM supported. 1 INTONNAK_AO Interrupt on NAK for interrupt and bulk OUT EP [12:12] ENUM ONLY_ACKNOWLEDGED_PA Only acknowledged packets generate an interrupt 0 BOTH_ACKNOWLEDGED_AN Both acknowledged and NAKed packets generate interrupts. 1 INTONNAK_AI Interrupt on NAK for interrupt and bulk IN EP [13:13] ENUM ONLY_ACKNOWLEDGED_PA Only acknowledged packets generate an interrupt 0 BOTH_ACKNOWLEDGED_AN Both acknowledged and NAKed packets generate interrupts. 1 INTONNAK_CO Interrupt on NAK for control OUT EP [14:14] ENUM ONLY_ACKNOWLEDGED_PA Only acknowledged packets generate an interrupt 0 BOTH_ACKNOWLEDGED_AN Both acknowledged and NAKed packets generate interrupts. 1 INTONNAK_CI Interrupt on NAK for control IN EP [15:15] ENUM ONLY_ACKNOWLEDGED_PA Only acknowledged packets generate an interrupt 0 BOTH_ACKNOWLEDGED_AN Both acknowledged and NAKed packets generate interrupts. 1 DCON Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VbusDebounced bit is one. [16:16] DSUS Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect. [17:17] RESERVED Reserved. [18:18] LPM_SUS Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10us has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one. [19:19] LPM_REWP LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction. [20:20] RESERVED Reserved. [23:21] DCON_C Device status - connect change. The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. [24:24] DSUS_C Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it. [25:25] DRES_C Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it. [26:26] RESERVED Reserved. [27:27] VBUSDEBOUNCED This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. [28:28] RESERVED Reserved. [31:29] INFO USB Info register 0x004 read-write 0 0xFFFFFFFF FRAME_NR Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device. [10:0] ERR_CODE The error code which last occurred: [14:11] ENUM NO_ERROR No error 0x0 PID_ENCODING_ERROR PID encoding error 0x1 PID_UNKNOWN PID unknown 0x2 PACKET_UNEXPECTED Packet unexpected 0x3 TOKEN_CRC_ERROR Token CRC error 0x4 DATA_CRC_ERROR Data CRC error 0x5 TIME_OUT Time out 0x6 BABBLE Babble 0x7 TRUNCATED_EOP Truncated EOP 0x8 SENT_RECEIVED_NAK Sent/Received NAK 0x9 SENT_STALL Sent Stall 0xA OVERRUN Overrun 0xB SENT_EMPTY_PACKET Sent empty packet 0xC BITSTUFF_ERROR Bitstuff error 0xD SYNC_ERROR Sync error 0xE WRONG_DATA_TOGGLE Wrong data toggle 0xF RESERVED Reserved. [15:15] RESERVED Reserved [31:16] EPLISTSTART USB EP Command/Status List start address 0x008 read-write 0 0xFFFFFFFF RESERVED Reserved [7:0] EP_LIST Start address of the USB EP Command/Status List. [31:8] DATABUFSTART USB Data buffer start address 0x00C read-write 0 0xFFFFFFFF RESERVED Reserved [21:0] DA_BUF Start address of the buffer pointer page where all endpoint data buffers are located. [31:22] LPM Link Power Management register 0x010 read-write 0 0xFFFFFFFF HIRD_HW Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token [3:0] HIRD_SW Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. [7:4] DATA_PENDING As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1. [8:8] RESERVED Reserved [31:9] EPSKIP USB Endpoint skip 0x014 read-write 0 0xFFFFFFFF SKIP Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. [29:0] RESERVED Reserved [31:30] EPINUSE USB Endpoint Buffer in use 0x018 read-write 0 0xFFFFFFFF RESERVED Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint. [1:0] BUF Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1. [9:2] RESERVED Reserved [31:10] EPBUFCFG USB Endpoint Buffer Configuration register 0x01C read-write 0 0xFFFFFFFF RESERVED Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint. [1:0] BUF_SB Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer. [9:2] RESERVED Reserved [31:10] INTSTAT USB interrupt status register 0x020 read-write 0 0xFFFFFFFF EP0OUT Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it. [0:0] EP0IN Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it. [1:1] EP1OUT Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it. [2:2] EP1IN Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it. [3:3] EP2OUT Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it. [4:4] EP2IN Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it. [5:5] EP3OUT Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it. [6:6] EP3IN Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it. [7:7] EP4OUT Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it. [8:8] EP4IN Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it. [9:9] RESERVED Reserved [29:10] FRAME_INT Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it. [30:30] DEV_INT Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it. [31:31] INTEN USB interrupt enable register 0x024 read-write 0 0xFFFFFFFF EP_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. [9:0] RESERVED Reserved [29:10] FRAME_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. [30:30] DEV_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. [31:31] INTSETSTAT USB set interrupt status register 0x028 read-write 0 0xFFFFFFFF EP_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. [9:0] RESERVED Reserved [29:10] FRAME_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. [30:30] DEV_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. [31:31] INTROUTING USB interrupt routing register 0x02C read-write 0 0xFFFFFFFF ROUTE_INT9_0 This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit [9:0] RESERVED Reserved [29:10] ROUTE_INT30 This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit [30:30] ROUTE_INT31 This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit [31:31] EPTOGGLE USB Endpoint toggle register 0x034 read-only 0 0xFFFFFFFF TOGGLE Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. [9:0] RESERVED Reserved [31:10] CRC Cyclic Redundancy Check (CRC) engine CRC 0x1C010000 0x0 0xFFF registers MODE CRC mode register 0x00 read-write 0x00000000 0xFFFFFFFF CRC_POLY CRC polynom: 1X= CRC-32 polynomial 01= CRC-16 polynomial 00= CRC-CCITT polynomial [1:0] BIT_RVS_WR Data bit order: 1= Bit order reverse for CRC_WR_DATA (per byte) 0= No bit order reverse for CRC_WR_DATA (per byte) [2:2] CMPL_WR Data complement: 1= 1's complement for CRC_WR_DATA 0= No 1's complement for CRC_WR_DATA [3:3] BIT_RVS_SUM CRC sum bit order: 1= Bit order reverse for CRC_SUM 0= No bit order reverse for CRC_SUM [4:4] CMPL_SUM CRC sum complement: 1= 1's complement for CRC_SUM 0=No 1's complement for CRC_SUM [5:5] Reserved Always 0 when read [31:6] SEED CRC seed register 0x04 read-write 0x0000FFFF 0xFFFFFFFF CRC_SEED A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses. [31:0] SUM CRC checksum register 0x08 read-only 0x0000FFFF 0xFFFFFFFF CRC_SUM The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. [31:0] WR_DATA CRC data register SUM 0x08 write-only 0 0x00000000 CRC_WR_DATA Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions. [31:0] SCT0 Large State Configurable Timers 0/1 (SCT0/1) SCT0 0x1C018000 0x0 0xFFF registers SCT0 16 CONFIG SCT configuration register 0x000 read-write 0x00007E00 0xFFFFFFFF UNIFY SCT operation [0:0] ENUM THE_SCT_OPERATES_AS The SCT operates as two 16-bit counters named L and H. 0 THE_SCT_OPERATES_AS The SCT operates as a unified 32-bit counter. 1 CLKMODE SCT clock mode [2:1] ENUM SYSTEM_CLOCK System clock. The system clock clocks the SCT and prescalers. 0x0 PRESCALED_SYSTEM_CLO Prescaled system clock. The SCT clock is the system clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode. 0x1 SCT_INPUT SCT input. The input selected by CLKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode. 0x2 PRESCALED_SCT_INPUT Prescaled SCT input. The SCT and prescalers are clocked by the input edge selected by the CLKSEL field. In this mode, most of the SCT is clocked by the (selected polarity of the) input. The outputs are switched synchronously to the input clock. The input clock rate must be at least half the system clock rate and can the same or faster than the system clock. 0x3 CLKSEL SCT clock select [6:3] ENUM RISING_EDGES_ON_INPU Rising edges on input 0. 0x0 FALLING_EDGES_ON_INP Falling edges on input 0. 0x1 RISING_EDGES_ON_INPU Rising edges on input 1. 0x2 FALLING_EDGES_ON_INP Falling edges on input 1. 0x3 RISING_EDGES_ON_INPU Rising edges on input 2. 0x4 FALLING_EDGES_ON_INP Falling edges on input 2. 0x5 RISING_EDGES_ON_INPU Rising edges on input 3. 0x6 FALLING_EDGES_ON_INP Falling edges on input 3. 0x7 RISING_EDGES_ON_INPU Rising edges on input 4. 0x8 FALLING_EDGES_ON_INP Falling edges on input 4. 0x9 RISING_EDGES_ON_INPU Rising edges on input 5. 0xA FALLING_EDGES_ON_INP Falling edges on input 5. 0xB RISING_EDGES_ON_INPU Rising edges on input 6. 0xC FALLING_EDGES_ON_INP Falling edges on input 6. 0xD RISING_EDGES_ON_INPU Rising edges on input 7. 0xE FALLING_EDGES_ON_INP Falling edges on input 7. 0xF NORELAOD_L A 1 in this bit prevents the lower match and fractional match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. [7:7] NORELOAD_H A 1 in this bit prevents the higher match and fractional match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. [8:8] INSYNC Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used. [16:9] AUTOLIMIT_L A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. [17:17] AUTOLIMIT_H A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. [18:18] RESERVED Reserved [31:19] CTRL SCT control register 0x004 read-write 0x00040004 0xFFFFFFFF DOWN_L This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs. [0:0] STOP_L When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. [1:1] HALT_L When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation. [2:2] CLRCTR_L Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. [3:3] BIDIR_L L or unified counter direction select [4:4] ENUM THE_COUNTER_COUNTS_U The counter counts up to its limit condition, then is cleared to zero. 0 THE_COUNTER_COUNTS_U The counter counts up to its limit, then counts down to a limit condition or to 0. 1 PRE_L Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. [12:5] RESERVED Reserved [15:13] DOWN_H This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs. [16:16] STOP_H When this bit is 1 and HALT is 0, the H counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. [17:17] HALT_H When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation. [18:18] CLRCTR_H Writing a 1 to this bit clears the H counter. This bit always reads as 0. [19:19] BIDIR_H Direction select [20:20] ENUM THE_H_COUNTER_COUNTS The H counter counts up to its limit condition, then is cleared to zero. 0 THE_H_COUNTER_COUNTS The H counter counts up to its limit, then counts down to a limit condition or to 0. 1 PRE_H Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. [28:21] RESERVED Reserved [31:29] LIMIT SCT limit register 0x008 read-write 0x00000000 0xFFFFFFFF LIMMSK_L If bit n is one, event n is used as a counter limit event for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). [15:0] LIMMSK_H If bit n is one, event n is used as a counter limit event for the H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31). [31:16] HALT SCT halt condition register 0x00C read-write 0x00000000 0xFFFFFFFF HALTMSK_L If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). [15:0] HALTMSK_H If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31). [31:16] STOP SCT stop condition register 0x010 read-write 0x00000000 0xFFFFFFFF STOPMSK_L If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). [15:0] STOPMSK_H If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31). [31:16] START SCT start condition register 0x014 read-write 0x00000000 0xFFFFFFFF STARTMSK_L If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). [15:0] STARTMSK_H If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31). [31:16] DITHER SCT dither condition register 0x018 read-write 0 0x00000000 DITHMSK_L If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit low counter or the unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle. [15:0] DITHMSK_H If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit high counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle. [31:16] COUNT SCT counter register 0x040 read-write 0x00000000 0xFFFFFFFF CTR_L When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter. [15:0] CTR_H When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter. [31:16] STATE SCT state register 0x044 read-write 0x00000000 0xFFFFFFFF STATE_L State variable. [4:0] RESERVED Reserved. [15:5] STATE_H State variable. [20:16] RESERVED Reserved. [31:21] INPUT SCT input register 0x048 read-only 0x00000000 0xFFFFFFFF AIN0 Real-time status of input 0. [0:0] AIN1 Real-time status of input 1. [1:1] AIN2 Real-time status of input 2. [2:2] AIN3 Real-time status of input 3. [3:3] AIN4 Real-time status of input 4. [4:4] AIN5 Real-time status of input 5. [5:5] AIN6 Real-time status of input 6. [6:6] AIN7 Real-time status of input 7. [7:7] RESERVED Reserved. [15:8] SIN0 Input 0 state synchronized to the SCT clock. [16:16] SIN1 Input 1 state synchronized to the SCT clock. [17:17] SIN2 Input 2 state synchronized to the SCT clock. [18:18] SIN3 Input 3 state synchronized to the SCT clock. [19:19] SIN4 Input 4 state synchronized to the SCT clock. [20:20] SIN5 Input 5 state synchronized to the SCT clock. [21:21] SIN6 Input 6 state synchronized to the SCT clock. [22:22] SIN7 Input 7 state synchronized to the SCT clock. [23:23] RESERVED Reserved [31:24] REGMODE SCT match/capture registers mode register 0x04C read-write 0x00000000 0xFFFFFFFF REGMOD_L Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15). 0 = registers operate as match registers. 1 = registers operate as capture registers. [15:0] REGMOD_H Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31). 0 = registers operate as match registers. 1 = registers operate as capture registers. [31:16] OUTPUT SCT output register 0x050 read-write 0x00000000 0xFFFFFFFF OUT Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 9 = bit 9). [9:0] RESERVED Reserved [31:10] OUTPUTDIRCTRL SCT output counter direction control register 0x054 read-write 0x00000000 0xFFFFFFFF SETCLR0 Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. [1:0] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR1 Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. [3:2] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR2 Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. [5:4] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR3 Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. [7:6] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR4 Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. [9:8] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR5 Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. [11:10] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR6 Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. [13:12] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR7 Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. [15:14] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR8 Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. [17:16] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR9 Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. [19:18] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 RESERVED Reserved. [31:20] RES SCT conflict resolution register 0x058 read-write 0x00000000 0xFFFFFFFF O0RES Effect of simultaneous set and clear on output 0. [1:0] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR0 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR0 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O1RES Effect of simultaneous set and clear on output 1. [3:2] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR1 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR1 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O2RES Effect of simultaneous set and clear on output 2. [5:4] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR2 field). 0x1 CLEAR_OUTPUT_N_OR_S Clear output n (or set based on the SETCLR2 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O3RES Effect of simultaneous set and clear on output 3. [7:6] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR3 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR3 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O4RES Effect of simultaneous set and clear on output 4. [9:8] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR4 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR4 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O5RES Effect of simultaneous set and clear on output 5. [11:10] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR5 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR5 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O6RES Effect of simultaneous set and clear on output 6. [13:12] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR6 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR6 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O7RES Effect of simultaneous set and clear on output 7. [15:14] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR7 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR7 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O8RES Effect of simultaneous set and clear on output 8. [17:16] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR8 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR8 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O9RES Effect of simultaneous set and clear on output 9. [19:18] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR9 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR9 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 RESERVED Reserved. [31:20] DMAREQ0 SCT DMA request 0 register 0x05C read-write 0x00000000 0xFFFFFFFF DEV_0 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [15:0] RESERVED Reserved [29:16] DRL0 A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers. [30:30] DRQ0 This read-only bit indicates the state of DMA Request 0 [31:31] DMAREQ1 SCT DMA request 1 register 0x060 read-write 0x00000000 0xFFFFFFFF DEV_1 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [15:0] RESERVED Reserved [29:16] DRL1 A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. [30:30] DRQ1 This read-only bit indicates the state of DMA Request 1. [31:31] EVEN SCT event enable register 0x0F0 read-write 0x00000000 0xFFFFFFFF IEN The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [15:0] RESERVED Reserved [31:16] EVFLAG SCT event flag register 0x0F4 read-write 0x00000000 0xFFFFFFFF FLAG Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [15:0] RESERVED Reserved [31:16] CONEN SCT conflict enable register 0x0F8 read-write 0x00000000 0xFFFFFFFF NCEN The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 9 = bit 9). [9:0] RESERVED Reserved [31:10] CONFLAG SCT conflict flag register 0x0FC read-write 0x00000000 0xFFFFFFFF NCFLAG Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 9 = bit 9). [9:0] RESERVED Reserved. [29:10] BUSERRL The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful. [30:30] BUSERRH The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted. [31:31] 16 0x4 0-15 MATCH%s SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0 0x100 read-write 0x00000000 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. [15:0] MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. [31:16] 6 0x4 0-5 FRACMAT%s Fractional match registers 0 to 5 for SCT match value registers 0 to 5. 0x140 read-write 0x00000000 0xFFFFFFFF FRACMAT_L When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register. [3:0] RESERVED Reserved. [15:4] FRACMAT_H When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5). [19:16] RESERVED Reserved. [31:20] 16 0x4 0-15 CAP%s SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1 MATCH%s 0x100 read-only 0x00000000 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. [15:0] CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. [31:16] 16 0x4 0-15 MATCHREL%s SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0 0x200 read-write 0x00000000 0xFFFFFFFF RELOADn_L When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. [15:0] RELOADn_H When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. [31:16] 6 0x4 0-5 FRACMATREL%s Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5. 0x240 read-write 0x00000000 0xFFFFFFFF RELFRAC_L When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register. [3:0] RESERVED Reserved. [15:4] RELFRAC_H When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register. [19:16] RESERVED Reserved. [31:20] 16 0x4 0-15 CAPCTRL%s SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1 MATCHREL%s 0x200 read-write 0x00000000 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [15:0] CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31). [31:16] 16 0x8 0-15 EV%s_STATE SCT event state register 0 0x300 read-write 0x00000000 0xFFFFFFFF STATEMSKn If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [31:0] 16 0x8 0-15 EV%s_CTRL SCT event control register 0 0x304 read-write 0x00000000 0xFFFFFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. [3:0] HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. [4:4] ENUM SELECTS_THE_L_STATE Selects the L state and the L match register selected by MATCHSEL. 0 SELECTS_THE_H_STATE Selects the H state and the H match register selected by MATCHSEL. 1 OUTSEL Input/output select [5:5] ENUM SELECTS_THE_INPUT_SE Selects the input selected by IOSEL. 0 SELECTS_THE_OUTPUT_S Selects the output selected by IOSEL. 1 IOSEL Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. [9:6] IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . [11:10] ENUM LOW LOW 0x0 RISE Rise 0x1 FALL Fall 0x2 HIGH HIGH 0x3 COMBMODE Selects how the specified match and I/O condition are used and combined. [13:12] ENUM OR OR. The event occurs when either the specified match or I/O condition occurs. 0x0 MATCH MATCH. Uses the specified match only. 0x1 IO IO. Uses the specified I/O condition only. 0x2 AND AND. The event occurs when the specified match and I/O condition occur simultaneously. 0x3 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. [14:14] ENUM STATEV_VALUE_IS_ADDE STATEV value is added into STATE (the carry-out is ignored). 0 STATEV_VALUE_IS_LOAD STATEV value is loaded into STATE. 1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. [19:15] MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. [20:20] DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. [22:21] ENUM DIRECTION_INDEPENDEN Direction independent. This event is triggered regardless of the count direction. 0x0 COUNTING_UP Counting up. This event is triggered only during up-counting when BIDIR = 1. 0x1 COUNTING_DOWN Counting down. This event is triggered only during down-counting when BIDIR = 1. 0x2 RESERVED Reserved [31:23] 10 0x8 0-9 OUT%s_SET SCT output 0 set register 0x500 read-write 0x00000000 0xFFFFFFFF SET A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [15:0] RESERVED Reserved [31:16] 10 0x8 0-9 OUT%s_CLR SCT output 0 clear register 0x504 read-write 0x00000000 0xFFFFFFFF CLR A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [15:0] RESERVED Reserved [31:16] SCT1 SCT1 0x1C01C000 0 0xFFF registers SCT1 17 SCT2 Small State Configurable Timers 2/3 (SCT2/3) SCT2 0x1C020000 0x0 0xFFF registers SCT2 18 CONFIG SCT configuration register 0x000 read-write 0x00007E00 0xFFFFFFFF UNIFY SCT operation [0:0] ENUM THE_SCT_OPERATES_AS The SCT operates as two 16-bit counters named L and H. 0 THE_SCT_OPERATES_AS The SCT operates as a unified 32-bit counter. 1 CLKMODE SCT clock mode [2:1] ENUM THE_BUS_CLOCK_CLOCKS The bus clock clocks the SCT and prescalers. 0x0 THE_SCT_CLOCK_IS_THE The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode. 0x1 THE_INPUT_SELECTED_B The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode. 0x2 RESERVED Reserved.This is not reserved on the LPC15xx. Need to add back in from spec. 0x3 CKSEL SCT clock select [6:3] ENUM RISING_EDGES_ON_INPU Rising edges on input 0. 0x0 FALLING_EDGES_ON_INP Falling edges on input 0. 0x1 RISING_EDGES_ON_INPU Rising edges on input 1. 0x2 FALLING_EDGES_ON_INP Falling edges on input 1. 0x3 RISING_EDGES_ON_INPU Rising edges on input 2. 0x4 FALLING_EDGES_ON_INP Falling edges on input 2. 0x5 RISING_EDGES_ON_INPU Rising edges on input 3. 0x6 FALLING_EDGES_ON_INP Falling edges on input 3. 0x7 NORELAOD_L A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. [7:7] NORELOAD_H A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. [8:8] INSYNC Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used. [16:9] AUTOLIMIT_L A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. [17:17] AUTOLIMIT_H A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. [18:18] RESERVED Reserved [31:19] CTRL SCT control register 0x004 read-write 0x00040004 0xFFFFFFFF DOWN_L This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. [0:0] STOP_L When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. [1:1] HALT_L When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation. [2:2] CLRCTR_L Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. [3:3] BIDIR_L L or unified counter direction select [4:4] ENUM THE_COUNTER_COUNTS_U The counter counts up to its limit condition, then is cleared to zero. 0 THE_COUNTER_COUNTS_U The counter counts up to its limit, then counts down to a limit condition or to 0. 1 PRE_L Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. [12:5] RESERVED Reserved [15:13] DOWN_H This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. [16:16] STOP_H When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. [17:17] HALT_H When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation. [18:18] CLRCTR_H Writing a 1 to this bit clears the H counter. This bit always reads as 0. [19:19] BIDIR_H Direction select [20:20] ENUM THE_H_COUNTER_COUNTS The H counter counts up to its limit condition, then is cleared to zero. 0 THE_H_COUNTER_COUNTS The H counter counts up to its limit, then counts down to a limit condition or to 0. 1 PRE_H Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. [28:21] RESERVED Reserved [31:29] LIMIT SCT limit register 0x008 read-write 0x00000000 0xFFFFFFFF LIMMSK_L If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). [15:0] LIMMSK_H If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31). [31:16] HALT SCT halt condition register 0x00C read-write 0x00000000 0xFFFFFFFF HALTMSK_L If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). [15:0] HALTMSK_H If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31). [31:16] STOP SCT stop condition register 0x010 read-write 0x00000000 0xFFFFFFFF STOPMSK_L If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). [15:0] STOPMSK_H If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31). [31:16] START SCT start condition register 0x014 read-write 0x00000000 0xFFFFFFFF STARTMSK_L If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). [15:0] STARTMSK_H If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31). [31:16] COUNT SCT counter register 0x040 read-write 0x00000000 0xFFFFFFFF CTR_L When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter. [15:0] CTR_H When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter. [31:16] STATE SCT state register 0x044 read-write 0x00000000 0xFFFFFFFF STATE_L State variable. [4:0] RESERVED Reserved. [15:5] STATE_H State variable. [20:16] RESERVED Reserved. [31:21] INPUT SCT input register 0x048 read-only 0x00000000 0xFFFFFFFF AIN0 Real-time status of input 0. [0:0] AIN1 Real-time status of input 1. [1:1] AIN2 Real-time status of input 2. [2:2] AIN3 Real-time status of input 3. [3:3] RESERVED Reserved. [15:4] SIN0 Input 0 state synchronized to the SCT clock. [16:16] SIN1 Input 1 state synchronized to the SCT clock. [17:17] SIN2 Input 2 state synchronized to the SCT clock. [18:18] SIN3 Input 3 state synchronized to the SCT clock. [19:19] RESERVED Reserved [31:20] REGMODE SCT match/capture registers mode register 0x04C read-write 0x00000000 0xFFFFFFFF REGMOD_L Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15). 0 = registers operate as match registers. 1 = registers operate as capture registers. [15:0] REGMOD_H Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31). 0 = registers operate as match registers. 1 = registers operate as capture registers. [31:16] OUTPUT SCT output register 0x050 read-write 0x00000000 0xFFFFFFFF OUT Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 5 = bit 5). [5:0] RESERVED Reserved [31:6] OUTPUTDIRCTRL SCT output counter direction control register 0x054 read-write 0x00000000 0xFFFFFFFF SETCLR0 Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. [1:0] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR1 Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. [3:2] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR2 Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. [5:4] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR3 Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. [7:6] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR4 Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. [9:8] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR5 Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. [11:10] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 RESERVED Reserved [31:12] RES SCT conflict resolution register 0x058 read-write 0x00000000 0xFFFFFFFF O0RES Effect of simultaneous set and clear on output 0. [1:0] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR0 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR0 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O1RES Effect of simultaneous set and clear on output 1. [3:2] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR1 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR1 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O2RES Effect of simultaneous set and clear on output 2. [5:4] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR2 field). 0x1 CLEAR_OUTPUT_N_OR_S Clear output n (or set based on the SETCLR2 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O3RES Effect of simultaneous set and clear on output 3. [7:6] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR3 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR3 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O4RES Effect of simultaneous set and clear on output 4. [9:8] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR4 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR4 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O5RES Effect of simultaneous set and clear on output 5. [11:10] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR5 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR5 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 RESERVED Reserved [31:12] DMAREQ0 SCT DMA request 0 register 0x05C read-write 0x00000000 0xFFFFFFFF DEV_0 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [15:0] RESERVED Reserved [29:16] DRL0 A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers. [30:30] DRQ0 This read-only bit indicates the state of DMA Request 0 [31:31] DMAREQ1 SCT DMA request 1 register 0x060 read-write 0x00000000 0xFFFFFFFF DEV_1 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [15:0] RESERVED Reserved [29:16] DRL1 A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. [30:30] DRQ1 This read-only bit indicates the state of DMA Request 1. [31:31] EVEN SCT event enable register 0x0F0 read-write 0x00000000 0xFFFFFFFF IEN The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [15:0] RESERVED Reserved [31:16] EVFLAG SCT event flag register 0x0F4 read-write 0x00000000 0xFFFFFFFF FLAG Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [15:0] RESERVED Reserved [31:16] CONEN SCT conflict enable register 0x0F8 read-write 0x00000000 0xFFFFFFFF NCEN The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [15:0] RESERVED Reserved [31:16] CONFLAG SCT conflict flag register 0x0FC read-write 0x00000000 0xFFFFFFFF NCFLAG Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 5 = bit 5). [5:0] RESERVED Reserved. [29:6] BUSERRL The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful. [30:30] BUSERRH The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted. [31:31] 8 0x4 0-7 MATCH%s SCT match value register of match channels 0 to 7; REGMOD0 to REGMODE7 = 0 0x100 read-write 0x00000000 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. [15:0] MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. [31:16] 8 0x4 0-7 CAP%s SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7 = 1 MATCH%s 0x100 read-only 0x00000000 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. [15:0] CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. [31:16] 8 0x4 0-7 MATCHREL%s SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7 = 0 0x200 read-write 0x00000000 0xFFFFFFFF RELOADn_L When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. [15:0] RELOADn_H When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. [31:16] 8 0x4 0-7 CAPCTRL%s SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7 = 1 MATCHREL%s 0x200 read-write 0x00000000 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 9 = bit 9). [9:0] RESERVED Reserved. [15:10] CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 9 = bit 24). [24:16] RESERVED Reserved. [31:25] 10 0x8 0-9 EV%s_STATE SCT event state register 0 0x300 read-write 0x00000000 0xFFFFFFFF STATEMSKn If bit m is one, event n (n= 0 to 9) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 9 = bit 9). [9:0] RESERVED Reserved. [31:10] 10 0x8 0-9 EV%s_CTRL SCT event control register 0 0x304 read-write 0x00000000 0xFFFFFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. [3:0] HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. [4:4] ENUM SELECTS_THE_L_STATE Selects the L state and the L match register selected by MATCHSEL. 0 SELECTS_THE_H_STATE Selects the H state and the H match register selected by MATCHSEL. 1 OUTSEL Input/output select [5:5] ENUM SELECTS_THE_INPUTS_E Selects the inputs elected by IOSEL. 0 SELECTS_THE_OUTPUTS Selects the outputs selected by IOSEL. 1 IOSEL Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. [9:6] IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . [11:10] ENUM LOW LOW 0x0 RISE Rise 0x1 FALL Fall 0x2 HIGH HIGH 0x3 COMBMODE Selects how the specified match and I/O condition are used and combined. [13:12] ENUM OR OR. The event occurs when either the specified match or I/O condition occurs. 0x0 MATCH MATCH. Uses the specified match only. 0x1 IO IO. Uses the specified I/O condition only. 0x2 AND AND. The event occurs when the specified match and I/O condition occur simultaneously. 0x3 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. [14:14] ENUM STATEV_VALUE_IS_ADDE STATEV value is added into STATE (the carry-out is ignored). 0 STATEV_VALUE_IS_LOAD STATEV value is loaded into STATE. 1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. [19:15] MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. [20:20] DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. [22:21] ENUM DIRECTION_INDEPENDEN Direction independent. This event is triggered regardless of the count direction. 0x0 COUNTING_UP Counting up. This event is triggered only during up-counting when BIDIR = 1. 0x1 COUNTING_DOWN Counting down. This event is triggered only during down-counting when BIDIR = 1. 0x2 RESERVED Reserved [31:23] 6 0x8 0-5 OUT%s_SET SCT output 0 set register 0x500 read-write 0x00000000 0xFFFFFFFF SET A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 9 = bit 9. [9:0] RESERVED Reserved [31:10] 6 0x8 0-5 OUT%s_CLR SCT output 0 clear register 0x504 read-write 0x00000000 0xFFFFFFFF CLR A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 9 = bit 9. [9:0] RESERVED Reserved [31:10] SCT3 SCT3 0x1C024000 0 0xFFF registers SCT3 19 ADC0 12-bit ADC controller ADC0/1 ADC 0x40000000 0x0 0xFFF registers ADC0_SEQA 31 ADC0_SEQB 32 ADC0_THCMP 33 ADC0_OVR 34 CTRL A/D Control Register. Contains the clock divide value, enable bits for each sequence and the A/D power-down bit. 0x000 read-write 0x0 0xFFFFFFFF CLKDIV In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the A/D converter, which should be less than or equal to 50 MHz (up to 100 MHz in 10-bit mode). Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode. [7:0] ASYNMODE Select clock mode. [8:8] ENUM SYNCHRONOUS_MODE Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. In Synchronous mode with the SYNCBYPASS bit set, sampling of the A/D input and start of conversion will initiate exactly 2 system clocks after the leading edge of a (synchronous) trigger pulse. 0 ASYNCHRONOUS_MODE Asynchronous mode. The ADC clock is based on the output of the asynchronous ADC clock divider ADCASYNCCLKSEL in the SYSCON block. The frequency of this clock is limited to 50 MHz max (100 MHz in 10-bit mode). In addition, the ADC clock must never be faster than 10x the system clock. 1 MODE10BIT Select 10-bit conversion. In 10-bit mode higher conversion rates of up to 100 MHz are supported. A/D resolution is reduced to ten bits, but the clock rate (set via the CLKDIV field) can be increased up to 100 MHz to achieve a conversion rate of up to four million samples per second. The two LSBs of the result data are forced to zero. [9:9] ENUM DISABLED Disabled. The 10-bit/high-conversion rate mode is disabled. 0 ENABLED Enabled. The 10-bit/high-conversion rate is enabled. 1 LPWRMODE Select low-power ADC mode. The analog circuitry is automatically powered-down when no conversions are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is enabled. After the required start-up time, the requested conversion will be launched. Once the conversion completes, the analog-circuitry will again be powered-down provided no further conversions are pending. Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are required relatively infrequently. The penalty for using this mode is an approximately 15 ADC clock delay (30 clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger event occurs until sampling of the A/D input commences. This mode will NOT power-up the A/D if the ADC_ENA bit is low. [10:10] ENUM DISABLED Disabled. The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested. 0 ENABLED Enabled. The low-power ADC mode is enabled. 1 RESERVED Reserved. [29:11] CALMODE Writing a 1 to this bit initiates a self-calibration cycle. This bit will be automatically cleared by hardware after the calibration cycle is complete. Other bits of this register may be written to concurrently with setting this bit, however once this bit has been set no further writes to this register are permitted until the full calibration cycle has ended. [30:30] RESERVED Reserved. [31:31] INSEL A/D Input Select Register: Selects between external pin and internal source for various channels 0x004 read-write 0x0 0xFFFFFFFF AD0SEL This field selects the input source for channel 0. All other values are reserved. [3:0] ENUM ADCN_0_PIN ADCn_0 pin. Voltage on ADC channel 0 input. 0x0 CORE_VOLTAGE_REGULAT Core voltage regulator output (1.2V to 1.8V). If the WRAPEN field is 0x2, the core voltage regulator output is also is output on the ADC0/1_0 pin. 0x1 INTERNAL_VOLTAGE_REF Internal voltage reference. If the WRAPEN field is 0x2, the internal voltage reference is also is output on the ADCn_0 pin. 0x2 TEMPERATURE_SENSOR Temperature Sensor. If the WRAPEN field is 0x2, the temperature sensor voltage is also is output on the ADCn_0 pin. 0x3 VDDADIV2 VDDA/2. 0x4 NO_CONNECTION_OR_LOA No connection or load 0xF RESERVED Reserved. [29:4] RESERVED Reserved. [31:30] SEQA_CTRL A/D Conversion Sequence-A control Register: Controls triggering and channel selection for conversion sequence-A. Also specifies interrupt mode for sequence-A. 0x008 read-write 0x0 0xFFFFFFFF CHANNELS Selects which one or more of the twelve channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, A/D conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while the SEQA_ENA bit (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write. [11:0] TRIGGER Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. [15:12] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [17:16] TRIGPOL Select the polarity of the selected input trigger for this conversion sequence. [18:18] ENUM NEGATIVE_EDGE Negative edge. A negative edge launches the conversion sequence on the selected trigger input. 0 POSITIVE_EDGE Positive edge. A positive edge launches the conversion sequence on the selected trigger input. 1 SYNCBYPASS Setting this bit allows the hardware trigger input to bypass synchronization flip-flops stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode: Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode: Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period. [19:19] ENUM ENABLE_SYNCHRONIZATI Enable synchronization. The hardware trigger bypass is not enabled. 0 BYPASS_SYNCHRONIZATI Bypass synchronization. The hardware trigger bypass is enabled. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [25:20] START Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written-to to launch a conversion sequence. It will consequently always read-back as a zero. [26:26] BURST Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. [27:27] SINGLESTEP When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit. [28:28] LOWPRIO Set priority for sequence A. [29:29] ENUM LOW_PRIORITY Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost. 0 HIGH_PRIORITY High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt this sequence and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point. 1 MODE Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA requests for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below: [30:30] ENUM END_OF_CONVERSION End of conversion. The sequence A interrupt/DMA flag will be set at the end of each individual A/D conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA request if enabled. 0 END_OF_SEQUENCE End of sequence. The sequence A interrupt/DMA flag will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA request since it is assumed this register may not be utilized in this mode. 1 SEQA_ENA Sequence Enable [31:31] ENUM DISABLED Disabled. Sequence A is disabled. Sequence A triggers are ignored. If this bit is cleared while sequence A is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel. 0 ENABLED Enabled. Sequence A is enabled. 1 SEQB_CTRL A/D Conversion Sequence-B Control Register: Controls triggering and channel selection for conversion sequence-B. Also specifies interrupt mode for sequence-B. 0x00C read-write 0x0 0xFFFFFFFF CHANNELS Selects which one or more of the twelve channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, A/D conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while the SEQB_ENA bit (bit 31) is LOW. It is permissible to change this field and set bit 31 in the same write. [11:0] TRIGGER Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. [15:12] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [17:16] TRIGPOL Select the polarity of the selected input trigger for this conversion sequence. [18:18] ENUM NEGATIVE_EDGE Negative edge. A negative edge launches the conversion sequence on the selected trigger input. 0 POSITIVE_EDGE Positive edge. A positive edge launches the conversion sequence on the selected trigger input. 1 SYNCBYPASS Setting this bit allows the hardware trigger input to bypass synchronization flip-flops stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode: Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode: Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period. [19:19] ENUM ENABLE_SYNCHRONIZATI Enable synchronization. The hardware trigger bypass is not enabled. 0 BYPASS_SYNCHRONIZATI Bypass synchronization. The hardware trigger bypass is enabled. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [25:20] START Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write a 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written-to to launch a conversion sequence. It will consequently always read-back as a zero. [26:26] BURST Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other B triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. [27:27] SINGLESTEP When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit. [28:28] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [29:29] MODE Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQB_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA requests for sequence-B will be generated and which overrun conditions contribute to an overrun interrupt as described below: [30:30] ENUM END_OF_CONVERSION End of conversion. The sequence B interrupt/DMA flag will be set at the end of each individual A/D conversion performed under sequence B. This flag will mirror the DATAVALID bit in the SEQB_GDAT register. The OVERRUN bit in the SEQB_GDAT register will contribute to generation of an overrun interrupt/DMA request if enabled. 0 END_OF_SEQUENCE End of sequence. The sequence B interrupt/DMA flag will be set when the entire set of sequence B conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQB_GDAT register will NOT contribute to generation of an overrun interrupt/DMA request since it is assumed this register will not be utilized in this mode. 1 SEQB_ENA Sequence Enable [31:31] ENUM DISABLED Disabled. Sequence B is disabled. Sequence B triggers are ignored. If this bit is cleared while sequence B is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel. 0 ENABLED Enabled. Sequence B is enabled. 1 SEQA_GDAT A/D Sequence-A Global Data Register. This register contains the result of the most recent A/D conversion performed under sequence-A 0x010 read-write 0 0x00000000 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [3:0] RESULT This field contains the 12-bit A/D conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is the a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read. [15:4] THCMPRANGE Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH). [17:16] THCMPCROSS Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred. [19:18] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [25:20] CHN These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1...). [29:26] OVERRUN This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt request if the MODE bit (in SEQA_CTRL) for the corresponding sequence is set to 0 (and if the overrun interrupt is enabled). [30:30] DATAVALID This bit is set to 1 at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled). [31:31] SEQB_GDAT A/D Sequence-B Global Data Register. This register contains the result of the most recent A/D conversion performed under sequence-B 0x014 read-write 0 0x00000000 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [3:0] RESULT This field contains the 12-bit A/D conversion result from the most recent conversion performed under conversion sequence associated with this register. This will be a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on V REFP. DATAVALID = 1 indicates that this result has not yet been read. [15:4] THCMPRANGE Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH). Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved. [17:16] THCMPCROSS Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. [19:18] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [25:20] CHN These bits contain the channel from which the RESULT bits were converted (e.g. 0b0000 identifies channel 0, 0b0001 channel 1...). [29:26] OVERRUN This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt request if the MODE bit (in SEQB_CTRL) for the corresponding sequence is set to 0 (and if the overrun interrupt is enabled). [30:30] DATAVALID This bit is set to 1 at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQB_CTRL) for that sequence is set to 0 (and if the interrupt is enabled). [31:31] 12 0x4 0-11 DAT[%s] DAT[%s] A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. 0x020 read-only 0 0x00000000 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [3:0] RESULT This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. [15:4] THCMPRANGE Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved. [17:16] THCMPCROSS Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. [19:18] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [25:20] CHANNEL This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc) [29:26] OVERRUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. [30:30] DATAVALID This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. [31:31] THR0_LOW A/D Low Compare Threshold Register 0 : Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. 0x050 read-write 0x0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [3:0] THRLOW Low threshold value against which A/D results will be compared [15:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] THR1_LOW A/D Low Compare Threshold Register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. 0x054 read-write 0x0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [3:0] THRLOW Low threshold value against which A/D results will be compared [15:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] THR0_HIGH A/D High Compare Threshold Register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. 0x058 read-write 0x0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [3:0] THRHIGH High threshold value against which A/D results will be compared [15:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] THR1_HIGH A/D High Compare Threshold Register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. 0x05C read-write 0x0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [3:0] THRHIGH High threshold value against which A/D results will be compared [15:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] CHAN_THRSEL A/D Channel-Threshold Select Register. Specifies which set of threshold compare registers are to be used for each channel 0x060 read-only 0x0 0xFFFFFFFF CH0_THRSEL Threshold select by channel. [0:0] ENUM THRESHOLD_0 Threshold 0. Channel 0 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 0 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH1_THRSEL Threshold select by channel. [1:1] ENUM THRESHOLD_0 Threshold 0. Channel 1 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 1 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH2_THRSEL Threshold select by channel. [2:2] ENUM THRESHOLD_0 Threshold 0. Channel 2 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 2 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH3_THRSEL Threshold select by channel. [3:3] ENUM THRESHOLD_0 Threshold 0. Channel 3 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 3 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH4_THRSEL Threshold select by channel. [4:4] ENUM THRESHOLD_0 Threshold 0. Channel 4 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 4 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH5_THRSEL Threshold select by channel. [5:5] ENUM THRESHOLD_0 Threshold 0. Channel 5 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 5 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH6_THRSEL Threshold select by channel. [6:6] ENUM THRESHOLD_0 Threshold 0. Channel 6 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 6 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH7_THRSEL Threshold select by channel. [7:7] ENUM THRESHOLD_0 Threshold 0. Channel 7 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 7 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH8_THRSEL Threshold select by channel. [8:8] ENUM THRESHOLD_0 Threshold 0. Channel 8 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 8 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH9_THRSEL Threshold select by channel. [9:9] ENUM THRESHOLD_0 Threshold 0. Channel 9 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 9 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH10_THRSEL Threshold select by channel. [10:10] ENUM THRESHOLD_0 Threshold 0. Channel 10 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 10 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH11_THRSEL Threshold select by channel. [11:11] ENUM THRESHOLD_0 Threshold 0. Channel 11 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 11 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] INTEN A/D Interrupt Enable Register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. 0x064 read-write 0x0 0xFFFFFFFF SEQA_INTEN Sequence A interrupt enable. [0:0] ENUM DISABLED Disabled. The sequence A interrupt/DMA request is disabled. 0 ENABLED Enabled. The sequence A interrupt/DMA request is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register. 1 SEQB_INTEN Sequence B interrupt enable. [1:1] ENUM DISABLED Disabled. The sequence B interrupt/DMA request is disabled. 0 ENABLED Enabled. The sequence B interrupt/DMA request is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register. 1 OVR_INTEN Overrun interrupt enable. [2:2] ENUM DISABLED Disabled. The overrun interrupt is disabled. 0 ENABLED Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt request. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt request to be asserted. 1 ADCMPINTEN0 Threshold comparison interrupt enable. [4:3] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 ADCMPINTEN1 Threshold comparison interrupt enable. [6:5] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved. 0x3 ADCMPINTEN2 Threshold comparison interrupt enable. [8:7] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 ADCMPINTEN3 Threshold comparison interrupt enable. [10:9] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 ADCMPINTEN4 Threshold comparison interrupt enable. [12:11] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 ADCMPINTEN5 Threshold comparison interrupt enable. [14:13] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 ADCMPINTEN6 Threshold comparison interrupt enable. [16:15] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved. 0x3 ADCMPINTEN7 Threshold comparison interrupt enable. [18:17] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 ADCMPINTEN8 Threshold comparison interrupt enable. [20:19] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 ADCMPINTEN9 Threshold comparison interrupt enable. [22:21] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 ADCMPINTEN10 Threshold comparison interrupt enable. [24:23] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 ADCMPINTEN11 Threshold comparison interrupt enable. [26:25] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:27] FLAGS A/D Flags Register. Contains the four interrupt request flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). 0x068 read-only 0x0 0xFFFFFFFF THCMP0 Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [0:0] THCMP1 Threshold comparison event on Channel 1. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [1:1] THCMP2 Threshold comparison event on Channel 2. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [2:2] THCMP3 Threshold comparison event on Channel 3. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [3:3] THCMP4 Threshold comparison event on Channel 4. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [4:4] THCMP5 Threshold comparison event on Channel 5. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [5:5] THCMP6 Threshold comparison event on Channel 6. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [6:6] THCMP7 Threshold comparison event on Channel 7. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [7:7] THCMP8 Threshold comparison event on Channel 8. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [8:8] THCMP9 Threshold comparison event on Channel 9. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [9:9] THCMP10 Threshold comparison event on Channel 10. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [10:10] THCMP11 Threshold comparison event on Channel 11. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [11:11] OVERRUN0 Mirrors the OVERRRUN status flag from the result register for A/D channel 0 [12:12] OVERRUN1 Mirrors the OVERRRUN status flag from the result register for A/D channel 1 [13:13] OVERRUN2 Mirrors the OVERRRUN status flag from the result register for A/D channel 2 [14:14] OVERRUN3 Mirrors the OVERRRUN status flag from the result register for A/D channel 3 [15:15] OVERRUN4 Mirrors the OVERRRUN status flag from the result register for A/D channel 4 [16:16] OVERRUN5 Mirrors the OVERRRUN status flag from the result register for A/D channel 5 [17:17] OVERRUN6 Mirrors the OVERRRUN status flag from the result register for A/D channel 6 [18:18] OVERRUN7 Mirrors the OVERRRUN status flag from the result register for A/D channel 7 [19:19] OVERRUN8 Mirrors the OVERRRUN status flag from the result register for A/D channel 8 [20:20] OVERRUN9 Mirrors the OVERRRUN status flag from the result register for A/D channel 9 [21:21] OVERRUN10 Mirrors the OVERRRUN status flag from the result register for A/D channel 10 [22:22] OVERRUN11 Mirrors the OVERRRUN status flag from the result register for A/D channel 11 [23:23] SEQA_OVR Mirrors the global OVERRUN status flag in the SEQA_GDAT register [24:24] SEQB_OVR Mirrors the global OVERRUN status flag in the SEQB_GDAT register [25:25] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [27:26] SEQA_INT Sequence A interrupt/DMA flag. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every A/D conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register. [28:28] SEQB_INT Sequence A interrupt/DMA flag. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every A/D conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN register. [29:29] THCMP_INT Threshold Comparison Interrupt/DMA flag. This bit will be set if any of the 12 THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the component flags in bits 11:0 are cleared via writing 1s to those bits. [30:30] OVR_INT Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers. [31:31] TRM ADC trim register. 0x06C read-write 0x00000F00 0xFFFFFFFF RESERVED Reserved. [4:0] VRANGE Reserved. [5:5] ENUM HIGH_VOLTAGE High voltage. VDDA = 2.7 V to 3.6 V. 0 LOW_VOLTAGE Low voltage. VDDA = 2.4 V to 2.7 V. 1 RESERVED Reserved. [31:6] DAC 12-bit DAC Modification DAC 0x40004000 0x0 0xFFF registers DAC 39 VAL D/A Converter Value Register. This register contains the digital value to be converted to analog. 0x000 read-write 0x0 0xFFFFFFFF RESERVED Reserved. Software should only write zeros to unused bits. [3:0] VALUE The voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V REFN)/4096) + VREFN. This voltage will be stable the selected settling time (specified by the BIAS field in the DAC Control Register) after this field is modified. [15:4] RESERVED Reserved. Software should only write zeros to unused bits. [31:16] CTRL DAC Control register. This register contains bits to configure DAC operation and the interrupt/dma request flag. 0x004 read-write 0x0 0xFFFFFFFF INT_DMA_FLAG Interrupt/DMA request flag. This bit is read-only. 0 = This bit is cleared upon any write to the DACVAL register. 1 = This bit is set by hardware only if a hardware trigger has been selected as follows: - If the internal timer is selected, this bit will be set when the timer times-out. - If an external trigger input is selected, this bit will be set when a transition of the specified polarity is detected on the selected input. [0:0] TRIG_SRC Hardware Trigger Source: If anyof these hardware trigger sources are selected, an interrupt/dma request will be generated when the specified trigger occurs. In addition, if double-buffering is enabled (the DBLBUF_ENA' bit is set), the DACVAL register will be loaded from the pre-buffer at the same time. [3:1] ENUM INTERNAL Internal. Selects the internal timer as the trigger source provided the timer is enabled (the TIMER_ENA bit is set). Otherwise (if the timer is not enabled), hardware triggering is disabled. If hardware triggering is disabled no interrupt or DMA requests will be generated. Double-buffering of the DAC VAL register is not useful and cannot be enabled when hardware triggering is disabled. 0x0 PIN Pin. External DAC_TRIG port input is selected. Also select this function in the PINASSIGN11 register in the switchmatrix. 0x1 POLARITY Specifies the polarity of the selected external trigger input. Does not apply if the TRIG_SRC field is set to 0. [4:4] ENUM RISING Rising. A trigger will be asserted when a RISING edge is detected on the selected external trigger input. 0 FALLING Falling. A trigger will be asserted when a FALLING edge is detected on the selected external trigger input. 1 SYNC_BYPASS Permits bypassing of one synchronization flip-flop, if not required. Does not apply if the TRIG_SRC field is set to 0. [5:5] ENUM SYNCHRONIZE Synchronize. The selected trigger input will be synchronized to the system clock prior to edge-detection. 0 NOT_SYNCHRONIZE Not synchronize. The selected trigger input will not be synchronized to the system clock prior to edge-detection. This will save one clock of latency. This bit should only be set f the selected hardware input trigger is from a source that is guaranteeed to already be synchronous to the system clock. 1 TIMER_ENA Timer Enable [6:6] ENUM DISABLED Disabled. The internal timer is disabled. If the TRIG_SEL field is also set to 000 then hardware triggering is disabled. 0 ENABLED Enabled. The internal timer is enabled and counting. Note: This bit should only be set after a valid count value has been programmed into the DACCNTVAL register. 1 DBLBUF_ENA Double-Buffer Enable. [7:7] ENUM DISABLED Disabled. Double-buffering of the DACVAL register is disabled. Software writes to the DACVAL address will directly modify the DAC data presented to the D/A converter. Hardware trigger events, if selected, will not affect the DACVAL contents. 0 ENABLED Enabled. The double-buffering feature in the DACVAL register is enabled. Writes to the DACVAL register are written to a pre-buffer and then transferred to the DACVAL when the specified hardware trigger occurs. Setting this bit will have no effect if hardware triggering is disabled. Double-buffering is of no value under this condition. 1 SHUTOFF_ENA Shutoff Enable [8:8] ENUM DISABLED Disabled. The hardware DAC-shutoff feature is disabled. 0 ENABLED Enabled. The hardware DAC-shutoff feature is enabled. Whenever the DAC_SHUTOFF (port pin) input is high, the DAC output voltage will be forced to zero. The DAC output will return to the value specifed in the DACVAL register once the input pin returns to the low state. 1 SHUTOFF_FLAG Shutoff Flag. This is a read-only bit. Reflects the state of the DAC_SHUTOFF input if the Shutoff feature is enabled. 0 = DAC_SHUTOFF (port pin) input is low. DAC is outputting the voltage specified in the DAC VAL register. 1 = DAC_SHUTOFF (port pin) input is high. The DAC output is forced to zero. This bit serves as a flag only, If a processor interrupt is desired when a DAC shutoff condition occurrs, that can be accomplished by enabling the port pin selected as the DAC_SHUTOFF pin to directly generate a port interrupt. [9:9] BIAS These bits permit trading-off longer DAC settling times to achieve reduced power consumption. The default setting provides maximum speed but also maximum power. [12:10] RESERVED Reserved. Software should only write zeros to unused bits. [31:13] CNTVAL DAC Counter Value register. This register contains the reload value for the internal DAC DMA/Interrupt timer. 0x008 read-write 0x0 0xFFFFFFFF CNTVAL 16-bit reload value for the internal DAC interrupt/DMA timer. The timer will overflow at the fixed rate of the system clock divided by CNTVAL+1. Upon each overflow an interrupt/dma request will be generated and the DAC VAL register contents will be updated if double-buffering is enabled. [15:0] RESERVED Reserved. Software should only write zeros to unused bits. [31:16] ACMP Analog comparators ACMP0/1/2/3 ACMP 0x40008000 0x0 0xFFF registers CMP0 40 CMP1 41 CMP2 42 CMP3 43 CTRL Comparator block control register 0x000 read-write 0x0 0xFFFFFFFF RESERVED Reserved. [7:0] ROSCCTL Selects the which comparators set and reset the ROSC output. [8:8] ENUM ACMP1_ACMP0 ACMP1/ACMP0. The ROSC output is set by ACMP1 and reset by ACMP0. 0 ACMP0_ACMP1 ACMP0/ACMP1. The ROSC output is set by ACMP0 and reset by ACMP1. 1 EXT_RESET Selects the reset source for the ROSC output. [9:9] ENUM INTERNAL Internal. The ROSC output is reset by the internal chip reset. 0 FROM_PIN_ROSC_RESET From pin ROSC_RESET. The ROSC output is reset by the ROSC_RESET input. 1 RESERVED Reserved. [31:10] CMP0 Comparator 0 source control 0x004 read-write 0x0 0xFFFFFFFF EN Comparator enable control. [0:0] ENUM DISABLED Disabled. Comparator disabled. 0 ENABLED Enabled. Comparator is enabled. 1 RESERVED Reserved. [1:1] INTEN Interrupt enable. [2:2] ENUM DISABLED Disabled. Interrupts are disabled.. 0 ENABLED Enabled. Interrupts are enabled.. Must set to 1 for interrupts to propagate to the NVIC and start-up logic. 1 STAT Comparator status. This bit reflects the comparator output [3:3] VM VM input select. [6:4] ENUM VREF_DIVIDER_0 Vref divider 0. 0x0 ACMP_I1 ACMP_I1. 0x1 ACMP_I2 ACMP_I2. 0x2 ACMP0_I3 ACMP0_I3. 0x3 ACMP0_I4 ACMP0_I4. 0x4 INTERNAL_0 Internal 0.9 V band gap reference. 0x5 TEMP_SENSOR Temp sensor. 0x6 ADC0_2 ADC0_2. Input for ADC0 channel 2. 0x7 RESERVED Reserved. [7:7] VP VP input select. [10:8] ENUM VREF_DIVIDER_0 Vref divider 0. 0x0 ACMP_I1 ACMP_I1. 0x1 ACMP_I2 ACMP_I2. 0x2 ACMP0_I3 ACMP0_I3. 0x3 ACMP0_I4 ACMP0_I4. 0x4 INTERNAL_0 Internal 0.9 V band gap reference. 0x5 TEMP_SENSOR Temp sensor. 0x6 ADC0_2 ADC0_2. Input for ADC0 channel 2. 0x7 RESERVED Reserved. [12:11] HYS Hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output. [14:13] ENUM HYSTERESIS_IS_TURNED Hysteresis is turned off, comparator output will change as the input voltages cross. 0x0 HYSTERESIS_EQ_5_MV Hysteresis = 5 mV. 0x1 HYSTERESIS_EQ_10_MV Hysteresis = 10 mV. 0x2 HYSTERESIS_EQ_15_MV Hysteresis = 15 mV. 0x3 INTPOL Selects the polarity of the CMP output for purposes of generating level interrupts. [15:15] ENUM NOT_INVERTED Not inverted. The output is used as-is for generating interrupts. 0 INVERTED Inverted. The output is used inverted for generating interrupts. 1 INTTYPE Select interrupt type. [16:16] ENUM EDGE Edge. Comparator interrupt is edge triggered. 0 LEVEL Level. Comparator interrupt is level triggered. 1 INTEDGE Select edge triggered interrupt to be active on either high or low transitions, when INTTYPE = 0. [18:17] ENUM FALLING Falling. Comparator interrupt is active on falling edges. 0x0 RISING Rising. Comparator interrupt is active on rising edges. 0x1 BOTH_EDGES Both edges. Comparator Interrupt is active on both edges. 0x2 RESERVED Reserved. 0x3 INTFLAG Interrupt flag. [19:19] ENUM NOT_PENDING Not pending. The Comparator interrupt is not pending. 0 PENDING Pending. The Comparator interrupt is pending. Writing a 1 to this bit clears the flag. 1 VLADEN Voltage ladder enable for comparator 0. [20:20] ENUM DISABLED Disabled. The Comparator voltage ladder is disabled. 0 ENABLED Enabled. The Comparator voltage ladder is enabled. 1 RESERVED Reserved. [21:21] VLADREF Voltage reference select for comparator 0 voltage ladder. [22:22] ENUM VREF_CMP_PIN VREF_CMP pin. 0 VDDA_PIN VDDA pin. 1 RESERVED Reserved. [23:23] VSEL Voltage ladder value for comparator 0. The reference voltage Vref depends on the setting of VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x Vref / 31. 00010 = 2 x Vref / 31. ... 11111 = Vref [28:24] DLY Configure the propagation delay. A shorter propagation delay means higher power consumption. Use values from 0x0 (shortest propagation delay and highest power consumption) to 0x2 (longest propagation delay and lowest power consumption). See the data sheet for details. [30:29] RESERVED Reserved. [31:31] CMP1 Comparator 1 source control 0x00C read-write 0x0 0xFFFFFFFF EN Comparator enable control. [0:0] ENUM DISABLED Disabled. Comparator disabled. 0 ENABLED Enabled. Comparator is enabled. 1 RESERVED Reserved. [1:1] INTEN Interrupt enable. [2:2] ENUM DISABLED Disabled. Interrupts are disabled.. 0 ENABLED Enabled. Interrupts are enabled.. Must set to 1 for interrupts to propagate to the NVIC and start-up logic. 1 STAT Comparator status. This bit reflects the comparator output [3:3] VM VM input select. [6:4] ENUM VREF_DIVIDER_1 Vref divider 1. 0x0 ACMP_I1 ACMP_I1. 0x1 ACMP_I2 ACMP_I2. 0x2 ACMP1_I3 ACMP1_I3. 0x3 ACMP1_I4 ACMP1_I4. 0x4 INTERNAL_0 Internal 0.9 V band gap reference. 0x5 ADC0_1 ADC0_1. Input for ADC0 channel 1. 0x6 ADC0_3 ADC0_3. Input for ADC0 channel 3. 0x7 RESERVED Reserved. [7:7] VP VP input select. [10:8] ENUM VREF_DIVIDER_1 Vref divider 1. 0x0 ACMP_I1 ACMP_I1. 0x1 ACMP_I2 ACMP_I2. 0x2 ACMP1_I3 ACMP1_I3. 0x3 ACMP1_I4 ACMP1_I4. 0x4 INTERNAL_0 Internal 0.9 V band gap reference. 0x5 ADC0_1 ADC0_1. Input for ADC0 channel 1. 0x6 ADC0_3 ADC0_3. Input for ADC0 channel 3. 0x7 RESERVED Reserved. [12:11] HYS Hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output. [14:13] ENUM HYSTERESIS_IS_TURNED Hysteresis is turned off, comparator output will change as the input voltages cross. 0x0 HYSTERESIS_EQ_5_MV Hysteresis = 5 mV. 0x1 HYSTERESIS_EQ_10_MV Hysteresis = 10 mV. 0x2 HYSTERESIS_EQ_15_MV Hysteresis = 15 mV. 0x3 INTPOL Selects the polarity of the CMP output for purposes of generating level interrupts. [15:15] ENUM NOT_INVERTED Not inverted. The output is used as-is for generating interrupts. 0 INVERTED Inverted. The output is used inverted for generating interrupts. 1 INTTYPE Select interrupt type. [16:16] ENUM EDGE Edge. Comparator interrupt is edge triggered. 0 LEVEL Level. Comparator interrupt is level triggered. 1 INTEDGE Select edge triggered interrupt to be active on either high or low transitions, when INTTYPE = 0. [18:17] ENUM FALLING Falling. Comparator interrupt is active on falling edges. 0x0 RISING Rising. Comparator interrupt is active on rising edges. 0x1 BOTH_EDGES Both edges. Comparator Interrupt is active on both edges. 0x2 RESERVED Reserved. 0x3 INTFLAG Interrupt flag. [19:19] ENUM NOT_PENDING Not pending. The Comparator interrupt is not pending. 0 PENDING Pending. The Comparator interrupt is pending. Writing a 1 to this bit clears the flag. 1 VLADEN Voltage ladder enable for comparator 1. [20:20] ENUM DISABLED Disabled. The Comparator voltage ladder is disabled. 0 ENABLED Enabled. The Comparator voltage ladder is enabled. 1 RESERVED Reserved. [21:21] VLADREF Voltage reference select for comparator 1 voltage ladder. [22:22] ENUM VREF_CMP_PIN VREF_CMP pin. 0 VDDA_PIN VDDA pin. 1 RESERVED Reserved. [23:23] VSEL Voltage ladder value for comparator 1. The reference voltage Vref depends on the setting of VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x Vref / 31. 00010 = 2 x Vref / 31. ... 11111 = Vref [28:24] DLY Configure the propagation delay. A shorter propagation delay means higher power consumption. Use values from 0x0 (shortest propagation delay and highest power consumption) to 0x2 (longest propagation delay and lowest power consumption). See the data sheet for details. [30:29] RESERVED Reserved. [31:31] CMP2 Comparator 2 source control 0x014 read-write 0x0 0xFFFFFFFF EN Comparator enable control. [0:0] ENUM DISABLED Disabled. Comparator disabled. 0 ENABLED Enabled. Comparator is enabled. 1 RESERVED Reserved. [1:1] INTEN Interrupt enable. [2:2] ENUM DISABLED Disabled. Interrupts are disabled.. 0 ENABLED Enabled. Interrupts are enabled.. Must set to 1 for interrupts to propagate to the NVIC and start-up logic. 1 STAT Comparator status. This bit reflects the comparator output [3:3] VM VM input select. [6:4] ENUM VREF_DIVIDER_2 Vref divider 2. 0x0 ACMP_I1 ACMP_I1. 0x1 ACMP_I2 ACMP_I2. 0x2 ACMP2_I3 ACMP2_I3. 0x3 ACMP2_I4 ACMP2_I4. 0x4 INTERNAL_0 Internal 0.9 V band gap reference. 0x5 ADC0_0 ADC0_0. Input for ADC0 channel 0. 0x6 ADC1_2 ADC1_2. Input for ADC1 channel 2. 0x7 RESERVED Reserved. [7:7] VP VP input select. [10:8] ENUM VREF_DIVIDER_2 Vref divider 2. 0x0 ACMP_I1 ACMP_I1. 0x1 ACMP_I2 ACMP_I2. 0x2 ACMP2_I3 ACMP2_I3. 0x3 ACMP2_I4 ACMP2_I4. 0x4 INTERNAL_0 Internal 0.9 V band gap reference. 0x5 ADC0_0 ADC0_0. Input for ADC0 channel 0. 0x6 ADC1_2 ADC1_2. Input for ADC1 channel 2. 0x7 RESERVED Reserved. [12:11] HYS Hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output. [14:13] ENUM HYSTERESIS_IS_TURNED Hysteresis is turned off, comparator output will change as the input voltages cross. 0x0 HYSTERESIS_EQ_5_MV Hysteresis = 5 mV. 0x1 HYSTERESIS_EQ_10_MV Hysteresis = 10 mV. 0x2 HYSTERESIS_EQ_15_MV Hysteresis = 15 mV. 0x3 INTPOL Selects the polarity of the CMP output for purposes of generating level interrupts. [15:15] ENUM NOT_INVERTED Not inverted. The output is used as-is for generating interrupts. 0 INVERTED Inverted. The output is used inverted for generating interrupts. 1 INTTYPE Select interrupt type. [16:16] ENUM EDGE Edge. Comparator interrupt is edge triggered. 0 LEVEL Level. Comparator interrupt is level triggered. 1 INTEDGE Select edge triggered interrupt to be active on either high or low transitions, when INTTYPE = 0. [18:17] ENUM FALLING Falling. Comparator interrupt is active on falling edges. 0x0 RISING Rising. Comparator interrupt is active on rising edges. 0x1 BOTH_EDGES Both edges. Comparator Interrupt is active on both edges. 0x2 RESERVED Reserved. 0x3 INTFLAG Interrupt flag. [19:19] ENUM NOT_PENDING Not pending. The Comparator interrupt is not pending. 0 PENDING Pending. The Comparator interrupt is pending. Writing a 1 to this bit clears the flag. 1 VLADEN Voltage ladder enable for comparator 2. [20:20] ENUM DISABLED Disabled. The Comparator voltage ladder is disabled. 0 ENABLED Enabled. The Comparator voltage ladder is enabled. 1 RESERVED Reserved. [21:21] VLADREF Voltage reference select for comparator 2 voltage ladder. [22:22] ENUM VREF_CMP_PIN VREF_CMP pin. 0 VDDA_PIN VDDA pin. 1 RESERVED Reserved. [23:23] VSEL Voltage ladder value for comparator 2. The reference voltage Vref depends on the setting of VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x Vref / 31. 00010 = 2 x Vref / 31. ... 11111 = Vref [28:24] DLY Configure the propagation delay. A shorter propagation delay means higher power consumption. Use values from 0x0 (shortest propagation delay and highest power consumption) to 0x2 (longest propagation delay and lowest power consumption). See the data sheet for details. [30:29] RESERVED Reserved. [31:31] CMP3 Comparator 3 source control 0x01C read-write 0x0 0xFFFFFFFF EN Comparator enable control. [0:0] ENUM DISABLED Disabled. Comparator disabled. 0 ENABLED Enabled. Comparator is enabled. 1 RESERVED Reserved. [1:1] INTEN Interrupt enable. [2:2] ENUM DISABLED Disabled. Interrupts are disabled.. 0 ENABLED Enabled. Interrupts are enabled.. Must set to 1 for interrupts to propagate to the NVIC and start-up logic. 1 STAT Comparator status. This bit reflects the comparator output [3:3] VM VM input select. [6:4] ENUM VREF_DIVIDER_3 Vref divider 3. 0x0 ACMP_I1 ACMP_I1. 0x1 ACMP_I2 ACMP_I2. 0x2 ACMP3_I3 ACMP3_I3. 0x3 ACMP3_I4 ACMP3_I4. 0x4 INTERNAL_0 Internal 0.9 V band gap reference. 0x5 ADC1_1 ADC1_1. Input for ADC1 channel 1. 0x6 ADC1_3 ADC1_3. Input for ADC1 channel 3. 0x7 RESERVED Reserved. [7:7] VP VP input select. [10:8] ENUM VREF_DIVIDER_3 Vref divider 3. 0x0 ACMP_I1 ACMP_I1. 0x1 ACMP_I2 ACMP_I2. 0x2 ACMP3_I3 ACMP3_I3. 0x3 ACMP3_I4 ACMP3_I4. 0x4 INTERNAL_0 Internal 0.9 V band gap reference. 0x5 ADC1_1 ADC1_1. Input for ADC1 channel 1. 0x6 ADC1_3 ADC1_3. Input for ADC1 channel 3. 0x7 RESERVED Reserved. [12:11] HYS Hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output. [14:13] ENUM HYSTERESIS_IS_TURNED Hysteresis is turned off, comparator output will change as the input voltages cross. 0x0 HYSTERESIS_EQ_5_MV Hysteresis = 5 mV. 0x1 HYSTERESIS_EQ_10_MV Hysteresis = 10 mV. 0x2 HYSTERESIS_EQ_15_MV Hysteresis = 15 mV. 0x3 INTPOL Selects the polarity of the CMP output for purposes of generating level interrupts. [15:15] ENUM NOT_INVERTED Not inverted. The output is used as-is for generating interrupts. 0 INVERTED Inverted. The output is used inverted for generating interrupts. 1 INTTYPE Select interrupt type. [16:16] ENUM EDGE Edge. Comparator interrupt is edge triggered. 0 LEVEL Level. Comparator interrupt is level triggered. 1 INTEDGE Select edge triggered interrupt to be active on either high or low transitions, when INTTYPE = 0. [18:17] ENUM FALLING Falling. Comparator interrupt is active on falling edges. 0x0 RISING Rising. Comparator interrupt is active on rising edges. 0x1 BOTH_EDGES Both edges. Comparator Interrupt is active on both edges. 0x2 RESERVED Reserved. 0x3 INTFLAG Interrupt flag. [19:19] ENUM NOT_PENDING Not pending. The Comparator interrupt is not pending. 0 PENDING Pending. The Comparator interrupt is pending. Writing a 1 to this bit clears the flag. 1 VLADEN Voltage ladder enable for comparator 3. [20:20] ENUM DISABLED Disabled. The Comparator voltage ladder is disabled. 0 ENABLED Enabled. The Comparator voltage ladder is enabled. 1 RESERVED Reserved. [21:21] VLADREF Voltage reference select for comparator 3 voltage ladder. [22:22] ENUM VREF_CMP_PIN VREF_CMP pin. 0 VDDA_PIN VDDA pin. 1 RESERVED Reserved. [23:23] VSEL Voltage ladder value for comparator 3. The reference voltage Vref depends on the setting of VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x Vref / 31. 00010 = 2 x Vref / 31. ... 11111 = Vref [28:24] DLY Configure the propagation delay. A shorter propagation delay means higher power consumption. Use values from 0x0 (shortest propagation delay and highest power consumption) to 0x2 (longest propagation delay and lowest power consumption). See the data sheet for details. [30:29] RESERVED Reserved. [31:31] 4 0x8 0-3 CMPFILTR%s Comparator 0 pin filter set-up 0x008 read-write 0x0 0xFFFFFFFF S_MODE Digital filter sample mode. [1:0] ENUM BYPASS_INPUT_FILTER Bypass input filter. 0x0 1_CLOCK_CYCLE 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLKDIV Select clock divider for comparator clock CMP_PCLK. [4:2] ENUM CMP_PCLK CMP_PCLK. 0x0 CMP_PCLKDIV2 CMP_PCLK/2. 0x1 CMP_PCLKDIV4 CMP_PCLK/4. 0x2 CMP_PCLKDIV8 CMP_PCLK/8. 0x3 CMP_PCLKDIV16 CMP_PCLK/16. 0x4 CMP_PCLKDIV32 CMP_PCLK/32. 0x5 CMP_PCLKDIV64 CMP_PCLK/64. 0x6 RESERVED Reserved [31:5] INMUX Input multiplexing (INMUX) INMUX 0x40014000 0x0 0xFFF registers 7 0x4 0-6 SCT0_INMUX[%s] SCT0_INMUX[%s] Pinmux register for SCT0 input 0 0x000 read-write 0x1F 0xFFFFFFFF INP_N Input number (decimal value) to SCT0 inputs 0 to 6. 0 = PIO0_2 (external pin) 1 = PIO0_3 (external pin) 2 = PIO0_17 (external pin) 3 = PIO0_30 (external pin) 4 = PIO1_6 (external pin) 5 = PIO1_7 (external pin) 6 = PIO1_12 (external pin) 7 = PIO1_13 (external pin) 8 = SCT1_OUT4 (large SCT1 output 4) 9 = SCT2_OUT4 (companion small SCT2 output 4) 10 = SCT2_OUT5 (companion small SCT2 output 5) 11 = ADC0_THCMP_IRQ () 12 = ADC1_THCMP_IRQ () 13 = COMP0_OUT (One output from each analog comparator) 14 = COMP1_OUT 15 = COMP2_OUT 16 = COMP3_OUT 17 = SCTIPU_ABORT 18 = SCTIPU_SAMPLE0 19 = SCTIPU_SAMPLE1 20 = SCTIPU_SAMPLE2 21 = SCTIPU_SAMPLE3 22 = DEBUG_HALTED (from ARM Cortex CoreSight Debugger) [4:0] PIO0_2 PIO0_2 (external pin) 0x0 PIO0_3 PIO0_3 (external pin) 0x1 PIO0_17 PIO0_17 (external pin) 0x2 PIO0_30 PIO0_30 (external pin) 0x3 PIO1_6 PIO1_6 (external pin) 0x4 PIO1_7 PIO1_7 (external pin) 0x5 PIO1_12 PIO1_12 (external pin) 0x6 PIO1_13 PIO1_13 (external pin) 0x7 SCT1_OUT4 SCT1_OUT4 (large SCT1 output 4) 0x8 SCT2_OUT4 SCT2_OUT4 (small SCT2 output 4) 0x9 SCT2_OUT5 SCT2_OUT5 (small SCT2 output 5) 0xA ADC0_THCMP_IRQ ADC0_THCMP_IRQ (ADC0 threshold compare interrupt) 0xB ADC1_THCMP_IRQ ADC1_THCMP_IRQ (ADC1 threshold compare interrupt) 0xC ACMP0_OUT ACMP0_OUT (One output from each analog comparator) 0xD ACMP1_OUT ACMP1_OUT (One output from each analog comparator) 0xE ACMP2_OUT ACMP2_OUT (One output from each analog comparator) 0xF ACMP3_OUT ACMP3_OUT (One output from each analog comparator) 0x10 SCTIPU_ABORT SCTIPU_ABORT 0x11 SCTIPU_SAMPLE0 SCTIPU_SAMPLE0 0x12 SCTIPU_SAMPLE1 SCTIPU_SAMPLE1 0x13 SCTIPU_SAMPLE2 SCTIPU_SAMPLE2 0x14 SCTIPU_SAMPLE3 SCTIPU_SAMPLE3 0x15 DEBUG_HALTED ARM DEBUG HALTED 0x16 RESERVED Reserved. [31:5] 7 0x4 0-6 SCT1_INMUX[%s] SCT1_INMUX[%s] Pinmux register for SCT1 input 0 0x020 read-write 0x1F 0xFFFFFFFF INP_N Input number (decimal value) to SCT1 inputs 0 to 6. 0 = PIO0_15 (external pin) 1 = PIO0_16 (external pin) 2 = PIO0_21 (external pin) 3 = PIO0_31 (external pin) 4 = PIO1_4 (external pin) 5 = PIO1_5 (external pin) 6 = PIO1_15 (external pin) 7 = PIO1_16 (external pin) 8 = SCT0_OUT4 (large SCT0 output 4) 9 = SCT3_OUT4 (small companion SCT3 output 4) 10 = SCT3_OUT5 (small companion SCT3 output 5) 11 = ADC0_THCMP_IRQ 12 = ADC1_THCMP_IRQ 13 = COMP0_OUT (One output from each analog comparator) 14 = COMP1_OUT 15 = COMP2_OUT 16 = A COMP3_OUT 17 = SCTIPU_ABORT 18 = SCTIPU_SAMPLE0 19 = SCTIPU_SAMPLE1 20 = SCTIPU_SAMPLE2 21 = SCTIPU_SAMPLE3 22 = DEBUG_HALTED DEBUG_HALTED (from ARM Cortex CoreSight Debugger) [4:0] RESERVED Reserved. [31:5] 3 0x4 0-2 SCT2_INMUX[%s] SCT2_INMUX[%s] Pinmux register for SCT2 input 0 0x040 read-write 0x1F 0xFFFFFFFF INP_N Input number (decimal value) to SCT2 inputs 0 to 2. 0 = P0_4 (external pin) 1 = P0_27 (external pin) 2 = P1_18 (external pin) 3 = P1_19 (external pin) 4 = SCT0_OUT4 5 = SCT0_OUT5 6 = SCT0_OUT7 7 = SCT0_OUT8 8 = ADC0_THCMP_IRQ 9 = ADC1_THCMP_IRQ 10 = COMP0_OUT (One output from each analog comparator) 11 = COMP1_OUT 12 = COMP2_OUT 13 = COMP3_OUT 14 = SCTIPU_ABORT 15 = SCTIPU_SAMPLE0 16 = SCTIPU_SAMPLE1 17 = SCTIPU_SAMPLE2 18 = SCTIPU_SAMPLE3 19 = USB_FRAME_TOGGLE 20 = DEBUG_HALTED [4:0] RESERVED Reserved. [31:5] 3 0x4 0-2 SCT3_INMUX[%s] SCT3_INMUX[%s] Pinmux register for SCT3 input 0 0x060 read-write 0x1F 0xFFFFFFFF INP_N Input number (decimal value) to SCT3 inputs 0 to 2. 0 = PIO0_7 1 = PIO1_11 2 = PIO1_21 3 = PIO1_22 4 = SCT1_OUT4 5 = SCT1_OUT5 6 = SCT1_OUT7 7 = SCT1_OUT8 8 = ADC0_THCMP_IRQ 9 = ADC1_THCMP_IRQ 10 = COMP0_OUT 11 = COMP1_OUT 12 = COMP2_OUT 13 = COMP3_OUT 14 = SCTIPU_ABORT3 15 = SCTIPU_SAMPLE0 16 = SCTIPU_SAMPLE1 17 = SCTIPU_SAMPLE2 18 = SCTIPU_SAMPLE3 19 = USB_FRAME_TOGGLE 20 = DEBUG_HALTED [4:0] RESERVED Reserved. [31:5] 8 0x4 0-7 PINTSEL[%s] PINTSEL[%s] Pin interrupt select register 0 0x0C0 read-write 0 0x7F INTPIN Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63). [7:0] RESERVED Reserved [31:7] 18 0x4 0-17 DMA_ITRIG_INMUX[%s] DMA_ITRIG_INMUX[%s] Trigger input for DMA channel 0 select register. 0x0E0 read-write 0x1F 0xFFFFFFFF INP_N Trigger input number (decimal value) to DMA channel n. 0 = ADC0_SEQA_IRQ 1 = ADC0_SEQB_IRQ 2 = ADC1_SEQA_IRQ 3 = ADC1_SEQB_IRQ 4 = SCT0_DMA0 5 = SCT0_DMA1 6 = SCT1_DMA0 7 = SCT1_DMA1 8 = SCT2_DMA0 9 = SCT2_DMA1 10 = SCT3_DMA0 11 = SCT3_DMA1 12 = COMP0_OUT (One output from each analog comparator) 13 = COMP1_OUT 14 = COMP2_OUT 15 = COMP3_OUT 16 = SDMA_TRIGOUT_A 17 = SDMA_TRIGOUT_B 18 = SDMA_TRIGOUT_C 19 = SDMA_TRIGOUT_D [4:0] RESERVED Reserved. [31:5] 4 0x4 0-3 DMA_INMUX_INMUX[%s] DMA_INMUX_INMUX[%s] DMA trigger input select register. 0x140 read-write 0x1F 0xFFFFFFFF INP DMA trigger output number [4:0] RESERVED Reserved. [31:5] FREQMEAS_REF Clock selection for frequency measurement function reference clock 0x160 read-write 0xF 0xFFFFFFFF CLKIN Clock source number (decimal value) for frequency measure function target clock: 0 = System oscilator (MAIN_OSC) 1 = IRC 2 = WDOSC 3 = 32KHZOSC 4 = USB_FTOGGLE 5 = PIO0_5 6 = PIO0_19 7 = PIO0_30 8 = PIO1_27 [3:0] RESERVED Reserved. [31:4] FREQMEAS_TARGET Clock selection for frequency measurement function target clock 0x164 read-write 0xF 0xFFFFFFFF CLKIN Clock source number (decimal value) for frequency measure function target clock: 0 = System oscillator (MAIN_OSC) 1 = IRC 2 = WDOSC 3 = 32KHZOSC 4 = USB_FTOGGLE 5 = PIO0_5 6 = PIO0_19 7 = PIO0_30 8 = PIO1_27 [3:0] RESERVED Reserved. [31:4] RTC Real-Time Clock (RTC) RTC 0x40028000 0x0 0xFFF registers RTC_ALARM 45 RTC_WAKE 46 CTRL RTC control register 0x000 read-write 0xF 0xFFFFFFFF SWRESET Software reset control [0:0] ENUM NOT_IN_RESET Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. 0 IN_RESET In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared. This bit may also serve as a Power Fail Detect flag for the always-on voltage domain. 1 OFD Oscillator fail detect status. [1:1] ENUM RUN Run. The RTC oscillator is running properly. Writing a 0 has no effect. 0 FAIL Fail. RTC oscillator fail detected. Clear this flag after the following power-up. Writing a 1 clears this bit. 1 ALARM1HZ RTC 1 Hz timer alarm flag status. [2:2] ENUM NO_MATCH No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. 0 MATCH Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. 1 WAKE1KHZ RTC 1 kHz timer wake-up flag status. [3:3] ENUM RUN Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. 0 TIME_OUT Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. 1 ALARMDPD_EN RTC 1 Hz timer alarm enable for Deep power-down. [4:4] ENUM DISABLE Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. 0 ENABLE Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. 1 WAKEDPD_EN RTC 1 kHz timer wake-up enable for Deep power-down. [5:5] ENUM DISABLE Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. 0 ENABLE Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. 1 RTC1KHZ_EN RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). [6:6] ENUM DISABLE Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. 0 ENABLE Enable. The 1 kHz RTC timer is enabled. 1 RTC_EN RTC enable. [7:7] ENUM DISABLE Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register. 0 ENABLE Enable. The 1 Hz RTC clock is running and RTC operation is enabled. You must set this bit to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register. 1 RESERVED Reserved [31:8] MATCH RTC match register 0x004 read-write 0xFFFF 0xFFFFFFFF MATVAL Contains the match value against which the 1 Hz RTC timer will be compared to generate set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. [31:0] COUNT RTC counter register 0x008 read-write 0 0xFFFFFFFF VAL A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC1HZ_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC1HZ_EN bit is set. [31:0] WAKE RTC high-resolution/wake-up timer control register 0x00C read-write 0 0xFFFFFFFF VAL A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress. [15:0] RESERVED Reserved. [31:16] WWDT Windowed Watchdog Timer (WWDT) WWDT 0x4002C000 0x0 0xFFF registers WDT 0 MOD Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. 0x000 read-write 0 0xFFFFFFFF WDEN Watchdog enable bit. Once this bit has been written with a 1, it cannot be re-written with a 0. Once this bit is set to one and performing a watchdog feed, the watchdog timer starts running permanently. [0:0] ENUM STOP Stop. The watchdog timer is stopped. 0 RUN Run. The watchdog timer is running. 1 WDRESET Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. [1:1] ENUM INTERRUPT Interrupt. A watchdog time-out will not cause a chip reset. 0 RESET Reset. A watchdog time-out will cause a chip reset. 1 WDTOF Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1. [2:2] WDINT Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. [3:3] WDPROTECT Watchdog update mode. This bit can be set once by software and is only cleared by a reset. [4:4] ENUM FLEXIBLE Flexible. The watchdog time-out value (TC) can be changed at any time. 0 THRESHOLD Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. 1 LOCK A 1 in this bit prevents disabling or powering down the watchdog oscillator. This bit can be set once by software and is only cleared by any reset. [5:5] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] TC Watchdog timer constant register. This 24-bit register determines the time-out value. 0x004 read-write 0xFF 0xFFFFFFFF COUNT Watchdog time-out value. [23:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] FEED Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. 0x008 write-only 0 0x00000000 FEED Feed value should be 0xAA followed by 0x55. [7:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] TV Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. 0x00C read-only 0xFF 0xFFFFFFFF COUNT Counter timer value. [23:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] WARNINT Watchdog Warning Interrupt compare value. 0x014 read-write 0 0xFFFFFFFF WARNINT Watchdog warning interrupt compare value. [9:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] WINDOW Watchdog Window compare value. 0x018 read-write 0xFFFFFF 0xFFFFFFFF WINDOW Watchdog window value. [23:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] SWM Switch Matrix (SWM) SWM 0x40038000 0x0 0xFFF registers PINASSIGN0 Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS. 0x000 read-write 0xFFFFFFFF 0xFFFFFFFF UART0_TXD_O UART0_TXD function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [7:0] UART0_RXD_I UART0_RXD function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [15:8] UART0_RTS_O UART0_RTS function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [23:16] UART0_CTS_I UART0_CTS function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [31:24] PINASSIGN1 Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, U1_RXD, U1_RTS. 0x004 read-write 0xFFFFFFFF 0xFFFFFFFF UART0_SCLK_IO UART0_SCLK function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [7:0] UART1_TXD_O UART1_TXD function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [15:8] UART1_RXD_I UART1_RXD function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [23:16] UART1_RTS_O UART1_RTS function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [31:24] PINASSIGN2 Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK, U2_TXD, U2_RXD. 0x008 read-write 0xFFFFFFFF 0xFFFFFFFF UART1_CTS_I UART1_CTS function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [7:0] UART1_SCLK_IO UART1_SCLK function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [15:8] UART2_TXD_O UART2_TXD function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [23:16] UART2_RXD_I UART2_RXD function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [31:24] PINASSIGN3 Pin assign register 3. Assign movable function . 0x00C read-write 0xFFFFFFFF 0xFFFFFFFF UART2_SCLK_IO UART2_SCLK function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [7:0] SSP0_SCK_IO SSP0_SCK function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [15:8] SSP0_MOSI_IO SSP0_MOSI function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [23:16] SSP0_MISO_IO SSP0_MISO function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [31:24] PINASSIGN4 Pin assign register 4. Assign movable functions 0x010 read-write 0xFFFFFFFF 0xFFFFFFFF SSP0_SSELSN_0_IO SSP0_SSELSN_0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [7:0] SSP0_SSELSN_1_IO SSP0_SSELSN_1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [15:8] SSP0_SSELSN_2_IO SSP0_SSELSN_2 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [23:16] SSP0_SSELSN_3_IO SSP0_SSELSN_3 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [31:24] PINASSIGN5 Pin assign register 5. Assign movable functions 0x014 read-write 0xFFFFFFFF 0xFFFFFFFF SSP1_SCK_IO SSP1_SCK function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [7:0] SSP1_MOSI_IO SSP1_MOSI function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [15:8] SSP1_MISO_IO SSP1_MISO function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [23:16] SSP1_SSELSN_0_IO SSP1_SSELSN_0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [31:24] PINASSIGN6 Pin assign register 6. Assign movable functions 0x018 read-write 0xFFFFFFFF 0xFFFFFFFF SSP1_SSELSN_1_IO SSP1_SSELSN_1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [7:0] CAN_TD1_O CAN_TD1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [15:8] CAN_RD1_I CAN_RD1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [23:16] USB_CONNECTN_O USB_CONNECTN function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [31:24] PINASSIGN7 Pin assign register 7. Assign movable functions 0x01C read-write 0xFFFFFFFF 0xFFFFFFFF USB_VBUS_I USB_VBUS function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [7:0] SCT0_OUT0_O SCT0_OUT0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [15:8] SCT0_OUT1_O SCT0_OUT1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [23:16] SCT0_OUT2_O SCT0_OUT2 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [31:24] PINASSIGN8 Pin assign register 8. Assign movable functions 0x020 read-write 0xFFFFFFFF 0xFFFFFFFF SCT1_OUT0_O SCT1_OUT0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [7:0] SCT1_OUT1_O SCT1_OUT1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [15:8] SCT1_OUT2_O SCT1_OUT2 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [23:16] SCT2_OUT0_O SCT2_OUT0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [31:24] PINASSIGN9 Pin assign register 9. Assign movable functions 0x024 read-write 0xFFFFFFFF 0xFFFFFFFF SCT2_OUT1_O SCT2_OUT1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [7:0] SCT2_OUT2_O SCT2_OUT2 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [15:8] SCT3_OUT0_O SCT3_OUT0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [23:16] SCT3_OUT1_O SCT3_OUT1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [31:24] PINASSIGN10 Pin assign register 10. Assign movable functions 0x028 read-write 0xFFFFFFFF 0xFFFFFFFF SCT3_OUT2_O SCT3_OUT2 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [7:0] SCT_ABORT0_I SCT_ABORT0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [15:8] SCT_ABORT1_I SCT_ABORT1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [23:16] ADC0_PIN_TRIG0_I ADC0_PIN_TRIG0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [31:24] PINASSIGN11 Pin assign register 11. Assign movable functions 0x02C read-write 0xFFFFFFFF 0xFFFFFFFF ADC0_PIN_TRIG1_I ADC0_PIN_TRIG1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [7:0] ADC1_PIN_TRIG0_I ADC1_PIN_TRIG0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [15:8] ADC1_PIN_TRIG1_I ADC1_PIN_TRIG1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [23:16] DAC_PIN_TRIG_I DAC_PIN_TRIG function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [31:24] PINASSIGN12 Pin assign register 12. Assign movable functions 0x030 read-write 0xFFFFFFFF 0xFFFFFFFF DAC_SHUTOFF_I DAC_SHUTOFF function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [7:0] ACMP0_OUT_O ACMP0_OUT function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [15:8] ACMP1_OUT_O ACMP1_OUT function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [23:16] ACMP2_OUT_O ACMP2_OUT function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [31:24] PINASSIGN13 Pin assign register 13. Assign movable functions 0x034 read-write 0xFFFFFFFF 0xFFFFFFFF ACMP3_OUT_O ACMP3_OUT function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [7:0] CLK_OUT_O CLK_OUT function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [15:8] ROSC0_O ROSC0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [23:16] ROSC_RST0_I ROSC_RST0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [31:24] PINASSIGN14 Pin assign register 14. Assign movable functions 0x038 read-write 0xFFFFFFFF 0xFFFFFFFF USB_FRAME_TOG_O USB_FRAME_TOG function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [7:0] QEI0_PHA_I QEI0_PHA function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [15:8] QEI0_PHB_I QEI0_PHB function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [23:16] QEI0_IDX_I QEI0_IDX function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [31:24] PINASSIGN15 Pin assign register 15. Assign movable functions 0x03C read-write 0xFFFFFFFF 0xFFFFFFFF GPIO_INT_BMATCH_O GPIO_INT_BMATCH function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [7:0] SWO_O SWO function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75. [15:8] RESERVED Reserved. [23:16] RESERVED Reserved. [31:24] PINENABLE0 Pin enable register 0. Enables fixed-pin functions 0x1C0 read-write 0 0x00000000 ADC0_0 ADC0_0 pin enable. [0:0] ENUM ENABLED_ON_PIN_P0_08 Enabled on pin P0_08. 0 DISABLED Disabled. 1 ADC0_1 ADC0_1 pin enable. [1:1] ENUM ENABLED_ON_PIN_P0_07 Enabled on pin P0_07. 0 DISABLED Disabled. 1 ADC0_2 ADC0_2 pin enable. [2:2] ENUM ENABLED_ON_PIN_P0_06 Enabled on pin P0_06. 0 DISABLED Disabled. 1 ADC0_3 ADC0_3 pin enable. [3:3] ENUM ENABLED_ON_PIN_P0_05 Enabled on pin P0_05. 0 DISABLED Disabled. 1 ADC0_4 ADC0_4 pin enable. [4:4] ENUM ENABLED_ON_PIN_P0_04 Enabled on pin P0_04. 0 DISABLED Disabled. 1 ADC0_5 ADC0_5 pin enable. [5:5] ENUM ENABLED_ON_PIN_P0_03 Enabled on pin P0_03. 0 DISABLED Disabled. 1 ADC0_6 ADC0_6 pin enable. [6:6] ENUM ENABLED_ON_PIN_P0_02 Enabled on pin P0_02. 0 DISABLED Disabled. 1 ADC0_7 ADC0_7 pin enable. [7:7] ENUM ENABLED_ON_PIN_P0_01 Enabled on pin P0_01. 0 DISABLED Disabled. 1 ADC0_8 ADC0_8 pin enable. [8:8] ENUM ENABLED_ON_PIN_P1_00 Enabled on pin P1_00 . 0 DISABLED Disabled. 1 ADC0_9 ADC0_9 pin enable. [9:9] ENUM ENABLED_ON_PIN_P0_31 Enabled on pin P0_31. 0 DISABLED Disabled. 1 ADC0_10 ADC0_10 pin enable. [10:10] ENUM ENABLED_ON_PIN_P0_00 Enabled on pin P0_00. 0 DISABLED Disabled. 1 ADC0_11 ADC0_11 pin enable. [11:11] ENUM ENABLED_ON_PIN_P0_30 Enabled on pin P0_30. 0 DISABLED Disabled. 1 ADC1_0 ADC1_0 pin enable. [12:12] ENUM ENABLED_ON_PIN_P1_01 Enabled on pin P1_01. 0 DISABLED Disabled. 1 ADC1_1 ADC1_1 pin enable. [13:13] ENUM ENABLED_ON_PIN_P0_09 Enabled on pin P0_09. 0 DISABLED Disabled. 1 ADC1_2 ADC1_2 pin enable. [14:14] ENUM ENABLED_ON_PIN_P0_10 Enabled on pin P0_10. 0 DISABLED Disabled. 1 ADC1_3 ADC1_3 pin enable. [15:15] ENUM ENABLED_ON_PIN_P0_11 Enabled on pin P0_11. 0 DISABLED Disabled. 1 ADC1_4 ADC1_4 pin enable. [16:16] ENUM ENABLED_ON_PIN_P1_02 Enabled on pin P1_02. 0 DISABLED Disabled. 1 ADC1_5 ADC1_5 pin enable. [17:17] ENUM ENABLED_ON_PIN_P1_03 Enabled on pin P1_03. 0 DISABLED Disabled. 1 ADC1_6 ADC1_6 pin enable. [18:18] ENUM ENABLED_ON_PIN_P0_13 Enabled on pin P0_13. 0 DISABLED Disabled. 1 ADC1_7 ADC1_7 pin enable. [19:19] ENUM ENABLED_ON_PIN_P0_14 Enabled on pin P0_14. 0 DISABLED Disabled. 1 ADC1_8 ADC1_8 pin enable. [20:20] ENUM ENABLED_ON_PIN_P0_15 Enabled on pin P0_15. 0 DISABLED Disabled. 1 ADC1_9 ADC1_9 pin enable. [21:21] ENUM ENABLED_ON_PIN_P0_16 Enabled on pin P0_16. 0 DISABLED Disabled. 1 ADC1_10 ADC1_10 pin enable. [22:22] ENUM ENABLED_ON_PIN_P1_04 Enabled on pin P1_04. 0 DISABLED Disabled. 1 ADC1_11 ADC1_11 pin enable. [23:23] ENUM ENABLED_ON_PIN_P1_05 Enabled on pin P1_05. 0 DISABLED Disabled. 1 DAC_OUT DAC_OUT pin enable. [24:24] ENUM ENABLED_ON_PIN_P0_12 Enabled on pin P0_12. 0 DISABLED Disabled. 1 ACMP_I1 ACMP input 1 (common input) pin enable. [25:25] ENUM ENABLED_ON_PIN_P0_27 Enabled on pin P0_27. 0 DISABLED Disabled. 1 ACMP_I2 ACMP input 2 (common input) pin enable. [26:26] ENUM ENABLED_ON_PIN_P1_06 Enabled on pin P1_06. 0 DISABLED Disabled. 1 ACMP0_I3 Analog comparator 0 input 3 pin enable. [27:27] ENUM ENABLED_ON_PIN_P0_26 Enabled on pin P0_26. 0 DISABLED Disabled. 1 ACMP0_I4 Analog comparator 0 input 4 pin enable. [28:28] ENUM ENABLED_ON_PIN_P0_25 Enabled on pin P0_25. 0 DISABLED Disabled. 1 ACMP1_I3 Analog comparator 1 input 3 pin enable. [29:29] ENUM ENABLED_ON_PIN_P0_28 Enabled on pin P0_28. 0 DISABLED Disabled. 1 ACMP1_I4 Analog comparator 1 input 4 pin enable. [30:30] ENUM ENABLED_ON_PIN_P1_10 Enabled on pin P1_10. 0 DISABLED Disabled. 1 ACMP2_I3 Analog comparator 2 input 3 pin enable. [31:31] ENUM ENABLED_ON_PIN_P0_29 Enabled on pin P0_29. 0 DISABLED Disabled. 1 PINENABLE1 Pin enable register 0. Enables fixed-pin functions 0x1C4 read-write 0 0x00000000 ACMP2_I4 Analog comparator 2 input 4 pin enable. [0:0] ENUM ENABLED_ON_PIN_P1_09 Enabled on pin P1_09. 0 DISABLED Disabled. 1 ACMP3_I3 Analog comparator 3 input 3 pin enable. [1:1] ENUM ENABLED_ON_PIN_P1_08 Enabled on pin P1_08. 0 DISABLED Disabled. 1 ACMP3_I4 Analog comparator 3 input 4 pin enable. [2:2] ENUM ENABLED_ON_PIN_P1_07 Enabled on pin P1_07. 0 DISABLED Disabled. 1 I2C0_SDA I2C0_SDA pin enable. [3:3] ENUM ENABLED_ON_PIN_P0_23 Enabled on pin P0_23. 0 DISABLED Disabled. 1 I2C0_SCL I2C0_SCL pin enable. [4:4] ENUM ENABLED_ON_PIN_P0_22 Enabled on pin P0_22. 0 DISABLED Disabled. 1 SCT0_OUT3 SCT0_OUT3 pin enable. [5:5] ENUM ENABLED_ON_PIN_P0_00 Enabled on pin P0_00. 0 DISABLED Disabled. 1 SCT0_OUT4 SCT0_OUT4 pin enable. [6:6] ENUM ENABLED_ON_PIN_P0_01 Enabled on pin P0_01. 0 DISABLED Disabled. 1 SCT0_OUT5 SCT0_OUT5 pin enable. [7:7] ENUM ENABLED_ON_PIN_P0_18 Enabled on pin P0_18. 0 DISABLED Disabled. 1 SCT0_OUT6 SCT0_OUT6 pin enable. [8:8] ENUM ENABLED_ON_PIN_P0_24 Enabled on pin P0_24. 0 DISABLED Disabled. 1 SCT0_OUT7 SCT0_OUT7 pin enable. [9:9] ENUM ENABLED_ON_PIN_P1_14 Enabled on pin P1_14. 0 DISABLED Disabled. 1 SCT1_OUT3 SCT1_OUT3 pin enable. [10:10] ENUM ENABLED_ON_PIN_P0_02 Enabled on pin P0_02. 0 DISABLED Disabled. 1 SCT1_OUT4 SCT1_OUT4 pin enable. [11:11] ENUM ENABLED_ON_PIN_P0_03 Enabled on pin P0_03. 0 DISABLED Disabled. 1 SCT1_OUT5 SCT1_OUT5 pin enable. [12:12] ENUM ENABLED_ON_PIN_P0_14 Enabled on pin P0_14. 0 DISABLED Disabled. 1 SCT1_OUT6 SCT1_OUT6 pin enable. [13:13] ENUM ENABLED_ON_PIN_P0_20 Enabled on pin P0_20. 0 DISABLED Disabled. 1 SCT1_OUT7 SCT1_OUT7 pin enable. [14:14] ENUM ENABLED_ON_PIN_P1_17 Enabled on pin P1_17. 0 DISABLED Disabled. 1 SCT2_OUT3 SCT2_OUT3 pin enable. [15:15] ENUM ENABLED_ON_PIN_P0_06 Enabled on pin P0_06. 0 DISABLED Disabled. 1 SCT2_OUT4 SCT2_OUT4 pin enable. [16:16] ENUM ENABLED_ON_PIN_P0_29 Enabled on pin P0_29. 0 DISABLED Disabled. 1 SCT2_OUT5 SCT2_OUT5 pin enable. [17:17] ENUM ENABLED_ON_PIN_P1_20 Enabled on pin P1_20. 0 DISABLED Disabled. 1 SCT3_OUT3 SCT3_OUT3 pin enable. [18:18] ENUM ENABLED_ON_PIN_P0_26 Enabled on pin P0_26. 0 DISABLED Disabled. 1 SCT3_OUT4 SCT3_OUT4 pin enable. [19:19] ENUM ENABLED_ON_PIN_P1_08 Enabled on pin P1_08. 0 DISABLED Disabled. 1 SCT3_OUT5 SCT3_OUT5 pin enable. [20:20] ENUM ENABLED_ON_PIN_P1_24 Enabled on pin P1_24. 0 DISABLED Disabled. 1 RESETN RESETN pin enable. [21:21] ENUM ENABLED_ON_PIN_P0_21 Enabled on pin P0_21. 0 DISABLED Disabled. 1 SWCLK_TCK SWCLK_TCK pin enable. [22:22] ENUM ENABLED_ON_PIN_P0_19 Enabled on pin P0_19. 0 DISABLED Disabled. 1 SWDIO SWDIO pin enable. [23:23] ENUM ENABLED_ON_PIN_P0_20 Enabled on pin P0_20. 0 DISABLED Disabled. 1 RESERVED Reserved. [24:24] RESERVED Reserved. [25:25] RESERVED Reserved. [26:26] RESERVED Reserved. [27:27] RESERVED Reserved. [28:28] RESERVED Reserved. [29:29] RESERVED Reserved. [30:30] RESERVED Reserved. [31:31] PMU Power Management Unit (PMU) PMU 0x4003C000 0x0 0xFFF registers PCON Power control register 0x000 read-write 0x0 0xFFFFFFFF NODPD A 1 in this bit prevents entry to Deep power-down mode. This bit is cleared by power-on reset. [3:3] RESERVED Reserved. Do not write ones to this bit. [7:4] SLEEPFLAG Sleep mode flag [8:8] ENUM READ_NO_POWER_DOWN Read: No power-down mode entered. The part is in Active mode. Write: No effect. 0 SLEEP_DEEP_SLEEP Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0. 1 RESERVED Reserved. Do not write ones to this bit. [10:9] DPDFLAG Deep power-down flag [11:11] ENUM READ_DEEP_POWER_DOW Read: Deep power-down mode not entered. Write: No effect. 0 READ_DEEP_POWER_DOW Read: Deep power-down mode entered. Write: Clear the Deep power-down flag. 1 RESERVED Reserved. Do not write ones to this bit. [31:12] 4 0x4 0-3 GPREG%s General purpose register 0 0x004 read-write 0x0 0xFFFFFFFF GPDATA Data retained during Deep power-down mode. [31:0] DPDCTRL Deep power-down control register 0x014 read-write 0x0 0xFFFFFFFF WAKEUPHYS WAKEUP pin hysteresis enable [0:0] ENUM DISABLED Disabled. Hysteresis for WAKEUP pin disabled. 0 ENABLED Enabled. Hysteresis for WAKEUP pin enabled. 1 WAKEPAD_DISABLE WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be used for other purposes. Never set this bit if you intend to use a pin to wake up the part from Deep power-down mode. You can only disable the wake-up pin if the self wake-up timer is enabled and configured. Setting this bit is not necessary if Deep power-down mode is not used. [1:1] ENUM ENABLED Enabled. The wake-up function is enabled on pin PIO0_4. 0 DISABLED Disabled. Setting this bit disables the wake-up function on pin PIO0_4. 1 LPOSCEN Enable the low-power oscillator for use with the 10 kHz self wake-up timer clock. You must set this bit if the CLKSEL bit in the self wake-up timer CTRL bit is set. Do not enable the low-power oscillator if the self wake-up timer is clocked by the divided IRC. [2:2] ENUM DISABLED Disabled. 0 ENABLED Enabled. 1 LPOSCDPDEN Enable the low-power oscillator in Deep power-down mode. Setting this bit causes the low-power oscillator to remain running during Deep power-down mode provided that bit 2 in this register is set as well. You must set this bit for the self wake-up timer to be able to wake up the part from Deep power-down mode. Do not set this bit unless you use the self wake-up timer to wake up from Deep power-down mode. [3:3] ENUM DISABLED Disabled. 0 ENABLED Enabled. 1 RESERVED Data retained during Deep power-down mode. [31:4] USART0 USART0 USART0 0x40040000 0x0 0xFFF registers UART0 21 CFG USART Configuration register. Basic USART configuration settings that typically are not changed during operation. 0x000 read-write 0 0xFFFFFFFF ENABLE USART Enable. [0:0] ENUM DISABLED Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if enabled in the INTENSET register) or a DMA transfer request because the transmitter has been reset and is therefore available. 0 ENABLED Enabled. The USART is enabled for operation. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [1:1] DATALEN Selects the data size for the USART. [3:2] ENUM 7_BIT_DATA_LENGTH 7 bit Data length. 0x0 8_BIT_DATA_LENGTH 8 bit Data length. 0x1 9_BIT_DATA_LENGTH 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. 0x2 RESERVED Reserved. 0x3 PARITYSEL Selects what type of parity is used by the USART. [5:4] ENUM NO_PARITY No parity. 0x0 RESERVED Reserved. 0x1 EVEN_PARITY Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. 0x2 ODD_PARITY Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. 0x3 STOPLEN Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. [6:6] ENUM 1_STOP_BIT 1 stop bit. 0 2_STOP_BITS 2 stop bits. This setting should only be used for asynchronous communication. 1 RESERVED Reserved. Only write 0 to this bit. [7:7] MODE32K Selects standard or 32 kHz clocking mode. [7:7] ENUM UART_USES_STANDARD_C UART uses standard clocking. 0 UART_USES_THE_32_KHZ UART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [8:8] CTSEN CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. See Section 24.7.4 for more information. [9:9] ENUM NO_FLOW_CONTROL No flow control. The transmitter does not receive any automatic flow control signal. 0 FLOW_CONTROL_ENABLED Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [10:10] SYNCEN Selects synchronous or asynchronous operation. [11:11] ENUM ASYNCHRONOUS_MODE_IS Asynchronous mode is selected. 0 SYNCHRONOUS_MODE_IS Synchronous mode is selected. 1 CLKPOL Selects the clock polarity and sampling edge of received data in synchronous mode. [12:12] ENUM FALLING_EDGE Falling edge. Un_RXD is sampled on the falling edge of SCLK. 0 RISING_EDGE Rising edge. Un_RXD is sampled on the rising edge of SCLK. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [13:13] SYNCMST Synchronous mode Master select. [14:14] ENUM SLAVE Slave. When synchronous mode is enabled, the USART is a slave. 0 MASTER Master. When synchronous mode is enabled, the USART is a master. 1 LOOP Selects data loopback mode. [15:15] ENUM NORMAL_OPERATION Normal operation. 0 LOOPBACK_MODE Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [17:16] OETA Output Enable Turnaround time enable for RS-485 operation. [18:18] ENUM DISABLED Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. 0 ENABLED Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. 1 AUTOADDR Automatic Address matching enable. [19:19] ENUM DISABLED Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). 0 ENABLED Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. 1 OESEL Output Enable Select. [20:20] ENUM STANDARD Standard. The RTS signal is used as the standard flow control function. 0 RS_485 RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. 1 OEPOL Output Enable Polarity. [21:21] ENUM LOW Low. If selected by OESEL, the output enable is active low. 0 HIGH High. If selected by OESEL, the output enable is active high. 1 RXPOL Receive data polarity. [22:22] ENUM STANDARD Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. 0 INVERTED Inverted. The RX signal is inverted before being used by the UART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. 1 TXPOL Transmit data polarity. [23:23] ENUM STANDARD Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. 0 INVERTED Inverted. The TX signal is inverted by the UART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:24] CTL USART Control register. USART control settings that are more likely to change during operation. 0x004 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [0:0] TXBRKEN Break Enable. [1:1] ENUM NORMAL_OPERATION Normal operation. 0 CONTINUOUS_BREAK_IS Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. 1 ADDRDET Enable address detect mode. [2:2] ENUM DISABLED Disabled. The USART presents all incoming data. 0 ENABLED Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [5:3] TXDIS Transmit Disable. [6:6] ENUM NOT_DISABLED Not disabled. USART transmitter is not disabled. 0 DISABLED Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] CC Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. [8:8] ENUM CLOCK_ON_CHARACTER Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. 0 CONTINUOUS_CLOCK Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). 1 CLRCCONRX Clear Continuous Clock. [9:9] ENUM NO_AFFECT_ON_THE_CC No affect on the CC bit. 0 AUTO_CLEAR Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [15:10] AUTOBAUD Autobaud enable. [16:16] ENUM DISABLED Disabled. UART is in normal operating mode. 0 ENABLED Enabled. UART is in autobaud mode. This bit should only be set when the UART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:17] STAT USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. 0x008 read-write 0x000E 0xFFFFFFFF RXRDY Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers. [0:0] RXIDLE Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. [1:1] TXRDY Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register. [2:2] TXIDLE Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. [3:3] CTS This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. [4:4] DELTACTS This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. [5:5] TXDISSTAT Transmitter Disabled Status flag. When 1, this bit indicates that the UART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] OVERRUNINT Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost. [8:8] RESERVED Reserved. Read value is undefined, only zero should be written. [9:9] RXBRK Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. [10:10] DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. Cleared by software. [11:11] START This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software. [12:12] FRAMERRINT Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. [13:13] PARITYERRINT Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.. [14:14] RXNOISEINT Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. [15:15] ABERR Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out. [16:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:17] INTENSET Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0x00C read-write 0 0xFFFFFFFF RXRDYEN When 1, enables an interrupt when there is a received character available to be read from the RXDAT register. [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [1:1] TXRDYEN When 1, enables an interrupt when the TXDAT register is available to take another character to transmit. [2:2] TXIDLEEN When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). [3:3] RESERVED Reserved. Read value is undefined, only zero should be written. [4:4] DELTACTSEN When 1, enables an interrupt when there is a change in the state of the CTS input. [5:5] TXDISEN When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] OVERRUNEN When 1, enables an interrupt when an overrun error occurred. [8:8] RESERVED Reserved. Read value is undefined, only zero should be written. [10:9] DELTARXBRKEN When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). [11:11] STARTEN When 1, enables an interrupt when a received start bit has been detected. [12:12] FRAMERREN When 1, enables an interrupt when a framing error has been detected. [13:13] PARITYERREN When 1, enables an interrupt when a parity error has been detected. [14:14] RXNOISEEN When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 322. [15:15] ABERREN When 1, enables an interrupt when an auto baud error occurs. [16:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:17] INTENCLR Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. 0x010 write-only 0 0x00000000 RXRDYCLR Writing 1 clears the corresponding bit in the INTENSET register. [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [1:1] TXRDYCLR Writing 1 clears the corresponding bit in the INTENSET register. [2:2] TXIDLECLR Writing 1 clears the corresponding bit in the INTENSET register. [3:3] RESERVED Reserved. Read value is undefined, only zero should be written. [4:4] DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET register. [5:5] TXDISCLR Writing 1 clears the corresponding bit in the INTENSET register. [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] OVERRUNCLR Writing 1 clears the corresponding bit in the INTENSET register. [8:8] RESERVED Reserved. Read value is undefined, only zero should be written. [10:9] DELTARXBRKCLR Writing 1 clears the corresponding bit in the INTENSET register. [11:11] STARTCLR Writing 1 clears the corresponding bit in the INTENSET register. [12:12] FRAMERRCLR Writing 1 clears the corresponding bit in the INTENSET register. [13:13] PARITYERRCLR Writing 1 clears the corresponding bit in the INTENSET register. [14:14] RXNOISECLR Writing 1 clears the corresponding bit in the INTENSET register. [15:15] ABERRCLR Writing 1 clears the corresponding bit in the INTENSET register. [16:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:17] RXDAT Receiver Data register. Contains the last character received. 0x014 read-only 0 0x00000000 modify DATA The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings. [8:0] RESERVED Reserved, the value read from a reserved bit is not defined. [31:9] RXDATSTAT Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together. 0x018 read-only 0 0x00000000 modify RXDATA The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings. [8:0] RESERVED Reserved, the value read from a reserved bit is not defined. [12:9] FRAMERR Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. [13:13] PARITYERR Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character. [14:14] RXNOISE Received Noise flag. See description of the RxNoiseInt bit in Table 322. [15:15] RESERVED Reserved, the value read from a reserved bit is not defined. [31:16] TXDAT Transmit Data register. Data to be transmitted is written here. 0x01C read-write 0 0xFFFFFFFF TXDATA Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0. [8:0] RESERVED Reserved. Only zero should be written. [31:9] BRG Baud Rate Generator register. 16-bit integer baud rate divisor value. 0x020 read-write 0 0xFFFFFFFF BRGVAL This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function. [15:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] INTSTAT Interrupt status register. Reflects interrupts that are currently enabled. 0x024 read-only 0x0005 0xFFFFFFFF RXRDY Receiver Ready flag. [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [1:1] TXRDY Transmitter Ready flag. [2:2] TXIDLE Transmitter Idle status. [3:3] RESERVED Reserved. Read value is undefined, only zero should be written. [4:4] DELTACTS This bit is set when a change in the state of the CTS input is detected. [5:5] TXDISINT Transmitter Disabled Interrupt flag. [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] OVERRUNINT Overrun Error interrupt flag. [8:8] RESERVED Reserved. Read value is undefined, only zero should be written. [10:9] DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. [11:11] START This bit is set when a start is detected on the receiver input. [12:12] FRAMERRINT Framing Error interrupt flag. [13:13] PARITYERRINT Parity Error interrupt flag. [14:14] RXNOISEINT Received Noise interrupt flag. [15:15] ABERRINT Auto baud Error Interrupt flag. [16:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:17] OSR Oversample selection register for asynchronous communication. 0x028 read-write 0xF 0xFFFFFFFF OSRVAL Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit. [3:0] RESERVED Reserved, the value read from a reserved bit is not defined. [31:4] ADDR Address register for automatic address matching. 0x02C read-write 0 0xFFFFFFFF ADDRESS 8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). [7:0] RESERVED Reserved, the value read from a reserved bit is not defined. [31:8] USART1 USART1 0x40044000 0 0xFFF registers UART1 22 SPI0 SPI0 SPI0 0x40048000 0x0 0xFFF registers SPI0 25 CFG SPI Configuration register 0x000 read-write 0 0xFFFFFFFF ENABLE SPI enable. [0:0] ENUM DISABLED Disabled. The SPI is disabled and the internal state machine and counters are reset. 0 ENABLED Enabled. The SPI is enabled for operation. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [1:1] MASTER Master mode select. [2:2] ENUM SLAVE_MODE Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. 0 MASTER_MODE Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. 1 LSBF LSB First mode enable. [3:3] ENUM STANDARD Standard. Data is transmitted and received in standard MSB first order. 0 REVERSE Reverse. Data is transmitted and received in reverse order (LSB first). 1 CPHA Clock Phase select. [4:4] ENUM CHANGE Change. The SPI captures serial data on the first clock transition of the frame (when the clock changes away from the rest state). Data is changed on the following edge. 0 CAPTURE Capture. The SPI changes serial data on the first clock transition of the frame (when the clock changes away from the rest state). Data is captured on the following edge. 1 CPOL Clock Polarity select. [5:5] ENUM LOW Low. The rest state of the clock (between frames) is low. 0 HIGH High. The rest state of the clock (between frames) is high. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [6:6] LOOP Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. [7:7] ENUM DISABLED Disabled. 0 ENABLED Enabled. 1 SPOL0 SSEL0 Polarity select. [8:8] ENUM LOW Low. The SSEL0 pin is active low. The value in the SSEL0 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL0 is not inverted relative to the pins. 0 HIGH High. The SSEL0 pin is active high. The value in the SSEL0 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL0 is inverted relative to the pins. 1 SPOL1 SSEL1 Polarity select. [9:9] ENUM LOW Low. The SSEL1 pin is active low. The value in the SSEL1 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL1 is not inverted relative to the pins. 0 HIGH High. The SSEL1 pin is active high. The value in the SSEL1 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL1 is inverted relative to the pins. 1 SPOL2 SSEL2 Polarity select. [10:10] ENUM LOW Low. The SSEL2 pin is active low. The value in the SSEL2 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL2 is not inverted relative to the pins. 0 HIGH High. The SSEL2 pin is active high. The value in the SSEL2 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL2 is inverted relative to the pins. 1 SPOL3 SSEL3 Polarity select. [11:11] ENUM LOW Low. The SSEL3 pin is active low. The value in the SSEL3 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL3 is not inverted relative to the pins. 0 HIGH High. The SSEL3 pin is active high. The value in the SSEL3 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL3 is inverted relative to the pins. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:12] DLY SPI Delay register 0x004 read-write 0 0xFFFFFFFF PRE_DELAY Controls the amount of time between SSEL assertion and the beginning of a data frame. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted. [3:0] POST_DELAY Controls the amount of time between the end of a data frame and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted. [7:4] FRAME_DELAY Controls the minimum amount of time between adjacent data frames. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted. [11:8] TRANSFER_DELAY Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. ... 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times. [15:12] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] STAT SPI Status. Some status flags can be cleared by writing a 1 to that bit position 0x008 read-write 0x0102 0xFFFFFFFF RXRDY Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register. [0:0] TXRDY Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register. [1:1] RXOV Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set. [2:2] TXUR Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be considered undefined if TXUR is set. [3:3] SSA Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software. [4:4] SSD Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software. [5:5] STALLED Stalled status flag. This indicates whether the SPI is currently in a stall condition. [6:6] ENDTRANSFER End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes Idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FrameDelay and TransferDelay to be inserted. [7:7] IDLE Idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data. [8:8] RESERVED Reserved. Read value is undefined, only zero should be written. [31:9] INTENSET SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0x00C read-write 0 0xFFFFFFFF RXRDYEN Determines whether an interrupt occurs when receiver data is available. [0:0] ENUM NO_INTERRUPT_WILL_BE No interrupt will be generated when receiver data is available. 0 AN_INTERRUPT_WILL_BE An interrupt will be generated when receiver data is available in the RXDAT register. 1 TXRDYEN Determines whether an interrupt occurs when the transmitter holding register is available. [1:1] ENUM NO_INTERRUPT_WILL_BE No interrupt will be generated when the transmitter holding register is available. 0 AN_INTERRUPT_WILL_BE An interrupt will be generated when data may be written to TXDAT. 1 RXOVEN Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur. [2:2] ENUM NO_INTERRUPT_WILL_BE No interrupt will be generated when a receiver overrun occurs. 0 AN_INTERRUPT_WILL_BE An interrupt will be generated if a receiver overrun occurs. 1 TXUREN Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available. [3:3] ENUM NO_INTERRUPT_WILL_BE No interrupt will be generated when the transmitter underruns. 0 AN_INTERRUPT_WILL_BE An interrupt will be generated if the transmitter underruns. 1 SSAEN Determines whether an interrupt occurs when the Slave Select is asserted. [4:4] ENUM NO_INTERRUPT_WILL_BE No interrupt will be generated when any Slave Select transitions from deasserted to asserted. 0 AN_INTERRUPT_WILL_BE An interrupt will be generated when any Slave Select transitions from deasserted to asserted. 1 SSDEN Determines whether an interrupt occurs when the Slave Select is deasserted. [5:5] ENUM NO_INTERRUPT_WILL_BE No interrupt will be generated when all asserted Slave Selects transition to deasserted. 0 AN_INTERRUPT_WILL_BE An interrupt will be generated when all asserted Slave Selects transition to deasserted. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:6] INTENCLR SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. 0x010 write-only 0 0x00000000 RXRDYEN Writing 1 clears the corresponding bits in the INTENSET register. [0:0] TXRDYEN Writing 1 clears the corresponding bits in the INTENSET register. [1:1] RXOVEN Writing 1 clears the corresponding bits in the INTENSET register. [2:2] TXUREN Writing 1 clears the corresponding bits in the INTENSET register. [3:3] SSAEN Writing 1 clears the corresponding bits in the INTENSET register. [4:4] SSDEN Writing 1 clears the corresponding bits in the INTENSET register. [5:5] RESERVED Reserved. Read value is undefined, only zero should be written. [31:6] RXDAT SPI Receive Data 0x014 read-only 0 0x00000000 modify RXDAT Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the FLen setting in TXCTL / TXDATCTL. [15:0] RXSSEL0 Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. [16:16] RXSSEL1 Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. [17:17] RXSSEL2 Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. [18:18] RXSSEL3 Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. [19:19] SOT Start of Transfer flag. This flag will be 1 if this is the first frame after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the frame length is greater than 16 bit. [20:20] RESERVED Reserved, the value read from a reserved bit is not defined. [31:21] TXDATCTL SPI Transmit Data with Control 0x018 read-write 0 0xFFFFFFFF TXDAT Transmit Data. This field provides from 1 to 16 bits of data to be transmitted. [15:0] TXSSEL0 Transmit Slave Select . This field controls what is output for SSEL0 in master mode. The active state of the SSEL0 function is configured by bits in the CFG register. [16:16] ENUM SSEL0_ASSERTED SSEL0 asserted. 0 SSEL0_NOT_ASSERTED SSEL0 not asserted. 1 TXSSEL1 Transmit Slave Select . This field controls what is output for SSEL1 in master mode. The active state of the SSEL1 function is configured by bits in the CFG register. [17:17] ENUM SSEL1_ASSERTED SSEL1 asserted. 0 SSEL1_NOT_ASSERTED SSEL1 not asserted. 1 TXSSEL2 Transmit Slave Select . This field controls what is output for SSEL2 in master mode. The active state of the SSEL2 function is configured by bits in the CFG register. [18:18] ENUM SSEL2_ASSERTED SSEL2 asserted. 0 SSEL2_NOT_ASSERTED SSEL2 not asserted. 1 TXSSEL3 Transmit Slave Select . This field controls what is output for SSEL3 in master mode. The active state of the SSEL3 function is configured by bits in the CFG register. [19:19] ENUM SSEL3_ASSERTED SSEL3 asserted. 0 SSEL3_NOT_ASSERTED SSEL3 not asserted. 1 EOT End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register. [20:20] ENUM SSEL_NOT_DEASSERTED SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. 0 SSEL_DEASSERTED SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. 1 EOF End of Frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. [21:21] ENUM DATA_NOT_EOF Data not EOF. This piece of data transmitted is not treated as the end of a frame. 0 DATA_EOF Data EOF. This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted. 1 RXIGNORE Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver to simplify the transmit process and can be used with the DMA. [22:22] ENUM READ_RECEIVED_DATA Read received data. Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received. 0 IGNORE_RECEIVED_DATA Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [23:23] FLEN Frame Length. Specifies the frame length from 1 to 16 bits. Note that frame lengths greater than 16 bits are supported by implementing multiple sequential frames. Note that if a 1-bit frame is selected, the master function will always insert a delay with a length of one SCK time following the single clock seen on the SCK pin. 0x0 = Data frame is 1 bit in length. 0x1 = Data frame is 2 bits in length. 0x2 = Data frame is 3 bits in length. ... 0xF = Data frame is 16 bits in length. [27:24] RESERVED Reserved. Read value is undefined, only zero should be written. [31:28] TXDAT SPI Transmit Data with Control 0x01C read-write 0 0xFFFFFFFF DATA Transmit Data. This field provides from 4 to 16 bits of data to be transmitted. [15:0] RESERVED Reserved. Only zero should be written. [31:16] TXCTL SPI Transmit Control 0x020 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [15:0] TXSSEL0 Transmit Slave Select 0. [16:16] TXSSEL1 Transmit Slave Select 1. [17:17] TXSSEL2 Transmit Slave Select 2. [18:18] TXSSEL3 Transmit Slave Select 3. [19:19] EOT End of Transfer. [20:20] EOF End of Frame. [21:21] RXIGNORE Receive Ignore. [22:22] RESERVED Reserved. Read value is undefined, only zero should be written. [23:23] FLEN Frame Length. [27:24] RESERVED Reserved. Read value is undefined, only zero should be written. [31:28] DIV SPI clock Divider 0x024 read-write 0 0xFFFFFFFF DIVVAL Rate divider value. Specifies how the PCLK for the SPI is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in PCLK/1, the value 1 results in PCLK/2, up to the maximum possible divide value of 0xFFFF, which results in PCLK/65536. [15:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] INTSTAT SPI Interrupt Status 0x028 read-only 0x02 0xFFFFFFFF RXRDY Receiver Ready flag. [0:0] TXRDY Transmitter Ready flag. [1:1] RXOV Receiver Overrun interrupt flag. [2:2] TXUR Transmitter Underrun interrupt flag. [3:3] SSA Slave Select Assert. [4:4] SSD Slave Select Deassert. [5:5] RESERVED Reserved. Read value is undefined, only zero should be written. [31:6] SPI1 SPI1 0x4004C000 0 0xFFF registers SPI1 26 I2C0 I2C-bus interface I2C0 0x40050000 0x0 0xFFF registers I2C0 24 CFG Configuration for shared functions. 0x00 read-write 0 0xFFFFFFFF MSTEN Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. [0:0] ENUM DISABLED Disabled. The I2C Master function is disabled. 0 ENABLED Enabled. The I2C Master function is enabled. 1 SLVEN Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. [1:1] ENUM DISABLED Disabled. The I2C slave function is disabled. 0 ENABLED Enabled. The I2C slave function is enabled. 1 MONEN Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. [2:2] ENUM DISABLED Disabled. The I2C monitor function is disabled. 0 ENABLED Enabled. The I2C monitor function is enabled. 1 TIMEOUTEN I2C bus Time-out Enable. When disabled, the time-out function is internally reset. [3:3] ENUM DISABLED Disabled. Time-out function is disabled. 0 ENABLED Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system. 1 MONCLKSTR Monitor function Clock Stretching. [4:4] ENUM DISABLED Disabled. The monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. 0 ENABLED Enabled. The monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the monitor function. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:5] STAT Status register for Master, Slave, and Monitor functions. 0x04 read-write 0x000801 0xFFFFFFFF MSTPENDING Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt. [0:0] ENUM IN_PROGRESS In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. 0 PENDING Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit. 1 MSTSTATE Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. [3:1] ENUM IDLE Idle. The Master function is available to be used for a new transaction. 0x0 RECEIVE_READY Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. 0x1 TRANSMIT_READY Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. 0x2 NACK_ADDRESS NACK Address. Slave NACKed address. 0x3 NACK_DATA NACK Data. Slave NACKed transmitted data. 0x4 MSTARBLOSS Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. [4:4] ENUM NO_LOSS No loss. No Arbitration Loss has occurred. 0 ARBITRATION_LOSS Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [5:5] MSTSTSTPERR Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. [6:6] ENUM NO_STARTSTOP_ERROR No Start/Stop Error has occurred. 0 STARTSTOP_ERROR_HAS Start/stop error has occurred. The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] SLVPENDING Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the MSTCTL register. [8:8] ENUM IN_PROGRESS In progress. The Slave function does not currently need service. 0 PENDING Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. 1 SLVSTATE Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. [10:9] ENUM SLAVE_ADDRESS Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. 0x0 SLAVE_RECEIVE Slave receive. Received data is available (Slave Receiver mode). 0x1 SLAVE_TRANSMIT Slave transmit. Data can be transmitted (Slave Transmitter mode). 0x2 RESERVED Reserved. 0x3 SLVNOTSTR Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. [11:11] ENUM STRETCHING Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. 0 NOT_STRETCHING Not stretching. The slave function is not currently stretching the I2C bus clock. Deep-sleep or Power-down mode could be entered at this time. 1 SLVIDX Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. [13:12] ENUM SLAVE_ADDRESS_0_WAS Slave address 0 was matched. 0x0 SLAVE_ADDRESS_1_WAS Slave address 1 was matched. 0x1 SLAVE_ADDRESS_2_WAS Slave address 2 was matched. 0x2 SLAVE_ADDRESS_3_WAS Slave address 3 was matched. 0x3 SLVSEL Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, or when there is a Stop detected on the bus. SLVSEL is not cleared if software Nacks data. [14:14] ENUM NOT_SELECTED Not selected. The Slave function is not currently selected. 0 SELECTED Selected. The Slave function is currently selected. 1 SLVDESEL Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. [15:15] ENUM NOT_DESELECTED Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. 0 DESELECTED Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. 1 MONRDY Monitor Ready. This flag is cleared when the MONRXDAT register is read. [16:16] ENUM NO_DATA No data. The Monitor function does not currently have data available. 0 DATA_WAITING Data waiting. The Monitor function has data waiting to be read. 1 MONOV Monitor Overflow flag. [17:17] ENUM NO_OVERRUN No overrun. Monitor data has not overrun. 0 OVERRUN Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. 1 MONACTIVE Monitor Active flag. This flag indicates when the Monitor function considers the I2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. [18:18] ENUM INACTIVE Inactive. The Monitor function considers the I2C bus to be inactive. 0 ACTIVE Active. The Monitor function considers the I2C bus to be active. 1 MONIDLE Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register . The flag can be cleared by writing a 1 to this bit. [19:19] ENUM NOT_IDLE Not idle. The I2C bus is not idle, or this flag has been cleared by software. 0 IDLE Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [23:20] EVENTTIMEOUT Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. [24:24] ENUM NO_TIME_OUT No time-out. I2C bus events have not caused a time-out. 0 EVENT_TIME_OUT Event time-out. The time between I2C bus events has been longer than the time specified by the I2C TIMEOUT register. 1 SCLTIMEOUT SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. [25:25] ENUM NO_TIME_OUT No time-out. SCL low time has not caused a time-out. 0 TIME_OUT Time-out. SCL low time has caused a time-out. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:26] INTENSET Interrupt Enable Set and read register. 0x08 read-write 0 0xFFFFFFFF MSTPENDINGEN Master Pending interrupt Enable. [0:0] ENUM THE_MSTPENDING_INTER The MstPending interrupt is disabled. 0 THE_MSTPENDING_INTER The MstPending interrupt is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [3:1] MSTARBLOSSEN Master Arbitration Loss interrupt Enable. [4:4] ENUM THE_MSTARBLOSS_INTER The MstArbLoss interrupt is disabled. 0 THE_MSTARBLOSS_INTER The MstArbLoss interrupt is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [5:5] MSTSTSTPERREN Master Start/Stop Error interrupt Enable. [6:6] ENUM THE_MSTSTSTPERR_INTE The MstStStpErr interrupt is disabled. 0 THE_MSTSTSTPERR_INTE The MstStStpErr interrupt is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] SLVPENDINGEN Slave Pending interrupt Enable. [8:8] ENUM THE_SLVPENDING_INTER The SlvPending interrupt is disabled. 0 THE_SLVPENDING_INTER The SlvPending interrupt is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [10:9] SLVNOTSTREN Slave Not Stretching interrupt Enable. [11:11] ENUM THE_SLVNOTSTR_INTERR The SlvNotStr interrupt is disabled. 0 THE_SLVNOTSTR_INTERR The SlvNotStr interrupt is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [14:12] SLVDESELEN Slave Deselect interrupt Enable. [15:15] ENUM THE_SLVDESEL_INTERRU The SlvDeSel interrupt is disabled. 0 THE_SLVDESEL_INTERRU The SlvDeSel interrupt is enabled. 1 MONRDYEN Monitor data Ready interrupt Enable. [16:16] ENUM THE_MONRDY_INTERRUPT The MonRdy interrupt is disabled. 0 THE_MONRDY_INTERRUPT The MonRdy interrupt is enabled. 1 MONOVEN Monitor Overrun interrupt Enable. [17:17] ENUM THE_MONOV_INTERRUPT The MonOv interrupt is disabled. 0 THE_MONOV_INTERRUPT The MonOv interrupt is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [18:18] MONIDLEEN Monitor Idle interrupt Enable. [19:19] ENUM THE_MONIDLE_INTERRUP The MonIdle interrupt is disabled. 0 THE_MONIDLE_INTERRUP The MonIdle interrupt is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [23:20] EVENTTIMEOUTEN Event time-out interrupt Enable. [24:24] ENUM THE_EVENT_TIME_OUT_I The Event time-out interrupt is disabled. 0 THE_EVENT_TIME_OUT_I The Event time-out interrupt is enabled. 1 SCLTIMEOUTEN SCL time-out interrupt Enable. [25:25] ENUM THE_SCL_TIME_OUT_INT The SCL time-out interrupt is disabled. 0 THE_SCL_TIME_OUT_INT The SCL time-out interrupt is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:26] INTENCLR Interrupt Enable Clear register. 0x0C write-only 0 0x00000000 MSTPENDINGCLR Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented. [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [3:1] MSTARBLOSSCLR Master Arbitration Loss interrupt clear. [4:4] RESERVED Reserved. Read value is undefined, only zero should be written. [5:5] MSTSTSTPERRCLR Master Start/Stop Error interrupt clear. [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] SLVPENDINGCLR Slave Pending interrupt clear. [8:8] RESERVED Reserved. Read value is undefined, only zero should be written. [10:9] SLVNOTSTRCLR Slave Not Stretching interrupt clear. [11:11] RESERVED Reserved. Read value is undefined, only zero should be written. [14:12] SLVDESELCLR Slave Deselect interrupt clear. [15:15] MONRDYCLR Monitor data Ready interrupt clear. [16:16] MONOVCLR Monitor Overrun interrupt clear. [17:17] RESERVED Reserved. Read value is undefined, only zero should be written. [18:18] MONIDLECLR Monitor Idle interrupt clear. [19:19] RESERVED Reserved. Read value is undefined, only zero should be written. [23:20] EVENTTIMEOUTCLR Event time-out interrupt clear. [24:24] SCLTIMEOUTCLR SCL time-out interrupt clear. [25:25] RESERVED Reserved. Read value is undefined, only zero should be written. [31:26] TIMEOUT Time-out value register. 0x10 read-write 0xFFFF 0xFFFFFFFF TOMIN Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. [3:0] TO Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. ... 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock. [15:4] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] CLKDIV Clock pre-divider for the entire I2C block. This determines what time increments are used for the MSTTIME and SLVTIME registers. 0x14 read-write 0 0xFFFFFFFF DIVVAL This field controls how the clock (PCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = PCLK is used directly by the I2C function. 0x0001 = PCLK is divided by 2 before use by the I 2C function. 0x0002 = PCLK is divided by 3 before use by the I 2C function. ... 0xFFFF = PCLK is divided by 65,536 before use by the I2C function. [15:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] INTSTAT Interrupt Status register for Master, Slave, and Monitor functions. 0x18 read-only 0 0xFFFFFFFF MSTPENDING Master Pending. [0:0] RESERVED Reserved. [3:1] MSTARBLOSS Master Arbitration Loss flag. [4:4] RESERVED Reserved. Read value is undefined, only zero should be written. [5:5] MSTSTSTPERR Master Start/Stop Error flag. [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] SLVPENDING Slave Pending. [8:8] RESERVED Reserved. Read value is undefined, only zero should be written. [10:9] SLVNOTSTR Slave Not Stretching status. [11:11] RESERVED Reserved. Read value is undefined, only zero should be written. [14:12] SLVDESEL Slave Deselected flag. [15:15] MONRDY Monitor Ready. [16:16] MONOV Monitor Overflow flag. [17:17] RESERVED Reserved. Read value is undefined, only zero should be written. [18:18] MONIDLE Monitor Idle flag. [19:19] RESERVED Reserved. Read value is undefined, only zero should be written. [23:20] EVENTTIMEOUT Event time-out Interrupt flag. [24:24] SCLTIMEOUT SCL time-out Interrupt flag. [25:25] RESERVED Reserved. Read value is undefined, only zero should be written. [31:26] MSTCTL Master control register. 0x20 read-write 0 0xFFFFFFFF MSTCONTINUE Master Continue. This bit is write-only. [0:0] ENUM NO_EFFECT No effect. 0 CONTINUE Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. 1 MSTSTART Master Start control. This bit is write-only. [1:1] ENUM NO_EFFECT No effect. 0 START Start. A Start will be generated on the I2C bus at the next allowed time. 1 MSTSTOP Master Stop control. This bit is write-only. [2:2] ENUM NO_EFFECT No effect. 0 STOP Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode). 1 MSTDMA Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. [3:3] ENUM DISABLE Disable. No DMA requests are generated for master operation. 0 ENABLE Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:4] MSTTIME Master timing configuration. 0x24 read-write 0x77 0xFFFFFFFF MSTSCLLOW Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter tLOW in the I2C bus specification. I2C bus specification parameters tBUF and t SU;STA have the same values and are also controlled by MSTSCLLOW. [2:0] ENUM 2_CLOCKS 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. 0x0 3_CLOCKS 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. 0x1 4_CLOCKS 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. 0x2 5_CLOCKS 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. 0x3 6_CLOCKS 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. 0x4 7_CLOCKS 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. 0x5 8_CLOCKS 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. 0x6 9_CLOCKS 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. 0x7 RESERVED Reserved. [3:3] MSTSCLHIGH Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. [6:4] ENUM 2_CLOCKS 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. 0x0 3_CLOCKS 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . 0x1 4_CLOCKS 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. 0x2 5_CLOCKS 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. 0x3 6_CLOCKS 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. 0x4 7_CLOCKS 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. 0x5 8_CLOCKS 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. 0x6 9_CLOCKS 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. 0x7 RESERVED Reserved. Read value is undefined, only zero should be written. [31:7] MSTDAT Combined Master receiver and transmitter data register. 0x28 read-write 0 0x00000000 DATA Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] SLVCTL Slave control register. 0x40 read-write 0 0xFFFFFFFF SLVCONTINUE Slave Continue. [0:0] ENUM NO_EFFECT No effect. 0 CONTINUE Continue. Informs the Slave function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. 1 SLVNACK Slave NACK. [1:1] ENUM NO_EFFECT No effect. 0 NACK NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). 1 RESERVED Reserved. Read value is undefined, only zero should be written. [2:2] SLVDMA Slave DMA enable. [3:3] ENUM DISABLED Disabled. No DMA requests are issued for Slave mode operation. 0 ENABLED Enabled. DMA requests are issued for I2C slave data transmission and reception. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:4] SLVDAT Combined Slave receiver and transmitter data register. 0x44 read-write 0 0x00000000 DATA Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] 4 0x4 0-3 SLVADR%s Slave address 0. 0x48 read-write 0x01 0xFFFFFFFF SADISABLE Slave Address n Disable. [0:0] ENUM ENABLED Enabled. Slave Address n is enabled and will be recognized with any changes specified by the SLVQUAL0 register. 0 IGNORED_SLAVE_ADDRES Ignored Slave Address n is ignored. 1 SLVADR Seven bit slave address that is compared to received addresses if enabled. [7:1] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] SLVQUAL0 Slave Qualification for address 0. 0x58 read-write 0 0xFFFFFFFF QUALMODE0 Reserved. Read value is undefined, only zero should be written. [0:0] ENUM THE_SLVQUAL0_FIELD_I The SLVQUAL0 field is used as a logical mask for matching address 0. 0 THE_SLVQUAL0_FIELD_I The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. 1 SLVQUAL0 Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] < = received address <= SLVQUAL0[7:1]). [7:1] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] MONRXDAT Monitor receiver data register. 0x80 read-only 0 0xFFFFFFFF MONRXDAT Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins, and adds indication of Start, Repeated Start, and data NACK. [7:0] MONSTART Monitor Received Start. [8:8] ENUM NO_DETECT No detect. The monitor function has not detected a Start event on the I2C bus. 0 START_DETECT Start detect. The monitor function has detected a Start event on the I2C bus. 1 MONRESTART Monitor Received Repeated Start. [9:9] ENUM NO_START_DETECT No start detect. The monitor function has not detected a Repeated Start event on the I2C bus. 0 REPEATED_START_DETEC Repeated start detect. The monitor function has detected a Repeated Start event on the I 2C bus. 1 MONNACK Monitor Received NACK. [10:10] ENUM ACKNOWLEDGED Acknowledged. The data currently being provided by the monitor function was acknowledged by at least one master or slave receiver. 0 NOT_ACKNOWLEDGED Not acknowledged. The data currently being provided by the monitor function was not acknowledged by any receiver. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:11] QEI Quadrature Encoder Interface (QEI) QEI 0x40058000 0x0 0xFFF registers QEI 44 CON Control register 0x000 write-only 0 0xFFFFFFFF RESP Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared. [0:0] RESPI Reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs. Autoclears when the position counter is cleared. [1:1] RESV Reset velocity. When set = 1, resets the velocity counter to all zeros and reloads the velocity timer. Autoclears when the velocity counter is cleared. [2:2] RESI Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared. [3:3] RESERVED reserved [31:4] STAT Encoder status register 0x004 read-only 0 0xFFFFFFFF DIR Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 284. [0:0] RESERVED reserved [31:1] CONF Configuration register 0x008 read-write 0x000F0000 0xFFFFFFFF DIRINV Direction invert. When = 1, complements the DIR bit. [0:0] SIGMODE Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA functions as the direction signal and PhB functions as the clock signal. [1:1] CAPMODE Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range. [2:2] INVINX Invert Index. When set, inverts the sense of the index input. [3:3] CRESPI Continuously reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs at the next position increase (recalibration). Auto-clears when the position counter is cleared. [4:4] RESERVED Reserved [15:5] INXGATE Index gating configuration: when INXGATE(19)=1, pass the index when Pha=0 and Phb=0, else block. when INXGATE(18)=1, pass the index when Pha=0 and Phb=1, else block. when INXGATE(17)=1, pass the index when Pha=1 and Phb=1, else block. when INXGATE(16)=1, pass the index when Pha=1 and Phb=0, else block. [19:16] RESERVED reserved [31:20] POS Position register 0x00C read-only 0 0xFFFFFFFF POS Current position value. [31:0] MAXPOS Maximum position register 0x010 read-write 0 0xFFFFFFFF MAXPOS Maximum position value. [31:0] CMPOS0 position compare register 0 0x014 read-write 0xFFFFFFFF 0xFFFFFFFF PCMP0 Position compare value 0. [31:0] CMPOS1 position compare register 1 0x018 read-write 0xFFFFFFFF 0xFFFFFFFF PCMP1 Position compare value 1. [31:0] CMPOS2 position compare register 2 0x01C read-write 0xFFFFFFFF 0xFFFFFFFF PCMP2 Position compare value 2. [31:0] INXCNT Index count register 0x020 read-only 0 0xFFFFFFFF ENCPOS Current encoder position value. [31:0] INXCMP0 Index compare register 0 0x024 read-write 0xFFFFFFFF 0xFFFFFFFF ICMP0 Index compare value. [31:0] LOAD Velocity timer reload register 0x028 read-write 0xFFFFFFFF 0xFFFFFFFF VELLOAD Current velocity timer pre-load value.The velocity timer counts down from this value. [31:0] TIME Velocity timer register 0x02C read-only 0xFFFFFFFF 0xFFFFFFFF VELVAL Current velocity timer value. [31:0] VEL Velocity counter register 0x030 read-only 0 0xFFFFFFFF VELPC Current velocity pulse count. [31:0] CAP Velocity capture register 0x034 read-only 0xFFFFFFFF 0xFFFFFFFF VELCAP Velocity capture value. [31:0] VELCOMP Velocity compare register 0x038 read-write 0 0xFFFFFFFF VELCMP Velocity compare value. [31:0] FILTERPHA Digital filter register on input phase A (QEI_A) 0x03C read-write 0 0xFFFFFFFF FILTA Digital filter sampling delay [31:0] FILTERPHB Digital filter register on input phase B (QEI_B) 0x040 read-write 0 0xFFFFFFFF FILTB Digital filter sampling delay [31:0] FILTERINX Digital filter register on input index (QEI_IDX) 0x044 read-write 0 0xFFFFFFFF FITLINX Digital filter sampling delay [31:0] WINDOW Index acceptance window register 0x048 read-write 0x00000000 0xFFFFFFFF WINDOW Index acceptance window width [31:0] INXCMP1 Index compare register 1 0x04C read-write 0xFFFFFFFF 0xFFFFFFFF ICMP1 Index compare value 1. [31:0] INXCMP2 Index compare register 2 0x050 read-write 0xFFFFFFFF 0xFFFFFFFF ICMP2 Index compare value 2. [31:0] IEC Interrupt enable clear register 0xFD8 write-only 0 0xFFFFFFFF INX_EN Indicates that an index pulse was detected. [0:0] TIM_EN Indicates that a velocity timer overflow occurred [1:1] VELC_EN Indicates that captured velocity is less than compare velocity. [2:2] DIR_EN Indicates that a change of direction was detected. [3:3] ERR_EN Indicates that an encoder phase error was detected. [4:4] ENCLK_EN Indicates that and encoder clock pulse was detected. [5:5] POS0_INT Indicates that the position 0 compare value is equal to the current position. [6:6] POS1_INT Indicates that the position 1compare value is equal to the current position. [7:7] POS2_INT Indicates that the position 2 compare value is equal to the current position. [8:8] REV0_INT Indicates that the index 0 compare value is equal to the current index count. [9:9] POS0REV_INT Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is set and the REV0_Int is set. [10:10] POS1REV_INT Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is set and the REV1_INT is set. [11:11] POS2REV_INT Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is set and the REV2_INT is set. [12:12] REV1_INT Indicates that the index 1 compare value is equal to the current index count. [13:13] REV2_INT Indicates that the index 2 compare value is equal to the current index count. [14:14] MAXPOS_INT Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction. [15:15] RESERVED Reserved [31:16] IES Interrupt enable set register 0xFDC write-only 0 0xFFFFFFFF INX_EN Indicates that an index pulse was detected. [0:0] TIM_EN Indicates that a velocity timer overflow occurred [1:1] VELC_EN Indicates that captured velocity is less than compare velocity. [2:2] DIR_EN Indicates that a change of direction was detected. [3:3] ERR_EN Indicates that an encoder phase error was detected. [4:4] ENCLK_EN Indicates that and encoder clock pulse was detected. [5:5] POS0_INT Indicates that the position 0 compare value is equal to the current position. [6:6] POS1_INT Indicates that the position 1 compare value is equal to the current position. [7:7] POS2_INT Indicates that the position 2 compare value is equal to the current position. [8:8] REV0_INT Indicates that the index compare value is equal to the current index count. [9:9] POS0REV_INT Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is set and the REV0_INT is set. [10:10] POS1REV_INT Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is set and the REV1_INT is set. [11:11] POS2REV_INT Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is set and the REV2_INT is set. [12:12] REV1_INT Indicates that the index 1 compare value is equal to the current index count. [13:13] REV2_INT Indicates that the index 2 compare value is equal to the current index count. [14:14] MAXPOS_INT Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction. [15:15] RESERVED Reserved [31:16] INTSTAT Interrupt status register 0xFE0 read-only 0 0xFFFFFFFF INX_INT Indicates that an index pulse was detected. [0:0] TIM_INT Indicates that a velocity timer overflow occurred [1:1] VELC_INT Indicates that captured velocity is less than compare velocity. [2:2] DIR_INT Indicates that a change of direction was detected. [3:3] ERR_INT Indicates that an encoder phase error was detected. [4:4] ENCLK_INT Indicates that and encoder clock pulse was detected. [5:5] POS0_INT Indicates that the position 0 compare value is equal to the current position. [6:6] POS1_INT Indicates that the position 1compare value is equal to the current position. [7:7] POS2_INT Indicates that the position 2 compare value is equal to the current position. [8:8] REV0_INT Indicates that the index compare value is equal to the current index count. [9:9] POS0REV_INT Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is set and the REV0_INT is set. [10:10] POS1REV_INT Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is set and the REV1_INT is set. [11:11] POS2REV_INT Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is set and the REV2_INT is set. [12:12] REV1_INT Indicates that the index 1 compare value is equal to the current index count. [13:13] REV2_INT Indicates that the index 2 compare value is equal to the current index count. [14:14] MAXPOS_INT Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction. [15:15] RESERVED Reserved [31:16] IE Interrupt enable clear register 0xFE4 write-only 0 0xFFFFFFFF INX_INT Indicates that an index pulse was detected. [0:0] TIM_INT Indicates that a velocity timer overflow occurred [1:1] VELC_INT Indicates that captured velocity is less than compare velocity. [2:2] DIR_INT Indicates that a change of direction was detected. [3:3] ERR_INT Indicates that an encoder phase error was detected. [4:4] ENCLK_INT Indicates that and encoder clock pulse was detected. [5:5] POS0_INT Indicates that the position 0 compare value is equal to the current position. [6:6] POS1_INT Indicates that the position 1compare value is equal to the current position. [7:7] POS2_INT Indicates that the position 2 compare value is equal to the current position. [8:8] REV0_INT Indicates that the index compare value is equal to the current index count. [9:9] POS0REV_INT Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is set and the REV0_INT is set. [10:10] POS1REV_INT Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is set and the REV1_INT is set. [11:11] POS2REV_INT Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is set and the REV2_INT is set. [12:12] REV1_INT Indicates that the index 1 compare value is equal to the current index count. [13:13] REV2_INT Indicates that the index 2 compare value is equal to the current index count. [14:14] MAXPOS_INT Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction. [15:15] RESERVED Reserved [31:16] CLR Interrupt status clear register 0xFE8 write-only 0 0xFFFFFFFF INX_INT Indicates that an index pulse was detected. [0:0] TIM_INT Indicates that a velocity timer overflow occurred [1:1] VELC_INT Indicates that captured velocity is less than compare velocity. [2:2] DIR_INT Indicates that a change of direction was detected. [3:3] ERR_INT Indicates that an encoder phase error was detected. [4:4] ENCLK_INT Indicates that and encoder clock pulse was detected. [5:5] POS0_INT Indicates that the position 0 compare value is equal to the current position. [6:6] POS1_INT Indicates that the position 1compare value is equal to the current position. [7:7] POS2_INT Indicates that the position 2 compare value is equal to the current position. [8:8] REV0_INT Indicates that the index compare value is equal to the current index count. [9:9] POS0REV_INT Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is set and the REV0_INT is set. [10:10] POS1REV_INT Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is set and the REV1_INT is set. [11:11] POS2REV_INT Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is set and the REV2_INT is set. [12:12] REV1_INT Indicates that the index 1 compare value is equal to the current index count. [13:13] REV2_INT Indicates that the index 2 compare value is equal to the current index count. [14:14] MAXPOS_INT Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction. [15:15] RESERVED Reserved [31:16] SET Interrupt status set register 0xFEC write-only 0 0xFFFFFFFF INX_INT Indicates that an index pulse was detected. [0:0] TIM_INT Indicates that a velocity timer overflow occurred [1:1] VELC_INT Indicates that captured velocity is less than compare velocity. [2:2] DIR_INT Indicates that a change of direction was detected. [3:3] ERR_INT Indicates that an encoder phase error was detected. [4:4] ENCLK_INT Indicates that and encoder clock pulse was detected. [5:5] POS0_INT Indicates that the position 0 compare value is equal to the current position. [6:6] POS1_INT Indicates that the position 1compare value is equal to the current position. [7:7] POS2_INT Indicates that the position 2 compare value is equal to the current position. [8:8] REV0_INT Indicates that the index compare value is equal to the current index count. [9:9] POS0REV_INT Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is set and the REV0_INT is set. [10:10] POS1REV_INT Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is set and the REV1_INT is set. [11:11] POS2REV_INT Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is set and the REV2_INT is set. [12:12] REV1_INT Indicates that the index 1 compare value is equal to the current index count. [13:13] REV2_INT Indicates that the index 2 compare value is equal to the current index count. [14:14] MAXPOS_INT Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction. [15:15] RESERVED Reserved [31:16] SYSCON System configuration (SYSCON) SYSCON 0x40074000 0x0 0xFFF registers BOD_IRQ 1 SYSMEMREMAP System memory remap 0x000 read-write 0x2 0xFFFFFFFF MAP tbd [1:0] RESERVED RESERVED [31:2] SYSTCKCAL System tick counter calibration 0x014 read-write 0x0 0xFFFFFFFF CAL System tick timer calibration value [25:0] RESERVED Reserved [31:26] NMISRC NMI Source Control 0x01C read-write 0 0xFFFFFFFF IRQNO The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1. See Table 3 for the list of interrupt sources and their IRQ numbers. [4:0] RESERVED Reserved [30:5] NMIEN Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0. [31:31] SYSRSTSTAT System reset status register 0x040 read-write 0 0xFFFFFFFF POR POR reset status [0:0] ENUM NO_POR_DETECTED No POR detected 0 POR_DETECTED_WRITIN POR detected. Writing a one clears this reset. 1 EXTRST Status of the external RESET pin. External reset status. [1:1] ENUM NO_RESET_EVENT_DETEC No reset event detected. 0 RESET_DETECTED_WRIT Reset detected. Writing a one clears this reset. 1 WDT Status of the Watchdog reset [2:2] ENUM NO_WDT_RESET_DETECTE No WDT reset detected 0 WDT_RESET_DETECTED_ WDT reset detected. Writing a one clears this reset. 1 BOD Status of the Brown-out detect reset [3:3] ENUM NO_BOD_RESET_DETECTE No BOD reset detected 0 BOD_RESET_DETECTED_ BOD reset detected. Writing a one clears this reset. 1 SYSRST Status of the software system reset [4:4] ENUM NO_SYSTEM_RESET_DETE No System reset detected 0 SYSTEM_RESET_DETECTE System reset detected. Writing a one clears this reset. 1 RESERVED Reserved [31:5] PRESETCTRL0 Peripheral reset control 0 0x044 read-write 0 0xFFFFFFFF RESERVED Reserved [6:0] FLASH_RST Flash reset control [7:7] ENUM CLEAR_FLASH_RESET_ Clear flash reset. 0 ASSERT_FLASH_RESET_ Assert flash reset. 1 FMC_RST FMC reset control FMC? Is this the flash controller? [8:8] ENUM CLEAR_FMC_RESET_ Clear FMC reset. 0 ASSERT_FMC_RESET_ Assert FMC reset. 1 EEPROM_RST EEPROM reset control [9:9] ENUM CLEAR_EEPROM_RESET_ Clear EEPROM reset. 0 ASSERT_EEPROM_RESET_ Assert EEPROM reset. 1 RESERVED Reserved [10:10] PMUX_RST Pin mux reset control [11:11] ENUM CLEAR_PIN_MUX_RESET_ Clear pin mux reset. 0 ASSERT_PIN_MUX_RESET Assert pin mux reset. 1 RESERVED Reserved [12:12] IOCON_RST IOCON reset control [13:13] ENUM CLEAR_IOCON_RESET_ Clear IOCON reset. 0 ASSERT_IOCON_RESET_ Assert IOCON reset. 1 GPIO0_RST GPIO0 reset control [14:14] ENUM CLEAR_GPIO0_RESET_ Clear GPIO0 reset. 0 ASSERT_GPIO0_RESET_ Assert GPIO0 reset. 1 GPIO1_RST GPIO1 reset control [15:15] ENUM CLEAR_GPIO1_RESET_ Clear GPIO1 reset. 0 ASSERT_GPIO1_RESET_ Assert GPIO1 reset. 1 GPIO2_RST GPIO2 reset control [16:16] ENUM CLEAR_GPIO2_RESET_ Clear GPIO2 reset. 0 ASSERT_GPIO2_RESET_ Assert GPIO2 reset. 1 RESERVED Reserved [17:17] PINT_RST Pin interrupt (PINT) reset control [18:18] ENUM CLEAR_PINT_RESET_ Clear PINT reset. 0 ASSERT_PINT_RESET_ Assert PINT reset. 1 GINT_RST Grouped interrupt (GINT) reset control [19:19] ENUM CLEAR_GINT_RESET_ Clear GINT reset. 0 ASSERT_GINT_RESET_ Assert GINT reset. 1 DMA_RST DMA reset control [20:20] ENUM CLEAR_DMA_RESET_ Clear DMA reset. 0 ASSERT_DMA_RESET_ Assert DMA reset. 1 CRC_RST CRC generator reset control [21:21] ENUM CLEAR_CRC_RESET_ Clear CRC reset. 0 ASSERT_CRC_RESET_ Assert CRC reset. 1 RESERVED Reserved [26:22] ADC0_RST ADC0 reset control [27:27] ENUM CLEAR_ADC0_RESET_ Clear ADC0 reset. 0 ASSERT_ADC0_RESET_ Assert ADC0 reset. 1 ADC1_RST ADC1 reset control [28:28] ENUM CLEAR_ADC1_RESET_ Clear ADC1 reset. 0 ASSERT_ADC1_RESET_ Assert ADC1 reset. 1 DAC_RST DAC reset control [29:29] ENUM CLEAR_DAC_RESET_ Clear DAC reset. 0 ASSERT_DAC_RESET_ Assert DAC reset. 1 ACMP_RST Analog Comparator (ACMP) reset control for all four 4 comparators in the analog comparator block. [30:30] ENUM CLEAR_CMP_RESET_ Clear CMP reset. 0 ASSERT_CMP_RESET_ Assert CMP reset. 1 RESERVED Reserved [31:31] PRESETCTRL1 Peripheral reset control 1 0x048 read-write 0 0xFFFFFFFF MRT_RST Multi-rate timer (MRT) reset control [0:0] ENUM CLEAR_MRT_RESET_ Clear MRT reset. 0 ASSERT_MRT_RESET_ Assert MRT reset. 1 RIT_RST Repetitive interrupt timer (RIT) reset control [1:1] ENUM CLEAR_RIT_RESET_ Clear RIT reset. 0 ASSERT_RIT_RESET_ Assert RIT reset. 1 SCT0_RST State configurable timer 0 (SCT0) reset control [2:2] ENUM CLEAR_SCT0_RESET_ Clear SCT0 reset. 0 ASSERT_SCT0_RESET_ Assert SCT0 reset. 1 SCT1_RST State configurable timer 1 (SCT1) reset control [3:3] ENUM CLEAR_SCT1_RESET_ Clear SCT1 reset. 0 ASSERT_SCT1_RESET_ Assert SCT1 reset. 1 SCT2_RST State configurable timer 2 (SCT2) reset control [4:4] ENUM CLEAR_SCT2_RESET_ Clear SCT2 reset. 0 ASSERT_SCT2_RESET_ Assert SCT2 reset. 1 SCT3_RST State configurable timer 3 (SCT3) reset control [5:5] ENUM CLEAR_SCT3_RESET_ Clear SCT3 reset. 0 ASSERT_SCT3_RESET_ Assert SCT3 reset. 1 SCTIPU_RST State configurable timer IPU (SCTIPU) reset control [6:6] ENUM CLEAR_SCTIPU_RESET_ Clear SCTIPU reset. 0 ASSERT_SCTIPU_RESET_ Assert SCTIPU reset. 1 CCAN_RST CCAN reset control [7:7] ENUM CLEAR_CCAN_RESET_ Clear CCAN reset. 0 ASSERT_CCAN_RESET_ Assert CCAN reset. 1 RESERVED Reserved [8:8] SPI0_RST SPI0 reset control [9:9] ENUM CLEAR_SPI0_RESET_ Clear SPI0 reset. 0 ASSERT_SPI0_RESET_ Assert SPI0 reset. 1 SPI1_RST SPI1 reset control [10:10] ENUM CLEAR_SPI1_RESET_ Clear SPI1 reset. 0 ASSERT_SPI1_RESET_ Assert SPI1 reset. 1 RESERVED Reserved [12:11] I2C0_RST I2C0 reset control [13:13] ENUM CLEAR_I2C0_RESET_ Clear I2C0 reset. 0 ASSERT_I2C0_RESET_ Assert I2C0 reset. 1 RESERVED Reserved [16:14] UART0_RST UART0 reset control [17:17] ENUM CLEAR_UART0_RESET_ Clear UART0 reset. 0 ASSERT_UART0_RESET_ Assert UART0 reset. 1 UART1_RST UART1 reset control [18:18] ENUM CLEAR_UART1_RESET_ Clear UART1 reset. 0 ASSERT_UART1_RESET_ Assert UART1 reset. 1 UART2_RST UART2 reset control [19:19] ENUM CLEAR_UART2_RESET_ Clear UART2 reset. 0 ASSERT_UART2_RESET_ Assert UART2 reset. 1 RESERVED Reserved [20:20] QEI0_RST QEI0 reset control [21:21] ENUM CLEAR_QEI0_RESET_ Clear QEI0 reset. 0 ASSERT_QEI0_RESET_ Assert QEI0 reset. 1 RESERVED Reserved [22:22] USB_RST USB reset control [23:23] ENUM CLEAR_USB_RESET_ Clear USB reset. 0 ASSERT_USB_RESET_ Assert USB reset. 1 RESERVED Reserved [31:24] PIOPORCAP0 POR captured PIO status 0 0x04C read-only 0 0x00000000 PIOSTAT State of PIO0_31 through PIO0_0 at power-on reset [31:0] PIOPORCAP1 POR captured PIO status 1 0x050 read-only 0 0x00000000 PIOSTAT State of PIO1_31 through PIO1_0 at power-on reset [31:0] PIOPORCAP2 POR captured PIO status 2 0x054 read-only 0 0x00000000 PIOSTAT State of PIO2_11 through PIO2_0 at power-on reset [11:0] RESERVED Reserved. [31:12] MAINCLKSELA Main clock source select A 0x080 read-write 0 0xFFFFFFFF SEL Clock source for main clock source selector A [1:0] ENUM IRC_OSCILLATOR IRC Oscillator 0x0 SYSTEM_OSCILLATOR System oscillator 0x1 WATCHDOG_OSCILLATOR Watchdog oscillator 0x2 RESERVED Reserved 0x3 RESERVED Reserved [31:2] MAINCLKSELB Main clock source select B 0x084 read-write 0 0xFFFFFFFF SEL Clock source for main clock source selector B. Selects the clock source for the main clock. [1:0] ENUM MAINCLKSELA_CLOCK_S MAINCLKSELA. Clock source selected in MAINCLKSELA register. 0x0 SYSTEM_PLL_INPUT_ System PLL input. 0x1 SYSTEM_PLL_OUTPUT_ System PLL output. 0x2 RTC_OSCILLATOR_32_KH RTC oscillator 32 kHz output. 0x3 RESERVED Reserved [31:2] USBCLKSEL USB clock source select 0x088 read-write 0 0x00000000 SEL USB clock source. [1:0] ENUM IRC_OSCILLATOR IRC Oscillator 0x0 SYSTEM_OSCILLATOR System oscillator 0x1 USB_PLL_OUT USB PLL out 0x2 MAIN_CLOCK Main clock 0x3 RESERVED Reserved [31:2] ADCASYNCCLKSEL ADC asynchronous clock source select 0x08C read-write 0 0x00000000 SEL USB clock source. [1:0] ENUM IRC_OSCILLATOR IRC Oscillator 0x0 SYSTEM_PLL_OUTPUT System PLL output 0x1 USB_PLL_OUTPUT USB PLL output 0x2 SCT_PLL_OUTPUT SCT PLL output 0x3 RESERVED Reserved [31:2] CLKOUTSELA CLKOUT clock source select A 0x094 read-write 0 0xFFFFFFFF SEL CLKOUT clock source [1:0] ENUM IRC_OSCILLATOR IRC oscillator 0x0 CRYSTAL_OSCILLATOR_ Crystal oscillator (SYSOSC) 0x1 WATCHDOG_OSCILLATOR Watchdog oscillator 0x2 MAIN_CLOCK Main clock 0x3 RESERVED Reserved [31:2] CLKOUTSELB CLKOUT clock source select B 0x098 read-write 0 0xFFFFFFFF SEL CLKOUT clock source [1:0] ENUM CLKOUTSELA_CLOCK_SO CLKOUTSELA. Clock source selected in the CLKOUTSELA register. 0x0 USB_PLL_OUTPUT_ USB PLL output . 0x1 SCT_PLL_OUTPUT_ SCT PLL output . 0x2 RTC_32_KHZ_OUTPUT_ RTC 32 kHz output. 0x3 RESERVED Reserved [31:2] SYSPLLCLKSEL System PLL clock source select 0x0A0 read-write 0 0xFFFFFFFF SEL System PLL clock source [1:0] ENUM IRC IRC 0x0 CRYSTAL_OSCILLATOR_ Crystal Oscillator (SYSOSC) 0x1 RESERVED_ Reserved. 0x2 RESERVED_ Reserved. 0x3 RESERVED Reserved [31:2] USBPLLCLKSEL USB PLL clock source select 0x0A4 read-write 0 0x00000000 SEL USB PLL clock source [1:0] ENUM IRC_THE_USB_PLL_CLO IRC. The USB PLL clock source must be switched to system oscillator for correct USB operation.In low-speed mode IRC is ok? 0x0 SYSTEM_OSCILLATOR System oscillator 0x1 RESERVED Reserved 0x2 RESERVED Reserved 0x3 RESERVED Reserved [31:2] SCTPLLCLKSEL SCT PLL clock source select 0x0A8 read-write 0 0x00000000 SEL SCT PLL clock source [1:0] ENUM IRC IRC 0x0 SYSTEM_OSCILLATOR System oscillator 0x1 RESERVED Reserved 0x2 RESERVED Reserved 0x3 RESERVED Reserved [31:2] SYSAHBCLKDIV System clock divider 0x0C0 read-write 0 0x00000000 DIV System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] SYSAHBCLKCTRL0 System clock control 0 0x0C4 read-write 0 0x00000000 SYS Enables the clock for the AHB, the APB bridges, the Cortex-M3 core clocks, SYSCON, reset control, SRAM0, and the PMU. This bit is read-only and always reads as 1. [0:0] ENUM RESERVED Reserved 0 ENABLE Enable 1 ROM Enables clock for ROM. [1:1] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [2:2] SRAM1 Enables clock for SRAM1. [3:3] ENUM DISABLE Disable 0 ENABLE Enable 1 SRAM2 Enables clock for SRAM2. [4:4] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [6:5] FLASH Enables clock for flash memory. [7:7] ENUM DISABLE Disable 0 ENABLE Enable 1 FMC Enables clock for flash controller. [8:8] ENUM DISABLE Disable 0 ENABLE Enable 1 EEPROM Enables clock for EEPROM. [9:9] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [10:10] PMUX Enables clock for pin mux. [11:11] ENUM DISABLE Disable 0 ENABLE Enable 1 SWM Enables clock for switch matrix. [12:12] ENUM DISABLE Disable 0 ENABLE Enable 1 IOCON Enables clock for IOCON block. [13:13] ENUM DISABLE Disable 0 ENABLE Enable 1 GPIO0 Enables clock for GPIO0 port registers. [14:14] ENUM DISABLE Disable 0 ENABLE Enable 1 GPIO1 Enables clock for GPIO1 port registers. [15:15] ENUM DISABLE Disable 0 ENABLE Enable 1 GPIO2 Enables clock for GPIO2 port registers. [16:16] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [17:17] PINT Enables clock for pin interrupt block. [18:18] ENUM DISABLE Disable 0 ENABLE Enable 1 GINT Enables clock for grouped pin interrupt block. [19:19] ENUM DISABLE Disable 0 ENABLE Enable 1 DMA Enables clock for DMA. [20:20] ENUM DISABLE Disable 0 ENABLE Enable 1 CRC Enables clock for CRC. [21:21] ENUM DISABLE Disable 0 ENABLE Enable 1 WWDT Enables clock for WWDT. [22:22] ENUM DISABLE Disable 0 ENABLE Enable 1 RTC Enables clock for RTC. [23:23] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [26:24] ADC0 Enables clock for ADC0 register interface. [27:27] ENUM DISABLE Disable 0 ENABLE Enable 1 ADC1 Enables clock for ADC1 register interface. [28:28] ENUM DISABLE Disable 0 ENABLE Enable 1 DAC Enables clock for DAC. [29:29] ENUM DISABLE Disable 0 ENABLE Enable 1 CMP Enables clock to analog comparator block. This is the clock to the register interface for all 4 comparators. [30:30] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [31:31] SYSAHBCLKCTRL1 System clock control 1 0x0C8 read-write 0 0xFFFFFFFF MRT Enables clock for multi-rate timer. [0:0] ENUM DISABLE Disable 0 ENABLE Enable 1 RIT Enables clock for repetitive interrupt timer. [1:1] ENUM DISABLE Disable 0 ENABLE Enable 1 SCT0 Enables clock for SCT0. [2:2] ENUM DISABLE Disable 0 ENABLE Enable 1 SCT1 Enables clock for SCT1. [3:3] ENUM DISABLE Disable 0 ENABLE Enable 1 SCT2 Enables clock for SCT2. [4:4] ENUM DISABLE Disable 0 ENABLE Enable 1 SCT3 Enables clock for SCT3. [5:5] ENUM DISABLE Disable 0 ENABLE Enable 1 SCTIPU Enables clock for SCTIPU. [6:6] ENUM DISABLE Disable 0 ENABLE Enable 1 CCAN Enables clock for CCAN. [7:7] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [8:8] SPI0 Enables clock for SPI0. [9:9] ENUM DISABLE Disable 0 ENABLE Enable 1 SPI1 Enables clock for SPI1. [10:10] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [12:11] I2C0 Enables clock for I2C0. [13:13] ENUM DISABLE Disable 0 ENABLE Enable 1 I2C1 Enables clock for I2C1. [14:14] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [16:15] UART0 Enables clock for USART0. [17:17] ENUM DISABLE Disable 0 ENABLE Enable 1 UART1 Enables clock for USART1. [18:18] ENUM DISABLE Disable 0 ENABLE Enable 1 UART2 Enables clock for USART2. [19:19] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [20:20] QEI Enables clock for QEI. [21:21] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [22:22] USB Enables clock for USB register interface. [23:23] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [31:24] SYSTICKCLKDIV SYSTICK clock divider 0x0CC read-write 0 0xFFFFFFFF DIV SYSTICK clock divider values. 0: Disable SYSTICK timer clock. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] UARTCLKDIV USART clock divider. Clock divider for the USART fractional baud rate generator. 0x0D0 read-write 0 0xFFFFFFFF DIV USART fractional baud rate generator clock divider values. 0: Clock disabled. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] IOCONCLKDIV Peripheral clock to the IOCON block for programmable glitch filter 0x0D4 read-write 0 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] TRACECLKDIV ARM trace clock divider 0x0D8 read-write 0 0xFFFFFFFF DIV ARM trace clock divider values. 0: Disable TRACE_CLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] USBCLKDIV USB clock divider 0x0EC read-write 0 0x00000000 DIV USB clock divider values 0: Disable USB clock. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] ADCASYNCCLKDIV Asynchronous ADC clock divider 0x0F0 read-write 0 0x00000000 DIV USB clock divider values 0: Disable USB clock. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] CLKOUTDIV CLKOUT clock divider 0x0F8 read-write 0 0xFFFFFFFF DIV CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] FRGCTRL USART fractional baud rate generator control 0x128 read-write 0 0x00000000 DIV Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator. [7:0] MULT Numerator of the fractional divider. MULT is equal to the programmed value. [15:8] RESERVED Reserved [31:16] USBCLKCTRL USB clock control 0x12C read-write 0 0x00000000 AP_CLK USB need_clock signal control [0:0] ENUM UNDER_HARDWARE_CONTR Under hardware control. 0 FORCED_HIGH_ Forced HIGH. 1 POL_CLK USB need_clock polarity for triggering the USB wake-up interrupt [1:1] ENUM FALLING_EDGE_OF_THE_ Falling edge of the USB need_clock triggers the USB wake-up (default). 0 RISING_EDGE_OF_THE_U Rising edge of the USB need_clock triggers the USB wake-up. 1 RESERVED Reserved [31:2] USBCLKST USB clock status 0x130 read-write 0 0x00000000 NEED_CLKST USB need_clock signal status [0:0] ENUM LOW LOW 0 HIGH HIGH 1 RESERVED Reserved [31:1] BODCTRL Brown-Out Detect 0x180 read-write 0 0xFFFFFFFF BODRSTLEV BOD reset level [1:0] ENUM LEVEL_0_THE_RESET_A Level 0: The reset assertion threshold voltage is ; the reset de-assertion threshold voltage is . 0x0 LEVEL_1_THE_RESET_A Level 1: The reset assertion threshold voltage is ; the reset de-assertion threshold voltage is . 0x1 LEVEL_2_THE_RESET_A Level 2: The reset assertion threshold voltage is ; the reset de-assertion threshold voltage is . 0x2 LEVEL_3_THE_RESET_A Level 3: The reset assertion threshold voltage is ; the reset de-assertion threshold voltage is. 0x3 BODINTVAL BOD interrupt level [3:2] ENUM LEVEL_0_THE_INTERRU Level 0: The interrupt assertion threshold voltage is ; the interrupt de-assertion threshold voltage is 0x0 LEVEL_1_THE_INTERRU Level 1: The interrupt assertion threshold voltage is ; the interrupt de-assertion threshold voltage is . 0x1 LEVEL_2_THE_INTERRU Level 2: The interrupt assertion threshold voltage is ; the interrupt de-assertion threshold voltage is . 0x2 LEVEL_3_THE_INTERRU Level 3: The interrupt assertion threshold voltage is ; the interrupt de-assertion threshold voltage is . 0x3 BODRSTENA BOD reset enable [4:4] ENUM DISABLE_RESET_FUNCTI Disable reset function. 0 ENABLE_RESET_FUNCTIO Enable reset function. 1 RESERVED Reserved [31:5] SYSOSCCTRL System oscillator control 0x188 read-write 0x000 0xFFFFFFFF BYPASS Bypass system oscillator [0:0] ENUM DISABLED_OSCILLATOR Disabled. Oscillator is not bypassed. 0 ENABLED_PLL_INPUT_ Enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pin bypassing the oscillator. Use this mode when using an external clock source instead of the crystal oscillator. 1 FREQRANGE Determines frequency range for Low-power oscillator. [1:1] ENUM 1__20_MHZ_FREQUENCY 1 - 20 MHz frequency range. 0 15__25_MHZ_FREQUENC 15 - 25 MHz frequency range 1 RESERVED Reserved [31:2] RTCOSCCTRL RTC oscillator control 0x190 read-write 0x1 0xFFFFFFFF EN RTC 32 kHz clock enable. [0:0] ENUM DISABLED_RTC_CLOCK_ Disabled. RTC clock off. 0 ENABLED_RTC_CLOCK_O Enabled. RTC clock on. 1 RESERVED Reserved [31:1] SYSPLLCTRL System PLL control 0x198 read-write 0 0xFFFFFFFF MSEL Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 111111: Division ratio M = 64 [5:0] PSEL Post divider ratio P. The division ratio is 2 x P. [7:6] ENUM P_EQ_1 P = 1 0x0 P_EQ_2 P = 2 0x1 P_EQ_4 P = 4 0x2 P_EQ_8 P = 8 0x3 RESERVED Reserved. Do not write ones to reserved bits. [31:8] SYSPLLSTAT System PLL status 0x19C read-only 0 0xFFFFFFFF LOCK PLL lock status [0:0] ENUM PLL_NOT_LOCKED PLL not locked 0 PLL_LOCKED PLL locked 1 RESERVED Reserved [31:1] USBPLLCTRL USB PLL control 0x1A0 read-write 0 0x00000000 MSEL Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 111111: Division ratio M = 64. [5:0] PSEL Post divider ratio P. The division ratio is 2 x P. [7:6] ENUM P_EQ_1 P = 1 0x0 P_EQ_2 P = 2 0x1 P_EQ_4 P = 4 0x2 P_EQ_8 P = 8 0x3 RESERVED Reserved. Do not write ones to reserved bits. [31:8] USBPLLSTAT USB PLL status 0x1A4 read-only 0 0x00000000 LOCK PLL lock status [0:0] ENUM PLL_NOT_LOCKED PLL not locked 0 PLL_LOCKED PLL locked 1 RESERVED Reserved [31:1] SCTPLLCTRL SCT PLL control 0x1A8 read-write 0 0x00000000 MSEL Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 111111: Division ratio M = 64. [5:0] PSEL Post divider ratio P. The division ratio is 2 x P. [7:6] ENUM P_EQ_1 P = 1 0x0 P_EQ_2 P = 2 0x1 P_EQ_4 P = 4 0x2 P_EQ_8 P = 8 0x3 RESERVED Reserved. Do not write ones to reserved bits. [31:8] SCTPLLSTAT SCT PLL status 0x1AC read-only 0 0x00000000 LOCK PLL lock status [0:0] ENUM PLL_NOT_LOCKED PLL not locked 0 PLL_LOCKED PLL locked 1 RESERVED Reserved [31:1] PDAWAKECFG Power-down states for wake-up from deep-sleep 0x204 read-write 0xFFFFFF00 0xFFFFFFFF RESERVED Reserved. [2:0] IRCOUT_PD IRC oscillator output wake-up configuration [3:3] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 IRC IRC oscillator wake-up configuration [4:4] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 FLASH Flash memory wake-up configuration [5:5] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 EEPROM EEPROM wake-up configuration [6:6] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved [7:7] BOD_PD BOD wake-up configuration [8:8] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 USBPHY_PD USB PHY wake-up configuration [9:9] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 ADC0_PD ADC0 wake-up configuration [10:10] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 ADC1_PD ADC1 wake-up configuration [11:11] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 DAC_PD DAC wake-up configuration [12:12] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 ACMP0_PD Analog comparator 0 wake-up configuration [13:13] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 ACMP1_PD Analog comparator 1 wake-up configuration [14:14] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 ACMP2_PD Analog comparator 2 wake-up configuration [15:15] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 ACMP3_PD Analog comparator 3 wake-up configuration [16:16] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 IREF_PD Internal voltage reference wake-up configuration [17:17] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 TS_PD Temperature sensor wake-up configuration [18:18] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 VDDADIV_PD VDDA divider what is this for? wake-up configuration [19:19] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 WDTOSC_PD Watchdog oscillator wake-up configuration. [20:20] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SYSOSC_PD System oscillator wake-up configuration [21:21] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SYSPLL_PD System PLL wake-up configuration [22:22] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 USBPLL_PD USB PLL wake-up configuration [23:23] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SCTPLL_PD USB PLL wake-up configuration [24:24] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved [31:25] PDRUNCFG Power configuration register 0x208 read-write 0xFFFFFF00 0xFFFFFFFF RESERVED Reserved. [2:0] IRCOUT_PD IRC oscillator output [3:3] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 IRC IRC oscillator [4:4] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 FLASH Flash memory [5:5] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 EEPROM EEPROM [6:6] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved [7:7] BOD_PD BOD power-down [8:8] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 USBPHY_PD USB PHY power-down [9:9] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 ADC0_PD ADC0 power-down [10:10] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 ADC1_PD ADC1 power-down [11:11] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 DAC_PD DAC power-down [12:12] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 ACMP0_PD Analog comparator 0 power-down [13:13] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 ACMP1_PD Analog comparator 1 power-down [14:14] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 ACMP2_PD Analog comparator 2 power-down [15:15] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 ACMP3_PD Analog comparator 3 power-down [16:16] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 IREF_PD Internal voltage reference power-down [17:17] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 TS_PD Temperature sensor power-down [18:18] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 VDDADIV_PD VDDA divider what is this for? [19:19] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 WDTOSC_PD Watchdog oscillator power-down . [20:20] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SYSOSC_PD System oscillator power-down [21:21] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SYSPLL_PD System PLL power-down [22:22] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 USBPLL_PD USB PLL power-down [23:23] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SCTPLL_PD USB PLL power-down [24:24] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved [31:25] STARTERP0 Start logic 0 wake-up enable register 0x218 read-write 0 0xFFFFFFFF WWDT WWDT interrupt wake-up. [0:0] ENUM DISABLED Disabled 0 ENABLED Enabled 1 BOD BOD interrupt wake-up. [1:1] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved. [4:2] GINT0 Group interrupt 0 wake-up. [5:5] ENUM DISABLED Disabled 0 ENABLED Enabled 1 GINT1 Group interrupt 1 wake-up. [6:6] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT0 GPIO pin interrupt 0 wake-up [7:7] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT1 GPIO pin interrupt 1 wake-up [8:8] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT2 GPIO pin interrupt 2 wake-up [9:9] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT3 GPIO pin interrupt 3 wake-up [10:10] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT4 GPIO pin interrupt 4 wake-up [11:11] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT5 GPIO pin interrupt 5 wake-up [12:12] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT6 GPIO pin interrupt 6 wake-up [13:13] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT7 GPIO pin interrupt 7 wake-up [14:14] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved. [20:15] USART0 USART0 interrupt wake-up. Configure USART in synchronous slave mode or in 32 kHz mode.. [21:21] ENUM DISABLED Disabled 0 ENABLED Enabled 1 USART1 USART1 interrupt wake-up. Configure USART in synchronous slave mode or in 32 kHz mode... [22:22] ENUM DISABLED Disabled 0 ENABLED Enabled 1 USART2 USART2 interrupt wake-up. Configure USART in synchronous slave mode or in 32 kHz mode... [23:23] ENUM DISABLED Disabled 0 ENABLED Enabled 1 I2C I2C interrupt wake-up. [24:24] ENUM DISABLED Disabled 0 ENABLED Enabled 1 SPI0 SPI0 interrupt wake-up [25:25] ENUM DISABLED Disabled 0 ENABLED Enabled 1 SPI1 SPI1 interrupt wake-up [26:26] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved [29:27] USB_WAKEUP USB need_clock signal wake-up [30:30] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved [31:31] STARTERP1 Start logic 1 wake-up enable register 0x21C read-write 0 0xFFFFFFFF RESERVED Reserved [7:0] ACMP0 Analog comparator 0 interrupt wake-up [8:8] ENUM DISABLED Disabled 0 ENABLED Enabled 1 ACMP1 Analog comparator 1 interrupt wake-up [9:9] ENUM DISABLED Disabled 0 ENABLED Enabled 1 ACMP2 Analog comparator 2 interrupt wake-up [10:10] ENUM DISABLED Disabled 0 ENABLED Enabled 1 ACMP3 Analog comparator 3 interrupt wake-up [11:11] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved [12:12] RTCALARM RTC alarm interrupt wake-up [13:13] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RTCWAKE RTC wake-up interrupt wake-up [14:14] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved. [31:15] ADC1 ADC1 0x40080000 0 0xFFF registers ADC1_SEQA 35 ADC1_SEQB 36 ADC1_THCMP 37 ADC1_OVR 38 MRT Multi-Rate Timer (MRT) MRT 0x400A0000 0x0 0xFFF registers MRT 20 4 0x10 0-3 INTVAL%s MRT0 Time interval value register. This value is loaded into the TIMER0 register. 0x0 read-write 0 0xFFFFFFFF IVALUE Time interval load value. This value is loaded into the TIMERn register and the MRTn starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval. [23:0] RESERVED Reserved. [30:24] LOAD Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. [31:31] ENUM NO_FORCE_LOAD No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected. 0 FORCE_LOAD Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. 1 4 0x10 0-3 TIMER%s MRT0 Timer register. This register reads the value of the down-counter. 0x4 read-only 0xFFFFFF 0xFFFFFFFF VALUE Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF). [23:0] RESERVED Reserved. [31:24] 4 0x10 0-3 CTRL%s MRT0 Control register. This register controls the MRT0 modes. 0x8 read-write 0 0xFFFFFFFF INTEN Enable the TIMERn interrupt. [0:0] ENUM DISABLE Disable. 0 ENABLE Enable. 1 MODE Selects timer mode. [2:1] ENUM REPEAT_INTERRUPT_MOD Repeat interrupt mode. 0x0 ONE_SHOT_INTERRUPT_M One-shot interrupt mode. 0x1 RESERVED Reserved. 0x2 RESERVED Reserved. 0x3 RESERVED Reserved. [31:3] 4 0x10 0-3 STAT%s MRT0 Status register. 0xC read-write 0 0xFFFFFFFF INTFLAG Monitors the interrupt flag. [0:0] ENUM NO_PENDING_INTERRUPT No pending interrupt. Writing a zero is equivalent to no operation. 0 PENDING_INTERRUPT Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. 1 RUN Indicates the state of TIMERn. This bit is read-only. [1:1] ENUM IDLE_STATE Idle state. TIMERn is stopped. 0 RUNNING Running. TIMERn is running. 1 RESERVED Reserved. [31:2] IDLE_CH Idle channel register. This register returns the number of the first idle channel. 0xF4 read-only 0 0xFFFFFFFF RESERVED Reserved. [3:0] CHAN Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. If all timer channels are running, CHAN = 4. To make sure that all outstanding interrupt requests have been serviced, a channel is considered idle only when both the corresponding RUN bit and the interrupt flag are zero in the STATUS register. [7:4] RESERVED Reserved. [31:8] IRQ_FLAG Global interrupt flag register 0xF8 read-write 0 0xFFFFFFFF GFLAG0 Monitors the interrupt flag of TIMER0. [0:0] ENUM NO_PENDING_INTERRUPT No pending interrupt. Writing a zero is equivalent to no operation. 0 PENDING_INTERRUPT Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. 1 GFLAG1 Monitors the interrupt flag of TIMER1. [1:1] ENUM NO_PENDING_INTERRUPT No pending interrupt. Writing a zero is equivalent to no operation. 0 PENDING_INTERRUPT Pending interrupt. The interrupt is pending because TIMER1 has reached the end of the time interval. If the INTEN bit in the CONTROL1 register is also set to 1, the interrupt for timer channel 1 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. 1 GFLAG2 Monitors the interrupt flag of TIMER2. [2:2] ENUM NO_PENDING_INTERRUPT No pending interrupt. Writing a zero is equivalent to no operation. 0 PENDING_INTERRUPT Pending interrupt. The interrupt is pending because TIMER2 has reached the end of the time interval. If the INTEN bit in the CONTROL2 register is also set to 1, the interrupt for timer channel 2 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. 1 GFLAG3 Monitors the interrupt flag of TIMER3. [3:3] ENUM NO_PENDING_INTERRUPT No pending interrupt. Writing a zero is equivalent to no operation. 0 PENDING_INTERRUPT Pending interrupt. The interrupt is pending because TIMER3 has reached the end of the time interval. If the INTEN bit in the CONTROL3 register is also set to 1, the interrupt for timer channel 3 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. 1 RESERVED Reserved. [31:4] PINT Pin interrupt and pattern match (PINT) PINT 0x400A4000 0x0 0xFFF registers PIN_INT0 7 PIN_INT1 8 PIN_INT2 9 PIN_INT3 10 PIN_INT4 11 PIN_INT5 12 PIN_INT6 13 PIN_INT7 14 ISEL Pin Interrupt Mode register 0x000 read-write 0 0xFFFFFFFF PMODE0 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [0:0] PMODE1 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [1:1] PMODE2 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [2:2] PMODE3 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [3:3] PMODE4 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [4:4] PMODE5 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [5:5] PMODE6 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [6:6] PMODE7 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [7:7] RESERVED Reserved. [31:8] IENR Pin interrupt level or rising edge interrupt enable register 0x004 read-write 0 0xFFFFFFFF ENRL0 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [0:0] ENRL1 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [1:1] ENRL2 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [2:2] ENRL3 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [3:3] ENRL4 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [4:4] ENRL5 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [5:5] ENRL6 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [6:6] ENRL7 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [7:7] RESERVED Reserved. [31:8] SIENR Pin interrupt level or rising edge interrupt set register 0x008 write-only 0 0x00000000 SETENRL0 Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. [0:0] SETENRL1 Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. [1:1] SETENRL2 Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. [2:2] SETENRL3 Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. [3:3] SETENRL4 Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. [4:4] SETENRL5 Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. [5:5] SETENRL6 Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. [6:6] SETENRL7 Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. [7:7] RESERVED Reserved. [31:8] CIENR Pin interrupt level (rising edge interrupt) clear register 0x00C write-only 0 0x00000000 CENRL0 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [0:0] CENRL1 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [1:1] CENRL2 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [2:2] CENRL3 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [3:3] CENRL4 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [4:4] CENRL5 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [5:5] CENRL6 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [6:6] CENRL7 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [7:7] RESERVED Reserved. [31:8] IENF Pin interrupt active level or falling edge interrupt enable register 0x010 read-write 0 0xFFFFFFFF ENAF0 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [0:0] ENAF1 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [1:1] ENAF2 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [2:2] ENAF3 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [3:3] ENAF4 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [4:4] ENAF5 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [5:5] ENAF6 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [6:6] ENAF7 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [7:7] RESERVED Reserved. [31:8] SIENF Pin interrupt active level or falling edge interrupt set register 0x014 write-only 0 0x00000000 SETENAF0 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [0:0] SETENAF1 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [1:1] SETENAF2 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [2:2] SETENAF3 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [3:3] SETENAF4 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [4:4] SETENAF5 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [5:5] SETENAF6 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [6:6] SETENAF7 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [7:7] RESERVED Reserved. [31:8] CIENF Pin interrupt active level or falling edge interrupt clear register 0x018 write-only 0 0x00000000 CENAF0 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [0:0] CENAF1 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [1:1] CENAF2 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [2:2] CENAF3 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [3:3] CENAF4 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [4:4] CENAF5 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [5:5] CENAF6 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [6:6] CENAF7 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [7:7] RESERVED Reserved. [31:8] RISE Pin interrupt rising edge register 0x01C read-write 0 0xFFFFFFFF RDET0 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [0:0] RDET1 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [1:1] RDET2 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [2:2] RDET3 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [3:3] RDET4 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [4:4] RDET5 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [5:5] RDET6 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [6:6] RDET7 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [7:7] RESERVED Reserved. [31:8] FALL Pin interrupt falling edge register 0x020 read-write 0 0xFFFFFFFF FDET0 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [0:0] FDET1 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [1:1] FDET2 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [2:2] FDET3 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [3:3] FDET4 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [4:4] FDET5 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [5:5] FDET6 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [6:6] FDET7 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [7:7] RESERVED Reserved. [31:8] IST Pin interrupt status register 0x024 read-write 0 0xFFFFFFFF PSTAT0 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). [0:0] PSTAT1 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). [1:1] PSTAT2 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). [2:2] PSTAT3 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). [3:3] PSTAT4 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). [4:4] PSTAT5 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). [5:5] PSTAT6 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). [6:6] PSTAT7 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). [7:7] RESERVED Reserved. [31:8] PMCTRL Pattern match interrupt control register 0x028 read-write 0 0xFFFFFFFF SEL_PMATCH Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. [0:0] ENUM PIN_INTERRUPT_INTER Pin interrupt. Interrupts are driven in response to the standard pin interrupt function 0 PATTERN_MATCH_INTER Pattern match. Interrupts are driven in response to pattern matches. 1 ENA_RXEV Enables the RXEV output to the ARM cpu and/or to a GPIO output when the specified boolean expression evaluates to true. [1:1] ENUM DISABLED_RXEV_OUTPU Disabled. RXEV output to the cpu is disabled. 0 ENABLED_RXEV_OUTPUT Enabled. RXEV output to the cpu is enabled. 1 RESERVED Reserved. Do not write 1s to unused bits. [23:2] PMAT This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs. [31:24] PMSRC Pattern match interrupt bit-slice source register 0x02C read-write 0 0xFFFFFFFF Reserved Software should not write 1s to unused bits. [7:0] SRC0 Selects the input source for bit slice 0 [10:8] ENUM INPUT_0_SELECTS_PIN Input 0. Selects the output of pin interrupt select register 0 as the source to bit slice 0. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects the output of pin interrupt select register 1 as the source to bit slice 0. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects the output of pin interrupt select register 2 as the source to bit slice 0. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects the output of pin interrupt select register 3 as the source to bit slice 0. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects the output of pin interrupt select register 4 as the source to bit slice 0. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects the output of pin interrupt select register 5 as the source to bit slice 0. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects the output of pin interrupt select register 6 as the source to bit slice 0. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects the output of pin interrupt select register 7 as the source to bit slice 0. 0x7 SRC1 Selects the input source for bit slice 1 [13:11] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 1. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 1. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 1. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 1. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 1. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 1. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 1. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 1. 0x7 SRC2 Selects the input source for bit slice 2 [16:14] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 2. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 2. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 2. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 2. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 2. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 2. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 2. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 2. 0x7 SRC3 Selects the input source for bit slice 3 [19:17] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 3. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 3. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 3. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 3. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 3. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 3. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 3. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 3. 0x7 SRC4 Selects the input source for bit slice 4 [22:20] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 4. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 4. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 4. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 4. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 4. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 4. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 4. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 4. 0x7 SRC5 Selects the input source for bit slice 5 [25:23] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 5. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 5. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 5. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 5. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 5. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 5. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 5. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 5. 0x7 SRC6 Selects the input source for bit slice 6 [28:26] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 6. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 6. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 6. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 6. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 6. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 6. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 6. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 6. 0x7 SRC7 Selects the input source for bit slice 7 [31:29] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 7. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 7. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 7. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 7. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 7. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 7. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 7. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 7. 0x7 PMCFG Pattern match interrupt bit slice configuration register 0x030 read-write 0 0xFFFFFFFF PROD_ENDPTS A 1 in any bit of this field causes the corresponding bit slice to be the final component of a product term in the boolean expression. This has two effects: 1. The interrupt request associated with this bit-slice will be asserted whenever a match to that product term is detected. 2. The next bit slice will start a new, independent product term in the boolean expression (i.e. an OR will be inserted in the boolean expression following the element controlled by this bit slice). [6:0] RESERVED Reserved. Bit slice 7 is automatically considered a product end point. [7:7] CFG0 Specifies the match contribution condition for bit slice 0. [10:8] ENUM CONSTANT_HIGH_THIS_ Constant HIGH. This bit slice always contributes to a product term match. 0x0 STICKY_RISING_EDGEMA Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE_ Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_OR_FAL Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT_NON_STICKY_RI Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle. 0x7 CFG1 Specifies the match contribution condition for bit slice 1. [13:11] ENUM CONSTANT_HIGH_THIS_ Constant HIGH. This bit slice always contributes to a product term match. 0x0 STICKY_RISING_EDGEMA Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE_ Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_OR_FAL Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT_NON_STICKY_RI Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle. 0x7 CFG2 Specifies the match contribution condition for bit slice 2. [16:14] ENUM CONSTANT_HIGH_THIS_ Constant HIGH. This bit slice always contributes to a product term match. 0x0 STICKY_RISING_EDGEMA Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE_ Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_OR_FAL Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT_NON_STICKY_RI Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle. 0x7 CFG3 Specifies the match contribution condition for bit slice 3. [19:17] ENUM CONSTANT_HIGH_THIS_ Constant HIGH. This bit slice always contributes to a product term match. 0x0 STICKY_RISING_EDGEMA Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE_ Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_OR_FAL Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT_NON_STICKY_RI Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle. 0x7 CFG4 Specifies the match contribution condition for bit slice 4. [22:20] ENUM CONSTANT_HIGH_THIS_ Constant HIGH. This bit slice always contributes to a product term match. 0x0 STICKY_RISING_EDGEMA Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE_ Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_OR_FAL Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT_NON_STICKY_RI Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle. 0x7 CFG5 Specifies the match contribution condition for bit slice 5. [25:23] ENUM CONSTANT_HIGH_THIS_ Constant HIGH. This bit slice always contributes to a product term match. 0x0 STICKY_RISING_EDGEMA Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE_ Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_OR_FAL Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT_NON_STICKY_RI Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle. 0x7 CFG6 Specifies the match contribution condition for bit slice 6. [28:26] ENUM CONSTANT_HIGH_THIS_ Constant HIGH. This bit slice always contributes to a product term match. 0x0 STICKY_RISING_EDGEMA Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE_ Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_OR_FAL Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT_NON_STICKY_RI Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle. 0x7 CFG7 Specifies the match contribution condition for bit slice 7. [31:29] ENUM CONSTANT_HIGH_THIS_ Constant HIGH. This bit slice always contributes to a product term match. 0x0 STICKY_RISING_EDGEMA Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE_ Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_OR_FAL Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT_NON_STICKY_RI Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle. 0x7 GINT0 Group interrupt 0/1 (GINT0/1) GINT 0x400A8000 0x0 0xFFF registers GINT0 5 CTRL GPIO grouped interrupt control register 0x000 read-write 0 0xFFFFFFFF INT Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. [0:0] ENUM NO_INTERRUPT_REQUEST No interrupt request is pending. 0 INTERRUPT_REQUEST_IS Interrupt request is active. 1 COMB Combine enabled inputs for group interrupt [1:1] ENUM OR_FUNCTIONALITY_A_ OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). 0 AND_FUNCTIONALITY_A AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). 1 TRIG Group interrupt trigger [2:2] ENUM EDGE_TRIGGERED Edge-triggered 0 LEVEL_TRIGGERED Level-triggered 1 RESERVED Reserved [31:3] 3 0x4 0-2 PORT_POL[%s] PORT_POL[%s] GPIO grouped interrupt port 0 polarity register 0x020 read-write 0xFFFFFFFF 0xFFFFFFFF POL0 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [0:0] POL1 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [1:1] POL2 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [2:2] POL3 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [3:3] POL4 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [4:4] POL5 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [5:5] POL6 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [6:6] POL7 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [7:7] POL8 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [8:8] POL9 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [9:9] POL10 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [10:10] POL11 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [11:11] POL12 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [12:12] POL13 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [13:13] POL14 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [14:14] POL15 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [15:15] POL16 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [16:16] POL17 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [17:17] POL18 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [18:18] POL19 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [19:19] POL20 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [20:20] POL21 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [21:21] POL22 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [22:22] POL23 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [23:23] POL24 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [24:24] POL25 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [25:25] POL26 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [26:26] POL27 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [27:27] POL28 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [28:28] POL29 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [29:29] POL30 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [30:30] POL31 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [31:31] 3 0x4 0-2 PORT_ENA[%s] PORT_ENA[%s] GPIO grouped interrupt port 0 enable register 0x040 read-write 0 0xFFFFFFFF ENA0 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [0:0] ENA1 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [1:1] ENA2 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [2:2] ENA3 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [3:3] ENA4 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [4:4] ENA5 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [5:5] ENA6 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [6:6] ENA7 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [7:7] ENA8 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [8:8] ENA9 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [9:9] ENA10 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [10:10] ENA11 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [11:11] ENA12 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [12:12] ENA13 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [13:13] ENA14 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [14:14] ENA15 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [15:15] ENA16 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [16:16] ENA17 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [17:17] ENA18 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [18:18] ENA19 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [19:19] ENA20 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [20:20] ENA21 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [21:21] ENA22 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [22:22] ENA23 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [23:23] ENA24 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [24:24] ENA25 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [25:25] ENA26 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [26:26] ENA27 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [27:27] ENA28 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [28:28] ENA29 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [29:29] ENA30 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [30:30] ENA31 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [31:31] GINT1 GINT1 0x400AC000 0 0xFFF registers GINT1 6 RIT Repetitive Interrupt Timer (RIT) RIT 0x400B4000 0x0 0xFFF registers RIT 15 COMPVAL Compare value LSB register. Holds the 32 LSBs of the compare value. 0x000 read-write 0xFFFFFFFF 0xFFFFFFFF RICOMP Compare register. Holds the 32 LSBs of the compare value which is compared to the counter. [31:0] MASK Mask LSB register. This register holds the 32 LSB s of the mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. 0x004 read-write 0 0xFFFFFFFF RIMASK Mask register. This register holds the 32 LSBs of the mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true). [31:0] CTRL Control register. 0x008 read-write 0xC 0xFFFFFFFF RITINT Interrupt flag [0:0] ENUM THIS_BIT_IS_SET_TO_1 This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect. 1 THE_COUNTER_VALUE_DO The counter value does not equal the masked compare value. 0 RITENCLR Timer enable clear [1:1] ENUM THE_TIMER_WILL_BE_CL The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of COMPVAL/COMPVAL_H and MASK/MASK_H registers. This will occur on the same clock that sets the interrupt flag. 1 THE_TIMER_WILL_NOT_B The timer will not be cleared to 0. 0 RITENBR Timer enable for debug [2:2] ENUM THE_TIMER_IS_HALTED The timer is halted when the processor is halted for debugging. 1 DEBUG_HAS_NO_EFFECT Debug has no effect on the timer operation. 0 RITEN Timer enable. [3:3] ENUM TIMER_ENABLED Timer enabled. This can be overruled by a debug halt if enabled in bit 2. 1 TIMER_DISABLED Timer disabled. 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] COUNTER Counter LSB register. 32 LSBs of the counter. 0x00C read-write 0 0xFFFFFFFF RICOUNTER 32 LSBs of the up counter. Counts continuously unless RITEN bit in CTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software. [31:0] COMPVAL_H Compare value MSB register. Holds the 16 MSBs of the compare value. 0x010 read-write 0x0000FFFF 0xFFFFFFFF RICOMP Compare value MSB register. Holds the 16 MSBs of the compare value which is compared to the counter. [15:0] RESERVED Reserved. [31:16] MASK_H Mask MSB register. This register holds the 16 MSBs of the mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. 0x014 read-write 0 0xFFFFFFFF RIMASK Mask register. This register holds the 16 MSBs of the mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true). [15:0] RESERVED Reserved. [31:16] COUNTER_H Counter MSB register. 16 MSBs of the counter. 0x01C read-write 0 0xFFFFFFFF RICOUNTER 16 LSBs of the up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software. [15:0] RESERVED Reserved. [31:16] SCTIPU SCT Input Processing Unit (IPU) SCTIPU 0x400B8000 0x0 0xFFF registers SAMPLE_CTRL SCT IPU sample control register. Contains the input mux selects, latch/sample-enable mux selects, and sample overrride bits for the SAMPLE module. 0x000 read-write 0 0xFFFFFFFF IN0SEL Select SCT IPU input source for output channel 0. [0:0] ENUM SAMPE_IN_A0_SELECT_ SAMPE_IN_A0. Select input SAMPLE_IN_A0. 0 SAMPE_IN_B0_SELECT_ SAMPE_IN_B0. Select input SAMPLE_IN_B0. 1 IN1SEL Select SCT IPU input source for output channel 1. [1:1] ENUM SAMPE_IN_A1_SELECT_ SAMPE_IN_A1. Select input SAMPLE_IN_A1. 0 SAMPE_IN_B1_SELECT_ SAMPE_IN_B1. Select input SAMPLE_IN_B1. 1 IN2SEL Select SCT IPU input source for output channel 2. [2:2] ENUM SAMPE_IN_A2_SELECT_ SAMPE_IN_A2. Select input SAMPLE_IN_A2. 0 SAMPE_IN_B2_SELECT_ SAMPE_IN_B2. Select input SAMPLE_IN_B2. 1 IN3SEL Select. SCT IPU input source for output channel 3. [3:3] ENUM SAMPE_IN_A3_SELECT_ SAMPE_IN_A3. Select input SAMPLE_IN_A3. 0 SAMPE_IN_B3_SELECT_ SAMPE_IN_B3. Select input SAMPLE_IN_B3. 1 SAMPLE_EN0SEL Select the sample enable input as the latch/sample-enable control for the Sample_Output(0) latch. Depending on the value of the corresponding LATCHn_EN bit, this latch is transparent when the LATCHn_EN bit is 1 or latched when the LATCHn_EN bit is 0. [5:4] ENUM SELECTS_SAMPLE_ENABL Selects Sample_Enable_A as the latch/sample-enable control for the Sample_Output(0) latch. 0x0 SELECTS_SAMPLE_ENABL Selects Sample_Enable_B as the latch/sample-enable control for the Sample_Output(0) latch. 0x1 SELECTS_SAMPLE_ENABL Selects Sample_Enable_C as the latch/sample-enable control for the Sample_Output(0) latch. 0x2 SELECTS_SAMPLE_ENABL Selects Sample_Enable_D as the latch/sample-enable control for the Sample_Output(0) latch. 0x3 SAMPLE_EN1SEL Select the sample enable input as the latch/sample-enable control for the Sample_Output(1) latch. Depending on the value of the corresponding LATCHn_EN bit, this latch is transparent when the LATCHn_EN bit is 1 or latched when the LATCHn_EN bit is 0. [7:6] ENUM SELECTS_SAMPLE_ENABL Selects Sample_Enable_A as the latch/sample-enable control for the Sample_Output(1) latch. 0x0 SELECTS_SAMPLE_ENABL Selects Sample_Enable_B as the latch/sample-enable control for the Sample_Output(1) latch. 0x1 SELECTS_SAMPLE_ENABL Selects Sample_Enable_C as the latch/sample-enable control for the Sample_Output(1) latch. 0x2 SELECTS_SAMPLE_ENABL Selects Sample_Enable_D as the latch/sample-enable control for the Sample_Output(1) latch. 0x3 SAMPLE_EN2SEL Select the sample enable input as the latch/sample-enable control for the Sample_Output(2) latch. Depending on the value of the corresponding LATCHn_EN bit, this latch is transparent when the LATCHn_EN bit is 1 or latched when the LATCHn_EN bit is 0. [9:8] ENUM SELECTS_SAMPLE_ENABL Selects Sample_Enable_A as the latch/sample-enable control for the Sample_Output(2) latch. 0x0 SELECTS_SAMPLE_ENABL Selects Sample_Enable_B as the latch/sample-enable control for the Sample_Output(2) latch. 0x1 SELECTS_SAMPLE_ENABL Selects Sample_Enable_C as the latch/sample-enable control for the Sample_Output(2) latch. 0x2 SELECTS_SAMPLE_ENABL Selects Sample_Enable_D as the latch/sample-enable control for the Sample_Output(2) latch. 0x3 SAMPLE_EN3SEL Select the sample enable input as the latch/sample-enable control for the Sample_Output(3) latch. Depending on the value of the corresponding LATCHn_EN bit, this latch is transparent when the LATCHn_EN bit is 1 or latched when the LATCHn_EN bit is 0. [11:10] ENUM SELECTS_SAMPLE_ENABL Selects Sample_Enable_A as the latch/sample-enable control for the Sample_Output(3) latch. 0x0 SELECTS_SAMPLE_ENABL Selects Sample_Enable_B as the latch/sample-enable control for the Sample_Output(3) latch. 0x1 SELECTS_SAMPLE_ENABL Selects Sample_Enable_C as the latch/sample-enable control for the Sample_Output(3) latch. 0x2 SELECTS_SAMPLE_ENABL Selects Sample_Enable_D as the latch/sample-enable control for the Sample_Output(3) latch. 0x3 LATCHEN0 Enable latch for output channel 0. [12:12] ENUM TRANSPARENT_MODE_SA Transparent mode. Sample_Output(0) latch is forced into transparent mode. The selected Sample_Input is passed directly through to Sample_Output(0). The sample-enable control line selected for this latch has no effect. 0 LATCHED_MODE_THE_SA Latched mode. The Sample_Output(0) latch is operational and will sample or latch based on the state of the selected sample-enable control signal. 1 LATCHEN1 Enable latch for output channel 1. [13:13] ENUM TRANSPARENT_MODE_SA Transparent mode. Sample_Output(1) latch is forced into transparent mode. The selected Sample_Input is passed directly through to Sample_Output(1). The sample-enable control line selected for this latch has no effect. 0 LATCHED_MODE_THE_SA Latched mode. The Sample_Output(1) latch is operational and will sample or latch based on the state of the selected sample-enable control signal. 1 LATCHEN2 Enable latch for output channel 2. [14:14] ENUM TRANSPARENT_MODE_SA Transparent mode. Sample_Output(2) latch is forced into transparent mode. The selected Sample_Input is passed directly through to Sample_Output(2). The sample-enable control line selected for this latch has no effect. 0 LATCHED_MODE_THE_SA Latched mode. The Sample_Output(2) latch is operational and will sample or latch based on the state of the selected sample-enable control signal. 1 LATCHEN3 Enable latch for output channel 3. [15:15] ENUM TRANSPARENT_MODE_SA Transparent mode. Sample_Output(3) latch is forced into transparent mode. The selected Sample_Input is passed directly through to Sample_Output(3). The sample-enable control line selected for this latch has no effect. 0 LATCHED_MODE_THE_SA Latched mode. The Sample_Output(3) latch is operational and will sample or latch based on the state of the selected sample-enable control signal. 1 4 0x20 0-3 ABORT_ENABLE%s SCT IPU abort enable register: Selects which input source contributes to ORed Abort Output 0. 0x020 read-write 0 0xFFFFFFFF ENA0 Enable abort source SCT_ABORT0. [0:0] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 ENA1 Enable abort source SCT_ABORT1. [1:1] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 ENA2 Enable abort source ACMP0 output. [2:2] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 ENA3 Enable abort source ACMP1 output. [3:3] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 ENA4 Enable abort source ACMP2 output. [4:4] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 ENA5 Enable abort source ACMP3 output. [5:5] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 ENA6 Enable abort source SCT0_OUT9. [6:6] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 ENA7 Enable abort source ADC0_THCMP_IRQ. [7:7] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 ENA8 Enable abort source ADC1_THCMP_IRQ. [8:8] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 4 0x20 0-3 ABORT_SOURCE%s SCT IPU abort source register: Status register indicating which input source caused abort output 0. 0x024 read-write 0 0xFFFFFFFF ACT0 Source SCT_ABORT0 activated. This bit is set by hardware when the source is actived. Write 0 to clear. This function can be assigned to any pin via the PINASSIGN10 register in the switch matrix. [0:0] ENUM NOT_ACTIVATED_ Not activated. 0 ACTIVATED_ Activated. 1 ACT1 Source SCT_ABORT1 activated. This bit is set by hardware when the source is actived. Write 0 to clear. This function can be assigned to any pin via the PINASSIGN10 register in the switch matrix. [1:1] ENUM NOT_ACTIVATED_ Not activated. 0 ACTIVATED_ Activated. 1 ACT2 Source ACMP0 output activated. This bit is set by hardware when the source is actived. Write 0 to clear. [2:2] ENUM NOT_ACTIVATED_ Not activated. 0 ACTIVATED_ Activated. 1 ACT3 Source ACMP1 output activated. This bit is set by hardware when the source is actived. Write 0 to clear. [3:3] ENUM NOT_ACTIVATED_ Not activated. 0 ACTIVATED_ Activated. 1 ACT4 Source ACMP2 output activated. This bit is set by hardware when the source is actived. Write 0 to clear. [4:4] ENUM NOT_ACTIVATED_ Not activated. 0 ACTIVATED_ Activated. 1 ACT5 Source ACMP3 output activated. This bit is set by hardware when the source is actived. Write 0 to clear. [5:5] ENUM NOT_ACTIVATED_ Not activated. 0 ACTIVATED_ Activated. 1 ACT6 Source SCT0_OUT9 activated. This bit is set by hardware when the source is actived. Write 0 to clear. [6:6] ENUM NOT_ACTIVATED_ Not activated. 0 ACTIVATED_ Activated. 1 ACT7 Source ADC0_THCMP_IRQ activated. This bit is set by hardware when the source is actived. Write 0 to clear. [7:7] ENUM NOT_ACTIVATED_ Not activated. 0 ACTIVATED_ Activated. 1 ACT8 Source ADC1_THCMP_IRQ activated. This bit is set by hardware when the source is actived. Write 0 to clear. [8:8] ENUM NOT_ACTIVATED_ Not activated. 0 ACTIVATED_ Activated. 1 FLASHCTRL Flash controller FLASHCTRL 0x400BC000 0x0 0xFFF registers FLASH 2 EE 3 FMSSTART Signature start address register 0x020 read-write 0 0xFFFFFFFF START Signature generation start address (corresponds to AHB byte address bits[20:4]). [16:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:17] FMSSTOP Signature stop-address register 0x024 read-write 0 0xFFFFFFFF STOPA Stop address for signature generation (the word specified by STOPA is included in the address range). The address is in units of memory words, not bytes. [16:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [30:17] STRTBIST When this bit is written to 1, signature generation starts. At the end of signature generation, this bit is automatically cleared. [31:31] FMSW0 Signature word 0x02C read-only 0 0x00000000 SIG 32-bit signature. [31:0] USART2 USART2 0x400C0000 0 0xFFF registers UART2 23 C_CAN0 Controller Area Network C_CAN0 C_CAN0 0x400F0000 0x0 0xFFF registers C_CAN0 27 CNTL CAN control 0x000 read-write 0x0001 0xFFFFFFFF INIT Initialization [0:0] ENUM NORMAL_OPERATION Normal operation. 0 STARTED Started. Initialization is started. On reset, software needs to initialize the CAN controller. 1 IE Module interrupt enable [1:1] ENUM DISABLE_CAN_INTERRUP Disable CAN interrupts. The interrupt line is always HIGH. 0 ENABLE_CAN_INTERRUPT Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared. 1 SIE Status change interrupt enable [2:2] ENUM DISABLE_STATUS_CHANG Disable status change interrupts. No status change interrupt will be generated. 0 ENABLE_STATUS_CHANGE Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected. 1 EIE Error interrupt enable [3:3] ENUM DISABLE_ERROR_INTERR Disable error interrupt. No error status interrupt will be generated. 0 ENABLE_ERROR_INTERRU Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt. 1 RESERVED reserved [4:4] DAR Disable automatic retransmission [5:5] ENUM ENABLED Enabled. Automatic retransmission of disturbed messages enabled. 0 DISABLED Disabled. Automatic retransmission disabled. 1 CCE Configuration change enable [6:6] ENUM NO_WRITE_ACCESS No write access. The CPU has no write access to the bit timing register. 0 WRITE_ACCESS Write access. The CPU has write access to the CANBT register while the INIT bit is one. 1 TEST Test mode enable [7:7] ENUM NORMAL_OPERATION Normal operation. 0 TEST_MODE Test mode. 1 RESERVED reserved [31:8] STAT Status register 0x004 read-write 0x0000 0xFFFFFFFF LEC Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates. [2:0] ENUM NO_ERROR No error. 0x0 STUFF_ERROR Stuff error. More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 0x1 FORM_ERROR Form error. A fixed format part of a received frame has the wrong format. 0x2 ACKERROR AckError. The message this CAN core transmitted was not acknowledged. 0x3 BIT1ERROR Bit1Error. During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant. 0x4 BIT0ERROR Bit0Error. During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed). 0x5 CRCERROR CRCError. The CRC checksum was incorrect in the message received. 0x6 UNUSED Unused. No CAN bus event was detected (written by the CPU). 0x7 TXOK Transmitted a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller. [3:3] ENUM NO_TRANSMIT No transmit. Since this bit was last reset by the CPU, no message has been successfully transmitted. 0 SUCCESSFUL_TRANSMIT Successful transmit. Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node). 1 RXOK Received a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller. [4:4] ENUM NO_RECEIVE No receive. Since this bit was last reset by the CPU, no message has been successfully received. 0 SUCCESSFUL_RECEIVE Successful receive.Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering. 1 EPASS Error passive [5:5] ENUM ACTIVE Active. The CAN controller is in the error active state. 0 PASSIVE Passive. The CAN controller is in the error passive state as defined in the CAN 2.0 specification. 1 EWARN Warning status [6:6] ENUM BELOW_LIMIT Below limit. Both error counters are below the error warning limit of 96. 0 AT_LIMIT At limit. At least one of the error counters in the EC has reached the error warning limit of 96. 1 BOFF Busoff status [7:7] ENUM THE_CAN_MODULE_IS_NO The CAN module is not in busoff. 0 THE_CAN_CONTROLLER_I The CAN controller is in busoff state. 1 RESERVED reserved [31:8] EC Error counter 0x008 read-only 0x0000 0xFFFFFFFF TEC7_0 Transmit error counter Current value of the transmit error counter (maximum value 255) [7:0] REC6_0 Receive error counter Current value of the receive error counter (maximum value 127). [14:8] RP Receive error passive [15:15] ENUM BELOW_ERROR_LEVEL Below error level. The receive counter is below the error passive level. 0 AT_ERROR_LEVEL At error level. The receive counter has reached the error passive level as defined in the CAN2.0 specification. 1 RESERVED Reserved [31:16] BT Bit timing register 0x00C read-write 0x2301 0xFFFFFFFF BRP Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63.[1] [5:0] SJW (Re)synchronization jump width Valid programmed values are 0 to 3.[1] [7:6] TSEG1 Time segment before the sample point Valid values are 1 to 15.[1] [11:8] TSEG2 Time segment after the sample point Valid values are 0 to 7.[1] [14:12] RESERVED Reserved [31:15] INT Interrupt register 0x010 read-only 0x0000 0xFFFFFFFF INTID 0x0000 = No interrupt is pending. 0x0001 - 0x0020 = Number of message object which caused the interrupt. 0x0021 - 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 - 0xFFFF = Unused [15:0] RESERVED Reserved [31:16] TEST Test register 0x014 read-write 0 0x00000000 RESERVED Reserved [1:0] BASIC Basic mode [2:2] ENUM DISABLED Disabled. Basic mode disabled. 0 ENABLED Enabled. IF1 registers used as TX buffer, IF2 registers used as RX buffer. 1 SILENT Silent mode [3:3] ENUM NORMAL_OPERATION Normal operation. 0 SILENT_MODE Silent mode. The module is in silent mode. 1 LBACK Loop back mode [4:4] ENUM DISABLED Disabled. Loop back mode is disabled. 0 ENABLED Enabled. Loop back mode is enabled. 1 TX Control of CAN_TXD pins [6:5] ENUM CONTROLLER Controller. Level at the CAN_TXD pin is controlled by the CAN controller. This is the value at reset. 0x0 SAMPLE_POINT Sample point. The sample point can be monitored at the CAN_TXD pin. 0x1 LOW Low. CAN_TXD pin is driven LOW/dominant. 0x2 HOGH Hogh. CAN_TXD pin is driven HIGH/recessive. 0x3 RX Monitors the actual value of the CAN_RXD pin. [7:7] ENUM RECESSIVE Recessive. The CAN bus is recessive (CAN_RXD = 1). 0 DOMINANT Dominant. The CAN bus is dominant (CAN_RXD = 0). 1 RESERVED R/W [31:8] BRPE Baud rate prescaler extension register 0x018 read-write 0x0000 0xFFFFFFFF BRPE Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0 to 15. [3:0] RESERVED Reserved [31:4] 2 0x60 1-2 IF%s_CMDREQ Message interface command request 0x020 read-write 0x0001 0xFFFFFFFF MN Message number 0x01 - 0x20 = Valid message numbers. The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 - 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1] [5:0] RESERVED reserved [14:6] BUSY BUSY flag [15:15] ENUM DONE Done. Set to zero by hardware when read/write action to this Command request register has finished. 0 BUSY Busy. Set to one by hardware when writing to this Command request register. 1 RESERVED Reserved [31:16] 2 0x60 1-2 IF%s_CMDMSK_W Message interface command mask (write direction) 0x024 read-write 0x0000 0xFFFFFFFF DATA_B Access data bytes 4-7 [0:0] ENUM UNCHANGED Unchanged. Data bytes 4-7 unchanged. 0 TRANSFER Transfer. Transfer data bytes 4-7 to message object. 1 DATA_A Access data bytes 0-3 [1:1] ENUM UNCHANGED Unchanged. Data bytes 0-3 unchanged. 0 TRANSFER Transfer. Transfer data bytes 0-3 to message object. 1 TXRQST Access transmission request bit [2:2] ENUM NO_TRANSMISSION_REQU No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored. 0 REQUEST_A_TRANSMISSI Request a transmission. Set the TXRQST bit IF1/2_MCTRL. 1 CLRINTPND This bit is ignored in the write direction. [3:3] CTRL Access control bits [4:4] ENUM UNCHANGED Unchanged. Control bits unchanged. 0 TRANSFER Transfer. Transfer control bits to message object 1 ARB Access arbitration bits [5:5] ENUM UNCHANGED Unchanged. Arbitration bits unchanged. 0 TRANSFER Transfer. Transfer Identifier, DIR, XTD, and MSGVAL bits to message object. 1 MASK Access mask bits [6:6] ENUM UNCHANGED Unchanged. Mask bits unchanged. 0 TRANSFER Transfer. Transfer Identifier MASK + MDIR + MXTD to message object. 1 WR_RD Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ. [7:7] RESERVED reserved [31:8] 2 0x60 1-2 IF%s_CMDMSK_R Message interface command mask (read direction) IF%s_CMDMSK_W 0x024 read-write 0x0000 0xFFFFFFFF DATA_B Access data bytes 4-7 [0:0] ENUM UNCHANGED Unchanged. Data bytes 4-7 unchanged. 0 TRANSFER Transfer. Transfer data bytes 4-7 to IFx message buffer register. 1 DATA_A Access data bytes 0-3 [1:1] ENUM UNCHANGED Unchanged. Data bytes 0-3 unchanged. 0 TRANSFER Transfer. Transfer data bytes 0-3 to IFx message buffer. 1 NEWDAT Access new data bit [2:2] ENUM UNCHANGED Unchanged. NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits. 0 CLEAR Clear. Clear NEWDAT bit in the message object. 1 CLRINTPND Clear interrupt pending bit. [3:3] ENUM UNCHANGED Unchanged. INTPND bit remains unchanged. 0 CLEAR Clear. Clear INTPND bit in the message object. 1 CTRL Access control bits [4:4] ENUM UNCHANGED Unchanged. Control bits unchanged. 0 TRANSFER Transfer. Transfer control bits to IFx message buffer. 1 ARB Access arbitration bits [5:5] ENUM UNCHANGED Unchanged. Arbitration bits unchanged. 0 TRANSFER Transfer. Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register. 1 MASK Access mask bits [6:6] ENUM UNCHANGED Unchanged. Mask bits unchanged. 0 TRANSFER Transfer. Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register. 1 WR_RD Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ. [7:7] RESERVED reserved [31:8] 2 0x60 1-2 IF%s_MSK1 Message interface mask 1 0x028 read-write 0xFFFF 0xFFFFFFFF MSK15_0 Identifier mask [15:0] [15:0] ENUM MATCH Match. The corresponding bit in the identifier of the message cannot inhibit the match in the acceptance filtering. 0 MASK Mask. The corresponding identifier bit is used for acceptance filtering. 1 RESERVED Reserved [31:16] 2 0x60 1-2 IF%s_MSK2 Message interface mask 2 0x02C read-write 0xFFFF 0xFFFFFFFF MSK28_16 Identifier mask [28:16] [12:0] ENUM MATCH Match. The corresponding bit in the identifier of the message cannot inhibit the match in the acceptance filtering. 0 MASK Mask. The corresponding identifier bit is used for acceptance filtering. 1 RESERVED Reserved [13:13] MDIR Mask message direction [14:14] ENUM WITHOUT_DIR_BIT Without DIR bit. The message direction bit (DIR) has no effect on acceptance filtering. 0 WITH_DIR_BIT With DIR bit. The message direction bit (DIR) is used for acceptance filtering. 1 MXTD Mask extend identifier [15:15] ENUM WITHOUT_XTD Without XTD. The extended identifier bit (XTD) has no effect on acceptance filtering. 0 WITH_XTD With XTD. The extended identifier bit (XTD) is used for acceptance filtering. 1 RESERVED Reserved [31:16] 2 0x60 1-2 IF%s_ARB1 Message interface arbitration 1 0x030 read-write 0x0000 0xFFFFFFFF ID15_0 Message identifier [15:0] 29-bit identifier (extended frame) 11-bit identifier (standard frame) [15:0] RESERVED Reserved [31:16] 2 0x60 1-2 IF%s_ARB2 Message interface arbitration 2 0x034 read-write 0x0000 0xFFFFFFFF ID28_16 Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame) [12:0] DIR Message direction [13:13] ENUM RECEIVE Receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object. 0 TANSMIT Tansmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one). 1 XTD Extend identifier [14:14] ENUM STANDARD Standard. The 11-bit standard identifier will be used for this message object. 0 EXTENDED Extended. The 29-bit extended identifier will be used for this message object. 1 MSGVAL Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required. [15:15] ENUM INVALID Invalid. The message object is ignored by the message handler. 0 VALID Valid. The message object is configured and should be considered by the message handler. 1 RESERVED Reserved [31:16] 2 0x60 1-2 IF%s_MCTRL Message interface message control 0x038 read-write 0x0000 0xFFFFFFFF DLC3_0 Data length code 3:0 The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 - 1000 = Data frame has 0 - 8 data bytes. 1001 - 1111 = Data frame has 8 data bytes. [3:0] RESERVED Reserved [6:4] EOB End of buffer [7:7] ENUM NOT_END_OF_BUFFER Not end of buffer. Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer. 0 END_OF_BUFFER End of buffer. Single message object or last message object of a FIFO buffer. 1 TXRQST Transmit request [8:8] ENUM NOT_WAITING Not waiting. This message object is not waiting for transmission. 0 WAITING Waiting. The transmission of this message object is requested and is not yet done 1 RMTEN Remote enable [9:9] ENUM TXRQST_UNCHANGED TXRQST unchanged. At the reception of a remote frame, TXRQST is left unchanged. 0 TXRQST_SET TXRQST set. At the reception of a remote frame, TXRQST is set. 1 RXIE Receive interrupt enable [10:10] ENUM INTPND_UNCHANGED INTPND unchanged. INTPND will be left unchanged after successful reception of a frame. 0 INTPND_SET INTPND set. INTPND will be set after successful reception of a frame. 1 TXIE Transmit interrupt enable [11:11] ENUM INTPND_UNCHANGED INTPND unchanged. The INTPND bit will be left unchanged after a successful transmission of a frame. 0 INTPND_SET INTPND set. INTPND will be set after a successful transmission of a frame. 1 UMASK Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1. [12:12] ENUM IGNORE Ignore. Mask ignored. 0 USE Use. Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering. 1 INTPND Interrupt pending [13:13] ENUM NOT_PENDING Not pending. This message object is not the source of an interrupt. 0 PENDING Pending. This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority. 1 MSGLST Message lost (only valid for message objects in the direction receive). [14:14] ENUM NOT_LOST Not lost. No message lost since this bit was reset last by the CPU. 0 LOST Lost. The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message. 1 NEWDAT New data [15:15] ENUM NO_NEW_DATA No new data. No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU. 0 NEW_DATA New data. The message handler or the CPU has written new data into the data portion of this message object. 1 RESERVED Reserved [31:16] 2 0x60 1-2 IF%s_DA1 Message interface data A1 0x03C read-write 0x0000 0xFFFFFFFF DATA0 Data byte 0 [7:0] DATA1 Data byte 1 [15:8] RESERVED Reserved [31:16] 2 0x60 1-2 IF%s_DA2 Message interface 1 data A2 0x040 read-write 0x0000 0xFFFFFFFF DATA2 Data byte 2 [7:0] DATA3 Data byte 3 [15:8] RESERVED Reserved [31:16] 2 0x60 1-2 IF%s_DB1 Message interface 1 data B1 0x044 read-write 0x0000 0xFFFFFFFF DATA4 Data byte 4 [7:0] DATA5 Data byte 5 [15:8] RESERVED Reserved [31:16] 2 0x60 1-2 IF%s_DB2 Message interface 1 data B2 0x048 read-write 0x0000 0xFFFFFFFF DATA6 Data byte 6 [7:0] DATA7 Data byte 7 [15:8] RESERVED Reserved [31:16] TXREQ1 Transmission request 1 0x100 read-only 0x0000 0xFFFFFFFF TXRQST16_1 Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done. [15:0] RESERVED Reserved [31:16] TXREQ2 Transmission request 2 0x104 read-only 0x0000 0xFFFFFFFF TXRQST32_17 Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done. [15:0] RESERVED Reserved [31:16] ND1 New data 1 0x120 read-only 0x0000 0xFFFFFFFF NEWDAT16_1 New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object. [15:0] RESERVED Reserved [31:16] ND2 New data 2 0x124 read-only 0x0000 0xFFFFFFFF NEWDAT32_17 New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object. [15:0] RESERVED Reserved [31:16] IR1 Interrupt pending 1 0x140 read-only 0x0000 0xFFFFFFFF INTPND16_1 Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt. [15:0] RESERVED Reserved [31:16] IR2 Interrupt pending 2 0x144 read-only 0x0000 0xFFFFFFFF INTPND32_17 Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt. [15:0] RESERVED Reserved [31:16] MSGV1 Message valid 1 0x160 read-only 0x0000 0xFFFFFFFF MSGVAL16_1 Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler. [15:0] RESERVED Reserved [31:16] MSGV2 Message valid 2 0x164 read-only 0x0000 0xFFFFFFFF MSGVAL32_17 Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler. [15:0] RESERVED Reserved [31:16] CLKDIV CAN clock divider register 0x180 read-write 0x1 0xFFFFFFFF CLKDIVVAL Clock divider value. CAN_CLK = system clock/(CLKDIVVAL +1) 0000: CAN_CLK = system clock divided by 1. 0001: CAN_CLK = system clock divided by 2. 0010: CAN_CLK = system clockdivided by 3 0011: CAN_CLK = system clock divided by 4. ... 1111: CAN_CLK = system clock divided by 16. [3:0] RESERVED reserved [31:4] IOCON I/O pin configuration (IOCON) IOCON 0x400F8000 0x0 0xFFF registers 18 0x4 0-17 PIO0_%s PIO0_%s Digital I/O control for port 0 pins PIO0_0 to PIO0_17. With glitch filter. 0x000 read-write 0 0x00000000 RESERVED Reserved. Only write 0 to these bits. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE Disable. 0 ENABLE Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [7:7] FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_ENABLED_ Filter enabled. 0 FILTER_DISABLED_ Filter disabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER Bypass input filter. 0x0 1_CLOCK_CYCLE 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLKDIV Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved. [15:13] ENUM CMP_PCLK CMP_PCLK. 0x0 CMP_PCLKDIV2 CMP_PCLK/2. 0x1 CMP_PCLKDIV4 CMP_PCLK/4. 0x2 CMP_PCLKDIV8 CMP_PCLK/8. 0x3 CMP_PCLKDIV16 CMP_PCLK/16. 0x4 CMP_PCLKDIV32 CMP_PCLK/32. 0x5 CMP_PCLKDIV64 CMP_PCLK/64. 0x6 RESERVED Reserved. [31:16] 4 0x4 18-21 PIO0_%s Digital I/O control for port 0 pins PIO0_18 to PIO0_21. Without glitch filter. 0x048 read-write 0 0x00000000 RESERVED Reserved. Only write 0 to these bits. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE Disable. 0 ENABLE Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER Bypass input filter. 0x0 1_CLOCK_CYCLE 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLKDIV Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved. [15:13] ENUM CMP_PCLK CMP_PCLK. 0x0 CMP_PCLKDIV2 CMP_PCLK/2. 0x1 CMP_PCLKDIV4 CMP_PCLK/4. 0x2 CMP_PCLKDIV8 CMP_PCLK/8. 0x3 CMP_PCLKDIV16 CMP_PCLK/16. 0x4 CMP_PCLKDIV32 CMP_PCLK/32. 0x5 CMP_PCLKDIV64 CMP_PCLK/64. 0x6 RESERVED Reserved. [31:16] 2 0x4 22-23 PIO0_%s I/O control for open-drain pin PIO0_22. This pin is used for the I2C-bus SCL function. 0x058 read-write 0 0x00000000 RESERVED Reserved. Only write 0 to these bits. [5:0] INV Invert input [6:6] ENUM INPUT_NOT_INVERTED Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [7:7] I2CMODE Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000). [9:8] ENUM STANDARD_MODE Standard mode/ Fast-mode I2C. 0x0 STANDARD_IO_FUNCTIO Standard I/O functionality 0x1 FAST_MODE_PLUS_I2C Fast-mode Plus I2C 0x2 RESERVED Reserved. 0x3 RESERVED Reserved. [10:10] S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER Bypass input filter. 0x0 1_CLOCK_CYCLE 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLKDIV Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved. [15:13] ENUM CMP_PCLK CMP_PCLK. 0x0 CMP_PCLKDIV2 CMP_PCLK/2. 0x1 CMP_PCLKDIV4 CMP_PCLK/4. 0x2 CMP_PCLKDIV8 CMP_PCLK/8. 0x3 CMP_PCLKDIV16 CMP_PCLK/16. 0x4 CMP_PCLKDIV32 CMP_PCLK/32. 0x5 CMP_PCLKDIV64 CMP_PCLK/64. 0x6 RESERVED Reserved. [31:16] 1 0x4 24-24 PIO0_%s Digital I/O control for port 0 pins PIO0_24. Without glitch filter. 0x060 read-write 0 0x00000000 RESERVED Reserved. Only write 0 to these bits. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE Disable. 0 ENABLE Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER Bypass input filter. 0x0 1_CLOCK_CYCLE 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLKDIV Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved. [15:13] ENUM CMP_PCLK CMP_PCLK. 0x0 CMP_PCLKDIV2 CMP_PCLK/2. 0x1 CMP_PCLKDIV4 CMP_PCLK/4. 0x2 CMP_PCLKDIV8 CMP_PCLK/8. 0x3 CMP_PCLKDIV16 CMP_PCLK/16. 0x4 CMP_PCLKDIV32 CMP_PCLK/32. 0x5 CMP_PCLKDIV64 CMP_PCLK/64. 0x6 RESERVED Reserved. [31:16] 7 0x4 25-31 PIO0_%s PIO0_%s Digital I/O control for port 0 pins PIO0_25 to PIO0_31. With glitch filter. 0x064 read-write 0 0x00000000 RESERVED Reserved. Only write 0 to these bits. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE Disable. 0 ENABLE Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [7:7] FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_ENABLED_ Filter enabled. 0 FILTER_DISABLED_ Filter disabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER Bypass input filter. 0x0 1_CLOCK_CYCLE 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLKDIV Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved. [15:13] ENUM CMP_PCLK CMP_PCLK. 0x0 CMP_PCLKDIV2 CMP_PCLK/2. 0x1 CMP_PCLKDIV4 CMP_PCLK/4. 0x2 CMP_PCLKDIV8 CMP_PCLK/8. 0x3 CMP_PCLKDIV16 CMP_PCLK/16. 0x4 CMP_PCLKDIV32 CMP_PCLK/32. 0x5 CMP_PCLKDIV64 CMP_PCLK/64. 0x6 RESERVED Reserved. [31:16] 11 0x4 0-10 PIO1_%s Digital I/O control for port 1 pins PIO1_0 to PIO1_10. With glitch filter. 0x080 read-write 0 0x00000000 RESERVED Reserved. Only write 0 to these bits. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE Disable. 0 ENABLE Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [7:7] FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_ENABLED_ Filter enabled. 0 FILTER_DISABLED_ Filter disabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER Bypass input filter. 0x0 1_CLOCK_CYCLE 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLKDIV Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved. [15:13] ENUM CMP_PCLK CMP_PCLK. 0x0 CMP_PCLKDIV2 CMP_PCLK/2. 0x1 CMP_PCLKDIV4 CMP_PCLK/4. 0x2 CMP_PCLKDIV8 CMP_PCLK/8. 0x3 CMP_PCLKDIV16 CMP_PCLK/16. 0x4 CMP_PCLKDIV32 CMP_PCLK/32. 0x5 CMP_PCLKDIV64 CMP_PCLK/64. 0x6 RESERVED Reserved. [31:16] 21 0x4 11-31 PIO1_%s Digital I/O control for port 1 pins PIO1_11 to PIO1_31. Without glitch filter. 0x0AC read-write 0 0x00000000 RESERVED Reserved. Only write 0 to these bits. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE Disable. 0 ENABLE Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER Bypass input filter. 0x0 1_CLOCK_CYCLE 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLKDIV Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved. [15:13] ENUM CMP_PCLK CMP_PCLK. 0x0 CMP_PCLKDIV2 CMP_PCLK/2. 0x1 CMP_PCLKDIV4 CMP_PCLK/4. 0x2 CMP_PCLKDIV8 CMP_PCLK/8. 0x3 CMP_PCLKDIV16 CMP_PCLK/16. 0x4 CMP_PCLKDIV32 CMP_PCLK/32. 0x5 CMP_PCLKDIV64 CMP_PCLK/64. 0x6 RESERVED Reserved. [31:16] 14 0x4 0-13 PIO2_%s Digital I/O control for port 2 pins PIO2_0 to PIO2_13. Without glitch filter. 0x100 read-write 0 0x00000000 RESERVED Reserved. Only write 0 to these bits. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE Disable. 0 ENABLE Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER Bypass input filter. 0x0 1_CLOCK_CYCLE 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLKDIV Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved. [15:13] ENUM CMP_PCLK CMP_PCLK. 0x0 CMP_PCLKDIV2 CMP_PCLK/2. 0x1 CMP_PCLKDIV4 CMP_PCLK/4. 0x2 CMP_PCLKDIV8 CMP_PCLK/8. 0x3 CMP_PCLKDIV16 CMP_PCLK/16. 0x4 CMP_PCLKDIV32 CMP_PCLK/32. 0x5 CMP_PCLKDIV64 CMP_PCLK/64. 0x6 RESERVED Reserved. [31:16]