LPC11E6x 0.8 LPC11E6x ARM cortex-m0+ CM0PLUS r0p1 little 0 0 2 0 LPC_ 8 32 32 I2C0 I2C-bus controller I2C0 0x40000000 0 0xFFF registers I2C0 15 CONSET I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. 0x000 read-write 0x00 0xFFFFFFFF RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1:0] AA Assert acknowledge flag. [2:2] SI I2C interrupt flag. [3:3] STO STOP flag. [4:4] STA START flag. [5:5] I2EN I2C interface enable. [6:6] RESERVED Reserved. The value read from a reserved bit is not defined. [31:7] STAT I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. 0x004 read-only 0xF8 0xFFFFFFFF RESERVED These bits are unused and are always 0. [2:0] Status These bits give the actual status information about the I2C interface. [7:3] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] DAT I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. 0x008 read-write 0x00 0xFFFFFFFF Data This register holds data values that have been received or are to be transmitted. [7:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] ADR0 I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. 0x00C read-write 0x00 0xFFFFFFFF GC General Call enable bit. [0:0] Address The I2C device address for slave mode. [7:1] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] SCLH SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. 0x010 read-write 0x04 0xFFFFFFFF SCLH Count for SCL HIGH time period selection. [15:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:16] SCLL SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. 0x014 read-write 0x04 0xFFFFFFFF SCLL Count for SCL low time period selection. [15:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:16] CONCLR I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. 0x018 write-only 0 0x00000000 RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1:0] AAC Assert acknowledge Clear bit. [2:2] SIC I2C interrupt Clear bit. [3:3] RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [4:4] STAC START flag Clear bit. [5:5] I2ENC I2C interface Disable bit. [6:6] RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:7] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] MMCTRL Monitor mode control register. 0x01C read-write 0x00 0xFFFFFFFF MM_ENA Monitor mode enable. [0:0] ENUM MONITOR_MODE_DISABLE Monitor mode disabled. 0 THE_I2C_MODULE_WILL_ The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line. 1 ENA_SCL SCL output enable. [1:1] ENUM HIGH When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line. 0 NORMAL When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1] 1 MATCH_ALL Select interrupt register match. [2:2] ENUM MATCH When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned. 0 ANYADDRESS When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus. 1 RESERVED Reserved. The value read from reserved bits is not defined. [31:3] 3 0x4 1-3 ADR%s I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. 0x020 read-write 0x00 0xFFFFFFFF GC General Call enable bit. [0:0] Address The I2C device address for slave mode. [7:1] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] DATA_BUFFER Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. 0x02C read-only 0x00 0xFFFFFFFF Data This register holds contents of the 8 MSBs of the DAT shift register. [7:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] 4 0x4 0-3 MASK%s I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). 0x030 read-write 0x00 0xFFFFFFFF RESERVED Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. [0:0] MASK Mask bits. [7:1] RESERVED Reserved. The value read from reserved bits is undefined. [31:8] WWDT Windowed Watchdog Timer (WWDT) WWDT 0x40004000 0x0 0xFFF registers MOD Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. 0x000 read-write 0 0xFFFFFFFF WDEN Watchdog enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0. [0:0] ENUM STOPPED The watchdog timer is stopped. 0 RUNNING The watchdog timer is running. 1 WDRESET Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0. [1:1] ENUM INTERRUPT A watchdog timeout will not cause a chip reset. 0 WDTOF Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1. [2:2] WDINT Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. [3:3] WDPROTECT Watchdog update mode. This bit can be set once by software and is only cleared by a reset. [4:4] ENUM NOT_LOCKED The watchdog time-out value (TC) can be changed at any time. 0 LOCKED The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. 1 LOCK A 1 in this bit prevents disabling or powering down the clock source selected by bit 0 of the WDCLKSRC register and also prevents switching to a clock source that is disabled or powered down. This bit can be set once by software and is only cleared by any reset. If this bit is one and the WWDT clock source is the IRC when Deep-sleep or Power-down modes are entered, the IRC remains running thereby increasing power consumption in Deep-sleep mode and potentially preventing the part of entering Power-down mode correctly (see Section 15.7). [5:5] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] TC Watchdog timer constant register. This 24-bit register determines the time-out value. 0x004 read-write 0xFF 0xFFFFFFFF COUNT Watchdog time-out value. [23:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] FEED Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. 0x008 write-only 0 0x00000000 FEED Feed value should be 0xAA followed by 0x55. [7:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] TV Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. 0x00C read-only 0xFF 0xFFFFFFFF COUNT Counter timer value. [23:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] CLKSEL Watchdog clock select register. 0x010 read-write 0 0xFFFFFFFF CLKSEL Selects source of WDT clock [0:0] ENUM IRC IRC 0 WATCHDOG_OSCILLATOR_ Watchdog oscillator (WDOSC) 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [30:1] LOCK If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0. [31:31] WARNINT Watchdog Warning Interrupt compare value. 0x014 read-write 0 0xFFFFFFFF WARNINT Watchdog warning interrupt compare value. [9:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] WINDOW Watchdog Window compare value. 0x018 read-write 0xFFFFFF 0xFFFFFFFF WINDOW Watchdog window value. [23:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] USART0 USART0 USART0 0x40008000 0 0xFFF registers USART 21 RBR Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) 0x000 read-only 0 0x00000000 modify RBR The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO. [7:0] RESERVED Reserved [31:8] THR Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) RBR 0x000 write-only 0 0x00000000 modify THR Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it is the oldest byte in the FIFO and the transmitter is available. [7:0] RESERVED Reserved [31:8] DLL Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) RBR 0x000 read-write 0x01 0xFFFFFFFF DLLSB The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART. [7:0] RESERVED Reserved [31:8] DLM Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) 0x004 read-write 0 0xFFFFFFFF DLMSB The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART. [7:0] RESERVED Reserved [31:8] IER Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) DLM 0x004 read-write 0 0xFFFFFFFF RBRINTEN RBR Interrupt Enable. Enables the Receive Data Available interrupt. It also controls the Character Receive Time-out interrupt. [0:0] ENUM DISABLE_THE_RDA_INTE Disable the RDA interrupt. 0 ENABLE_THE_RDA_INTER Enable the RDA interrupt. 1 THREINTEN THRE Interrupt Enable. Enables the THRE interrupt. The status of this interrupt can be read from LSR[5]. [1:1] ENUM DISABLE_THE_THRE_INT Disable the THRE interrupt. 0 ENABLE_THE_THRE_INTE Enable the THRE interrupt. 1 RLSINTEN Enables the Receive Line Status interrupt. The status of this interrupt can be read from LSR[4:1]. [2:2] ENUM DISABLE_THE_RLS_INTE Disable the RLS interrupt. 0 ENABLE_THE_RLS_INTER Enable the RLS interrupt. 1 MSINTEN Enables the Modem Status interrupt. The components of this interrupt can be read from the MSR. [3:3] ENUM DISABLE_THE_MS_INTER Disable the MS interrupt. 0 ENABLE_THE_MS_INTERR Enable the MS interrupt. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:4] ABEOINTEN Enables the end of auto-baud interrupt. [8:8] ENUM DISABLE_END_OF_AUTO_ Disable end of auto-baud Interrupt. 0 ENABLE_END_OF_AUTO_B Enable end of auto-baud Interrupt. 1 ABTOINTEN Enables the auto-baud time-out interrupt. [9:9] ENUM DISABLE_AUTO_BAUD_TI Disable auto-baud time-out Interrupt. 0 ENABLE_AUTO_BAUD_TIM Enable auto-baud time-out Interrupt. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] IIR Interrupt ID Register. Identifies which interrupt(s) are pending. 0x008 read-only 0x01 0xFFFFFFFF INTSTATUS Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]. [0:0] ENUM AT_LEAST_ONE_INTERRU At least one interrupt is pending. 0 NO_INTERRUPT_IS_PEND No interrupt is pending. 1 INTID Interrupt identification. IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other values of IER[3:1] not listed below are reserved. [3:1] ENUM 1_RECEIVE_LINE_S 1 - Receive Line Status (RLS). 0x3 2A__RECEIVE_DATA_AV 2a - Receive Data Available (RDA). 0x2 2B__CHARACTER_TIME_ 2b - Character Time-out Indicator (CTI). 0x6 3_THRE_INTERRUPT 3 - THRE Interrupt. 0x1 4_MODEM_STATUS 4 - Modem status 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:4] FIFOEN These bits are equivalent to FCR[0]. [7:6] ABEOINT End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. [8:8] ABTOINT Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. [9:9] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] FCR FIFO Control Register. Controls USART FIFO usage and modes. 0x008 write-only 0 0xFFFFFFFF FIFOEN FIFO enable [0:0] ENUM DISABLED USART FIFOs are disabled. Must not be used in the application. 0 ENABLED Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs. 1 RXFIFORES RX FIFO Reset [1:1] ENUM NO_IMPACT No impact on either of USART FIFOs. 0 CLEAR Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing. 1 TXFIFORES TX FIFO Reset [2:2] ENUM NO_IMPACT No impact on either of USART FIFOs. 0 CLEAR Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing. 1 RESERVED Reserved [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:4] RXTL RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated. [7:6] ENUM TRIGGER_LEVEL_0_1_C Trigger level 0 (1 character or 0x01). 0x0 TRIGGER_LEVEL_1_4_C Trigger level 1 (4 characters or 0x04). 0x1 TRIGGER_LEVEL_2_8_C Trigger level 2 (8 characters or 0x08). 0x2 TRIGGER_LEVEL_3_14_ Trigger level 3 (14 characters or 0x0E). 0x3 RESERVED Reserved [31:8] LCR Line Control Register. Contains controls for frame formatting and break generation. 0x00C read-write 0 0xFFFFFFFF WLS Word Length Select [1:0] ENUM 5_BIT_CHARACTER_LENG 5-bit character length. 0x0 6_BIT_CHARACTER_LENG 6-bit character length. 0x1 7_BIT_CHARACTER_LENG 7-bit character length. 0x2 8_BIT_CHARACTER_LENG 8-bit character length. 0x3 SBS Stop Bit Select [2:2] ENUM 1_STOP_BIT_ 1 stop bit. 0 2_STOP_BITS_1_5_IF_ 2 stop bits (1.5 if LCR[1:0]=00). 1 PE Parity Enable [3:3] ENUM DISABLE_PARITY_GENER Disable parity generation and checking. 0 ENABLE_PARITY_GENERA Enable parity generation and checking. 1 PS Parity Select [5:4] ENUM ODD_PARITY_NUMBER_O Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 0x0 EVEN_PARITY_NUMBER_ Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 0x1 FORCED_1_STICK_PARIT Forced 1 stick parity. 0x2 FORCED_0_STICK_PARIT Forced 0 stick parity. 0x3 BC Break Control [6:6] ENUM DISABLE_BREAK_TRANSM Disable break transmission. 0 ENABLE_BREAK_TRANSMI Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high. 1 DLAB Divisor Latch Access Bit [7:7] ENUM DISABLE_ACCESS_TO_DI Disable access to Divisor Latches. 0 ENABLE_ACCESS_TO_DIV Enable access to Divisor Latches. 1 RESERVED Reserved [31:8] MCR Modem Control Register. 0x010 read-write 0 0xFFFFFFFF DTRCTRL Source for modem output pin DTR. This bit reads as 0 when modem loopback mode is active. [0:0] RTSCTRL Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active. [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [3:2] LMS Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The DSR, CTS, DCD, and RI pins are ignored. Externally, DTR and RTS are set inactive. Internally, the upper four bits of the MSR are driven by the lower four bits of the MCR. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR. [4:4] ENUM DISABLE_MODEM_LOOPBA Disable modem loopback mode. 0 ENABLE_MODEM_LOOPBAC Enable modem loopback mode. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:5] RTSEN RTS enable [6:6] ENUM DISABLE_AUTO_RTS_FLO Disable auto-rts flow control. 0 ENABLE_AUTO_RTS_FLOW Enable auto-rts flow control. 1 CTSEN CTS enable [7:7] ENUM DISABLE_AUTO_CTS_FLO Disable auto-cts flow control. 0 ENABLE_AUTO_CTS_FLOW Enable auto-cts flow control. 1 RESERVED Reserved [31:8] LSR Line Status Register. Contains flags for transmit and receive status, including line errors. 0x014 read-only 0x60 0xFFFFFFFF modify RDR Receiver Data Ready:LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty. [0:0] ENUM RBR_IS_EMPTY_ RBR is empty. 0 RBR_CONTAINS_VALID_D RBR contains valid data. 1 OE Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost. [1:1] ENUM INACTIVE Overrun error status is inactive. 0 ACTIVE Overrun error status is active. 1 PE Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO. [2:2] ENUM INACTIVE Parity error status is inactive. 0 ACTIVE Parity error status is active. 1 FE Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO. [3:3] ENUM INACTIVE Framing error status is inactive. 0 ACTIVE Framing error status is active. 1 BI Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO. [4:4] ENUM INACTIVE Break interrupt status is inactive. 0 ACTIVE Break interrupt status is active. 1 THRE Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write. [5:5] ENUM THR_CONTAINS_VALID_D THR contains valid data. 0 THR_IS_EMPTY_ THR is empty. 1 TEMT Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data. [6:6] ENUM VALID_D THR and/or the TSR contains valid data. 0 EMPTY THR and the TSR are empty. 1 RXFE Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO. [7:7] ENUM NO_ERROR RBR contains no USART RX errors or FCR[0]=0. 0 ERRO USART RBR contains at least one USART RX error. 1 TXERR Tx Error. In smart card T=0 operation, this bit is set when the smart card has NACKed a transmitted character, one more than the number of times indicated by the TXRETRY field. [8:8] RESERVED Reserved [31:9] MSR Modem Status Register. 0x018 read-only 0 0xFFFFFFFF modify DCTS Delta CTS. Set upon state change of input CTS. Cleared on an MSR read. [0:0] ENUM NO_CHANGE_DETECTED_O No change detected on modem input, CTS. 0 STATE_CHANGE_DETECTE State change detected on modem input, CTS. 1 DDSR Delta DSR. Set upon state change of input DSR. Cleared on an MSR read. [1:1] ENUM NO_CHANGE_DETECTED_O No change detected on modem input, DSR. 0 STATE_CHANGE_DETECTE State change detected on modem input, DSR. 1 TERI Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read. [2:2] ENUM NO_CHANGE_DETECTED_O No change detected on modem input, RI. 0 LOW_TO_HIGH_TRANSITI Low-to-high transition detected on RI. 1 DDCD Delta DCD. Set upon state change of input DCD. Cleared on an MSR read. [3:3] ENUM NO_CHANGE_DETECTED_O No change detected on modem input, DCD. 0 STATE_CHANGE_DETECTE State change detected on modem input, DCD. 1 CTS Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode. [4:4] DSR Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode. [5:5] RI Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode. [6:6] DCD Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode. [7:7] RESERVED Reserved, the value read from a reserved bit is not defined. [31:8] SCR Scratch Pad Register. Eight-bit temporary storage for software. 0x01C read-write 0 0xFFFFFFFF PAD A readable, writable byte. [7:0] RESERVED Reserved [31:8] ACR Auto-baud Control Register. Contains controls for the auto-baud feature. 0x020 read-write 0 0xFFFFFFFF START This bit is automatically cleared after auto-baud completion. [0:0] ENUM AUTO_BAUD_STOP_AUTO Auto-baud stop (auto-baud is not running). 0 AUTO_BAUD_START_AUT Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. 1 MODE Auto-baud mode select bit. [1:1] ENUM MODE_0_ Mode 0. 0 MODE_1_ Mode 1. 1 AUTORESTART Start mode [2:2] ENUM NO_RESTART No restart 0 RESTART_IN_CASE_OF_T Restart in case of time-out (counter restarts at next USART Rx falling edge) 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:3] ABEOINTCLR End of auto-baud interrupt clear bit (write only accessible). [8:8] ENUM NO_IMPACT Writing a 0 has no impact. 0 CLEAR Writing a 1 will clear the corresponding interrupt in the IIR. 1 ABTOINTCLR Auto-baud time-out interrupt clear bit (write only accessible). [9:9] ENUM NO_IMPACT Writing a 0 has no impact. 0 CLEAR Writing a 1 will clear the corresponding interrupt in the IIR. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] ICR IrDA Control Register. Enables and configures the IrDA (remote control) mode. 0x024 read-write 0 0xFFFFFFFF IRDAEN IrDA mode enable [0:0] ENUM IRDA_MODE_IS_DISABLE IrDA mode is disabled, USARTn acts as a standard USART. 0 IRDA_MODE_IS_ENABLED IrDA mode is enabled. 1 IRDAINV Serial input inverter [1:1] ENUM INVERTED The serial input is not inverted. 0 NOT_INVERTED The serial input is inverted. This has no effect on the serial output. 1 FIXPULSEEN IrDA fixed pulse width mode. [2:2] ENUM DISABLED IrDA fixed pulse width mode disabled. 0 ENABLED IrDA fixed pulse width mode enabled. 1 PULSEDIV Configures the pulse width when FixPulseEn = 1. [5:3] ENUM 3_DIV_16_X_BAUD_RATE 3 / (16 x baud rate) 0x0 2_X_TPCLK 2 x TPCLK 0x1 4_X_TPCLK 4 x TPCLK 0x2 8_X_TPCLK 8 x TPCLK 0x3 16_X_TPCLK 16 x TPCLK 0x4 32_X_TPCLK 32 x TPCLK 0x5 64_X_TPCLK 64 x TPCLK 0x6 128_X_TPCLK 128 x TPCLK 0x7 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] FDR Fractional Divider Register. Generates a clock input for the baud rate divider. 0x028 read-write 0x10 0xFFFFFFFF DIVADDVAL Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate. [3:0] MULVAL Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not. [7:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] OSR Oversampling Register. Controls the degree of oversampling during each bit time. 0x02C read-write 0xF0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [0:0] OSFRAC Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875) [3:1] OSINT Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time. [7:4] FDINT In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372. [14:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:15] TER Transmit Enable Register. Turns off USART transmitter for use with software flow control. 0x030 read-write 0x80 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [6:0] TXEN When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. [7:7] RESERVED Reserved [31:8] HDEN Half duplex enable register. 0x040 read-write 0 0xFFFFFFFF HDEN Half-duplex mode enable [0:0] ENUM DISABLE_HALF_DUPLEX_ Disable half-duplex mode. 0 ENABLE_HALF_DUPLEX_M Enable half-duplex mode. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:1] SCICTRL Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. 0x048 read-write 0 0xFFFFFFFF SCIEN Smart Card Interface Enable. [0:0] ENUM SMART_CARD_INTERFACE Smart card interface disabled. 0 ASYNCHRONOUS_HALF_DU Asynchronous half duplex smart card interface is enabled. 1 NACKDIS NACK response disable. Only applicable in T=0. [1:1] ENUM ENABLED A NACK response is enabled. 0 DISABLED A NACK response is inhibited. 1 PROTSEL Protocol selection as defined in the ISO7816-3 standard. [2:2] ENUM T_EQ_0 T = 0 0 T_EQ_1 T = 1 1 RESERVED Reserved. [4:3] TXRETRY When the protocol selection T bit (above) is 0, the field controls the maximum number of retransmissions that the USART will attempt if the remote device signals NACK. When NACK has occurred this number of times plus one, the Tx Error bit in the LSR is set, an interrupt is requested if enabled, and the USART is locked until the FIFO is cleared. [7:5] XTRAGUARD When the protocol selection T bit (above) is 0, this field indicates the number of bit times (ETUs) by which the guard time after a character transmitted by the USART should exceed the nominal 2 bit times. 0xFF in this field may indicate that there is just a single bit after a character and 11 bit times/character [15:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] RS485CTRL RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. 0x04C read-write 0 0xFFFFFFFF NMMEN NMM enable. [0:0] ENUM DISABLED RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. 0 ENABLED RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt. 1 RXDIS Receiver enable. [1:1] ENUM THE_RECEIVER_IS_ENAB The receiver is enabled. 0 THE_RECEIVER_IS_DISA The receiver is disabled. 1 AADEN AAD enable. [2:2] ENUM AUTO_ADDRESS_DETECT_ Auto Address Detect (AAD) is disabled. 0 AUTO_ADDRESS_DETECT_ Auto Address Detect (AAD) is enabled. 1 SEL Select direction control pin [3:3] ENUM RTS If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control. 0 DTR If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control. 1 DCTRL Auto direction control enable. [4:4] ENUM DISABLE_AUTO_DIRECTI Disable Auto Direction Control. 0 ENABLE_AUTO_DIRECTIO Enable Auto Direction Control. 1 OINV Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. [5:5] ENUM LOW The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. 0 HIGH The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] RS485ADRMATCH RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. 0x050 read-write 0 0xFFFFFFFF ADRMATCH Contains the address match value. [7:0] RESERVED Reserved [31:8] RS485DLY RS-485/EIA-485 direction control delay. 0x054 read-write 0 0xFFFFFFFF DLY Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter. [7:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] SYNCCTRL Synchronous mode control register. 0x058 read-write 0 0xFFFFFFFF SYNC Enables synchronous mode. [0:0] ENUM DISABLED Disabled 0 ENABLED Enabled 1 CSRC Clock source select. [1:1] ENUM SYNCHRONOUS_SLAVE_MO Synchronous slave mode (SCLK in) 0 SYNCHRONOUS_MASTER_M Synchronous master mode (SCLK out) 1 FES Falling edge sampling. [2:2] ENUM RISING RxD is sampled on the rising edge of SCLK 0 FALLING RxD is sampled on the falling edge of SCLK 1 TSBYPASS Transmit synchronization bypass in synchronous slave mode. [3:3] ENUM SYNC The input clock is synchronized prior to being used in clock edge detection logic 0 NOSYNC The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability. 1 CSCEN Continuous master clock enable (used only when CSRC is 1) [4:4] ENUM SCLK_CYCLES_ONLY_WHE SCLK cycles only when characters are being sent on TxD 0 SCLK_RUNS_CONTINUOUS SCLK runs continuously (characters can be received on RxD independently from transmission on TxD) 1 SSDIS Start/stop bits [5:5] ENUM SEND_START_AND_STOP_ Send start and stop bits as in other modes. 0 DO_NOT_SEND_STARTSTOP Do not send start/stop bits. 1 CCCLR Continuous clock clear [6:6] ENUM CSCEN_IS_UNDER_SOFTW CSCEN is under software control. 0 HARDWARE_CLEARS_CSCE Hardware clears CSCEN after each character is received. 1 RESERVED Reserved. The value read from a reserved bit is not defined. [31:7] CT16B0 16-bit counter/timers CT16B0 CT16B0 0x4000C000 0 0xFFF registers CT16B0 16 IR Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. 0x000 read-write 0 0xFFFFFFFF MR0INT Interrupt flag for match channel 0. [0:0] MR1INT Interrupt flag for match channel 1. [1:1] MR2INT Interrupt flag for match channel 2. [2:2] MR3INT Interrupt flag for match channel 3. [3:3] CR0INT Interrupt flag for capture channel 0 event. [4:4] CR1INT Interrupt flag for capture channel 1 event. [5:5] CR2INT Interrupt flag for capture channel 2 event. [6:6] RESERVED Reserved [31:7] TCR Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x004 read-write 0 0xFFFFFFFF CEN Counter enable. [0:0] ENUM DISABLED The counters are disabled. 0 ENABLED The Timer Counter and Prescale Counter are enabled for counting. 1 CRST Counter reset. [1:1] ENUM NOP Do nothing. 0 RESET The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] TC Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x008 read-write 0 0xFFFFFFFF TCVAL Timer counter value. [15:0] RESERVED Reserved. [31:16] PR Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0x00C read-write 0 0xFFFFFFFF PCVAL Prescale value. [15:0] RESERVED Reserved. [31:16] PC Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x010 read-write 0 0xFFFFFFFF PC Prescale counter value. [15:0] RESERVED Reserved. [31:16] MCR Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x014 read-write 0 0xFFFFFFFF MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. [0:0] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR0R Reset on MR0: the TC will be reset if MR0 matches it. [1:1] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. [2:2] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. [3:3] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1R Reset on MR1: the TC will be reset if MR1 matches it. [4:4] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. [5:5] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. [6:6] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2R Reset on MR2: the TC will be reset if MR2 matches it. [7:7] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. [8:8] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. [9:9] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3R Reset on MR3: the TC will be reset if MR3 matches it. [10:10] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. [11:11] ENUM ENABLED Enabled 1 DISABLED Disabled 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] 4 0x4 0-3 MR%s Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x018 read-write 0 0xFFFFFFFF MATCH Timer counter match value. [15:0] RESERVED Reserved. [31:16] CCR Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x028 read-write 0 0xFFFFFFFF CAP0RE Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. [0:0] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP0FE Falling edge of capture channel 0:: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. [1:1] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP0I Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. [2:2] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP1RE Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. [3:3] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP1FE Falling edge of capture channel 1:: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. [4:4] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP1I Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. [5:5] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP2RE Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. [6:6] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP2FE Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. [7:7] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP2I Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. [8:8] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:9] 3 0x4 0-2 CR%s Capture Register. CR is loaded with the value of TC when there is an event on the CAP input. 0x02C read-only 0 0xFFFFFFFF CAP Timer counter capture value. [15:0] RESERVED Reserved. [31:16] EMR External Match Register. The EMR controls the match function and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. 0x03C read-write 0 0xFFFFFFFF EM0 External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [0:0] EM1 External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [1:1] EM2 External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. [2:2] EM3 External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. [3:3] EMC0 External Match Control 0. Determines the functionality of External Match 0. Table 267 shows the encoding of these bits. [5:4] ENUM NOP Do Nothing. 0x0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (CT16Bn_MAT0 pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. [7:6] ENUM NOP Do Nothing. 0x0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (CT16Bn_MAT0 pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. [9:8] ENUM NOP Do Nothing. 0x0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (CT16Bn_MAT0 pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. [11:10] ENUM NOP Do Nothing. 0x0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (CT16Bn_MAT0 pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] CTCR Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x070 read-write 0 0xFFFFFFFF CTM Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000. [1:0] ENUM TIMER_MODE Timer Mode. Increments every rising PCLK edge 0x0 RISING Counter Moderising edge. . TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 FALLING Counter Mode falling edge: TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 DUAL Counter Mode dual edge: TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 CIS Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Value 0x3 isreserved. [3:2] ENUM CAPTURE_CHANNEL_0 Capture channel 0. 0x0 CAPTURE_CHANNEL_1 Capture channel 1. 0x1 CAPTURE_CHANNEL_2 Capture channel 2. 0x2 ENCC Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. [4:4] SELCC Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. [7:5] ENUM CAP0RISING Rising Edge of thesignal on capture channel 0 clears the timer (if bit 4 is set). 0x0 CAP0FALLING Falling Edge of thesignal on capture channel 0 clears the timer (if bit 4 is set). 0x1 CAP1RISING Rising Edge of thesignal on capture channel 1 clears the timer (if bit 4 is set). 0x2 CAP1FALLING Falling Edge of thesignal on capture channel 1 clears the timer (if bit 4 is set). 0x3 CAP2RISING Rising Edge of thesignal on capture channel 2 clears the timer (if bit 4 is set). 0x4 CAP1FALLING Falling Edge of thesignal on capture channel 2 clears the timer (if bit 4 is set). 0x5 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] PWMC PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. 0x074 read-write 0 0xFFFFFFFF PWMEN0 PWM mode enable for channel0. [0:0] ENUM EM0 CT16Bn_MAT0 is controlled by EM0. 0 PWM PWM mode is enabled for CT16Bn_MAT0. 1 PWMEN1 PWM mode enable for channel1. [1:1] ENUM EM1 CT16Bn_MAT01 is controlled by EM1. 0 PWM PWM mode is enabled for CT16Bn_MAT1. 1 PWMEN2 PWM mode enable for channel2. [2:2] ENUM EM2 CT16Bn_MAT2 is controlled by EM2. 0 PWM PWM mode is enabled for CT16Bn_MAT2. 1 PWMEN3 PWM mode enable for channel3. [3:3] ENUM EM3 CT16Bn_MAT3 is controlled by EM3. 0 PWM PWM mode is enabled for CT16Bn_MAT3. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] CT16B1 16-bit counter/timers CT16B1 0x40010000 0 0xFFF registers CT16B1 17 CT32B0 32-bit counter/timers CT32B0 CT32B0 0x40014000 0 0xFFF registers CT32B0 18 IR Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. 0x000 read-write 0 0xFFFFFFFF MR0INT Interrupt flag for match channel 0. [0:0] MR1INT Interrupt flag for match channel 1. [1:1] MR2INT Interrupt flag for match channel 2. [2:2] MR3INT Interrupt flag for match channel 3. [3:3] CR0INT Interrupt flag for capture channel 0 event. [4:4] CR1INT Interrupt flag for capture channel 1 event. [5:5] CR2INT Interrupt flag for capture channel 2 event. [6:6] RESERVED Reserved [31:7] TCR Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x004 read-write 0 0xFFFFFFFF CEN Counter enable. [0:0] ENUM DISABLED The counters are disabled. 0 ENABLED The Timer Counter and Prescale Counter are enabled for counting. 1 CRST Counter reset. [1:1] ENUM NOP Do nothing. 0 RESET The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] TC Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x008 read-write 0 0xFFFFFFFF TCVAL Timer counter value. [31:0] PR Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0x00C read-write 0 0xFFFFFFFF PCVAL Prescaler value. [31:0] PC Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x010 read-write 0 0xFFFFFFFF PC Prescale counter value. [31:0] MCR Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x014 read-write 0 0xFFFFFFFF MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. [0:0] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR0R Reset on MR0: the TC will be reset if MR0 matches it. [1:1] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. [2:2] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. [3:3] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1R Reset on MR1: the TC will be reset if MR1 matches it. [4:4] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. [5:5] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. [6:6] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2R Reset on MR2: the TC will be reset if MR2 matches it. [7:7] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. [8:8] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. [9:9] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3R Reset on MR3: the TC will be reset if MR3 matches it. [10:10] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. [11:11] ENUM ENABLED Enabled 1 DISABLED Disabled 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] 4 0x4 0-3 MR%s Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x018 read-write 0 0xFFFFFFFF MATCH Timer counter match value. [31:0] CCR Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x028 read-write 0 0xFFFFFFFF CAP0RE Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. [0:0] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP0FE Falling edge of capture channel 0:: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. [1:1] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP0I Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. [2:2] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP1RE Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. [3:3] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP1FE Falling edge of capture channel 1:: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. [4:4] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP1I Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. [5:5] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP2RE Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. [6:6] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP2FE Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. [7:7] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP2I Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. [8:8] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:9] 3 0x4 0-2 CR%s Capture Register. CR is loaded with the value of TC when there is an event on the CAP input. 0x02C read-only 0 0xFFFFFFFF CAP Timer counter capture value. [31:0] EMR External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. 0x03C read-write 0 0xFFFFFFFF EM0 External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [0:0] EM1 External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [1:1] EM2 External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [2:2] EM3 External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [3:3] EMC0 External Match Control 0. Determines the functionality of External Match 0. [5:4] ENUM NOP Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. [7:6] ENUM NOP Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. [9:8] ENUM NOP Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. [11:10] ENUM NOP Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] CTCR Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x070 read-write 0 0xFFFFFFFF CTM Counter/Timer Mode. This field selects which rising PCLK edges can increment the Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000. [1:0] ENUM TIMER_MODE Timer Mode. Increments every rising PCLK edge 0x0 COUNTER_MODE_RISING Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 COUNTER_MODE_FALLING Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 COUNTER_MODE_DUAL_ED Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 CIS Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Value 0x3 is reserved. [3:2] ENUM CAPTURE_CHANNEL_0 Capture channel 0. 0x0 CAPTURE_CHANNEL_1 Capture channel 1. 0x1 CAPTURE_CHANNEL_2 Capture channel 2. 0x2 ENCC Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. [4:4] SELCC Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. [7:5] ENUM CAP0RISING Rising Edge of the signal on capture channel 0 clears the timer (if bit 4 is set). 0x0 CAP0FALLING Falling Edge of the signal on capture channel 0 clears the timer (if bit 4 is set). 0x1 CAP1RISING Rising Edge of the signal on capture channel 1 clears the timer (if bit 4 is set). 0x2 CAP1FALLING Falling Edge of the signal on capture channel 1 clears the timer (if bit 4 is set). 0x3 CAP2RISING Rising Edge of the signal on capture channel 2 clears the timer (if bit 4 is set). 0x4 CAP2FALLING Falling Edge of the signal on capture channel 2 clears the timer (if bit 4 is set). 0x5 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] PWMC PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. 0x074 read-write 0 0xFFFFFFFF PWMEN0 PWM mode enable for channel0. [0:0] ENUM EM0 CT32Bn_MAT0 is controlled by EM0. 0 PWM PWM mode is enabled for CT32Bn_MAT0. 1 PWMEN1 PWM mode enable for channel1. [1:1] ENUM EM1 CT32Bn_MAT01 is controlled by EM1. 0 PWM PWM mode is enabled for CT32Bn_MAT1. 1 PWMEN2 PWM mode enable for channel2. [2:2] ENUM EM2 CT32Bn_MAT2 is controlled by EM2. 0 PWM PWM mode is enabled for CT32Bn_MAT2. 1 PWMEN3 PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. [3:3] ENUM EM3 CT32Bn_MAT3 is controlled by EM3. 0 PWM PWM mode is enabled for CT132Bn_MAT3. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] CT32B1 32-bit counter/timers CT32B1 0x40018000 0 0xFFF registers CT32B1 19 ADC 12-bit Analog-to-Digital Converter (ADC) ADC 0x4001C000 0x0 0xFFF registers ADC_A 24 CTRL A/D Control Register. Contains the clock divide value, enable bits for each sequence and the A/D power-down bit. 0x000 read-write 0x0 0xFFFFFFFF CLKDIV The system clock is divided by this value plus one to produce the clock for the A/D converter, which should be less than or equal to 50 MHz (up to 100 MHz in 10-bit mode). Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. [7:0] RESERVED Reserved. [9:8] LPWRMODE Select low-power ADC mode. The analog circuitry is automatically powered-down when no conversions are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is enabled. After the required start-up time, the requested conversion will be launched. Once the conversion completes, the analog-circuitry will again be powered-down provided no further conversions are pending. Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are required relatively infrequently. The penalty for using this mode is an approximately 15 ADC clock delay (30 clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger event occurs until sampling of the A/D input commences. This mode will NOT power-up the A/D if the ADC_ENA bit is low. [10:10] ENUM DISABLED Disabled. The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested. 0 ENABLED Enabled. The low-power ADC mode is enabled. 1 CAL_MODE Writing a 1 to this bit initiates a self-calibration cycle. This bit will be automatically cleared by hardware after the calibration cycle is complete. Other bits of this register may be written to concurrently with setting this bit, however once this bit has been set no further writes to this register are permitted until the full calibration cycle has ended. [30:30] RESERVED Reserved. [31:31] SEQA_CTRL A/D Conversion Sequence-A control Register: Controls triggering and channel selection for conversion sequence-A. Also specifies interrupt mode for sequence-A. 0x008 read-write 0x0 0xFFFFFFFF CHANNELS Selects which one or more of the twelve channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, A/D conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while the SEQA_ENA bit (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write. [11:0] TRIGGER Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. [14:12] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [17:15] TRIGPOL Select the polarity of the selected input trigger for this conversion sequence. [18:18] ENUM NEGATIVE_EDGE Negative edge. A negative edge launches the conversion sequence on the selected trigger input. 0 POSITIVE_EDGE Positive edge. A positive edge launches the conversion sequence on the selected trigger input. 1 SYNCBYPASS Setting this bit allows the hardware trigger input to bypass synchronization flip-flops stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode: Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode: Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period. [19:19] ENUM ENABLE_SYNCHRONIZATI Enable synchronization. The hardware trigger bypass is not enabled. 0 BYPASS_SYNCHRONIZATI Bypass synchronization. The hardware trigger bypass is enabled. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [25:20] START Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written-to to launch a conversion sequence. It will consequently always read-back as a zero. [26:26] BURST Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. [27:27] SINGLESTEP When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit. [28:28] LOWPRIO Set priority for sequence A. [29:29] ENUM LOW_PRIORITY Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost. 0 HIGH_PRIORITY High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt this sequence and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point. 1 MODE Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA requests for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below: [30:30] ENUM END_OF_CONVERSION End of conversion. The sequence A interrupt/DMA flag will be set at the end of each individual A/D conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA request if enabled. 0 END_OF_SEQUENCE End of sequence. The sequence A interrupt/DMA flag will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA request since it is assumed this register may not be utilized in this mode. 1 SEQA_ENA Sequence Enable [31:31] ENUM DISABLED Disabled. Sequence A is disabled. Sequence A triggers are ignored. If this bit is cleared while sequence A is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel. 0 ENABLED Enabled. Sequence A is enabled. 1 SEQB_CTRL A/D Conversion Sequence-B Control Register: Controls triggering and channel selection for conversion sequence-B. Also specifies interrupt mode for sequence-B. 0x00C read-write 0x0 0xFFFFFFFF CHANNELS Selects which one or more of the twelve channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, A/D conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while the SEQB_ENA bit (bit 31) is LOW. It is permissible to change this field and set bit 31 in the same write. [11:0] TRIGGER Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. [14:12] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [17:15] TRIGPOL Select the polarity of the selected input trigger for this conversion sequence. [18:18] ENUM NEGATIVE_EDGE Negative edge. A negative edge launches the conversion sequence on the selected trigger input. 0 POSITIVE_EDGE Positive edge. A positive edge launches the conversion sequence on the selected trigger input. 1 SYNCBYPASS Setting this bit allows the hardware trigger input to bypass synchronization flip-flops stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode: Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode: Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period. [19:19] ENUM ENABLE_SYNCHRONIZATI Enable synchronization. The hardware trigger bypass is not enabled. 0 BYPASS_SYNCHRONIZATI Bypass synchronization. The hardware trigger bypass is enabled. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [25:20] START Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write a 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written-to to launch a conversion sequence. It will consequently always read-back as a zero. [26:26] BURST Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other B triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. [27:27] SINGLESTEP When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit. [28:28] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [29:29] MODE Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQB_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA requests for sequence-B will be generated and which overrun conditions contribute to an overrun interrupt as described below: [30:30] ENUM END_OF_CONVERSION End of conversion. The sequence B interrupt/DMA flag will be set at the end of each individual A/D conversion performed under sequence B. This flag will mirror the DATAVALID bit in the SEQB_GDAT register. The OVERRUN bit in the SEQB_GDAT register will contribute to generation of an overrun interrupt/DMA request if enabled. 0 END_OF_SEQUENCE End of sequence. The sequence B interrupt/DMA flag will be set when the entire set of sequence B conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQB_GDAT register will NOT contribute to generation of an overrun interrupt/DMA request since it is assumed this register will not be utilized in this mode. 1 SEQB_ENA Sequence Enable [31:31] ENUM DISABLED Disabled. Sequence B is disabled. Sequence B triggers are ignored. If this bit is cleared while sequence B is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel. 0 ENABLED Enabled. Sequence B is enabled. 1 SEQA_GDAT A/D Sequence-A Global Data Register. This register contains the result of the most recent A/D conversion performed under sequence-A 0x010 read-write 0 0x00000000 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [3:0] RESULT This field contains the 12-bit A/D conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is the a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read. [15:4] THCMPRANGE Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH). [17:16] THCMPCROSS Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred. [19:18] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [25:20] CHN These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1...). [29:26] OVERRUN This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt request if the MODE bit (in SEQA_CTRL) for the corresponding sequence is set to '0' (and if the overrun interrupt is enabled). [30:30] DATAVALID This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled). [31:31] SEQB_GDAT A/D Sequence-B Global Data Register. This register contains the result of the most recent A/D conversion performed under sequence-B 0x014 read-write 0 0x00000000 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [3:0] RESULT This field contains the 12-bit A/D conversion result from the most recent conversion performed under conversion sequence associated with this register. This will be a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on V REFP. DATAVALID = 1 indicates that this result has not yet been read. [15:4] THCMPRANGE Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH). Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved. [17:16] THCMPCROSS Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. [19:18] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [25:20] CHN These bits contain the channel from which the RESULT bits were converted (e.g. 0b0000 identifies channel 0, 0b0001 channel 1...). [29:26] OVERRUN This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt request if the MODE bit (in SEQB_CTRL) for the corresponding sequence is set to 0 (and if the overrun interrupt is enabled). [30:30] DATAVALID This bit is set to 1 at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQB_CTRL) for that sequence is set to 0 (and if the interrupt is enabled). [31:31] 12 0x4 0-11 DAT[%s] DAT[%s] A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. 0x020 read-only 0 0x00000000 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [3:0] RESULT This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. [15:4] THCMPRANGE Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved. [17:16] THCMPCROSS Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. [19:18] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [25:20] CHANNEL This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc) [29:26] OVERRUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. [30:30] DATAVALID This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. [31:31] THR0_LOW A/D Low Compare Threshold Register 0 : Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. 0x050 read-write 0x0 0xFFFFFFFF THRLOW Low threshold value against which A/D results will be compared [15:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] THR1_LOW A/D Low Compare Threshold Register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. 0x054 read-write 0x0 0xFFFFFFFF THRLOW Low threshold value against which A/D results will be compared [15:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] THR0_HIGH A/D High Compare Threshold Register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. 0x058 read-write 0x0 0xFFFFFFFF THRHIGH High threshold value against which A/D results will be compared [15:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] THR1_HIGH A/D High Compare Threshold Register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. 0x05C read-write 0x0 0xFFFFFFFF THRHIGH High threshold value against which A/D results will be compared [15:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] CHAN_THRSEL A/D Channel-Threshold Select Register. Specifies which set of threshold compare registers are to be used for each channel 0x060 read-only 0x0 0xFFFFFFFF CH0_THRSEL Threshold select by channel. [0:0] ENUM THRESHOLD_0 Threshold 0. Channel 0 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 0 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH1_THRSEL Threshold select by channel. [1:1] ENUM THRESHOLD_0 Threshold 0. Channel 1 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 1 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH2_THRSEL Threshold select by channel. [2:2] ENUM THRESHOLD_0 Threshold 0. Channel 2 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 2 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH3_THRSEL Threshold select by channel. [3:3] ENUM THRESHOLD_0 Threshold 0. Channel 3 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 3 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH4_THRSEL Threshold select by channel. [4:4] ENUM THRESHOLD_0 Threshold 0. Channel 4 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 4 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH5_THRSEL Threshold select by channel. [5:5] ENUM THRESHOLD_0 Threshold 0. Channel 5 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 5 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH6_THRSEL Threshold select by channel. [6:6] ENUM THRESHOLD_0 Threshold 0. Channel 6 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 6 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH7_THRSEL Threshold select by channel. [7:7] ENUM THRESHOLD_0 Threshold 0. Channel 7 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 7 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH8_THRSEL Threshold select by channel. [8:8] ENUM THRESHOLD_0 Threshold 0. Channel 8 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 8 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH9_THRSEL Threshold select by channel. [9:9] ENUM THRESHOLD_0 Threshold 0. Channel 9 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 9 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH10_THRSEL Threshold select by channel. [10:10] ENUM THRESHOLD_0 Threshold 0. Channel 10 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 10 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH11_THRSEL Threshold select by channel. [11:11] ENUM THRESHOLD_0 Threshold 0. Channel 11 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 0 THRESHOLD_1 Threshold 1. Channel 11 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 INTEN A/D Interrupt Enable Register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. 0x064 read-write 0x0 0xFFFFFFFF SEQA_INTEN Sequence A interrupt enable. [0:0] ENUM DISABLED Disabled. The sequence A interrupt/DMA request is disabled. 0 ENABLED Enabled. The sequence A interrupt/DMA request is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register. 1 SEQB_INTEN Sequence B interrupt enable. [1:1] ENUM DISABLED Disabled. The sequence B interrupt/DMA request is disabled. 0 ENABLED Enabled. The sequence B interrupt/DMA request is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register. 1 OVR_INTEN Overrun interrupt enable. [2:2] ENUM DISABLED Disabled. The overrun interrupt is disabled. 0 ENABLED Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt request. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt request to be asserted. 1 ADCMPINTEN0 Threshold comparison interrupt enable. [4:3] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 ADCMPINTEN1 Threshold comparison interrupt enable. [6:5] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved. 0x3 ADCMPINTEN2 Threshold comparison interrupt enable. [8:7] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 ADCMPINTEN3 Threshold comparison interrupt enable. [10:9] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 ADCMPINTEN4 Threshold comparison interrupt enable. [12:11] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 ADCMPINTEN5 Threshold comparison interrupt enable. [14:13] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 ADCMPINTEN6 Threshold comparison interrupt enable. [16:15] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved. 0x3 ADCMPINTEN7 Threshold comparison interrupt enable. [18:17] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 ADCMPINTEN8 Threshold comparison interrupt enable. [20:19] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 ADCMPINTEN9 Threshold comparison interrupt enable. [22:21] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 ADCMPINTEN10 Threshold comparison interrupt enable. [24:23] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 ADCMPINTEN11 Threshold comparison interrupt enable. [26:25] ENUM DISABLED Disabled. 0x0 OUTSIDE_THRESHOLD Outside threshold. 0x1 CROSSING_THRESHOLD Crossing threshold. 0x2 RESERVED Reserved 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:27] FLAGS A/D Flags Register. Contains the four interrupt request flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). 0x068 read-only 0x0 0xFFFFFFFF THCMP0 Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [0:0] THCMP1 Threshold comparison event on Channel 1. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [1:1] THCMP2 Threshold comparison event on Channel 2. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [2:2] THCMP3 Threshold comparison event on Channel 3. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [3:3] THCMP4 Threshold comparison event on Channel 4. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [4:4] THCMP5 Threshold comparison event on Channel 5. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [5:5] THCMP6 Threshold comparison event on Channel 6. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [6:6] THCMP7 Threshold comparison event on Channel 7. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [7:7] THCMP8 Threshold comparison event on Channel 8. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [8:8] THCMP9 Threshold comparison event on Channel 9. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [9:9] THCMP10 Threshold comparison event on Channel 10. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [10:10] THCMP11 Threshold comparison event on Channel 11. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. [11:11] OVERRUN0 Mirrors the OVERRRUN status flag from the result register for A/D channel 0 [12:12] OVERRUN1 Mirrors the OVERRRUN status flag from the result register for A/D channel 1 [13:13] OVERRUN2 Mirrors the OVERRRUN status flag from the result register for A/D channel 2 [14:14] OVERRUN3 Mirrors the OVERRRUN status flag from the result register for A/D channel 3 [15:15] OVERRUN4 Mirrors the OVERRRUN status flag from the result register for A/D channel 4 [16:16] OVERRUN5 Mirrors the OVERRRUN status flag from the result register for A/D channel 5 [17:17] OVERRUN6 Mirrors the OVERRRUN status flag from the result register for A/D channel 6 [18:18] OVERRUN7 Mirrors the OVERRRUN status flag from the result register for A/D channel 7 [19:19] OVERRUN8 Mirrors the OVERRRUN status flag from the result register for A/D channel 8 [20:20] OVERRUN9 Mirrors the OVERRRUN status flag from the result register for A/D channel 9 [21:21] OVERRUN10 Mirrors the OVERRRUN status flag from the result register for A/D channel 10 [22:22] OVERRUN11 Mirrors the OVERRRUN status flag from the result register for A/D channel 11 [23:23] SEQA_OVR Mirrors the global OVERRUN status flag in the SEQA_GDAT register [24:24] SEQB_OVR Mirrors the global OVERRUN status flag in the SEQB_GDAT register [25:25] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [27:26] SEQA_INT Sequence A interrupt/DMA flag. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every A/D conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register. [28:28] SEQB_INT Sequence A interrupt/DMA flag. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every A/D conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN register. [29:29] THCMP_INT Threshold Comparison Interrupt/DMA flag. This bit will be set if any of the 12 THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the component flags in bits 11:0 are cleared via writing 1s to those bits. [30:30] OVR_INT Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers. [31:31] TRM ADC trim register. 0x06C read-write 0x00000F00 0xFFFFFFFF RESERVED Reserved. [4:0] VRANGE Reserved. [5:5] ENUM HIGH_VOLTAGE High voltage. VDDA = 2.7 V to 3.6 V. 0 LOW_VOLTAGE Low voltage. VDDA = 1.8 V to 2.7 V. 1 RESERVED Reserved. [31:6] I2C1 I2C1 0x40020000 0 0xFFF registers I2C1 10 RTC Real-Time Clock (RTC) RTC 0x40024000 0x0 0xFFF registers RTC 25 CTRL RTC control register 0x000 read-write 0xF 0xFFFFFFFF SWRESET Software reset control [0:0] ENUM NOT_IN_RESET Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. 0 IN_RESET In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared. This bit may also serve as a Power Fail Detect flag for the always-on voltage domain. 1 OFD Oscillator fail detect status. [1:1] ENUM RUN Run. The RTC oscillator is running properly. Writing a 0 has no effect. 0 FAIL Fail. RTC oscillator fail detected. Clear this flag after the following power-up. Writing a 1 clears this bit. 1 ALARM1HZ RTC 1 Hz timer alarm flag status. [2:2] ENUM NO_MATCH No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. 0 MATCH Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. 1 WAKE1KHZ RTC 1 kHz timer wake-up flag status. [3:3] ENUM RUN Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. 0 TIME_OUT Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. 1 ALARMDPD_EN RTC 1 Hz timer alarm enable for Deep power-down. [4:4] ENUM DISABLE Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. 0 ENABLE Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. 1 WAKEDPD_EN RTC 1 kHz timer wake-up enable for Deep power-down. [5:5] ENUM DISABLE Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. 0 ENABLE Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. 1 RTC1KHZ_EN RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). [6:6] ENUM DISABLE Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. 0 ENABLE Enable. The 1 kHz RTC timer is enabled. 1 RTC_EN RTC enable. [7:7] ENUM DISABLE Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register. 0 ENABLE Enable. The 1 Hz RTC clock is running and RTC operation is enabled. You must set this bit to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register. 1 RESERVED Reserved [31:8] MATCH RTC match register 0x004 read-write 0xFFFF 0xFFFFFFFF MATVAL Contains the match value against which the 1 Hz RTC timer will be compared to generate set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. [31:0] COUNT RTC counter register 0x008 read-write 0 0xFFFFFFFF VAL A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC1HZ_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC1HZ_EN bit is set. [31:0] WAKE RTC high-resolution/wake-up timer control register 0x00C read-write 0 0xFFFFFFFF VAL A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress. [15:0] RESERVED Reserved. [31:16] DMATRIGMUX DMA controller DMATRIGMUX 0x40028000 0x0 0xFFF registers 16 0x4 0-15 DMA_ITRIG_PINMUX[%s] DMA_ITRIG_PINMUX[%s] Trigger input select register for DMA channel 0. 0x000 read-write 0x1F 0xFFFFFFFF INP_N Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0 = ADC0_SEQA_IRQ 1 = ADC0_SEQB_IRQ 2 = CT16B0_MAT0 3 = CT16B1_MAT0 4 = CT32B0_MAT0 5 = CT16B1_MAT0 6 = PINT0 ( pin interrupt 0) 7 = PINT1 (pin interrupt1 ) 8 = SCT0_DMA0 9 = SCT0_DMA1 10 = SCT1_DMA0 11 = SCT1_DMA1 [4:0] RESERVED Reserved. [31:5] PMU Power Management Unit (PMU) PMU 0x40038000 0x0 0xFFF registers PCON Power control register 0x000 read-write 0x0 0xFFFFFFFF PM Power mode [2:0] ENUM DEFAULT Default. The part is in active or sleep mode. 0x0 DEEP_SLEEP Deep-sleep. ARM WFI will enter Deep-sleep mode. 0x1 POWER_DOWN Power-down. ARM WFI will enter Power-down mode. 0x2 DEEP_POWER_DOWN Deep power-down. ARM WFI will enter Deep-power down mode (ARM Cortex-M0+ core powered-down). 0x3 NODPD A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked. [3:3] RESERVED Reserved. Do not write ones to this bit. [7:4] SLEEPFLAG Sleep mode flag [8:8] ENUM ACTIVE_MODE Active mode. Read: No power-down mode entered. Part is in Active mode. Write: No effect. 0 LOW_POWER_MODE Low power mode. Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0. 1 RESERVED Reserved. Do not write ones to this bit. [10:9] DPDFLAG Deep power-down flag [11:11] ENUM NOT_DEEP_POWER_DOWN Not Deep power-down. Read: Deep power-down mode not entered. Write: No effect. 0 DEEP_POWER_DOWN Deep power-down. Read: Deep power-down mode entered. Write: Clear the Deep power-down flag. 1 RESERVED Reserved. Do not write ones to this bit. [31:12] 4 0x4 0-3 GPREG%s General purpose register 0 0x004 read-write 0x0 0xFFFFFFFF GPDATA Data retained during Deep power-down mode. [31:0] GPREG4 Deep power down control register 0x014 read-write 0x0 0xFFFFFFFF RESERVED Reserved. Do not write ones to this bit. [9:0] WAKEUPHYS WAKEUP pin hysteresis enable [10:10] ENUM DISABLE_HYSTERESIS_F Disable Hysteresis for WAKUP pin disabled. 0 ENABLE Enable. Hysteresis for WAKEUP pin enabled. 1 WAKEPAD_DISABLE WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be used for other purposes. Never set this bit if you intend to use a pin to wake up the part from Deep power-down mode. You can only disable the wake-up pin if the RTC wake-up timer is enabled and configured. Setting this bit is not necessary if Deep power-down mode is not used. [11:11] ENUM ENABLE Enable. The wake-up function is enabled on pin PIO0_16. 0 DISABLE Disable. Setting this bit disables the wake-up function on pin PIO0_16. 1 GPDATA Data retained during Deep power-down mode. [31:12] FLASHCTRL Flash controller FLASHCTRL 0x4003C000 0x0 0xFFF registers FLASH 27 FLASHCFG Flash configuration register 0x010 read-write 0 0x00000000 FLASHTIM Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access. [1:0] ENUM 1_SYSTEM_CLOCK_FLASH 1 system clock flash access time (for system clock frequencies of up to 20 MHz). 0x0 2_SYSTEM_CLOCKS_FLAS 2 system clocks flash access time (for system clock frequencies of up to 30 MHz). 0x1 RESERVED_ Reserved. 0x2 RESERVED_ Reserved. 0x3 RESERVED Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read. [31:2] FMSSTART Signature start address register 0x020 read-write 0 0xFFFFFFFF START Signature generation start address (corresponds to AHB byte address bits[20:4]). [16:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:17] FMSSTOP Signature stop-address register 0x024 read-write 0 0xFFFFFFFF STOPA Stop address for signature generation (the word specified by STOPA is included in the address range). The address is in units of memory words, not bytes. If the option bistprotection=1, bits 2:0 cannot be written and are forced to 111. [16:0] STRTBIST When this bit is written to 1, signature generation starts. At the end of signature generation, this bit is automatically cleared. [17:17] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:18] FMSW0 Signature Word 0x02C read-only 0 0x00000000 SIG 32-bit signature. [31:0] SSP0 SSP/SPI SSP0 0x40040000 0 0xFFF registers SSP0 20 CR0 Control Register 0. Selects the serial clock rate, bus type, and data size. 0x000 read-write 0 0xFFFFFFFF DSS Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. [3:0] ENUM 4_BIT_TRANSFER 4-bit transfer 0x3 5_BIT_TRANSFER 5-bit transfer 0x4 6_BIT_TRANSFER 6-bit transfer 0x5 7_BIT_TRANSFER 7-bit transfer 0x6 8_BIT_TRANSFER 8-bit transfer 0x7 9_BIT_TRANSFER 9-bit transfer 0x8 10_BIT_TRANSFER 10-bit transfer 0x9 11_BIT_TRANSFER 11-bit transfer 0xA 12_BIT_TRANSFER 12-bit transfer 0xB 13_BIT_TRANSFER 13-bit transfer 0xC 14_BIT_TRANSFER 14-bit transfer 0xD 15_BIT_TRANSFER 15-bit transfer 0xE 16_BIT_TRANSFER 16-bit transfer 0xF FRF Frame Format. [5:4] ENUM SPI SPI 0x0 TI TI 0x1 MICROWIRE Microwire 0x2 RESERVED This combination is not supported and should not be used. 0x3 CPOL Clock Out Polarity. This bit is only used in SPI mode. [6:6] ENUM LOW SPI controller maintains the bus clock low between frames. 0 HIGH SPI controller maintains the bus clock high between frames. 1 CPHA Clock Out Phase. This bit is only used in SPI mode. [7:7] ENUM FIRSTCLOCK SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. 0 SECONDCLOCK SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. 1 SCR Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). [15:8] RESERVED Reserved [31:16] CR1 Control Register 1. Selects master/slave and other modes. 0x004 read-write 0 0xFFFFFFFF LBM Loop Back Mode. [0:0] ENUM DURING_NORMAL_OPERAT During normal operation. 0 SERIAL_INPUT_IS_TAKE Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). 1 SSE SPI Enable. [1:1] ENUM DISABLED The SPI controller is disabled. 0 ENABLED The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit. 1 MS Master/Slave Mode.This bit can only be written when the SSE bit is 0. [2:2] ENUM MASTER The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. 0 SLAVE The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. 1 SOD Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO). [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DR Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. 0x008 read-write 0 0xFFFFFFFF modify DATA Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s. [15:0] RESERVED Reserved. [31:16] SR Status Register 0x00C read-only 0x00000003 0xFFFFFFFF TFE Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. [0:0] TNF Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. [1:1] RNE Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. [2:2] RFF Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. [3:3] BSY Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. [4:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] CPSR Clock Prescale Register 0x010 read-write 0 0xFFFFFFFF CPSDVSR This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. [7:0] RESERVED Reserved. [31:8] IMSC Interrupt Mask Set and Clear Register 0x014 read-write 0 0xFFFFFFFF RORIM Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. [0:0] RTIM Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). [1:1] RXIM Software should set this bit to enable interrupt when the Rx FIFO is at least half full. [2:2] TXIM Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] RIS Raw Interrupt Status Register 0x018 read-only 0x00000008 0xFFFFFFFF RORRIS This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. [0:0] RTRIS This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). [1:1] RXRIS This bit is 1 if the Rx FIFO is at least half full. [2:2] TXRIS This bit is 1 if the Tx FIFO is at least half empty. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] MIS Masked Interrupt Status Register 0x01C read-only 0 0xFFFFFFFF RORMIS This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. [0:0] RTMIS This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). [1:1] RXMIS This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. [2:2] TXMIS This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] ICR SSPICR Interrupt Clear Register 0x020 write-only 0 0x00000000 RORIC Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. [0:0] RTIC Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] IOCON I/O control (IOCON) IOCON 0x40044000 0x0 0xFFF registers 4 0x4 0-3 PIO0_%s I/O configuration for port PIO0 0x000 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE Disable. 0 ENABLE Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE Disable. 0 ENABLE Enable. Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER Bypass input filter. 0x0 1_CLOCK_CYCLE 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLKDIV Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved. [15:13] ENUM IOCONCLKDIV0 IOCONCLKDIV0. Use IOCON clock divider 0. 0x0 IOCONCLKDIV1 IOCONCLKDIV1. Use IOCON clock divider 1. 0x1 IOCONCLKDIV2 IOCONCLKDIV2 Use IOCON clock divider 2. 0x2 IOCONCLKDIV3 IOCONCLKDIV3. Use IOCON clock divider 3. 0x3 IOCONCLKDIV4 IOCONCLKDIV4. Use IOCON clock divider 4. 0x4 IOCONCLKDIV5 IOCONCLKDIV5. Use IOCON clock divider 5. 0x5 IOCONCLKDIV6 IOCONCLKDIV6. Use IOCON clock divider 6. 0x6 RESERVED Reserved. [31:16] PIO0_4 I/O configuration for open-drain pin PIO0_4 0x010 read-write 0x00000080 0xFFFFFFFF FUNC Selects pin function. [2:0] RESERVED Reserved. [7:3] I2CMODE Selects I2C mode (see Section 7.3.8). Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000). [9:8] ENUM STANDARD_MODE_FAST Standard mode/ Fast-mode I2C. 0x0 STANDARD_IO_FUNCTIO Standard I/O functionality 0x1 FAST_MODE_PLUS_I2C Fast-mode Plus I2C 0x2 RESERVED Reserved. 0x3 RESERVED Reserved. [31:10] PIO0_5 I/O configuration for open-drain pin PIO0_5 0x014 read-write 0x00000080 0xFFFFFFFF FUNC Selects pin function. [2:0] RESERVED Reserved. [7:3] I2CMODE Selects I2C mode (see Section 7.3.8). Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000). [9:8] ENUM STANDARD_MODE_FAST Standard mode/ Fast-mode I2C. 0x0 STANDARD_IO_FUNCTIO Standard I/O functionality 0x1 FAST_MODE_PLUS_I2C Fast-mode Plus I2C 0x2 RESERVED Reserved. 0x3 RESERVED Reserved. [31:10] 18 0x4 6-23 PIO0_%s I/O configuration for port PIO0 0x018 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE Disable. 0 ENABLE Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE Disable. 0 ENABLE Enable. Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER Bypass input filter. 0x0 1_CLOCK_CYCLE 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLKDIV Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved. [15:13] ENUM IOCONCLKDIV0 IOCONCLKDIV0. Use IOCON clock divider 0. 0x0 IOCONCLKDIV1 IOCONCLKDIV1. Use IOCON clock divider 1. 0x1 IOCONCLKDIV2 IOCONCLKDIV2 Use IOCON clock divider 2. 0x2 IOCONCLKDIV3 IOCONCLKDIV3. Use IOCON clock divider 3. 0x3 IOCONCLKDIV4 IOCONCLKDIV4. Use IOCON clock divider 4. 0x4 IOCONCLKDIV5 IOCONCLKDIV5. Use IOCON clock divider 5. 0x5 IOCONCLKDIV6 IOCONCLKDIV6. Use IOCON clock divider 6. 0x6 RESERVED Reserved. [31:16] 32 0x4 0-31 PIO1_%s I/O configuration for port PIO1 0x060 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE Disable. 0 ENABLE Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE Disable. 0 ENABLED Enabled. Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER Bypass input filter. 0x0 1_CLOCK_CYCLE 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLKDIV Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved. [15:13] ENUM IOCONCLKDIV0 IOCONCLKDIV0. Use IOCON clock divider 0. 0x0 IOCONCLKDIV1 IOCONCLKDIV1. Use IOCON clock divider 1. 0x1 IOCONCLKDIV2 IOCONCLKDIV2 Use IOCON clock divider 2. 0x2 IOCONCLKDIV3 IOCONCLKDIV3. Use IOCON clock divider 3. 0x3 IOCONCLKDIV4 IOCONCLKDIV4. Use IOCON clock divider 4. 0x4 IOCONCLKDIV5 IOCONCLKDIV5. Use IOCON clock divider 5. 0x5 IOCONCLKDIV6 IOCONCLKDIV6. Use IOCON clock divider 6. 0x6 RESERVED Reserved. [31:16] 2 0x4 0-1 PIO2_%s I/O configuration for port PIO2 0x0F0 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE Disable. 0 ENABLE Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE Disable. 0 ENABLED Enabled. Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER Bypass input filter. 0x0 1_CLOCK_CYCLE 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLKDIV Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved. [15:13] ENUM IOCONCLKDIV0 IOCONCLKDIV0. Use IOCON clock divider 0. 0x0 IOCONCLKDIV1 IOCONCLKDIV1. Use IOCON clock divider 1. 0x1 IOCONCLKDIV2 IOCONCLKDIV2 Use IOCON clock divider 2. 0x2 IOCONCLKDIV3 IOCONCLKDIV3. Use IOCON clock divider 3. 0x3 IOCONCLKDIV4 IOCONCLKDIV4. Use IOCON clock divider 4. 0x4 IOCONCLKDIV5 IOCONCLKDIV5. Use IOCON clock divider 5. 0x5 IOCONCLKDIV6 IOCONCLKDIV6. Use IOCON clock divider 6. 0x6 RESERVED Reserved. [31:16] 22 0x4 2-23 PIO2_%s I/O configuration for port PIO2 0x0FC read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE Disable. 0 ENABLE Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE Disable. 0 ENABLED Enabled. Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER Bypass input filter. 0x0 1_CLOCK_CYCLE 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLKDIV Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved. [15:13] ENUM IOCONCLKDIV0 IOCONCLKDIV0. Use IOCON clock divider 0. 0x0 IOCONCLKDIV1 IOCONCLKDIV1. Use IOCON clock divider 1. 0x1 IOCONCLKDIV2 IOCONCLKDIV2 Use IOCON clock divider 2. 0x2 IOCONCLKDIV3 IOCONCLKDIV3. Use IOCON clock divider 3. 0x3 IOCONCLKDIV4 IOCONCLKDIV4. Use IOCON clock divider 4. 0x4 IOCONCLKDIV5 IOCONCLKDIV5. Use IOCON clock divider 5. 0x5 IOCONCLKDIV6 IOCONCLKDIV6. Use IOCON clock divider 6. 0x6 RESERVED Reserved. [31:16] SYSCON System configuration (SYSCON) SYSCON 0x40048000 0x0 0xFFF registers BOD_WDT 26 SYSMEMREMAP System memory remap 0x000 read-write 0 0xFFFFFFFF MAP System memory remap. Value 0x3 is reserved. [1:0] ENUM BOOT_LOADER_MODE Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. 0x0 USER_RAM_MODE User RAM Mode. Interrupt vectors are re-mapped to Static RAM. 0x1 USER_FLASH_MODE User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. 0x2 RESERVED Reserved [31:2] PRESETCTRL Peripheral reset control 0x004 read-write 0 0xFFFFFFFF SSP0_RST_N SSP0 reset control [0:0] ENUM RESET Reset. Resets the SSP0 peripheral. 0 CLEAR_RESET Clear reset. SSP0 reset de-asserted. 1 I2C0_RST_N I2C0 reset control [1:1] ENUM RESET Reset. Resets the I2C0 peripheral. 0 CLEAR_RESET Clear reset. I2C0 reset de-asserted. 1 SSP1_RST_N SSP1 reset control [2:2] ENUM RESET Reset. Resets the SSP1 peripheral. 0 CLEAR_RESET Clear reset. SSP1 reset de-asserted. 1 I2C1_RST_N I2C1 reset control [3:3] ENUM RESET Reset. Resets the I2C1 peripheral. 0 CLEAR_RESET Clear reset. I2C1 reset de-asserted. 1 FRG_RST_N FRG reset control [4:4] ENUM RESET Reset. Resets the FRG peripheral. 0 CLEAR_RESET Clear reset. FRG reset de-asserted. 1 USART1_RST_N USART1 reset control [5:5] ENUM RESET Reset. Resets the USART1 peripheral. 0 CLEAR_RESET Clear reset. USART1 reset de-asserted. 1 USART2_RST_N USART2 reset control [6:6] ENUM RESET Reset. Resets the USART2 peripheral. 0 CLEAR_RESET Clear reset. USART2 reset de-asserted. 1 USART3_RST_N USART3 reset control [7:7] ENUM RESET Reset. Resets the USART3 peripheral. 0 CLEAR_RESET Clear reset. USART3 reset de-asserted. 1 USART4_RST_N USART4 reset control [8:8] ENUM RESET Reset. Resets the USART4 peripheral. 0 CLEAR_RESET Clear reset. USART4 reset de-asserted. 1 SCT0_RST_N SCT0 reset control [9:9] ENUM RESET Reset. Resets the SCT0 peripheral. 0 CLEAR_RESET Clear reset. SCT0 reset de-asserted. 1 SCT1_RST_N SCT1 reset control [10:10] ENUM RESET Reset. Resets the SCT1 peripheral. 0 CLEAR_RESET Clear reset. SCT1 reset de-asserted. 1 RESERVED Reserved [31:11] SYSPLLCTRL System PLL control 0x008 read-write 0 0xFFFFFFFF MSEL Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32 [4:0] PSEL Post divider ratio P. The division ratio is 2 x P. [6:5] ENUM P_EQ_1 P = 1 0x0 P_EQ_2 P = 2 0x1 P_EQ_4 P = 4 0x2 P_EQ_8 P = 8 0x3 RESERVED Reserved. Do not write ones to reserved bits. [31:7] SYSPLLSTAT System PLL status 0x00C read-only 0 0xFFFFFFFF LOCK PLL lock status [0:0] ENUM NO_LOCK No lock. PLL not locked 0 LOCK Lock. PLL locked 1 RESERVED Reserved [31:1] RTCOSCCTRL RTC oscillator 32 kHz output control 0x01C read-write 0x1 0xFFFFFFFF RTCOSCEN Enable the RTC 32 kHz output. [0:0] ENUM DISABLED Disabled. 32 kHz output disabled. 0 ENABLED Enabled. 32 kHz output enabled. 1 RESERVED Reserved [31:1] SYSOSCCTRL System oscillator control 0x020 read-write 0x000 0xFFFFFFFF BYPASS Bypass system oscillator [0:0] ENUM OSCILLATOR_IS_NOT_BY Oscillator is not bypassed. 0 BYPASS_ENABLED Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pin bypassing the oscillator. Use this mode when using an external clock source instead of the crystal oscillator. 1 FREQRANGE Determines frequency range for Low-power oscillator. [1:1] ENUM LOW Low. 1 - 20 MHz frequency range. 0 HIGH High. 15 - 25 MHz frequency range. 1 RESERVED Reserved [31:2] WDTOSCCTRL Watchdog oscillator control 0x024 read-write 0 0xFFFFFFFF DIVSEL Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64 [4:0] FREQSEL Select watchdog oscillator analog output frequency (Fclkana). [8:5] ENUM 0 0.6 MHz 0x1 1 1.05 MHz 0x2 1 1.4 MHz 0x3 1 1.75 MHz 0x4 2 2.1 MHz 0x5 2 2.4 MHz 0x6 2 2.7 MHz 0x7 3 3.0 MHz 0x8 3 3.25 MHz 0x9 3 3.5 MHz 0xA 3 3.75 MHz 0xB 4 4.0 MHz 0xC 4 4.2 MHz 0xD 4 4.4 MHz 0xE 4 4.6 MHz 0xF RESERVED Reserved [31:9] IRCCTRL IRC control 0x028 read-write 0x080 0xFFFFFFFF TRIM Trim value [7:0] RESERVED Reserved [31:8] SYSRSTSTAT System reset status register 0x030 read-write 0 0xFFFFFFFF POR POR reset status [0:0] ENUM NO_POR_DETECTED No POR detected 0 POR_DETECTED POR detected 1 EXTRST Status of the external RESET pin [1:1] ENUM NO_RESET_EVENT_DETEC No reset event detected 0 RESET_DETECTED Reset detected 1 WDT Status of the Watchdog reset [2:2] ENUM NO_WDT_RESET_DETECTE No WDT reset detected 0 WDT_RESET_DETECTED WDT reset detected 1 BOD Status of the Brown-out detect reset [3:3] ENUM NO_BOD_RESET_DETECTE No BOD reset detected 0 BOD_RESET_DETECTED BOD reset detected 1 SYSRST Status of the software system reset [4:4] ENUM NO_SYSTEM_RESET_DETE No System reset detected 0 SYSTEM_RESET_DETECTE System reset detected 1 RESERVED Reserved [31:5] SYSPLLCLKSEL System PLL clock source select 0x040 read-write 0 0xFFFFFFFF SEL System PLL clock source [1:0] ENUM IRC IRC 0x0 SYSTEM_OSCILLATOR System oscillator. Crystal Oscillator (SYSOSC) 0x1 RESERVED Reserved 0x2 32_KHZ_CLOCK 32 kHz clock.Select this option when the 32 kHz clock is the clock source for the main clock and select the pll input in the MAINCLKSEL register. Do not use the 32 kHz clock with the PLL. 0x3 RESERVED Reserved [31:2] SYSPLLCLKUEN System PLL clock source update enable 0x044 read-write 0x1 0xFFFFFFFF ENA Enable system PLL clock source update [0:0] ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved [31:1] MAINCLKSEL Main clock source select 0x070 read-write 0 0xFFFFFFFF SEL Clock source for main clock [1:0] ENUM IRC_OSCILLATOR IRC Oscillator 0x0 PLL_INPUT PLL input 0x1 WATCHDOG_OSCILLATOR Watchdog oscillator 0x2 PLL_OUTPUT PLL output 0x3 RESERVED Reserved [31:2] MAINCLKUEN Main clock source update enable 0x074 read-write 0x1 0xFFFFFFFF ENA Enable main clock source update [0:0] ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved [31:1] SYSAHBCLKDIV System clock divider 0x078 read-write 0x001 0xFFFFFFFF DIV System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] SYSAHBCLKCTRL System clock control 0x080 read-write 0x3F 0xFFFFFFFF SYS This bit is read-only and always reads as 1. It configures the always-on clock for the AHB, the APB bridges, the Cortex-M0 core clocks, SYSCON, reset control, SRAM0, and the PMU. Writes to this bit are ignored. [0:0] ROM Enables clock for ROM. [1:1] ENUM DISABLE Disable 0 ENABLE Enable 1 RAM0 Enables clock for Main SRAM0. [2:2] ENUM DISABLE Disable 0 ENABLE Enable 1 FLASHREG Enables clock for flash register interface. [3:3] ENUM DISABLED Disabled 0 ENABLED Enabled 1 FLASHARRAY Enables clock for flash access. [4:4] ENUM DISABLED Disabled 0 ENABLED Enabled 1 I2C0 Enables clock for I2C. [5:5] ENUM DISABLE Disable 0 ENABLE Enable 1 GPIO Enables clock for GPIO port registers. [6:6] ENUM DISABLE Disable 0 ENABLE Enable 1 CT16B0 Enables clock for 16-bit counter/timer 0. [7:7] ENUM DISABLE Disable 0 ENABLE Enable 1 CT16B1 Enables clock for 16-bit counter/timer 1. [8:8] ENUM DISABLE Disable 0 ENABLE Enable 1 CT32B0 Enables clock for 32-bit counter/timer 0. [9:9] ENUM DISABLE Disable 0 ENABLE Enable 1 CT32B1 Enables clock for 32-bit counter/timer 1. [10:10] ENUM DISABLE Disable 0 ENABLE Enable 1 SSP0 Enables clock for SSP0. [11:11] ENUM DISABLE Disable 0 ENABLE Enable 1 USART0 Enables clock for USART0. [12:12] ENUM DISABLE Disable 0 ENABLE Enable 1 ADC Enables clock for ADC. [13:13] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [14:14] WWDT Enables clock for WWDT. [15:15] ENUM DISABLE Disable 0 ENABLE Enable 1 IOCON Enables clock for I/O configuration block. [16:16] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [17:17] SSP1 Enables clock for SSP1. [18:18] ENUM DISABLE Disable 0 ENABLE Enable 1 PINT Enables clock to GPIO Pin interrupt register interface. [19:19] ENUM DISABLE Disable 0 ENABLE Enable 1 USART1 Enables clock to USART1 register interface. [20:20] ENUM DISABLE Disable 0 ENABLE Enable 1 USART2 Enables clock to USART2 register interface. [21:21] ENUM DISABLE Disable 0 ENABLE Enable 1 USART3_4 Enables clock to USART3 and USART4 register interfaces. [22:22] ENUM DISABLE Disable 0 ENABLE Enable 1 GROUP0INT Enables clock to GPIO GROUP0 interrupt register interface. [23:23] ENUM DISABLE Disable 0 ENABLE Enable 1 GROUP1INT Enables clock to GPIO GROUP1 interrupt register interface. [24:24] ENUM DISABLE Disable 0 ENABLE Enable 1 I2C1 Enables clock for I2C1. [25:25] ENUM DISABLE Disable 0 ENABLE Enable 1 RAM1 Enables clock for SRAM1 located at 0x2000 0000 to 0x2000 0800. [26:26] ENUM DISABLE Disable 0 ENABLE Enable 1 USBSRAM Enables USB SRAM/SRAM2 block located at 0x2000 4000 to 0x2000 4800. [27:27] ENUM DISABLE Disable 0 ENABLE Enable 1 CRC Enables clock for CRC. [28:28] ENUM DISABLE Disable 0 ENABLE Enable 1 DMA Enables clock for DMA. [29:29] ENUM DISABLE Disable 0 ENABLE Enable 1 RTC Enables clock for RTC register interface. [30:30] ENUM DISABLE Disable 0 ENABLE Enable 1 SCT0_1 Enables clock for SCT0 and SCT1. [31:31] ENUM DISABLE Disable 0 ENABLE Enable 1 SSP0CLKDIV SSP0 clock divider 0x094 read-write 0 0xFFFFFFFF DIV SPI0_PCLK clock divider values. 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] USART0CLKDIV USART0 clock divider 0x098 read-write 0 0xFFFFFFFF DIV UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] SSP1CLKDIV SSP1 clock divider 0x09C read-write 0x0000 0xFFFFFFFF DIV SSP1_PCLK clock divider values 0: Disable SSP1_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] FRGCLKDIV Clock divider for the common fractional baud rate generator of USART1, USART2, USART3, USART4 0x0A0 read-write 0 0xFFFFFFFF DIV USART fractional baud rate generator clock divider values. 0: Clock disabled. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] CLKOUTSEL CLKOUT clock source select 0x0E0 read-write 0 0xFFFFFFFF SEL CLKOUT clock source [1:0] ENUM IRC_OSCILLATOR IRC oscillator 0x0 CRYSTAL_OSCILLATOR Crystal oscillator (SYSOSC) 0x1 WATCHDOG_OSCILLATOR Watchdog oscillator 0x2 MAIN_CLOCK Main clock 0x3 RESERVED Reserved [31:2] CLKOUTUEN CLKOUT clock source update enable 0x0E4 read-write 0 0xFFFFFFFF ENA Enable CLKOUT clock source update [0:0] ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved [31:1] CLKOUTDIV CLKOUT clock divider 0x0E8 read-write 0 0xFFFFFFFF DIV CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] UARTFRGDIV USART fractional generator divider value 0x0F0 read-write 0 0xFFFFFFFF DIV Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator. [7:0] RESERVED Reserved [31:8] UARTFRGMULT USART fractional generator multiplier value 0x0F4 read-write 0 0xFFFFFFFF MULT Numerator of the fractional divider. MULT is equal to the programmed value. [7:0] RESERVED Reserved [31:8] EXTTRACECMD External trace buffer command register 0x0FC read-write 0 0xFFFFFFFF START Trace start command. Writing a one to this bit sets the TSTART signal to the MTB to HIGH and starts tracing if the TSTARTEN bit in the MTB master register is set to one as well. [0:0] STOP Trace stop command. Writing a one to this bit sets the TSTOP signal in the MTB to HIGH and stops tracing if the TSTOPEN bit in the MTB master register is set to one as well. [1:1] RESERVED Reserved [31:2] PIOPORCAP0 POR captured PIO status 0 0x100 read-only 0 0x00000000 PIOSTAT State of PIO0_23 through PIO0_0 at power-on reset [23:0] RESERVED Reserved [31:24] PIOPORCAP1 POR captured PIO status 1 0x104 read-only 0 0x00000000 PIOSTAT State of PIO1_31 through PIO1_0 at power-on reset [31:0] PIOPORCAP2 POR captured PIO status 1 0x108 read-only 0 0x00000000 PIOSTAT State of PIO2_23 through PIO2_0 at power-on reset [23:0] IOCONCLKDIV6 Peripheral clock to the IOCON block for programmable glitch filter 0x134 read-write 0x00000000 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] IOCONCLKDIV5 Peripheral clock to the IOCON block for programmable glitch filter 0x138 read-write 0x00000000 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] IOCONCLKDIV4 Peripheral clock to the IOCON block for programmable glitch filter 0x13C read-write 0x00000000 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] IOCONCLKDIV3 Peripheral clock to the IOCON block for programmable glitch filter 0x140 read-write 0x00000000 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] IOCONCLKDIV2 Peripheral clock to the IOCON block for programmable glitch filter 0x144 read-write 0x00000000 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] IOCONCLKDIV1 Peripheral clock to the IOCON block for programmable glitch filter 0x148 read-write 0x00000000 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] IOCONCLKDIV0 Peripheral clock to the IOCON block for programmable glitch filter 0x14C read-write 0x00000000 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] BODCTRL Brown-Out Detect 0x150 read-write 0 0xFFFFFFFF BODRSTLEV BOD reset level [1:0] ENUM LEVEL_0 Level 0. 0x0 LEVEL_1 Level 1. 0x1 LEVEL_2 Level 2. 0x2 LEVEL_3 Level 3. 0x3 BODINTVAL BOD interrupt level [3:2] ENUM RESERVED Reserved. 0x0 RESERVED Reserved 0x1 LEVEL_2 Level 2. 0x2 LEVEL_3 Level 3. 0x3 BODRSTENA BOD reset enable [4:4] ENUM DISABLE_RESET_FUNCTI Disable reset function. 0 ENABLE_RESET_FUNCTIO Enable reset function. 1 RESERVED Reserved [31:5] SYSTCKCAL System tick counter calibration 0x154 read-write 0 0x00000000 CAL System tick timer calibration value [25:0] RESERVED Reserved [31:26] IRQLATENCY IRQ delay. Allows trade-off between interrupt latency and determinism. 0x170 read-write 0x00000010 0xFFFFFFFF LATENCY 8-bit latency value [7:0] RESERVED Reserved [31:8] NMISRC NMI Source Control 0x174 read-write 0 0xFFFFFFFF IRQN The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1. See Table 6 for the list of interrupt sources and their IRQ numbers. [4:0] RESERVED Reserved [30:5] NMIEN Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0. [31:31] 8 0x4 0-7 PINTSEL%s GPIO Pin Interrupt Select register 0 0x178 read-write 0 0xFFFFFFFF INTPIN Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63. [5:0] RESERVED Reserved [31:6] STARTERP0 Start logic 0 interrupt wake-up enable register 0 0x204 read-write 0 0xFFFFFFFF PINT0 Pin interrupt 0 wake-up [0:0] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT1 Pin interrupt 1 wake-up [1:1] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT2 Pin interrupt 2 wake-up [2:2] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT3 Pin interrupt 3 wake-up [3:3] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT4 Pin interrupt 4 wake-up [4:4] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT5 Pin interrupt 5 wake-up [5:5] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT6 Pin interrupt 6 wake-up [6:6] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT7 Pin interrupt 7 wake-up [7:7] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved [31:8] STARTERP1 Start logic 1 interrupt wake-up enable register 1 0x214 read-write 0 0xFFFFFFFF RTCINT RTC interrupt wake-up [12:12] ENUM DISABLED Disabled 0 ENABLED Enabled 1 WWDT_BODINT Combined WWDT interrupt or Brown Out Detect (BOD) interrupt wake-up [13:13] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved [18:14] RESERVED Reserved [19:19] GROUP0INT GPIO GROUP0 interrupt wake-up [20:20] ENUM DISABLED Disabled 0 ENABLED Enabled 1 GROUP1INT GPIO GROUP1 interrupt wake-up [21:21] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved. [22:22] USART1_4 Combined USART1 and USART4 interrupt wake-up [23:23] ENUM DISABLED Disabled 0 ENABLED Enabled 1 USART2_3 Combined USART2 and USART3 interrupt wake-up [24:24] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PDSLEEPCFG Power-down states in deep-sleep mode 0x230 read-write 0 0x00000000 BOD_PD BOD power-down control for Deep-sleep and Power-down mode [3:3] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 RESERVED Reserved. [5:4] WDTOSC_PD Watchdog oscillator power-down control for Deep-sleep and Power-down mode [6:6] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 RESERVED Reserved [31:7] PDAWAKECFG Power-down states for wake-up from deep-sleep 0x234 read-write 0 0x00000000 IRCOUT_PD IRC oscillator output wake-up configuration [0:0] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 IRC_PD IRC oscillator power-down wake-up configuration [1:1] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 FLASH_PD Flash wake-up configuration [2:2] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 BOD_PD BOD wake-up configuration [3:3] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 ADC_PD ADC wake-up configuration [4:4] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 SYSOSC_PD Crystal oscillator wake-up configuration [5:5] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 WDTOSC_PD Watchdog oscillator wake-up configuration [6:6] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 SYSPLL_PD System PLL wake-up configuration [7:7] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 RESERVED Reserved [8:8] RESERVED Reserved. Always write this bit as 0. [9:9] RESERVED Reserved [10:10] RESERVED Reserved. This bit must be set to one in Run mode. [11:11] RESERVED Reserved. [12:12] TEMPSENSE_PD Temperature sensor wake-up configuration [13:13] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved [31:14] PDRUNCFG Power configuration register 0x238 read-write 0 0x00000000 IRCOUT_PD IRC oscillator output power-down [0:0] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 IRC_PD IRC oscillator power-down [1:1] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 FLASH_PD Flash power-down [2:2] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 BOD_PD BOD power-down [3:3] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 ADC_PD ADC power-down [4:4] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SYSOSC_PD Crystal oscillator power-down. After power-up, add a software delay of approximately 500 us before using. [5:5] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 WDTOSC_PD Watchdog oscillator power-down [6:6] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SYSPLL_PD System PLL power-down [7:7] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved [8:8] RESERVED Reserved. Always write this bit as 0. [9:9] RESERVED Reserved [10:10] RESERVED Reserved. This bit must be set to one in Run mode. [11:11] RESERVED Reserved. [12:12] TEMPSENSE_PD Temperature sensor wake-up configuration [13:13] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved. Always write these bits as 0b11. [15:14] RESERVED Reserved [31:16] DEVICE_ID Device ID 0x3F4 read-only 0 0x00000000 DEVICEID PARTID [31:0] USART4 USART4 USART4 0x4004C000 0x0 0xFFF registers USART1_4 11 CFG USART Configuration register. Basic USART configuration settings that typically are not changed during operation. 0x000 read-write 0 0xFFFFFFFF ENABLE USART Enable. [0:0] ENUM DISABLED Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if enabled in the INTENSET register) or a DMA transfer request because the transmitter has been reset and is therefore available. 0 ENABLED Enabled. The USART is enabled for operation. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [1:1] DATALEN Selects the data size for the USART. [3:2] ENUM 7_BIT_DATA_LENGTH 7 bit Data length. 0x0 8_BIT_DATA_LENGTH 8 bit Data length. 0x1 9_BIT_DATA_LENGTH 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. 0x2 RESERVED Reserved. 0x3 PARITYSEL Selects what type of parity is used by the USART. [5:4] ENUM NO_PARITY No parity. 0x0 RESERVED Reserved. 0x1 EVEN_PARITY Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. 0x2 ODD_PARITY Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. 0x3 STOPLEN Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. [6:6] ENUM 1_STOP_BIT 1 stop bit. 0 2_STOP_BITS 2 stop bits. This setting should only be used for asynchronous communication. 1 MODE32K Selects standard or 32 kHz clocking mode. [7:7] ENUM STANDARD UART uses standard clocking. 0 32KHZ UART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [8:8] CTSEN CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. See Section 11.8.4 for more information. [9:9] ENUM NO_FLOW_CONTROL No flow control. The transmitter does not receive any automatic flow control signal. 0 FLOW_CONTROL_ENABLED Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [10:10] SYNCEN Selects synchronous or asynchronous operation. [11:11] ENUM ASYNCHRONOUS Asynchronous mode is selected. 0 SYNCHRONOUS Synchronous mode is selected. 1 CLKPOL Selects the clock polarity and sampling edge of received data in synchronous mode. [12:12] ENUM FALLING_EDGE Falling edge. Un_RXD is sampled on the falling edge of SCLK. 0 RISING_EDGE Rising edge. Un_RXD is sampled on the rising edge of SCLK. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [13:13] SYNCMST Synchronous mode Master select. [14:14] ENUM SLAVE Slave. When synchronous mode is enabled, the USART is a slave. 0 MASTER Master. When synchronous mode is enabled, the USART is a master. 1 LOOP Selects data loopback mode. [15:15] ENUM NORMAL_OPERATION Normal operation. 0 LOOPBACK_MODE Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [17:16] OETA Output Enable Turnaround time enable for RS-485 operation. [18:18] ENUM DEASSERTED Deasserted. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. 0 ASSERTED Asserted. If selected by OESEL, the Output Enable signal remains asserted for 1 character time after then end the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. 1 AUTOADDR Automatic Address matching enable. [19:19] ENUM DISABLED Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). 0 ENABLED Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. 1 OESEL Output Enable Select. [20:20] ENUM FLOW_CONTROL Flow control. The RTS signal is used as the standard flow control function. 0 OUTPUT_ENABLE Output enable. The RTS signal is taken over in order to provide an output enable signal to control an RS-485 transceiver. 1 OEPOL Output Enable Polarity. [21:21] ENUM LOW Low. If selected by OESEL, the output enable is active low. 0 HIGH High. If selected by OESEL, the output enable is active high. 1 RXPOL Receive data polarity. [22:22] ENUM NOT_CHANGED Not changed. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. 0 INVERTED Inverted. The RX signal is inverted before being used by the UART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. 1 TXPOL Transmit data polarity. [23:23] ENUM NOT_CHANGED Not changed. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. 0 INVERTED Inverted. The TX signal is inverted by the UART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:24] CTL USART Control register. USART control settings that are more likely to change during operation. 0x004 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [0:0] TXBRKEN Break Enable. [1:1] ENUM NORMAL_OPERATION Normal operation. 0 CONTINUOUS_BREAK_IS Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. 1 ADDRDET Enable address detect mode. [2:2] ENUM DISABLED Disabled. The USART presents all incoming data. 0 ENABLED Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [5:3] TXDIS Transmit Disable. [6:6] ENUM NOT_DISABLED Not disabled. USART transmitter is not disabled. 0 DISABLED Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] CC Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. [8:8] ENUM CLOCK_ON_CHARACTER Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. 0 CONTINUOUS_CLOCK Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). 1 CLRCCONRX Clear Continuous Clock. [9:9] ENUM NO_EFFECT No effect on the CC bit. 0 AUTO_CLEAR Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [15:10] AUTOBAUD Autobaud enable. [16:16] ENUM DISABLED Disabled. UART is in normal operating mode. 0 ENABLED Enabled. UART is in autobaud mode. This bit should only be set when the UART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. This bit can be cleared by software when set, but only when the UART receiver is idle. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:17] STAT USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. 0x008 read-write 0x000E 0xFFFFFFFF RXRDY Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers. [0:0] RXIDLE Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. [1:1] TXRDY Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register. [2:2] TXIDLE Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. [3:3] CTS This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. [4:4] DELTACTS This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. [5:5] TXDISSTAT Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CFG register (TXDIS = 1). [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] OVERRUNINT Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost. [8:8] RESERVED Reserved. Read value is undefined, only zero should be written. [9:9] RXBRK Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. [10:10] DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. Cleared by software. [11:11] START This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software. [12:12] FRAMERRINT Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. [13:13] PARITYERRINT Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.. [14:14] RXNOISEINT Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. [15:15] ABERR Auto-baud Error. An auto-baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto-baud time-out. [16:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:17] INTENSET Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0x00C read-write 0 0xFFFFFFFF RXRDYEN When 1, enables an interrupt when there is a received character available to be read from the RXDAT register. [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [1:1] TXRDYEN When 1, enables an interrupt when the TXDAT register is available to take another character to transmit. [2:2] TXIDLEEN When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). [3:3] RESERVED Reserved. Read value is undefined, only zero should be written. [4:4] DELTACTSEN When 1, enables an interrupt when there is a change in the state of the CTS input. [5:5] TXDISEN When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] OVERRUNEN When 1, enables an interrupt when an overrun error occurred. [8:8] RESERVED Reserved. Read value is undefined, only zero should be written. [10:9] DELTARXBRKEN When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). [11:11] STARTEN When 1, enables an interrupt when a received start bit has been detected. [12:12] FRAMERREN When 1, enables an interrupt when a framing error has been detected. [13:13] PARITYERREN When 1, enables an interrupt when a parity error has been detected. [14:14] RXNOISEEN When 1, enables an interrupt when noise is detected. [15:15] ABERREN When 1, enables an interrupt when an auto-baud error occurs. [16:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:17] INTENCLR Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. 0x010 write-only 0 0x00000000 RXRDYCLR Writing 1 clears the corresponding bit in the INTENSET register. [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [1:1] TXRDYCLR Writing 1 clears the corresponding bit in the INTENSET register. [2:2] TXIDLECLR Writing 1 clears the corresponding bit in the INTENSET register. [3:3] RESERVED Reserved. Read value is undefined, only zero should be written. [4:4] DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET register. [5:5] TXDISINTCLR Writing 1 clears the corresponding bit in the INTENSET register. [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] OVERRUNCLR Writing 1 clears the corresponding bit in the INTENSET register. [8:8] RESERVED Reserved. Read value is undefined, only zero should be written. [10:9] DELTARXBRKCLR Writing 1 clears the corresponding bit in the INTENSET register. [11:11] STARTCLR Writing 1 clears the corresponding bit in the INTENSET register. [12:12] FRAMERRCLR Writing 1 clears the corresponding bit in the INTENSET register. [13:13] PARITYERRCLR Writing 1 clears the corresponding bit in the INTENSET register. [14:14] RXNOISECLR Writing 1 clears the corresponding bit in the INTENSET register. [15:15] ABERRCLR Writing 1 clears the corresponding bit in the INTENSET register. [16:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:17] RXDAT Receiver Data register. Contains the last character received. 0x014 read-only 0 0x00000000 modify RXDAT The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings. [8:0] RESERVED Reserved, the value read from a reserved bit is not defined. [31:9] RXDATSTAT Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together. 0x018 read-only 0 0x00000000 modify RXDAT The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings. [8:0] RESERVED Reserved, the value read from a reserved bit is not defined. [12:9] FRAMERR Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. [13:13] PARITYERR Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character. [14:14] RXNOISE Received Noise flag. See description of the RXNOISEINT bit in Table 133. [15:15] RESERVED Reserved, the value read from a reserved bit is not defined. [31:16] TXDAT Transmit Data register. Data to be transmitted is written here. 0x01C read-write 0 0xFFFFFFFF TXDAT Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0. [8:0] RESERVED Reserved. Only zero should be written. [31:9] BRG Baud Rate Generator register. 16-bit integer baud rate divisor value. 0x020 read-write 0 0xFFFFFFFF BRGVAL This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function. [15:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] INTSTAT Interrupt status register. Reflects interrupts that are currently enabled. 0x024 read-only 0x0005 0xFFFFFFFF RXRDY Receiver Ready flag. [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [1:1] TXRDY Transmitter Ready flag. [2:2] TXIDLE Transmitter idle status. [3:3] RESERVED Reserved. Read value is undefined, only zero should be written. [4:4] DELTACTS This bit is set when a change in the state of the CTS input is detected. [5:5] TXDISINT Transmitter Disabled Interrupt flag. [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] OVERRUNINT Overrun Error interrupt flag. [8:8] RESERVED Reserved. Read value is undefined, only zero should be written. [10:9] DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. [11:11] START This bit is set when a start is detected on the receiver input. [12:12] FRAMERRINT Framing Error interrupt flag. [13:13] PARITYERRINT Parity Error interrupt flag. [14:14] RXNOISEINT Received Noise interrupt flag. [15:15] ABERR Auto-baud Error flag. [16:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:17] OSR Oversample selection register for asynchronous communication. 0x028 read-write 0xF 0xFFFFFFFF OSRVAL Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit. [3:0] RESERVED Reserved, the value read from a reserved bit is not defined. [31:4] ADDR Address register for automatic address matching. 0x02C read-write 0 0xFFFFFFFF ADDRESS 8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). [7:0] RESERVED Reserved, the value read from a reserved bit is not defined. [31:8] SSP1 SSP1 0x40058000 0 0xFFF registers SSP1 14 GINT0 GPIO group interrupt 0 GINT0 0x4005C000 0 0xFFF registers GINT0 8 CTRL GPIO grouped interrupt control register 0x000 read-write 0 0xFFFFFFFF INT Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. [0:0] ENUM NO_INTERRUPT_REQUEST No interrupt request is pending. 0 INTERRUPT_REQUEST_IS Interrupt request is active. 1 COMB Combine enabled inputs for group interrupt [1:1] ENUM OR_FUNCTIONALITY_A_ OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). 0 AND_FUNCTIONALITY_A AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). 1 TRIG Group interrupt trigger [2:2] ENUM EDGE_TRIGGERED Edge-triggered 0 LEVEL_TRIGGERED Level-triggered 1 RESERVED Reserved [31:3] 3 0x4 0-2 PORT_POL[%s] PORT_POL[%s] GPIO grouped interrupt port 0 polarity register 0x020 read-write 0xFFFFFFFF 0xFFFFFFFF POL0 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [0:0] POL1 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [1:1] POL2 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [2:2] POL3 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [3:3] POL4 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [4:4] POL5 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [5:5] POL6 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [6:6] POL7 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [7:7] POL8 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [8:8] POL9 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [9:9] POL10 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [10:10] POL11 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [11:11] POL12 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [12:12] POL13 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [13:13] POL14 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [14:14] POL15 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [15:15] POL16 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [16:16] POL17 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [17:17] POL18 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [18:18] POL19 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [19:19] POL20 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [20:20] POL21 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [21:21] POL22 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [22:22] POL23 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [23:23] POL24 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [24:24] POL25 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [25:25] POL26 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [26:26] POL27 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [27:27] POL28 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [28:28] POL29 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [29:29] POL30 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [30:30] POL31 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [31:31] 3 0x4 0-2 PORT_ENA[%s] PORT_ENA[%s] GPIO grouped interrupt port enable register 0x040 read-write 0 0xFFFFFFFF ENA0 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [0:0] ENA1 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [1:1] ENA2 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [2:2] ENA3 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [3:3] ENA4 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [4:4] ENA5 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [5:5] ENA6 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [6:6] ENA7 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [7:7] ENA8 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [8:8] ENA9 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [9:9] ENA10 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [10:10] ENA11 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [11:11] ENA12 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [12:12] ENA13 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [13:13] ENA14 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [14:14] ENA15 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [15:15] ENA16 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [16:16] ENA17 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [17:17] ENA18 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [18:18] ENA19 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [19:19] ENA20 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [20:20] ENA21 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [21:21] ENA22 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [22:22] ENA23 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [23:23] ENA24 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [24:24] ENA25 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [25:25] ENA26 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [26:26] ENA27 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [27:27] ENA28 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [28:28] ENA29 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [29:29] ENA30 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [30:30] ENA31 Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. [31:31] GINT1 GINT1 0x40060000 0 0xFFF registers GINT1 9 USART1 USART1 0x4006C000 0 0xFFF registers USART2 USART2 0x40070000 0 0xFFF registers USART2_3 12 USART3 USART3 0x40074000 0 0xFFF registers CRC Cyclic Redundancy Check (CRC) engine CRC 0x50000000 0x0 0xFFF registers MODE CRC mode register 0x00 read-write 0x00000000 0xFFFFFFFF CRC_POLY CRC polynom: 1X= CRC-32 polynomial 01= CRC-16 polynomial 00= CRC-CCITT polynomial [1:0] BIT_RVS_WR Data bit order: 1= Bit order reverse for CRC_WR_DATA (per byte) 0= No bit order reverse for CRC_WR_DATA (per byte) [2:2] CMPL_WR Data complement: 1= 1's complement for CRC_WR_DATA 0= No 1's complement for CRC_WR_DATA [3:3] BIT_RVS_SUM CRC sum bit order: 1= Bit order reverse for CRC_SUM 0= No bit order reverse for CRC_SUM [4:4] CMPL_SUM CRC sum complement: 1= 1's complement for CRC_SUM 0=No 1's complement for CRC_SUM [5:5] Reserved Always 0 when read [31:6] SEED CRC seed register 0x04 read-write 0x0000FFFF 0xFFFFFFFF CRC_SEED A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses. [31:0] SUM CRC checksum register 0x08 read-only 0x0000FFFF 0xFFFFFFFF CRC_SUM The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. [31:0] WR_DATA CRC data register SUM 0x08 write-only 0 0x00000000 CRC_WR_DATA Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions. [31:0] DMA DMA controller DMA 0x50004000 0x0 0xFFF registers DMA 28 CTRL DMA control. 0x000 read-write 0 0xFFFFFFFF ENABLE DMA controller master enable. [0:0] ENUM DISABLED Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled. 0 ENABLED Enabled. The DMA controller is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:1] INTSTAT Interrupt status. 0x004 read-only 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [0:0] ACTIVEINT Summarizes whether any enabled interrupts are pending. [1:1] ENUM NOT_PENDING Not pending. No enabled interrupts are pending. 0 PENDING Pending. At least one enabled interrupt is pending. 1 ACTIVEERRINT Summarizes whether any error interrupts are pending. [2:2] ENUM NOT_PENDING Not pending. No error interrupts are pending. 0 PENDING Pending. At least one error interrupt is pending. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:3] SRAMBASE SRAM address of the channel configuration table. 0x008 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [9:0] OFFSET Address of the beginning of the DMA descriptor table. The table must begin on a 1 kB boundary. Boundary needed for 18 channel DMA configuration: 512 bytes (bottom 9 bits = 0) [31:10] ENABLESET0 Channel Enable read and Set for all DMA channels. 0x020 read-write 0 0xFFFFFFFF ENA Enable for DMA channels 15:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled. [15:0] RESERVED Reserved. [31:16] ENABLECLR0 Channel Enable Clear for all DMA channels. 0x028 write-only 0 0x00000000 CLR Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. [15:0] ACTIVE0 Channel Active status for all DMA channels. 0x030 read-only 0 0xFFFFFFFF ACT Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active. [15:0] RESERVED Reserved. [31:16] BUSY0 Channel Busy status for all DMA channels. 0x038 read-only 0 0xFFFFFFFF BSY Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy. [15:0] RESERVED Reserved. [31:16] ERRINT0 Error Interrupt status for all DMA channels. 0x040 read-write 0 0xFFFFFFFF ERR Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active. [15:0] RESERVED Reserved. [31:18] INTENSET0 Interrupt Enable read and Set for all DMA channels. 0x048 read-write 0 0xFFFFFFFF INTEN Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. [15:0] RESERVED Reserved. [31:16] INTENCLR0 Interrupt Enable Clear for all DMA channels. 0x050 write-only 0 0x00000000 CLR Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. [15:0] RESERVED Reserved. [31:16] INTA0 Interrupt A status for all DMA channels. 0x058 read-write 0 0xFFFFFFFF IA Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. [15:0] RESERVED Reserved. [31:16] INTB0 Interrupt B status for all DMA channels. 0x060 read-write 0 0xFFFFFFFF IB Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. [15:0] RESERVED Reserved. [31:16] SETVALID0 Set ValidPending control bits for all DMA channels. 0x068 write-only 0 0x00000000 SV SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n. [15:0] RESERVED Reserved. [31:16] SETTRIG0 Set Trigger control bits for all DMA channels. 0x070 write-only 0 0x00000000 TRIG Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. [15:0] RESERVED Reserved. [31:16] ABORT0 Channel Abort control for all DMA channels. 0x078 write-only 0 0x00000000 AORTCTRL Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. [15:0] RESERVED Reserved. [31:16] 16 0x10 0-15 CFG%s Configuration register for DMA channel 0. 0x400 read-write 0 0x00000000 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. [0:0] ENUM DISABLED Disabled. Peripheral DMA requests are disabled. 0 ENABLED Enabled. Peripheral DMA requests are enabled. 1 HWTRIGEN Hardware Triggering Enable for this channel. [1:1] ENUM DISABLED Disabled. Hardware triggering is not used. 0 ENABLED Enabled. Use hardware triggering. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [3:2] TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. [4:4] ENUM ACTIVE_LOW__FALLING Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. 0 ACTIVE_HIGH__RISING Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. 1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. [5:5] ENUM EDGE Edge. Hardware trigger is edge triggered. 0 LEVEL Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. 1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. [6:6] ENUM SINGLE_TRANSFER Single transfer. Hardware trigger causes a single transfer. 0 BURST_TRANSFER Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. [11:8] RESERVED Reserved. Read value is undefined, only zero should be written. [13:12] SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. [14:14] ENUM DISABLED Disabled. Source burst wrapping is not enabled for this DMA channel. 0 ENABLED Enabled. Source burst wrapping is enabled for this DMA channel. 1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. [15:15] ENUM DISABLED Disabled. Destination burst wrapping is not enabled for this DMA channel. 0 ENABLED Enabled. Destination burst wrapping is enabled for this DMA channel. 1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority. [17:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:18] 16 0x10 0-15 CTLSTAT%s Control and status register for DMA channel 0. 0x404 read-only 0 0x00000000 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. [0:0] ENUM NO_EFFECT_ON_DMA_OPE No effect on DMA operation. 0 VALID_PENDING Valid pending. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [1:1] TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. [2:2] ENUM NOT_TRIGGERED Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. 0 TRIGGERED Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:3] 16 0x10 0-15 XFERCFG%s Transfer configuration register for DMA channel 0. 0x408 read-write 0 0x00000000 CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. [0:0] ENUM NOT_VALID Not valid. The current channel descriptor is not considered valid. 0 VALID Valid. The current channel descriptor is considered valid. 1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. [1:1] ENUM DISABLED Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. 0 ENABLED Enabled. Reload the channels' control structure when the current descriptor is exhausted. 1 SWTRIG Software Trigger. [2:2] ENUM WHEN_WRITTEN_BY_SOFT When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. 0 WHEN_WRITTEN_BY_SOFT When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. 1 CLRTRIG Clear Trigger. [3:3] ENUM NOT_CLEARED Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. 0 CLEARED Cleared. The trigger is cleared when this descriptor is exhausted. 1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. [4:4] ENUM NO_EFFECT No effect. 0 SET Set. The INTA flag for this channel will be set when the current descriptor is exhausted. 1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. [5:5] ENUM NO_EFFECT No effect. 0 SET Set. The INTB flag for this channel will be set when the current descriptor is exhausted. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [7:6] WIDTH Transfer width used for this DMA channel. [9:8] ENUM 8_BIT_TRANSFERS 8-bit transfers are performed (8-bit source reads and destination writes). 0x0 16_BIT_TRANSFERS 16-bit transfers are performed (16-bit source reads and destination writes). 0x1 32_BIT_TRANSFERS 32-bit transfers are performed (32-bit source reads and destination writes). 0x2 RESERVED Reserved setting, do not use. 0x3 RESERVED Reserved. Read value is undefined, only zero should be written. [11:10] SRCINC Determines whether the source address is incremented for each DMA transfer. [13:12] ENUM NO_INCREMENT No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. 0x0 1_X_WIDTH 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. 0x1 2_X_WIDTH 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. 0x2 4_X_WIDTH 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. 0x3 DSTINC Determines whether the destination address is incremented for each DMA transfer. [15:14] ENUM NO_INCREMENT No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. 0x0 1_X_WIDTH 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. 0x1 2_X_WIDTH 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. 0x2 4_X_WIDTH 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. 0x3 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed. [25:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:26] SCT0 State Configurable Timers (SCTimer/PWM) SCT0 0x5000C000 0x0 0xFFF registers SCT0_1 13 CONFIG SCT configuration register 0x000 read-write 0x00007E00 0xFFFFFFFF UNIFY SCT operation [0:0] ENUM THE_SCT_OPERATES_AS The SCT operates as two 16-bit counters named L and H. 0 THE_SCT_OPERATES_AS The SCT operates as a unified 32-bit counter. 1 CLKMODE SCT clock mode [2:1] ENUM THE_BUS_CLOCK_CLOCKS The bus clock clocks the SCT and prescalers. 0x0 THE_SCT_CLOCK_IS_THE The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode. 0x1 THE_INPUT_SELECTED_B The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode. 0x2 PRESCALED_SCT_INPUT Prescaled SCT input. The SCT and prescalers are clocked by the input edge selected by the CKSEL field. In this mode, most of the SCT is clocked by the (selected polarity of the) input. The outputs are switched synchronously to the input clock. The input clock rate must be at least half the system clock rate and can the same or faster than the system clock. 0x3 CKSEL SCT clock select [6:3] ENUM RISING_EDGES_ON_INPU Rising edges on input 0. 0x0 FALLING_EDGES_ON_INP Falling edges on input 0. 0x1 RISING_EDGES_ON_INPU Rising edges on input 1. 0x2 FALLING_EDGES_ON_INP Falling edges on input 1. 0x3 RISING_EDGES_ON_INPU Rising edges on input 2. 0x4 FALLING_EDGES_ON_INP Falling edges on input 2. 0x5 RISING_EDGES_ON_INPU Rising edges on input 3. 0x6 FALLING_EDGES_ON_INP Falling edges on input 3. 0x7 NORELAOD_L A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. [7:7] NORELOAD_H A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. [8:8] INSYNC Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used. [16:9] AUTOLIMIT_L A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. [17:17] AUTOLIMIT_H A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. [18:18] RESERVED Reserved [31:19] CTRL SCT control register 0x004 read-write 0x00040004 0xFFFFFFFF DOWN_L This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. [0:0] STOP_L When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. [1:1] HALT_L When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation. [2:2] CLRCTR_L Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. [3:3] BIDIR_L L or unified counter direction select [4:4] ENUM THE_COUNTER_COUNTS_U The counter counts up to its limit condition, then is cleared to zero. 0 THE_COUNTER_COUNTS_U The counter counts up to its limit, then counts down to a limit condition or to 0. 1 PRE_L Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. [12:5] RESERVED Reserved [15:13] DOWN_H This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. [16:16] STOP_H When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. [17:17] HALT_H When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation. [18:18] CLRCTR_H Writing a 1 to this bit clears the H counter. This bit always reads as 0. [19:19] BIDIR_H Direction select [20:20] ENUM THE_H_COUNTER_COUNTS The H counter counts up to its limit condition, then is cleared to zero. 0 THE_H_COUNTER_COUNTS The H counter counts up to its limit, then counts down to a limit condition or to 0. 1 PRE_H Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. [28:21] RESERVED Reserved [31:29] LIMIT SCT limit register 0x008 read-write 0x00000000 0xFFFFFFFF LIMMSK_L If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5). [5:0] RESERVED Reserved. [15:6] LIMMSK_H If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21). [21:16] RESERVED Reserved. [31:22] HALT SCT halt condition register 0x00C read-write 0x00000000 0xFFFFFFFF HALTMSK_L If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5). [5:0] RESERVED Reserved. [15:6] HALTMSK_H If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21). [21:16] RESERVED Reserved. [31:22] STOP SCT stop condition register 0x010 read-write 0x00000000 0xFFFFFFFF STOPMSK_L If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5). [5:0] RESERVED Reserved. [15:6] STOPMSK_H If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21). [21:16] RESERVED Reserved. [31:22] START SCT start condition register 0x014 read-write 0x00000000 0xFFFFFFFF STARTMSK_L If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5). [5:0] RESERVED Reserved. [15:6] STARTMSK_H If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21). [21:16] RESERVED Reserved. [31:22] COUNT SCT counter register 0x040 read-write 0x00000000 0xFFFFFFFF CTR_L When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter. [15:0] CTR_H When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter. [31:16] STATE SCT state register 0x044 read-write 0x00000000 0xFFFFFFFF STATE_L State variable. [4:0] RESERVED Reserved. [15:5] STATE_H State variable. [20:16] RESERVED Reserved. [31:21] INPUT SCT input register 0x048 read-only 0x00000000 0xFFFFFFFF AIN0 Real-time status of input 0. [0:0] AIN1 Real-time status of input 1. [1:1] AIN2 Real-time status of input 2. [2:2] AIN3 Real-time status of input 3. [3:3] RESERVED Reserved. [15:4] SIN0 Input 0 state synchronized to the SCT clock. [16:16] SIN1 Input 1 state synchronized to the SCT clock. [17:17] SIN2 Input 2 state synchronized to the SCT clock. [18:18] SIN3 Input 3 state synchronized to the SCT clock. [19:19] RESERVED Reserved [31:20] REGMODE SCT match/capture registers mode register 0x04C read-write 0x00000000 0xFFFFFFFF REGMOD_L Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 4 = bit 4). 0 = registers operate as match registers. 1 = registers operate as capture registers. [4:0] RESERVED Reserved. [15:5] REGMOD_H Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 4 = bit 20). 0 = registers operate as match registers. 1 = registers operate as capture registers. [20:16] RESERVED Reserved. [31:21] OUTPUT SCT output register 0x050 read-write 0x00000000 0xFFFFFFFF OUT Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3). [3:0] RESERVED Reserved [31:4] OUTPUTDIRCTRL SCT output counter direction control register 0x054 read-write 0x00000000 0xFFFFFFFF SETCLR0 Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. [1:0] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR1 Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. [3:2] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR2 Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. [5:4] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR3 Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. [7:6] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 RESERVED Reserved [31:8] RES SCT conflict resolution register 0x058 read-write 0x00000000 0xFFFFFFFF O0RES Effect of simultaneous set and clear on output 0. [1:0] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR0 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR0 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O1RES Effect of simultaneous set and clear on output 1. [3:2] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR1 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR1 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O2RES Effect of simultaneous set and clear on output 2. [5:4] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR2 field). 0x1 CLEAR_OUTPUT_N_OR_S Clear output n (or set based on the SETCLR2 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O3RES Effect of simultaneous set and clear on output 3. [7:6] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR3 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR3 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 RESERVED Reserved [31:8] DMAREQ0 SCT DMA request 0 register 0x05C read-write 0x00000000 0xFFFFFFFF DEV_0 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5). [5:0] RESERVED Reserved [29:6] DRL0 A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers. [30:30] DRQ0 This read-only bit indicates the state of DMA Request 0 [31:31] DMAREQ1 SCT DMA request 1 register 0x060 read-write 0x00000000 0xFFFFFFFF DEV_1 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5). [5:0] RESERVED Reserved [29:6] DRL1 A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. [30:30] DRQ1 This read-only bit indicates the state of DMA Request 1. [31:31] EVEN SCT event enable register 0x0F0 read-write 0x00000000 0xFFFFFFFF IEN The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5). [5:0] RESERVED Reserved [31:6] EVFLAG SCT event flag register 0x0F4 read-write 0x00000000 0xFFFFFFFF FLAG Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5). [5:0] RESERVED Reserved [31:6] CONEN SCT conflict enable register 0x0F8 read-write 0x00000000 0xFFFFFFFF NCEN The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3). [3:0] RESERVED Reserved [31:4] CONFLAG SCT conflict flag register 0x0FC read-write 0x00000000 0xFFFFFFFF NCFLAG Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3). [3:0] RESERVED Reserved. [29:4] BUSERRL The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful. [30:30] BUSERRH The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted. [31:31] 5 0x4 0-4 MATCH%s SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0 0x100 read-write 0x00000000 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. [15:0] MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. [31:16] 5 0x4 0-4 CAP%s SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1 MATCH%s 0x100 read-write 0x00000000 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. [15:0] CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. [31:16] 5 0x4 0-4 MATCHREL%s SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0 0x200 read-write 0x00000000 0xFFFFFFFF RELOADn_L When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. [15:0] RELOADn_H When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. [31:16] 5 0x4 0-4 CAPCTRL%s SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1 MATCHREL%s 0x200 read-write 0x00000000 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5). [5:0] RESERVED Reserved. [15:6] CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21). [21:16] RESERVED Reserved. [31:22] 6 0x8 0-5 EV%s_STATE SCT event state register 0 0x300 read-write 0x00000000 0xFFFFFFFF STATEMSKn If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7). [7:0] RESERVED Reserved. [31:8] 6 0x8 0-5 EV%s_CTRL SCT event control register 0 0x304 read-write 0x00000000 0xFFFFFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. [3:0] HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. [4:4] ENUM SELECTS_THE_L_STATE Selects the L state and the L match register selected by MATCHSEL. 0 SELECTS_THE_H_STATE Selects the H state and the H match register selected by MATCHSEL. 1 OUTSEL Input/output select [5:5] ENUM SELECTS_THE_INPUTS_E Selects the inputs elected by IOSEL. 0 SELECTS_THE_OUTPUTS Selects the outputs selected by IOSEL. 1 IOSEL Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. [9:6] IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . [11:10] ENUM LOW LOW 0x0 RISE Rise 0x1 FALL Fall 0x2 HIGH HIGH 0x3 COMBMODE Selects how the specified match and I/O condition are used and combined. [13:12] ENUM OR OR. The event occurs when either the specified match or I/O condition occurs. 0x0 MATCH MATCH. Uses the specified match only. 0x1 IO IO. Uses the specified I/O condition only. 0x2 AND AND. The event occurs when the specified match and I/O condition occur simultaneously. 0x3 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. [14:14] ENUM STATEV_VALUE_IS_ADDE STATEV value is added into STATE (the carry-out is ignored). 0 STATEV_VALUE_IS_LOAD STATEV value is loaded into STATE. 1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. [19:15] MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. [20:20] DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. [22:21] ENUM DIRECTION_INDEPENDEN Direction independent. This event is triggered regardless of the count direction. 0x0 COUNTING_UP Counting up. This event is triggered only during up-counting when BIDIR = 1. 0x1 COUNTING_DOWN Counting down. This event is triggered only during down-counting when BIDIR = 1. 0x2 RESERVED Reserved [31:23] 4 0x8 0-3 OUT%s_SET SCT output 0 set register 0x500 read-write 0x00000000 0xFFFFFFFF SET A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5. [5:0] RESERVED Reserved [31:6] 4 0x8 0-3 OUT%s_CLR SCT output 0 clear register 0x504 read-write 0x00000000 0xFFFFFFFF CLR A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5. [5:0] RESERVED Reserved [31:6] SCT1 SCT1 0x5000E000 0 0xFFF registers GPIO_PORT General Purpose I/O (GPIO) GPIO 0xA0000000 0x0 0x3FFF registers 88 0x1 0-87 B[%s] B[%s] Byte pin registers 0x0000 8 read-write 0 0x00000000 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit. [0:0] 88 0x4 0-87 W[%s] W[%s] Word pin registers 0x1000 read-write 0 0x00000000 PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. [31:0] 3 0x4 0-2 DIR[%s] DIR[%s] Port Direction registers 0x2000 read-write 0 0xFFFFFFFF DIRP0 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [0:0] DIRP1 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [1:1] DIRP2 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [2:2] DIRP3 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [3:3] DIRP4 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [4:4] DIRP5 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [5:5] DIRP6 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [6:6] DIRP7 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [7:7] DIRP8 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [8:8] DIRP9 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [9:9] DIRP10 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [10:10] DIRP11 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [11:11] DIRP12 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [12:12] DIRP13 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [13:13] DIRP14 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [14:14] DIRP15 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [15:15] DIRP16 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [16:16] DIRP17 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [17:17] DIRP18 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [18:18] DIRP19 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [19:19] DIRP20 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [20:20] DIRP21 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [21:21] DIRP22 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [22:22] DIRP23 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [23:23] DIRP24 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [24:24] DIRP25 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [25:25] DIRP26 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [26:26] DIRP27 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [27:27] DIRP28 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [28:28] DIRP29 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [29:29] DIRP30 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [30:30] DIRP31 Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output. [31:31] 3 0x4 0-2 MASK[%s] MASK[%s] Port Mask register 0x2080 read-write 0 0xFFFFFFFF MASKP0 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [0:0] MASKP1 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [1:1] MASKP2 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [2:2] MASKP3 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [3:3] MASKP4 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [4:4] MASKP5 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [5:5] MASKP6 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [6:6] MASKP7 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [7:7] MASKP8 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [8:8] MASKP9 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [9:9] MASKP10 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [10:10] MASKP11 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [11:11] MASKP12 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [12:12] MASKP13 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [13:13] MASKP14 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [14:14] MASKP15 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [15:15] MASKP16 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [16:16] MASKP17 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [17:17] MASKP18 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [18:18] MASKP19 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [19:19] MASKP20 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [20:20] MASKP21 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [21:21] MASKP22 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [22:22] MASKP23 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [23:23] MASKP24 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [24:24] MASKP25 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [25:25] MASKP26 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [26:26] MASKP27 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [27:27] MASKP28 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [28:28] MASKP29 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [29:29] MASKP30 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [30:30] MASKP31 Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [31:31] 3 0x4 0-2 PIN[%s] PIN[%s] Port pin register 0x2100 read-write 0 0x00000000 PORT0 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [0:0] PORT1 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [1:1] PORT2 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [2:2] PORT3 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [3:3] PORT4 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [4:4] PORT5 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [5:5] PORT6 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [6:6] PORT7 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [7:7] PORT8 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [8:8] PORT9 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [9:9] PORT10 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [10:10] PORT11 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [11:11] PORT12 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [12:12] PORT13 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [13:13] PORT14 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [14:14] PORT15 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [15:15] PORT16 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [16:16] PORT17 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [17:17] PORT18 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [18:18] PORT19 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [19:19] PORT20 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [20:20] PORT21 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [21:21] PORT22 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [22:22] PORT23 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [23:23] PORT24 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [24:24] PORT25 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [25:25] PORT26 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [26:26] PORT27 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [27:27] PORT28 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [28:28] PORT29 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [29:29] PORT30 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [30:30] PORT31 Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [31:31] 3 0x4 0-2 MPIN[%s] MPIN[%s] Masked port register 0x2180 read-write 0 0x00000000 MPORTP0 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [0:0] MPORTP1 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [1:1] MPORTP2 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [2:2] MPORTP3 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [3:3] MPORTP4 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [4:4] MPORTP5 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [5:5] MPORTP6 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [6:6] MPORTP7 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [7:7] MPORTP8 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [8:8] MPORTP9 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [9:9] MPORTP10 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [10:10] MPORTP11 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [11:11] MPORTP12 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [12:12] MPORTP13 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [13:13] MPORTP14 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [14:14] MPORTP15 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [15:15] MPORTP16 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [16:16] MPORTP17 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [17:17] MPORTP18 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [18:18] MPORTP19 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [19:19] MPORTP20 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [20:20] MPORTP21 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [21:21] MPORTP22 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [22:22] MPORTP23 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [23:23] MPORTP24 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [24:24] MPORTP25 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [25:25] MPORTP26 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [26:26] MPORTP27 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [27:27] MPORTP28 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [28:28] MPORTP29 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [29:29] MPORTP30 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [30:30] MPORTP31 Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [31:31] 3 0x4 0-2 SET[%s] SET[%s] Write: Set port register Read: port output bits 0x2200 read-write 0 0xFFFFFFFF SETP00 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [0:0] SETP01 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [1:1] SETP02 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [2:2] SETP03 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [3:3] SETP04 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [4:4] SETP05 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [5:5] SETP06 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [6:6] SETP07 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [7:7] SETP08 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [8:8] SETP09 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [9:9] SETP010 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [10:10] SETP011 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [11:11] SETP012 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [12:12] SETP013 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [13:13] SETP014 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [14:14] SETP015 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [15:15] SETP016 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [16:16] SETP017 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [17:17] SETP018 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [18:18] SETP019 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [19:19] SETP020 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [20:20] SETP021 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [21:21] SETP022 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [22:22] SETP023 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [23:23] SETP024 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [24:24] SETP025 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [25:25] SETP026 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [26:26] SETP027 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [27:27] SETP028 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [28:28] SETP029 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [29:29] SETP030 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [30:30] SETP031 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [31:31] 3 0x4 0-2 CLR[%s] CLR[%s] Clear port 0x2280 write-only 0 0x00000000 CLRP00 Clear output bits: 0 = No operation. 1 = Clear output bit. [0:0] CLRP01 Clear output bits: 0 = No operation. 1 = Clear output bit. [1:1] CLRP02 Clear output bits: 0 = No operation. 1 = Clear output bit. [2:2] CLRP03 Clear output bits: 0 = No operation. 1 = Clear output bit. [3:3] CLRP04 Clear output bits: 0 = No operation. 1 = Clear output bit. [4:4] CLRP05 Clear output bits: 0 = No operation. 1 = Clear output bit. [5:5] CLRP06 Clear output bits: 0 = No operation. 1 = Clear output bit. [6:6] CLRP07 Clear output bits: 0 = No operation. 1 = Clear output bit. [7:7] CLRP08 Clear output bits: 0 = No operation. 1 = Clear output bit. [8:8] CLRP09 Clear output bits: 0 = No operation. 1 = Clear output bit. [9:9] CLRP010 Clear output bits: 0 = No operation. 1 = Clear output bit. [10:10] CLRP011 Clear output bits: 0 = No operation. 1 = Clear output bit. [11:11] CLRP012 Clear output bits: 0 = No operation. 1 = Clear output bit. [12:12] CLRP013 Clear output bits: 0 = No operation. 1 = Clear output bit. [13:13] CLRP014 Clear output bits: 0 = No operation. 1 = Clear output bit. [14:14] CLRP015 Clear output bits: 0 = No operation. 1 = Clear output bit. [15:15] CLRP016 Clear output bits: 0 = No operation. 1 = Clear output bit. [16:16] CLRP017 Clear output bits: 0 = No operation. 1 = Clear output bit. [17:17] CLRP018 Clear output bits: 0 = No operation. 1 = Clear output bit. [18:18] CLRP019 Clear output bits: 0 = No operation. 1 = Clear output bit. [19:19] CLRP020 Clear output bits: 0 = No operation. 1 = Clear output bit. [20:20] CLRP021 Clear output bits: 0 = No operation. 1 = Clear output bit. [21:21] CLRP022 Clear output bits: 0 = No operation. 1 = Clear output bit. [22:22] CLRP023 Clear output bits: 0 = No operation. 1 = Clear output bit. [23:23] CLRP024 Clear output bits: 0 = No operation. 1 = Clear output bit. [24:24] CLRP025 Clear output bits: 0 = No operation. 1 = Clear output bit. [25:25] CLRP026 Clear output bits: 0 = No operation. 1 = Clear output bit. [26:26] CLRP027 Clear output bits: 0 = No operation. 1 = Clear output bit. [27:27] CLRP028 Clear output bits: 0 = No operation. 1 = Clear output bit. [28:28] CLRP029 Clear output bits: 0 = No operation. 1 = Clear output bit. [29:29] CLRP030 Clear output bits: 0 = No operation. 1 = Clear output bit. [30:30] CLRP031 Clear output bits: 0 = No operation. 1 = Clear output bit. [31:31] 3 0x4 0-2 NOT[%s] NOT[%s] Toggle port 0x2300 write-only 0 0x00000000 NOTP00 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [0:0] NOTP01 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [1:1] NOTP02 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [2:2] NOTP03 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [3:3] NOTP04 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [4:4] NOTP05 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [5:5] NOTP06 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [6:6] NOTP07 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [7:7] NOTP08 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [8:8] NOTP09 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [9:9] NOTP010 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [10:10] NOTP011 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [11:11] NOTP012 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [12:12] NOTP013 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [13:13] NOTP014 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [14:14] NOTP015 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [15:15] NOTP016 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [16:16] NOTP017 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [17:17] NOTP018 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [18:18] NOTP019 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [19:19] NOTP020 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [20:20] NOTP021 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [21:21] NOTP022 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [22:22] NOTP023 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [23:23] NOTP024 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [24:24] NOTP025 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [25:25] NOTP026 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [26:26] NOTP027 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [27:27] NOTP028 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [28:28] NOTP029 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [29:29] NOTP030 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [30:30] NOTP031 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [31:31] PINT Pin interrupt and pattern match (PINT) PINT 0xA0004000 0x0 0xFFF registers PIN_INT0 0 PIN_INT1 1 PIN_INT2 2 PIN_INT3 3 PIN_INT4 4 PIN_INT5 5 PIN_INT6 6 PIN_INT7 7 ISEL Pin Interrupt Mode register 0x000 read-write 0 0xFFFFFFFF PMODE0 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [0:0] PMODE1 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [1:1] PMODE2 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [2:2] PMODE3 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [3:3] PMODE4 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [4:4] PMODE5 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [5:5] PMODE6 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [6:6] PMODE7 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [7:7] RESERVED Reserved. [31:8] IENR Pin interrupt level or rising edge interrupt enable register 0x004 read-write 0 0xFFFFFFFF ENRL0 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [0:0] ENRL1 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [1:1] ENRL2 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [2:2] ENRL3 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [3:3] ENRL4 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [4:4] ENRL5 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [5:5] ENRL6 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [6:6] ENRL7 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [7:7] RESERVED Reserved. [31:8] SIENR Pin interrupt level or rising edge interrupt set register 0x008 write-only 0 0x00000000 SETENRL0 Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. [0:0] SETENRL1 Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. [1:1] SETENRL2 Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. [2:2] SETENRL3 Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. [3:3] SETENRL4 Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. [4:4] SETENRL5 Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. [5:5] SETENRL6 Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. [6:6] SETENRL7 Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. [7:7] RESERVED Reserved. [31:8] CIENR Pin interrupt level (rising edge interrupt) clear register 0x00C write-only 0 0x00000000 CENRL0 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [0:0] CENRL1 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [1:1] CENRL2 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [2:2] CENRL3 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [3:3] CENRL4 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [4:4] CENRL5 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [5:5] CENRL6 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [6:6] CENRL7 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [7:7] RESERVED Reserved. [31:8] IENF Pin interrupt active level or falling edge interrupt enable register 0x010 read-write 0 0xFFFFFFFF ENAF0 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [0:0] ENAF1 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [1:1] ENAF2 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [2:2] ENAF3 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [3:3] ENAF4 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [4:4] ENAF5 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [5:5] ENAF6 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [6:6] ENAF7 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [7:7] RESERVED Reserved. [31:8] SIENF Pin interrupt active level or falling edge interrupt set register 0x014 write-only 0 0x00000000 SETENAF0 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [0:0] SETENAF1 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [1:1] SETENAF2 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [2:2] SETENAF3 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [3:3] SETENAF4 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [4:4] SETENAF5 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [5:5] SETENAF6 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [6:6] SETENAF7 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [7:7] RESERVED Reserved. [31:8] CIENF Pin interrupt active level or falling edge interrupt clear register 0x018 write-only 0 0x00000000 CENAF0 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [0:0] CENAF1 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [1:1] CENAF2 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [2:2] CENAF3 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [3:3] CENAF4 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [4:4] CENAF5 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [5:5] CENAF6 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [6:6] CENAF7 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [7:7] RESERVED Reserved. [31:8] RISE Pin interrupt rising edge register 0x01C read-write 0 0xFFFFFFFF RDET0 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [0:0] RDET1 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [1:1] RDET2 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [2:2] RDET3 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [3:3] RDET4 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [4:4] RDET5 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [5:5] RDET6 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [6:6] RDET7 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [7:7] RESERVED Reserved. [31:8] FALL Pin interrupt falling edge register 0x020 read-write 0 0xFFFFFFFF FDET0 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [0:0] FDET1 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [1:1] FDET2 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [2:2] FDET3 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [3:3] FDET4 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [4:4] FDET5 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [5:5] FDET6 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [6:6] FDET7 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [7:7] RESERVED Reserved. [31:8] IST Pin interrupt status register 0x024 read-write 0 0xFFFFFFFF PSTAT0 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). [0:0] PSTAT1 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). [1:1] PSTAT2 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). [2:2] PSTAT3 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). [3:3] PSTAT4 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). [4:4] PSTAT5 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). [5:5] PSTAT6 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). [6:6] PSTAT7 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). [7:7] RESERVED Reserved. [31:8] PMCTRL Pattern match interrupt control register 0x028 read-write 0 0xFFFFFFFF SEL_PMATCH Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. [0:0] ENUM PIN_INTERRUPT_INTER Pin interrupt. Interrupts are driven in response to the standard pin interrupt function 0 PATTERN_MATCH_INTER Pattern match. Interrupts are driven in response to pattern matches. 1 ENA_RXEV Enables the RXEV output to the ARM cpu and/or to a GPIO output when the specified boolean expression evaluates to true. [1:1] ENUM DISABLED_RXEV_OUTPU Disabled. RXEV output to the cpu is disabled. 0 ENABLED_RXEV_OUTPUT Enabled. RXEV output to the cpu is enabled. 1 RESERVED Reserved. Do not write 1s to unused bits. [23:2] PMAT This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs. [31:24] PMSRC Pattern match interrupt bit-slice source register 0x02C read-write 0 0xFFFFFFFF Reserved Software should not write 1s to unused bits. [7:0] SRC0 Selects the input source for bit slice 0 [10:8] ENUM INPUT_0_SELECTS_PIN Input 0. Selects the output of pin interrupt select register 0 as the source to bit slice 0. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects the output of pin interrupt select register 1 as the source to bit slice 0. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects the output of pin interrupt select register 2 as the source to bit slice 0. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects the output of pin interrupt select register 3 as the source to bit slice 0. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects the output of pin interrupt select register 4 as the source to bit slice 0. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects the output of pin interrupt select register 5 as the source to bit slice 0. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects the output of pin interrupt select register 6 as the source to bit slice 0. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects the output of pin interrupt select register 7 as the source to bit slice 0. 0x7 SRC1 Selects the input source for bit slice 1 [13:11] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 1. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 1. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 1. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 1. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 1. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 1. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 1. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 1. 0x7 SRC2 Selects the input source for bit slice 2 [16:14] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 2. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 2. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 2. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 2. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 2. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 2. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 2. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 2. 0x7 SRC3 Selects the input source for bit slice 3 [19:17] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 3. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 3. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 3. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 3. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 3. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 3. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 3. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 3. 0x7 SRC4 Selects the input source for bit slice 4 [22:20] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 4. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 4. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 4. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 4. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 4. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 4. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 4. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 4. 0x7 SRC5 Selects the input source for bit slice 5 [25:23] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 5. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 5. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 5. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 5. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 5. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 5. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 5. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 5. 0x7 SRC6 Selects the input source for bit slice 6 [28:26] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 6. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 6. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 6. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 6. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 6. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 6. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 6. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 6. 0x7 SRC7 Selects the input source for bit slice 7 [31:29] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 7. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 7. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 7. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 7. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 7. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 7. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 7. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 7. 0x7 PMCFG Pattern match interrupt bit slice configuration register 0x030 read-write 0 0xFFFFFFFF PROD_ENDPTS A 1 in any bit of this field causes the corresponding bit slice to be the final component of a product term in the boolean expression. This has two effects: 1. The interrupt request associated with this bit-slice will be asserted whenever a match to that product term is detected. 2. The next bit slice will start a new, independent product term in the boolean expression (i.e. an OR will be inserted in the boolean expression following the element controlled by this bit slice). [6:0] RESERVED Reserved. Bit slice 7 is automatically considered a product end point. [7:7] CFG0 Specifies the match contribution condition for bit slice 0. [10:8] ENUM CONSTANT_HIGH_THIS_ Constant HIGH. This bit slice always contributes to a product term match. 0x0 STICKY_RISING_EDGEMA Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE_ Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_OR_FAL Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT_NON_STICKY_RI Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle. 0x7 CFG1 Specifies the match contribution condition for bit slice 1. [13:11] ENUM CONSTANT_HIGH_THIS_ Constant HIGH. This bit slice always contributes to a product term match. 0x0 STICKY_RISING_EDGEMA Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE_ Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_OR_FAL Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT_NON_STICKY_RI Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle. 0x7 CFG2 Specifies the match contribution condition for bit slice 2. [16:14] ENUM CONSTANT_HIGH_THIS_ Constant HIGH. This bit slice always contributes to a product term match. 0x0 STICKY_RISING_EDGEMA Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE_ Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_OR_FAL Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT_NON_STICKY_RI Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle. 0x7 CFG3 Specifies the match contribution condition for bit slice 3. [19:17] ENUM CONSTANT_HIGH_THIS_ Constant HIGH. This bit slice always contributes to a product term match. 0x0 STICKY_RISING_EDGEMA Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE_ Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_OR_FAL Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT_NON_STICKY_RI Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle. 0x7 CFG4 Specifies the match contribution condition for bit slice 4. [22:20] ENUM CONSTANT_HIGH_THIS_ Constant HIGH. This bit slice always contributes to a product term match. 0x0 STICKY_RISING_EDGEMA Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE_ Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_OR_FAL Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT_NON_STICKY_RI Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle. 0x7 CFG5 Specifies the match contribution condition for bit slice 5. [25:23] ENUM CONSTANT_HIGH_THIS_ Constant HIGH. This bit slice always contributes to a product term match. 0x0 STICKY_RISING_EDGEMA Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE_ Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_OR_FAL Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT_NON_STICKY_RI Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle. 0x7 CFG6 Specifies the match contribution condition for bit slice 6. [28:26] ENUM CONSTANT_HIGH_THIS_ Constant HIGH. This bit slice always contributes to a product term match. 0x0 STICKY_RISING_EDGEMA Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE_ Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_OR_FAL Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT_NON_STICKY_RI Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle. 0x7 CFG7 Specifies the match contribution condition for bit slice 7. [31:29] ENUM CONSTANT_HIGH_THIS_ Constant HIGH. This bit slice always contributes to a product term match. 0x0 STICKY_RISING_EDGEMA Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE_ Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_OR_FAL Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT_NON_STICKY_RI Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle. 0x7