LPC1102_04 4 LPC1102/04 CM0 r0p0 little 0 0 2 0 LPC_ 8 32 32 WWDT Windowed WatchDog Timer (WDT) WWDT 0x40004000 0x0 0xFFF registers WDT 25 WDMOD Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. 0x000 read-write 0 0xFFFFFFFF WDEN Watchdog enable bit. This bit is Set Only. Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one. [0:0] ENUM STOPPED The watchdog timer is stopped. 0 RUN The watchdog timer is running. 1 WDRESET Watchdog reset enable bit. This bit is Set Only. [1:1] ENUM NORESET A watchdog timeout will not cause a chip reset. 0 RESET A watchdog timeout will cause a chip reset. 1 WDTOF Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. [2:2] WDINT Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. [3:3] WDPROTECT Watchdog update mode. This bit is Set Only. [4:4] ENUM ANYTIME The watchdog reload value (WDTC) can be changed at any time. 0 LOWCOUNTER The watchdog reload value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. Note: this mode is intended for use only when WDRESET =1. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:5] WDTC Watchdog timer constant register. This register determines the time-out value. 0x004 read-write 0xFF 0xFFFFFFFF Count Watchdog time-out interval. [23:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:24] WDFEED Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. 0x008 write-only 0 0x00000000 Feed Feed value should be 0xAA followed by 0x55. [7:0] RESERVED Reserved [31:8] WDTV Watchdog timer value register. This register reads out the current value of the Watchdog timer. 0x00C read-only 0xFF 0xFFFFFFFF Count Counter timer value. [23:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:24] WDWARNINT Watchdog Warning Interrupt compare value. 0x014 read-write 0 0xFFFFFFFF WARNINT Watchdog warning interrupt compare value. [9:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:10] WDWINDOW Watchdog Window compare value. 0x018 read-write 0xFFFFFF 0xFFFFFFFF WINDOW Watchdog window value. [23:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:24] UART UART UART 0x40008000 0x0 0xFFF registers UART 21 RBR Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) 0x000 read-only 0 0x00000000 RBR The UART Receiver Buffer Register contains the oldest received byte in the UART RX FIFO. [7:0] RESERVED Reserved [31:8] THR Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) RBR 0x000 write-only 0 0x00000000 THR Writing to the UART Transmit Holding Register causes the data to be stored in the UART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. [7:0] RESERVED Reserved [31:8] DLL Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) RBR 0x000 read-write 0x01 0xFFFFFFFF DLLSB The UART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART. [7:0] RESERVED Reserved [31:8] DLM Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) 0x004 read-write 0x00 0xFFFFFFFF DLMSB The UART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART. [7:0] RESERVED Reserved [31:8] IER Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. (DLAB=0) DLM 0x004 read-write 0x00 0xFFFFFFFF RBRIE RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART. It also controls the Character Receive Time-out interrupt. [0:0] ENUM DISABLE_THE_RDA_INTE Disable the RDA interrupt. 0 ENABLE_THE_RDA_INTER Enable the RDA interrupt. 1 THREIE THRE Interrupt Enable. Enables the THRE interrupt for UART. The status of this interrupt can be read from LSR[5]. [1:1] ENUM DISABLE_THE_THRE_INT Disable the THRE interrupt. 0 ENABLE_THE_THRE_INTE Enable the THRE interrupt. 1 RXLIE RX Line Interrupt Enable. Enables the UART RX line status interrupts. The status of this interrupt can be read from LSR[4:1]. [2:2] ENUM DISABLE_THE_RX_LINE_ Disable the RX line status interrupts. 0 ENABLE_THE_RX_LINE_S Enable the RX line status interrupts. 1 RESERVED Reserved [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [6:4] RESERVED Reserved [7:7] ABEOINTEN Enables the end of auto-baud interrupt. [8:8] ENUM DISABLE_END_OF_AUTO_ Disable end of auto-baud Interrupt. 0 ENABLE_END_OF_AUTO_B Enable end of auto-baud Interrupt. 1 ABTOINTEN Enables the auto-baud time-out interrupt. [9:9] ENUM DISABLE_AUTO_BAUD_TI Disable auto-baud time-out Interrupt. 0 ENABLE_AUTO_BAUD_TIM Enable auto-baud time-out Interrupt. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] IIR Interrupt ID Register. Identifies which interrupt(s) are pending. 0x008 read-only 0x01 0xFFFFFFFF INTSTATUS Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]. [0:0] ENUM PENDING At least one interrupt is pending. 0 NO_INTERRUPT_IS_PEND No interrupt is pending. 1 INTID Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111). [3:1] ENUM 1_RECEIVE_LINE_S 1 - Receive Line Status (RLS). 0x3 2A__RECEIVE_DATA_AV 2a - Receive Data Available (RDA). 0x2 2B__CHARACTER_TIME_ 2b - Character Time-out Indicator (CTI). 0x6 3_THRE_INTERRUPT 3 - THRE Interrupt. 0x1 4_MODEM_INTERRUP 4 - Modem interrupt. 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:4] FIFOENABLE These bits are equivalent to FCR[0]. [7:6] ABEOINT End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. [8:8] ABTOINT Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. [9:9] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] FCR FIFO Control Register. Controls UART FIFO usage and modes. IIR 0x008 write-only 0x00 0xFFFFFFFF FIFOEN FIFO Enable [0:0] ENUM DISABLED UART FIFOs are disabled. Must not be used in the application. 0 ENABLED Active high enable for both UART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the UART FIFOs. 1 RXFIFORES RX FIFO Reset [1:1] ENUM NO_IMPACT_ON_EITHER_ No impact on either of UART FIFOs. 0 CLEAR Writing a logic 1 to FCR[1] will clear all bytes in UART Rx FIFO, reset the pointer logic. This bit is self-clearing. 1 TXFIFORES TX FIFO Reset [2:2] ENUM NO_IMPACT_ON_EITHER_ No impact on either of UART FIFOs. 0 CLEAR Writing a logic 1 to FCR[2] will clear all bytes in UART TX FIFO, reset the pointer logic. This bit is self-clearing. 1 RESERVED Reserved [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:4] RXTL RX Trigger Level. These two bits determine how many receiver UART FIFO characters must be written before an interrupt is activated. [7:6] ENUM TRIGGER_LEVEL_0_1_C Trigger level 0 (1 character or 0x01). 0x0 TRIGGER_LEVEL_1_4_C Trigger level 1 (4 characters or 0x04). 0x1 TRIGGER_LEVEL_2_8_C Trigger level 2 (8 characters or 0x08). 0x2 TRIGGER_LEVEL_3_14_ Trigger level 3 (14 characters or 0x0E). 0x3 RESERVED Reserved [31:8] LCR Line Control Register. Contains controls for frame formatting and break generation. 0x00C read-write 0x00 0xFFFFFFFF WLS Word Length Select [1:0] ENUM 5_BIT_CHARACTER_LENG 5-bit character length. 0x0 6_BIT_CHARACTER_LENG 6-bit character length. 0x1 7_BIT_CHARACTER_LENG 7-bit character length. 0x2 8_BIT_CHARACTER_LENG 8-bit character length. 0x3 SBS Stop Bit Select [2:2] ENUM 1_STOP_BIT_ 1 stop bit. 0 2_STOP_BITS 2 stop bits (1.5 if LCR[1:0]=00). 1 PE Parity Enable [3:3] ENUM DISABLE_PARITY_GENER Disable parity generation and checking. 0 ENABLE_PARITY_GENERA Enable parity generation and checking. 1 PS Parity Select [5:4] ENUM ODD_PARITY_NUMBER_O Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 0x0 EVEN_PARITY_NUMBER_ Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 0x1 FORCED_1_STICK_PARIT Forced 1 stick parity. 0x2 FORCED_0_STICK_PARIT Forced 0 stick parity. 0x3 BC Break Control [6:6] ENUM DISABLE_BREAK_TRANSM Disable break transmission. 0 ENABLE_BREAK_TRANSMI Enable break transmission. Output pin UART TXD is forced to logic 0 when LCR[6] is active high. 1 DLAB Divisor Latch Access Bit [7:7] ENUM DISABLE_ACCESS_TO_DI Disable access to Divisor Latches. 0 ENABLE_ACCESS_TO_DIV Enable access to Divisor Latches. 1 RESERVED Reserved [31:8] LSR Line Status Register. Contains flags for transmit and receive status, including line errors. 0x014 read-only 0x60 0xFFFFFFFF RDR Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART RBR FIFO is empty. [0:0] ENUM EMPTY_ RBR is empty. 0 VALID RBR contains valid data. 1 OE Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost. [1:1] ENUM INACTIVE Overrun error status is inactive. 0 ACTIVE Overrun error status is active. 1 PE Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART RBR FIFO. [2:2] ENUM INACTIVE Parity error status is inactive. 0 ACTIVE Parity error status is active. 1 FE Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO. [3:3] ENUM INACTIVE Framing error status is inactive. 0 ACTIVE Framing error status is active. 1 BI Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO. [4:4] ENUM INACTIVE Break interrupt status is inactive. 0 ACTIVE Break interrupt status is active. 1 THRE Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART THR and is cleared on a THR write. [5:5] ENUM VALID THR contains valid data. 0 EMPTY_ THR is empty. 1 TEMT Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data. [6:6] ENUM VALID THR and/or the TSR contains valid data. 0 EMPTY_ THR and the TSR are empty. 1 RXFE Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART FIFO. [7:7] ENUM NOERROR RBR contains no UART RX errors or FCR[0]=0. 0 ERROR UART RBR contains at least one UART RX error. 1 RESERVED Reserved [31:8] SCR Scratch Pad Register. Eight-bit temporary storage for software. 0x01C read-write 0x00 0xFFFFFFFF pad A readable, writable byte. [7:0] RESERVED Reserved [31:8] ACR Auto-baud Control Register. Contains controls for the auto-baud feature. 0x020 read-write 0x00 0xFFFFFFFF START Start bit. This bit is automatically cleared after auto-baud completion. [0:0] ENUM STOP Auto-baud stop (auto-baud is not running). 0 START Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. 1 MODE Auto-baud mode select [1:1] ENUM MODE_0_ Mode 0. 0 MODE_1_ Mode 1. 1 AUTORESTART Restart enable [2:2] ENUM NO_RESTART No restart 0 RESTART_IN_CASE_OF_T Restart in case of time-out (counter restarts at next UART Rx falling edge) 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:3] ABEOINTCLR End of auto-baud interrupt clear (write only accessible) [8:8] ENUM NOIMPACT Writing a 0 has no impact. 0 CLEAR Writing a 1 will clear the corresponding interrupt in the IIR. 1 ABTOINTCLR Auto-baud time-out interrupt clear (write only accessible) [9:9] ENUM NOIMPACT Writing a 0 has no impact. 0 CLEAR Writing a 1 will clear the corresponding interrupt in the IIR. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] FDR Fractional Divider Register. Generates a clock input for the baud rate divider. 0x028 read-write 0x10 0xFFFFFFFF DIVADDVAL Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART baud rate. [3:0] MULVAL Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART to operate properly, regardless of whether the fractional baud rate generator is used or not. [7:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] TER Transmit Enable Register. Turns off UART transmitter for use with software flow control. 0x030 read-write 0x80 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [6:0] TXEN When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. [7:7] RESERVED Reserved [31:8] RS485CTRL RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. 0x04C read-write 0x00 0xFFFFFFFF NMMEN NMM enable. [0:0] ENUM DISABLED RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. 0 ENABLED RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt. 1 RXDIS Receiver enable. [1:1] ENUM ENABLED The receiver is enabled. 0 DISABLED The receiver is disabled. 1 AADEN AAD enable. [2:2] ENUM DISABLED Auto Address Detect (AAD) is disabled. 0 ENABLED Auto Address Detect (AAD) is enabled. 1 SEL Select direction control pin [3:3] ENUM RTS If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control. 0 DTR If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control. 1 DCTRL Auto direction control enable. [4:4] ENUM DISABLE_AUTO_DIRECTI Disable Auto Direction Control. 0 ENABLE_AUTO_DIRECTIO Enable Auto Direction Control. 1 OINV Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. [5:5] ENUM LOW The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. 0 HIGH The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] RS485ADRMATCH RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. 0x050 read-write 0x00 0xFFFFFFFF ADRMATCH Contains the address match value. [7:0] RESERVED Reserved [31:8] RS485DLY RS-485/EIA-485 direction control delay. 0x054 read-write 0x00 0xFFFFFFFF DLY Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter. [7:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] CT16B0 16-bitcounter/timers (CT16B0/1) CT16B0 0x4000C000 0 0xFFF registers CT16B0 16 IR Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending. 0x000 read-write 0 0xFFFFFFFF MR0INT Interrupt flag for match channel 0. [0:0] MR1INT Interrupt flag for match channel 1. [1:1] MR2INT Interrupt flag for match channel 2. [2:2] MR3INT Interrupt flag for match channel 3. [3:3] RESERVED Reserved [31:4] TCR Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x004 read-write 0 0xFFFFFFFF CEN When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. [0:0] CRST When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] TC Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x008 read-write 0 0xFFFFFFFF TC Timer counter value. [15:0] RESERVED Reserved. [31:16] PR Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0x00C read-write 0 0xFFFFFFFF PR Prescale counter max value. [15:0] RESERVED Reserved. [31:16] PC Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x010 read-write 0 0xFFFFFFFF PC prescale counter value. [15:0] RESERVED Reserved. [31:16] MCR Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x014 read-write 0 0xFFFFFFFF MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. [0:0] ENUM Enabled Enabled 1 Disabled Disabled 0 MR0R Reset on MR0: the TC will be reset if MR0 matches it. [1:1] ENUM Enabled Enabled 1 Disabled Disabled 0 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. [2:2] ENUM Enabled Enabled 1 Disabled Disabled 0 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. [3:3] ENUM Enabled Enabled 1 Disabled Disabled 0 MR1R Reset on MR1: the TC will be reset if MR1 matches it. [4:4] ENUM Enabled Enabled 1 Disabled Disabled 0 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. [5:5] ENUM Enabled Enabled 1 Disabled Disabled 0 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. [6:6] ENUM Enabled Enabled 1 Disabled Disabled 0 MR2R Reset on MR2: the TC will be reset if MR2 matches it. [7:7] ENUM Enabled Enabled 1 Disabled Disabled 0 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. [8:8] ENUM Enabled Enabled 1 Disabled Disabled 0 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. [9:9] ENUM Enabled Enabled 1 Disabled Disabled 0 MR3R Reset on MR3: the TC will be reset if MR3 matches it. [10:10] ENUM Enabled Enabled 1 Disabled Disabled 0 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. [11:11] ENUM Enabled Enabled 1 Disabled Disabled 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] 4 0x4 0-3 MR%s Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate aninterrupt every time MR matches the TC. 0x018 read-write 0 0xFFFFFFFF MATCH Timer counter match value. [15:0] RESERVED Reserved. [31:16] EMR External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT[2:0]. 0x03C read-write 0 0xFFFFFFFF EM0 External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [0:0] EM1 External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [1:1] EM2 External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [2:2] EM3 External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers. [3:3] EMC0 External Match Control 0. Determines the functionality of External Match 0. [5:4] ENUM DONOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. [7:6] ENUM DONOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. [9:8] ENUM DONOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. [11:10] ENUM DONOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] PWMC PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT[2:0]. 0x074 read-write 0 0xFFFFFFFF PWMEN0 When one, PWM mode is enabled for CT16Bn_MAT0. When zero, CT16Bn_MAT0 is controlled by EM0. [0:0] PWMEN1 When one, PWM mode is enabled for CT16Bn_MAT1. When zero, CT16Bn_MAT1 is controlled by EM1. [1:1] PWMEN2 When one, PWM mode is enabled for match channel 2 or pin CT16B0_MAT2. When zero, match channel 2 or pin CT16B0_MAT2 is controlled by EM2. Match channel 2 is not pinned out on timer 1. [2:2] PWMEN3 When one, PWM mode is enabled for match channel 3. When zero, match channel 3 is controlled by EM3. Note: It is recommended to use to set the PWM cycle because it is not pinned out. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] CT16B1 0x40010000 0 0xFFF registers CT16B1 17 CT32B0 32-bit counter/timers (CT32B0/1) CT32B0 0x40014000 0 0xFFF registers CT32B0 18 IR Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending. 0x000 read-write 0 0xFFFFFFFF MR0INT Interrupt flag for match channel 0. [0:0] MR1INT Interrupt flag for match channel 1. [1:1] MR2INT Interrupt flag for match channel 2. [2:2] MR3INT Interrupt flag for match channel 3. [3:3] CR0INT Interrupt flag for capture channel 0 event. [4:4] RESERVED Reserved [31:5] TCR Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x004 read-write 0 0xFFFFFFFF CEN Counter Enable When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. [0:0] CRST Counter Reset When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] TC Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x008 read-write 0 0xFFFFFFFF TC Timer counter value. [31:0] PR Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0x00C read-write 0 0xFFFFFFFF PR Prescale counter max value. [31:0] PC Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x010 read-write 0 0xFFFFFFFF PC Prescale counter value. [31:0] MCR Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x014 read-write 0 0xFFFFFFFF MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. [0:0] ENUM Enabled Enabled 1 Disabled Disabled 0 MR0R Reset on MR0: the TC will be reset if MR0 matches it. [1:1] ENUM Enabled Enabled 1 Disabled Disabled 0 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. [2:2] ENUM Enabled Enabled 1 Disabled Disabled 0 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. [3:3] ENUM Enabled Enabled 1 Disabled Disabled 0 MR1R Reset on MR1: the TC will be reset if MR1 matches it. [4:4] ENUM Enabled Enabled 1 Disabled Disabled 0 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. [5:5] ENUM Enabled Enabled 1 Disabled Disabled 0 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. [6:6] ENUM Enabled Enabled 1 Disabled Disabled 0 MR2R Reset on MR2: the TC will be reset if MR2 matches it. [7:7] ENUM Enabled Enabled 1 Disabled Disabled 0 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. [8:8] ENUM Enabled Enabled 1 Disabled Disabled 0 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. [9:9] ENUM Enabled Enabled 1 Disabled Disabled 0 MR3R Reset on MR3: the TC will be reset if MR3 matches it. [10:10] ENUM Enabled Enabled 1 Disabled Disabled 0 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. [11:11] ENUM Enabled Enabled 1 Disabled Disabled 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] 4 0x4 0-3 MR%s Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate aninterrupt every time MR matches the TC. 0x018 read-write 0 0xFFFFFFFF MATCH Timer counter match value. [31:0] EMR External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0]. 0x03C read-write 0 0xFFFFFFFF EM0 External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [0:0] EM1 External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [1:1] EM2 External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [2:2] EM3 External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [3:3] EMC0 External Match Control 0. Determines the functionality of External Match 0. [5:4] ENUM DONOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. [7:6] ENUM DONOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. [9:8] ENUM DONOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. [11:10] ENUM DONOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] PWMC PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0]. 0x074 read-write 0 0xFFFFFFFF PWMEN0 When one, PWM mode is enabled for CT32Bn_MAT0. When zero, CT32Bn_MAT0 is controlled by EM0. [0:0] PWMEN1 When one, PWM mode is enabled for CT32Bn_MAT1. When zero, CT32Bn_MAT1 is controlled by EM1. [1:1] PWMEN2 When one, PWM mode is enabled for CT32Bn_MAT2. When zero, CT32Bn_MAT2 is controlled by EM2. [2:2] PWMEN3 When one, PWM mode is enabled for CT32Bn_MAT3. When zero, CT32Bn_MAT3 is controlled by EM3. Note: It is recommended to use match channel 3 to set the PWM cycle. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] CT32B1 Product name title=UM10429 Chapter title=LPC11102 32-bit counter/timers (CT32B0/1) Modification date=11/1/2010 Major revision=1 Minor revision=not available CT32B1 0x40018000 0 0xFFF registers CT32B1 19 IR Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending. 0x000 read-write 0 0xFFFFFFFF MR0INT Interrupt flag for match channel 0. [0:0] MR1INT Interrupt flag for match channel 1. [1:1] MR2INT Interrupt flag for match channel 2. [2:2] MR3INT Interrupt flag for match channel 3. [3:3] CR0INT Interrupt flag for capture channel 0 event. [4:4] RESERVED Reserved [31:5] TCR Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x004 read-write 0 0xFFFFFFFF CEN Counter Enable When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. [0:0] CRST Counter Reset When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] TC Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x008 read-write 0 0xFFFFFFFF TC Timer counter value. [31:0] PR Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0x00C read-write 0 0xFFFFFFFF PR Prescale counter max value. [31:0] PC Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x010 read-write 0 0xFFFFFFFF PC Prescale counter value. [31:0] MCR Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x014 read-write 0 0xFFFFFFFF MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. [0:0] ENUM Enabled Enabled 1 Disabled Disabled 0 MR0R Reset on MR0: the TC will be reset if MR0 matches it. [1:1] ENUM Enabled Enabled 1 Disabled Disabled 0 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. [2:2] ENUM Enabled Enabled 1 Disabled Disabled 0 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. [3:3] ENUM Enabled Enabled 1 Disabled Disabled 0 MR1R Reset on MR1: the TC will be reset if MR1 matches it. [4:4] ENUM Enabled Enabled 1 Disabled Disabled 0 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. [5:5] ENUM Enabled Enabled 1 Disabled Disabled 0 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. [6:6] ENUM Enabled Enabled 1 Disabled Disabled 0 MR2R Reset on MR2: the TC will be reset if MR2 matches it. [7:7] ENUM Enabled Enabled 1 Disabled Disabled 0 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. [8:8] ENUM Enabled Enabled 1 Disabled Disabled 0 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. [9:9] ENUM Enabled Enabled 1 Disabled Disabled 0 MR3R Reset on MR3: the TC will be reset if MR3 matches it. [10:10] ENUM Enabled Enabled 1 Disabled Disabled 0 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. [11:11] ENUM Enabled Enabled 1 Disabled Disabled 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] 4 0x4 0-3 MR%s Match Register. MR can be enabled through theMCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. 0x018 read-write 0 0xFFFFFFFF MATCH Timer counter match value. [31:0] CCR Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x028 read-write 0 0xFFFFFFFF CAP0RE Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC. [0:0] ENUM Enabled Enabled 1 Disabled Disabled 0 CAP0FE Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC. [1:1] ENUM Enabled Enabled 1 Disabled Disabled 0 CAP0I Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt. [2:2] ENUM Enabled Enabled 1 Disabled Disabled 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:3] CR0 Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input. 0x02C read-only 0 0xFFFFFFFF CAP Timer counter capture value. [31:0] EMR External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0]. 0x03C read-write 0 0xFFFFFFFF EM0 External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [0:0] EM1 External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [1:1] EM2 External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [2:2] EM3 External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [3:3] EMC0 External Match Control 0. Determines the functionality of External Match 0. [5:4] ENUM DONOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. [7:6] ENUM DONOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. [9:8] ENUM DONOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. [11:10] ENUM DONOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] CTCR Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x070 read-write 0 0xFFFFFFFF CTM Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge [1:0] ENUM TIMERMODE Timer Mode: every rising PCLK edge 0x0 RISING Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 FALLING Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 RISINGFALLING Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 CIS Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. 0x1 - 0x3 reserved. [3:2] ENUM CT32Bn_CAP0 CT32Bn_CAP0 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] PWMC PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0]. 0x074 read-write 0 0xFFFFFFFF PWMEN0 When one, PWM mode is enabled for CT32Bn_MAT0. When zero, CT32Bn_MAT0 is controlled by EM0. [0:0] PWMEN1 When one, PWM mode is enabled for CT32Bn_MAT1. When zero, CT32Bn_MAT1 is controlled by EM1. [1:1] PWMEN2 When one, PWM mode is enabled for CT32Bn_MAT2. When zero, CT32Bn_MAT2 is controlled by EM2. [2:2] PWMEN3 When one, PWM mode is enabled for CT32Bn_MAT3. When zero, CT32Bn_MAT3 is controlled by EM3. Note: It is recommended to use match channel 3 to set the PWM cycle. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] ADC 10-bit ADC ADC 0x4001C000 0x0 0xFFF registers ADC 24 CR A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur. 0x000 read-write 0x00000000 0xFFFFFFFF SEL Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01). [7:0] CLKDIV The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. [15:8] BURST Burst mode [16:16] test SWMODE Software-controlled mode: Conversions are software-controlled and require 11 clocks. 0 HWMODE Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start. 1 CLKS This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits). [19:17] test 10BIT 11 clocks / 10 bits 0x0 9BIT 10 clocks / 9 bits 0x1 8BIT 9 clocks / 8 bits 0x2 7BIT 8 clocks / 7 bits 0x3 6BIT 7 clocks / 6 bits 0x4 5BIT 6 clocks / 5 bits 0x5 4BIT 5 clocks / 4 bits 0x6 3BIT 4 clocks / 3 bits 0x7 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [23:20] START When the BURST bit is 0, these bits control whether and when an A/D conversion is started: [26:24] test STOP No start (this value should be used when clearing PDN to 0). 0x0 START Start conversion now. 0x1 EDGEPIO0_2 Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0. 0x2 EDGEPIO1_5 Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0. 0x3 EDGECT32B0_MAT0_1 Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0[1]. 0x4 EDGECT32B0_MAT1_1 Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1[1]. 0x5 EDGECT16B0_MAT0_1 Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0[1]. 0x6 EDGECT16B0_MAT1_1 Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1]. 0x7 EDGE This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal. [27:27] test RISING Start conversion on a rising edge on the selected CAP/MAT signal. 0 FALLING Start conversion on a rising edge on the selected CAP/MAT signal. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:28] GDR A/D Global Data Register. Contains the result of the most recent A/D conversion. 0x004 read-write 0 0x00000000 RESERVED Reserved. These bits always read as zeroes. [5:0] V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF. [15:6] RESERVED Reserved. These bits always read as zeroes. [23:16] CHN These bits contain the channel from which the result bits V_VREF were converted. [26:24] RESERVED Reserved. These bits always read as zeroes. [29:27] OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits. [30:30] DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. [31:31] STAT A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. 0x030 read-only 0 0xFFFFFFFF DONE These bits mirror the DONE status flags that appear in the result register for each A/D channel n. [7:0] OVERRUN These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel n. Reading ADSTAT allows checking the status of all A/D channels simultaneously. [15:8] ADINT This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. [16:16] RESERVED Unused, always 0. [31:17] INTEN A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. 0x00C read-write 0x00000100 0xFFFFFFFF ADINTENn These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc. [7:0] ADGINTEN When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts. [8:8] RESERVED Unused, always 0. [31:9] 5 0x4 0-4 DR%s A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n. 0x010 read-write 0 0xFFFFFFFF RESERVED Reserved, always 0. These bits always read as zeroes. [5:0] V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. [15:6] RESERVED These bits always read as zeroes. [29:16] OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register. [30:30] DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. [31:31] PMU PMU (PowerManagement Unit) PMU 0x40038000 0 0xFFF registers PCON Power control register 0x000 read-write 0x0 0xFFFFFFFF RESERVED Reserved. This bit must always be written as 0. [0:0] RESERVED Reserved. This bit must always be written as 0. [1:1] RESERVED Reserved. These bits must always be written as 0. [7:2] SLEEPFLAG Sleep mode flag [8:8] ENUM NOPOWERDOWN Read: No power-down mode entered. LPC1102 is in Active mode. Write: No effect. 0 POWERDOWNENTERED Read: Sleep/Deep-sleepmode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0. 1 RESERVED Reserved. These bits must always be written as 0. [10:9] RESERVED Reserved. This bit must always be written as 0. [11:11] RESERVED Reserved. Do not write ones to this bit. [31:12] FLASHCTRL Flash controller FLASHCTRL 0x4003C000 0 0xFFF registers FMC 27 FLASHCFG Flash memory access time configuration register 0x010 read-write 0 0x00000000 FLASHTIM Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access. [1:0] ENUM 1_SYSTEM_CLOCK_FLASH 1 system clock flash access time (for system clock frequencies of up to 20 MHz). 0x1 2_SYSTEM_CLOCKS_FLAS 2 system clocks flash access time (for system clock frequencies of up to 40 MHz). 0x2 3_SYSTEM_CLOCKS_FLAS 3 system clocks flash access time (for system clock frequencies of up to 50 MHz). 0x3 RESERVED Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read. [31:2] FMSSTART Signature start address register 0x020 read-write 0 0xFFFFFFFF START Signature generation start address (corresponds to AHB byte address bits[20:4]). [16:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:17] FMSSTOP Signature stop-address register 0x024 read-write 0 0xFFFFFFFF STOP BIST stop address divided by 16 (corresponds to AHB byte address [20:4]). [16:0] SIG_START Start control bit for signature generation. [17:17] ENUM SIGNATURE_GENERATION Signature generation is stopped 0 INITIATE_SIGNATURE_G Initiate signature generation 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:18] FMSW0 Word 0 [31:0] 0x02C read-only 0 0x00000000 SW0_31_0 Word 0 of 128-bit signature (bits 31 to 0). [31:0] FMSW1 Word 1 [63:32] 0x030 read-only 0 0x00000000 SW1_63_32 Word 1 of 128-bit signature (bits 63 to 32). [31:0] FMSW2 Word 2 [95:64] 0x034 read-only 0 0x00000000 SW2_95_64 Word 2 of 128-bit signature (bits 95 to 64). [31:0] FMSW3 Word 3 [127:96] 0x038 read-only 0 0x00000000 SW3_127_96 Word 3 of 128-bit signature (bits 127 to 96). [31:0] FMSTAT Signature generation status register 0xFE0 read-only 0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1:0] SIG_DONE When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag. [2:2] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:3] FMSTATCLR Signature generation status clear register 0xFE8 write-only 0 0x00000000 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1:0] SIG_DONE_CLR Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register. [2:2] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:3] SPI0 SPI0 SPI 0x40040000 0 0xFFF registers SPI0 20 CR0 Control Register 0. Selects the serial clock rate, bus type, and data size. 0x000 read-write 0 0xFFFFFFFF DSS Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. [3:0] ENUM 4_BIT_TRANSFER 4-bit transfer 0x3 5_BIT_TRANSFER 5-bit transfer 0x4 6_BIT_TRANSFER 6-bit transfer 0x5 7_BIT_TRANSFER 7-bit transfer 0x6 8_BIT_TRANSFER 8-bit transfer 0x7 9_BIT_TRANSFER 9-bit transfer 0x8 10_BIT_TRANSFER 10-bit transfer 0x9 11_BIT_TRANSFER 11-bit transfer 0xA 12_BIT_TRANSFER 12-bit transfer 0xB 13_BIT_TRANSFER 13-bit transfer 0xC 14_BIT_TRANSFER 14-bit transfer 0xD 15_BIT_TRANSFER 15-bit transfer 0xE 16_BIT_TRANSFER 16-bit transfer 0xF FRF Frame Format. [5:4] ENUM SPI SPI 0x0 TI TI 0x1 MICROWIRE Microwire 0x2 RESERVED This combination is not supported and should not be used. 0x3 CPOL Clock Out Polarity. This bit is only used in SPI mode. [6:6] ENUM LOW SPI controller maintains the bus clock low between frames. 0 HIGH SPI controller maintains the bus clock high between frames. 1 CPHA Clock Out Phase. This bit is only used in SPI mode. [7:7] ENUM FIRSTCLOCK SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. 0 SECONDCLOCK SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. 1 SCR Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). [15:8] RESERVED Reserved [31:16] CR1 Control Register 1. Selects master/slave and other modes. 0x004 read-write 0 0xFFFFFFFF LBM Loop Back Mode. [0:0] test NORMAL During normal operation. 0 LOOPBACK Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). 1 SSE SPI Enable. [1:1] test DISABLE The SPI controller is disabled. 0 ENABLE The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SPI/SSP registers and interrupt controller registers, before setting this bit. 1 MS Master/Slave Mode.This bit can only be written when the SSE bit is 0. [2:2] test MASTER The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. 0 SLAVE The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. 1 SOD Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO). [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DR Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. 0x008 read-write 0 0xFFFFFFFF DATA Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s. [15:0] RESERVED Reserved. [31:16] SR Status Register 0x00C read-only 0x00000003 0xFFFFFFFF TFE Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. [0:0] TNF Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. [1:1] RNE Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. [2:2] RFF Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. [3:3] BSY Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. [4:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] CPSR Clock Prescale Register 0x010 read-write 0 0xFFFFFFFF CPSDVSR This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. [7:0] RESERVED Reserved. [31:8] IMSC Interrupt Mask Set and Clear Register 0x014 read-write 0 0xFFFFFFFF RORIM Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. [0:0] RTIM Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). [1:1] RXIM Software should set this bit to enable interrupt when the Rx FIFO is at least half full. [2:2] TXIM Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] RIS Raw Interrupt Status Register 0x018 read-only 0x00000008 0xFFFFFFFF RORRIS This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. [0:0] RTRIS This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). [1:1] RXRIS This bit is 1 if the Rx FIFO is at least half full. [2:2] TXRIS This bit is 1 if the Tx FIFO is at least half empty. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] MIS Masked Interrupt Status Register 0x01C read-only 0 0xFFFFFFFF RORMIS This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. [0:0] RTMIS This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). [1:1] RXMIS This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. [2:2] TXMIS This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] ICR SSPICR Interrupt Clear Register 0x020 write-only 0 0x00000000 RORIC Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. [0:0] RTIC Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] IOCON I/O Configuration IOCON 0x40044000 0 0xFFF registers RESET_PIO0_0 I/O configuration for pin RESET/PIO0_0 0x00C read-write 0xD0 0xFFFFFFFF FUNC Selects pin function. All other values are reserved. [2:0] ENUM SELECTS_FUNCTION_RESET Selects function RESET. 0x0 SELECTS_FUNCTION_PIO0_0 Selects function PIO0_0. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 RESERVED Reserved [9:6] OD Selects pseudo open-drain mode. See Section 7.1 for part specific details. [10:10] ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved [31:11] IOCON_PIO0_1 I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 0x010 read-write 0xD0 0xFFFFFFFF FUNC Selects pin function. All other values are reserved. [2:0] ENUM SELECTS_FUNCTION_PIO0_1 Selects function PIO0_1. 0x0 SELECTS_FUNCTION_CLKOUT Selects function CLKOUT. 0x1 SELECTS_FUNCTION_CT32B0_MAT2 Selects function CT32B0_MAT2. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 RESERVED Reserved [9:6] OD Selects pseudo open-drain mode. [10:10] ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved [31:11] IOCON_PIO0_6 I/O configuration for pin PIO0_6/SCK0 0x04C read-write 0xD0 0xFFFFFFFF FUNC Selects pin function. All other values are reserved. [2:0] ENUM SELECTS_FUNCTION_PIO0_6 Selects function PIO0_6. 0x0 RESERVED_ Reserved. 0x1 SELECTS_FUNCTION_SCK0 Selects function SCK0 (only if pin PIO0_6/SCK0 selected in Table 147). 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 RESERVED Reserved [9:6] OD Selects pseudo open-drain mode. [10:10] ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved [31:11] PIO0_8 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 0x060 read-write 0xD0 0xFFFFFFFF FUNC Selects pin function. All other values are reserved. [2:0] ENUM SELECTS_FUNCTION_PIO0_8 Selects function PIO0_8. 0x0 SELECTS_FUNCTION_MISO0 Selects function MISO0. 0x1 SELECTS_FUNCTION_CT16B0_MAT0 Selects function CT16B0_MAT0. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 RESERVED Reserved [9:6] OD Selects pseudo open-drain mode. See Section 7.1 for part specific details. [10:10] ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved [31:11] PIO0_9 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 0x064 read-write 0xD0 0xFFFFFFFF FUNC Selects pin function. All other values are reserved. [2:0] ENUM SELECTS_FUNCTION_PIO0_9 Selects function PIO0_9. 0x0 SELECTS_FUNCTION_MOSI0 Selects function MOSI0. 0x1 SELECTS_FUNCTION_CT16B0_MAT1 Selects function CT16B0_MAT1. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 RESERVED Reserved [9:6] OD Selects pseudo open-drain mode. See Section 7.1 for part specific details. [10:10] ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved [31:11] SWCLK_PIO0_10 I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 0x068 read-write 0xD0 0xFFFFFFFF FUNC Selects pin function. All other values are reserved. [2:0] ENUM SELECTS_FUNCTION_SWCLK Selects function SWCLK. 0x0 SELECTS_FUNCTION_PIO0_10 Selects function PIO0_10. 0x1 SELECTS_FUNCTION_SCK0 Selects function SCK0 (only if pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 selected in Table 98). 0x2 SELECTS_FUNCTION_CT16B0_MAT2 Selects function CT16B0_MAT2. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 RESERVED Reserved [9:6] OD Selects pseudo open-drain mode. [10:10] ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved [31:11] R_PIO0_11 I/O configuration for pin R/PIO0_11/AD0/CT32B0_MAT3 0x074 read-write 0xD0 0xFFFFFFFF FUNC Selects pin function. All other values are reserved. [2:0] ENUM SELECTS_FUNCTION_R_ Selects function R. This function is reserved. Select one of the alternate functions below. 0x0 SELECTS_FUNCTION_PIO0_11 Selects function PIO0_11. 0x1 SELECTS_FUNCTION_AD0 Selects function AD0. 0x2 SELECTS_FUNCTION_CT32B0_MAT3 Selects function CT32B0_MAT3. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 RESERVED Reserved [6:6] ADMODE Selects Analog/Digital mode [7:7] ENUM ANALOG_INPUT_MODE Analog input mode 0 DIGITAL_FUNCTIONAL_M Digital functional mode 1 RESERVED Reserved [9:8] OD Selects pseudo open-drain mode. [10:10] ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved [31:11] R_PIO1_0 I/O configuration for pin R/PIO1_0/AD1/CT32B1_CAP0 0x078 read-write 0xD0 0xFFFFFFFF FUNC Selects pin function. All other values are reserved. [2:0] ENUM SELECTS_FUNCTION_R_ Selects function R. This function is reserved. Select one of the alternate functions below. 0x0 SELECTS_FUNCTION_PIO1_0 Selects function PIO1_0. 0x1 SELECTS_FUNCTION_AD1 Selects function AD1. 0x2 SELECTS_FUNCTION_CT32B1_CAP0 Selects function CT32B1_CAP0. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 RESERVED Reserved [6:6] ADMODE Selects Analog/Digital mode [7:7] ENUM ANALOG_INPUT_MODE Analog input mode 0 DIGITAL_FUNCTIONAL_M Digital functional mode 1 RESERVED Reserved [9:8] OD Selects pseudo open-drain mode. See Section 7.1 for part specific details. [10:10] ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved [31:11] R_PIO1_1 I/O configuration for pin R/PIO1_1/AD2/CT32B1_MAT0 0x07C read-write 0xD0 0xFFFFFFFF FUNC Selects pin function. All other values are reserved. [2:0] ENUM SELECTS_FUNCTION_R_ Selects function R. This function is reserved. Select one of the alternate functions below. 0x0 SELECTS_FUNCTION_PIO1_1 Selects function PIO1_1. 0x1 SELECTS_FUNCTION_AD2 Selects function AD2. 0x2 SELECTS_FUNCTION_CT32B1_MAT0 Selects function CT32B1_MAT0. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 RESERVED Reserved [6:6] ADMODE Selects Analog/Digital mode [7:7] ENUM ANALOG_INPUT_MODE Analog input mode 0 DIGITAL_FUNCTIONAL_M Digital functional mode 1 RESERVED Reserved [9:8] OD Selects pseudo open-drain mode. See Section 7.1 for part specific details. [10:10] ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved [31:11] R_PIO1_2 I/O configuration for pin R/PIO1_2/AD3/CT32B1_MAT1 0x080 read-write 0xD0 0xFFFFFFFF FUNC Selects pin function. All other values are reserved. [2:0] ENUM SELECTS_FUNCTION_R_ Selects function R. This function is reserved. Select one of the alternate functions below. 0x0 SELECTS_FUNCTION_PIO1_2 Selects function PIO1_2. 0x1 SELECTS_FUNCTION_AD3 Selects function AD3. 0x2 SELECTS_FUNCTION_CT32B1_MAT1 Selects function CT32B1_MAT1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 RESERVED Reserved [6:6] ADMODE Selects Analog/Digital mode [7:7] ENUM ANALOG_INPUT_MODE Analog input mode 0 DIGITAL_FUNCTIONAL_M Digital functional mode 1 RESERVED Reserved [9:8] OD Selects pseudo open-drain mode. See Section 7.1 for part specific details. [10:10] ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved [31:11] SWDIO_PIO1_3 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 0x090 read-write 0xD0 0xFFFFFFFF FUNC Selects pin function. All other values are reserved. [2:0] ENUM SELECTS_FUNCTION_SWDIO Selects function SWDIO. 0x0 SELECTS_FUNCTION_PIO1_3 Selects function PIO1_3. 0x1 SELECTS_FUNCTION_AD4 Selects function AD4. 0x2 SELECTS_FUNCTION_CT32B1_MAT2 Selects function CT32B1_MAT2. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 RESERVED Reserved [6:6] ADMODE Selects Analog/Digital mode [7:7] ENUM ANALOG_INPUT_MODE Analog input mode 0 DIGITAL_FUNCTIONAL_M Digital functional mode 1 RESERVED Reserved [9:8] OD Selects pseudo open-drain mode. [10:10] ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved [31:11] PIO1_6 I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 0x0A4 read-write 0xD0 0xFFFFFFFF FUNC Selects pin function. All other values are reserved. [2:0] ENUM SELECTS_FUNCTION_PIO1_6 Selects function PIO1_6. 0x0 SELECTS_FUNCTION_RXD Selects function RXD. 0x1 SELECTS_FUNCTION_CT32B0_MAT0 Selects function CT32B0_MAT0. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 RESERVED Reserved [9:6] OD Selects pseudo open-drain mode. See Section 7.1 for part specific details. [10:10] ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved [31:11] PIO1_7 I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 0x0A8 read-write 0xD0 0xFFFFFFFF FUNC Selects pin function. All other values are reserved. [2:0] ENUM SELECTS_FUNCTION_PIO1_7 Selects function PIO1_7. 0x0 SELECTS_FUNCTION_TXD Selects function TXD. 0x1 SELECTS_FUNCTION_CT32B0_MAT1 Selects function CT32B0_MAT1. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 RESERVED Reserved [9:6] OD Selects pseudo open-drain mode. See Section 7.1 for part specific details. [10:10] ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved [31:11] SYSCON System configuration SYSCON 0x40048000 0 0xFFF registers BOD 26 PIO0_0 0 PIO0_8 8 PIO0_9 9 PIO0_10 10 PIO0_11 11 PIO1_0 12 SYSMEMREMAP System memory remap 0x000 read-write 0x002 0xFFFFFFFF MAP System memory remap [1:0] ENUM BOOT_LOADER_MODE_IN Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. 0x0 USER_RAM_MODE_INTER User RAM Mode. Interrupt vectors are re-mapped to Static RAM. 0x1 USER_FLASH_MODE_INT User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. 0x2 USER_FLASH_MODE_INT User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. 0x3 RESERVED Reserved [31:2] PRESETCTRL Peripheral reset control 0x004 read-write 0x000 0xFFFFFFFF SSP0_RST_N SPI0 reset control [0:0] ENUM RESETS_THE_SPI0_PERI Resets the SPI0 peripheral. 0 SPI0_RESET_DE_ASSERT SPI0 reset de-asserted. 1 RESERVED Reserved [31:1] SYSPLLCTRL System PLL control 0x008 read-write 0x000 0xFFFFFFFF MSEL Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ration M = 32 [4:0] PSEL Post divider ratio P. The division ratio is 2 x P. [6:5] ENUM P_EQ_1 P = 1 0x0 P_EQ_2 P = 2 0x1 P_EQ_4 P = 4 0x2 P_EQ_8 P = 8 0x3 RESERVED Reserved. Do not write ones to reserved bits. [31:7] SYSPLLSTAT System PLL status 0x00C read-only 0x000 0xFFFFFFFF LOCK PLL lock status [0:0] ENUM PLL_NOT_LOCKED PLL not locked 0 PLL_LOCKED PLL locked 1 RESERVED Reserved [31:1] SYSOSCCTRL System oscillator control 0x020 read-write 0x000 0xFFFFFFFF BYPASS Bypass system oscillator [0:0] ENUM OSCILLATOR_IS_NOT_BY Oscillator is not bypassed. 0 BYPASS_ENABLED_PLL_ Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pin bypassing the oscillator. Use this mode when using an external clock source instead of the crystal oscillator. 1 FREQRANGE Determines frequency range for Low-power oscillator. [1:1] ENUM 1__20_MHZ_FREQUENCY 1 - 20 MHz frequency range. 0 15__25_MHZ_FREQUENC 15 - 25 MHz frequency range 1 RESERVED Reserved [31:2] WDTOSCCTRL Watchdog oscillator control 0x024 read-write 0x000 0xFFFFFFFF DIVSEL Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64 [4:0] FREQSEL Select watchdog oscillator analog output frequency (Fclkana). [8:5] ENUM 0_6_MHZ 0.6 MHz 0x1 1_05_MHZ 1.05 MHz 0x2 1_4_MHZ 1.4 MHz 0x3 1_75_MHZ 1.75 MHz 0x4 2_1_MHZ 2.1 MHz 0x5 2_4_MHZ 2.4 MHz 0x6 2_7_MHZ 2.7 MHz 0x7 3_0_MHZ 3.0 MHz 0x8 3_25_MHZ 3.25 MHz 0x9 3_5_MHZ 3.5 MHz 0xA 3_75_MHZ 3.75 MHz 0xB 4_0_MHZ 4.0 MHz 0xC 4_2_MHZ 4.2 MHz 0xD 4_4_MHZ 4.4 MHz 0xE 4_6_MHZ 4.6 MHz 0xF RESERVED Reserved [31:9] IRCCTRL IRC control 0x028 read-write 0x080 0xFFFFFFFF TRIM Trim value [7:0] RESERVED Reserved [31:9] SYSRSTSTAT System reset status register 0x030 read-write 0x000 0xFFFFFFFF POR POR reset status [0:0] ENUM NO_POR_DETECTED No POR detected 0 POR_DETECTED_WRITIN POR detected. Writing a one clears this reset. 1 EXTRST Status of the external RESET pin [1:1] ENUM NO_RESET_PIN_EVENT_D No RESET pin event detected 0 RESET_DETECTED_WRIT RESET detected. Writing a one clears this reset. 1 WDT Status of the Watchdog reset [2:2] ENUM NO_WDT_RESET_DETECTE No WDT reset detected 0 WDT_RESET_DETECTED_ WDT reset detected. Writing a one clears this reset. 1 BOD Status of the Brown-out detect reset [3:3] ENUM NO_BOD_RESET_DETECTE No BOD reset detected 0 BOD_RESET_DETECTED_ BOD reset detected. Writing a one clears this reset. 1 SYSRST Status of the software system reset [4:4] ENUM NO_SYSTEM_RESET_DETE No System reset detected 0 SYSTEM_RESET_DETECTE System reset detected. Writing a one clears this reset. 1 RESERVED Reserved [31:5] SYSPLLCLKSEL System PLL clock source select 0x040 read-write 0x000 0xFFFFFFFF SEL System PLL clock source [1:0] ENUM IRC_OSCILLATOR IRC oscillator 0x0 SYSTEM_OSCILLATOR System oscillator 0x1 RESERVED Reserved 0x2 RESERVED Reserved 0x3 RESERVED Reserved [31:2] SYSPLLCLKUEN System PLL clock source update enable 0x044 read-write 0x000 0xFFFFFFFF ENA Enable system PLL clock source update [0:0] ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved [31:1] MAINCLKSEL Main clock source select 0x070 read-write 0x000 0xFFFFFFFF SEL Clock source for main clock [1:0] ENUM IRC_OSCILLATOR IRC oscillator 0x0 INPUT_CLOCK_TO_SYSTE Input clock to system PLL 0x1 WDT_OSCILLATOR WDT oscillator 0x2 SYSTEM_PLL_CLOCK_OUT System PLL clock out 0x3 RESERVED Reserved [31:2] MAINCLKUEN Main clock source update enable 0x074 read-write 0x000 0xFFFFFFFF ENA Enable main clock source update [0:0] ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved [31:1] SYSAHBCLKDIV System AHB clock divider 0x078 read-write 0x001 0xFFFFFFFF DIV System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] SYSAHBCLKCTRL System AHB clock control 0x080 read-write 0x85F 0xFFFFFFFF SYS Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M0 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only. [0:0] ENUM RESERVED Reserved 0 ENABLE Enable 1 ROM Enables clock for ROM. [1:1] ENUM DISABLE Disable 0 ENABLE Enable 1 RAM Enables clock for RAM. [2:2] ENUM DISABLE Disable 0 ENABLE Enable 1 FLASHREG Enables clock for flash register interface. [3:3] ENUM DISABLED Disabled 0 ENABLED Enabled 1 FLASHARRAY Enables clock for flash array access. [4:4] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved. [5:5] GPIO Enables clock for GPIO. [6:6] ENUM DISABLE Disable 0 ENABLE Enable 1 CT16B0 Enables clock for 16-bit counter/timer 0. [7:7] ENUM DISABLE Disable 0 ENABLE Enable 1 CT16B1 Enables clock for 16-bit counter/timer 1. [8:8] ENUM DISABLE Disable 0 ENABLE Enable 1 CT32B0 Enables clock for 32-bit counter/timer 0. [9:9] ENUM DISABLE Disable 0 ENABLE Enable 1 CT32B1 Enables clock for 32-bit counter/timer 1. [10:10] ENUM DISABLE Disable 0 ENABLE Enable 1 SSP0 Enables clock for SPI0. [11:11] ENUM DISABLE Disable 0 ENABLE Enable 1 UART Enables clock for UART. [12:12] ENUM DISABLE Disable 0 ENABLE Enable 1 ADC Enables clock for ADC. [13:13] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [14:14] WDT Enables clock for WDT. [15:15] ENUM DISABLE Disable 0 ENABLE Enable 1 IOCON Enables clock for I/O configuration block. [16:16] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [31:17] SSP0CLKDIV SPI0 clock divder 0x094 read-write 0x000 0xFFFFFFFF DIV SPI0_PCLK clock divider values 0: Disable SPI0_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] UARTCLKDIV UART clock divder 0x098 read-write 0x000 0xFFFFFFFF DIV UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] WDTCLKSEL WDT clock source select 0x0D0 read-write 0x000 0xFFFFFFFF SEL WDT clock source [1:0] ENUM IRC_OSCILLATOR IRC oscillator 0x0 MAIN_CLOCK Main clock 0x1 WATCHDOG_OSCILLATOR Watchdog oscillator 0x2 RESERVED Reserved 0x3 RESERVED Reserved [31:2] WDTCLKUEN WDT clock source update enable 0x0D4 read-write 0x000 0xFFFFFFFF ENA Enable WDT clock source update [0:0] ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved [31:1] WDTCLKDIV WDT clock divider 0x0D8 read-write 0x000 0xFFFFFFFF DIV WDT clock divider values 0: Disable WDCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] CLKOUTCLKSEL CLKOUT clock source select 0x0E0 read-write 0x000 0xFFFFFFFF SEL CLKOUT clock source [1:0] ENUM IRC_OSCILLATOR IRC oscillator 0x0 SYSTEM_OSCILLATOR System oscillator 0x1 WATCHDOG_OSCILLATOR Watchdog oscillator 0x2 MAIN_CLOCK Main clock 0x3 RESERVED Reserved [31:2] CLKOUTUEN CLKOUT clock source update enable 0x0E4 read-write 0x000 0xFFFFFFFF ENA Enable CLKOUT clock source update [0:0] ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved [31:1] CLKOUTCLKDIV CLKOUT clock divider 0x0E8 read-write 0x000 0xFFFFFFFF DIV Clock output divider values 0: Disable CLKOUT. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] PIOPORCAP0 POR captured PIO status 0 0x100 read-only 0 0x00000000 CAPPIO0_0 Raw reset status input PIO0_0 [0:0] RESERVED Reserved. [7:1] CAPPIO0_8 Raw reset status input PIO0_8 [8:8] CAPPIO0_9 Raw reset status input PIO0_9 [9:9] CAPPIO0_10 Raw reset status input PIO0_10 [10:10] CAPPIO0_11 Raw reset status input PIO0_11 [11:11] CAPPIO1_0 Raw reset status input PIO1_0 [12:12] CAPPIO1_1 Raw reset status input PIO1_1 [13:13] CAPPIO1_2 Raw reset status input PIO1_2 [14:14] CAPPIO1_3 Raw reset status input PIO1_3 [15:15] RESERVED Reserved. [17:16] CAPPIO1_6 Raw reset status input PIO1_6 [18:18] CAPPIO1_7 Raw reset status input PIO1_7 [19:19] RESERVED Reserved. [31:20] BODCTRL BOD control 0x150 read-write 0x000 0xFFFFFFFF BODRSTLEV BOD reset level [1:0] ENUM LEVEL_0_RESERVED_ Level 0: Reserved. 0x0 LEVEL_1_THE_RESET_A Level 1: The reset assertion threshold voltage is 2.06 V; the reset de-assertion threshold voltage is 2.15 V. 0x1 LEVEL_2_THE_RESET_A Level 2: The reset assertion threshold voltage is 2.35 V; the reset de-assertion threshold voltage is 2.43 V. 0x2 LEVEL_3_THE_RESET_A Level 3: The reset assertion threshold voltage is 2.63 V; the reset de-assertion threshold voltage is 2.71 V. 0x3 BODINTVAL BOD interrupt level [3:2] ENUM LEVEL_0_RESERVED_ Level 0: Reserved. 0x0 LEVEL_1THE_INTERRUP Level 1:The interrupt assertion threshold voltage is 2.22 V; the interrupt de-assertion threshold voltage is 2.35 V. 0x1 LEVEL_2_THE_INTERRU Level 2: The interrupt assertion threshold voltage is 2.52 V; the interrupt de-assertion threshold voltage is 2.66 V. 0x2 LEVEL_3_THE_INTERRU Level 3: The interrupt assertion threshold voltage is 2.80 V; the interrupt de-assertion threshold voltage is 2.90 V. 0x3 BODRSTENA BOD reset enable [4:4] ENUM DISABLE_RESET_FUNCTI Disable reset function. 0 ENABLE_RESET_FUNCTIO Enable reset function. 1 RESERVED Reserved [31:5] SYSTCKCAL System tick counter calibration 0x154 read-write 0x004 0xFFFFFFFF CAL System tick timer calibration value [25:0] RESERVED Reserved [31:26] STARTAPRP0 Start logic edge control register 0 0x200 read-write 0 0x00000000 APRPIO0_0 Edge select for start logic input PIO0_0 [0:0] ENUM FALLING_EDGE Falling edge 0 RISING_EDGE Rising edge 1 RESERVED Reserved [7:1] APRPIO0_8 Edge select for start logic input PIO0_8 [8:8] ENUM FALLING_EDGE Falling edge 0 RISING_EDGE Rising edge 1 APRPIO0_9 Edge select for start logic input PIO0_9 [9:9] ENUM FALLING_EDGE Falling edge 0 RISING_EDGE Rising edge 1 APRPIO0_10 Edge select for start logic input PIO0_10 [10:10] ENUM FALLING_EDGE Falling edge 0 RISING_EDGE Rising edge 1 APRPIO0_11 Edge select for start logic input PIO0_11 [11:11] ENUM FALLING_EDGE Falling edge 0 RISING_EDGE Rising edge 1 APRPIO1_0 Edge select for start logic input PIO1_0. [12:12] ENUM FALLING_EDGE Falling edge 0 RISING_EDGE Rising edge 1 RESERVED Reserved [31:13] STARTERP0 Start logic signal enable register 0 0x204 read-write 0 0x00000000 ERPIO0_0 Enable start signal for start logic input PIO0_0 [0:0] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved [7:1] ERPIO0_8 Enable start signal for start logic input PIO0_8 [8:8] ENUM DISABLED Disabled 0 ENABLED Enabled 1 ERPIO0_9 Enable start signal for start logic input PIO0_9 [9:9] ENUM DISABLED Disabled 0 ENABLED Enabled 1 ERPIO0_10 Enable start signal for start logic input PIO0_10 [10:10] ENUM DISABLED Disabled 0 ENABLED Enabled 1 ERPIO0_11 Enable start signal for start logic input PIO0_11 [11:11] ENUM DISABLED Disabled 0 ENABLED Enabled 1 ERPIO1_0 Enable start signal for start logic input PIO1_0 [12:12] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved. Do not set reserved bits in this register to one. [31:13] STARTRSRP0CLR Start logic reset register 0 0x208 write-only 0 0x00000000 RSRPIO0_0 Start signal reset for start logic input PIO0_0 [0:0] ENUM _ RESERVED 0 WRITE_RESET_START_S Write: reset start signal 1 RESERVED Reserved [7:1] RSRPIO0_8 Start signal reset for start logic input PIO0_8 [8:8] ENUM _ RESERVED 0 WRITE_RESET_START_S Write: reset start signal 1 RSRPIO0_9 Start signal reset for start logic input PIO0_9 [9:9] ENUM _ RESERVED 0 WRITE_RESET_START_S Write: reset start signal 1 RSRPIO0_10 Start signal reset for start logic input PIO0_10 [10:10] ENUM _ RESERVED 0 WRITE_RESET_START_S Write: reset start signal 1 RSRPIO0_11 Start signal reset for start logic input PIO0_11 [11:11] ENUM _ RESERVED 0 WRITE_RESET_START_S Write: reset start signal 1 RSRPIO1_0 Start signal reset for start logic input PIO1_0 [12:12] ENUM _ RESERVED 0 WRITE_RESET_START_S Write: reset start signal 1 RESERVED Reserved [31:13] STARTSRP0 Start logic status register 0 0x20C read-only 0 0x00000000 SRPIO0_0 Start signal status for start logic input 0PIO0_0 [0:0] ENUM NO_START_SIGNAL_RECE No start signal received 0 START_SIGNAL_PENDING Start signal pending 1 RESERVED Reserved [7:1] SRPIO0_8 Start signal status for start logic input PIO0_8 [8:8] ENUM NO_START_SIGNAL_RECE No start signal received 0 START_SIGNAL_PENDING Start signal pending 1 SRPIO0_9 Start signal status for start logic input PIO0_9 [9:9] ENUM NO_START_SIGNAL_RECE No start signal received 0 START_SIGNAL_PENDING Start signal pending 1 SRPIO0_10 Start signal status for start logic input PIO0_10 [10:10] ENUM NO_START_SIGNAL_RECE No start signal received 0 START_SIGNAL_PENDING Start signal pending 1 SRPIO0_11 Start signal status for start logic input PIO0_11 [11:11] ENUM NO_START_SIGNAL_RECE No start signal received 0 START_SIGNAL_PENDING Start signal pending 1 SRPIO1_0 Start signal status for start logic input PIO1_0 [12:12] ENUM NO_START_SIGNAL_RECE No start signal received 0 START_SIGNAL_PENDING Start signal pending 1 RESERVED Reserved [31:13] PDSLEEPCFG Power-down states in Deep-sleep mode 0x230 read-write 0x00000000 0xFFFFFFFF RESERVED Reserved. Always write these bits as 111. [2:0] BOD_PD BOD power-down control in Deep-sleep mode, see Table 35. [3:3] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved. Always write these bits as 11. [5:4] WDTOSC_PD Watchdog oscillator power control in Deep-sleep mode, see Table 35. [6:6] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved. Always write this bit as 1. [7:7] RESERVED Reserved. Always write these bits as 000. [10:8] RESERVED Reserved. Always write these bits as 11. [12:11] RESERVED Reserved [31:13] PDAWAKECFG Power-down states after wake-up from Deep-sleep mode 0x234 read-write 0x0000EDF0 0xFFFFFFFF IRCOUT_PD IRC oscillator output wake-up configuration [0:0] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 IRC_PD IRC oscillator power-down wake-up configuration [1:1] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 FLASH_PD Flash wake-up configuration [2:2] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 BOD_PD BOD wake-up configuration [3:3] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 ADC_PD ADC wake-up configuration [4:4] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SYSOSC_PD System oscillator wake-up configuration [5:5] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 WDTOSC_PD Watchdog oscillator wake-up configuration [6:6] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SYSPLL_PD System PLL wake-up configuration [7:7] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved. Always write this bit as 1. [8:8] RESERVED Reserved. Always write this bit as 0. [9:9] RESERVED Reserved. Always write this bit as 1. [10:10] RESERVED Reserved. Always write this bit as 1. [11:11] RESERVED Reserved. Always write this bit as 0. [12:12] RESERVED Reserved. Always write these bits as 111. [15:13] RESERVED Reserved [31:16] PDRUNCFG Power-down configuration register 0x238 read-write 0x0000EDF0 0xFFFFFFFF IRCOUT_PD IRC oscillator output power-down [0:0] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 IRC_PD IRC oscillator power-down [1:1] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 FLASH_PD Flash power-down [2:2] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 BOD_PD BOD power-down [3:3] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 ADC_PD ADC power-down [4:4] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SYSOSC_PD System oscillator power-down [5:5] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 WDTOSC_PD Watchdog oscillator power-down [6:6] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SYSPLL_PD System PLL power-down [7:7] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved. Always write this bit as 1. [8:8] RESERVED Reserved. Always write this bit as 0. [9:9] RESERVED Reserved. Always write this bit as 1. [10:10] RESERVED Reserved. Always write this bit as 1. [11:11] RESERVED Reserved. Always write this bit as 0. [12:12] RESERVED Reserved. Always write these bits as 111. [15:13] RESERVED Reserved [31:16] DEVICE_ID Device ID 0x3F4 read-only 0 0x00000000 DEVICEID Part ID numbers for LPC1102/04 parts LPC1102 = 0x2500 102B LPC1104 = 0x2548 102B [31:0] GPIO0 General Purpose I/O (GPIO) GPIO 0x50000000 0 0xFFFFFF registers GPIO0 31 DATA Port n data address masking register locations for pins PIOn_0 to PIOn_11 (see Section 9.4.1). 0x3FF8 read-write 0x00000000 0x00000000 DATA0 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. [0:0] DATA1 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. [1:1] DATA2 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. [2:2] DATA3 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. [3:3] DATA4 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. [4:4] DATA5 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. [5:5] DATA6 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. [6:6] DATA7 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. [7:7] DATA8 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. [8:8] DATA9 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. [9:9] DATA10 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. [10:10] DATA11 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. [11:11] RESERVED Reserved [31:12] DIR Data direction register for port n 0x8000 read-write 0x00 0xFFFFFFFF IO0 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. [0:0] IO1 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. [1:1] IO2 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. [2:2] IO3 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. [3:3] IO4 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. [4:4] IO5 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. [5:5] IO6 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. [6:6] IO7 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. [7:7] IO8 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. [8:8] IO9 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. [9:9] IO10 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. [10:10] IO11 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. [11:11] RESERVED Reserved [31:12] IS Interrupt sense register for port n 0x8004 read-write 0x00 0xFFFFFFFF ISENSE0 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. [0:0] ISENSE1 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. [1:1] ISENSE2 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. [2:2] ISENSE3 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. [3:3] ISENSE4 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. [4:4] ISENSE5 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. [5:5] ISENSE6 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. [6:6] ISENSE7 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. [7:7] ISENSE8 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. [8:8] ISENSE9 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. [9:9] ISENSE10 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. [10:10] ISENSE11 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. [11:11] RESERVED Reserved [31:12] IBE Interrupt both edges register for port n 0x8008 read-write 0x00 0xFFFFFFFF IBE0 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register IEV. 1 = Both edges on pin PIOn_x trigger an interrupt. [0:0] IBE1 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register IEV. 1 = Both edges on pin PIOn_x trigger an interrupt. [1:1] IBE2 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register IEV. 1 = Both edges on pin PIOn_x trigger an interrupt. [2:2] IBE3 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register IEV. 1 = Both edges on pin PIOn_x trigger an interrupt. [3:3] IBE4 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register IEV. 1 = Both edges on pin PIOn_x trigger an interrupt. [4:4] IBE5 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register IEV. 1 = Both edges on pin PIOn_x trigger an interrupt. [5:5] IBE6 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register IEV. 1 = Both edges on pin PIOn_x trigger an interrupt. [6:6] IBE7 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register IEV. 1 = Both edges on pin PIOn_x trigger an interrupt. [7:7] IBE8 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register IEV. 1 = Both edges on pin PIOn_x trigger an interrupt. [8:8] IBE9 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register IEV. 1 = Both edges on pin PIOn_x trigger an interrupt. [9:9] IBE10 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register IEV. 1 = Both edges on pin PIOn_x trigger an interrupt. [10:10] IBE11 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register IEV. 1 = Both edges on pin PIOn_x trigger an interrupt. [11:11] RESERVED Reserved [31:12] IEV Interrupt event register for port n 0x800C read-write 0x00 0xFFFFFFFF IEV0 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register IS , falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register IS , rising edges or HIGH level on pin PIOn_x trigger an interrupt. [0:0] IEV1 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register IS , falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register IS , rising edges or HIGH level on pin PIOn_x trigger an interrupt. [1:1] IEV2 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register IS , falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register IS , rising edges or HIGH level on pin PIOn_x trigger an interrupt. [2:2] IEV3 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register IS , falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register IS , rising edges or HIGH level on pin PIOn_x trigger an interrupt. [3:3] IEV4 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GIS , falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register IS , rising edges or HIGH level on pin PIOn_x trigger an interrupt. [4:4] IEV5 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register IS , falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register IS , rising edges or HIGH level on pin PIOn_x trigger an interrupt. [5:5] IEV6 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register IS , falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register IS , rising edges or HIGH level on pin PIOn_x trigger an interrupt. [6:6] IEV7 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register IS , falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register IS , rising edges or HIGH level on pin PIOn_x trigger an interrupt. [7:7] IEV8 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register IS , falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register IS , rising edges or HIGH level on pin PIOn_x trigger an interrupt. [8:8] IEV9 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register IS , falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register IS , rising edges or HIGH level on pin PIOn_x trigger an interrupt. [9:9] IEV10 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register IS , falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register IS , rising edges or HIGH level on pin PIOn_x trigger an interrupt. [10:10] IEV11 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register IS , falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register IS MR0 to 3, rising edges or HIGH level on pin PIOn_x trigger an interrupt. [11:11] RESERVED Reserved [31:12] IE Interrupt mask register for port n 0x8010 read-write 0x00 0xFFFFFFFF MASK0 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. [0:0] MASK1 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. [1:1] MASK2 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. [2:2] MASK3 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. [3:3] MASK4 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. [4:4] MASK5 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. [5:5] MASK6 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. [6:6] MASK7 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. [7:7] MASK8 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. [8:8] MASK9 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. [9:9] MASK10 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. [10:10] MASK11 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. [11:11] RESERVED Reserved [31:12] RIS Raw interrupt status register for port n 0x8014 read-only 0x00 0xFFFFFFFF RAWST0 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. [0:0] RAWST1 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. [1:1] RAWST2 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. [2:2] RAWST3 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. [3:3] RAWST4 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. [4:4] RAWST5 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. [5:5] RAWST6 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. [6:6] RAWST7 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. [7:7] RAWST8 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. [8:8] RAWST9 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. [9:9] RAWST10 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. [10:10] RAWST11 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. [11:11] RESERVED Reserved [31:12] MIS Masked interrupt status register for port n 0x8018 read-only 0x00 0xFFFFFFFF MASK0 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. [0:0] MASK1 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. [1:1] MASK2 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. [2:2] MASK3 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. [3:3] MASK4 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. [4:4] MASK5 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. [5:5] MASK6 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. [6:6] MASK7 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. [7:7] MASK8 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. [8:8] MASK9 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. [9:9] MASK10 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. [10:10] MASK11 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. [11:11] RESERVED Reserved [31:12] IC Interrupt clear register for port n 0x801C write-only 0x00 0xFFFFFFFF CLR0 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. [0:0] CLR1 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. [1:1] CLR2 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. [2:2] CLR3 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. [3:3] CLR4 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. [4:4] CLR5 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. [5:5] CLR6 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. [6:6] CLR7 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. [7:7] CLR8 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. [8:8] CLR9 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. [9:9] CLR10 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. [10:10] CLR11 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. [11:11] RESERVED Reserved [31:12] GPIO1 0x50010000 GPIO1 30