<?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>Canaan Inc.</vendor>
<name>K210</name>
<version>1.0</version>
<description>Kendryte K210 64-bit RISC-V CPU</description>
<addressUnitBits>8</addressUnitBits>
<width>64</width>
<size>32</size>
<access>read-write</access>
<!-- TODO: remove this -->
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
<!-- CLINT -->
<peripheral>
<name>CLINT</name>
<description>Core Local Interruptor</description>
<groupName>CLINT</groupName>
<baseAddress>0x02000000</baseAddress>
<registers>
<register>
<dim>2</dim>
<dimIncrement>0x04</dimIncrement>
<name>msip[%s]</name>
<description>Hart software interrupt register</description>
<addressOffset>0x0000</addressOffset>
<writeConstraint>
<range>
<minimum>0</minimum>
<maximum>1</maximum>
</range>
</writeConstraint>
</register>
<register>
<size>64</size>
<dim>2</dim>
<dimIncrement>0x08</dimIncrement>
<name>mtimecmp[%s]</name>
<description>Hart time comparator register</description>
<addressOffset>0x4000</addressOffset>
</register>
<register>
<size>64</size>
<name>mtime</name>
<description>Timer register</description>
<addressOffset>0xBFF8</addressOffset>
</register>
</registers>
</peripheral>
<!-- CLINT -->
<!-- PLIC -->
<peripheral>
<name>PLIC</name>
<description>Platform-Level Interrupt Controller</description>
<groupName>PLIC</groupName>
<baseAddress>0x0C000000</baseAddress>
<registers>
<register>
<dim>1024</dim>
<dimIncrement>0x04</dimIncrement>
<name>priority[%s]</name>
<description>Interrupt Source Priority Register</description>
<addressOffset>0x000000</addressOffset>
<enumeratedValues derivedFrom="threshold">
</enumeratedValues>
</register>
<register>
<dim>32</dim>
<dimIncrement>0x04</dimIncrement>
<name>pending[%s]</name>
<description>Interrupt Pending Register</description>
<addressOffset>0x001000</addressOffset>
</register>
<cluster>
<name>target_enables[%s]</name>
<description>Target Interrupt Enables</description>
<addressOffset>0x002000</addressOffset>
<dim>4</dim>
<dimIncrement>0x80</dimIncrement>
<register>
<dim>32</dim>
<dimIncrement>0x04</dimIncrement>
<name>enable[%s]</name>
<description>Interrupt Enable Register</description>
<addressOffset>0</addressOffset>
</register>
</cluster>
<cluster>
<name>targets[%s]</name>
<description>Target Configuration</description>
<addressOffset>0x200000</addressOffset>
<dim>4</dim>
<dimIncrement>0x1000</dimIncrement>
<register>
<name>threshold</name>
<description>Priority Threshold Register</description>
<addressOffset>0x0</addressOffset>
<fields>
<field>
<name>priority</name>
<msb>2</msb><lsb>0</lsb>
<enumeratedValues>
<name>Priority</name>
<enumeratedValue>
<name>Never</name>
<description>Never interrupt</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>P1</name>
<description>Priority 1</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>P2</name>
<description>Priority 2</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>P3</name>
<description>Priority 3</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>P4</name>
<description>Priority 4</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>P5</name>
<description>Priority 5</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>P6</name>
<description>Priority 6</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>P7</name>
<description>Priority 7</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>claim</name>
<description>Claim/Complete Register</description>
<addressOffset>0x4</addressOffset>
<range>
<minimum>0x00000000</minimum>
<maximum>0xFFFFFFFF</maximum>
</range>
</register>
<register>
<name>_reserved</name>
<description>Padding to make sure targets is an array</description>
<addressOffset>0xffc</addressOffset>
</register>
</cluster>
</registers>
</peripheral>
<!-- PLIC -->
<!-- UARTHS -->
<peripheral>
<name>UARTHS</name>
<description>High-speed UART</description>
<groupName>UARTHS</groupName>
<baseAddress>0x38000000</baseAddress>
<registers>
<register>
<name>txdata</name>
<description>Transmit Data Register</description>
<addressOffset>0x00</addressOffset>
<fields>
<field>
<name>data</name>
<description>Transmit data</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>full</name>
<description>Transmit FIFO full</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>rxdata</name>
<description>Receive Data Register</description>
<addressOffset>0x04</addressOffset>
<fields>
<field>
<name>data</name>
<description>Received data</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>empty</name>
<description>Receive FIFO empty</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>txctrl</name>
<description>Transmit Control Register</description>
<addressOffset>0x08</addressOffset>
<fields>
<field>
<name>txen</name>
<description>Transmit enable</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>nstop</name>
<description>Number of stop bits</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>txcnt</name>
<description>Transmit watermark level</description>
<bitRange>[18:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>rxctrl</name>
<description>Receive Control Register</description>
<addressOffset>0x0C</addressOffset>
<fields>
<field>
<name>rxen</name>
<description>Receive enable</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>rxcnt</name>
<description>Receive watermark level</description>
<bitRange>[18:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>ie</name>
<description>Interrupt Enable Register</description>
<addressOffset>0x10</addressOffset>
<fields>
<field>
<name>txwm</name>
<description>Transmit watermark interrupt enable</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>rxwm</name>
<description>Receive watermark interrupt enable</description>
<bitRange>[1:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>ip</name>
<description>Interrupt Pending Register</description>
<addressOffset>0x14</addressOffset>
<fields>
<field>
<name>txwm</name>
<description>Transmit watermark interrupt pending</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>rxwm</name>
<description>Receive watermark interrupt pending</description>
<bitRange>[1:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>div</name>
<description>Baud Rate Divisor Register</description>
<addressOffset>0x18</addressOffset>
<fields>
<field>
<name>div</name>
<description>Baud rate divisor</description>
<bitRange>[15:0]</bitRange>
</field>
</fields>
</register>
</registers>
<interrupt>
<name>UARTHS</name>
<value>33</value>
</interrupt>
</peripheral>
<!-- UARTHS -->
<!-- GPIOHS -->
<peripheral>
<name>GPIOHS</name>
<description>High-speed GPIO</description>
<groupName>GPIOHS</groupName>
<baseAddress>0x38001000</baseAddress>
<registers>
<register>
<name>input_val</name>
<description>Input Value Register</description>
<addressOffset>0x000</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>32</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>input_en</name>
<description>Pin Input Enable Register</description>
<addressOffset>0x004</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>32</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>output_en</name>
<description>Pin Output Enable Register</description>
<addressOffset>0x008</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>32</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>output_val</name>
<description>Output Value Register</description>
<addressOffset>0x00C</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>32</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>pullup_en</name>
<description>Internal Pull-Up Enable Register</description>
<addressOffset>0x010</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>32</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>drive</name>
<description>Drive Strength Register</description>
<addressOffset>0x014</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>32</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>rise_ie</name>
<description>Rise Interrupt Enable Register</description>
<addressOffset>0x018</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>32</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>rise_ip</name>
<description>Rise Interrupt Pending Register</description>
<addressOffset>0x01C</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>32</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>fall_ie</name>
<description>Fall Interrupt Enable Register</description>
<addressOffset>0x020</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>32</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>fall_ip</name>
<description>Fall Interrupt Pending Register</description>
<addressOffset>0x024</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>32</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>high_ie</name>
<description>High Interrupt Enable Register</description>
<addressOffset>0x028</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>32</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>high_ip</name>
<description>High Interrupt Pending Register</description>
<addressOffset>0x02C</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>32</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>low_ie</name>
<description>Low Interrupt Enable Register</description>
<addressOffset>0x030</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>32</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>low_ip</name>
<description>Low Interrupt Pending Register</description>
<addressOffset>0x034</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>32</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>iof_en</name>
<description>HW I/O Function Enable Register</description>
<addressOffset>0x038</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>32</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>iof_sel</name>
<description>HW I/O Function Select Register</description>
<addressOffset>0x03C</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>32</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>output_xor</name>
<description>Output XOR (invert) Register</description>
<addressOffset>0x040</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>32</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
</registers>
<interrupt>
<name>GPIOHS0</name>
<value>34</value>
</interrupt>
<interrupt>
<name>GPIOHS1</name>
<value>35</value>
</interrupt>
<interrupt>
<name>GPIOHS2</name>
<value>36</value>
</interrupt>
<interrupt>
<name>GPIOHS3</name>
<value>37</value>
</interrupt>
<interrupt>
<name>GPIOHS4</name>
<value>38</value>
</interrupt>
<interrupt>
<name>GPIOHS5</name>
<value>39</value>
</interrupt>
<interrupt>
<name>GPIOHS6</name>
<value>40</value>
</interrupt>
<interrupt>
<name>GPIOHS7</name>
<value>41</value>
</interrupt>
<interrupt>
<name>GPIOHS8</name>
<value>42</value>
</interrupt>
<interrupt>
<name>GPIOHS9</name>
<value>43</value>
</interrupt>
<interrupt>
<name>GPIOHS10</name>
<value>44</value>
</interrupt>
<interrupt>
<name>GPIOHS11</name>
<value>45</value>
</interrupt>
<interrupt>
<name>GPIOHS12</name>
<value>46</value>
</interrupt>
<interrupt>
<name>GPIOHS13</name>
<value>47</value>
</interrupt>
<interrupt>
<name>GPIOHS14</name>
<value>48</value>
</interrupt>
<interrupt>
<name>GPIOHS15</name>
<value>49</value>
</interrupt>
<interrupt>
<name>GPIOHS16</name>
<value>50</value>
</interrupt>
<interrupt>
<name>GPIOHS17</name>
<value>51</value>
</interrupt>
<interrupt>
<name>GPIOHS18</name>
<value>52</value>
</interrupt>
<interrupt>
<name>GPIOHS19</name>
<value>53</value>
</interrupt>
<interrupt>
<name>GPIOHS20</name>
<value>54</value>
</interrupt>
<interrupt>
<name>GPIOHS21</name>
<value>55</value>
</interrupt>
<interrupt>
<name>GPIOHS22</name>
<value>56</value>
</interrupt>
<interrupt>
<name>GPIOHS23</name>
<value>57</value>
</interrupt>
<interrupt>
<name>GPIOHS24</name>
<value>58</value>
</interrupt>
<interrupt>
<name>GPIOHS25</name>
<value>59</value>
</interrupt>
<interrupt>
<name>GPIOHS26</name>
<value>60</value>
</interrupt>
<interrupt>
<name>GPIOHS27</name>
<value>61</value>
</interrupt>
<interrupt>
<name>GPIOHS28</name>
<value>62</value>
</interrupt>
<interrupt>
<name>GPIOHS29</name>
<value>63</value>
</interrupt>
<interrupt>
<name>GPIOHS30</name>
<value>64</value>
</interrupt>
<interrupt>
<name>GPIOHS31</name>
<value>65</value>
</interrupt>
</peripheral>
<!-- GPIOHS -->
<!-- KPU -->
<peripheral>
<name>KPU</name>
<description>Neural Network Accelerator</description>
<groupName>KPU</groupName>
<baseAddress>0x40800000</baseAddress>
<!-- TODO <size>64</size> -->
<registers>
<register>
<name>layer_argument_fifo</name>
<description>Layer arguments FIFO: each layer is defined by writing 12 successive argument values to this register</description>
<addressOffset>0x00</addressOffset>
<size>64</size>
</register>
<register>
<name>interrupt_status</name>
<description>Interrupt status</description>
<addressOffset>0x08</addressOffset>
<size>64</size>
<fields>
<field>
<name>calc_done</name>
<description>Interrupt raised when calculation is done</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>layer_cfg_almost_empty</name>
<description>Interrupt raised when layer arguments FIFO almost empty</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>layer_cfg_almost_full</name>
<description>Interrupt raised when layer arguments FIFO almost full</description>
<bitRange>[2:2]</bitRange>
</field>
</fields>
</register>
<register derivedFrom="interrupt_status">
<name>interrupt_raw</name>
<description>Interrupt raw</description>
<addressOffset>0x10</addressOffset>
<size>64</size>
</register>
<register derivedFrom="interrupt_status">
<name>interrupt_mask</name>
<description>Interrupt mask: 0 enables the interrupt, 1 masks the interrupt</description>
<addressOffset>0x18</addressOffset>
<size>64</size>
</register>
<register derivedFrom="interrupt_status">
<name>interrupt_clear</name>
<description>Interrupt clear: write 1 to a bit to clear interrupt</description>
<addressOffset>0x20</addressOffset>
<size>64</size>
</register>
<register>
<name>fifo_threshold</name>
<description>FIFO threshold</description>
<addressOffset>0x28</addressOffset>
<size>64</size>
<fields>
<field>
<name>full_threshold</name>
<description>FIFO full threshold</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>empty_threshold</name>
<description>FIFO empty threshold</description>
<bitRange>[7:4]</bitRange>
</field>
</fields>
</register>
<register>
<name>fifo_data_out</name>
<description>FIFO data output</description>
<addressOffset>0x30</addressOffset>
<size>64</size>
</register>
<register>
<name>fifo_ctrl</name>
<description>FIFO control</description>
<addressOffset>0x38</addressOffset>
<size>64</size>
<fields>
<field>
<name>dma_fifo_flush_n</name>
<description>Flush DMA FIFO</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>gs_fifo_flush_n</name>
<description>Flush GS FIFO</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>cfg_fifo_flush_n</name>
<description>Flush configuration FIFO</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>cmd_fifo_flush_n</name>
<description>Flush command FIFO</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>resp_fifo_flush_n</name>
<description>Flush response FIFO</description>
<bitRange>[4:4]</bitRange>
</field>
</fields>
</register>
<register>
<name>eight_bit_mode</name>
<description>Eight bit mode</description>
<addressOffset>0x40</addressOffset>
<size>64</size>
<fields>
<field>
<name>eight_bit_mode</name>
<description>Use 8-bit instead of 16-bit precision if set</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
</registers>
<interrupt>
<name>KPU</name>
<value>25</value>
</interrupt>
</peripheral>
<!-- KPU -->
<!-- FFT -->
<peripheral>
<name>FFT</name>
<description>Fast Fourier Transform Accelerator</description>
<groupName>FFT</groupName>
<baseAddress>0x42000000</baseAddress>
<registers>
<register>
<name>input_fifo</name>
<description>FFT input data fifo</description>
<addressOffset>0x00</addressOffset>
<size>64</size>
</register>
<register>
<name>ctrl</name>
<description>FFT control register</description>
<addressOffset>0x08</addressOffset>
<size>64</size>
<fields>
<field>
<name>point</name>
<description>FFT calculation data length</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>p512</name>
<description>512 point</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>p256</name>
<description>256 point</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>p128</name>
<description>128 point</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>p64</name>
<description>64 point</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>mode</name>
<description>FFT mode</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>fft</name>
<description>FFT mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ifft</name>
<description>Inverse FFT mode</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>shift</name>
<description>Corresponding to the nine layer butterfly shift operation, 0x0: does not shift; 0x1: shift 1st layer. ...</description>
<bitRange>[12:4]</bitRange>
</field>
<field>
<name>enable</name>
<description>FFT enable</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>dma_send</name>
<description>FFT DMA enable</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>input_mode</name>
<description>Input data arrangement</description>
<bitRange>[16:15]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>riri</name>
<description>RIRI (real imaginary interleaved)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>rrrr</name>
<description>RRRR (only real part)</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>rrii</name>
<description>First input the real part and then input the imaginary part</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>data_mode</name>
<description>Effective width of input data</description>
<bitRange>[17:17]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>width_64</name>
<description>64 bit effective</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>width_128</name>
<description>128 bit effective</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<!-- reserved bit 18..63 -->
</fields>
</register>
<register>
<name>fifo_ctrl</name>
<description>FIFO control</description>
<addressOffset>0x10</addressOffset>
<size>64</size>
<fields>
<field>
<name>resp_fifo_flush</name>
<description>Response memory initialization flag</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>cmd_fifo_flush</name>
<description>Command memory initialization flag</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>gs_fifo_flush</name>
<description>Output interface memory initialization flag</description>
<bitRange>[2:2]</bitRange>
</field>
<!-- reserved bit 3..63 -->
</fields>
</register>
<register>
<name>intr_mask</name>
<description>interrupt mask</description>
<addressOffset>0x18</addressOffset>
<size>64</size>
<fields>
<field>
<name>fft_done</name>
<description>FFT done</description>
<bitRange>[0:0]</bitRange>
</field>
<!-- reserved bit 1..63 -->
</fields>
</register>
<register>
<name>intr_clear</name>
<description>Interrupt clear</description>
<addressOffset>0x20</addressOffset>
<size>64</size>
<fields>
<field>
<name>fft_done</name>
<description>FFT done</description>
<bitRange>[0:0]</bitRange>
</field>
<!-- reserved bit 1..63 -->
</fields>
</register>
<register>
<name>status</name>
<description>FFT status register</description>
<addressOffset>0x28</addressOffset>
<size>64</size>
<fields>
<field>
<name>fft_done</name>
<description>FFT done</description>
<bitRange>[0:0]</bitRange>
</field>
<!-- reserved bit 1..63 -->
</fields>
</register>
<register>
<name>status_raw</name>
<description>FFT status raw</description>
<addressOffset>0x30</addressOffset>
<size>64</size>
<fields>
<field>
<name>fft_done</name>
<description>FFT done</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>fft_work</name>
<description>FFT work</description>
<bitRange>[1:1]</bitRange>
</field>
<!-- reserved bit 2..63 -->
</fields>
</register>
<register>
<name>output_fifo</name>
<description>FFT output FIFO</description>
<addressOffset>0x38</addressOffset>
<size>64</size>
</register>
</registers>
<interrupt>
<name>FFT</name>
<value>26</value>
</interrupt>
</peripheral>
<!-- FFT -->
<!-- DMAC -->
<peripheral>
<name>DMAC</name>
<description>Direct Memory Access Controller</description>
<groupName>DMAC</groupName>
<baseAddress>0x50000000</baseAddress>
<!-- TODO <size>64</size> -->
<registers>
<register>
<name>id</name>
<description>ID Register</description>
<addressOffset>0x00</addressOffset>
<size>64</size>
</register>
<register>
<name>compver</name>
<description>COMPVER Register</description>
<addressOffset>0x08</addressOffset>
<size>64</size>
</register>
<register>
<name>cfg</name>
<description>Configure Register</description>
<addressOffset>0x10</addressOffset>
<size>64</size>
<fields>
<field>
<name>dmac_en</name>
<description>Enable DMAC</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>int_en</name>
<description>Globally enable interrupt generation</description>
<bitRange>[1:1]</bitRange>
</field>
<!-- reserved bit 2..63 -->
</fields>
</register>
<register>
<name>chen</name>
<description>Channel Enable Register</description>
<addressOffset>0x18</addressOffset>
<size>64</size>
<fields>
<field>
<name>ch%s_en</name>
<description>Enable channel %s</description>
<bitRange>[0:0]</bitRange>
<dim>6</dim>
<dimIncrement>1</dimIncrement>
<dimIndex>1-6</dimIndex>
</field>
<!-- reserved bit 6..7 -->
<field>
<name>ch%s_en_we</name>
<description>Write enable channel %s</description>
<bitRange>[8:8]</bitRange>
<dim>6</dim>
<dimIncrement>1</dimIncrement>
<dimIndex>1-6</dimIndex>
</field>
<!-- reserved bit 14..15 -->
<field>
<name>ch%s_susp</name>
<description>Suspend request channel %s</description>
<bitRange>[16:16]</bitRange>
<dim>6</dim>
<dimIncrement>1</dimIncrement>
<dimIndex>1-6</dimIndex>
</field>
<!-- reserved bit 22.23 -->
<field>
<name>ch%s_susp_we</name>
<description>Enable write to ch%s_susp bit</description>
<bitRange>[24:24]</bitRange>
<dim>6</dim>
<dimIncrement>1</dimIncrement>
<dimIndex>1-6</dimIndex>
</field>
<!-- reserved bit 30..31 -->
<field>
<name>ch%s_abort</name>
<description>Abort request channel %s</description>
<bitRange>[32:32]</bitRange>
<dim>6</dim>
<dimIncrement>1</dimIncrement>
<dimIndex>1-6</dimIndex>
</field>
<!-- reserved bit 38..39 -->
<field>
<name>ch%s_abort_we</name>
<description>Enable write to ch%s_abort bit</description>
<bitRange>[40:40]</bitRange>
<dim>6</dim>
<dimIncrement>1</dimIncrement>
<dimIndex>1-6</dimIndex>
</field>
<!-- reserved bit 46..63 -->
</fields>
</register>
<!-- reserved: 0x20..0x2f -->
<register>
<name>intstatus</name>
<description>Interrupt Status Register</description>
<addressOffset>0x30</addressOffset>
<size>64</size>
<fields>
<field>
<name>ch%s_intstat</name>
<description>Channel %s interrupt bit</description>
<bitRange>[0:0]</bitRange>
<dim>6</dim>
<dimIncrement>1</dimIncrement>
<dimIndex>1-6</dimIndex>
</field>
<!-- reserved bit 6..15 -->
<field>
<name>commonreg_intstat</name>
<description>Common register status bit</description>
<bitRange>[16:16]</bitRange>
</field>
<!-- reserved bit 17..63 -->
</fields>
</register>
<register>
<name>com_intclear</name>
<description>Common Interrupt Clear Register</description>
<addressOffset>0x38</addressOffset>
<size>64</size>
<fields>
<field>
<name>slvif_dec_err</name>
<description>Clear slvif_dec_err interrupt in com_intstatus</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>slvif_wr2ro_err</name>
<description>Clear slvif_wr2ro_err interrupt in com_intstatus</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>slvif_rd2wo_err</name>
<description>Clear slvif_rd2wo_err interrupt in com_intstatus</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>slvif_wronhold_err</name>
<description>Clear slvif_wronhold_err interrupt in com_intstatus</description>
<bitRange>[3:3]</bitRange>
</field>
<!-- reserved bit 4..7 -->
<field>
<name>slvif_undefinedreg_dec_err</name>
<description>Clear slvif_undefinedreg_dec_err in com_intstatus</description>
<bitRange>[8:8]</bitRange>
</field>
<!-- reserved bit 9..63 -->
</fields>
</register>
<register>
<name>com_intstatus_en</name>
<description>Common Interrupt Status Enable Register</description>
<addressOffset>0x40</addressOffset>
<size>64</size>
<fields>
<field>
<name>slvif_dec_err</name>
<description>Slave Interface Common Register Decode Error</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>slvif_wr2ro_err</name>
<description>Slave Interface Common Register Write to Read only Error</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>slvif_rd2wo_err</name>
<description>Slave Interface Common Register Read to Write-only Error</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>slvif_wronhold_err</name>
<description>Slave Interface Common Register Write On Hold Error</description>
<bitRange>[3:3]</bitRange>
</field>
<!-- reserved bit 4..7 -->
<field>
<name>slvif_undefinedreg_dec_err</name>
<description>Slave Interface Undefined Register Decode Error</description>
<bitRange>[8:8]</bitRange>
</field>
<!-- reserved bit 9..63 -->
</fields>
</register>
<register>
<name>com_intsignal_en</name>
<description>Common Interrupt Signal Enable Register</description>
<addressOffset>0x48</addressOffset>
<size>64</size>
<fields>
<field>
<name>slvif_dec_err</name>
<description>Slave Interface Common Register Decode Error</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>slvif_wr2ro_err</name>
<description>Slave Interface Common Register Write to Read only Error</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>slvif_rd2wo_err</name>
<description>Slave Interface Common Register Read to Write-only Error</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>slvif_wronhold_err</name>
<description>Slave Interface Common Register Write On Hold Error</description>
<bitRange>[3:3]</bitRange>
</field>
<!-- reserved bit 4..7 -->
<field>
<name>slvif_undefinedreg_dec_err</name>
<description>Slave Interface Undefined Register Decode Error</description>
<bitRange>[8:8]</bitRange>
</field>
<!-- reserved bit 9..63 -->
</fields>
</register>
<register>
<name>com_intstatus</name>
<description>Common Interrupt Status</description>
<addressOffset>0x50</addressOffset>
<size>64</size>
<fields>
<field>
<name>slvif_dec_err</name>
<description>Slave Interface Common Register Decode Error</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>slvif_wr2ro_err</name>
<description>Slave Interface Common Register Write to Read only Error</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>slvif_rd2wo_err</name>
<description>Slave Interface Common Register Read to Write-only Error</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>slvif_wronhold_err</name>
<description>Slave Interface Common Register Write On Hold Error</description>
<bitRange>[3:3]</bitRange>
</field>
<!-- reserved bit 4..7 -->
<field>
<name>slvif_undefinedreg_dec_err</name>
<description>Slave Interface Undefined Register Decode Error</description>
<bitRange>[8:8]</bitRange>
</field>
<!-- reserved bit 9..63 -->
</fields>
</register>
<register>
<name>reset</name>
<description>Reset register</description>
<addressOffset>0x58</addressOffset>
<size>64</size>
<fields>
<field>
<name>rst</name>
<description>DMAC reset request bit</description>
<bitRange>[0:0]</bitRange>
</field>
<!-- reserved bit 1..63 -->
</fields>
</register>
<!-- reserved: 0x60..0xff -->
<cluster>
<name>channel[%s]</name>
<description>Channel configuration</description>
<dim>6</dim>
<addressOffset>0x100</addressOffset>
<dimIncrement>0x100</dimIncrement>
<size>64</size>
<register>
<name>sar</name>
<description>SAR Address Register</description>
<addressOffset>0x00</addressOffset>
</register>
<register>
<name>dar</name>
<description>DAR Address Register</description>
<addressOffset>0x08</addressOffset>
</register>
<register>
<name>block_ts</name>
<description>Block Transfer Size Register</description>
<addressOffset>0x10</addressOffset>
<fields>
<field>
<name>block_ts</name>
<description>Block transfer size</description>
<bitRange>[21:0]</bitRange>
</field>
<!-- reserved bit 22..63 -->
</fields>
</register>
<register>
<name>ctl</name>
<description>Control Register</description>
<addressOffset>0x18</addressOffset>
<fields>
<field>
<name>sms</name>
<description>Source master select</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>MASTER_SELECT</name>
<enumeratedValue>
<name>axi_master_1</name>
<description>AXI master 1</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>axi_master_2</name>
<description>AXI master 2</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<!-- reserved bit 1 -->
<field>
<name>dms</name>
<description>Destination master select</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues derivedFrom="MASTER_SELECT"/>
</field>
<!-- reserved bit 3 -->
<field>
<name>sinc</name>
<description>Source address increment</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>INCREMENT</name>
<enumeratedValue>
<name>increment</name>
<description>Increment address</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>nochange</name>
<description>Don't increment address</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<!-- reserved bit 5 -->
<field>
<name>dinc</name>
<description>Destination address increment</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues derivedFrom="INCREMENT"/>
</field>
<!-- reserved bit 7 -->
<field>
<name>src_tr_width</name>
<description>Source transfer width</description>
<bitRange>[10:8]</bitRange>
<enumeratedValues>
<name>TRANSFER_WIDTH</name>
<enumeratedValue>
<name>width_8</name>
<description>8 bits</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>width_16</name>
<description>16 bits</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>width_32</name>
<description>32 bits</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>width_64</name>
<description>64 bits</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>width_128</name>
<description>128 bits</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>width_256</name>
<description>256 bits</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>width_512</name>
<description>512 bits</description>
<value>6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>dst_tr_width</name>
<description>Destination transfer width</description>
<bitRange>[13:11]</bitRange>
<enumeratedValues derivedFrom="TRANSFER_WIDTH"/>
</field>
<field>
<name>src_msize</name>
<description>Source burst transaction length</description>
<bitRange>[17:14]</bitRange>
<enumeratedValues>
<name>BURST_LENGTH</name>
<enumeratedValue>
<name>length_1</name>
<description>1 data item</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>length_4</name>
<description>4 data items</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>length_8</name>
<description>8 data items</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>length_16</name>
<description>16 data items</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>length_32</name>
<description>32 data items</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>length_64</name>
<description>64 data items</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>length_128</name>
<description>128 data items</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>length_256</name>
<description>256 data items</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>length_512</name>
<description>512 data items</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>length_1024</name>
<description>1024 data items</description>
<value>9</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>dst_msize</name>
<description>Destination burst transaction length</description>
<bitRange>[21:18]</bitRange>
<enumeratedValues derivedFrom="BURST_LENGTH" />
</field>
<!-- reserved bit 22..29 -->
<field>
<name>nonposted_lastwrite_en</name>
<description>Non Posted Last Write Enable (posted writes may be used till the end of the block)</description>
<bitRange>[30:30]</bitRange>
</field>
<!-- reserved bit 31..37 -->
<field>
<name>arlen_en</name>
<description>Source burst length enable</description>
<bitRange>[38:38]</bitRange>
</field>
<field>
<name>arlen</name>
<description>Source burst length</description>
<bitRange>[46:39]</bitRange>
</field>
<field>
<name>awlen_en</name>
<description>Destination burst length enable</description>
<bitRange>[47:47]</bitRange>
</field>
<field>
<name>awlen</name>
<description>Destination burst length</description>
<bitRange>[55:48]</bitRange>
</field>
<field>
<name>src_stat_en</name>
<description>Source status enable</description>
<bitRange>[56:56]</bitRange>
</field>
<field>
<name>dst_stat_en</name>
<description>Destination status enable</description>
<bitRange>[57:57]</bitRange>
</field>
<field>
<name>ioc_blktfr</name>
<description>Interrupt completion of block transfer</description>
<bitRange>[58:58]</bitRange>
</field>
<!-- reserved bit 59..61 -->
<field>
<name>shadowreg_or_lli_last</name>
<description>Last shadow linked list item (indicates shadowreg/LLI content is the last one)</description>
<bitRange>[62:62]</bitRange>
</field>
<field>
<name>shadowreg_or_lli_valid</name>
<description>last shadow linked list item valid (indicate shadowreg/LLI content is valid)</description>
<bitRange>[63:63]</bitRange>
</field>
</fields>
</register>
<register>
<name>cfg</name>
<description>Configure Register</description>
<addressOffset>0x20</addressOffset>
<fields>
<field>
<name>src_multblk_type</name>
<description>Source multi-block transfer type</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>MULTIBLK_TRANSFER_TYPE</name>
<enumeratedValue>
<name>contiguous</name>
<description>Continuous multi-block type</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>reload</name>
<description>Reload multi-block type</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>shadow_register</name>
<description>Shadow register based multi-block type</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>linked_list</name>
<description>Linked list based multi-block type</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>dst_multblk_type</name>
<description>Destination multi-block transfer type</description>
<bitRange>[3:2]</bitRange>
<enumeratedValues derivedFrom="MULTIBLK_TRANSFER_TYPE" />
</field>
<!-- reserved bit 4..31 -->
<field>
<name>tt_fc</name>
<description>Transfer type and flow control</description>
<bitRange>[34:32]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>mem2mem_dma</name>
<description>Transfer memory to memory and flow controller is DMAC</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>mem2prf_dma</name>
<description>Transfer memory to peripheral and flow controller is DMAC</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>prf2mem_dma</name>
<description>Transfer peripheral to memory and flow controller is DMAC</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>prf2prf_dma</name>
<description>Transfer peripheral to peripheral and flow controller is DMAC</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>prf2mem_prf</name>
<description>Transfer peripheral to memory and flow controller is source peripheral</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>prf2prf_srcprf</name>
<description>Transfer peripheral to peripheral and flow controller is source peripheral</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>mem2prf_prf</name>
<description>Transfer memory to peripheral and flow controller is destination peripheral</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>prf2prf_dstprf</name>
<description>Transfer peripheral to peripheral and flow controller is destination peripheral</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hs_sel_src</name>
<description>Source software or hardware handshaking select</description>
<bitRange>[35:35]</bitRange>
<enumeratedValues>
<name>HANDSHAKING</name>
<enumeratedValue>
<name>hardware</name>
<description>Hardware handshaking is used</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>software</name>
<description>Software handshaking is used</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hs_sel_dst</name>
<description>Destination software or hardware handshaking select</description>
<bitRange>[36:36]</bitRange>
<enumeratedValues derivedFrom="HANDSHAKING" />
</field>
<field>
<name>src_hwhs_pol</name>
<description>Source hardware handshaking interface polarity</description>
<bitRange>[37:37]</bitRange>
<enumeratedValues>
<name>POLARITY</name>
<enumeratedValue>
<name>active_high</name>
<description>Active high</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>active_low</name>
<description>Active low</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>dst_hwhs_pol</name>
<description>Destination hardware handshaking interface polarity</description>
<bitRange>[38:38]</bitRange>
<enumeratedValues derivedFrom="POLARITY" />
</field>
<field>
<name>src_per</name>
<description>Assign a hardware handshaking interface to source of channel</description>
<bitRange>[42:39]</bitRange>
</field>
<!-- reserved bit 43 -->
<field>
<name>dst_per</name>
<description>Assign a hardware handshaking interface to destination of channel</description>
<bitRange>[47:44]</bitRange>
</field>
<!-- reserved bit 48 -->
<field>
<name>ch_prior</name>
<description>Channel priority (7 is highest, 0 is lowest)</description>
<bitRange>[51:49]</bitRange>
</field>
<field>
<name>lock_ch</name>
<description>Channel lock bit</description>
<bitRange>[52:52]</bitRange>
</field>
<field>
<name>lock_ch_l</name>
<description>Channel lock level</description>
<bitRange>[54:53]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>dma_transfer</name>
<description>Duration of channel is locked for entire DMA transfer</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>block_transfer</name>
<description>Duration of channel is locked for current block transfer</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>transaction</name>
<description>Duration of channel is locked for current transaction</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>src_osr_lmt</name>
<description>Source outstanding request limit</description>
<bitRange>[58:55]</bitRange>
</field>
<field>
<name>dst_osr_lmt</name>
<description>Destination outstanding request limit</description>
<bitRange>[62:59]</bitRange>
</field>
<!-- reserved bit 63 -->
</fields>
</register>
<register>
<name>llp</name>
<description>Linked List Pointer register</description>
<addressOffset>0x28</addressOffset>
<fields>
<field>
<name>lms</name>
<description>LLI master select</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues derivedFrom="ctl.sms.MASTER_SELECT" />
</field>
<!-- reserved bit 1..5 -->
<field>
<name>loc</name>
<description>Starting address memeory of LLI block</description>
<bitRange>[63:6]</bitRange>
</field>
</fields>
</register>
<register>
<name>status</name>
<description>Channel Status Register</description>
<addressOffset>0x30</addressOffset>
<fields>
<field>
<name>cmpltd_blk_size</name>
<description>Completed block transfer size</description>
<bitRange>[21:0]</bitRange>
</field>
<!-- reserved bit 22..63 -->
</fields>
</register>
<register>
<name>swhssrc</name>
<description>Channel Software handshake Source Register</description>
<addressOffset>0x38</addressOffset>
<fields>
<field>
<name>req</name>
<description>Software handshake request for channel source</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>req_we</name>
<description>Write enable bit for software handshake request</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>sglreq</name>
<description>Software handshake single request for channel source</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>sglreq_we</name>
<description>Write enable bit for software handshake</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>lst</name>
<description>Software handshake last request for channel source</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>lst_we</name>
<description>Write enable bit for software handshake last request</description>
<bitRange>[5:5]</bitRange>
</field>
<!-- reserved bits 6..63 -->
</fields>
</register>
<register>
<name>swhsdst</name>
<description>Channel Software handshake Destination Register</description>
<addressOffset>0x40</addressOffset>
<fields>
<field>
<name>req</name>
<description>Software handshake request for channel destination</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>req_we</name>
<description>Write enable bit for software handshake request</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>sglreq</name>
<description>Software handshake single request for channel destination</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>sglreq_we</name>
<description>Write enable bit for software handshake</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>lst</name>
<description>Software handshake last request for channel destination</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>lst_we</name>
<description>Write enable bit for software handshake last request</description>
<bitRange>[5:5]</bitRange>
</field>
<!-- reserved bits 6..63 -->
</fields>
</register>
<register>
<name>blk_tfr</name>
<description>Channel Block Transfer Resume Request Register</description>
<addressOffset>0x48</addressOffset>
<fields>
<field>
<name>resumereq</name>
<description>Block transfer resume request</description>
<bitRange>[0:0]</bitRange>
</field>
<!-- reserved bits 1..63 -->
</fields>
</register>
<register>
<name>axi_id</name>
<description>Channel AXI ID Register</description>
<addressOffset>0x50</addressOffset>
</register>
<register>
<name>axi_qos</name>
<description>AXI QOS Register</description>
<addressOffset>0x58</addressOffset>
</register>
<!-- reserved: 0x60..0x7f -->
<register>
<name>intstatus_en</name>
<description>Interrupt Status Enable Register</description>
<addressOffset>0x80</addressOffset>
<fields>
<field>
<name>block_tfr_done</name>
<description>Block transfer done</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>tfr_done</name>
<description>Transfer done</description>
<bitRange>[1:1]</bitRange>
</field>
<!-- reserved bit 2 -->
<field>
<name>src_transcomp</name>
<description>Source transaction complete</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>dst_transcomp</name>
<description>Destination transaction complete</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>src_dec_err</name>
<description>Source Decode Error</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>dst_dec_err</name>
<description>Destination Decode Error</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>src_slv_err</name>
<description>Source Slave Error</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>dst_slv_err</name>
<description>Destination Slave Error</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>lli_rd_dec_err</name>
<description>LLI Read Decode Error Status Enable</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>lli_wr_dec_err</name>
<description>LLI WRITE Decode Error</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>lli_rd_slv_err</name>
<description>LLI Read Slave Error</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>lli_wr_slv_err</name>
<description>LLI WRITE Slave Error</description>
<bitRange>[12:12]</bitRange>
</field>
<!-- reserved bit 13..63 -->
</fields>
</register>
<register>
<name>intstatus</name>
<description>Channel Interrupt Status Register</description>
<addressOffset>0x88</addressOffset>
<fields>
<field>
<name>block_tfr_done</name>
<description>Block transfer done</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>tfr_done</name>
<description>Transfer done</description>
<bitRange>[1:1]</bitRange>
</field>
<!-- reserved bit 2 -->
<field>
<name>src_transcomp</name>
<description>Source transaction complete</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>dst_transcomp</name>
<description>Destination transaction complete</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>src_dec_err</name>
<description>Source Decode Error</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>dst_dec_err</name>
<description>Destination Decode Error</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>src_slv_err</name>
<description>Source Slave Error</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>dst_slv_err</name>
<description>Destination Slave Error</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>lli_rd_dec_err</name>
<description>LLI Read Decode Error Status Enable</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>lli_wr_dec_err</name>
<description>LLI WRITE Decode Error</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>lli_rd_slv_err</name>
<description>LLI Read Slave Error</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>lli_wr_slv_err</name>
<description>LLI WRITE Slave Error</description>
<bitRange>[12:12]</bitRange>
</field>
<!-- reserved bit 13..63 -->
</fields>
</register>
<register>
<name>intsignal_en</name>
<description>Interrupt Signal Enable Register</description>
<addressOffset>0x90</addressOffset>
<fields>
<field>
<name>block_tfr_done</name>
<description>Block transfer done</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>tfr_done</name>
<description>Transfer done</description>
<bitRange>[1:1]</bitRange>
</field>
<!-- reserved bit 2 -->
<field>
<name>src_transcomp</name>
<description>Source transaction complete</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>dst_transcomp</name>
<description>Destination transaction complete</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>src_dec_err</name>
<description>Source Decode Error</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>dst_dec_err</name>
<description>Destination Decode Error</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>src_slv_err</name>
<description>Source Slave Error</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>dst_slv_err</name>
<description>Destination Slave Error</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>lli_rd_dec_err</name>
<description>LLI Read Decode Error Status Enable</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>lli_wr_dec_err</name>
<description>LLI WRITE Decode Error</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>lli_rd_slv_err</name>
<description>LLI Read Slave Error</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>lli_wr_slv_err</name>
<description>LLI WRITE Slave Error</description>
<bitRange>[12:12]</bitRange>
</field>
<!-- reserved bit 13..63 -->
</fields>
</register>
<register>
<name>intclear</name>
<description>Interrupt Clear Register</description>
<addressOffset>0x98</addressOffset>
<fields>
<field>
<name>block_tfr_done</name>
<description>Block transfer done</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>tfr_done</name>
<description>Transfer done</description>
<bitRange>[1:1]</bitRange>
</field>
<!-- reserved bit 2 -->
<field>
<name>src_transcomp</name>
<description>Source transaction complete</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>dst_transcomp</name>
<description>Destination transaction complete</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>src_dec_err</name>
<description>Source Decode Error</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>dst_dec_err</name>
<description>Destination Decode Error</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>src_slv_err</name>
<description>Source Slave Error</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>dst_slv_err</name>
<description>Destination Slave Error</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>lli_rd_dec_err</name>
<description>LLI Read Decode Error Status Enable</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>lli_wr_dec_err</name>
<description>LLI WRITE Decode Error</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>lli_rd_slv_err</name>
<description>LLI Read Slave Error</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>lli_wr_slv_err</name>
<description>LLI WRITE Slave Error</description>
<bitRange>[12:12]</bitRange>
</field>
<!-- reserved bit 13..63 -->
</fields>
</register>
<!-- reserved: 0xa0..0xff -->
<register>
<name>_reserved</name>
<description>Padding to make structure size 256 bytes so that channels[] is an array</description>
<addressOffset>0xf8</addressOffset>
</register>
</cluster>
</registers>
<interrupt>
<name>DMA0</name>
<value>27</value>
</interrupt>
<interrupt>
<name>DMA1</name>
<value>28</value>
</interrupt>
<interrupt>
<name>DMA2</name>
<value>29</value>
</interrupt>
<interrupt>
<name>DMA3</name>
<value>30</value>
</interrupt>
<interrupt>
<name>DMA4</name>
<value>31</value>
</interrupt>
<interrupt>
<name>DMA5</name>
<value>32</value>
</interrupt>
</peripheral>
<!-- DMAC -->
<!-- GPIO -->
<peripheral>
<name>GPIO</name>
<description>General Purpose Input/Output Interface</description>
<groupName>GPIO</groupName>
<baseAddress>0x50200000</baseAddress>
<registers>
<register>
<name>data_output</name>
<description>Data (output) registers</description>
<addressOffset>0x00</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>8</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>direction</name>
<description>Data direction registers</description>
<addressOffset>0x04</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>8</dim>
<dimIncrement>1</dimIncrement>
<enumeratedValues>
<name>DIRECTION</name>
<enumeratedValue>
<name>input</name>
<description>Pin is input</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>output</name>
<description>Pin is output</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>source</name>
<description>Data source registers</description>
<addressOffset>0x08</addressOffset>
</register>
<register>
<name>interrupt_enable</name>
<description>Interrupt enable/disable registers</description>
<addressOffset>0x30</addressOffset>
</register>
<register>
<name>interrupt_mask</name>
<description>Interrupt mask registers</description>
<addressOffset>0x34</addressOffset>
</register>
<register>
<name>interrupt_level</name>
<description>Interrupt level registers</description>
<addressOffset>0x38</addressOffset>
</register>
<register>
<name>interrupt_polarity</name>
<description>Interrupt polarity registers</description>
<addressOffset>0x3c</addressOffset>
</register>
<register>
<name>interrupt_status</name>
<description>Interrupt status registers</description>
<addressOffset>0x40</addressOffset>
</register>
<register>
<name>interrupt_status_raw</name>
<description>Raw interrupt status registers</description>
<addressOffset>0x44</addressOffset>
</register>
<register>
<name>interrupt_debounce</name>
<description>Interrupt debounce registers</description>
<addressOffset>0x48</addressOffset>
</register>
<register>
<name>interrupt_clear</name>
<description>Registers for clearing interrupts</description>
<addressOffset>0x4c</addressOffset>
</register>
<register>
<name>data_input</name>
<description>External port (data input) registers</description>
<addressOffset>0x50</addressOffset>
<fields>
<field>
<name>pin%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>8</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>sync_level</name>
<description>Sync level registers</description>
<addressOffset>0x60</addressOffset>
</register>
<register>
<name>id_code</name>
<description>ID code</description>
<addressOffset>0x64</addressOffset>
</register>
<register>
<name>interrupt_bothedge</name>
<description>Interrupt both edge type</description>
<addressOffset>0x68</addressOffset>
</register>
</registers>
<interrupt>
<name>APB_GPIO</name>
<value>23</value>
</interrupt>
</peripheral>
<!-- GPIO -->
<!-- UART1 -->
<peripheral>
<name>UART1</name>
<description>Universal Asynchronous Receiver-Transmitter 1</description>
<groupName>UART</groupName>
<baseAddress>0x50210000</baseAddress>
<registers>
<register>
<name>rbr_dll_thr</name>
<description>Receive Buffer Register / Divisor Latch (Low) / Transmit Holding Register (depending on context and R/W)</description>
<addressOffset>0x00</addressOffset>
</register>
<register>
<name>dlh_ier</name>
<description>Divisor Latch (High) / Interrupt Enable Register</description>
<addressOffset>0x04</addressOffset>
</register>
<register>
<name>fcr_iir</name>
<description>FIFO Control Register / Interrupt Identification Register</description>
<addressOffset>0x08</addressOffset>
</register>
<register>
<name>lcr</name>
<description>Line Control Register</description>
<addressOffset>0x0c</addressOffset>
</register>
<register>
<name>mcr</name>
<description>Modem Control Register</description>
<addressOffset>0x10</addressOffset>
</register>
<register>
<name>lsr</name>
<description>Line Status Register</description>
<addressOffset>0x14</addressOffset>
</register>
<register>
<name>msr</name>
<description>Modem Status Register</description>
<addressOffset>0x18</addressOffset>
</register>
<register>
<name>scr</name>
<description>Scratchpad Register</description>
<addressOffset>0x1c</addressOffset>
</register>
<register>
<name>lpdll</name>
<description>Low Power Divisor Latch (Low) Register</description>
<addressOffset>0x20</addressOffset>
</register>
<register>
<name>lpdlh</name>
<description>Low Power Divisor Latch (High) Register</description>
<addressOffset>0x24</addressOffset>
</register>
<register>
<name>srbr_sthr[%s]</name>
<dim>16</dim>
<dimIncrement>4</dimIncrement>
<description>Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)</description>
<addressOffset>0x30</addressOffset>
</register>
<register>
<name>far</name>
<description>FIFO Access Register</description>
<addressOffset>0x70</addressOffset>
</register>
<register>
<name>tfr</name>
<description>Transmit FIFO Read Register</description>
<addressOffset>0x74</addressOffset>
</register>
<register>
<name>rfw</name>
<description>Receive FIFO Write Register</description>
<addressOffset>0x78</addressOffset>
</register>
<register>
<name>usr</name>
<description>UART Status Register</description>
<addressOffset>0x7c</addressOffset>
</register>
<register>
<name>tfl</name>
<description>Transmit FIFO Level</description>
<addressOffset>0x80</addressOffset>
</register>
<register>
<name>rfl</name>
<description>Receive FIFO Level</description>
<addressOffset>0x84</addressOffset>
</register>
<register>
<name>srr</name>
<description>Software Reset Register</description>
<addressOffset>0x88</addressOffset>
</register>
<register>
<name>srts</name>
<description>Shadow Request to Send Register</description>
<addressOffset>0x8c</addressOffset>
</register>
<register>
<name>sbcr</name>
<description>Shadow Break Control Register</description>
<addressOffset>0x90</addressOffset>
</register>
<register>
<name>sdmam</name>
<description>Shadow DMA Mode</description>
<addressOffset>0x94</addressOffset>
</register>
<register>
<name>sfe</name>
<description>Shadow FIFO Enable</description>
<addressOffset>0x98</addressOffset>
</register>
<register>
<name>srt</name>
<description>Shadow RCVR Trigger Register</description>
<addressOffset>0x9c</addressOffset>
</register>
<register>
<name>stet</name>
<description>Shadow TX Empty Trigger Register</description>
<addressOffset>0xa0</addressOffset>
</register>
<register>
<name>htx</name>
<description>Halt TX Regster</description>
<addressOffset>0xa4</addressOffset>
</register>
<register>
<name>dmasa</name>
<description>DMA Software Acknowledge Register</description>
<addressOffset>0xa8</addressOffset>
</register>
<register>
<name>tcr</name>
<description>Transfer Control Register</description>
<addressOffset>0xac</addressOffset>
</register>
<register>
<name>de_en</name>
<description>DE Enable Register</description>
<addressOffset>0xb0</addressOffset>
</register>
<register>
<name>re_en</name>
<description>RE Enable Register</description>
<addressOffset>0xb4</addressOffset>
</register>
<register>
<name>det</name>
<description>DE Assertion Time Register</description>
<addressOffset>0xb8</addressOffset>
</register>
<register>
<name>tat</name>
<description>Turn-Around Time Register</description>
<addressOffset>0xbc</addressOffset>
</register>
<register>
<name>dlf</name>
<description>Divisor Latch (Fractional) Register</description>
<addressOffset>0xc0</addressOffset>
</register>
<register>
<name>rar</name>
<description>Receive-Mode Address Register</description>
<addressOffset>0xc4</addressOffset>
</register>
<register>
<name>tar</name>
<description>Transmit-Mode Address Register</description>
<addressOffset>0xc8</addressOffset>
</register>
<register>
<name>lcr_ext</name>
<description>Line Control Register (Extended)</description>
<addressOffset>0xcc</addressOffset>
</register>
<register>
<name>cpr</name>
<description>Component Parameter Register</description>
<addressOffset>0xf4</addressOffset>
</register>
<register>
<name>ucv</name>
<description>UART Component Version</description>
<addressOffset>0xf8</addressOffset>
</register>
<register>
<name>ctr</name>
<description>Component Type Register</description>
<addressOffset>0xfc</addressOffset>
</register>
</registers>
<interrupt>
<name>UART1</name>
<value>11</value>
</interrupt>
</peripheral>
<!-- UART1 -->
<!-- UART2 -->
<peripheral derivedFrom="UART1">
<name>UART2</name>
<description>Universal Asynchronous Receiver-Transmitter 2</description>
<baseAddress>0x50220000</baseAddress>
<interrupt>
<name>UART2</name>
<value>12</value>
</interrupt>
</peripheral>
<!-- UART2 -->
<!-- UART3 -->
<peripheral derivedFrom="UART1">
<name>UART3</name>
<description>Universal Asynchronous Receiver-Transmitter 3</description>
<baseAddress>0x50230000</baseAddress>
<interrupt>
<name>UART3</name>
<value>13</value>
</interrupt>
</peripheral>
<!-- UART3 -->
<!-- SPI0 -->
<peripheral>
<name>SPI0</name>
<description>Serial Peripheral Interface 0 (master)</description>
<groupName>SPI</groupName>
<baseAddress>0x52000000</baseAddress>
<registers>
<register>
<!-- TODO -->
<name>ctrlr0</name>
<description>Control Register 0</description>
<addressOffset>0x00</addressOffset>
<fields>
<field>
<name>work_mode</name>
<description>WORK_MODE</description>
<bitRange>[7:6]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>mode0</name>
<description>MODE_0</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>mode1</name>
<description>MODE_1</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>mode2</name>
<description>MODE_2</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>mode3</name>
<description>MODE_3</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tmod</name>
<description>TRANSFER_MODE</description>
<bitRange>[9:8]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>trans_recv</name>
<description>TRANS_RECV</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>trans</name>
<description>TRANS</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>recv</name>
<description>RECV</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>eerom</name>
<description>EEROM</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>frame_format</name>
<description>FRAME_FORMAT</description>
<bitRange>[22:21]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>standard</name>
<description>STANDARD</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>dual</name>
<description>DUAL</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>quad</name>
<description>QUAD</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>octal</name>
<description>OCTAL</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>data_length</name>
<description>DATA_BIT_LENGTH</description>
<bitRange>[20:16]</bitRange>
<writeConstraint><range><minimum>3</minimum><maximum>31</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<!-- TODO -->
<name>ctrlr1</name>
<description>Control Register 1</description>
<addressOffset>0x04</addressOffset>
</register>
<register>
<!-- TODO -->
<name>ssienr</name>
<description>Enable Register</description>
<addressOffset>0x08</addressOffset>
</register>
<register>
<!-- TODO -->
<name>mwcr</name>
<description>Microwire Control Register</description>
<addressOffset>0x0c</addressOffset>
</register>
<register>
<!-- TODO -->
<name>ser</name>
<description>Slave Enable Register</description>
<addressOffset>0x10</addressOffset>
</register>
<register>
<!-- TODO -->
<name>baudr</name>
<description>Baud Rate Select</description>
<addressOffset>0x14</addressOffset>
</register>
<register>
<!-- TODO -->
<name>txftlr</name>
<description>Transmit FIFO Threshold Level</description>
<addressOffset>0x18</addressOffset>
</register>
<register>
<!-- TODO -->
<name>rxftlr</name>
<description>Receive FIFO Threshold Level</description>
<addressOffset>0x1c</addressOffset>
</register>
<register>
<!-- TODO -->
<name>txflr</name>
<description>Transmit FIFO Level Register</description>
<addressOffset>0x20</addressOffset>
</register>
<register>
<!-- TODO -->
<name>rxflr</name>
<description>Receive FIFO Level Register</description>
<addressOffset>0x24</addressOffset>
</register>
<register>
<!-- TODO -->
<name>sr</name>
<description>Status Register</description>
<addressOffset>0x28</addressOffset>
</register>
<register>
<!-- TODO -->
<name>imr</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x2c</addressOffset>
</register>
<register>
<!-- TODO -->
<name>isr</name>
<description>Interrupt Status Register</description>
<addressOffset>0x30</addressOffset>
</register>
<register>
<name>risr</name>
<description>Raw Interrupt Status Register</description>
<addressOffset>0x34</addressOffset>
</register>
<register>
<!-- TODO -->
<name>txoicr</name>
<description>Transmit FIFO Overflow Interrupt Clear Register</description>
<addressOffset>0x38</addressOffset>
</register>
<register>
<!-- TODO -->
<name>rxoicr</name>
<description>Receive FIFO Overflow Interrupt Clear Register</description>
<addressOffset>0x3c</addressOffset>
</register>
<register>
<!-- TODO -->
<name>rxuicr</name>
<description>Receive FIFO Underflow Interrupt Clear Register</description>
<addressOffset>0x40</addressOffset>
</register>
<register>
<!-- TODO -->
<name>msticr</name>
<description>Multi-Master Interrupt Clear Register</description>
<addressOffset>0x44</addressOffset>
</register>
<register>
<!-- TODO -->
<name>icr</name>
<description>Interrupt Clear Register</description>
<addressOffset>0x48</addressOffset>
</register>
<register>
<!-- TODO -->
<name>dmacr</name>
<description>DMA Control Register</description>
<addressOffset>0x4c</addressOffset>
</register>
<register>
<!-- TODO -->
<name>dmatdlr</name>
<description>DMA Transmit Data Level</description>
<addressOffset>0x50</addressOffset>
</register>
<register>
<!-- TODO -->
<name>dmardlr</name>
<description>DMA Receive Data Level</description>
<addressOffset>0x54</addressOffset>
</register>
<register>
<!-- TODO -->
<name>idr</name>
<description>Identification Register</description>
<addressOffset>0x58</addressOffset>
</register>
<register>
<!-- TODO -->
<name>ssic_version_id</name>
<description>DWC_ssi component version</description>
<addressOffset>0x5c</addressOffset>
</register>
<register>
<!-- TODO -->
<name>dr%s</name>
<description>Data Register</description>
<addressOffset>0x60</addressOffset>
<dim>36</dim>
<dimIndex>0-35</dimIndex>
<dimIncrement>0x4</dimIncrement>
</register>
<register>
<!-- TODO -->
<name>rx_sample_delay</name>
<description>RX Sample Delay Register</description>
<addressOffset>0xf0</addressOffset>
</register>
<register>
<!-- TODO -->
<name>spi_ctrlr0</name>
<description>SPI Control Register</description>
<addressOffset>0xf4</addressOffset>
<fields>
<field>
<name>aitm</name>
<description>instruction_address_trans_mode</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>standard</name>
<description>STANDARD</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>addr_standard</name>
<description>ADDR_STANDARD</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>as_frame_format</name>
<description>AS_FRAME_FORMAT</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>addr_length</name>
<description>ADDR_LENGTH</description>
<bitRange>[5:2]</bitRange>
</field>
<field>
<name>inst_length</name>
<description>INSTRUCTION_LENGTH</description>
<bitRange>[9:8]</bitRange>
</field>
<field>
<name>wait_cycles</name>
<description>WAIT_CYCLES</description>
<bitRange>[15:11]</bitRange>
<writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<!-- TODO -->
<name>xip_mode_bits</name>
<description>XIP Mode bits</description>
<addressOffset>0xfc</addressOffset>
</register>
<register>
<name>xip_incr_inst</name>
<description>XIP INCR transfer opcode</description>
<addressOffset>0x100</addressOffset>
</register>
<register>
<!-- TODO -->
<name>xip_wrap_inst</name>
<description>XIP WRAP transfer opcode</description>
<addressOffset>0x104</addressOffset>
</register>
<register>
<name>xip_ctrl</name>
<description>XIP Control Register</description>
<addressOffset>0x108</addressOffset>
</register>
<register>
<!-- TODO -->
<name>xip_ser</name>
<description>XIP Slave Enable Register</description>
<addressOffset>0x10c</addressOffset>
</register>
<register>
<!-- TODO -->
<name>xrxoicr</name>
<description>XIP Receive FIFO Overflow Interrupt Clear Register</description>
<addressOffset>0x110</addressOffset>
</register>
<register>
<!-- TODO -->
<name>xip_cnt_time_out</name>
<description>XIP time out register for continuous transfers</description>
<addressOffset>0x114</addressOffset>
</register>
<register>
<!-- TODO -->
<name>endian</name>
<description>ENDIAN</description>
<addressOffset>0x118</addressOffset>
</register>
</registers>
<interrupt>
<name>SPI0</name>
<value>1</value>
</interrupt>
</peripheral>
<!-- SPI0 -->
<!-- SPI1 -->
<peripheral derivedFrom="SPI0">
<name>SPI1</name>
<description>Serial Peripheral Interface 1 (master)</description>
<baseAddress>0x53000000</baseAddress>
<interrupt>
<name>SPI1</name>
<value>2</value>
</interrupt>
</peripheral>
<!-- SPI1 -->
<!-- SPI2 -->
<peripheral>
<name>SPI2</name>
<description>Serial Peripheral Interface 2 (slave)</description>
<baseAddress>0x50240000</baseAddress>
<registers>
<!-- TODO -->
<register>
<name>dummy</name>
<description>Dummy register: this peripheral is not implemented yet</description>
<addressOffset>0x00</addressOffset>
</register>
</registers>
<interrupt>
<name>SPI_SLAVE</name>
<value>3</value>
</interrupt>
</peripheral>
<!-- SPI2 -->
<!-- SPI3 -->
<peripheral>
<name>SPI3</name>
<description>Serial Peripheral Interface 3 (master)</description>
<baseAddress>0x54000000</baseAddress>
<registers>
<register>
<!-- TODO -->
<name>ctrlr0</name>
<description>Control Register 0</description>
<addressOffset>0x00</addressOffset>
<fields>
<field>
<name>data_length</name>
<description>DATA_BIT_LENGTH</description>
<bitRange>[4:0]</bitRange>
<writeConstraint><range><minimum>3</minimum><maximum>31</maximum></range></writeConstraint>
</field>
<field>
<name>work_mode</name>
<description>WORK_MODE</description>
<bitRange>[9:8]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>mode0</name>
<description>MODE_0</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>mode1</name>
<description>MODE_1</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>mode2</name>
<description>MODE_2</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>mode3</name>
<description>MODE_3</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tmod</name>
<description>TRANSFER_MODE</description>
<bitRange>[11:10]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>trans_recv</name>
<description>TRANS_RECV</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>trans</name>
<description>TRANS</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>recv</name>
<description>RECV</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>eerom</name>
<description>EEROM</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>frame_format</name>
<description>FRAME_FORMAT</description>
<bitRange>[23:22]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>standard</name>
<description>STANDARD</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>dual</name>
<description>DUAL</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>quad</name>
<description>QUAD</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>octal</name>
<description>OCTAL</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<!-- TODO -->
<name>ctrlr1</name>
<description>Control Register 1</description>
<addressOffset>0x04</addressOffset>
</register>
<register>
<!-- TODO -->
<name>ssienr</name>
<description>Enable Register</description>
<addressOffset>0x08</addressOffset>
</register>
<register>
<!-- TODO -->
<name>mwcr</name>
<description>Microwire Control Register</description>
<addressOffset>0x0c</addressOffset>
</register>
<register>
<!-- TODO -->
<name>ser</name>
<description>Slave Enable Register</description>
<addressOffset>0x10</addressOffset>
</register>
<register>
<!-- TODO -->
<name>baudr</name>
<description>Baud Rate Select</description>
<addressOffset>0x14</addressOffset>
</register>
<register>
<!-- TODO -->
<name>txftlr</name>
<description>Transmit FIFO Threshold Level</description>
<addressOffset>0x18</addressOffset>
</register>
<register>
<!-- TODO -->
<name>rxftlr</name>
<description>Receive FIFO Threshold Level</description>
<addressOffset>0x1c</addressOffset>
</register>
<register>
<!-- TODO -->
<name>txflr</name>
<description>Transmit FIFO Level Register</description>
<addressOffset>0x20</addressOffset>
</register>
<register>
<!-- TODO -->
<name>rxflr</name>
<description>Receive FIFO Level Register</description>
<addressOffset>0x24</addressOffset>
</register>
<register>
<!-- TODO -->
<name>sr</name>
<description>Status Register</description>
<addressOffset>0x28</addressOffset>
</register>
<register>
<!-- TODO -->
<name>imr</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x2c</addressOffset>
</register>
<register>
<!-- TODO -->
<name>isr</name>
<description>Interrupt Status Register</description>
<addressOffset>0x30</addressOffset>
</register>
<register>
<name>risr</name>
<description>Raw Interrupt Status Register</description>
<addressOffset>0x34</addressOffset>
</register>
<register>
<!-- TODO -->
<name>txoicr</name>
<description>Transmit FIFO Overflow Interrupt Clear Register</description>
<addressOffset>0x38</addressOffset>
</register>
<register>
<!-- TODO -->
<name>rxoicr</name>
<description>Receive FIFO Overflow Interrupt Clear Register</description>
<addressOffset>0x3c</addressOffset>
</register>
<register>
<!-- TODO -->
<name>rxuicr</name>
<description>Receive FIFO Underflow Interrupt Clear Register</description>
<addressOffset>0x40</addressOffset>
</register>
<register>
<!-- TODO -->
<name>msticr</name>
<description>Multi-Master Interrupt Clear Register</description>
<addressOffset>0x44</addressOffset>
</register>
<register>
<!-- TODO -->
<name>icr</name>
<description>Interrupt Clear Register</description>
<addressOffset>0x48</addressOffset>
</register>
<register>
<!-- TODO -->
<name>dmacr</name>
<description>DMA Control Register</description>
<addressOffset>0x4c</addressOffset>
</register>
<register>
<!-- TODO -->
<name>dmatdlr</name>
<description>DMA Transmit Data Level</description>
<addressOffset>0x50</addressOffset>
</register>
<register>
<!-- TODO -->
<name>dmardlr</name>
<description>DMA Receive Data Level</description>
<addressOffset>0x54</addressOffset>
</register>
<register>
<!-- TODO -->
<name>idr</name>
<description>Identification Register</description>
<addressOffset>0x58</addressOffset>
</register>
<register>
<!-- TODO -->
<name>ssic_version_id</name>
<description>DWC_ssi component version</description>
<addressOffset>0x5c</addressOffset>
</register>
<register>
<!-- TODO -->
<name>dr%s</name>
<description>Data Register</description>
<addressOffset>0x60</addressOffset>
<dim>36</dim>
<dimIndex>0-35</dimIndex>
<dimIncrement>0x4</dimIncrement>
</register>
<register>
<!-- TODO -->
<name>rx_sample_delay</name>
<description>RX Sample Delay Register</description>
<addressOffset>0xf0</addressOffset>
</register>
<register>
<!-- TODO -->
<name>spi_ctrlr0</name>
<description>SPI Control Register</description>
<addressOffset>0xf4</addressOffset>
<fields>
<field>
<name>aitm</name>
<description>instruction_address_trans_mode</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>standard</name>
<description>STANDARD</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>addr_standard</name>
<description>ADDR_STANDARD</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>as_frame_format</name>
<description>AS_FRAME_FORMAT</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>addr_length</name>
<description>ADDR_LENGTH</description>
<bitRange>[5:2]</bitRange>
</field>
<field>
<name>inst_length</name>
<description>INSTRUCTION_LENGTH</description>
<bitRange>[9:8]</bitRange>
</field>
<field>
<name>wait_cycles</name>
<description>WAIT_CYCLES</description>
<bitRange>[15:11]</bitRange>
<writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<!-- TODO -->
<name>xip_mode_bits</name>
<description>XIP Mode bits</description>
<addressOffset>0xfc</addressOffset>
</register>
<register>
<name>xip_incr_inst</name>
<description>XIP INCR transfer opcode</description>
<addressOffset>0x100</addressOffset>
</register>
<register>
<!-- TODO -->
<name>xip_wrap_inst</name>
<description>XIP WRAP transfer opcode</description>
<addressOffset>0x104</addressOffset>
</register>
<register>
<name>xip_ctrl</name>
<description>XIP Control Register</description>
<addressOffset>0x108</addressOffset>
</register>
<register>
<!-- TODO -->
<name>xip_ser</name>
<description>XIP Slave Enable Register</description>
<addressOffset>0x10c</addressOffset>
</register>
<register>
<!-- TODO -->
<name>xrxoicr</name>
<description>XIP Receive FIFO Overflow Interrupt Clear Register</description>
<addressOffset>0x110</addressOffset>
</register>
<register>
<!-- TODO -->
<name>xip_cnt_time_out</name>
<description>XIP time out register for continuous transfers</description>
<addressOffset>0x114</addressOffset>
</register>
<register>
<!-- TODO -->
<name>endian</name>
<description>ENDIAN</description>
<addressOffset>0x118</addressOffset>
</register>
</registers>
<interrupt>
<name>SPI3</name>
<value>4</value>
</interrupt>
</peripheral>
<!-- SPI3 -->
<!-- I2S0 -->
<peripheral>
<name>I2S0</name>
<description>Inter-Integrated Sound Interface 0</description>
<groupName>I2S</groupName>
<baseAddress>0x50250000</baseAddress>
<registers>
<!-- TODO -->
<register>
<name>ier</name>
<description>Enable Register</description>
<addressOffset>0x00</addressOffset>
<fields>
<field>
<name>ien</name>
<description>I2S Enable</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>irer</name>
<description>Receiver Block Enable Register</description>
<addressOffset>0x04</addressOffset>
<fields>
<field>
<name>rxen</name>
<description>Receiver block enable</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>iter</name>
<description>Transmitter Block Enable Register</description>
<addressOffset>0x08</addressOffset>
<fields>
<field>
<name>txen</name>
<description>Transmitter block enable</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>cer</name>
<description>Clock Generation enable</description>
<addressOffset>0x0c</addressOffset>
<fields>
<field>
<name>clken</name>
<description>Transmitter block enable</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>ccr</name>
<description>Clock Configuration Register</description>
<addressOffset>0x10</addressOffset>
<fields>
<field>
<name>clk_gate</name>
<description>Gating of sclk</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>no</name>
<description>Clock gating is disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>cycles12</name>
<description>Gating after 12 sclk cycles</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>cycles16</name>
<description>Gating after 16 sclk cycles</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>cycles20</name>
<description>Gating after 20 sclk cycles</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>cycles24</name>
<description>Gating after 24 sclk cycles</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>clk_word_size</name>
<description>The number of sclk cycles for which the word select line stayd in the left aligned or right aligned mode</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>cycles16</name>
<description>16 sclk cycles</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>cycles24</name>
<description>24 sclk cycles</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>cycles32</name>
<description>32 sclk cycles</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>align_mode</name>
<description>Alignment mode setting</description>
<bitRange>[7:5]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>standard</name>
<description>Standard I2S format</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>right</name>
<description>Right aligned format</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>left</name>
<description>Left aligned format</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>dma_tx_en</name>
<description>DMA transmit enable control</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>dma_rx_en</name>
<description>DMA receive enable control</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>dma_divide_16</name>
<description>Split 32bit data to two 16 bit data and filled in left and right channel. Used with dma_tx_en or dma_rx_en</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>sign_expand_en</name>
<description>SIGN_EXPAND_EN</description>
<bitRange>[11:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>rxffr</name>
<description>Receiver Block FIFO Reset Register</description>
<addressOffset>0x14</addressOffset>
<fields>
<field>
<name>rxffr</name>
<description>Receiver FIFO reset</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>FLUSH</name>
<enumeratedValue>
<name>not_flush</name>
<description>Not flush FIFO</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>flush</name>
<description>Flush FIFO</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>txffr</name>
<description>Transmitter Block FIFO Reset Register</description>
<addressOffset>0x18</addressOffset>
<fields>
<field>
<name>rxffr</name>
<description>Transmitter FIFO reset</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues derivedFrom = "rxffr.rxffr.FLUSH">
</enumeratedValues>
</field>
</fields>
</register>
<cluster>
<name>channel%s</name>
<description>Channel cluster</description>
<addressOffset>0x20</addressOffset>
<dim>4</dim>
<dimIndex>0-3</dimIndex>
<dimIncrement>0x40</dimIncrement>
<register>
<!-- TODO -->
<name>left_rxtx</name>
<description>Left Receive or Left Transmit Register</description>
<addressOffset>0x00</addressOffset>
</register>
<register>
<name>right_rxtx</name>
<!-- TODO -->
<description>Right Receive or Right Transmit Register</description>
<addressOffset>0x04</addressOffset>
</register>
<register>
<name>rer</name>
<description>Receive Enable Register</description>
<addressOffset>0x08</addressOffset>
<fields>
<field>
<name>rxchenx</name>
<description>Receive channel enable/disable</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>ter</name>
<description>Transmit Enable Register</description>
<addressOffset>0x0c</addressOffset>
<fields>
<field>
<name>txchenx</name>
<description>Transmit channel enable/disable</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>rcr</name>
<description>Receive Configuration Register</description>
<addressOffset>0x10</addressOffset>
<fields>
<field>
<name>wlen</name>
<description>Desired data resolution of receiver</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>WLEN</name>
<enumeratedValue>
<name>ignore</name>
<description>Ignore the word length</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>resolution12</name>
<description>12-bit data resolution of the receiver</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>resolution16</name>
<description>16-bit data resolution of the receiver</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>resolution20</name>
<description>20-bit data resolution of the receiver</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>resolution24</name>
<description>24-bit data resolution of the receiver</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>resolution32</name>
<description>32-bit data resolution of the receiver</description>
<value>5</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>tcr</name>
<description>Transmit Configuration Register</description>
<addressOffset>0x14</addressOffset>
<fields>
<field>
<name>wlen</name>
<description>Desired data resolution of transmitter</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues derivedFrom = "rcr.wlen.WLEN">
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>isr</name>
<description>Interrupt Status Register</description>
<addressOffset>0x18</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>rxda</name>
<description>Status of receiver data avaliable interrupt</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>rxfo</name>
<description>Status of data overrun interrupt for RX channel</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>txfe</name>
<description>Status of transmit empty triger interrupt</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>txfo</name>
<description>Status of data overrun interrupt for the TX channel</description>
<bitRange>[5:5]</bitRange>
</field>
</fields>
</register>
<register>
<name>imr</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x1c</addressOffset>
<fields>
<field>
<name>rxdam</name>
<description>Mask RX FIFO data avaliable interrupt</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>rxfom</name>
<description>Mask RX FIFO overrun interrupt</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>txfem</name>
<description>Mask TX FIFO empty interrupt</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>txfom</name>
<description>Mask TX FIFO overrun interrupt</description>
<bitRange>[5:5]</bitRange>
</field>
</fields>
</register>
<register>
<name>ror</name>
<description>Receive Overrun Register</description>
<addressOffset>0x20</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>rxcho</name>
<description>Read this bit to clear RX FIFO data overrun interrupt. 0x0 for RX FIFO write valid, 0x1 for RX FIFO write overrun</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>tor</name>
<description>Transmit Overrun Register</description>
<addressOffset>0x24</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>txcho</name>
<description>Read this bit to clear TX FIFO data overrun interrupt. 0x0 for TX FIFO write valid, 0x1 for TX FIFO write overrun</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>rfcr</name>
<description>Receive FIFO Configuration Register</description>
<addressOffset>0x28</addressOffset>
<fields>
<field>
<name>rxchdt</name>
<description>Trigger level in the RX FIFO at which the receiver data available interrupt generate</description>
<bitRange>[3:0]</bitRange>
<enumeratedValues>
<name>LEVEL</name>
<enumeratedValue>
<name>level1</name>
<description>Interrupt trigger when FIFO level is 1</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>level2</name>
<description>Interrupt trigger when FIFO level is 2</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>level3</name>
<description>Interrupt trigger when FIFO level is 3</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>level4</name>
<description>Interrupt trigger when FIFO level is 4</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>level5</name>
<description>Interrupt trigger when FIFO level is 5</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>level6</name>
<description>Interrupt trigger when FIFO level is 6</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>level7</name>
<description>Interrupt trigger when FIFO level is 7</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>level8</name>
<description>Interrupt trigger when FIFO level is 8</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>level9</name>
<description>Interrupt trigger when FIFO level is 9</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>level10</name>
<description>Interrupt trigger when FIFO level is 10</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>level11</name>
<description>Interrupt trigger when FIFO level is 11</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>level12</name>
<description>Interrupt trigger when FIFO level is 12</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>level13</name>
<description>Interrupt trigger when FIFO level is 13</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>level14</name>
<description>Interrupt trigger when FIFO level is 14</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>level15</name>
<description>Interrupt trigger when FIFO level is 15</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>level16</name>
<description>Interrupt trigger when FIFO level is 16</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>tfcr</name>
<description>Transmit FIFO Configuration Register</description>
<addressOffset>0x2c</addressOffset>
<fields>
<field>
<name>txchet</name>
<description>Trigger level in the TX FIFO at which the transmitter data available interrupt generate</description>
<bitRange>[3:0]</bitRange>
<enumeratedValues derivedFrom = "rfcr.rxchdt.LEVEL">
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>rff</name>
<description>Receive FIFO Flush Register</description>
<addressOffset>0x30</addressOffset>
<fields>
<field>
<name>rxchfr</name>
<description>Receiver channel FIFO reset</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>FLUSH</name>
<enumeratedValue>
<name>not_flush</name>
<description>Not flush an individual FIFO</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>flush</name>
<description>Flush an indiviadual FIFO</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>tff</name>
<description>Transmit FIFO Flush Register</description>
<addressOffset>0x34</addressOffset>
<fields>
<field>
<name>rtxchfr</name>
<description>Transmit channel FIFO reset</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues derivedFrom="rff.rxchfr.FLUSH">
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>_reserved%s</name>
<description>_RESERVED0</description>
<addressOffset>0x38</addressOffset>
<dim>2</dim>
<dimIndex>0-1</dimIndex>
<dimIncrement>0x4</dimIncrement>
</register>
</cluster>
<register>
<!-- TODO -->
<name>rxdma</name>
<description>Receiver Block DMA Register</description>
<addressOffset>0x1c0</addressOffset>
</register>
<register>
<!-- TODO -->
<name>rrxdma</name>
<description>Reset Receiver Block DMA Register</description>
<addressOffset>0x1c4</addressOffset>
</register>
<register>
<!-- TODO -->
<name>txdma</name>
<description>Transmitter Block DMA Register</description>
<addressOffset>0x1c8</addressOffset>
</register>
<register>
<!-- TODO -->
<name>rtxdma</name>
<description>Reset Transmitter Block DMA Register</description>
<addressOffset>0x1cc</addressOffset>
</register>
<register>
<name>i2s_comp_param_2</name>
<description>Component Parameter Register 2</description>
<addressOffset>0x1f0</addressOffset>
</register>
<register>
<name>i2s_comp_param_1</name>
<description>Component Parameter Register 1</description>
<addressOffset>0x1f4</addressOffset>
</register>
<register>
<name>i2s_comp_version_1</name>
<description>Component Version Register</description>
<addressOffset>0x1f8</addressOffset>
</register>
<register>
<name>i2s_comp_type</name>
<description>Component Type Register</description>
<addressOffset>0x1fc</addressOffset>
</register>
</registers>
<interrupt>
<name>I2S0</name>
<value>5</value>
</interrupt>
</peripheral>
<!-- I2S0 -->
<!-- APU -->
<peripheral>
<name>APU</name>
<description>Audio Processor</description>
<groupName>APU</groupName>
<baseAddress>0x50250200</baseAddress>
<registers>
<register>
<name>ch_cfg</name>
<description>Channel Config Register</description>
<addressOffset>0x00</addressOffset>
<fields>
<field>
<name>sound_ch_en</name>
<description>BF unit sound channel enable control bits</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>target_dir</name>
<description>Target direction select for valid voice output</description>
<bitRange>[11:8]</bitRange>
</field>
<field>
<name>audio_gain</name>
<description>Audio sample gain factor</description>
<bitRange>[22:12]</bitRange>
</field>
<!-- reserved bit 23 -->
<field>
<name>data_src_mode</name>
<description>Audio data source configure parameter</description>
<bitRange>[24:24]</bitRange>
</field>
<!-- reserved bit 27..25 -->
<field>
<name>we_sound_ch_en</name>
<description>Write enable for sound_ch_en parameter</description>
<bitRange>[28:28]</bitRange>
<access>write-only</access>
</field>
<field>
<name>we_target_dir</name>
<description>Write enable for target_dir parameter</description>
<bitRange>[29:29]</bitRange>
<access>write-only</access>
</field>
<field>
<name>we_audio_gain</name>
<description>Write enable for audio_gain parameter</description>
<bitRange>[30:30]</bitRange>
<access>write-only</access>
</field>
<field>
<name>we_data_src_mode</name>
<description>Write enable for data_out_mode parameter</description>
<bitRange>[31:31]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>ctl</name>
<description>Control Register</description>
<addressOffset>0x04</addressOffset>
<fields>
<field>
<name>dir_search_en</name>
<description>Sound direction searching enable bit</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>search_path_reset</name>
<description>Reset all control logic on direction search processing path</description>
<bitRange>[1:1]</bitRange>
</field>
<!-- reserved bit 3..2 -->
<field>
<name>stream_gen_en</name>
<description>Valid voice sample stream generation enable bit</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>voice_gen_path_reset</name>
<description>Reset all control logic on voice stream generating path</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>update_voice_dir</name>
<description>Switch to a new voice source direction</description>
<bitRange>[6:6]</bitRange>
</field>
<!-- reserved bit 7 -->
<field>
<name>we_dir_search_en</name>
<description>Write enable for we_dir_search_en parameter</description>
<bitRange>[8:8]</bitRange>
<access>write-only</access>
</field>
<field>
<name>we_search_path_rst</name>
<description>Write enable for we_search_path_rst parameter</description>
<bitRange>[9:9]</bitRange>
<access>write-only</access>
</field>
<field>
<name>we_stream_gen</name>
<description>Write enable for we_stream_gen parameter</description>
<bitRange>[10:10]</bitRange>
<access>write-only</access>
</field>
<field>
<name>we_voice_gen_path_rst</name>
<description>Write enable for we_voice_gen_path_rst parameter</description>
<bitRange>[11:11]</bitRange>
<access>write-only</access>
</field>
<field>
<name>we_update_voice_dir</name>
<description>Write enable for we_update_voice_dir parameter</description>
<bitRange>[12:12]</bitRange>
<access>write-only</access>
</field>
<!-- reserved bit 13..31 -->
</fields>
</register>
<register>
<name>dir_bidx[%s]</name>
<description>Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)</description>
<addressOffset>0x08</addressOffset>
<dim>32</dim>
<dimIncrement>0x04</dimIncrement>
<fields>
<field>
<name>rd_idx%s</name>
<description>rd_idx%s</description>
<bitRange>[5:0]</bitRange>
<dim>4</dim>
<dimIncrement>8</dimIncrement>
</field>
<!-- reserved bit 7..6 -->
</fields>
</register>
<register>
<name>pre_fir0_coef[%s]</name>
<description>FIR0 pre-filter coefficients</description>
<addressOffset>0x88</addressOffset>
<dim>9</dim>
<dimIncrement>0x04</dimIncrement>
<fields>
<field>
<name>tap0</name>
<description>Tap 0</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>tap1</name>
<description>Tap 1</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register> <!-- duplicating fields: derivedFrom doesn't work for registers -->
<name>post_fir0_coef[%s]</name>
<description>FIR0 post-filter coefficients</description>
<addressOffset>0xac</addressOffset>
<dim>9</dim>
<dimIncrement>0x04</dimIncrement>
<fields>
<field>
<name>tap0</name>
<description>Tap 0</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>tap1</name>
<description>Tap 1</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register> <!-- duplicating fields: derivedFrom doesn't work for registers -->
<name>pre_fir1_coef[%s]</name>
<description>FIR1 pre-filter coeffecients</description>
<addressOffset>0xd0</addressOffset>
<dim>9</dim>
<dimIncrement>0x04</dimIncrement>
<fields>
<field>
<name>tap0</name>
<description>Tap 0</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>tap1</name>
<description>Tap 1</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register> <!-- duplicating fields: derivedFrom doesn't work for registers -->
<name>post_fir1_coef[%s]</name>
<description>FIR1 post-filter coefficients</description>
<addressOffset>0xf4</addressOffset>
<dim>9</dim>
<dimIncrement>0x04</dimIncrement>
<fields>
<field>
<name>tap0</name>
<description>Tap 0</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>tap1</name>
<description>Tap 1</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>dwsz_cfg</name>
<description>Downsize Config Register</description>
<addressOffset>0x118</addressOffset>
<fields>
<field>
<name>dir_dwn_siz_rate</name>
<description>Down-sizing ratio used for direction searching</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>voc_dwn_siz_rate</name>
<description>Down-sizing ratio used for voice stream generation</description>
<bitRange>[7:4]</bitRange>
</field>
<field>
<name>smpl_shift_bits</name>
<description>Sample precision reduction when the source sound sample precision is 20/24/32 bits</description>
<bitRange>[12:8]</bitRange>
</field>
<!-- reserved bits 31..13 -->
</fields>
</register>
<register>
<name>fft_cfg</name>
<description>FFT Config Register</description>
<addressOffset>0x11c</addressOffset>
<field>
<name>fft_shift_factor</name>
<description>FFT shift factor</description>
<bitRange>[8:0]</bitRange>
</field>
<!-- reserved bits 9..11 -->
<field>
<name>fft_enable</name>
<description>FFT enable</description>
<bitRange>[12:12]</bitRange>
</field>
<!-- reserved bits 31..13 -->
</register>
<register>
<name>sobuf_dma_rdata</name>
<description>Read register for DMA to sample-out buffers</description>
<addressOffset>0x120</addressOffset>
</register>
<register>
<name>vobuf_dma_rdata</name>
<description>Read register for DMA to voice-out buffers</description>
<addressOffset>0x124</addressOffset>
</register>
<register>
<name>int_stat</name>
<description>Interrupt Status Register</description>
<addressOffset>0x128</addressOffset>
<fields>
<field>
<name>dir_search_data_rdy</name>
<description>Sound direction searching data ready interrupt event</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>voc_buf_data_rdy</name>
<description>Voice output stream buffer data ready interrupt event</description>
<bitRange>[1:1]</bitRange>
</field>
<!-- reserved bits 2..31 -->
</fields>
</register>
<register>
<name>int_mask</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x12c</addressOffset>
<fields>
<field>
<name>dir_search_data_rdy</name>
<description>Sound direction searching data ready interrupt event</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>voc_buf_data_rdy</name>
<description>Voice output stream buffer data ready interrupt event</description>
<bitRange>[1:1]</bitRange>
</field>
<!-- reserved bits 2..31 -->
</fields>
</register>
<register>
<name>sat_counter</name>
<description>Saturation Counter</description>
<addressOffset>0x130</addressOffset>
<fields>
<field>
<name>counter</name>
<description>Counter</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>total</name>
<description>Total</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>sat_limits</name>
<description>Saturation Limits</description>
<addressOffset>0x134</addressOffset>
<fields>
<field>
<name>upper</name>
<description>Upper limit</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>bottom</name>
<description>Bottom limit</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<!-- APU -->
<!-- I2S1 -->
<peripheral derivedFrom="I2S0">
<name>I2S1</name>
<description>Inter-Integrated Sound Interface 1</description>
<baseAddress>0x50260000</baseAddress>
<interrupt>
<name>I2S1</name>
<value>6</value>
</interrupt>
</peripheral>
<!-- I2S1 -->
<!-- I2S2 -->
<peripheral derivedFrom="I2S0">
<name>I2S2</name>
<description>Inter-Integrated Sound Interface 2</description>
<baseAddress>0x50270000</baseAddress>
<interrupt>
<name>I2S2</name>
<value>7</value>
</interrupt>
</peripheral>
<!-- I2S2 -->
<!-- I2C0 -->
<peripheral>
<name>I2C0</name>
<description>Inter-Integrated Circuit Bus 0</description>
<groupName>I2C</groupName>
<baseAddress>0x50280000</baseAddress>
<registers>
<register>
<name>con</name>
<description>Control Register</description>
<addressOffset>0x00</addressOffset>
<fields>
<field>
<name>master_mode</name>
<description>Master Mode</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>speed</name>
<description>Speed</description>
<bitRange>[2:1]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>standard</name>
<description>STANDARD</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>fast</name>
<description>FAST</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>highspeed</name>
<description>HIGHSPEED</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>addr_slave_width</name>
<description>Slave address width</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>b7</name>
<description>7-bit address</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>b10</name>
<description>10-bit address</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>restart_en</name>
<description>Enable Restart</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>slave_disable</name>
<description>Disable Slave</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>stop_det</name>
<description>STOP_DET_IFADDRESSED</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>tx_empty</name>
<description>TX_EMPTY_CTRL</description>
<bitRange>[8:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>tar</name>
<description>Target Address Register</description>
<addressOffset>0x04</addressOffset>
<fields>
<field>
<name>address</name>
<description>Target Address</description>
<bitRange>[9:0]</bitRange>
</field>
<field>
<name>gc</name>
<description>GC_OR_START</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>special</name>
<description>SPECIAL</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>addr_master_width</name>
<description>Master Address</description>
<bitRange>[12:12]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>b7</name>
<description>7-bit address</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>b10</name>
<description>10-bit address</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>sar</name>
<description>Slave Address Register</description>
<addressOffset>0x08</addressOffset>
<fields>
<field>
<name>address</name>
<description>Slave Address</description>
<bitRange>[9:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>data_cmd</name>
<description>Data Buffer and Command Register</description>
<addressOffset>0x10</addressOffset>
<fields>
<field>
<name>cmd</name>
<description>CMD</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>data</name>
<description>Data</description>
<bitRange>[7:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>ss_scl_hcnt</name>
<description>Standard Speed Clock SCL High Count Register</description>
<addressOffset>0x14</addressOffset>
<fields>
<field>
<name>count</name>
<description>COUNT</description>
<bitRange>[15:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>ss_scl_lcnt</name>
<description>Standard Speed Clock SCL Low Count Register</description>
<addressOffset>0x18</addressOffset>
<fields>
<field>
<name>count</name>
<description>COUNT</description>
<bitRange>[15:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>intr_stat</name>
<description>Interrupt Status Register</description>
<addressOffset>0x2c</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>rx_under</name>
<description>RX_UNDER</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>rx_over</name>
<description>RX_OVER</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>rx_full</name>
<description>RX_FULL</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>tx_over</name>
<description>TX_OVER</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>tx_empty</name>
<description>TX_EMPTY</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>rd_req</name>
<description>RD_REQ</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>tx_abrt</name>
<description>TX_ABRT</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>rx_done</name>
<description>RX_DONE</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>activity</name>
<description>ACTIVITY</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>stop_det</name>
<description>STOP_DET</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>start_det</name>
<description>START_DET</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>gen_call</name>
<description>GEN_CALL</description>
<bitRange>[11:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>intr_mask</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x30</addressOffset>
<fields>
<field>
<name>rx_under</name>
<description>RX_UNDER</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>rx_over</name>
<description>RX_OVER</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>rx_full</name>
<description>RX_FULL</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>tx_over</name>
<description>TX_OVER</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>tx_empty</name>
<description>TX_EMPTY</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>rd_req</name>
<description>RD_REQ</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>tx_abrt</name>
<description>TX_ABRT</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>rx_done</name>
<description>RX_DONE</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>activity</name>
<description>ACTIVITY</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>stop_det</name>
<description>STOP_DET</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>start_det</name>
<description>START_DET</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>gen_call</name>
<description>GEN_CALL</description>
<bitRange>[11:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>raw_intr_stat</name>
<description>Raw Interrupt Status Register</description>
<addressOffset>0x34</addressOffset>
<fields>
<field>
<name>rx_under</name>
<description>RX_UNDER</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>rx_over</name>
<description>RX_OVER</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>rx_full</name>
<description>RX_FULL</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>tx_over</name>
<description>TX_OVER</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>tx_empty</name>
<description>TX_EMPTY</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>rd_req</name>
<description>RD_REQ</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>tx_abrt</name>
<description>TX_ABRT</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>rx_done</name>
<description>RX_DONE</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>activity</name>
<description>ACTIVITY</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>stop_det</name>
<description>STOP_DET</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>start_det</name>
<description>START_DET</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>gen_call</name>
<description>GEN_CALL</description>
<bitRange>[11:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>rx_tl</name>
<description>Receive FIFO Threshold Register</description>
<addressOffset>0x38</addressOffset>
<fields>
<field>
<name>value</name>
<description>VALUE</description>
<bitRange>[2:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>tx_tl</name>
<description>Transmit FIFO Threshold Register</description>
<addressOffset>0x3c</addressOffset>
<fields>
<field>
<name>value</name>
<description>VALUE</description>
<bitRange>[2:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>clr_intr</name>
<description>Clear Combined and Individual Interrupt Register</description>
<addressOffset>0x40</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>clr</name>
<description>CLR</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>clr_rx_under</name>
<description>Clear RX_UNDER Interrupt Register</description>
<addressOffset>0x44</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>clr</name>
<description>CLR</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>clr_rx_over</name>
<description>Clear RX_OVER Interrupt Register</description>
<addressOffset>0x48</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>clr</name>
<description>CLR</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>clr_tx_over</name>
<description>Clear TX_OVER Interrupt Register</description>
<addressOffset>0x4c</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>clr</name>
<description>CLR</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>clr_rd_req</name>
<description>Clear RD_REQ Interrupt Register</description>
<addressOffset>0x50</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>clr</name>
<description>CLR</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>clr_tx_abrt</name>
<description>Clear TX_ABRT Interrupt Register</description>
<addressOffset>0x54</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>clr</name>
<description>CLR</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>clr_rx_done</name>
<description>Clear RX_DONE Interrupt Register</description>
<addressOffset>0x58</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>clr</name>
<description>CLR</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>clr_activity</name>
<description>Clear ACTIVITY Interrupt Register</description>
<addressOffset>0x5c</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>clr</name>
<description>CLR</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>clr_stop_det</name>
<description>Clear STOP_DET Interrupt Register</description>
<addressOffset>0x60</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>clr</name>
<description>CLR</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>clr_start_det</name>
<description>Clear START_DET Interrupt Register</description>
<addressOffset>0x64</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>clr</name>
<description>CLR</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>clr_gen_call</name>
<description>I2C Clear GEN_CALL Interrupt Register</description>
<addressOffset>0x68</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>clr</name>
<description>CLR</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>enable</name>
<description>Enable Register</description>
<addressOffset>0x6c</addressOffset>
<fields>
<field>
<name>enable</name>
<description>ENABLE</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>abort</name>
<description>ABORT</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>tx_cmd_block</name>
<description>TX_CMD_BLOCK</description>
<bitRange>[2:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>status</name>
<description>Status Register</description>
<addressOffset>0x70</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>activity</name>
<description>ACTIVITY</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>tfnf</name>
<description>TFNF</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>tfe</name>
<description>TFE</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>rfne</name>
<description>RFNE</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>rff</name>
<description>RFF</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>mst_activity</name>
<description>MST_ACTIVITY</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>slv_activity</name>
<description>SLV_ACTIVITY</description>
<bitRange>[6:6]</bitRange>
</field>
</fields>
</register>
<register>
<name>txflr</name>
<description>Transmit FIFO Level Register</description>
<addressOffset>0x74</addressOffset>
<fields>
<field>
<name>value</name>
<description>VALUE</description>
<bitRange>[2:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>rxflr</name>
<description>Receive FIFO Level Register</description>
<addressOffset>0x78</addressOffset>
<fields>
<field>
<name>value</name>
<description>VALUE</description>
<bitRange>[2:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>sda_hold</name>
<description>SDA Hold Time Length Register</description>
<addressOffset>0x7c</addressOffset>
<fields>
<field>
<name>tx</name>
<description>TX</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>rx</name>
<description>RX</description>
<bitRange>[23:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>tx_abrt_source</name>
<description>Transmit Abort Source Register</description>
<addressOffset>0x80</addressOffset>
<fields>
<field>
<name>addr7_noack</name>
<description>7B_ADDR_NOACK</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>addr1_10_noack</name>
<description>10B_ADDR1_NOACK</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>addr2_10_noack</name>
<description>10B_ADDR2_NOACK</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>txdata_noack</name>
<description>TXDATA_NOACK</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>gcall_noack</name>
<description>GCALL_NOACK</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>gcall_read</name>
<description>GCALL_READ</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>hs_ackdet</name>
<description>HS_ACKDET</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>sbyte_ackdet</name>
<description>SBYTE_ACKDET</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>hs_norstrt</name>
<description>HS_NORSTRT</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>sbyte_norstrt</name>
<description>SBYTE_NORSTRT</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>rd_10_norstrt</name>
<description>10B_RD_NORSTRT</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>master_dis</name>
<description>MASTER_DIS</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>mst_arblost</name>
<description>MST_ARBLOST</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>slvflush_txfifo</name>
<description>SLVFLUSH_TXFIFO</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>slv_arblost</name>
<description>SLV_ARBLOST</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>slvrd_intx</name>
<description>SLVRD_INTX</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>user_abrt</name>
<description>USER_ABRT</description>
<bitRange>[16:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>dma_cr</name>
<description>I2C DMA Control Register</description>
<addressOffset>0x88</addressOffset>
<fields>
<field>
<name>RDMAE</name>
<description>RDMAE</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>TDMAE</name>
<description>TDMAE</description>
<bitRange>[1:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>dma_tdlr</name>
<description>DMA Transmit Data Level Register</description>
<addressOffset>0x8c</addressOffset>
<fields>
<field>
<name>value</name>
<description>VALUE</description>
<bitRange>[2:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>dma_rdlr</name>
<description>DMA Receive Data Level Register</description>
<addressOffset>0x90</addressOffset>
<fields>
<field>
<name>value</name>
<description>VALUE</description>
<bitRange>[2:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>sda_setup</name>
<description>SDA Setup Register</description>
<addressOffset>0x94</addressOffset>
<fields>
<field>
<name>value</name>
<description>VALUE</description>
<bitRange>[7:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>general_call</name>
<description>ACK General Call Register</description>
<addressOffset>0x98</addressOffset>
<fields>
<field>
<name>call_enable</name>
<description>CALL_ENABLE</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>enable_status</name>
<description>Enable Status Register</description>
<addressOffset>0x9c</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>ic_enable</name>
<description>IC_ENABLE</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>slv_dis_busy</name>
<description>SLV_DIS_BUSY</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>slv_rx_data_lost</name>
<description>SLV_RX_DATA_LOST</description>
<bitRange>[2:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>fs_spklen</name>
<description>SS, FS or FM+ spike suppression limit</description>
<addressOffset>0xa0</addressOffset>
<fields>
<field>
<name>value</name>
<description>VALUE</description>
<bitRange>[7:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>comp_param_1</name>
<description>Component Parameter Register 1</description>
<addressOffset>0xf4</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>apb_data_width</name>
<description>APB_DATA_WIDTH</description>
<bitRange>[1:0]</bitRange>
</field>
<field>
<name>max_speed_mode</name>
<description>MAX_SPEED_MODE</description>
<bitRange>[3:2]</bitRange>
</field>
<field>
<name>hc_count_values</name>
<description>HC_COUNT_VALUES</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>intr_io</name>
<description>INTR_IO</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>has_dma</name>
<description>HAS_DMA</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>encoded_params</name>
<description>ENCODED_PARAMS</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>rx_buffer_depth</name>
<description>RX_BUFFER_DEPTH</description>
<bitRange>[15:8]</bitRange>
</field>
<field>
<name>tx_buffer_depth</name>
<description>TX_BUFFER_DEPTH</description>
<bitRange>[23:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>comp_version</name>
<description>Component Version Register</description>
<addressOffset>0xf8</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>value</name>
<description>VALUE</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>comp_type</name>
<description>Component Type Register</description>
<addressOffset>0xfc</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>value</name>
<description>VALUE</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
</registers>
<interrupt>
<name>I2C0</name>
<value>8</value>
</interrupt>
</peripheral>
<!-- I2C0 -->
<!-- I2C1 -->
<peripheral derivedFrom="I2C0">
<name>I2C1</name>
<description>Inter-Integrated Circuit Bus 1</description>
<baseAddress>0x50290000</baseAddress>
<interrupt>
<name>I2C1</name>
<value>9</value>
</interrupt>
</peripheral>
<!-- I2C1 -->
<!-- I2C2 -->
<peripheral derivedFrom="I2C0">
<name>I2C2</name>
<description>Inter-Integrated Circuit Bus 2</description>
<baseAddress>0x502A0000</baseAddress>
<interrupt>
<name>I2C2</name>
<value>10</value>
</interrupt>
</peripheral>
<!-- I2C2 -->
<!-- FPIOA -->
<peripheral>
<name>FPIOA</name>
<description>Field Programmable IO Array</description>
<groupName>FPIOA</groupName>
<baseAddress>0x502B0000</baseAddress>
<registers>
<register>
<dim>48</dim>
<dimIncrement>0x04</dimIncrement>
<name>io[%s]</name>
<description>FPIOA GPIO multiplexer io array</description>
<addressOffset>0x00</addressOffset>
<fields>
<field>
<name>ch_sel</name>
<description>Channel select from 256 input</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>ds</name>
<description>Driving selector</description>
<bitRange>[11:8]</bitRange>
</field>
<field>
<name>oe_en</name>
<description>Static output enable, will AND with OE_INV</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>oe_inv</name>
<description>Invert output enable</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>do_sel</name>
<description>Data output select: 0 for DO, 1 for OE</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>do_inv</name>
<description>Invert the result of data output select (DO_SEL)</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>pu</name>
<description>Pull up enable. 0 for nothing, 1 for pull up</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>pd</name>
<description>Pull down enable. 0 for nothing, 1 for pull down</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>sl</name>
<description>Slew rate control enable</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>ie_en</name>
<description>Static input enable, will AND with IE_INV</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>ie_inv</name>
<description>Invert input enable</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>di_inv</name>
<description>Invert Data input</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>st</name>
<description>Schmitt trigger</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>pad_di</name>
<description>Read current IO's data input</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x04</dimIncrement>
<name>tie_en[%s]</name>
<description>FPIOA GPIO multiplexer tie enable array</description>
<addressOffset>0xC0</addressOffset>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x04</dimIncrement>
<name>tie_val[%s]</name>
<description>FPIOA GPIO multiplexer tie value array</description>
<addressOffset>0xE0</addressOffset>
</register>
</registers>
</peripheral>
<!-- FPIOA -->
<!-- SHA256 -->
<peripheral>
<name>SHA256</name>
<description>SHA256 Accelerator</description>
<groupName>SHA256</groupName>
<baseAddress>0x502C0000</baseAddress>
<registers>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<name>result[%s]</name>
<description>Calculated SHA256 return value</description>
<addressOffset>0x00</addressOffset>
</register>
<register>
<name>data_in</name>
<description>SHA256 input data is written to this register</description>
<addressOffset>0x20</addressOffset>
</register>
<register>
<name>num_reg</name>
<description>Counters register</description>
<addressOffset>0x28</addressOffset>
<fields>
<field>
<name>data_cnt</name>
<description>The total amount of data calculated by SHA256 is set by this register, and the smallest unit is 512bit</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>data_num</name>
<description>Currently calculated block number. 512bit=1block</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>function_reg_0</name>
<description>Function configuration register 0</description>
<addressOffset>0x2C</addressOffset>
<fields>
<field>
<name>en</name>
<description>write:SHA256 enable register. read:Calculation completed flag</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>overflow</name>
<description>SHA256 calculation overflow flag</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>endian</name>
<description>Endian setting</description>
<bitRange>[16:16]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>le</name>
<description>Little endian</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>be</name>
<description>Big endian</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>function_reg_1</name>
<description>Function configuration register 1</description>
<addressOffset>0x34</addressOffset>
<fields>
<field>
<name>dma_en</name>
<description>SHA and DMA handshake signals enable. 1:enable; 0:disable</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>fifo_in_full</name>
<description>1:SHA256 input fifo is full; 0:not full</description>
<bitRange>[8:8]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<!-- SHA256 -->
<!-- TIMER0 -->
<peripheral>
<name>TIMER0</name>
<description>Timer 0</description>
<groupName>TIMER</groupName>
<baseAddress>0x502D0000</baseAddress>
<registers>
<cluster>
<name>channel%s</name>
<description>Channel cluster: load_count, current_value, control, eoi and intr_stat registers</description>
<addressOffset>0x0</addressOffset>
<dim>4</dim>
<dimIndex>0-3</dimIndex>
<dimIncrement>0x14</dimIncrement>
<register>
<!-- TODO -->
<name>load_count</name>
<description>Load Count Register</description>
<addressOffset>0x00</addressOffset>
</register>
<register>
<!-- TODO -->
<name>current_value</name>
<description>Current Value Register</description>
<addressOffset>0x04</addressOffset>
</register>
<register>
<name>control</name>
<description>Control Register</description>
<addressOffset>0x08</addressOffset>
<fields>
<field>
<name>enable</name>
<description>ENABLE</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>mode</name>
<description>MODE</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>free</name>
<description>FREE_MODE</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>user</name>
<description>USER_MODE</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>interrupt</name>
<description>INTERRUPT_MASK</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>pwm_enable</name>
<description>PWM_ENABLE</description>
<bitRange>[3:3]</bitRange>
</field>
</fields>
</register>
<register>
<!-- TODO -->
<name>eoi</name>
<description>Interrupt Clear Register</description>
<addressOffset>0x0c</addressOffset>
</register>
<register>
<!-- TODO -->
<name>intr_stat</name>
<description>Interrupt Status Register</description>
<addressOffset>0x10</addressOffset>
</register>
</cluster>
<register>
<!-- TODO -->
<name>intr_stat</name>
<description>Interrupt Status Register</description>
<addressOffset>0xa0</addressOffset>
</register>
<register>
<!-- TODO -->
<name>eoi</name>
<description>Interrupt Clear Register</description>
<addressOffset>0xa4</addressOffset>
</register>
<register>
<!-- TODO -->
<name>raw_intr_stat</name>
<description>Raw Interrupt Status Register</description>
<addressOffset>0xa8</addressOffset>
</register>
<register>
<!-- TODO -->
<name>comp_version</name>
<description>Component Version Register</description>
<addressOffset>0xac</addressOffset>
</register>
<register>
<!-- TODO -->
<name>load_count2%s</name>
<description>Load Count2 Register</description>
<addressOffset>0xb0</addressOffset>
<dim>4</dim>
<dimIndex>0-3</dimIndex>
<dimIncrement>0x4</dimIncrement>
</register>
</registers>
<interrupt>
<name>TIMER0A</name>
<value>14</value>
</interrupt>
<interrupt>
<name>TIMER0B</name>
<value>15</value>
</interrupt>
</peripheral>
<!-- TIMER0 -->
<!-- TIMER1 -->
<peripheral derivedFrom="TIMER0">
<name>TIMER1</name>
<description>Timer 1</description>
<baseAddress>0x502E0000</baseAddress>
<interrupt>
<name>TIMER1A</name>
<value>16</value>
</interrupt>
<interrupt>
<name>TIMER1B</name>
<value>17</value>
</interrupt>
</peripheral>
<!-- TIMER1 -->
<!-- TIMER2 -->
<peripheral derivedFrom="TIMER0">
<name>TIMER2</name>
<description>Timer 2</description>
<baseAddress>0x502F0000</baseAddress>
<interrupt>
<name>TIMER2A</name>
<value>18</value>
</interrupt>
<interrupt>
<name>TIMER2B</name>
<value>19</value>
</interrupt>
</peripheral>
<!-- TIMER2 -->
<!-- WDT0 -->
<peripheral>
<name>WDT0</name>
<description>Watchdog Timer 0</description>
<groupName>WDT</groupName>
<baseAddress>0x50400000</baseAddress>
<registers>
<register>
<name>cr</name>
<description>Control Register</description>
<addressOffset>0x00</addressOffset>
<fields>
<field>
<name>enable</name>
<description>enable</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>rmod</name>
<description>rmod</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>reset</name>
<description>RESET</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>interrupt</name>
<description>INTERRUPT</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rpl</name>
<description>rpl</description>
<bitRange>[4:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>torr</name>
<description>Timeout Range Register</description>
<addressOffset>0x04</addressOffset>
<fields>
<field>
<name>top0</name>
<description>top (lower half)</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>top1</name>
<description>top (upper half)</description>
<bitRange>[7:4]</bitRange>
</field>
</fields>
</register>
<register>
<name>ccvr</name>
<description>Current Counter Value Register</description>
<addressOffset>0x08</addressOffset>
</register>
<register>
<name>crr</name>
<description>Counter Restart Register</description>
<addressOffset>0x0c</addressOffset>
</register>
<register>
<name>stat</name>
<description>Interrupt Status Register</description>
<addressOffset>0x10</addressOffset>
<fields>
<field>
<name>stat</name>
<description>stat</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>eoi</name>
<description>Interrupt Clear Register</description>
<addressOffset>0x14</addressOffset>
<fields>
<field>
<name>eoi</name>
<description>eoi</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<!-- reserved 0x18 -->
<register>
<name>prot_level</name>
<description>Protection level Register</description>
<addressOffset>0x1c</addressOffset>
<fields>
<field>
<name>prot_level</name>
<description>prot_level</description>
<bitRange>[2:0]</bitRange>
</field>
</fields>
</register>
<!-- reserved 0x20..0xe0 -->
<register>
<name>comp_param_5</name>
<description>Component Parameters Register 5</description>
<addressOffset>0xe4</addressOffset>
<fields>
<field>
<name>user_top_max</name>
<description>user_top_max</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>comp_param_4</name>
<description>Component Parameters Register 4</description>
<addressOffset>0xe8</addressOffset>
<fields>
<field>
<name>user_top_init_max</name>
<description>user_top_init_max</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>comp_param_3</name>
<description>Component Parameters Register 3</description>
<addressOffset>0xec</addressOffset>
<fields>
<field>
<name>top_rst</name>
<description>top_rst</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>comp_param_2</name>
<description>Component Parameters Register 2</description>
<addressOffset>0xf0</addressOffset>
<fields>
<field>
<name>cnt_rst</name>
<description>cnt_rst</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>comp_param_1</name>
<description>Component Parameters Register 1</description>
<addressOffset>0xf4</addressOffset>
<fields>
<field>
<name>always_en</name>
<description>always_en</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>dflt_rmod</name>
<description>dflt_rmod</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>dual_top</name>
<description>dual_top</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>hc_rmod</name>
<description>hc_rmod</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>hc_rpl</name>
<description>hc_rpl</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>hc_top</name>
<description>hc_top</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>use_fix_top</name>
<description>use_fix_top</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>pause</name>
<description>pause</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>apb_data_width</name>
<description>apb_data_width</description>
<bitRange>[9:8]</bitRange>
</field>
<field>
<name>dflt_rpl</name>
<description>dflt_rpl</description>
<bitRange>[12:10]</bitRange>
</field>
<!-- reserved 13..15 -->
<field>
<name>dflt_top</name>
<description>dflt_top</description>
<bitRange>[19:16]</bitRange>
</field>
<field>
<name>dflt_top_init</name>
<description>dflt_top_init</description>
<bitRange>[23:20]</bitRange>
</field>
<field>
<name>cnt_width</name>
<description>cnt_width</description>
<bitRange>[28:24]</bitRange>
</field>
<!-- reserved 29..31 -->
</fields>
</register>
<register>
<name>comp_version</name>
<description>Component Version Register</description>
<addressOffset>0xf8</addressOffset>
</register>
<register>
<name>comp_type</name>
<description>Component Type Register</description>
<addressOffset>0xfc</addressOffset>
</register>
</registers>
<interrupt>
<name>WDT0</name>
<value>21</value>
</interrupt>
</peripheral>
<!-- WDT0 -->
<!-- WDT1 -->
<peripheral derivedFrom="WDT0">
<name>WDT1</name>
<description>Watchdog Timer 1</description>
<baseAddress>0x50410000</baseAddress>
<interrupt>
<name>WDT1</name>
<value>22</value>
</interrupt>
</peripheral>
<!-- WDT1 -->
<!-- OTP -->
<peripheral>
<name>OTP</name>
<description>One-Time Programmable Memory Controller</description>
<groupName>OTP</groupName>
<baseAddress>0x50420000</baseAddress>
<registers>
<!-- TODO -->
<register>
<name>dummy</name>
<description>Dummy register: this peripheral is not implemented yet</description>
<addressOffset>0x00</addressOffset>
</register>
</registers>
</peripheral>
<!-- OTP -->
<!-- DVP -->
<peripheral>
<name>DVP</name>
<description>Digital Video Port</description>
<groupName>DVP</groupName>
<baseAddress>0x50430000</baseAddress>
<registers>
<!-- TODO -->
<register>
<name>dvp_cfg</name>
<description>Config Register</description>
<addressOffset>0x00</addressOffset>
<fields>
<field>
<name>start_int_enable</name>
<description>START_INT_ENABLE</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>finish_int_enable</name>
<description>FINISH_INT_ENABLE</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>ai_output_enable</name>
<description>AI_OUTPUT_ENABLE</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>display_output_enable</name>
<description>DISPLAY_OUTPUT_ENABLE</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>auto_enable</name>
<description>AUTO_ENABLE</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>burst_size_4beats</name>
<description>BURST_SIZE_4BEATS</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>format</name>
<description>FORMAT</description>
<bitRange>[10:9]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>rgb</name>
<description>RGB_FORMAT</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>yuv</name>
<description>YUV_FORMAT</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>y</name>
<description>Y_FORMAT</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>href_burst_num</name>
<description>HREF_BURST_NUM</description>
<bitRange>[19:12]</bitRange>
</field>
<field>
<name>line_num</name>
<description>LINE_NUM</description>
<bitRange>[29:20]</bitRange>
</field>
</fields>
</register>
<register>
<name>r_addr</name>
<description>R_ADDR</description>
<addressOffset>0x04</addressOffset>
</register>
<register>
<name>g_addr</name>
<description>G_ADDR</description>
<addressOffset>0x08</addressOffset>
</register>
<register>
<name>b_addr</name>
<description>B_ADDR</description>
<addressOffset>0x0c</addressOffset>
</register>
<register>
<name>cmos_cfg</name>
<description>CMOS Config Register</description>
<addressOffset>0x10</addressOffset>
<fields>
<field>
<name>clk_div</name>
<description>CLK_DIV</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>clk_enable</name>
<description>CLK_ENABLE</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>reset</name>
<description>RESET</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>power_down</name>
<description>POWER_DOWN</description>
<bitRange>[24:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>sccb_cfg</name>
<description>SCCB Config Register</description>
<addressOffset>0x14</addressOffset>
<fields>
<field>
<name>byte_num</name>
<description>BYTE_NUM</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>num2</name>
<description>BYTE_NUM_2</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>num3</name>
<description>BYTE_NUM_3</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>num4</name>
<description>BYTE_NUM_4</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>scl_lcnt</name>
<description>SCL_LCNT</description>
<bitRange>[15:8]</bitRange>
</field>
<field>
<name>scl_hcnt</name>
<description>SCL_HCNT</description>
<bitRange>[23:16]</bitRange>
</field>
<field>
<name>rdata</name>
<description>RDATA</description>
<bitRange>[31:24]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>sccb_ctl</name>
<description>SCCB Control Register</description>
<addressOffset>0x18</addressOffset>
<fields>
<field>
<!-- WRITE_DATA_ENABLE -->
<name>device_address</name>
<description>DEVICE_ADDRESS</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>reg_address</name>
<description>REG_ADDRESS</description>
<bitRange>[15:8]</bitRange>
</field>
<field>
<name>wdata_byte0</name>
<description>WDATA_BYTE0</description>
<bitRange>[23:16]</bitRange>
</field>
<field>
<name>wdata_byte1</name>
<description>WDATA_BYTE1</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>axi</name>
<description>AXI Register</description>
<addressOffset>0x1c</addressOffset>
<fields>
<field>
<name>gm_mlen</name>
<description>GM_MLEN</description>
<bitRange>[7:0]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>byte1</name>
<description>GM_MLEN_1BYTE</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>byte4</name>
<description>GM_MLEN_4BYTE</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>sts</name>
<description>STS Register</description>
<addressOffset>0x20</addressOffset>
<fields>
<field>
<name>frame_start</name>
<description>FRAME_START</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>frame_start_we</name>
<description>FRAME_START_WE</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>frame_finish</name>
<description>FRAME_FINISH</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>frame_finish_we</name>
<description>FRAME_FINISH_WE</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>dvp_en</name>
<description>DVP_EN</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>dvp_en_we</name>
<description>DVP_EN_WE</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>sccb_en</name>
<description>SCCB_EN</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>sccb_en_we</name>
<description>SCCB_EN_WE</description>
<bitRange>[25:25]</bitRange>
</field>
</fields>
</register>
<register>
<name>reverse</name>
<description>REVERSE</description>
<addressOffset>0x24</addressOffset>
</register>
<register>
<name>rgb_addr</name>
<description>RGB_ADDR</description>
<addressOffset>0x28</addressOffset>
</register>
</registers>
<interrupt>
<name>DVP</name>
<value>24</value>
</interrupt>
</peripheral>
<!-- DVP -->
<!-- SYSCTL -->
<peripheral>
<name>SYSCTL</name>
<description>System Controller</description>
<groupName>SYSCTL</groupName>
<baseAddress>0x50440000</baseAddress>
<registers>
<register>
<name>git_id</name>
<description>Git short commit id</description>
<addressOffset>0x00</addressOffset>
</register>
<register>
<name>clk_freq</name>
<description>System clock base frequency</description>
<addressOffset>0x04</addressOffset>
</register>
<register>
<name>pll0</name>
<description>PLL0 controller</description>
<addressOffset>0x08</addressOffset>
<fields>
<field>
<name>clkr</name>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>clkf</name>
<bitRange>[9:4]</bitRange>
</field>
<field>
<name>clkod</name>
<bitRange>[13:10]</bitRange>
</field>
<field>
<name>bwadj</name>
<bitRange>[19:14]</bitRange>
</field>
<field>
<name>reset</name>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>pwrd</name>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>intfb</name>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>bypass</name>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>test</name>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>out_en</name>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>test_en</name>
<bitRange>[26:26]</bitRange>
</field>
</fields>
</register>
<register>
<name>pll1</name>
<description>PLL1 controller</description>
<addressOffset>0x0c</addressOffset>
<fields>
<field>
<name>clkr</name>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>clkf</name>
<bitRange>[9:4]</bitRange>
</field>
<field>
<name>clkod</name>
<bitRange>[13:10]</bitRange>
</field>
<field>
<name>bwadj</name>
<bitRange>[19:14]</bitRange>
</field>
<field>
<name>reset</name>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>pwrd</name>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>intfb</name>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>bypass</name>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>test</name>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>out_en</name>
<bitRange>[25:25]</bitRange>
</field>
</fields>
</register>
<register>
<name>pll2</name>
<description>PLL2 controller</description>
<addressOffset>0x10</addressOffset>
<fields>
<field>
<name>clkr</name>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>clkf</name>
<bitRange>[9:4]</bitRange>
</field>
<field>
<name>clkod</name>
<bitRange>[13:10]</bitRange>
</field>
<field>
<name>bwadj</name>
<bitRange>[19:14]</bitRange>
</field>
<field>
<name>reset</name>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>pwrd</name>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>intfb</name>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>bypass</name>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>test</name>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>out_en</name>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>ckin_sel</name>
<bitRange>[27:26]</bitRange>
</field>
</fields>
</register>
<register>
<name>pll_lock</name>
<description>PLL lock tester</description>
<addressOffset>0x18</addressOffset>
<fields>
<field>
<name>pll_lock0</name>
<bitRange>[1:0]</bitRange>
</field>
<field>
<name>pll_slip_clear0</name>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>test_clk_out0</name>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>pll_lock1</name>
<bitRange>[9:8]</bitRange>
</field>
<field>
<name>pll_slip_clear1</name>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>test_clk_out1</name>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>pll_lock2</name>
<bitRange>[17:16]</bitRange>
</field>
<field>
<name>pll_slip_clear2</name>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>test_clk_out2</name>
<bitRange>[19:19]</bitRange>
</field>
</fields>
</register>
<register>
<name>rom_error</name>
<description>AXI ROM detector</description>
<addressOffset>0x1c</addressOffset>
<fields>
<field>
<name>rom_mul_error</name>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>rom_one_error</name>
<bitRange>[1:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>clk_sel0</name>
<description>Clock select controller 0</description>
<addressOffset>0x20</addressOffset>
<fields>
<field>
<name>aclk_sel</name>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>aclk_divider_sel</name>
<bitRange>[2:1]</bitRange>
</field>
<field>
<name>apb0_clk_sel</name>
<bitRange>[5:3]</bitRange>
</field>
<field>
<name>apb1_clk_sel</name>
<bitRange>[8:6]</bitRange>
</field>
<field>
<name>apb2_clk_sel</name>
<bitRange>[11:9]</bitRange>
</field>
<field>
<name>spi3_clk_sel</name>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>timer0_clk_sel</name>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>timer1_clk_sel</name>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>timer2_clk_sel</name>
<bitRange>[15:15]</bitRange>
</field>
</fields>
</register>
<register>
<name>clk_sel1</name>
<description>Clock select controller 1</description>
<addressOffset>0x24</addressOffset>
<fields>
<field>
<name>spi3_sample_clk_sel</name>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>clk_en_cent</name>
<description>Central clock enable</description>
<addressOffset>0x28</addressOffset>
<fields>
<field>
<name>cpu_clk_en</name>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>sram0_clk_en</name>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>sram1_clk_en</name>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>apb0_clk_en</name>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>apb1_clk_en</name>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>apb2_clk_en</name>
<bitRange>[5:5]</bitRange>
</field>
</fields>
</register>
<register>
<name>clk_en_peri</name>
<description>Peripheral clock enable</description>
<addressOffset>0x2c</addressOffset>
<fields>
<field>
<name>rom_clk_en</name>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>dma_clk_en</name>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>ai_clk_en</name>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>dvp_clk_en</name>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>fft_clk_en</name>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>gpio_clk_en</name>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>spi0_clk_en</name>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>spi1_clk_en</name>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>spi2_clk_en</name>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>spi3_clk_en</name>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>i2s0_clk_en</name>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>i2s1_clk_en</name>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>i2s2_clk_en</name>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>i2c0_clk_en</name>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>i2c1_clk_en</name>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>i2c2_clk_en</name>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>uart1_clk_en</name>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>uart2_clk_en</name>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>uart3_clk_en</name>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>aes_clk_en</name>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>fpioa_clk_en</name>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>timer0_clk_en</name>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>timer1_clk_en</name>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>timer2_clk_en</name>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>wdt0_clk_en</name>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>wdt1_clk_en</name>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>sha_clk_en</name>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>otp_clk_en</name>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>rtc_clk_en</name>
<bitRange>[29:29]</bitRange>
</field>
</fields>
</register>
<register>
<name>soft_reset</name>
<description>Soft reset ctrl</description>
<addressOffset>0x30</addressOffset>
<fields>
<field>
<name>soft_reset</name>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>peri_reset</name>
<description>Peripheral reset controller</description>
<addressOffset>0x34</addressOffset>
<fields>
<field>
<name>rom_reset</name>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>dma_reset</name>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>ai_reset</name>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>dvp_reset</name>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>fft_reset</name>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>gpio_reset</name>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>spi0_reset</name>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>spi1_reset</name>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>spi2_reset</name>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>spi3_reset</name>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>i2s0_reset</name>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>i2s1_reset</name>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>i2s2_reset</name>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>i2c0_reset</name>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>i2c1_reset</name>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>i2c2_reset</name>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>uart1_reset</name>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>uart2_reset</name>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>uart3_reset</name>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>aes_reset</name>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>fpioa_reset</name>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>timer0_reset</name>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>timer1_reset</name>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>timer2_reset</name>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>wdt0_reset</name>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>wdt1_reset</name>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>sha_reset</name>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>rtc_reset</name>
<bitRange>[29:29]</bitRange>
</field>
</fields>
</register>
<register>
<name>clk_th0</name>
<description>Clock threshold controller 0</description>
<addressOffset>0x38</addressOffset>
<fields>
<field>
<name>sram0_gclk</name>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>sram1_gclk</name>
<bitRange>[7:4]</bitRange>
</field>
<field>
<name>ai_gclk</name>
<bitRange>[11:8]</bitRange>
</field>
<field>
<name>dvp_gclk</name>
<bitRange>[15:12]</bitRange>
</field>
<field>
<name>rom_gclk</name>
<bitRange>[19:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>clk_th1</name>
<description>Clock threshold controller 1</description>
<addressOffset>0x3c</addressOffset>
<fields>
<field>
<name>spi0_clk</name>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>spi1_clk</name>
<bitRange>[15:8]</bitRange>
</field>
<field>
<name>spi2_clk</name>
<bitRange>[23:16]</bitRange>
</field>
<field>
<name>spi3_clk</name>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>clk_th2</name>
<description>Clock threshold controller 2</description>
<addressOffset>0x40</addressOffset>
<fields>
<field>
<name>timer0_clk</name>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>timer1_clk</name>
<bitRange>[15:8]</bitRange>
</field>
<field>
<name>timer2_clk</name>
<bitRange>[23:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>clk_th3</name>
<description>Clock threshold controller 3</description>
<addressOffset>0x44</addressOffset>
<fields>
<field>
<name>i2s0_clk</name>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>i2s1_clk</name>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>clk_th4</name>
<description>Clock threshold controller 4</description>
<addressOffset>0x48</addressOffset>
<fields>
<field>
<name>i2s2_clk</name>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>i2s0_mclk</name>
<bitRange>[23:16]</bitRange>
</field>
<field>
<name>i2s1_mclk</name>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>clk_th5</name>
<description>Clock threshold controller 5</description>
<addressOffset>0x4c</addressOffset>
<fields>
<field>
<name>i2s2_mclk</name>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>i2c0_clk</name>
<bitRange>[15:8]</bitRange>
</field>
<field>
<name>i2c1_clk</name>
<bitRange>[23:16]</bitRange>
</field>
<field>
<name>i2c2_clk</name>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>clk_th6</name>
<description>Clock threshold controller 6</description>
<addressOffset>0x50</addressOffset>
<fields>
<field>
<name>wdt0_clk</name>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>wdt1_clk</name>
<bitRange>[15:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>misc</name>
<description>Miscellaneous controller</description>
<addressOffset>0x54</addressOffset>
<fields>
<field>
<name>debug_sel</name>
<bitRange>[5:0]</bitRange>
</field>
<field>
<name>spi_dvp_data_enable</name>
<bitRange>[10:10]</bitRange>
</field>
</fields>
</register>
<register>
<name>peri</name>
<description>Peripheral controller</description>
<addressOffset>0x58</addressOffset>
<fields>
<field>
<name>timer0_pause</name>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>timer1_pause</name>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>timer2_pause</name>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>timer3_pause</name>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>timer4_pause</name>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>timer5_pause</name>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>timer6_pause</name>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>timer7_pause</name>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>timer8_pause</name>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>timer9_pause</name>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>timer10_pause</name>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>timer11_pause</name>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>spi0_xip_en</name>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>spi1_xip_en</name>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>spi2_xip_en</name>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>spi3_xip_en</name>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>spi0_clk_bypass</name>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>spi1_clk_bypass</name>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>spi2_clk_bypass</name>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>i2s0_clk_bypass</name>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>i2s1_clk_bypass</name>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>i2s2_clk_bypass</name>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>jtag_clk_bypass</name>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>dvp_clk_bypass</name>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>debug_clk_bypass</name>
<bitRange>[24:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>spi_sleep</name>
<description>SPI sleep controller</description>
<addressOffset>0x5c</addressOffset>
<fields>
<field>
<name>ssi0_sleep</name>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>ssi1_sleep</name>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>ssi2_sleep</name>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>ssi3_sleep</name>
<bitRange>[3:3]</bitRange>
</field>
</fields>
</register>
<register>
<name>reset_status</name>
<description>Reset source status</description>
<addressOffset>0x60</addressOffset>
<fields>
<field>
<name>reset_sts_clr</name>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>pin_reset_sts</name>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>wdt0_reset_sts</name>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>wdt1_reset_sts</name>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>soft_reset_sts</name>
<bitRange>[4:4]</bitRange>
</field>
</fields>
</register>
<register>
<name>dma_sel0</name>
<description>DMA handshake selector</description>
<addressOffset>0x64</addressOffset>
<fields>
<field>
<name>dma_sel0</name>
<bitRange>[5:0]</bitRange>
<enumeratedValues>
<name>DMASELECT</name>
<enumeratedValue><name>ssi0_rx_req</name><value>0</value></enumeratedValue>
<enumeratedValue><name>ssi0_tx_req</name><value>1</value></enumeratedValue>
<enumeratedValue><name>ssi1_rx_req</name><value>2</value></enumeratedValue>
<enumeratedValue><name>ssi1_tx_req</name><value>3</value></enumeratedValue>
<enumeratedValue><name>ssi2_rx_req</name><value>4</value></enumeratedValue>
<enumeratedValue><name>ssi2_tx_req</name><value>5</value></enumeratedValue>
<enumeratedValue><name>ssi3_rx_req</name><value>6</value></enumeratedValue>
<enumeratedValue><name>ssi3_tx_req</name><value>7</value></enumeratedValue>
<enumeratedValue><name>i2c0_rx_req</name><value>8</value></enumeratedValue>
<enumeratedValue><name>i2c0_tx_req</name><value>9</value></enumeratedValue>
<enumeratedValue><name>i2c1_rx_req</name><value>10</value></enumeratedValue>
<enumeratedValue><name>i2c1_tx_req</name><value>11</value></enumeratedValue>
<enumeratedValue><name>i2c2_rx_req</name><value>12</value></enumeratedValue>
<enumeratedValue><name>i2c2_tx_req</name><value>13</value></enumeratedValue>
<enumeratedValue><name>uart1_rx_req</name><value>14</value></enumeratedValue>
<enumeratedValue><name>uart1_tx_req</name><value>15</value></enumeratedValue>
<enumeratedValue><name>uart2_rx_req</name><value>16</value></enumeratedValue>
<enumeratedValue><name>uart2_tx_req</name><value>17</value></enumeratedValue>
<enumeratedValue><name>uart3_rx_req</name><value>18</value></enumeratedValue>
<enumeratedValue><name>uart3_tx_req</name><value>19</value></enumeratedValue>
<enumeratedValue><name>aes_req</name><value>20</value></enumeratedValue>
<enumeratedValue><name>sha_rx_req</name><value>21</value></enumeratedValue>
<enumeratedValue><name>ai_rx_req</name><value>22</value></enumeratedValue>
<enumeratedValue><name>fft_rx_req</name><value>23</value></enumeratedValue>
<enumeratedValue><name>fft_tx_req</name><value>24</value></enumeratedValue>
<enumeratedValue><name>i2s0_tx_req</name><value>25</value></enumeratedValue>
<enumeratedValue><name>i2s0_rx_req</name><value>26</value></enumeratedValue>
<enumeratedValue><name>i2s1_tx_req</name><value>27</value></enumeratedValue>
<enumeratedValue><name>i2s1_rx_req</name><value>28</value></enumeratedValue>
<enumeratedValue><name>i2s2_tx_req</name><value>29</value></enumeratedValue>
<enumeratedValue><name>i2s2_rx_req</name><value>30</value></enumeratedValue>
<enumeratedValue><name>i2s0_bf_dir_req</name><value>31</value></enumeratedValue>
<enumeratedValue><name>i2s0_bf_voice_req</name><value>32</value></enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>dma_sel1</name>
<bitRange>[11:6]</bitRange>
<enumeratedValues derivedFrom = "DMASELECT">
</enumeratedValues>
</field>
<field>
<name>dma_sel2</name>
<bitRange>[17:12]</bitRange>
<enumeratedValues derivedFrom = "DMASELECT">
</enumeratedValues>
</field>
<field>
<name>dma_sel3</name>
<bitRange>[23:18]</bitRange>
<enumeratedValues derivedFrom = "DMASELECT">
</enumeratedValues>
</field>
<field>
<name>dma_sel4</name>
<bitRange>[29:24]</bitRange>
<enumeratedValues derivedFrom = "DMASELECT">
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>dma_sel1</name>
<description>DMA handshake selector</description>
<addressOffset>0x68</addressOffset>
<fields>
<field>
<name>dma_sel5</name>
<bitRange>[5:0]</bitRange>
<enumeratedValues derivedFrom = "dma_sel0.dma_sel0.DMASELECT">
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>power_sel</name>
<description>IO Power Mode Select controller</description>
<addressOffset>0x6c</addressOffset>
<fields>
<field>
<name>power_mode_sel0</name>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>power_mode_sel1</name>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>power_mode_sel2</name>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>power_mode_sel3</name>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>power_mode_sel4</name>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>power_mode_sel5</name>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>power_mode_sel6</name>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>power_mode_sel7</name>
<bitRange>[7:7]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<!-- SYSCTL -->
<!-- AES -->
<peripheral>
<name>AES</name>
<description>AES Accelerator</description>
<groupName>AES</groupName>
<baseAddress>0x50450000</baseAddress>
<registers>
<register>
<dim>4</dim>
<dimIncrement>0x04</dimIncrement>
<name>key[%s]</name>
<description>1st-4th word of key</description>
<addressOffset>0x00</addressOffset>
</register>
<register>
<name>encrypt_sel</name>
<description>Encryption or decryption select</description>
<addressOffset>0x10</addressOffset>
<fields>
<field>
<name>encrypt_sel</name>
<description>Select encryption or decryption mode</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>encryption</name>
<description>Sets encryption mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>decryption</name>
<description>Sets decryption mode</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>mode_ctl</name>
<description>AES mode register</description>
<addressOffset>0x14</addressOffset>
<fields>
<field>
<name>cipher_mode</name>
<description>Cipher mode</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>ECB</name>
<description>Electronic Codebook</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CBC</name>
<description>Cipher Block Chaining</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>GCM</name>
<description>Galois/Counter Mode</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>key_mode</name>
<description>Key mode</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>AES128</name>
<description>AES-128</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AES192</name>
<description>AES-192</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>AES256</name>
<description>AES-256</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>key_order</name>
<description>Input key order</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENDIAN</name>
<enumeratedValue>
<name>be</name>
<description>Big Endian</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>le</name>
<description>Little Endian</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>input_order</name>
<description>Input data order</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues derivedFrom="ENDIAN">
</enumeratedValues>
</field>
<field>
<name>output_order</name>
<description>Output data order</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues derivedFrom="ENDIAN">
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x04</dimIncrement>
<name>iv[%s]</name>
<description>Initialisation Vector (96 bit for GCM, 128 bit for CBC)</description>
<addressOffset>0x18</addressOffset>
</register>
<register>
<name>endian</name>
<description>Endian control</description>
<addressOffset>0x28</addressOffset>
<fields>
<field>
<name>endian</name>
<description>Input data endian</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues derivedFrom="mode_ctl.key_order.ENDIAN">
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>finish</name>
<description>Finished status</description>
<addressOffset>0x2C</addressOffset>
<fields>
<field>
<name>finish</name>
<description>AES operation finished status</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>not_finished</name>
<description>Operation not finished</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>finished</name>
<description>Operation finished</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>dma_sel</name>
<description>DMA select</description>
<addressOffset>0x30</addressOffset>
<fields>
<field>
<name>dma_sel</name>
<description>Output to DMA if set, to CPU otherwise</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>aad_num</name>
<description>GCM additional authenticated data count in bytes, minus one</description>
<addressOffset>0x34</addressOffset>
</register>
<register>
<name>pc_num</name>
<description>Plaintext/ciphertext input data count in bytes, minus one</description>
<addressOffset>0x3c</addressOffset>
</register>
<register>
<name>text_data</name>
<description>Plaintext/ciphertext input data</description>
<addressOffset>0x40</addressOffset>
</register>
<register>
<name>aad_data</name>
<description>Additional authenticated data</description>
<addressOffset>0x44</addressOffset>
</register>
<register>
<name>tag_chk</name>
<description>Tag check status</description>
<addressOffset>0x48</addressOffset>
<fields>
<field>
<name>tag_chk</name>
<description>Tag check status</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>busy</name>
<description>Check not finished</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>fail</name>
<description>Check failed</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>success</name>
<description>Check success</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>data_in_flag</name>
<description>Data can input flag</description>
<addressOffset>0x4c</addressOffset>
<fields>
<field>
<name>data_in_flag</name>
<description>Data can be written to text_data or aad_data when this flag is set</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>CAN_INPUT</name>
<enumeratedValue>
<name>cannot_input</name>
<description>Cannot input</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>can_input</name>
<description>Can input</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x04</dimIncrement>
<name>gcm_in_tag[%s]</name>
<description>GCM input tag for comparison with the calculated tag</description>
<addressOffset>0x50</addressOffset>
</register>
<register>
<name>out_data</name>
<description>Plaintext/ciphertext output data</description>
<addressOffset>0x60</addressOffset>
</register>
<register>
<name>en</name>
<description>AES module enable</description>
<addressOffset>0x64</addressOffset>
<fields>
<field>
<name>en</name>
<description>AES module enable</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>disable</name>
<description>Disable module</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enable</name>
<description>Enable module</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>data_out_flag</name>
<description>Data can output flag</description>
<addressOffset>0x68</addressOffset>
<fields>
<field>
<name>data_out_flag</name>
<description>Data can be read from out_data when this flag is set</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>cannot_output</name>
<description>Data cannot output</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>can_output</name>
<description>Data can output</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>tag_in_flag</name>
<description>Can input tag (when using GCM)</description>
<addressOffset>0x6c</addressOffset>
<fields>
<field>
<name>tag_in_flag</name>
<description>GCM tag can be written to gcm_in_tag when this flag is set</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues derivedFrom="data_in_flag.data_in_flag.CAN_INPUT">
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>tag_clear</name>
<description>Tag clear (a write to this register clears the tag_chk status)</description>
<addressOffset>0x70</addressOffset>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x04</dimIncrement>
<name>gcm_out_tag[%s]</name>
<description>Computed GCM output tag</description>
<addressOffset>0x74</addressOffset>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x04</dimIncrement>
<name>key_ext[%s]</name>
<description>5th-8th word of key</description>
<addressOffset>0x84</addressOffset>
</register>
</registers>
</peripheral>
<!-- AES -->
<!-- RTC -->
<peripheral>
<name>RTC</name>
<description>Real Time Clock</description>
<groupName>RTC</groupName>
<baseAddress>0x50460000</baseAddress>
<registers>
<register>
<name>date</name>
<description>Timer date information</description>
<addressOffset>0x00</addressOffset>
<fields>
<field>
<name>week</name>
<description>Week. Range [0,6]. 0 is Sunday.</description>
<bitRange>[2:0]</bitRange>
<writeConstraint><range><minimum>0</minimum><maximum>6</maximum></range></writeConstraint>
</field>
<field>
<name>day</name>
<description>Day. Range [1,31] or [1,30] or [1,29] or [1,28]</description>
<bitRange>[12:8]</bitRange>
<writeConstraint><range><minimum>1</minimum><maximum>31</maximum></range></writeConstraint>
</field>
<field>
<name>month</name>
<description>Month. Range [1,12]</description>
<bitRange>[19:16]</bitRange>
<writeConstraint><range><minimum>1</minimum><maximum>12</maximum></range></writeConstraint>
</field>
<field>
<name>year</name>
<description>Year. Range [0,99]</description>
<bitRange>[31:20]</bitRange>
<writeConstraint><range><minimum>0</minimum><maximum>99</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>time</name>
<description>Timer time information</description>
<addressOffset>0x04</addressOffset>
<fields>
<field>
<name>second</name>
<description>Second. Range [0,59]</description>
<bitRange>[15:10]</bitRange>
<writeConstraint><range><minimum>0</minimum><maximum>59</maximum></range></writeConstraint>
</field>
<field>
<name>minute</name>
<description>Minute. Range [0,59]</description>
<bitRange>[21:16]</bitRange>
<writeConstraint><range><minimum>0</minimum><maximum>59</maximum></range></writeConstraint>
</field>
<field>
<name>hour</name>
<description>Hour. Range [0,23]</description>
<bitRange>[28:24]</bitRange>
<writeConstraint><range><minimum>0</minimum><maximum>23</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>alarm_date</name>
<description>Alarm date information</description>
<addressOffset>0x08</addressOffset>
<fields>
<field>
<name>week</name>
<description>Week. Range [0,6]. 0 is Sunday.</description>
<bitRange>[2:0]</bitRange>
<writeConstraint><range><minimum>0</minimum><maximum>6</maximum></range></writeConstraint>
</field>
<field>
<name>day</name>
<description>Day. Range [1,31] or [1,30] or [1,29] or [1,28]</description>
<bitRange>[12:8]</bitRange>
<writeConstraint><range><minimum>1</minimum><maximum>31</maximum></range></writeConstraint>
</field>
<field>
<name>month</name>
<description>Month. Range [1,12]</description>
<bitRange>[19:16]</bitRange>
<writeConstraint><range><minimum>1</minimum><maximum>12</maximum></range></writeConstraint>
</field>
<field>
<name>year</name>
<description>Year. Range [0,99]</description>
<bitRange>[31:20]</bitRange>
<writeConstraint><range><minimum>0</minimum><maximum>99</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>alarm_time</name>
<description>Alarm time information</description>
<addressOffset>0x0c</addressOffset>
<fields>
<field>
<name>second</name>
<description>Second. Range [0,59]</description>
<bitRange>[15:10]</bitRange>
<writeConstraint><range><minimum>0</minimum><maximum>59</maximum></range></writeConstraint>
</field>
<field>
<name>minute</name>
<description>Minute. Range [0,59]</description>
<bitRange>[21:16]</bitRange>
<writeConstraint><range><minimum>0</minimum><maximum>59</maximum></range></writeConstraint>
</field>
<field>
<name>hour</name>
<description>Hour. Range [0,23]</description>
<bitRange>[28:24]</bitRange>
<writeConstraint><range><minimum>0</minimum><maximum>23</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>initial_count</name>
<description>Timer counter initial value</description>
<addressOffset>0x10</addressOffset>
<fields>
<field>
<name>count</name>
<description>RTC counter initial value</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>current_count</name>
<description>Timer counter current value</description>
<addressOffset>0x14</addressOffset>
<fields>
<field>
<name>count</name>
<description>RTC counter current value</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>interrupt_ctrl</name>
<description>RTC interrupt settings</description>
<addressOffset>0x18</addressOffset>
<fields>
<field>
<name>tick_enable</name>
<description>TICK_ENABLE</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>alarm_enable</name>
<description>Alarm interrupt enable</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>tick_int_mode</name>
<description>Tick interrupt enable</description>
<bitRange>[3:2]</bitRange>
</field>
<field>
<name>alarm_compare_mask</name>
<description>Alarm compare mask for interrupt</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>register_ctrl</name>
<description>RTC register settings</description>
<addressOffset>0x1c</addressOffset>
<fields>
<field>
<name>read_enable</name>
<description>RTC timer read enable</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>write_enable</name>
<description>RTC timer write enable</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>timer_mask</name>
<description>RTC timer mask</description>
<bitRange>[20:13]</bitRange>
</field>
<field>
<name>alarm_mask</name>
<description>RTC alarm mask</description>
<bitRange>[28:21]</bitRange>
</field>
<field>
<name>initial_count_mask</name>
<description>RTC counter initial count value mask</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>interrupt_register_mask</name>
<description>RTC interrupt register mask</description>
<bitRange>[30:30]</bitRange>
</field>
</fields>
</register>
<register>
<name>extended</name>
<description>Timer extended information</description>
<addressOffset>0x28</addressOffset>
<fields>
<field>
<name>century</name>
<description>Century. Range [0,31]</description>
<bitRange>[4:0]</bitRange>
<writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint>
</field>
<field>
<name>leap_year</name>
<description>Is leap year. 1 is leap year, 0 is not leap year</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>not_leap</name>
<description>0 is not leap year</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>leap</name>
<description>1 is leap year</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
<interrupt>
<name>RTC</name>
<value>20</value>
</interrupt>
</peripheral>
<!-- RTC -->
</peripherals>
</device>