TLE985x 1.3 SVD file Infineon Technologies AG Infineon tbd CM0 r0p0 little false false 2 false 8 32 ADC1 ADC1 0x40004000 0x0 0x4000 registers INTISR3 Interrupt node 3: ADC1 3 INTISR21 Interrupt node 21: Differential Unit 21 CAL_CH0_1 Calibration for Channel 0 and 1 0x48 32 CALGAIN_CH1 Gain Calibration for channel 1 24 31 read-write CALOFFS_CH1 Offset Calibration for channel 1 16 20 read-write CALGAIN_CH0 Gain Calibration for channel 0 8 15 read-write CALOFFS_CH0 Offset Calibration for channel 0 0 4 read-write CAL_CH10_11 Calibration for Channel 10 and 11 0x5C 32 CALGAIN_CH11 Gain Calibration for channel 11 24 31 read-write CALOFFS_CH11 Offset Calibration for channel 11 16 20 read-write CALGAIN_CH10 Gain Calibration for channel 10 8 15 read-write CALOFFS_CH10 Offset Calibration for channel 10 0 4 read-write CAL_CH12_13 Calibration for Channel 12 and 13 0x138 32 CALGAIN_CH13 Gain Calibration for channel 13 24 31 read-write CALOFFS_CH13 Offset Calibration for channel 13 16 20 read-write CALGAIN_CH12 Gain Calibration for channel 12 8 15 read-write CALOFFS_CH12 Offset Calibration for channel 12 0 4 read-write CAL_CH2_3 Calibration for Channel 2 and 3 0x4C 32 CALGAIN_CH3 Gain Calibration for channel 3 24 31 read-write CALOFFS_CH3 Offset Calibration for channel 3 16 20 read-write CALGAIN_CH2 Gain Calibration for channel 2 8 15 read-write CALOFFS_CH2 Offset Calibration for channel 2 0 4 read-write CAL_CH4_5 Calibration for Channel 4 and 5 0x50 32 CALGAIN_CH5 Gain Calibration for channel 5 24 31 read-write CALOFFS_CH5 Offset Calibration for channel 5 16 20 read-write CALGAIN_CH4 Gain Calibration for channel 4 8 15 read-write CALOFFS_CH4 Offset Calibration for channel 4 0 4 read-write CAL_CH6_7 Calibration for Channel 6 and 7 0x54 32 CALGAIN_CH7 Gain Calibration for channel 7 24 31 read-write CALOFFS_CH7 Offset Calibration for channel 7 16 20 read-write CALGAIN_CH6 Gain Calibration for channel 6 8 15 read-write CALOFFS_CH6 Offset Calibration for channel 6 0 4 read-write CAL_CH8_9 Calibration for Channel 8 and 9 0x58 32 CALGAIN_CH9 Gain Calibration for channel 9 24 31 read-write CALOFFS_CH9 Offset Calibration for channel 9 16 20 read-write CALGAIN_CH8 Gain Calibration for channel 8 8 15 read-write CALOFFS_CH8 Offset Calibration for channel 8 0 4 read-write CHx_EIM Channel Setting Bits for Exceptional Interrupt Measurement 0x08 32 ADC1_EIM_TRIG_SEL Trigger selection for exceptional interrupt measurement (EIM) 16 18 read-write NONE 0b000 COUT63 0b001 GPT12_T6OUT 0b010 GPT12_T3OUT 0b011 T2 t2_adc_trigger 0b100 T21 t21_adc_trigger 0b101 EIM_EN Exceptional interrupt measurement (EIM) Trigger Event enable 11 11 read-write DISABLE start of EIM disabled 0b0 ENABLE start of IEM enabled 0b1 EIM_REP Repeat count for exceptional interrupt measurement (EIM) 8 10 read-write 1 Continuous Mode 0b000 2 Measurements (2 SOC generated for ADC10) 0b001 4 Measurements (4 SOC generated for ADC10) 0b010 8 Measurements (8 SOC generated for ADC10) 0b011 16 Measurements (16 SOC generated for ADC10) 0b100 32 Measurements (32 SOC generated for ADC10) 0b101 64 Measurements (64 SOC generated for ADC10) 0b110 128 Measurements (128 SOC generated for ADC10) 0b111 EIM_CHx Channel set for exceptional interrupt measurement (EIM) 0 3 read-write CH0_EN Channel 0 enable 0b0000 CH1_EN Channel 1 enable 0b0001 CH2_EN Channel 2 enable 0b0010 CH3_EN Channel 3 enable 0b0011 CH4_EN Channel 4 enable 0b0100 CH5_EN Channel 5 enable 0b0101 CH6_EN Channel 6 enable 0b0110 CH7_EN Channel 7 enable 0b0111 CH8_EN Channel 8 enable 0b1000 CH9_EN Channel 9 enable 0b1001 CH12_EN Channel 12 enable 0b1100 CH13_EN Channel 13 enable 0b1101 CHx_ESM Channel Setting Bits for Exceptional Sequence Measurement 0x0C 32 ESM_STS Exceptional Sequence Measurement is finished 31 31 read-write not active Exceptional Sequence Measurement not done 0b0 done Exceptional Sequence Measurement done 0b1 ESM_EN Enable for Exceptional Sequence Measurement Trigger Event 30 30 read-write Disable start of ESM disabled 0b0 Enable start of ESM enabled 0b1 ADC1_ESM_TRIG_SEL Trigger selection for exceptional interrupt measurement (ESM) 16 18 read-write NONE 0b000 COUT63 0b001 GPT12_T6OUT 0b010 GPT12_T3OUT 0b011 T2 t2_adc_trigger 0b100 T21 t21_adc_trigger 0b101 ESM_0 Channel Sequence for Exceptional Sequence Measurement (ESM) 0 13 read-write CH0_EN Channel 0 enable 0x0001 CH1_EN Channel 1 enable 0x0002 CH2_EN Channel 2 enable 0x0004 CH3_EN Channel 3 enable 0x0008 CH4_EN Channel 4 enable 0x0010 CH5_EN Channel 5 enable 0x0020 CH6_EN Channel 6 enable 0x0040 CH7_EN Channel 7 enable 0x0080 CH8_EN Channel 8 enable 0x0100 CH9_EN Channel 9 enable 0x0200 CH10_EN Channel 10 enable 0x0400 CH11_EN Channel 11 enable 0x0800 CH12_EN Channel 12 enable 0x1000 CH13_EN Channel 13 enable 0x2000 CNT0_3_LOWER Lower Counter Trigger Level Post-Processing-Channel 0-3 0xD8 32 HYST_LO_PP3 Post-Processing-Channel 3 lower hysteresis 27 28 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_PP3 Lower timer trigger threshold Post-Processing-Channel 3 24 25 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_LO_PP2 Post-Processing-Channel 2 lower hysteresis 19 20 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_PP2 Lower timer trigger threshold Post-Processing-Channel 2 16 17 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_LO_PP1 Post-Processing-Channel 1 lower hysteresis 11 12 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_PP1 Lower timer trigger threshold Post-Processing-Channel 1 8 9 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_LO_PP0 Post-Processing-Channel 0 lower hysteresis 3 4 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_PP0 Lower timer trigger threshold Post-Processing-Channel 0 0 1 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 CNT0_3_UPPER Upper Counter Trigger Level Post-Processing-Channel 0-3 0xE8 32 HYST_UP_PP3 Post-Processing-Channel 3 upper hysteresis 27 28 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_PP3 Upper timer trigger threshold Post-Processing-Channel 3 24 25 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_UP_PP2 Post-Processing-Channel 2 upper hysteresis 19 20 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_PP2 Upper timer trigger threshold Post-Processing-Channel 2 16 17 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_UP_PP1 Post-Processing-Channel 1 upper hysteresis 11 12 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_PP1 Upper timer trigger threshold Post-Processing-Channel 1 8 9 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_UP_PP0 Post-Processing-Channel 0 upper hysteresis 3 4 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_PP0 Upper timer trigger threshold Post-Processing-Channel 0 0 1 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 CNT4_7_LOWER Lower Counter Trigger Level Post-Processing-Channel 4-7 0xDC 32 HYST_LO_PP7 Post-Processing-Channel 7 lower hysteresis 27 28 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_PP7 Lower timer trigger threshold Post-Processing-Channel 7 24 25 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_LO_PP6 Channel 6 lower hysteresis 19 20 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_PP6 Lower timer trigger threshold Post-Processing-Channel 6 16 17 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_LO_PP5 Post-Processing-Channel 5 lower hysteresis 11 12 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_PP5 Lower timer trigger threshold Post-Processing-Channel 5 8 9 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_LO_PP4 Post-Processing-Channel 4 lower hysteresis 3 4 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_PP4 Lower timer trigger threshold Post-Processing-Channel 4 0 1 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 CNT4_7_UPPER Upper Counter Trigger Level Post-Processing-Channel 4-7 0xEC 32 HYST_UP_PP7 Post-Processing-Channel 7 upper hysteresis 27 28 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_PP7 Upper timer trigger threshold Post-Processing-Channel 7 24 25 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_UP_PP6 Post-Processing-Channel 6 upper hysteresis 19 20 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_PP6 Upper timer trigger threshold Post-Processing-Channel 6 16 17 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_UP_PP5 Post-Processing-Channel 5 upper hysteresis 11 12 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_PP5 Upper timer trigger threshold Post-Processing-Channel 5 8 9 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_UP_PP4 Post-Processing-Channel 4 upper hysteresis 3 4 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_PP4 Upper timer trigger threshold Post-Processing-Channel 4 0 1 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 CTRL2 Measurement Unit 1 Control Register 2 0x14 32 CAL_EN Calibration Enable for Channels 0 to 13 0 13 read-write CH0_EN Channel 0 calibration enable 0x0001 CH1_EN Channel 1 calibration enable 0x0002 CH2_EN Channel 2 calibration enable 0x0004 CH3_EN Channel 3 calibration enable 0x0008 CH4_EN Channel 4 calibration enable 0x0010 CH5_EN Channel 5 calibration enable 0x0020 CH6_EN Channel 6 calibration enable 0x0040 CH7_EN Channel 7 calibration enable 0x0080 CH8_EN Channel 8 calibration enable 0x0100 CH9_EN Channel 9 calibration enable 0x0200 CH10_EN Channel 10 calibration enable 0x0400 CH11_EN Channel 11 calibration enable 0x0800 CH12_EN Channel 12 calibration enable 0x1000 CH13_EN Channel 13 calibration enable 0x2000 CTRL3 Measurement Unit 1 Control Register 3 0x18 32 SAMPLE_TIME_LVCH Sample time of ADC1 16 19 read-write ADCCLK4 4 ADC_CLK clock periods 0x0 ADCCLK6 6 ADC_CLK clock periods 0x1 ADCCLK8 8 ADC_CLK clock periods(default) 0x2 ADCCLK10 10 ADC_CLK clock periods 0x3 ADCCLK12 12 ADC_CLK clock periods 0x4 ADCCLK14 14 ADC_CLK clock periods 0x5 ADCCLK16 16 ADC_CLK clock periods 0x6 ADCCLK18 18 ADC_CLK clock periods 0x7 ADCCLK20 20 ADC_CLK clock periods 0x8 ADCCLK22 22 ADC_CLK clock periods 0x9 SAMPLE_TIME_HVCH Sample time of ADC1 8 12 read-write ADCCLK4 4 ADC_CLK clock periods 0x00 ADCCLK6 6 ADC_CLK clock periods 0x01 ADCCLK8 8 ADC_CLK clock periods 0x02 ADCCLK10 10 ADC_CLK clock periods 0x03 ADCCLK12 12 ADC_CLK clock periods 0x04 ADCCLK14 14 ADC_CLK clock periods 0x05 ADCCLK16 16 ADC_CLK clock periods 0x06 ADCCLK18 18 ADC_CLK clock periods 0x07 ADCCLK20 20 ADC_CLK clock periods 0x08 ADCCLK22 22 ADC_CLK clock periods 0x09 ADCCLK24 24 ADC_CLK clock periods (default) 0x0A ADCCLK26 26 ADC_CLK clock periods 0x0B ADCCLK28 28 ADC_CLK clock periods 0x0C ADCCLK30 30 ADC_CLK clock periods 0x0D ADCCLK32 32 ADC_CLK clock periods 0x0E ADCCLK34 34 ADC_CLK clock periods 0x0F ADCCLK36 36 ADC_CLK clock periods 0x10 ADCCLK38 38 ADC_CLK clock periods 0x11 ADCCLK40 40 ADC_CLK clock periods 0x12 ADCCLK42 42 ADC_CLK clock periods 0x13 ADCCLK44 44 ADC_CLK clock periods 0x14 ADCCLK46 46 ADC_CLK clock periods 0x15 ADCCLK48 48 ADC_CLK clock periods 0x16 ADCCLK50 50 ADC_CLK clock periods 0x17 ADCCLK52 52 ADC_CLK clock periods 0x18 ADCCLK54 54 ADC_CLK clock periods 0x19 ADCCLK56 56 ADC_CLK clock periods 0x1A ADCCLK58 58 ADC_CLK clock periods 0x1B ADCCLK60 60 ADC_CLK clock periods 0x1C ADCCLK62 62 ADC_CLK clock periods 0x1D MCM_RDY Ready Signal for MCM after Power On or Reset 7 7 read-only MCM Not Ready Measurement Core Module in startup phase 0b0 MCM Ready Measurement Core Module start-up phase finished 0b1 EoC_FAIL Fail of ADC End of Conversion Signal 6 6 read-write ADC EoC available End of Conversion Signal was sent properly by ADC 0b0 ADC EoC not available End of Conversion Signal was not sent properly by ADC 0b1 EoC_FAIL_CLR Fail of ADC End of Conversion Signal Clear 4 4 write-only ADC EoC Fail not clear no clear of EoC_FAIL flag 0b0 ADC EoC Fail clear Clear of EoC_FAIL flag 0b1 SW_MODE Flag to enter SW Mode 1 1 read-write Software Mode Disable Sequencer running 0b0 Software Mode Enabled Sequencer stopped 0b1 MCM_PD_N Power Down Signal for MCM 0 0 read-write MCM Disabled Measurement Core Module Disabled 0b0 MCM Enabled Measurement Core Module Enabled 0b1 CTRL5 Measurement Unit 1 Control Register 5 0x1C 32 FILT_OUT_SEL_13_0 Output Filter Selection for Channels 0 to 13 0 13 read-write CTRL_STS ADC1 Control and Status Register 0x00 32 STRTUP_DIS DPP1 Startup Disable 18 18 read-write Startup Enable DPP1 Startup enabled 0b0 Startup Disable DPP1 Startup disable 0b1 SW_CH_SEL Channel for software mode 8 11 read-write CH0_EN Channel 0 enable 0b0000 CH1_EN Channel 1 enable 0b0001 CH2_EN Channel 2 enable 0b0010 CH3_EN Channel 3 enable 0b0011 CH4_EN Channel 4 enable 0b0100 CH5_EN Channel 5 enable 0b0101 CH6_EN Channel 6 enable 0b0110 CH7_EN Channel 7 enable 0b0111 CH8_EN Channel 8 enable 0b1000 CH9_EN Channel 9 enable 0b1001 CH12_EN Channel 12 enable 0b1100 CH13_EN Channel 13 enable 0b1101 EOC ADC1 End of Conversion (software mode) 7 7 read-only Pending conversion still running 0b0 Finished conversion has finished 0b1 CAL_SIGN Output of Comparator to Steer Gain / Offset calibration 5 5 read-only READY HVADC Ready bit 4 4 read-only Not ready Module in power down or in init phase 0b0 Ready set automatically 5 ADC clock cycles after module is enabled 0b1 SOS ADC1 Start of Sampling/Conversion (software mode) 2 2 read-write Disable no conversion is started 0b0 Enable conversion is started 0b1 SOOC ADC1 Start of Offset Calibration (software mode) 1 1 read-write Disable no offset calibration is started 0b0 Enable offset calibration is started 0b1 PD_N ADC1 Power Down Signal 0 0 read-write POWER DOWN ADC1 is powered down 0b0 ACTIVE ADC1 is switched on 0b1 DCHCNT1_4_LOWER Lower Counter Trigger Level DifferentialChannel 1 0xE4 32 HYST_LO_DCH1 Post-Processing-Channel 4 lower hysteresis 3 4 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_DCH1 Lower timer trigger threshold Post-Processing-Channel 4 0 1 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 DCHCNT1_4_UPPER Upper Counter Trigger Level DifferentialChannel 1 0xF4 32 HYST_UP_DCH1 Post-Processing-Channel 4 upper hysteresis 3 4 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_DCH1 Upper timer trigger threshold Post-Processing-Channel 4 0 1 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 DCHTH1_4_LOWER Lower Comparator Trigger Level Differential Channel 1 0xC4 32 DCH1_LOW Differential Channel 1 lower trigger level 0 7 read-write DCHTH1_4_UPPER Upper Comparator Trigger Level Differential Channel 1 0xD4 32 DCH1_UP Differential Channel 1 upper trigger level 0 7 read-write DIFFCH_OUT1 ADC1 Differential Channel Output 1 0xA0 32 DOF1 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 DVF1 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 DWFR1 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 DCH1 ADC differential output value 1 0 11 read-only DUIN_SEL Measurement Unit 1 - Differential Unit Input Selection Register 0xFC 32 DU1RES_NEG Differential Unit 1 result negative 4 4 read-only DU1 Result positive Differential Unit 1 result positive after calculation 0b0 DU1 Result negative Differential Unit 1 result negative after calculation 0b1 DU1_EN Differential Unit 1 enable 0 0 read-write DU1 disable Differential Unit 1 is disabled 0b0 DU1 enable Differential Unit 1 is enabled 0b1 FILT_OUT0 ADC1 or Filter Output Channel 0 0x70 32 OF0 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF0 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR0 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 FILT_OUT_CH0 ADC or filter output value channel 0 0 11 read-only FILT_OUT1 ADC1 or Filter Output Channel 1 0x74 32 OF1 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF1 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR1 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 FILT_OUT_CH1 ADC or filter output value channel 1 0 11 read-only FILT_OUT10 ADC1 or Filter Output Channel 10 0x98 32 OF10 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF10 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR10 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 FILT_OUT_CH10 ADC or filter output value channel 10 0 11 read-only FILT_OUT11 ADC1 or Filter Output Channel 11 0x9C 32 OF11 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF11 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR11 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 FILT_OUT_CH11 ADC or filter output value channel 11 0 11 read-only FILT_OUT12 ADC1 or Filter Output Channel 12 0x110 32 OF12 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF12 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR12 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 FILT_OUT_CH12 ADC or filter output value channel 12 0 11 read-only FILT_OUT13 ADC1 or Filter Output Channel 13 0x140 32 OF13 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF13 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR13 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 FILT_OUT_CH13 ADC or filter output value channel 13 0 11 read-only FILT_OUT2 ADC1 or Filter Output Channel 2 0x78 32 OF2 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF2 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR2 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 FILT_OUT_CH2 ADC or filter output value channel 2 0 11 read-only FILT_OUT3 ADC1 or Filter Output Channel 3 0x7C 32 OF3 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF3 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR3 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 FILT_OUT_CH3 ADC or filter output value channel 3 0 11 read-only FILT_OUT4 ADC1 or Filter Output Channel 4 0x80 32 OF4 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF4 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR4 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 FILT_OUT_CH4 ADC or filter output value channel 4 0 11 read-only FILT_OUT5 ADC1 or Filter Output Channel 5 0x84 32 OF5 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF5 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR5 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 FILT_OUT_CH5 ADC or filter output value channel 5 0 11 read-only FILT_OUT6 ADC1 or Filter Output Channel 6 0x88 32 OF6 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF6 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR6 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 FILT_OUT_CH6 ADC or filter output value channel 6 0 11 read-only FILT_OUT7 ADC1 or Filter Output Channel 7 0x8C 32 OF7 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF7 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR7 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 FILT_OUT_CH7 ADC or filter output value channel 7 0 11 read-only FILT_OUT8 ADC1 or Filter Output Channel 8 0x90 32 OF8 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF8 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR8 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 FILT_OUT_CH8 ADC or filter output value channel 8 0 11 read-only FILT_OUT9 ADC1 or Filter Output Channel 9 0x94 32 OF9 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF9 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR9 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 FILT_OUT_CH9 ADC or filter output value channel 9 0 11 read-only FILT_OUTEIM ADC1 or Filter Output of EIM 0x120 32 OF_EIM Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF_EIM Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR_EIM Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 FILT_OUT_EIM ADC or filter output value for last EIM measurement 0 11 read-only FILT_UPLO_CTRL Upper And Lower Threshold Filter Enable 0xB0 32 FUL_PP_CH7_EN Upper and lower threshold IIR filter enable Post-Processing-Channel 7 7 7 read-write Disable 0b0 Enable 0b1 FUL_PP_CH6_EN Upper and lower threshold IIR filter enable Post-Processing-Channel 6 6 6 read-write Disable 0b0 Enable 0b1 FUL_PP_CH5_EN Upper and lower threshold IIR filter enable Post-Processing-Channel 5 5 5 read-write Disable 0b0 Enable 0b1 FUL_PP_CH4_EN Upper and lower threshold IIR filter enable Post-Processing-Channel 4 4 4 read-write Disable 0b0 Enable 0b1 FUL_PP_CH3_EN Upper and lower threshold IIR filter enable Post-Processing-Channel 3 3 3 read-write Disable 0b0 Enable 0b1 FUL_PP_CH2_EN Upper and lower threshold IIR filter enable Post-Processing-Channel 2 2 2 read-write Disable 0b0 Enable 0b1 FUL_PP_CH1_EN Upper and lower threshold IIR filter enable Post-Processing-Channel 1 1 1 read-write Disable 0b0 Enable 0b1 FUL_PP_CH0_EN Upper and lower threshold IIR filter enable Post-Processing-Channel 0 0 0 read-write Disable 0b0 Enable 0b1 FILTCOEFF0_13 Filter Coefficients Measurement Unit Channel 0-13 0x60 32 CH13 Filter Coefficients ADC channel 13 26 27 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH12 Filter Coefficients ADC channel 12 24 25 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH11 Filter Coefficients ADC channel 11 22 23 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH10 Filter Coefficients ADC channel 10 20 21 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH9 Filter Coefficients ADC channel 9 18 19 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH8 Filter Coefficients ADC channel 8 16 17 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH7 Filter Coefficients ADC channel 7 14 15 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH6 Filter Coefficients ADC channel 6 12 13 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH5 Filter Coefficients ADC channel 5 10 11 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH4 Filter Coefficients ADC channel 4 8 9 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH3 Filter Coefficients ADC channel 3 6 7 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH2 Filter Coefficients ADC channel 2 4 5 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH1 Filter Coefficients ADC channel 1 2 3 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH0 Filter Coefficients ADC channel 0 0 1 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 IRQCLR_1 ADC1 Interrupt Status Clear 1 Register 0x6C 32 DU1UP_ISC Differential Unit 1 lower Interrupt Status Clear 25 25 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 DU1LO_ISC Differential Unit 1 lower Interrupt Status Clear 24 24 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 ESM_ISC Exceptional Sequence Measurement (ESM) Status Clear 17 17 write-only INACTIVE No ESM has cleared 0b0 ACTIVE ESM cleared 0b1 EIM_ISC Exceptional Interrupt Measurement (EIM) Status Clear 16 16 write-only INACTIVE No EIM cleared 0b0 ACTIVE EIM cleared 0b1 IIR_CH13_ISC ADC1 IIR-Filter-Channel 13 Interrupt Status Clear 13 13 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 IIR_CH12_ISC ADC1 IIR-Filter-Channel 12 Interrupt Status Clear 12 12 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 IIR_CH11_ISC ADC1 IIR-Filter-Channel 11 Interrupt Status Clear 11 11 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 IIR_CH10_ISC ADC1 IIR-Filter-Channel 10 Interrupt Status Clear 10 10 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 IIR_CH9_ISC ADC1 IIR-Filter-Channel 9 Interrupt Status Clear 9 9 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 IIR_CH8_ISC ADC1 IIR-Filter-Channel 8 Interrupt Status Clear 8 8 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 IIR_CH7_ISC ADC1 IIR-Filter-Channel 7 Interrupt Status Clear 7 7 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 IIR_CH6_ISC ADC1 IIR-Filter-Channel 6 Interrupt Status Clear 6 6 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 IIR_CH5_ISC ADC1 IIR-Filter-Channel 5 Interrupt Status Clear 5 5 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 IIR_CH4_ISC ADC1 IIR-Filter-Channel 4 Interrupt Status Clear 4 4 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 IIR_CH3_ISC ADC1 IIR-Filter-Channel 3 Interrupt Status Clear 3 3 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 IIR_CH2_ISC ADC1 IIR-Filter-Channel 2 Interrupt Status Clear 2 2 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 VS_ISC ADC1 IIR-Filter-Channel 1 Interrupt Status Clear 1 1 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 IIR_CH0_ISC ADC1 IIR-Filter-Channel 0 Interrupt Status Clear 0 0 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 IRQCLR_2 ADC1 Interrupt Status Clear 2 Register 0x108 32 PP_CH7_UP_ISC ADC1 Post-Processing-Channel 7 Upper Threshold Interrupt Status Clear 23 23 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 PP_CH6_UP_ISC ADC1 Post-Processing-Channel 6 Upper Threshold Interrupt Status Clear 22 22 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 PP_CH5_UP_ISC ADC1 Post-Processing-Channel 5 Upper Threshold Interrupt Status Clear 21 21 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 PP_CH4_UP_ISC ADC1 Post-Processing-Channel 4 Upper Threshold Interrupt Status Clear 20 20 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 PP_CH3_UP_ISC ADC1 Post-Processing-Channel 3 Upper Threshold Interrupt Status Clear 19 19 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 PP_CH2_UP_ISC ADC1 Post-Processing-Channel 2 Upper Threshold Interrupt Status Clear 18 18 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 VS_UP_ISC ADC1 Post-Processing-Channel 1 Upper Threshold Interrupt Status Clear 17 17 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 PP_CH0_UP_ISC ADC1 Post-Processing-Channel 0 Upper Threshold Interrupt Status Clear 16 16 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 PP_CH7_LO_ISC ADC1 Post-Processing-Channel 7 Lower Threshold Interrupt Status Clear 7 7 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 PP_CH6_LO_ISC ADC1 Post-Processing-Channel 6 Lower Threshold Interrupt Status Clear 6 6 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 PP_CH5_LO_ISC ADC1 Post-Processing-Channel 5 Lower Threshold Interrupt Status Clear 5 5 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 PP_CH4_LO_ISC ADC1 Post-Processing-Channel 4 Lower Threshold Interrupt Status Clear 4 4 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 PP_CH3_LO_ISC ADC1 Post-Processing-Channel 3 Lower Threshold Interrupt Status Clear 3 3 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 PP_CH2_LO_ISC ADC1 Post-Processing-Channel 2 Lower Threshold Interrupt Status Clear 2 2 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 VS_LO_ISC ADC1 Post-Processing-Channel 1 Lower Threshold Interrupt Status Clear 1 1 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 PP_CH0_LO_ISC ADC1 Post-Processing-Channel 0 Lower Threshold Interrupt Status Clear 0 0 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 IRQEN_1 ADC1 Interrupt Enable 1 Register 0x68 32 DU1UP_IEN Differential Unit 1 upper Interrupt Enable 25 25 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 DU1LO_IEN Differential Unit 1 lower Interrupt Enable 24 24 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 ESM_IEN Exceptional Sequence Measurement (ESM) Interrupt Enable 17 17 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 EIM_IEN Exceptional Interrupt Measurement (EIM) Interrupt Enable 16 16 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 IIR_CH13_IEN ADC1 IIR-Filter-Channel 13 Interrupt Enable 13 13 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 IIR_CH12_IEN ADC1 IIR-Filter-Channel 12 Interrupt Enable 12 12 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 IIR_CH11_IEN ADC1 IIR-Filter-Channel 11 Interrupt Enable 11 11 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 IIR_CH10_IEN ADC1 IIR-Filter-Channel 10 Interrupt Enable 10 10 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 IIR_CH9_IEN ADC1 IIR-Filter-Channel 9 Interrupt Enable 9 9 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 IIR_CH8_IEN ADC1 IIR-Filter-Channel 8 Interrupt Enable 8 8 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 IIR_CH7_IEN ADC1 IIR-Filter-Channel 7 Interrupt Enable 7 7 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 IIR_CH6_IEN ADC1 IIR-Filter-Channel 6 Interrupt Enable 6 6 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 IIR_CH5_IEN ADC1 IIR-Filter-Channel 5 Interrupt Enable 5 5 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 IIR_CH4_IEN ADC1 IIR-Filter-Channel 4 Interrupt Enable 4 4 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 IIR_CH3_IEN ADC1 IIR-Filter-Channel 3 Interrupt Enable 3 3 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 IIR_CH2_IEN ADC1 IIR-Filter-Channel 2 Interrupt Enable 2 2 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 VS_IEN ADC1 IIR-Filter-Channel 1 Interrupt Enable 1 1 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 IIR_CH0_IEN ADC1 IIR-Filter-Channel 0 Interrupt Enable 0 0 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 IRQEN_2 ADC1 Interrupt Enable 2 Register 0x10C 32 PP_CH7_UP_IEN ADC1 Post-Processing-Channel 7 Upper Threshold Interrupt Enable 23 23 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 PP_CH6_UP_IEN ADC1 Post-Processing-Channel 6 Upper Threshold Interrupt Enable 22 22 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 PP_CH5_UP_IEN ADC1 Post-Processing-Channel 5 Upper Threshold Interrupt Enable 21 21 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 PP_CH4_UP_IEN ADC1 Post-Processing-Channel 4 Upper Threshold Interrupt Enable 20 20 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 PP_CH3_UP_IEN ADC1 Post-Processing-Channel 3 Upper Threshold Interrupt Enable 19 19 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 PP_CH2_UP_IEN ADC1 Post-Processing-Channel 2 Upper Threshold Interrupt Enable 18 18 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 VS_UP_IEN ADC1 Post-Processing-Channel 1 Upper Threshold Interrupt Enable 17 17 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 PP_CH0_UP_IEN ADC1 Post-Processing-Channel 0 Upper Threshold Interrupt Enable 16 16 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 PP_CH7_LO_IEN ADC1 Post-Processing-Channel 7 Lower Threshold Interrupt Enable 7 7 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 PP_CH6_LO_IEN ADC1 Post-Processing-Channel 6 Lower Threshold Interrupt Enable 6 6 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 PP_CH5_LO_IEN ADC1 Post-Processing-Channel 5 Lower Threshold Interrupt Enable 5 5 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 PP_CH4_LO_IEN ADC1 Post-Processing-Channel 4 Lower Threshold Interrupt Enable 4 4 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 PP_CH3_LO_IEN ADC1 Post-Processing-Channel 3 Lower Threshold Interrupt Enable 3 3 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 PP_CH2_LO_IEN ADC1 Post-Processing-Channel 2 Lower Threshold Interrupt Enable 2 2 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 VS_LO_IEN ADC1 Post-Processing-Channel 1 Lower Threshold Interrupt Enable 1 1 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 PP_CH0_LO_IEN ADC1 Post-Processing-Channel 0 Lower Threshold Interrupt Enable 0 0 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 IRQS_1 ADC1 Interrupt Status 1 Register 0x64 32 DU1UP_IS ADC1 Differential Unit 1 (DU1) upper Channel Interrupt Status 25 25 read-write INACTIVE No DU upper Channel Interrupt has occurred 0b0 ACTIVE DU upper Channel Interrupt has occurred 0b1 DU1LO_IS ADC1 Differential Unit 1 (DU1) lower Channel Interrupt Status 24 24 read-write INACTIVE No DU lower Channel Interrupt has occurred 0b0 ACTIVE DU lower Channel Interrupt has occurred 0b1 ESM_IS Exceptional Sequence Measurement (ESM) Status 17 17 read-write INACTIVE No ESM has occurred 0b0 ACTIVE ESM occurred 0b1 EIM_IS Exceptional Interrupt Measurement (EIM) Status 16 16 read-write INACTIVE No EIM occurred 0b0 ACTIVE EIM occurred 0b1 IIR_CH13_IS ADC1 IIR-Filter-Channel 13 Interrupt Status 13 13 read-write INACTIVE No Channel 13 Interrupt has occurred 0b0 ACTIVE Channel 13 Interrupt has occurred 0b1 IIR_CH12_IS ADC1 IIR-Filter-Channel 12 Interrupt Status 12 12 read-write INACTIVE No Channel 12 Interrupt has occurred 0b0 ACTIVE Channel 12 Interrupt has occurred 0b1 IIR_CH11_IS ADC1 IIR-Filter-Channel 11 Interrupt Status 11 11 read-write INACTIVE No Channel 11 Interrupt has occurred 0b0 ACTIVE Channel 11 Interrupt has occurred 0b1 IIR_CH10_IS ADC1 IIR-Filter-Channel 10 Interrupt Status 10 10 read-write INACTIVE No Channel 10 Interrupt has occurred 0b0 ACTIVE Channel 10 Interrupt has occurred 0b1 IIR_CH9_IS ADC1 IIR-Filter-Channel 9 Interrupt Status 9 9 read-write INACTIVE No Channel 9 Interrupt has occurred 0b0 ACTIVE Channel 9 Interrupt has occurred 0b1 IIR_CH8_IS ADC1 IIR-Filter-Channel 8 Interrupt Status 8 8 read-write INACTIVE No Channel 8 Interrupt has occurred 0b0 ACTIVE Channel 8 Interrupt has occurred 0b1 IIR_CH7_IS ADC1 IIR-Filter-Channel 7 Interrupt Status 7 7 read-write INACTIVE No Channel 7 Interrupt has occurred 0b0 ACTIVE Channel 7 Interrupt has occurred 0b1 IIR_CH6_IS ADC1 IIR-Filter-Channel 6 Interrupt Status 6 6 read-write INACTIVE No Channel 6 Interrupt has occurred 0b0 ACTIVE Channel 6 Interrupt has occurred 0b1 IIR_CH5_IS ADC1 IIR-Filter-Channel 5 Interrupt Status 5 5 read-write INACTIVE No Channel 5 Interrupt has occurred 0b0 ACTIVE Channel 5 Interrupt has occurred 0b1 IIR_CH4_IS ADC1 IIR-Filter-Channel 4 Interrupt Status 4 4 read-write INACTIVE No Channel 4 Interrupt has occurred 0b0 ACTIVE Channel 4 Interrupt has occurred 0b1 IIR_CH3_IS ADC1 IIR-Filter-Channel 3 Interrupt Status 3 3 read-write INACTIVE No Channel 3 Interrupt has occurred 0b0 ACTIVE Channel 3 Interrupt has occurred 0b1 IIR_CH2_IS ADC1 IIR-Filter-Channel 2 Interrupt Status 2 2 read-write INACTIVE No Channel 2 Interrupt has occurred 0b0 ACTIVE Channel 2 Interrupt has occurred 0b1 VS_IS ADC1 IIR-Filter-Channel 1 Interrupt Status 1 1 read-write INACTIVE No Channel 1 Interrupt has occurred 0b0 ACTIVE Channel 1 Interrupt has occurred 0b1 IIR_CH0_IS ADC1 IIR-Filter-Channel 0 Interrupt Status 0 0 read-write INACTIVE No Channel 0 Interrupt has occurred 0b0 ACTIVE Channel 0 Interrupt has occurred 0b1 IRQS_2 ADC1 Interrupt Status 2 Register 0x100 32 PP_CH7_UP_IS ADC1 Post-Processing-Channel 7 Upper Threshold Interrupt Status 23 23 read-write INACTIVE no interrupt has occurred 0b0 ACTIVE interrupt has occurred 0b1 PP_CH6_UP_IS ADC1 Post-Processing-Channel 6 Upper Threshold Interrupt Status 22 22 read-write INACTIVE no interrupt has occurred 0b0 ACTIVE interrupt has occurred 0b1 PP_CH5_UP_IS ADC1 Post-Processing-Channel 5 Upper Threshold Interrupt Status 21 21 read-write INACTIVE no interrupt has occurred 0b0 ACTIVE interrupt has occurred 0b1 PP_CH4_UP_IS ADC1 Post-Processing-Channel 4 Upper Threshold Interrupt Status 20 20 read-write INACTIVE no interrupt has occurred 0b0 ACTIVE interrupt has occurred 0b1 PP_CH3_UP_IS ADC1 Post-Processing-Channel 3 Upper Threshold Interrupt Status 19 19 read-write INACTIVE no interrupt has occurred 0b0 ACTIVE interrupt has occurred 0b1 PP_CH2_UP_IS ADC1 Post-Processing-Channel 2 Upper Threshold Interrupt Status 18 18 read-write INACTIVE no interrupt has occurred 0b0 ACTIVE interrupt has occurred 0b1 VS_UP_IS ADC1 Post-Processing-Channel 1 Upper Threshold Interrupt Status 17 17 read-write INACTIVE no interrupt has occurred 0b0 ACTIVE interrupt has occurred 0b1 PP_CH0_UP_IS ADC1 Post-Processing-Channel 0 Upper Threshold Interrupt Status 16 16 read-write INACTIVE no interrupt has occurred 0b0 ACTIVE interrupt has occurred 0b1 PP_CH7_LO_IS ADC1 Post-Processing-Channel 7 Lower Threshold Interrupt Status 7 7 read-write INACTIVE no interrupt has occurred 0b0 ACTIVE interrupt has occurred 0b1 PP_CH6_LO_IS ADC1 Post-Processing-Channel 6 Lower Threshold Interrupt Status 6 6 read-write INACTIVE no interrupt has occurred 0b0 ACTIVE interrupt has occurred 0b1 PP_CH5_LO_IS ADC1 Post-Processing-Channel 5 Lower Threshold Interrupt Status 5 5 read-write INACTIVE no interrupt has occurred 0b0 ACTIVE interrupt has occurred 0b1 PP_CH4_LO_IS ADC1 Post-Processing-Channel 4 Lower Threshold Interrupt Status 4 4 read-write INACTIVE no interrupt has occurred 0b0 ACTIVE interrupt has occurred 0b1 PP_CH3_LO_IS ADC1 Post-Processing-Channel 3 Lower Threshold Interrupt Status 3 3 read-write INACTIVE no interrupt has occurred 0b0 ACTIVE interrupt has occurred 0b1 PP_CH2_LO_IS ADC1 Post-Processing-Channel 2 Lower Threshold Interrupt Status 2 2 read-write INACTIVE no interrupt has occurred 0b0 ACTIVE interrupt has occurred 0b1 VS_LO_IS ADC1 Post-Processing-Channel 1 Lower Threshold Interrupt Status 1 1 read-write INACTIVE no interrupt has occurred 0b0 ACTIVE interrupt has occurred 0b1 PP_CH0_LO_IS ADC1 Post-Processing-Channel 0 Lower Threshold Interrupt Status 0 0 read-write INACTIVE no interrupt has occurred 0b0 ACTIVE interrupt has occurred 0b1 MAX_TIME Maximum Time for Software Mode 0x10 32 MAX_TIME Maximum Time in Software Mode 0 7 read-write min Software mode is immediately left 0x00 max Software mode is active for 12.75 us 0xFF MMODE0_7 Overvoltage Measurement Mode of Post-Processing-Channel 0-7 0xF8 32 MMODE_D1 Measurement mode Differential Channel 1 24 25 read-write MMODE0 upper and lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 MMODE_7 Measurement mode Post-Processing-Channel 7 14 15 read-write MMODE0 upper and lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 MMODE_6 Measurement mode Post-Processing-Channel 6 12 13 read-write MMODE0 upper and lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 MMODE_5 Measurement mode Post-Processing-Channel 5 10 11 read-write MMODE0 upper and lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 MMODE_4 Measurement mode Post-Processing-Channel 4 8 9 read-write MMODE0 upper and lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 MMODE_3 Measurement mode Post-Processing-Channel 3 6 7 read-write MMODE0 upper and lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 MMODE_2 Measurement mode Post-Processing-Channel 2 4 5 read-write MMODE0 upper and lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 MMODE_1 Measurement mode Post-Processing-Channel 1 2 3 read-write MMODE0 upper and lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 MMODE_0 Measurement mode Post-Processing-Channel 0 0 1 read-write MMODE0 upper and lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 OFFSETCALIB ADC1 Offset Calibration Register 0x3C 32 OFFSET_DAC Set the Value of the Offset Calibration DAC 8 12 read-write OFFSET_SHIFT Set the Value of the Offset Shift DAC 0 2 read-write PP_MAP0_3 Post-Processing Mapping Channel 0-3 0x118 32 EN_PP_MAP3 Mapping Enable for Post-Processing-Channel 3 31 31 read-write Disabled Mapping Disabled 0b0 Enabled Mapping Enabled 0b1 RESET_PP_MAP3 Post-Processing Reset for Mapped Post-Processing-Channel 3 30 30 read-write Running Post-Processing running 0b0 Reset Post-Processing reset 0b1 PP_MAP3 Mapping of Entry Channel to Post-Processing-Channel 3 24 27 read-write Ch0 Entry Channel 0 0x0 Ch13 Entry Channel 13 0xD EN_PP_MAP2 Mapping Enable for Post-Processing-Channel 2 23 23 read-write Disabled Mapping Disabled 0b0 Enabled Mapping Enabled 0b1 RESET_PP_MAP2 Post-Processing Reset for Mapped Post-Processing-Channel 2 22 22 read-write Running Post-Processing running 0b0 Reset Post-Processing reset 0b1 PP_MAP2 Mapping of Entry Channel to Post-Processing-Channel 2 16 19 read-write Ch0 Entry Channel 0 0x0 Ch13 Entry Channel 13 0xD EN_PP_MAP1 Mapping Enable for Post-Processing-Channel 1 15 15 read-write Disabled Mapping Disabled 0b0 Enabled Mapping Enabled 0b1 RESET_PP_MAP1 Post-Processing Reset for Mapped Post-Processing-Channel 1 14 14 read-write Running Post-Processing running 0b0 Reset Post-Processing reset 0b1 EN_PP_MAP0 Mapping Enable for Post-Processing-Channel 0 7 7 read-write Disabled Mapping Disabled 0b0 Enabled Mapping Enabled 0b1 RESET_PP_MAP0 Post-Processing Reset for Mapped Post-Processing-Channel 0 6 6 read-write Running Post-Processing running 0b0 Reset Post-Processing reset 0b1 PP_MAP4_7 Post-Processing Mapping Channel 4-7 0x11C 32 EN_PP_MAP7 Mapping Enable for Post-Processing-Channel 7 31 31 read-write Disabled Mapping Disabled 0b0 Enabled Mapping Enabled 0b1 RESET_PP_MAP7 Post-Processing Reset for Mapped Post-Processing-Channel 7 30 30 read-write Running Post-Processing running 0b0 Reset Post-Processing reset 0b1 PP_MAP7 Mapping of Entry Channel to Post-Processing-Channel 7 24 27 read-write Ch0 Entry Channel 0 0x0 Ch13 Entry Channel 13 0xD EN_PP_MAP6 Mapping Enable for Post-Processing-Channel 6 23 23 read-write Disabled Mapping Disabled 0b0 Enabled Mapping Enabled 0b1 RESET_PP_MAP6 Post-Processing Reset for Mapped Post-Processing-Channel 6 22 22 read-write Running Post-Processing running 0b0 Reset Post-Processing reset 0b1 PP_MAP6 Mapping of Entry Channel to Post-Processing-Channel 6 16 19 read-write Ch0 Entry Channel 0 0x0 Ch13 Entry Channel 13 0xD EN_PP_MAP5 Mapping Enable for Post-Processing-Channel 5 15 15 read-write Disabled Mapping Disabled 0b0 Enabled Mapping Enabled 0b1 RESET_PP_MAP5 Post-Processing Reset for Mapped Post-Processing-Channel 5 14 14 read-write Running Post-Processing running 0b0 Reset Post-Processing reset 0b1 PP_MAP5 Mapping of Entry Channel to Post-Processing-Channel 5 8 11 read-write Ch0 Entry Channel 0 0x0 Ch13 Entry Channel 13 0xD EN_PP_MAP4 Mapping Enable for Post-Processing-Channel 4 7 7 read-write Disabled Mapping Disabled 0b0 Enabled Mapping Enabled 0b1 RESET_PP_MAP4 Post-Processing Reset for Mapped Post-Processing-Channel 4 6 6 read-write Running Post-Processing running 0b0 Reset Post-Processing reset 0b1 PP_MAP4 Mapping of Entry Channel to Post-Processing-Channel 4 0 3 read-write Ch0 Entry Channel 0 0x0 Ch13 Entry Channel 13 0xD SQ0_1 Measurement Unit 1 Channel Enable Bits for Cycle 0-1 0x20 32 SQ1 Sequence 1 channel enable 16 29 read-write SQ0 Sequence 0 channel enable 0 13 read-write SQ10_11 Measurement Unit 1 Channel Enable Bits for Cycle 10-11 0x34 32 SQ11 Sequence 11 channel enable 16 29 read-write SQ10 Sequence 10 channel enable 0 13 read-write SQ12_13 Measurement Unit 1 Channel Enable Bits for Cycle 12-13 0x130 32 SQ13 Sequence 13 channel enable 16 29 read-write SQ12 Sequence 12 channel enable 0 13 read-write SQ2_3 Measurement Unit 1 Channel Enable Bits for Cycle 2-3 0x24 32 SQ3 Sequence 3 channel enable 16 29 read-write SQ2 Sequence 2 channel enable 0 13 read-write SQ4_5 Measurement Unit 1 Channel Enable Bits for Cycle 4-5 0x28 32 SQ5 Sequence 5 channel enable 16 29 read-write SQ4 Sequence 4 channel enable 0 13 read-write SQ6_7 Measurement Unit 1 Channel Enable Bits for Cycle 6-7 0x2C 32 SQ7 Sequence 7 channel enable 16 29 read-write SQ6 Sequence 6 channel enable 0 13 read-write SQ8_9 Measurement Unit 1 Channel Enable Bits for Cycle 8-9 0x30 32 SQ9 Sequence 9 channel enable 16 29 read-write SQ8 Sequence 8 channel enable 0 13 read-write SQ_CH_MAP ADC1 Channel Mapping for Sequencer 0x38 32 SQ_CH12_MAP ADC mapping to CH12 12 12 read-write P2.7 P2.7 mapped to CH12 0b0 P2.4 P2.4 mapped to CH12 0b1 SQ_CH6_MAP ADC mapping to CH6 6 6 read-write P2.0 P2.0 mapped to CH6 0b0 P2.8 P2.8 mapped to CH6 0b1 SQ_CH5_MAP ADC mapping to CH5 5 5 read-write MON4 MON4 mapped to CH5 0b0 MON5 MON5 mapped to CH5 0b1 SQ_FB Sequencer Feedback Register 0x04 32 CHx Current ADC1 Channel 16 19 read-only CH0 Channel 0 enable 0b0000 CH1 Channel 1 enable 0b0001 CH2 Channel 2 enable 0b0010 CH3 Channel 3 enable 0b0011 CH4 Channel 4 enable 0b0100 CH5 Channel 5 enable 0b0101 CH6 Channel 6 enable 0b0110 CH7 Channel 7 enable 0b0111 CH8 Channel 8 enable 0b1000 CH9 Channel 9 enable 0b1001 CH10 Channel 10 enable 0b1010 CH11 Channel 11 enable 0b1011 CH12 Channel 12 enable 0b1100 CH13 Channel 13 enable 0b1101 SQx Current Active ADC1 Sequence 11 14 read-only SQ0 Sequence 0 enable 0b0000 SQ1 Sequence 1 enable 0b0001 SQ2 Sequence 2 enable 0b0010 SQ3 Sequence 3 enable 0b0011 SQ4 Sequence 4 enable 0b0100 SQ5 Sequence 5 enable 0b0101 SQ6 Sequence 6 enable 0b0110 SQ7 Sequence 7 enable 0b0111 SQ8 Sequence 8 enable 0b1000 SQ9 Sequence 9 enable 0b1001 SQ10 Sequence 10 enable 0b1010 SQ11 Sequence 11 enable 0b1011 SQ12 Sequence 12 enable 0b1100 SQ13 Sequence 13 enable 0b1101 ESM_ACTIVE ADC1 ESM active 10 10 read-only not active ESM not active 0b0 active ESM active 0b1 EIM_ACTIVE ADC1 EIM active 9 9 read-only not active EIM not active 0b0 active EIM active 0b1 SQ_STOP ADC1 Sequencer Stop Signal for DPP 8 8 read-only DPP Running Postprocessing Sequencer in running mode 0b0 DPP Stopped Postprocessing Sequencer stopped / Software Mode entered 0b1 SQ_FB Current Sequence that caused software mode 0 4 read-only SQ0 Sequence 0 enable 0b00000 SQ1 Sequence 1 enable 0b00001 SQ2 Sequence 2 enable 0b00010 SQ3 Sequence 3 enable 0b00011 SQ4 Sequence 4 enable 0b00100 SQ5 Sequence 5 enable 0b00101 SQ6 Sequence 6 enable 0b00110 SQ7 Sequence 7 enable 0b00111 SQ8 Sequence 8 enable 0b01000 SQ9 Sequence 9 enable 0b01001 SQ10 Sequence 10 enable 0b01010 SQ11 Sequence 11 enable 0b01011 SQ12 Sequence 12 enable 0b01100 SQ13 Sequence 13 enable 0b01101 ESM ESM 0b11010 SUSPEND SW Mode per Flag 0b11100 STATUS ADC1 Status Register 0xBC 32 SD_FEEDB_ON Sigma Delta Feedback Loop 31 31 read-write Disable 0b0 Enable 0b1 SOC_JITTER Programs Soc Clock Jitter 16 17 read-write 0n 0b00 3.5n 0b01 5.5n 0b10 8n 0b11 DAC_IN Programs the 2-bit DAC for functional test 0 2 read-write 0 added 0 LSB 0b000 1 added 1 LSB 0b001 2 added 2 LSB 0b010 3 added 3 LSB 0b011 STS_1 ADC1 Status 1Register 0x124 32 DU1UP_STS ADC1 Differential Unit 1 (DU1) upper Channel Status 25 25 read-write INACTIVE No DU upper Channel Status has occurred 0b0 ACTIVE DU upper Channel Status has occurred 0b1 DU1LO_STS ADC1 Differential Unit 1 (DU1) lower Channel Status 24 24 read-write INACTIVE No DU lower Channel Status has occurred 0b0 ACTIVE DU lower Channel Status has occurred 0b1 STS_2 ADC1 Status 2 Register 0x104 32 PP_CH7_UP_STS ADC1 Post-Processing-Channel 7 Upper Threshold Status 23 23 read-only Below limit Status below upper threshold 0b0 Above limit Upper threshold exceeded 0b1 PP_CH6_UP_STS ADC1 Post-Processing-Channel 6 Upper Threshold Status 22 22 read-only Below limit Status below upper threshold 0b0 Above limit Upper threshold exceeded 0b1 PP_CH5_UP_STS ADC1 Post-Processing-Channel 5 Upper Threshold Status 21 21 read-only Below limit Status below upper threshold 0b0 Above limit Upper threshold exceeded 0b1 PP_CH4_UP_STS ADC1 Post-Processing-Channel 4 Upper Threshold Status 20 20 read-only Below limit Status below upper threshold 0b0 Above limit Upper threshold exceeded 0b1 PP_CH3_UP_STS ADC1 Post-Processing-Channel 3 Upper Threshold Status 19 19 read-only Below limit Status below upper threshold 0b0 Above limit Upper threshold exceeded 0b1 PP_CH2_UP_STS ADC1 Post-Processing-Channel 2 Upper Threshold Status 18 18 read-only Below limit Status below upper threshold 0b0 Above limit Upper threshold exceeded 0b1 VS_UP_STS ADC1 Post-Processing-Channel 1 Upper Threshold Status 17 17 read-only Below limit Status below upper threshold 0b0 Above limit Upper threshold exceeded 0b1 PP_CH0_UP_STS ADC1 Post-Processing-Channel 0 Upper Threshold Status 16 16 read-only Below limit Status below upper threshold 0b0 Above limit Upper threshold exceeded 0b1 PP_CH7_LO_STS ADC1 Post-Processing-Channel 7 Lower Threshold Status 7 7 read-only Below limit Status below upper threshold 0b0 Above limit Upper threshold exceeded 0b1 PP_CH6_LO_STS ADC1 Post-Processing-Channel 6 Lower Threshold Status 6 6 read-only Below limit Status below upper threshold 0b0 Above limit Upper threshold exceeded 0b1 PP_CH5_LO_STS ADC1 Post-Processing-Channel 5 Lower Threshold Status 5 5 read-only Below limit Status below upper threshold 0b0 Above limit Upper threshold exceeded 0b1 PP_CH4_LO_STS ADC1 Post-Processing-Channel 4 Lower Threshold Status 4 4 read-only Below limit Status below upper threshold 0b0 Above limit Upper threshold exceeded 0b1 PP_CH3_LO_STS ADC1 Post-Processing-Channel 3 Lower Threshold Status 3 3 read-only Below limit Status below upper threshold 0b0 Above limit Upper threshold exceeded 0b1 PP_CH2_LO_STS ADC1 Post-Processing-Channel 2 Lower Threshold Status 2 2 read-only Below limit Status below upper threshold 0b0 Above limit Upper threshold exceeded 0b1 VS_LO_STS ADC1 Post-Processing-Channel 1 Lower Threshold Status 1 1 read-only Below limit Status below upper threshold 0b0 Above limit Upper threshold exceeded 0b1 PP_CH0_LO_STS ADC1 Post-Processing-Channel 0 Lower Threshold Status 0 0 read-only Below limit Status below upper threshold 0b0 Above limit Upper threshold exceeded 0b1 STSCLR_1 ADC1 Status Clear 1 Register 0x128 32 DU1UP_SC ADC1 Differential Unit 1 (DU1) upper Channel Status Clear 25 25 write-only INACTIVE No DU upper Channel Status has occurred 0b0 ACTIVE DU upper Channel Status has occurred 0b1 DU1LO_SC ADC1 Differential Unit 1 (DU1) lower Channel Status Clear 24 24 write-only INACTIVE No DU lower Channel Status has occurred 0b0 ACTIVE DU lower Channel Status has occurred 0b1 TH0_3_LOWER Lower Comparator Trigger Level Post-Processing-Channel 0-3 0x40 32 PP_CH3_LOW Post-Processing-Channel 3 lower trigger level 24 31 read-write PP_CH2_LOW Post-Processing-Channel 2 lower trigger level 16 23 read-write PP_CH1_LOW Post-Processing-Channel 1 lower trigger level 8 15 read-write PP_CH0_LOW Post-Processing-Channel 0 lower trigger level 0 7 read-write TH0_3_UPPER Upper Comparator Trigger Level Post-Processing-Channel 0-3 0xC8 32 PP_CH3_UP Post-Processing-Channel 3 upper trigger level 24 31 read-write PP_CH2_UP Post-Processing-Channel 2 upper trigger level 16 23 read-write PP_CH1_UP Post-Processing-Channel 1 upper trigger level 8 15 read-write PP_CH0_UP Post-Processing-Channel 0 upper trigger level 0 7 read-write TH4_7_LOWER Lower Comparator Trigger Level Post-Processing-Channel 4-7 0x44 32 PP_CH7_LOW Post-Processing-Channel 7 lower trigger level 24 31 read-write PP_CH6_LOW Post-Processing-Channel 6 lower trigger level 16 23 read-write PP_CH5_LOW Post-Processing-Channel 5 lower trigger level 8 15 read-write PP_CH4_LOW Post-Processing-Channel 4 lower trigger level 0 7 read-write TH4_7_UPPER Upper Comparator Trigger Level Post-Processing-Channel 4-7 0xCC 32 PP_CH7_UP Post-Processing-Channel 7 upper trigger level 24 31 read-write PP_CH6_UP Post-Processing-Channel 6upper trigger level 16 23 read-write PP_CH5_UP Post-Processing-Channel 5 upper trigger level 8 15 read-write PP_CH4_UP Post-Processing-Channel 4 upper trigger level 0 7 read-write ADC2 ADC2 0x4801C000 0x0 0x2000 registers INTISR2 Interrupt node 2: ADC2, Timer3 2 CAL_CH0_1 Calibration for Channel 0 and 1 0x34 32 GAIN_CH1 Gain Calibration for channel 1 24 31 read-write OFFS_CH1 Offset Calibration for channel 1 16 20 read-write GAIN_CH0 Gain Calibration for channel 0 8 15 read-write OFFS_CH0 Offset Calibration for channel 0 0 4 read-write CAL_CH2_3 Calibration for Channel 2 and 3 0x38 32 GAIN_CH3 Gain Calibration for channel 3 24 31 read-write OFFS_CH3 Offset Calibration for channel 3 16 20 read-write GAIN_CH2 Gain Calibration for channel 2 8 15 read-write OFFS_CH2 Offset Calibration for channel 2 0 4 read-write CAL_CH4_5 Calibration for Channel 4 and 5 0x3C 32 GAIN_CH5 Gain Calibration for channel 5 24 31 read-write OFFS_CH5 Offset Calibration for channel 5 16 20 read-write GAIN_CH4 Gain Calibration for channel 4 8 15 read-write OFFS_CH4 Offset Calibration for channel 4 0 4 read-write CAL_CH6_7 Calibration for Channel 6 and 7 0x40 32 GAIN_CH7 Gain Calibration for channel 7 24 31 read-write OFFS_CH7 Offset Calibration for channel 7 16 20 read-write GAIN_CH6 Gain Calibration for channel 6 8 15 read-write OFFS_CH6 Offset Calibration for channel 6 0 4 read-write CAL_CH8_9 Calibration for Channel 8 0x44 32 GAIN_CH8 Gain Calibration for channel 8 8 15 read-write OFFS_CH8 Offset Calibration for channel 8 0 4 read-write CHx_EIM Channel Settings Bits for Exceptional Interrupt Measurement 0x08 32 SEL Exceptional interrupt measurement (EIM) Trigger select 12 12 read-write GPT12PISEL.T3_GPT12_SEL Signal according to SCU_GPT12PISEL.T3_GPT12SEL setting 0b0 CP_clk Charge-pump clock 0b1 EN Exceptional interrupt measurement (EIM) Trigger Event enable 11 11 read-write DISABLE start of EIM disabled 0b0 ENABLE start of IEM enabled 0b1 REP Repeat count for exceptional interrupt measurement (EIM) 8 10 read-write 1 Measurement (minimum or continuous measurement as long as trigger signals stays high, 1 / continuous SOC generated for ADC8) 0b000 2 Measurements (2 SOC generated for ADC8) 0b001 4 Measurements (4 SOC generated for ADC8) 0b010 8 Measurements (8 SOC generated for ADC8) 0b011 16 Measurements (16 SOC generated for ADC8) 0b100 32 Measurements (32 SOC generated for ADC8) 0b101 64 Measurements (64 SOC generated for ADC8) 0b110 128 Measurements (128 SOC generated for ADC8) 0b111 CHx_SEL Channel set for exceptional interrupt measurement (EIM) 0 3 read-write CH0_EN Channel 0 enable 0b0000 CH1_EN Channel 1 enable 0b0001 CH2_EN Channel 2 enable 0b0010 CH3_EN Channel 3 enable 0b0011 CH4_EN Channel 4 enable 0b0100 CH5_EN Channel 5 enable 0b0101 CH6_EN Channel 6 enable 0b0110 CH7_EN Channel 7 enable 0b0111 CH8_EN Channel 8 enable 0b1000 CNT0_3_LOWER Lower Counter Trigger Level Channel 0 - 3 0x98 32 HYST_LO_CH3 Channel 3 lower hysteresis 27 28 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_CH3 Lower timer trigger threshold channel 3 24 25 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_LO_CH2 Channel 2 lower hysteresis 19 20 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_CH2 Lower timer trigger threshold channel 2 16 17 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_LO_CH1 Channel 1 lower hysteresis 11 12 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_CH1 Lower timer trigger threshold channel 1 8 9 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_LO_CH0 Channel 0 lower hysteresis 3 4 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_CH0 Lower timer trigger threshold channel 0 0 1 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 CNT0_3_UPPER Upper Counter Trigger Level Channel 0 - 3 0xA4 32 HYST_UP_CH3 Channel 3 upper hysteresis 27 28 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_CH3 Upper timer trigger threshold channel 3 24 25 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_UP_CH2 Channel 2 upper hysteresis 19 20 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_CH2 Upper timer trigger threshold channel 2 16 17 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_UP_CH1 Channel 1 upper hysteresis 11 12 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_CH1 Upper timer trigger threshold channel 1 8 9 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_UP_CH0 Channel 0 upper hysteresis 3 4 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_CH0 Upper timer trigger threshold channel 0 0 1 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 CNT4_7_LOWER Lower Counter Trigger Level Channel 4 to 7 0x9C 32 HYST_LO_CH7 Channel 7 lower hysteresis 27 28 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_CH7 Lower timer trigger threshold channel 7 24 25 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_LO_CH6 Channel 6 lower hysteresis 19 20 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_CH6 Lower timer trigger threshold channel 6 16 17 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_LO_CH5 Channel 5 lower hysteresis 11 12 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_CH5 Lower timer trigger threshold channel 5 8 9 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_LO_CH4 Channel 4 lower hysteresis 3 4 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_CH4 Lower timer trigger threshold channel 4 0 1 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 CNT4_7_UPPER Upper Counter Trigger Level Channel 4 to 7 0xA8 32 HYST_UP_CH7 Channel 7 upper hysteresis 27 28 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_CH7 Upper timer trigger threshold channel 7 24 25 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_UP_CH6 Channel 6 upper hysteresis 19 20 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_CH6 Upper timer trigger threshold channel 6 16 17 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_UP_CH5 Channel 5 upper hysteresis 11 12 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_CH5 Upper timer trigger threshold channel 5 8 9 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 HYST_UP_CH4 Channel 4 upper hysteresis 3 4 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_CH4 Upper timer trigger threshold channel 4 0 1 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 CNT8_11_LOWER Lower Counter Trigger Level Channel 8 0xA0 32 HYST_LO_CH8 Channel 8 lower hysteresis 3 4 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_CH8 Lower timer trigger threshold channel 8 0 1 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 CNT8_11_UPPER Upper Counter Trigger Level Channel 8 0xAC 32 HYST_UP_CH8 Channel 8 upper hysteresis 3 4 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_CH8 Upper timer trigger threshold channel 8 0 1 read-write 1 1 measurement 0x0 2 2 measurements 0x1 4 4 measurements 0x2 7 7 measurements 0x3 CTRL1 Measurement Unit Control Register 1 0x14 32 CALIB_EN_8_0 Calibration Enable for Channels 8 to 0 0 8 read-write CH0_EN Channel 0 calibration enable 0b000000001 CH1_EN Channel 1 calibration enable 0b000000010 CH2_EN Channel 2 calibration enable 0b000000100 CH3_EN Channel 3 calibration enable 0b000001000 CH4_EN Channel 4 calibration enable 0b000010000 CH5_EN Channel 5 calibration enable 0b000100000 CH6_EN Channel 6 calibration enable 0b001000000 CH7_EN Channel 7 calibration enable 0b010000000 CH8_EN Channel 8 calibration enable 0b100000000 CTRL2 Measurement Unit Control Register 2 0x18 32 SAMPLE_TIME_int Sample time of ADC2 8 11 read-write MICLK4 4 MI_CLK clock periods 0x0 MICLK6 6 MI_CLK clock periods 0x1 MICLK8 8 MI_CLK clock periods 0x2 MICLK10 10 MI_CLK clock periods 0x3 MICLK12 12 MI_CLK clock periods (default) 0x4 MICLK14 14 MI_CLK clock periods 0x5 MICLK16 16 MI_CLK clock periods 0x6 MICLK18 18 MI_CLK clock periods 0x7 MICLK20 20 MI_CLK clock periods 0x8 MICLK22 22 MI_CLK clock periods 0x9 MCM_RDY Ready Signal for MCM after Power On or Reset 7 7 read-only MCM Not Ready Measurement Core Module in startup phase 0b0 MCM Ready Measurement Core Module start-up phase finished 0b1 MCM_PD_N Power Down Signal for MCM 0 0 read-write MCM Disabled Measurement Core Module disabled 0b0 MCM Enabled Measurement Core Module enabled 0b1 CTRL4 Measurement Unit Control Register 4 0x1C 32 FILT_OUT_SEL_8_0 Output Filter Selection for Channels 0 to 8 0 8 read-write CTRL_STS ADC2 Control and Status Register 0x00 32 IN_MUX_SEL Channel for software mode 8 11 read-write CH0_EN Channel 0 enable 0b0000 CH1_EN Channel 1 enable 0b0001 CH2_EN Channel 2 enable 0b0010 CH3_EN Channel 3 enable 0b0011 CH4_EN Channel 4 enable 0b0100 CH5_EN Channel 5 enable 0b0101 CH6_EN Channel 6 enable 0b0110 CH7_EN Channel 7 enable 0b0111 CH8_EN Channel 8 enable 0b1000 EOC ADC2 End of Conversion in software mode 3 3 read-only Pending conversion still running 0b0 Finished conversion has finished 0b1 SOS ADC2 Start of Sampling/Conversion (software mode) 2 2 read-write Disable no conversion is started 0b0 Enable conversion is started 0b1 PD_N ADC2 Power Down Signal 0 0 read-write POWER DOWN ADC2 is powered down 0b0 ACTIVE ADC2 is switched on 0b1 FILT_OUT0 ADC or Filter Output Channel 0 0x50 32 OUT_CH0 ADC or filter output value channel 0 0 9 read-only FILT_OUT1 ADC or Filter Output Channel 1 0x54 32 OUT_CH1 ADC or filter output value channel 1 0 9 read-only FILT_OUT2 ADC or Filter Output Channel 2 0x58 32 OUT_CH2 ADC or filter output value channel 2 0 9 read-only FILT_OUT3 ADC or Filter Output Channel 3 0x5C 32 OUT_CH3 ADC or filter output value channel 3 0 9 read-only FILT_OUT4 ADC or Filter Output Channel 4 0x60 32 OUT_CH4 ADC or filter output value channel 4 0 9 read-only FILT_OUT5 ADC or Filter Output Channel 5 0x64 32 OUT_CH5 ADC or filter output value channel 5 0 9 read-only FILT_OUT6 ADC or Filter Output Channel 6 0x68 32 OUT_CH6 ADC or filter output value channel 6 0 9 read-only FILT_OUT7 ADC or Filter Output Channel 7 0x6C 32 OUT_CH7 ADC or filter output value channel 7 0 9 read-only FILT_OUT8 ADC or Filter Output Channel 8 0x70 32 OUT_CH8 ADC or filter output value channel 8 0 9 read-only FILT_UPLO_CTRL Upper and Lower Threshold Filter Enable 0x78 32 UPLOEN_Ch8 Upper and lower threshold IIR filter enable ch 8 8 8 read-write Disable 0b0 Enable 0b1 UPLOEN_Ch7 Upper and lower threshold IIR filter enable ch 7 7 7 read-write Disable 0b0 Enable 0b1 UPLOEN_Ch6 Upper and lower threshold IIR filter enable ch 6 6 6 read-write Disable 0b0 Enable 0b1 UPLOEN_Ch5 Upper and lower threshold IIR filter enable ch 5 5 5 read-write Disable 0b0 Enable 0b1 UPLOEN_Ch4 Upper and lower threshold IIR filter enable ch 4 4 4 read-write Disable 0b0 Enable 0b1 UPLOEN_Ch3 Upper and lower threshold IIR filter enable ch 3 3 3 read-write Disable 0b0 Enable 0b1 UPLOEN_Ch2 Upper and lower threshold IIR filter enable ch 2 2 2 read-write Disable 0b0 Enable 0b1 UPLOEN_Ch1 Upper and lower threshold IIR filter enable ch 1 1 1 read-write Disable 0b0 Enable 0b1 UPLOEN_Ch0 Upper and lower threshold IIR filter enable ch 0 0 0 read-write Disable 0b0 Enable 0b1 FILTCOEFF0_8 Filter Coefficients ADC Channel 0-8 0x48 32 A_CH8 Filter Coefficient A for ADC channel 8 16 17 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 A_CH7 Filter Coefficient A for ADC channel 7 14 15 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 A_CH6 Filter Coefficient A for ADC channel 6 12 13 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 A_CH5 Filter Coefficient A for ADC channel 5 10 11 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 A_CH4 Filter Coefficient A for ADC channel 4 8 9 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 A_CH3 Filter Coefficient A for ADC channel 3 6 7 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 A_CH2 Filter Coefficient A for ADC channel 2 4 5 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 A_CH1 Filter Coefficient A for ADC channel 1 2 3 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 A_CH0 Filter Coefficient A for ADC channel 0 0 1 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 MAX_TIME Maximum Time for Software Mode 0x10 32 MAX_TIME Maximum Time in Software Mode 0 7 read-write min Software mode is not entered 0x00 01 Software mode is active for 3 clock cycles 0x01 max Software mode is active for 257 clock cycles (typ. 12.85 us) 0xFF MMODE0_8 Measurement Mode of Ch 0-8 0xB0 32 MSEL_Ch8 Measurement mode ch 8 16 17 read-write MMODE0 upper and lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 MSEL_Ch7 Measurement mode ch 7 14 15 read-write MMODE0 upper and lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 MSEL_Ch6 Measurement mode ch 6 12 13 read-write MMODE0 upper and lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 MSEL_Ch5 Measurement mode ch 5 10 11 read-write MMODE0 upper and lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 MSEL_Ch4 Measurement mode ch 4 8 9 read-write MMODE0 upper and lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 MSEL_Ch3 Measurement mode ch 3 6 7 read-write MMODE0 upper and lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 MSEL_Ch2 Measurement mode ch 2 4 5 read-write MMODE0 upper and lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 MSEL_Ch1 Measurement mode ch 1 2 3 read-write MMODE0 upper and lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 MSEL_Ch0 Measurement mode ch 0 0 1 read-write MMODE0 upper and lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 SQ0_1 Measurement Channel Enable Bits for Sequence 0-1 0x20 32 SQ1 Sequence 1 channel enable 16 24 read-write CH0_EN Channel 0 enable 0b000000001 CH1_EN Channel 1 enable 0b000000010 CH2_EN Channel 2 enable 0b000000100 CH3_EN Channel 3 enable 0b000001000 CH4_EN Channel 4 enable 0b000010000 CH5_EN Channel 5 enable 0b000100000 CH6_EN Channel 6 enable 0b001000000 CH7_EN Channel 7 enable 0b010000000 CH8_EN Channel 8 enable 0b100000000 SQ0 Sequence 0 channel enable 0 8 read-write CH0_EN Channel 0 enable 0b000000001 CH1_EN Channel 1 enable 0b000000010 CH2_EN Channel 2 enable 0b000000100 CH3_EN Channel 3 enable 0b000001000 CH4_EN Channel 4 enable 0b000010000 CH5_EN Channel 5 enable 0b000100000 CH6_EN Channel 6 enable 0b001000000 CH7_EN Channel 7 enable 0b010000000 CH8_EN Channel 8 enable 0b100000000 SQ2_3 Measurement Channel Enable Bits for Sequence 2-3 0x28 32 SQ3 Sequence 3 channel enable 16 24 read-write CH0_EN Channel 0 enable 0b000000001 CH1_EN Channel 1 enable 0b000000010 CH2_EN Channel 2 enable 0b000000100 CH3_EN Channel 3 enable 0b000001000 CH4_EN Channel 4 enable 0b000010000 CH5_EN Channel 5 enable 0b000100000 CH6_EN Channel 6 enable 0b001000000 CH7_EN Channel 7 enable 0b010000000 CH8_EN Channel 8 enable 0b100000000 SQ2 Sequence 2 channel enable 0 8 read-write CH0_EN Channel 0 enable 0b000000001 CH1_EN Channel 1 enable 0b000000010 CH2_EN Channel 2 enable 0b000000100 CH3_EN Channel 3 enable 0b000001000 CH4_EN Channel 4 enable 0b000010000 CH5_EN Channel 5 enable 0b000100000 CH6_EN Channel 6 enable 0b001000000 CH7_EN Channel 7 enable 0b010000000 CH8_EN Channel 8 enable 0b100000000 SQ4_5 Measurement Channel Enable Bits for Sequence 4 - 5 0x24 32 SQ5 Sequence 5 channel enable 16 24 read-write CH0_EN Channel 0 enable 0b000000001 CH1_EN Channel 1 enable 0b000000010 CH2_EN Channel 2 enable 0b000000100 CH3_EN Channel 3 enable 0b000001000 CH4_EN Channel 4 enable 0b000010000 CH5_EN Channel 5 enable 0b000100000 CH6_EN Channel 6 enable 0b001000000 CH7_EN Channel 7 enable 0b010000000 CH8_EN Channel 8 enable 0b100000000 SQ4 Sequence 4 channel enable 0 8 read-write CH0_EN Channel 0 enable 0b000000001 CH1_EN Channel 1 enable 0b000000010 CH2_EN Channel 2 enable 0b000000100 CH3_EN Channel 3 enable 0b000001000 CH4_EN Channel 4 enable 0b000010000 CH5_EN Channel 5 enable 0b000100000 CH6_EN Channel 6 enable 0b001000000 CH7_EN Channel 7 enable 0b010000000 CH8_EN Channel 8 enable 0b100000000 SQ6_7 Measurement Channel Enable Bits for Sequence 6 - 7 0x2C 32 SQ7 Sequence 7 channel enable 16 24 read-write CH0_EN Channel 0 enable 0b000000001 CH1_EN Channel 1 enable 0b000000010 CH2_EN Channel 2 enable 0b000000100 CH3_EN Channel 3 enable 0b000001000 CH4_EN Channel 4 enable 0b000010000 CH5_EN Channel 5 enable 0b000100000 CH6_EN Channel 6 enable 0b001000000 CH7_EN Channel 7 enable 0b010000000 CH8_EN Channel 8 enable 0b100000000 SQ6 Sequence 6 channel enable 0 8 read-write CH0_EN Channel 0 enable 0b000000001 CH1_EN Channel 1 enable 0b000000010 CH2_EN Channel 2 enable 0b000000100 CH3_EN Channel 3 enable 0b000001000 CH4_EN Channel 4 enable 0b000010000 CH5_EN Channel 5 enable 0b000100000 CH6_EN Channel 6 enable 0b001000000 CH7_EN Channel 7 enable 0b010000000 CH8_EN Channel 8 enable 0b100000000 SQ8_9 Measurement Channel Enable Bits for Sequence 8 0x30 32 SQ8 Sequence 8 channel enable 0 8 read-write CH0_EN Channel 0 enable 0b000000001 CH1_EN Channel 1 enable 0b000000010 CH2_EN Channel 2 enable 0b000000100 CH3_EN Channel 3 enable 0b000001000 CH4_EN Channel 4 enable 0b000010000 CH5_EN Channel 5 enable 0b000100000 CH6_EN Channel 6 enable 0b001000000 CH7_EN Channel 7 enable 0b010000000 CH8_EN Channel 8 enable 0b100000000 SQ_FB Sequencer Feedback Register 0x04 32 CHx Current active ADC2 Channel (in normal mode) 16 19 read-only CH0 Channel 0 0b0000 CH1 Channel 1 0b0001 CH2 Channel 2 0b0010 CH3 Channel 3 0b0011 CH4 Channel 4 0b0100 CH5 Channel 5 0b0101 CH6 Channel 6 0b0110 CH7 Channel 7 0b0111 CH8 Channel 8 0b1000 SQx Current active ADC2 Sequence (in normal mode) 11 14 read-only SQ0 Sequence 0 0b0000 SQ1 Sequence 1 0b0001 SQ2 Sequence 2 0b0010 SQ3 Sequence 3 0b0011 SQ4 Sequence 4 0b0100 SQ5 Sequence 5 0b0101 SQ6 Sequence 6 0b0110 SQ7 Sequence 7 0b0111 SQ8 Sequence 8 0b1000 SQ9 Startup sequence 0b1001 EIM_ACTIVE ADC2 EIM active 9 9 read-only not active EIM not active 0b0 active EIM active 0b1 SQ_STOP ADC2 Sequencer Stop Signal for DPP 8 8 read-only DPP Running Postprocessing Sequencer in running mode 0b0 DPP Stopped Postprocessing Sequencer stopped / Software Mode entered 0b1 SQ_FB Current Sequence that caused software mode 0 3 read-only SQ0 Sequence 0 0b0000 SQ1 Sequence 1 0b0001 SQ2 Sequence 2 0b0010 SQ3 Sequence 3 0b0011 SQ4 Sequence 4 0b0100 SQ5 Sequence 5 0b0101 SQ6 Sequence 6 0b0110 SQ7 Sequence 7 0b0111 SQ8 Sequence 8 0b1000 CH_MASK Sequence was 0 only after masking; SWM not entered 0b1011 SUSPEND Debug Suspend Mode 0b1100 STATUS ADC2 HV Status Register 0xBC 32 READY HVADC Ready bit 1 1 read-only Not ready Module in power down or in init phase 0b0 Ready set automatically 5 ADC clock cycles after module is enabled 0b1 TH0_3_LOWER Lower Comparator Trigger Level Channel 0 -3 0x80 32 THLO_CH3 Channel 3 lower trigger level 24 31 read-write THLO_CH2 Channel 2 lower trigger level 16 23 read-write THLO_CH1 Channel 1 lower trigger level 8 15 read-write THLO_CH0 Channel 0 lower trigger level 0 7 read-write TH0_3_UPPER Upper Comparator Trigger Level Channel 0-3 0x8C 32 THUP_CH3 Channel 3 upper trigger level 24 31 read-write THUP_CH2 Channel 2 upper trigger level 16 23 read-write THUP_CH1 Channel 1 upper trigger level 8 15 read-write THUP_CH0 Channel 0 upper trigger level 0 7 read-write TH4_7_LOWER Lower Comparator Trigger Level Channel 4 to 7 0x84 32 THLO_CH7 Channel 7 lower trigger level 24 31 read-write THLO_CH6 Channel 6 lower trigger level 16 23 read-write THLO_CH5 Channel 5 lower trigger level 8 15 read-write THLO_CH4 Channel 4 lower trigger level 0 7 read-write TH4_7_UPPER Upper Comparator Trigger Level Channel 4 -7 0x90 32 THUP_CH7 Channel 7 upper trigger level 24 31 read-write THUP_CH6 Channel 6 upper trigger level 16 23 read-write THUP_CH5 Channel 5 upper trigger level 8 15 read-write THUP_CH4 Channel 4 upper trigger level 0 7 read-write TH8_11_LOWER Lower Comparator Trigger Level Channel 8 0x88 32 THLO_CH8 Channel 8 lower trigger level 0 7 read-write TH8_11_UPPER Upper Comparator Trigger Level Channel 8 0x94 32 THUP_CH8 Channel 8 upper trigger level 0 7 read-write BDRV BDRV 0x40034000 0x0 0x4000 registers INTISR17 Interrupt node 17: BDRV LS1, OC, OT, OL 17 INTISR18 Interrupt node 18: BDRV LS2, OC, OT, OL 18 INTISR19 Interrupt node 19: BDRV HS1, OC, OT, OL 19 INTISR20 Interrupt node 20: BDRV HS2, OC, OT, OL 20 ASEQC Adaptive Slewrate Sequencer Control Register 0x90 32 HB2OFFHYSTEN Half Bridge 2 Optimizer Hysteresis for Switch Off Enable Bit 23 23 read-write OFF current optimizer hysteresis is not enabled 0x0 ON current optimizer hysteresis is enabled 0x1 HB2ONHYSTEN Half Bridge 2 Optimizer Hysteresis for Switch On Enable Bit 22 22 read-write OFF current optimizer hysteresis is not enabled 0x0 ON current optimizer hysteresis is enabled 0x1 HB2OPTOFFACT Half Bridge 2 Optimizer for Switch Off Active Bit 21 21 read-write OFF current optimizer is not active 0x0 ON current optimizer is active 0x1 HB2OPTONACT Half Bridge 2 Optimizer for Switch On Active Bit 20 20 read-write OFF current optimizer is not active 0x0 ON current optimizer is active 0x1 HB2ASMOFFEN Half Bridge 2 Adaptive Sequencer Mode for Switch Off Enable 17 17 read-write Disable adaptive slew rate sequencer is disabled 0x0 Enable adaptive slew rate sequencer is enabled 0x1 HB2ASMONEN Half Bridge 2 Adaptive Sequencer Mode for Switch On Enable 16 16 read-write Disable adaptive slew rate sequencer is disabled 0x0 Enable adaptive slew rate sequencer is enabled 0x1 HB1OFFHYSTEN Half Bridge 1 Optimizer Hysteresis for Switch Off Enable Bit 7 7 read-write OFF current optimizer hysteresis is not enabled 0x0 ON current optimizer hysteresis is enabled 0x1 HB1ONHYSTEN Half Bridge 1 Optimizer Hysteresis for Switch On Enable Bit 6 6 read-write OFF current optimizer hysteresis is not enabled 0x0 ON current optimizer hysteresis is enabled 0x1 HB1OPTOFFACT Half Bridge 1 Optimizer for Switch Off Active Bit 5 5 read-write OFF current optimizer is not active 0x0 ON current optimizer is active 0x1 HB1OPTONACT Half Bridge 1 Optimizer for Switch On Active Bit 4 4 read-write OFF current optimizer is not active 0x0 ON current optimizer is active 0x1 HB1ASMOFFEN Half Bridge 1 Adaptive Sequencer Mode for Switch Off Enable 1 1 read-write Disable adaptive slew rate sequencer is disabled 0x0 Enable adaptive slew rate sequencer is enabled 0x1 HB1ASMONEN Half Bridge 1 Adaptive Sequencer Mode for Switch On Enable 0 0 read-write Disable adaptive slew rate sequencer is disabled 0x0 Enable adaptive slew rate sequencer is enabled 0x1 ASEQERRCNT Adaptive Slewrate Sequencer Error Counter Control Register 0xD8 32 HB2MFERRCNT Half Bridge 2-Measurement Failure Error Counter Setting 20 21 read-write 2 Events Error Flag is set after 2 Events 0b00 4 Events Error Flag is set after 4 Events 0b01 8 Events Error Flag is set after 8 Events 0b10 15 Events Error Flag is set after 15 Events 0b11 HB2T12ONERRCNT Half Bridge 2-T12 On Error Counter Setting 18 19 read-write 2 Events Error Flag is set after 2 Events 0b00 4 Events Error Flag is set after 4 Events 0b01 8 Events Error Flag is set after 8 Events 0b10 15 Events Error Flag is set after 15 Events 0b11 HB2T1OFFERRCNT Half Bridge 2-T1 Off Error Counter Setting 16 17 read-write 2 Events Error Flag is set after 2 Events 0b00 4 Events Error Flag is set after 4 Events 0b01 8 Events Error Flag is set after 8 Events 0b10 15 Events Error Flag is set after 15 Events 0b11 HB1MFERRCNT Half Bridge 1-Measurement Failure Error Counter Setting 4 5 read-write 2 Events Error Flag is set after 2 Events 0b00 4 Events Error Flag is set after 4 Events 0b01 8 Events Error Flag is set after 8 Events 0b10 15 Events Error Flag is set after 15 Events 0b11 HB1T12ONERRCNT Half Bridge 1-T12 On Error Counter Setting 2 3 read-write 2 Events Error Flag is set after 2 Events 0b00 4 Events Error Flag is set after 4 Events 0b01 8 Events Error Flag is set after 8 Events 0b10 15 Events Error Flag is set after 15 Events 0b11 HB1T1OFFERRCNT Half Bridge 1-T1 Off Error Counter Setting 0 1 read-write 2 Events Error Flag is set after 2 Events 0b00 4 Events Error Flag is set after 4 Events 0b01 8 Events Error Flag is set after 8 Events 0b10 15 Events Error Flag is set after 15 Events 0b11 ASEQIOFFMAX Adaptive Slewrate Sequencer Off Phase Maximum Current Setting 0xB4 32 I1OFFMAX Slew rate sequencer off-phase 1 max. current setting 0 5 read-write min. current IDISCHGmin 0x0 max. current IDISCHGmax 0x3F ASEQIOFFMIN Adaptive Slewrate Sequencer Off Phase Minimum Current Setting 0xA4 32 I1OFFMIN Slew rate sequencer off-phase 1 min. current setting 0 5 read-write min. current IDISCHGmin 0x0 max. current IDISCHGmax 0x3F ASEQIONMAX Adaptive Slewrate Sequencer On Phase Maximum Current Setting 0xB0 32 I1ONMAX Slew rate sequencer on-phase 1 max. current setting 0 5 read-write min. current ICHGmin 0x0 max. current ICHGmax 0x3F ASEQIONMIN Adaptive Slewrate Sequencer On Phase Minimum Current Setting 0xA0 32 I1ONMIN Slew rate sequencer on-phase 1 min. current setting 0 5 read-write min. current ICHGmin 0x0 max. current ICHGmax 0x3F ASEQSTS Adaptive Slewrate Sequencer Status Register 0x94 32 HB2ONMF Half Bridge 2- On Adaptive Mode Measurement Failure 31 31 read-only no Error No Measurement Failure 0x0 Error Measurement Failure 0x1 HB2OFFMF Half Bridge 2- Off Adaptive Mode Measurement Failure 30 30 read-only no Error No Measurement Failure 0x0 Error Measurement Failure 0x1 HB2I1ONMIN Half Bridge 2-I1 On Min Value reached 23 23 read-only no Error Min Value not reached 0x0 Error Min Value reached 0x1 HB2T12ONMIN Half Bridge 2-T12 On Min Value reached 22 22 read-only no Error Min Value not reached 0x0 Error Min Value reached 0x1 HB2I1ONMAX Half Bridge 2-I1 On Max Value reached 21 21 read-only no Error Max Value not reached 0x0 Error Max Value reached 0x1 HB2T12ONMAX Half Bridge 2-T12 On Max Value reached 20 20 read-only no Error Max Value not reached 0x0 Error Max Value reached 0x1 HB2I1OFFMIN Half Bridge 2-I1 Off Min Value reached 19 19 read-only no Error Min Value not reached 0x0 Error Min Value reached 0x1 HB2T1OFFMIN Half Bridge 2-T1 Off Min Value reached 18 18 read-only no Error Min Value not reached 0x0 Error Min Value reached 0x1 HB2I1OFFMAX Half Bridge 2-I1 Off Max Value reached 17 17 read-only no Error Max Value not reached 0x0 Error Max Value reached 0x1 HB2T1OFFMAX Half Bridge 2-T1 Off Max Value reached 16 16 read-only no Error Max Value not reached 0x0 Error Max Value reached 0x1 HB1ONMF Half Bridge 1-On Adaptive Mode Measurement Failure 15 15 read-only no Error No Measurement Failure 0x0 Error Measurement Failure 0x1 HB1OFFMF Half Bridge 1-Off Adaptive Mode Measurement Failure 14 14 read-only no Error No Measurement Failure 0x0 Error Measurement Failure 0x1 HB1I1ONMIN Half Bridge 1-I1 On Min Value reached 7 7 read-only no Error Min Value not reached 0x0 Error Min Value reached 0x1 HB1T12ONMIN Half Bridge 1-T12 On Min Value reached 6 6 read-only no Error Min Value not reached 0x0 Error Min Value reached 0x1 HB1I1ONMAX Half Bridge 1-I1 On Max Value reached 5 5 read-only no Error Max Value not reached 0x0 Error Max Value reached 0x1 HB1T12ONMAX Half Bridge 1-T12 On Max Value reached 4 4 read-only no Error Max Value not reached 0x0 Error Max Value reached 0x1 HB1I1OFFMIN Half Bridge 1-I1 Off Min Value reached 3 3 read-only no Error Min Value not reached 0x0 Error Min Value reached 0x1 HB1T1OFFMIN Half Bridge 1-T1 Off Min Value reached 2 2 read-only no Error Min Value not reached 0x0 Error Min Value reached 0x1 HB1I1OFFMAX Half Bridge 1-I1 Off Max Value reached 1 1 read-only no Error Max Value not reached 0x0 Error Max Value reached 0x1 HB1T1OFFMAX Half Bridge 1-T1 Off Max Value reached 0 0 read-only no Error Max Value not reached 0x0 Error Max Value reached 0x1 CP_CLK_CTRL Charge Pump Clock Control Register 0x24 32 CPCLKDIS_SET Charge Pump Clock Set If Disabled 16 16 read-write LOW Charge Pump Clock is 0 if disabled 0b0 HIGH Charge Pump Clock is 1 if disabled 0b1 CPCLK_EN Charge Pump Clock Enable 15 15 read-write DISABLE Charge Pump Clock is switched off and has value of according to CPCLKDIS_SET 0b0 ENABLE Charge Pump Clock is running 0b1 F_CP MSB of CP_CLK divider 13 14 read-write DITH_UPPER CP_CLK upper frequency boundary during dithering 8 12 read-write DITH_LOWER CP_CLK lower frequency boundary during dithering 0 4 read-write CP_CTRL Charge Pump Control and Status Register 0x20 32 CP_STAGE_SEL Charge Pump Output Voltage Trimming 29 30 read-write 2-stage 2-stage mode enabled 0b00 1-stage1 single stage mode enable (1st stage) 0b01 1-stage2 single stage mode enable (2nd stage) 0b10 auto automatic switch to single stage mode above 18V VSD (2nd stage) and switching back to 2-stage mode below 17V VSD 0b11 VCP14_15V_SEL Charge Pump 15V/14V Output Voltage Sel 28 28 read-write 14V output voltage set to 14V 0b0 15V output voltage set to 15V 0b1 VTHVCP_TRIM Charge Pump Output Voltage Trimming 26 27 read-write 0.0_V default 0b00 0.5_V plus 0.5V nom at 15V 0b01 1.0_V plus 1.0V nom at 15V 0b10 1.5_V plus 1.5V nom at 15V 0b11 VCP9V_SET Charge Pump 9 V Output Voltage Set 25 25 read-write 15_14V Set output voltage set according to VCP14_15V_SEL 0b0 9V Set output voltage set to 9V 0b1 CPLOPWRM_EN Charge Pump Low Power Mode Enable 24 24 read-write Low Power Mode Disable low power mode inactive 0b0 Low Power Mode Enable low power mode active 0b1 DRVx_VSDUP_DIS Driver On VSD Upper Voltage Disable 22 22 read-write Driver Enable DRVx on VSD overvoltage enable. 0b0 Driver Disable DRVx on VSD overvoltage disable. 0b1 DRVx_VSDLO_DIS Driver On VSD Lower Voltage Disable 20 20 read-write Driver Enable DRVx on VSD undervoltage enable. 0b0 Driver Disable DRVx on VSD undervoltage disable. 0b1 DRVx_VCPUP_DIS Driver On Charge Pump Upper Voltage Disable 18 18 read-write Driver Enable DRVx on Charge Pumpe overvoltage enable. 0b0 Driver Disable DRVx on Charge Pump overvoltage disable. 0b1 DRVx_VCPLO_SDEN Driver Charge Pump Low Voltage Shut-Down 17 17 read-write Shut-Down Disable DRVx Shut-Down for Charge Pump undervoltage disable. 0b0 Shut-Down Enable DRVx Shut-Down for Charge Pump undervoltage enable. 0b1 DRVx_VCPLO_DIS Driver On Charge Pump Low Voltage Disable 16 16 read-write Driver Enable DRVx on Charge Pump undervoltage enable. 0b0 Driver Disable DRVx on Charge Pump undervoltage disable. 0b1 VCP_LOWTH2 Charge Pump Output Voltage Lower Threshold Detection Level 8 10 read-write 7.325_V Threshold 0 0b000 7.654_V Threshold 1 0b001 7.982_V Threshold 2 0b010 8.309_V Threshold 3 0b011 8.638_V Threshold 4 0b100 8.966_V Threshold 5 0b101 9.293_V Threshold 6 0b110 9.620_V Threshold 7 0b111 CP_RDY_EN Bridge Driver on Charge Pump Ready Enable 2 2 read-write OFF Bridge Driver can be immediately enabled 0b0 ON Bridge Driver can only be enabled when Charge Pump is ready 0b1 CP_EN Charge Pump Enable 0 0 read-write DISABLE Charge Pump, circuit power off 0b0 ENABLE Charge Pump, circuit power on 0b1 CP_IRQCLR Charge Pump Interrupt Status Clear Register 0x44 32 VSD_UPTH_SC Driver Supply MU High Status Clear 31 31 write-only no Clear 0b0 Clear 0b1 VSD_LOTH_SC Driver Supply MU Low Status Clear 29 29 write-only no Clear 0b0 Clear 0b1 VCP_UPTH_SC Charge Pump MU High Status Clear 27 27 write-only no Clear 0b0 Clear 0b1 VCP_LOTH1_SC Charge Pump MU Low Status Clear 25 25 write-only no Clear 0b0 Clear 0b1 VCP_LOTH2_SC Charge Pump Low Status Clear 24 24 write-only no Clear 0b0 Clear 0b1 VCP_OTSD_SC Charge Pump Over-temperature Shutdown Status Clear 20 20 write-only no Clear 0b0 Clear 0b1 VCP_OTW_SC Charge Pump Over-temperature Warning Status Clear 16 16 write-only no Clear 0b0 Clear 0b1 VSD_UPTH_ISC Driver Supply MU High Interrupt Status Clear 15 15 write-only no Clear 0b0 Clear 0b1 VSD_LOTH_ISC Driver Supply MU Low Interrupt Status Clear 13 13 write-only no Clear 0b0 Clear 0b1 VCP_UPTH_ISC Charge Pump MU High Interrupt Status Clear 11 11 write-only no Clear 0b0 Clear 0b1 VCP_LOTH1_ISC Charge Pump MU Low Interrupt Status Clear 9 9 write-only no Clear 0b0 Clear 0b1 VCP_LOTH2_ISC Charge Pump Low Interrupt Status Clear 8 8 write-only no Clear 0b0 Clear 0b1 VCP_OTSD_ISC Charge Pump Over-temperature Shutdown Interrupt Status Clear 4 4 write-only no Clear 0b0 Clear 0b1 VCP_OTW_ISC Charge Pump Over-temperature Warning Interrupt Status Clear 0 0 write-only no Clear 0b0 Clear 0b1 CP_IRQEN Charge Pump Interrupt Enable Register 0x48 32 VSD_UPTH_IEN Driver Supply MU High Interrupt Enable 15 15 read-write disable 0b0 enable 0b1 VSD_LOTH_IEN Driver Supply MU Low Interrupt Enable 13 13 read-write disable 0b0 enable 0b1 VCP_UPTH_IEN Charge Pump MU High Interrupt Enable 11 11 read-write disable 0b0 enable 0b1 VCP_LOTH1_IEN Charge Pump MU Low Interrupt Enable 9 9 read-write disable 0b0 enable 0b1 VCP_LOTH2_IEN Charge Pump Low Interrupt Enable 8 8 read-write disable 0b0 enable 0b1 VCP_OTSD_IEN Charge Pump Over-temperature Shutdown Interrupt Enable 4 4 read-write disable 0b0 enable 0b1 VCP_OTW_IEN Charge Pump Over-temperature Warning Interrupt Enable 0 0 read-write disable 0b0 enable 0b1 CP_IRQS Charge Pump Status Register 0x40 32 VSD_UPTH_STS Driver Supply MU High Status 31 31 read-write ok Driver Supply Voltage ok, no overvoltage detected 0b0 too_high Driver Supply Voltage too high, overvoltage on VSD Pin detected 0b1 VSD_LOTH_STS Driver Supply MU Low Status 29 29 read-write ok Driver Supply Voltage ok, no undervoltage detected. 0b0 too_low Driver Supply Voltage too low, undervoltage on VSD Pin detected. 0b1 VCP_UPTH_STS Charge Pump MU High Status 27 27 read-write ok Charge Pump Output Voltage ok, no overvoltage detected 0b0 too_high Charge Pump Output Voltage too high, overvoltage on charge pump output detected 0b1 VCP_LOTH1_STS Charge Pump MU Low Status 25 25 read-write ok Charge Pump Output Voltage ok, no undervoltage detected. 0b0 too_low Charge Pump Output Voltage too low, undervoltage on chargepump output detected. 0b1 VCP_LOTH2_STS Charge Pump Low Status 24 24 read-write ok Charge Pump Output Voltage ok, no undervoltage detected. 0b0 too_low Charge Pump Output Voltage too low, undervoltage on chargepump output detected. 0b1 VCP_OTSD_STS Charge Pump Overtemperature Shutdown Status 20 20 read-write ok Charge Pump Overtemperature Shutdown Threshold not reached, no charge pump overtemperature shutdown detected. 0b0 shutdown Charge Pump Overtemperature Shutdown, overtemperature shutdown on charge pump occured. 0b1 VCP_OTW_STS Charge Pump Overtemperature Warning Status 16 16 read-write ok Charge Pump Temperature ok, no charge pump overtemperature warning detected. 0b0 warning harge Pump Overtemperature Warning, overtemperature threshold on charge pump reached. 0b1 VSD_UPTH_IS Driver Supply MU High Interrupt Status 15 15 read-write ok Driver Supply Voltage ok, no overvoltage detected 0b0 too_high Driver Supply Voltage too high, overvoltage on VSD Pin detected 0b1 VSD_LOTH_IS Driver Supply MU Low Interrupt Status 13 13 read-write ok Driver Supply Voltage ok, no undervoltage detected. 0b0 too_low Driver Supply Voltage too low, undervoltage on VSD Pin detected. 0b1 VCP_UPTH_IS Charge Pump MU High Interrupt Status 11 11 read-write ok Charge Pump Output Voltage ok, no overvoltage detected 0b0 too_high Charge Pump Output Voltage too high, overvoltage on charge pump output detected 0b1 VCP_LOTH1_IS Charge Pump MU Low Interrupt Status 9 9 read-write ok Charge Pump Output Voltage ok, no undervoltage detected. 0b0 too_low Charge Pump Output Voltage too low, undervoltage on charge pump output detected. 0b1 VCP_LOTH2_IS Charge Pump Low Interrupt Status 8 8 read-write ok Charge Pump Output Voltage ok, no undervoltage detected. 0b0 too_low Charge Pump Output Voltage too low, undervoltage on chargepump output detected. 0b1 VCP_OTSD_IS Charge Pump Overtemperature Shutdown Interrupt Status 4 4 read-write ok Charge Pump Overtemperature Shutdown Threshold not reached, no charge pump overtemperature shutdown detected. 0b0 shutdown Charge Pump Overtemperature Shutdown, overtemperature shutdown on charge pump occured. 0b1 VCP_OTW_IS Charge Pump Overtemperature Warning Interrupt Status 0 0 read-write ok Charge Pump Temperature ok, no charge pump overtemperature warning detected. 0b0 warning Charge Pump Overtemperature Warning, overtemperature threshold on charge pump reached. 0b1 CTRL1 H-Bridge Driver Control 1 0x00 32 HS2_OC_DIS High Side Driver Overcurrent Shutdown Select 31 31 read-write Global_Shutdown all bridges will be shut down in case of overcurrent 0x0 Local_Shutdown only local driver will be shut down in case of overcurrent 0x1 HS2_SUPERR_STS High Side Driver 2 Supply Error Status 29 29 read-only NORMAL supply is in required range. 0b0 SUPPLY_ERROR detected; this flag is an OR of the VSD_x_STS and VCP_x_STS flags. 0b1 HS2_DCS_EN High Side Driver 2 Diagnosis Current Source Enable 27 27 read-write DISABLE disable current source 0x0 ENABLE enable current source; short diagnosis can be performed by evaluating the LSx/HSx_DS_STS Flag 0x1 HS2_ON High Side Driver 2 On 26 26 read-write OFF Driver off 0b0 ON Driver on 0b1 HS2_PWM High Side Driver 2 PWM Enable 25 25 read-write DISABLE disables control by PWM input 0b0 ENABLE enables control by PWM input 0b1 HS2_EN High Side Driver 2 Enable 24 24 read-write DISABLE Driver circuit power off 0b0 ENABLE Driver circuit power on 0b1 HS1_OC_DIS High Side Driver Overcurrent Shutdown Select 23 23 read-write Global_Shutdown all bridges will be shut down in case of overcurrent 0x0 Local_Shutdown only local driver will be shut down in case of overcurrent 0x1 HS1_SUPERR_STS High Side Driver 1 Supply Error Status 21 21 read-only NORMAL supply is in required range. 0b0 SUPPLY_ERROR detected; this flag is an OR of the VDS_x_STS and VCP_x_STS flags. 0b1 HS1_DCS_EN High Side Driver 1 Diagnosis Current Source Enable 19 19 read-write DISABLE disable current source 0x0 ENABLE enable current source; short diagnosis can be performed by evaluating the LSx/HSx_DS_STS Flag 0x1 HS1_ON High Side Driver 1 On 18 18 read-write OFF Driver off 0b0 ON Driver on 0b1 HS1_PWM High Side Driver 1 PWM Enable 17 17 read-write DISABLE disables control by PWM input 0b0 ENABLE enables control by PWM input 0b1 HS1_EN High Side Driver 1 Enable 16 16 read-write DISABLE Driver circuit power off 0b0 ENABLE Driver circuit power on 0b1 LS2_OC_DIS Low Side Driver Overcurrent Shutdown Select 15 15 read-write Global_Shutdown all bridges will be shut down in case of overcurrent 0x0 Local_Shutdown only local driver will be shut down in case of overcurrent 0x1 LS2_SUPERR_STS Low Side Driver 2 Supply Error Status 13 13 read-only NORMAL supply is in required range. 0b0 SUPPLY_ERROR detected; this flag is an OR of the VDS_x_STS and VCP_x_STS flags. 0b1 LS2_ON Low Side Driver 2 On 10 10 read-write OFF Driver off 0b0 ON Driver on 0b1 LS2_PWM Low Side Driver 2 PWM Enable 9 9 read-write DISABLE disables control by PWM input 0b0 ENABLE enables control by PWM input 0b1 LS2_EN Low Side Driver 2 Enable 8 8 read-write DISABLE Driver circuit power off 0b0 ENABLE Driver circuit power on 0b1 LS1_OC_DIS Low Side Driver 1 Overcurrent Shutdown Select 7 7 read-write Global_Shutdown all bridges will be shut down in case of overcurrent 0x0 Local_Shutdown only local driver will be shut down in case of overcurrent 0x1 LS1_SUPERR_STS Low Side Driver 1 Supply Error Status 5 5 read-only NORMAL supply is in required range. 0b0 SUPPLY_ERROR detected; this flag is an OR of the VDS_x_STS and VCP_x_STS flags. 0b1 LS1_ON Low Side Driver 1 On 2 2 read-write OFF Driver off 0b0 ON Driver on 0b1 LS1_PWM Low Side Driver 1 PWM Enable 1 1 read-write DISABLE disables control by PWM input 0b0 ENABLE enables control by PWM input 0b1 LS1_EN Low Side Driver 1 Enable 0 0 read-write DISABLE Driver circuit power off 0b0 ENABLE Driver circuit power on 0b1 CTRL2 H-Bridge Driver Control 2 0x04 32 DLY_DIAG_DIRSEL Ext. power diag timer on / off select 31 31 read-write TURN OFF measure turn off time 0b0 TURN ON measure turn on time 0b1 DLY_DIAG_CHSEL Ext. power diag timer channel select 28 30 read-write DISABLE diag timer deactivated. 0b000 HB1 LS select measure LS1 on/off delay time. 0b001 HB2 LS select measure LS2 on/off delay time. 0b010 HB1 HS select measure HS1 on/off delay time. 0b101 HB2 HS select measure HS2 on/off delay time. 0b110 DLY_DIAG_STS Ext. power diag timer valid flag 27 27 read-only Diag_timer_invalid diag timer measurement ongoing 0b0 Diag_timer_valid diag timer measurement finished 0b1 DLY_DIAG_SCLR Ext. power diag timer valid flag clear 26 26 write-only Diag timer valid not clear 0b0 Diag timer valid clear 0b1 DLY_DIAG_TIM Ext. power diag timer result register 16 25 read-only HB2OFFSEQCNF Half Bridge 2 Off Sequencer Configuration 3 3 read-write Normal Mode OFF-Sequencer is disabled and driver operates with constant current. 0b0 Sequencer Mode OFF-Sequencer is enabled. 0b1 HB1OFFSEQCNF Half Bridge 1 Off Sequencer Configuration 2 2 read-write Normal Mode OFF-Sequencer is disabled and driver operates with constant current. 0b0 Sequencer Mode OFF-Sequencer is enabled. 0b1 HB2ONSEQCNF Half Bridge 2 On Sequencer Configuration 1 1 read-write Normal Mode ON-Sequencer is disabled and driver operates with constant current. 0b0 Sequencer Mode ON-Sequencer is enabled. 0b1 HB1ONSEQCNF Half Bridge 1 On Sequencer Configuration 0 0 read-write Normal Mode ON-Sequencer is disabled and driver operates with constant current. 0b0 Sequencer Mode ON-Sequencer is enabled. 0b1 CTRL3 H-Bridge Driver Control 3 0x08 32 DRV_CCP_DIS Dynamic cross conduction protection Disable 30 30 read-write CCP Enable dynamic ccp is active. 0b0 CCP Disable dynamic ccp is disabled, delayed gate clamp remains active. 0b1 DRV_CCP_TMUL Multiplier bits for cross conduction time settings in register DRV_CCP_TIMSEL 28 29 read-write MUL1 DRV_CCP_TIMSEL value is multiplied by 1 0b00 MUL2 DRV_CCP_TIMSEL value is multiplied by 2 0b01 MUL4 DRV_CCP_TIMSEL value is multiplied by 4 0b10 MUL8 DRV_CCP_TIMSEL value is multiplied by 8 0b11 DRV_CCP_TIMSEL Minimum cross conduction protection time setting 24 25 read-write 0.2us 200ns cross conduction protection time 0b00 0.4us 400ns cross conduction protection time 0b01 0.8us 800ns cross conduction protection time 0b10 1.6us 1.6us cross conduction protection time 0b11 DSMONVTH Voltage Threshold for Drain-Source Monitoring of external FETs 16 18 read-write 0.125_V Threshold 0 for VDS at 0.125 V 0b000 0.25_V Threshold 1 for VDS at 0.25 V 0b001 0.50_V Threshold 2 for VDS at 0.50 V 0b010 0.75_V Threshold 3 for VDS at 0.75 V 0b011 1.00_V Threshold 4 for VDS at 1.00 V 0b100 1.25_V Threshold 5 for VDS at 1.25 V 0b101 1.50_V Threshold 6 for VDS at 1.50 V 0b110 1.75_V Threshold 7 for VDS at 1.75 V 0b111 DCTRIM_DRVx Current Trimming of Driver 0xE0 32 COMPENS_LS Gain Settings for Low Side Charge Current Compensation 16 18 read-write DISABLE Dynamic Compensation is disabled. 0b000 gain_1 gain setting 1 (min) 0b001 gain_2 gain setting 2 0b010 gain_3 gain setting 3 0b011 gain_4 gain setting 4 (max) 0b100 COMPENS_HS Current Settings for High Side Charge Current Compensation 8 10 read-write DISABLE Dynamic Compensation is disabled. 0b000 gain_1 gain setting 1 (min) 0b001 gain_2 gain setting 2 0b010 gain_3 gain setting 3 0b011 gain_4 gain setting 4 (max) 0b100 HB1ASEQOFFVAL Half Bridge 1 Adaptive Sequencer Off Values 0xBC 32 HB1_OFFVALVF_CLR Half Bridge 1-Turn off slew rate values Valid Flag - Clear. 31 31 write-only NOT CLEAR no clear of HB1_OFFVALVF flag 0b0 CLEAR clear of HB1_OFFVALVF flag 0b1 HB1_OFFVALVF Half Bridge 1-Turn off slew rate values - Valid Flag. 30 30 read-write NOT VALID no new valid LS1/HS1_OFF values available 0b0 VALID LS1/HS1_OFF fields contain valid data and have not been read 0b1 HB1_T2MERR Half Bridge 1-T2 Measurement Error. 22 22 read-only VALID T2 value valid 0b0 ERROR T2 value not valid - Measurement Error 0b1 HB1_T2OFFCNT Half Bridge 1-Turn off slew rate-time value measured from beginning of phase 2 to end of phase 2. 16 21 read-only 50ns 50ns phase duration 0x0 3.2us 3.2us phase duration 0x3F HB1_I1OFFVAL Half Bridge 1-slew rate sequencer off-phase 1 current setting 8 13 read-only min. current ICHGmin 0x0 max. current ICHGmax 0x3F HB1_T1OFFCNT Half Bridge 1-Turn off slew rate-time value measured from beginning of phase 1 to end of phase 1. 0 7 read-only 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF HB1ASEQONVAL Half Bridge 1 Adaptive Sequencer On Values 0xB8 32 HB1_ONVALVF_CLR Half Bridge 1-Turn on slew rate values Valid Flag - Clear. 31 31 write-only NOT CLEAR no clear of HB1_ONVALVF flag 0b0 CLEAR clear of HB1_ONVALVF flag 0b1 HB1_ONVALVF Half Bridge 1-Turn on slew rate values - Valid Flag. 30 30 read-write NOT VALID no new valid LS1/HS1_ON values available 0b0 VALID LS1/HS1_ON fields contain valid data and have not been read 0b1 HB1_T3MERR Half Bridge 1-T3 Measurement Error. 22 22 read-only VALID T3 value valid 0b0 ERROR T3 value not valid - Measurement Error 0b1 HB1_T3ONCNT Half Bridge 1-Turn on slew rate-time value measured from beginning of phase 3 to end of phase 3. 16 21 read-only 50ns 50ns phase duration 0x0 3.2us 3.2us phase duration 0x3F HB1_I1ONVAL Half Bridge 1-slew rate sequencer on-phase 1 current setting 8 13 read-only min. current ICHGmin 0x0 max. current ICHGmax 0x3F HB1_T12ONCNT Half Bridge 1-Turn on slew rate-time value measured from beginning of phase 1 to end of phase 2. 0 7 read-only 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF HB2ASEQOFFVAL Half Bridge 2 Adaptive Sequencer Off Values 0xD4 32 HB2_OFFVALVF_CLR Half Bridge 2-Turn off slew rate values Valid Flag - Clear. 31 31 write-only NOT CLEAR no clear of HB2_OFFVALVF flag 0b0 CLEAR clear of HB2_OFFVALVF flag 0b1 HB2_OFFVALVF Half Bridge 2-Turn off slew rate values - Valid Flag. 30 30 read-write NOT VALID no new valid LS2/HS2_OFF values available 0b0 VALID LS2/HS2_OFF fields contain valid data and have not been read 0b1 HB2_T2MERR Half Bridge 2-T2 Measurement Error. 22 22 read-only VALID T2 value valid 0b0 ERROR T2 value not valid - Measurement Error 0b1 HB2_T2OFFCNT Half Bridge 2-Turn off slew rate-time value measured from beginning of phase 2 to end of phase 2. 16 21 read-only 50ns 50ns phase duration 0x0 3.2us 3.2us phase duration 0x3F HB2_I1OFFVAL Half Bridge 2-slew rate sequencer off-phase 1 current setting 8 13 read-only min. current ICHGmin 0x0 max. current ICHGmax 0x3F HB2_T1OFFCNT Half Bridge 2-Turn off slew rate-time value measured from beginning of phase 1 to end of phase 1. 0 7 read-only 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF HB2ASEQONVAL Half Bridge 2 Adaptive Sequencer On Values 0xD0 32 HB2_ONVALVF_CLR Half Bridge 2-Turn on slew rate values Valid Flag - Clear. 31 31 write-only NOT CLEAR no clear of HB2_ONVALVF flag 0b0 CLEAR clear of HB2_ONVALVF flag 0b1 HB2_ONVALVF Half Bridge 2-Turn on slew rate values - Valid Flag. 30 30 read-write NOT VALID no new valid LS2/HS2_ON values available 0b0 VALID LS2/HS2_ON fields contain valid data and have not been read 0b1 HB2_T3MERR Half Bridge 2-T3 Measurement Error. 22 22 read-only VALID T3 value valid 0b0 ERROR T3 value not valid - Measurement Error 0b1 HB2_T3ONCNT Half Bridge 2-Turn on slew rate-time value measured from beginning of phase 3 to end of phase 3. 16 21 read-only 50ns 50ns phase duration 0x0 3.2us 3.2us phase duration 0x3F HB2_I1ONVAL Half Bridge 2-slew rate sequencer on-phase 1 current setting 8 13 read-only min. current ICHGmin 0x0 max. current ICHGmax 0x3F HB2_T12ONCNT Half Bridge 2-Turn on slew rate-time value measured from beginning of phase 1 to end of phase 2. 0 7 read-only 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF IGATECLMPOFFC Gate Current Clamping Value in OFF State 0x34 32 HB2AF_ICLMPOFF Half Bridge 2-active freewheeling-current clamping value for OFF state 24 29 read-write min. current IDISCHGmin 0x0 max. current IDISCHGmax 0x3F HB1AF_ICLMPOFF Half Bridge 1-active freewheeling-current clamping value for OFF state 16 21 read-write min. current IDISCHGmin 0x0 max. current IDISCHGmax 0x3F HB2_ICLMPOFF Half Bridge 2-current clamping value for OFF state 8 13 read-write min. current IDISCHGmin 0x0 max. current IDISCHGmax 0x3F HB1_ICLMPOFF Half Bridge 1-current clamping value for OFF state 0 5 read-write min. current IDISCHGmin 0x0 max. current IDISCHGmax 0x3F IGATECLMPONC Gate Current Clamping Value in ON State 0x30 32 HB2AF_ICLMPON Half Bridge 2-active freewheeling-current clamping value for ON state 24 29 read-write min. current ICHGmin 0x0 max. current ICHGmax 0x3F HB1AF_ICLMPON Half Bridge 1-active freewheeling-current clamping value for ON state 16 21 read-write min. current ICHGmin 0x0 max. current ICHGmax 0x3F HB2_ICLMPON Half Bridge 2-current clamping value for ON state 8 13 read-write min. current ICHGmin 0x0 max. current ICHGmax 0x3F HB1_ICLMPON Half Bridge 1-current clamping value for ON state 0 5 read-write min. current ICHGmin 0x0 max. current ICHGmax 0x3F IRQCLR H-Bridge Driver Interrupt Status Clear Register 0xF4 32 SEQ_ERR_ISC Driver Sequence Error Status Clear 31 31 write-only no Clear 0b0 Clear 0b1 HS2_OC_ISC External High Side 2 FET Over-current Status Clear 30 30 write-only no Clear 0b0 Clear 0b1 HS2_DS_SC High Side Driver 2 Drain Source Monitoring Status Clear in OFF-State 29 29 write-only no Clear 0b0 Clear 0b1 HS2_DS_ISC High Side Driver 2 Drain Source Monitoring Interrupt Status Clear in OFF-State 28 28 write-only no Clear 0b0 Clear 0b1 HS1_OC_ISC External High Side 1 FET Over-current Status Clear 22 22 write-only no Clear 0b0 Clear 0b1 HS1_DS_SC High Side Driver 1 Drain Source Monitoring Status Clear in OFF-State 21 21 write-only no Clear 0b0 Clear 0b1 HS1_DS_ISC High Side Driver 1 Drain Source Monitoring Interrupt Status Clear in OFF-State 20 20 write-only no Clear 0b0 Clear 0b1 LS2_OC_ISC External Low Side 2 FET Over-current Status Clear 14 14 write-only no Clear 0b0 Clear 0b1 LS2_DS_SC Low Side Driver 2 Drain Source Monitoring Status Clear in OFF-State 13 13 write-only no Clear 0b0 Clear 0b1 LS2_DS_ISC Low Side Driver 2 Drain Source Monitoring Interrupt Status Clear in OFF-State 12 12 write-only no Clear 0b0 Clear 0b1 LS1_OC_ISC External Low Side 1 FET Over-current Status Clear 6 6 write-only no Clear 0b0 Clear 0b1 LS1_DS_SC Low Side Driver 1 Drain Source Monitoring Status Clear in OFF-State 5 5 write-only no Clear 0b0 Clear 0b1 LS1_DS_ISC Low Side Driver 1 Drain Source Monitoring Interrupt Status Clear in OFF-State 4 4 write-only no Clear 0b0 Clear 0b1 HB2_ASEQ_ISC Half Bridge 2 Adaptive Sequencer Interrupt Status Clear 1 1 write-only no Clear 0b0 Clear 0b1 HB1_ASEQ_ISC Half Bridge 1 Adaptive Sequencer Interrupt Status Clear 0 0 write-only no Clear 0b0 Clear 0b1 IRQEN H-Bridge Driver Control 0xF8 32 SEQ_ERR_IEN Driver Sequence Error Interrupt Enable 31 31 read-write disable 0b0 enable 0b1 HS2_OC_IEN External High Side 2 FET Over-current Interrupt Enable 30 30 read-write disable 0b0 enable 0b1 HS2_DS_IEN High Side Driver 2 Drain Source Monitoring Interrupt Enable in OFF-State 28 28 read-write disable 0b0 enable 0b1 HS1_OC_IEN External High Side 1 FET Over-current Interrupt Enable 22 22 read-write disable 0b0 enable 0b1 HS1_DS_IEN High Side Driver 1 Drain Source Monitoring Interrupt Enable in OFF-State 20 20 read-write disable 0b0 enable 0b1 LS2_OC_IEN External Low Side 2 FET Over-current Interrupt Enable 14 14 read-write disable 0b0 enable 0b1 LS2_DS_IEN Low Side Driver 2 Drain Source Monitoring Interrupt Enable in OFF-State 12 12 read-write disable 0b0 enable 0b1 LS1_OC_IEN External Low Side 1 FET Over-current Interrupt Enable 6 6 read-write disable 0b0 enable 0b1 LS1_DS_IEN Low Side Driver 1 Drain Source Monitoring Interrupt Enable in OFF-State 4 4 read-write disable 0b0 enable 0b1 HB2_ASEQ_IEN Half Bridge 2 Adaptive Sequencer Interrupt Enable 1 1 read-write disable 0b0 enable 0b1 HB1_ASEQ_IEN Half Bridge 1 Adaptive Sequencer Interrupt Enable 0 0 read-write disable 0b0 enable 0b1 IRQS H-Bridge Driver Interrupt Status 0xF0 32 SEQ_ERR_IS Driver Sequence Error Interrupt Status 31 31 read-write Driver Sequence ok no cross current 0b0 Driver Sequence fail HS and LS of same bridge concurrently activated, output protection activated 0b1 HS2_OC_IS External High Side 2 FET Over-current Interrupt Status 30 30 read-write no Over-current no over-current Condition occurred. 0b0 Over-current over-current occurred; switch is automatically shut down. 0b1 HS2_DS_STS High Side Driver 2 Drain Source Monitoring Status in OFF-State 29 29 read-write no short on external FET no short detected. 0b0 short on external FET detected short detected. 0b1 HS2_DS_IS High Side Driver 2 Drain Source Monitoring Interrupt Status in OFF-State 28 28 read-write no short on external FET no short detected. 0b0 short on external FET detected short detected. 0b1 HS1_OC_IS External High Side 1 FET Over-current Interrupt Status 22 22 read-write no Over-current no over-current Condition occurred. 0b0 Over-current over-current occurred; switch is automatically shutdown. 0b1 HS1_DS_STS High Side Driver 1 Drain Source Monitoring Status in OFF-State 21 21 read-write no short on external FET no short detected. 0b0 short on external FET detected short detected. 0b1 HS1_DS_IS High Side Driver 1 Drain Source Monitoring Interrupt Status in OFF-State 20 20 read-write no short on external FET no short detected. 0b0 short on external FET detected short detected. 0b1 LS2_OC_IS External Low Side 2 FET Over-current Interrupt Status 14 14 read-write no Over-current no over-current Condition occurred. 0b0 Over-current over-current occurred; switch is automatically shutdown. 0b1 LS2_DS_STS Low Side Driver 2 Drain Source Monitoring Status in OFF-State 13 13 read-write no short on external FET no short detected. 0b0 short on external FET detected short detected. 0b1 LS2_DS_IS Low Side Driver 2 Drain Source Monitoring Interrupt Status in OFF-State 12 12 read-write no short on external FET no short detected. 0b0 short on external FET detected short detected. 0b1 LS1_OC_IS External Low Side 1 FET Over-current Interrupt Status 6 6 read-write no Over-current no over-current Condition occurred. 0b0 Over-current over-current occurred; switch is automatically shutdown. 0b1 LS1_DS_STS Low Side Driver 1 Drain Source Monitoring Status in OFF-State 5 5 read-write no short on external FET no short detected. 0b0 short on external FET detected short detected. 0b1 LS1_DS_IS Low Side Driver 1 Drain Source Monitoring Interrupt Status in OFF-State 4 4 read-write no short on external FET no short detected. 0b0 short on external FET detected short detected. 0b1 HB2_ASEQ_IS Half Bridge 2 Adaptive Sequencer Interrupt Status 1 1 read-write no error in SEQ no sequencer Error detected. 0b0 error in SEQ sequencer Error detected. 0b1 HB1_ASEQ_IS Half Bridge 1 Adaptive Sequencer Interrupt Status 0 0 read-write no error in SEQ no sequencer Error detected. 0b0 error in SEQ sequencer Error detected. 0b1 OFFASEQTMAX Adaptive Slewrate Off Sequencer Maximum Time Setting 0xAC 32 T1OFFMAX Slew rate sequencer off-phase 1 max. time setting 0 7 read-write 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF OFFASEQTMIN Turn OFF Adaptive Slewrate Sequencer Minimum Time Setting 0x9C 32 HB2T1OFFADDDLY HB2 adaptive sequencer T1OFF additional delay setting. 12 15 read-write 0ns 0ns added to HB2T1OFF 0x0 750ns 750ns added to HB2T1OFF 0xF HB1T1OFFADDDLY HB1 adaptive sequencer T1OFF additional delay setting. 8 11 read-write 0ns 0ns added to HB1T1OFF 0x0 750ns 750ns added to HB1T1OFF 0xF T1OFFMIN Slew rate sequencer off-phase 1 min. time setting 0 7 read-write 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF OFFSEQHB1IC Turn-off Slewrate Sequencer Half Bridge 1 Current Control 0x54 32 HB1_I4OFF Half Bridge 1-slew rate sequencer off-phase 4 current setting 24 29 read-write min. current IDISCHGmin 0x0 max. current IDISCHGmax 0x3F HB1_I3OFF Half Bridge 1-slew rate sequencer off-phase 3 current setting 16 21 read-write min. current IDISCHGmin 0x0 max. current IDISCHGmax 0x3F HB1_I2OFF Half Bridge 1-slew rate sequencer-off phase 2 current setting 8 13 read-write min. current IDISCHGmin 0x0 max. current IDISCHGmax 0x3F HB1_I1OFF Half Bridge 1-slew rate sequencer off-phase 1 current setting 0 5 read-write min. current IDISCHGmin 0x0 max. current IDISCHGmax 0x3F OFFSEQHB1TC Turn-off Slewrate Sequencer Half Bridge 1 Time Control 0x50 32 HB1_T4OFF Half Bridge 1-slew rate sequencer off-phase 4 time setting 24 31 read-write 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF HB1_T3OFF Half Bridge 1-slew rate sequencer off-phase 3 time setting 16 21 read-write 50ns 50ns phase duration 0x0 3.2us 3.2us phase duration 0x3F HB1_T2OFF Half Bridge 1-slew rate sequencer off-phase 2 time setting 8 13 read-write 50ns 50ns phase duration 0x0 3.2us 3.2us phase duration 0x3F HB1_T1OFF Half Bridge 1-slew rate sequencer off-phase 1 time setting 0 7 read-write 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF OFFSEQHB2IC Turn-off Slewrate Sequencer Half Bridge 2 Current Control 0x74 32 HB2_I4OFF Half Bridge 2-slew rate sequencer off-phase 4 current setting 24 29 read-write min. current IDISCHGmin 0x0 max. current IDISCHGmax 0x3F HB2_I3OFF Half Bridge 2-slew rate sequencer off-phase 3 current setting 16 21 read-write min. current IDISCHGmin 0x0 max. current IDISCHGmax 0x3F HB2_I2OFF Half Bridge 2-slew rate sequencer off-phase 2 current setting 8 13 read-write min. current IDISCHGmin 0x0 max. current IDISCHGmax 0x3F HB2_I1OFF Half Bridge 2-slew rate sequencer off-phase 1 current setting 0 5 read-write min. current IDISCHGmin 0x0 max. current IDISCHGmax 0x3F OFFSEQHB2TC Turn-off Slewrate Sequencer Half Bridge 2 Time Control 0x70 32 HB2_T4OFF Half Bridge 2-slew rate sequencer off-phase 4 time setting 24 31 read-write 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF HB2_T3OFF Half Bridge 2-slew rate sequencer off-phase 3 time setting 16 21 read-write 50ns 50ns phase duration 0x0 3.2us 3.2us phase duration 0x3F HB2_T2OFF Half Bridge 2-slew rate sequencer off-phase 2 time setting 8 13 read-write 50ns 50ns phase duration 0x0 3.2us 3.2us phase duration 0x3F HB2_T1OFF Half Bridge 2-slew rate sequencer off-phase 1 time setting 0 7 read-write 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF ONASEQTMAX Adaptive Slewrate On Sequencer Maximum Time Setting 0xA8 32 T12ONMAX Slew rate sequencer on-phase 12 max. time setting 0 7 read-write 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF ONASEQTMIN Turn ON Adaptive Slewrate Sequencer Minimum Time Setting 0x98 32 T12ONMIN Slew rate sequencer on-phase 12 min. time setting 0 7 read-write 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF ONSEQHB1IC Turn-on Slewrate Sequencer Half Bridge 1 Current Control 0x5C 32 HB1_I4ON Half Bridge 1-slew rate sequencer on-phase 4 current setting 24 29 read-write min. current ICHGmin 0x0 max. current ICHGmax 0x3F HB1_I3ON Half Bridge 1-slew rate sequencer on-phase 3 current setting 16 21 read-write min. current ICHGmin 0x0 max. current ICHGmax 0x3F HB1_I2ON Half Bridge 1-slew rate sequencer on-phase 2 current setting 8 13 read-write min. current ICHGmin 0x0 max. current ICHGmax 0x3F HB1_I1ON Half Bridge 1-slew rate sequencer on-phase 1 current setting 0 5 read-write min. current ICHGmin 0x0 max. current ICHGmax 0x3F ONSEQHB1TC Turn-on Slewrate Sequencer Half Bridge 1 Time Control 0x58 32 HB1_T4ON Half Bridge 1-slew rate sequencer on-phase 4 time setting 24 31 read-write 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF HB1_T3ON Half Bridge 1-slew rate sequencer on-phase 3 time setting 16 21 read-write 50ns 50ns phase duration 0x0 3.2us 3.2us phase duration 0x3F HB1_T2ON Half Bridge 1-slew rate sequencer on-phase 2 time setting 8 13 read-write 50ns 50ns phase duration 0x0 3.2us 3.2us phase duration 0x3F HB1_T1ON Half Bridge 1-slew rate sequencer on-phase 1 time setting 0 7 read-write 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF ONSEQHB2IC Turn-on Slewrate Sequencer Half Bridge 2 Current Control 0x7C 32 HB2_I4ON Half Bridge 2-slew rate sequencer on-phase 4 current setting 24 29 read-write min. current ICHGmin 0x0 max. current ICHGmax 0x3F HB2_I3ON Half Bridge 2-slew rate sequencer on-phase 3 current setting 16 21 read-write min. current ICHGmin 0x0 max. current ICHGmax 0x3F HB2_I2ON Half Bridge 2-slew rate sequencer on-phase 2 current setting 8 13 read-write min. current ICHGmin 0x0 max. current ICHGmax 0x3F HB2_I1ON Half Bridge 2-slew rate sequencer on-phase 1 current setting 0 5 read-write min. current ICHGmin 0x0 max. current ICHGmax 0x3F ONSEQHB2TC Turn-on Slewrate Sequencer Half Bridge 2 Time Control 0x78 32 HB2_T4ON Half Bridge 2-slew rate sequencer on-phase 4 time setting 24 31 read-write 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF HB2_T3ON Half Bridge 2-slew rate sequencer on-phase 3 time setting 16 21 read-write 50ns 50ns phase duration 0x0 3.2us 3.2us phase duration 0x3F HB2_T2ON Half Bridge 2-slew rate sequencer on-phase 2 time setting 8 13 read-write 50ns 50ns phase duration 0x0 3.2us 3.2us phase duration 0x3F HB2_T1ON Half Bridge 2-slew rate sequencer on-phase 1 time setting 0 7 read-write 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF PWMSRCSEL PWM Source Selection Register 0x0C 32 HS2_SRC_SEL HS2 PWM Source Selection 19 20 read-write CC60 PWM output of CCU6 0b00 CC61 PWM output of CCU6 0b01 COUT60 PWM output of CCU6 0b10 COUT61 PWM output of CCU6 0b11 HS1_SRC_SEL HS1 PWM Source Selection 16 17 read-write CC60 PWM output of CCU6 0b00 CC61 PWM output of CCU6 0b01 COUT60 PWM output of CCU6 0b10 COUT61 PWM output of CCU6 0b11 LS2_SRC_SEL LS2 PWM Source Selection 3 4 read-write CC60 PWM output of CCU6 0b00 CC61 PWM output of CCU6 0b01 COUT60 PWM output of CCU6 0b10 COUT61 PWM output of CCU6 0b11 LS1_SRC_SEL LS1 PWM Source Selection 0 1 read-write CC60 PWM output of CCU6 0b00 CC61 PWM output of CCU6 0b01 COUT60 PWM output of CCU6 0b10 COUT61 PWM output of CCU6 0b11 SEQAFHB1CD Slewrate Sequencer-Active Freewheeling- Half Bridge 1 Clamping Current Delay 0x68 32 HB1AF_TDICLMPON Clamping current delay during active freewheeling for switch on 8 15 read-write 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF HB1AF_TDICLMPOFF Clamping current delay during active freewheeling for switch off 0 7 read-write 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF SEQAFHB1IC Slewrate Sequencer-Active Freewheeling-Half Bridge 1 Current Control 0x64 32 HB1AF_ION Half Bridge 1-active freewheeling-slew rate sequencer on-phase current setting 16 21 read-write min. current IDISCHGmin 0x0 max. current IDISCHGmax 0x3F HB1AF_IOFF Half Bridge 1-active freewheeling-slew rate sequencer off-phase current setting 0 5 read-write min. current IDISCHGmin 0x0 max. current IDISCHGmax 0x3F SEQAFHB2CD Slewrate Sequencer-Active Freewheeling- Half Bridge 2 Clamping Current Delay 0x88 32 HB2AF_TDICLMPON Clamping current delay during active freewheeling for switch on 8 15 read-write 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF HB2AF_TDICLMPOFF Clamping current delay during active freewheeling for switch off 0 7 read-write 50ns 50ns phase duration 0x0 12.8us 12.8us phase duration 0xFF SEQAFHB2IC Slewrate Sequencer-Active Freewheeling- Half Bridge 2 Current Control 0x84 32 HB2AF_ION Half Bridge 2-active freewheeling-slew rate sequencer on-phase current setting 16 21 read-write min. current IDISCHGmin 0x0 max. current IDISCHGmax 0x3F HB2AF_IOFF Half Bridge 2-active freewheeling-slew rate sequencer off-phase current setting 0 5 read-write min. current IDISCHGmin 0x0 max. current IDISCHGmax 0x3F SEQMAP Slewrate Sequencer Mapping Register 0x10 32 HB2_SEQMAP Half Bridge 2 Sequencer Mapping 2 2 read-write LS2 slew rate sequencer is mapped to LS2 0x0 HS2 slew rate sequencer is mapped to HS2 0x1 HB1_SEQMAP Half Bridge 1 Sequencer Mapping 0 0 read-write LS1 slew rate sequencer is mapped to LS1 0x0 HS1 slew rate sequencer is mapped to HS1 0x1 TRIM_DRVx Trimming of Driver 0x18 32 CPLOW_TFILT_SEL Filter Time for Charge Pump Voltage Low Diagnosis 28 29 read-write 4_us 4 us filter time 0b00 8_us 8 us filter time 0b01 16_us 16 us filter time 0b10 32_us 32 us filter time 0b11 HS2DRV_OCSDN_DIS High Side 2 Predriver in overcurrent situation disable 25 25 read-write Enable Predriver shutdown in overcurrent situation enable 0b0 Disable Predriver shutdown in overcurrent situation disable 0b1 HS1DRV_OCSDN_DIS High Side 1 Predriver in overcurrent situation disable 24 24 read-write Enable Predriver shutdown in overcurrent situation enable 0b0 Disable Predriver shutdown in overcurrent situation disable 0b1 HS2DRV_FDISCHG_DIS High Side 2 Predriver fast discharge disable 21 21 read-write Enable Predriver shutdown fast discharge enable 0b0 Disable Predriver shutdown fast discharge disable 0b1 HS1DRV_FDISCHG_DIS High Side 1 Predriver fast discharge disable 20 20 read-write Enable Predriver shutdown fast discharge enable 0b0 Disable Predriver shutdown fast discharge disable 0b1 HSDRV_DS_TFILT_SEL Filter Time for Drain-Source Monitoring of High Side Drivers 18 19 read-write 1_us 1 us filter time 0b00 2_us 2 us filter time 0b01 4_us 4 us filter time 0b10 8_us 8 us filter time 0b11 LS2DRV_OCSDN_DIS Low Side 2 Predriver in overcurrent situation disable 15 15 read-write Enable Predriver shutdown in overcurrent situation enable 0b0 Disable Predriver shutdown in overcurrent situation disable 0b1 LS1DRV_OCSDN_DIS Low Side 1 Predriver in overcurrent situation disable 14 14 read-write Enable Predriver shutdown in overcurrent situation enable 0b0 Disable Predriver shutdown in overcurrent situation disable 0b1 LS2DRV_FDISCHG_DIS Low Side 2 Predriver fast discharge disable 11 11 read-write Enable Predriver shutdown fast discharge enable 0b0 Disable Predriver shutdown fast discharge disable 0b1 LS1DRV_FDISCHG_DIS Low Side 1 Predriver fast discharge disable 10 10 read-write Enable Predriver shutdown fast discharge enable 0b0 Disable Predriver shutdown fast discharge disable 0b1 LSDRV_DS_TFILT_SEL Filter Time for Drain-Source Monitoring of Low Side Drivers 8 9 read-write 1_us 1 us filter time 0b00 2_us 2 us filter time 0b01 4_us 4 us filter time 0b10 8_us 8 us filter time 0b11 LS_HS_BT_TFILT_SEL Blanking Time for Drain-Source Monitoring of Low / High Side Drivers 0 1 read-write 1_us 1 us filter time 0b00 2_us 2 us filter time 0b01 4_us 4 us filter time 0b10 8_us 8 us filter time 0b11 CCU6 CCU6 0x4000C000 0x0 0x4000 registers INTISR4 Interrupt node 4: CCU6 node0 4 INTISR5 Interrupt node 5: CCU6 node1 5 INTISR6 Interrupt node 6: CCU6 node2 6 INTISR7 Interrupt node 7: CCU6 node3 7 CC60R Capture/Compare Register for Channel CC60 0x34 32 CCV Channel 0 Capture/Compare Value 0 15 read-only CC60SR Capture/Compare Shadow Register for Channel CC60 0x14 32 CCS Shadow Register for Channel 0 Capture/Compare Value 0 15 read-write CC61R Capture/Compare Register for Channel CC61 0x38 32 CCV Channel 1 Capture/Compare Value 0 15 read-only CC61SR Capture/Compare Shadow Register for Channel CC61 0x18 32 CCS Shadow Register for Channel 1 Capture/Compare Value 0 15 read-write CC62R Capture/Compare Register for Channel CC62 0x3C 32 CCV Channel 2 Capture/Compare Value 0 15 read-only CC62SR Capture/Compare Shadow Register for Channel CC62 0x1C 32 CCS Shadow Register for Channel 2 Capture/Compare Value 0 15 read-write CC63R Capture/Compare Register for Channel CC63 0x00 32 CCV Channel CC63 Compare Value Low Byte 0 15 read-only CC63SR Capture/Compare Shadow Register for Channel CC63 0x20 32 CCS Shadow Register for Channel CC63 Compare Value 0 15 read-write CMPMODIF Compare State Modification Register 0x10 32 MCC63R Capture/Compare Status Modification Bits (Reset) 14 14 write-only Not_changed Bit CC63ST is not changed. 0b00 Set Bit CC63ST is set. 0b01 Reset Bit CC63ST is reset. 0b10 MCC62R Capture/Compare Status Modification Bit 2(Reset) 10 10 write-only Not_changed Bit CC62ST is not changed. 0b00 Set Bit CC62ST is set. 0b01 Reset Bit CC62ST is reset. 0b10 MCC61R Capture/Compare Status Modification Bit 1(Reset) 9 9 write-only Not_changed Bit CC61ST is not changed. 0b00 Set Bit CC61ST is set. 0b01 Reset Bit CC61ST is reset. 0b10 MCC60R Capture/Compare Status Modification Bit 0(Reset) 8 8 write-only Not_changed Bit CC60ST is not changed. 0b00 Set Bit CC60ST is set. 0b01 Reset Bit CC60ST is reset. 0b10 MCC63S Capture/Compare Status Modification Bits (Set) 6 6 write-only Not_changed Bit CC63ST is not changed. 0b00 Set Bit CC63ST is set. 0b01 Reset Bit CC63ST is reset. 0b10 MCC62S Capture/Compare Status Modification Bit 2 (Set) 2 2 write-only Not_changed Bit CC62ST is not changed. 0b00 Set Bit CC62ST is set. 0b01 Reset Bit CC62ST is reset. 0b10 MCC61S Capture/Compare Status Modification Bit 1 (Set) 1 1 write-only Not_changed Bit CC61ST is not changed. 0b00 Set Bit CC61ST is set. 0b01 Reset Bit CC61ST is reset. 0b10 MCC60S Capture/Compare Status Modification Bit 0 (Set) 0 0 write-only Not_changed Bit CC60ST is not changed. 0b00 Set Bit CC60ST is set. 0b01 Reset Bit CC60ST is reset. 0b10 CMPSTAT Compare State Register 0x80 32 T13IM T13 Inverted Modulation 15 15 read-write Not inverted T13 output is not inverted. 0b0 Inverted T13 output is inverted for further modulation. 0b1 COUT63PS Passive State Select for Compare Outputs 14 14 read-write Zero The corresponding compare output drives passive level while CC6xST is 0. 0b0 One The corresponding compare output drives passive level while CC6xST is 1. 0b1 COUT62PS Passive State Select for Compare Outputs 13 13 read-write Zero The corresponding compare output drives passive level while CC6xST is 0. 0b0 One The corresponding compare output drives passive level while CC6xST is 1. 0b1 CC62PS Passive State Select for Compare Outputs 12 12 read-write Zero The corresponding compare output drives passive level while CC6xST is 0. 0b0 One The corresponding compare output drives passive level while CC6xST is 1. 0b1 COUT61PS Passive State Select for Compare Outputs 11 11 read-write Zero The corresponding compare output drives passive level while CC6xST is 0. 0b0 One The corresponding compare output drives passive level while CC6xST is 1. 0b1 CC61PS Passive State Select for Compare Outputs 10 10 read-write Zero The corresponding compare output drives passive level while CC6xST is 0. 0b0 One The corresponding compare output drives passive level while CC6xST is 1. 0b1 COUT60PS Passive State Select for Compare Outputs 9 9 read-write Zero The corresponding compare output drives passive level while CC6xST is 0. 0b0 One The corresponding compare output drives passive level while CC6xST is 1. 0b1 CC60PS Passive State Select for Compare Outputs 8 8 read-write Zero The corresponding compare output drives passive level while CC6xST is 0. 0b0 One The corresponding compare output drives passive level while CC6xST is 1. 0b1 CC63ST Capture/Compare State Bits 6 6 read-only Less In compare mode, the timer count is less than the compare value. In capture mode, the selected edge has not yet been detected since the bit has been reset by software the last time. 0b0 Greater In compare mode, the counter value is greater than or equal to the compare value. In capture mode, the selected edge has been detected. 0b1 CCPOS2 Sampled Hall Pattern Bit 2 5 5 read-only Zero The input CCPOS2 has been sampled as 0. 0b0 One The input CCPOS2 has been sampled as 1. 0b1 CCPOS1 Sampled Hall Pattern Bit 1 4 4 read-only Zero The input CCPOS1 has been sampled as 0. 0b0 One The input CCPOS1 has been sampled as 1. 0b1 CCPOS0 Sampled Hall Pattern Bit 0 3 3 read-only Zero The input CCPOS0 has been sampled as 0. 0b0 One The input CCPOS0 has been sampled as 1. 0b1 CC62ST Capture/Compare State Bits 2 2 read-only Less In compare mode, the timer count is less than the compare value. In capture mode, the selected edge has not yet been detected since the bit has been reset by software the last time. 0b0 Greater In compare mode, the counter value is greater than or equal to the compare value. In capture mode, the selected edge has been detected. 0b1 CC61ST Capture/Compare State Bits 1 1 read-only Less In compare mode, the timer count is less than the compare value. In capture mode, the selected edge has not yet been detected since the bit has been reset by software the last time. 0b0 Greater In compare mode, the counter value is greater than or equal to the compare value. In capture mode, the selected edge has been detected. 0b1 CC60ST Capture/Compare State Bits 0 0 read-only Less In compare mode, the timer count is less than the compare value. In capture mode, the selected edge has not yet been detected since the bit has been reset by software the last time. 0b0 Greater In compare mode, the counter value is greater than or equal to the compare value. In capture mode, the selected edge has been detected. 0b1 IEN Capture/Compare Interrupt Enable Register 0x44 32 ENSTR Enable Multi-Channel Mode Shadow Transfer Interrupt 15 15 read-write No interrupt No interrupt will be generated if the set condition for bit STR in register IS occurs. 0b0 Interrupt An interrupt will be generated if the set condition for bit STR in register IS occurs. The interrupt line that will be activated is selected by bit field INPCHE. 0b1 ENIDLE Enable Idle 14 14 read-write IDLE not set The bit IDLE is not automatically set when a wrong hall event is detected. 0b0 IDLE set The bit IDLE is automatically set when a wrong hall event is detected. 0b1 ENWHE Enable Interrupt for Wrong Hall Event 13 13 read-write No interrupt No interrupt will be generated if the set condition for bit WHE in register IS occurs. 0b0 Interrupt An interrupt will be generated if the set condition for bit WHE in register IS occurs. The interrupt line that will be activated is selected by bit field INPERR. 0b1 ENCHE Enable Interrupt for Correct Hall Event 12 12 read-write No interrupt No interrupt will be generated if the set condition for bit CHE in register IS occurs. 0b0 Interrupt An interrupt will be generated if the set condition for bit CHE in register IS occurs. The interrupt line that will be activated is selected by bit field INPCHE. 0b1 ENTRPF Enable Interrupt for Trap Flag 10 10 read-write No interrupt No interrupt will be generated if the set condition for bit TRPF in register IS occurs. 0b0 Interrupt An interrupt will be generated if the set condition for bit TRPF in register IS occurs. The interrupt line that will be activated is selected by bit field INPERR. 0b1 ENT13PM Enable Interrupt for T13 Period-Match 9 9 read-write No interrupt No interrupt will be generated if the set condition for bit T13PM in register IS occurs. 0b0 Interrupt An interrupt will be generated if the set condition for bit T13PM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT13. 0b1 ENT13CM Enable Interrupt for T13 Compare-Match 8 8 read-write No interrupt No interrupt will be generated if the set condition for bit T13CM in register IS occurs. 0b0 Interrupt An interrupt will be generated if the set condition for bit T13CM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT13. 0b1 ENT12PM Enable Interrupt for T12 Period-Match 7 7 read-write No interrupt No interrupt will be generated if the set condition for bit T12PM in register IS occurs. 0b0 Interrupt An interrupt will be generated if the set condition for bit T12PM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT12. 0b1 ENT12OM Enable Interrupt for T12 One-Match 6 6 read-write No interrupt No interrupt will be generated if the set condition for bit T12OM in register IS occurs. 0b0 Interrupt An interrupt will be generated if the set condition for bit T12OM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT12. 0b1 ENCC62F Capture, Compare-Match Falling Edge Interrupt Enable for Channel 2 5 5 read-write No interrupt No interrupt will be generated if the set condition for bit CC62F in register IS occurs. 0b0 Interrupt An interrupt will be generated if the set condition for bit CC62F in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC62. 0b1 ENCC62R Capture, Compare-Match Rising Edge Interrupt Enable for Channel 2 4 4 read-write No interrupt No interrupt will be generated if the set condition for bit CC62R in register IS occurs. 0b0 Interrupt An interrupt will be generated if the set condition for bit CC62R in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC62. 0b1 ENCC61F Capture, Compare-Match Falling Edge Interrupt Enable for Channel 1 3 3 read-write No interrupt No interrupt will be generated if the set condition for bit CC61F in register IS occurs. 0b0 Interrupt An interrupt will be generated if the set condition for bit CC61F in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC61. 0b1 ENCC61R Capture, Compare-Match Rising Edge Interrupt Enable for Channel 1 2 2 read-write No interrupt No interrupt will be generated if the set condition for bit CC61R in register IS occurs. 0b0 Interrupt An interrupt will be generated if the set condition for bit CC61R in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC61. 0b1 ENCC60F Capture, Compare-Match Falling Edge Interrupt Enable for Channel 0 1 1 read-write No interrupt No interrupt will be generated if the set condition for bit CC60F in register IS occurs. 0b0 Interrupt An interrupt will be generated if the set condition for bit CC60F in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC60. 0b1 ENCC60R Capture, Compare-Match Rising Edge Interrupt Enable for Channel 0 0 0 read-write No interrupt No interrupt will be generated if the set condition for bit CC60R in register IS occurs. 0b0 Interrupt An interrupt will be generated if the set condition for bit CC60R in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC60. 0b1 INP Capture/Compare Interrupt Node Pointer Register 0x48 32 INPT13 Interrupt Node Pointer for Timer T13 Interrupts 12 13 read-write SR0 Interrupt output line SR0 is selected. 0b00 SR1 Interrupt output line SR1 is selected. 0b01 SR2 Interrupt output line SR2 is selected. 0b10 SR3 Interrupt output line SR3 is selected. 0b11 INPT12 Interrupt Node Pointer for Timer T12 Interrupts 10 11 read-write SR0 Interrupt output line SR0 is selected. 0b00 SR1 Interrupt output line SR1 is selected. 0b01 SR2 Interrupt output line SR2 is selected. 0b10 SR3 Interrupt output line SR3 is selected. 0b11 INPERR Interrupt Node Pointer for Error Interrupts 8 9 read-write SR0 Interrupt output line SR0 is selected. 0b00 SR1 Interrupt output line SR1 is selected. 0b01 SR2 Interrupt output line SR2 is selected. 0b10 SR3 Interrupt output line SR3 is selected. 0b11 INPCHE Interrupt Node Pointer for the CHE Interrupt 6 7 read-write SR0 Interrupt output line SR0 is selected. 0b00 SR1 Interrupt output line SR1 is selected. 0b01 SR2 Interrupt output line SR2 is selected. 0b10 SR3 Interrupt output line SR3 is selected. 0b11 INPCC62 Interrupt Node Pointer for Channel 2 Interrupts 4 5 read-write SR0 Interrupt output line SR0 is selected. 0b00 SR1 Interrupt output line SR1 is selected. 0b01 SR2 Interrupt output line SR2 is selected. 0b10 SR3 Interrupt output line SR3 is selected. 0b11 INPCC61 Interrupt Node Pointer for Channel 1 Interrupts 2 3 read-write SR0 Interrupt output line SR0 is selected. 0b00 SR1 Interrupt output line SR1 is selected. 0b01 SR2 Interrupt output line SR2 is selected. 0b10 SR3 Interrupt output line SR3 is selected. 0b11 INPCC60 Interrupt Node Pointer for Channel 0 Interrupts 0 1 read-write SR0 Interrupt output line SR0 is selected. 0b00 SR1 Interrupt output line SR1 is selected. 0b01 SR2 Interrupt output line SR2 is selected. 0b10 SR3 Interrupt output line SR3 is selected. 0b11 IS Capture/Compare Interrupt Status Register 0x68 32 STR Multi-Channel Mode Shadow Transfer Request 15 15 read-only No The shadow transfer has not yet taken place. 0b0 Yes The shadow transfer has taken place. 0b1 IDLE IDLE State 14 14 read-only No action 0b0 Idle Bit field MCMP is cleared and held to 0, the selected outputs are set to passive state. 0b1 WHE Wrong Hall Event 13 13 read-only Not detected A transition to a wrong hall event (not the expected one) has not yet been detected since this bit has been reset for the last time. 0b0 Detected A transition to a wrong hall event (not the expected one) has been detected. 0b1 CHE Correct Hall Event 12 12 read-only Not detected A transition to a correct (= expected) hall event has not yet been detected since this bit has been reset for the last time. 0b0 Detected A transition to a correct (= expected) hall event has been detected. 0b1 TRPS Trap State 11 11 read-only Not active The trap state is not active. 0b0 Active The trap state is active. Bit TRPS is set while bit TRPF = 1. It is reset according to the mode selected in register TRPCTR. 0b1 TRPF Trap Flag 10 10 read-only Not detected The trap condition has not been detected. 0b0 Detected The trap condition has been detected (input CTRAP has been 0 or by software). 0b1 T13PM Timer T13 Period-Match Flag 9 9 read-only Not detected A timer T13 period-match has not yet been detected since this bit has been reset for the last time. 0b0 Detected A timer T13 period-match has been detected. 0b1 T13CM Timer T13 Compare-Match Flag 8 8 read-only Not detected A timer T13 compare-match has not yet been detected since this bit has been reset for the last time. 0b0 Detected A timer T13 compare-match has been detected. 0b1 T12PM Timer T12 Period-Match Flag 7 7 read-only Not detected A timer T12 period-match (while counting up) has not yet been detected since this bit has been reset for the last time. 0b0 Detected A timer T12 period-match (while counting up) has been detected. 0b1 T12OM Timer T12 One-Match Flag 6 6 read-only Not detected A timer T12 one-match (while counting down) has not yet been detected since this bit has been reset for the last time. 0b0 Detected A timer T12 one-match (while counting down) has been detected. 0b1 ICC62F Capture, Compare-Match Falling Edge Flag 5 5 read-only Not occurred The event has not yet occurred since this bit has been reset for the last time. 0b0 Detected The event described above has been detected. 0b1 ICC62R Capture, Compare-Match Rising Edge Flag 4 4 read-only Not occurred The event has not yet occurred since this bit has been reset for the last time. 0b0 Detected The event described above has been detected. 0b1 ICC61F Capture, Compare-Match Falling Edge Flag 3 3 read-only Not occurred The event has not yet occurred since this bit has been reset for the last time. 0b0 Detected The event described above has been detected. 0b1 ICC61R Capture, Compare-Match Rising Edge Flag 2 2 read-only Not occurred The event has not yet occurred since this bit has been reset for the last time. 0b0 Detected The event described above has been detected. 0b1 ICC60F Capture, Compare-Match Falling Edge Flag 1 1 read-only Not occurred The event has not yet occurred since this bit has been reset for the last time. 0b0 Detected The event described above has been detected. 0b1 ICC60R Capture, Compare-Match Rising Edge Flag 0 0 read-only Not occurred The event has not yet occurred since this bit has been reset for the last time. 0b0 Detected The event described above has been detected. 0b1 ISR Capture/Compare Interrupt Status Reset Register 0x0C 32 RSTR Reset STR Flag 15 15 write-only No action 0b0 Reset Bit STR in register IS will be reset. 0b1 RIDLE Reset IDLE Flag 14 14 write-only No action 0b0 Reset Bit IDLE in register IS will be reset. 0b1 RWHE Reset Wrong Hall Event Flag 13 13 write-only No action 0b0 Reset Bit WHE in register IS will be reset. 0b1 RCHE Reset Correct Hall Event Flag 12 12 write-only No action 0b0 Reset Bit CHE in register IS will be reset. 0b1 RTRPF Reset Trap Flag 10 10 write-only No action 0b0 Reset Bit TRPF in register IS will be reset (not taken into account while input CTRAP = 0 and TRPPEN = 1. 0b1 RT13PM Reset Timer T13 Period-Match Flag 9 9 write-only No action 0b0 Reset Bit T13PM in register IS will be reset. 0b1 RT13CM Reset Timer T13 Compare-Match Flag 8 8 write-only No action 0b0 Reset Bit T13CM in register IS will be reset. 0b1 RT12PM Reset Timer T12 Period-Match Flag 7 7 write-only No action 0b0 Reset Bit T12PM in register IS will be reset. 0b1 RT12OM Reset Timer T12 One-Match Flag 6 6 write-only No action 0b0 Reset Bit T12OM in register IS will be reset. 0b1 RCC62F Reset Capture, Compare-Match Falling Edge Flag 5 5 write-only No action 0b0 Reset Bit CC62F in register IS will be reset. 0b1 RCC62R Reset Capture, Compare-Match Rising Edge Flag 4 4 write-only No action 0b0 Reset Bit CC62R in register IS will be reset. 0b1 RCC61F Reset Capture, Compare-Match Falling Edge Flag 3 3 write-only No action 0b0 Reset Bit CC61F in register IS will be reset. 0b1 RCC61R Reset Capture, Compare-Match Rising Edge Flag 2 2 write-only No action 0b0 Reset Bit CC61R in register IS will be reset. 0b1 RCC60F Reset Capture, Compare-Match Falling Edge Flag 1 1 write-only No action 0b0 Reset Bit CC60F in register IS will be reset. 0b1 RCC60R Reset Capture, Compare-Match Rising Edge Flag 0 0 write-only No action 0b0 Reset Bit CC60R in register IS will be reset. 0b1 ISS Capture/Compare Interrupt Status Set Register 0x4C 32 SSTR Set STR Flag 15 15 write-only No action 0b0 Set Bit STR in register IS will be set. 0b1 SIDLE Set IDLE Flag 14 14 write-only No action 0b0 Set Bit IDLE in register IS will be set. 0b1 SWHE Set Wrong Hall Event Flag 13 13 write-only No action 0b0 Set Bit WHE in register IS will be set. 0b1 SCHE Set Correct Hall Event Flag 12 12 write-only No action 0b0 Set Bit CHE in register IS will be set. 0b1 SWHC Software Hall Compare 11 11 write-only No action 0b0 Set The Hall compare action is triggered. 0b1 STRPF Set Trap Flag 10 10 write-only No action 0b0 Set Bits TRPF and TRPS in register IS will be set. 0b1 ST13PM Set Timer T13 Period-Match Flag 9 9 write-only No action 0b0 Set Bit T13PM in register IS will be set. 0b1 ST13CM Set Timer T13 Compare-Match Flag 8 8 write-only No action 0b0 Set Bit T13CM in register IS will be set. 0b1 ST12PM Set Timer T12 Period-Match Flag 7 7 write-only No action 0b0 Set Bit T12PM in register IS will be set. 0b1 ST12OM Set Timer T12 One-Match Flag 6 6 write-only No action 0b0 Set Bit T12OM in register IS will be set. 0b1 SCC62F Set Capture, Compare-Match Falling Edge Flag 5 5 write-only No action 0b0 Set Bit CC62F in register IS will be set. 0b1 SCC62R Set Capture, Compare-Match Rising Edge Flag 4 4 write-only No action 0b0 Set Bit CC62R in register IS will be set. 0b1 SCC61F Set Capture, Compare-Match Falling Edge Flag 3 3 write-only No action 0b0 Set Bit CC61F in register IS will be set. 0b1 SCC61R Set Capture, Compare-Match Rising Edge Flag 2 2 write-only No action 0b0 Set Bit CC61R in register IS will be set. 0b1 SCC60F Set Capture, Compare-Match Falling Edge Flag 1 1 write-only No action 0b0 Set Bit CC60F in register IS will be set. 0b1 SCC60R Set Capture, Compare-Match Rising Edge Flag 0 0 write-only No action 0b0 Set Bit CC60R in register IS will be set. 0b1 MCMCTR Multi-Channel Mode Control Register 0x54 32 STE13U Shadow Transfer Enable for T13 Upcounting 10 10 read-write No action 0b0 Enabled The T13_ST shadow transfer mechanism is enabled if MCMEN = 1. 0b1 STE12D Shadow Transfer Enable for T12 Downcounting 9 9 read-write No action 0b0 Enabled The T12_ST shadow transfer mechanism is enabled if MCMEN = 1. 0b1 STE12U Shadow Transfer Enable for T12 Upcounting 8 8 read-write No action 0b0 Enabled The T12_ST shadow transfer mechanism is enabled if MCMEN = 1. 0b1 SWSYN Switching Synchronization 4 5 read-write Direct the trigger event directly causes the shadow transfer 0b00 T13 zero-match T13 zero-match triggers the shadow transfer 0b01 T12 zero-match a T12 zero-match (while counting up) triggers the shadow transfer 0b10 SWSEL Switching Selection 0 2 read-write No request no trigger request will be generated 0b000 Correct pattern correct hall pattern on CCPOSx detected 0b001 T13 period-match T13 period-match detected (while counting up) 0b010 T12 one-match T12 one-match (while counting down) 0b011 T12 channel1 compare-match T12 channel 1 compare-match detected (phase delay function) 0b100 T12 period-match T12 period match detected (while counting up) else reserved, no trigger request will be generated 0b101 MCMOUT Multi-Channel Mode Output Register 0x64 32 CURH Current Hall Pattern 11 13 read-only EXPH Expected Hall Pattern 8 10 read-only R Reminder Flag 6 6 read-only No shadow transfer Currently, no shadow transfer from MCMPS to MCMP is requested. 0b0 Shadow transfer A shadow transfer from MCMPS to MCMP has been requested by the selected trigger source, but it has not yet been executed, because the selected synchronization condition has not yet occurred. 0b1 MCMP Multi-Channel PWM Pattern 0 5 read-only Passive The output is set to the passive state. The PWM generated by T12 or T13 is not taken into account. 0b0 PWM The output can deliver the PWM generated by T12 or T13 (according to register MODCTR). 0b1 MCMOUTS Multi-Channel Mode Output Shadow Register 0x08 32 STRHP Shadow Transfer Request for the Hall Pattern 15 15 write-only by Hardware The bit fields CURH and EXPH are updated according to the defined hardware action. The write access to bit fields CURHS and EXPHS does not modify the bit fields CURH and EXPH. 0b0 by Software The bit fields CURH and EXPH are updated by the value written to the bit fields CURHS and EXPHS. 0b1 CURHS Current Hall Pattern Shadow 11 13 read-write EXPHS Expected Hall Pattern Shadow 8 10 read-write STRMCM Shadow Transfer Request for MCMPS 7 7 write-only by Hardware Bit field MCMP is updated according to the defined hardware action. The write access to bit field MCMPS does not modify bit field MCMP. 0b0 by Software Bit field MCMP is updated by the value written to bit field MCMPS. 0b1 MCMPS Multi-Channel PWM Pattern Shadow 0 5 read-write MODCTR Modulation Control Register 0x5C 32 ECT13O Enable Compare Timer T13 Output 15 15 read-write Disabled The alternate output function COUT63 is disabled. 0b0 Enabled The alternate output function COUT63 is enabled for the PWM signal generated by T13. 0b1 T13MODEN T13 Modulation Enable 8 13 read-write Disabled The modulation of the corresponding output signal by a T13 PWM pattern is disabled. 0b0 Enabled The modulation of the corresponding output signal by a T13 PWM pattern is enabled. 0b1 MCMEN Multi-Channel Mode Enable 7 7 read-write Disabled The modulation of the corresponding output signal by a multi-channel pattern according to bit field MCMOUT is disabled. 0b0 Enabled The modulation of the corresponding output signal by a multi-channel pattern according to bit field MCMOUT is enabled. 0b1 T12MODEN T12 Modulation Enable 0 5 read-write Disabled The modulation of the corresponding output signal by a T12 PWM pattern is disabled. 0b0 Enabled The modulation of the corresponding output signal by a T12 PWM pattern is enabled. 0b1 PISEL0 Port Input Select Register 0 0x6C 32 IST12HR Input Select for T12HR 14 15 read-write T12HRA Either signal T12HRA (if T12EXT = 0) or T12HRE (if T12EXT = 1) is selected. 0b00 T12HRB Either signal T12HRB (if T12EXT = 0) or T12HRF (if T12EXT = 1) is selected. 0b01 T12HRC Either signal T12HRC (if T12EXT = 0) or T12HRG (if T12EXT = 1) is selected. 0b10 T12HRD Either signal T12HRD (if T12EXT = 0) or T12HRH (if T12EXT = 1) is selected. 0b11 ISPOS2 Input Select for CCPOS2 12 13 read-write CCPOS2_0 The input pin for CCPOS2_0. 0b00 CCPOS2_1 The input pin for CCPOS2_1. 0b01 CCPOS2_2 The input pin for CCPOS2_2. 0b10 ISPOS1 Input Select for CCPOS1 10 11 read-write CCPOS1_0 The input pin for CCPOS1_0. 0b00 CCPOS1_1 The input pin for CCPOS1_1. 0b01 CCPOS1_2 The input pin for CCPOS1_2. 0b10 ISPOS0 Input Select for CCPOS0 8 9 read-write CCPOS0_0 The input pin for CCPOS0_0. 0b00 CCPOS0_1 The input pin for CCPOS0_1. 0b01 CCPOS0_2 The input pin for CCPOS0_2. 0b10 ISTRP Input Select for CTRAP 6 7 read-write CTRAP_0 The input pin for CTRAP_0. 0b00 CTRAP_1 The input pin for CTRAP_1. 0b01 CTRAP_2 The input pin for CTRAP_2. 0b10 DU1_UP_STS The output DU1_UP_STS of the Differential Measurement Unit is selected. 0b11 ISCC62 Input Select for CC62 4 5 read-write CC62_0 The input pin for CC62_0. 0b00 CC62_1 The input pin for CC62_1. 0b01 ISCC61 Input Select for CC61 2 3 read-write CC61_0 The input pin for CC61_0. 0b00 CC61_1 The input pin for CC61_1. 0b01 ISCC60 Input Select for CC60 0 1 read-write CC60_0 The input pin for CC60_0. 0b00 CC60_1 The input pin for CC60_1. 0b01 PISEL2 Port Input Select Register 2 0x74 32 T13EXT Extension for T13HR Inputs 7 7 read-write T13HR_D_A One of the signals T13HR[D:A] is selected. 0b0 T13HR_H_E One of the signals T13HR[H:E] is selected. 0b1 T12EXT Extension for T12HR Inputs 6 6 read-write T12HR_D_A One of the signals T12HR[D:A] is selected. 0b0 T12HR_H_E One of the signals T12HR[H:E] is selected. 0b1 ISCNT13 Input Select for T13 Counting Input 4 5 read-write T13 prescaler The T13 prescaler generates the counting events. Bit TCTR4.T13CNT is not taken into account. 0b00 TCTR4.T13CNT Bit TCTR4.T13CNT written with 1 is a counting event. The T13 prescaler is not taken into account. 0b01 Rising edge The timer T13 is counting each rising edge detected in the selected T13HR signal. 0b10 Falling Edge The timer T13 is counting each falling edge detected in the selected T13HR signal. 0b11 ISCNT12 Input Select for T12 Counting Input 2 3 read-write T12 prescaler The T12 prescaler generates the counting events. Bit TCTR4.T12CNT is not taken into account. 0b00 TCTR4.T12CNT Bit TCTR4.T12CNT written with 1 is a counting event. The T12 prescaler is not taken into account. 0b01 Rising edge The timer T12 is counting each rising edge detected in the selected T12HR signal. 0b10 Falling edge The timer T12 is counting each falling edge detected in the selected T12HR signal. 0b11 IST13HR Input Select for T13HR 0 1 read-write T13HRA Either signal T13HRA (if T13EXT = 0) or T13HRE (if T13EXT = 1) is selected. 0b00 T13HRB Either signal T13HRB (if T13EXT = 0) or T13HRF (if T13EXT = 1) is selected. 0b01 T13HRC Either signal T13HRC (if T13EXT = 0) or T13HRG (if T13EXT = 1) is selected. 0b10 T13HRD Either signal T13HRD (if T13EXT = 0) or T13HRH (if T13EXT = 1) is selected. 0b11 PSLR Passive State Level Register 0x50 32 PSL63 Passive State Level of Output COUT63 7 7 read-write Level 0 The passive level is 0. 0b0 Level 1 The passive level is 1. 0b1 PSL Compare Outputs Passive State Level 0 5 read-write Level 0 The passive level is 0. 0b0 Level 1 The passive level is 1. 0b1 T12 Timer T12 Counter Register 0x78 32 T12CV Timer T12 Counter Value 0 15 read-write T12DTC Dead-Time Control Register for Timer T12 Low 0x2C 32 DTR2 Dead-Time Run Indication Bit 2 14 14 read-only Zero The value of the corresponding dead-time counter channel is 0. 0b0 Not Zero The value of the corresponding dead-time counter channel is not 0. 0b1 DTR1 Dead-Time Run Indication Bit 1 13 13 read-only Zero The value of the corresponding dead-time counter channel is 0. 0b0 Not Zero The value of the corresponding dead-time counter channel is not 0. 0b1 DTR0 Dead-Time Run Indication Bit 0 12 12 read-only Zero The value of the corresponding dead-time counter channel is 0. 0b0 Not Zero The value of the corresponding dead-time counter channel is not 0. 0b1 DTE2 Dead-Time Enable Bit 2 10 10 read-write Disabled Dead-time generation is disabled. The corresponding outputs switch from the passive state to the active state (according to the actual compare status) without any delay. 0b0 Enabled Dead-time generation is enabled. The corresponding outputs switch from the passive state to the active state (according to the compare status) with the delay programmed in bit field DTM. 0b1 DTE1 Dead-Time Enable Bit 1 9 9 read-write Disabled Dead-time generation is disabled. The corresponding outputs switch from the passive state to the active state (according to the actual compare status) without any delay. 0b0 Enabled Dead-time generation is enabled. The corresponding outputs switch from the passive state to the active state (according to the compare status) with the delay programmed in bit field DTM. 0b1 DTE0 Dead-Time Enable Bit 0 8 8 read-write Disabled Dead-time generation is disabled. The corresponding outputs switch from the passive state to the active state (according to the actual compare status) without any delay. 0b0 Enabled Dead-time generation is enabled. The corresponding outputs switch from the passive state to the active state (according to the compare status) with the delay programmed in bit field DTM. 0b1 DTM Dead-Time 0 7 read-write T12MSEL T12 Capture/Compare Mode Select Register 0x40 32 DBYP Delay Bypass 15 15 read-write Not active The delay bypass is not active. The dead-time counter DTC0 is generating a delay after the source signal becomes active. 0b0 Active The delay bypass is active. The dead-time counter DTC0 is not used by the sampling of the Hall pattern. 0b1 HSYNC Hall Synchronization 12 14 read-write Any Any edge at one of the inputs CCPOSx (x = 0, 1, 2) triggers the sampling. 0b000 T13 compare-match A T13 compare-match triggers the sampling. 0b001 T13 period-match A T13 period-match triggers the sampling. 0b010 Hall The Hall sampling triggered by hardware sources is switched off. 0b011 T12 period-match A T12 period-match (while counting up) triggers the sampling. 0b100 T12 one-match A T12 one-match (while counting down) triggers the sampling. 0b101 T12 compare-match UP A T12 compare-match of channel 0 (while counting up) triggers the sampling. 0b110 T12 compare-match DOWN A T12 compare-match of channel 0 (while counting down) triggers the sampling. 0b111 MSEL62 Capture/Compare Mode Selection 8 11 read-write Compare outputs disabled Compare outputs disabled, pins CC6n and COUT6n can be used for I/O. No capture action. 0b0000 Pin CC6n, pin COUT6n Compare output on pin CC6n, pin COUT6n can be used for I/O. No capture action. 0b0001 Pin COUT6n, Pin CC6n Compare output on pin COUT6n, pin CC6n can be used for I/O. No capture action. 0b0010 Pins COUT6n and CC6n Compare output on pins COUT6n and CC6n. 0b0011 Double-Register Capture modes see . 0b01XX Hall Sensor mode see . In order to enable the hall edge detection, all three MSEL6x must be programmed to Hall Sensor mode. 0b1000 Hysteresis-like_mode see . 0b1001 Multi-Input_Capture_modes see . 0b101X Multi-Input_Capture_modes see . 0b11XX MSEL61 Capture/Compare Mode Selection 4 7 read-write Compare outputs disabled Compare outputs disabled, pins CC6n and COUT6n can be used for I/O. No capture action. 0b0000 Pin CC6n, pin COUT6n Compare output on pin CC6n, pin COUT6n can be used for I/O. No capture action. 0b0001 Pin COUT6n, Pin CC6n Compare output on pin COUT6n, pin CC6n can be used for I/O. No capture action. 0b0010 Pins COUT6n and CC6n Compare output on pins COUT6n and CC6n. 0b0011 Double-Register Capture modes see . 0b01XX Hysteresis-like_mode see . In order to enable the hall edge detection, all three MSEL6x must be programmed to Hall Sensor mode. 0b1000 Multi-Input_Capture_modes see . 0b11XX MSEL60 Capture/Compare Mode Selection 0 3 read-write Compare outputs disabled Compare outputs disabled, pins CC6n and COUT6n can be used for I/O. No capture action. 0b0000 Pin CC6n, pin COUT6n Compare output on pin CC6n, pin COUT6n can be used for I/O. No capture action. 0b0001 Pin COUT6n, Pin CC6n Compare output on pin COUT6n, pin CC6n can be used for I/O. No capture action. 0b0010 Pins COUT6n and CC6n Compare output on pins COUT6n and CC6n. 0b0011 Double-Register Capture modes see . 0b01XX Hysteresis-like_mode see . In order to enable the hall edge detection, all three MSEL6x must be programmed to Hall Sensor mode. 0b1000 Multi-Input_Capture_modes see . 0b11XX T12PR Timer T12 Period Register 0x24 32 T12PV T12 Period Value 0 15 read-write T13 Timer T13 Counter Register 0x7C 32 T13CV Timer T13 Counter Value 0 15 read-write T13PR Timer T13 Period Register 0x28 32 T13PV T13 Period Value 0 15 read-write TCTR0 Timer Control Register 0 0x30 32 STE13 Timer T13 Shadow Transfer Enable 13 13 read-only Disabled The shadow register transfer is disabled. 0b0 Enabled The shadow register transfer is enabled. 0b1 T13R Timer T13 Run Bit 12 12 read-only Stop Timer T13 is stopped. 0b0 Run Timer T13 is running. 0b1 T13PRE Timer T13 Prescaler Bit 11 11 read-write Disabled The additional prescaler for T13 is disabled. 0b0 Enabled The additional prescaler for T13 is enabled. 0b1 T13CLK Timer T13 Input Clock Select 8 10 read-write 1 fT13 = fCCU 0b000 2 fT13 = fCCU / 2 0b001 4 fT13 = fCCU / 4 0b010 8 fT13 = fCCU / 8 0b011 16 fT13 = fCCU / 16 0b100 32 fT13 = fCCU / 32 0b101 64 fT13 = fCCU / 64 0b110 128 fT13 = fCCU / 128 0b111 CTM T12 Operating Mode 7 7 read-write Edge-aligned Mode T12 always counts up and continues counting from zero after reaching the period value. 0b0 Center-aligned Mode T12 counts down after detecting a period-match and counts up after detecting a one-match. 0b1 CDIR Count Direction of Timer T12 6 6 read-only UP T12 counts up. 0b0 DOWN T12 counts down. 0b1 STE12 Timer T12 Shadow Transfer Enable 5 5 read-only Disabled The shadow register transfer is disabled. 0b0 Enabled The shadow register transfer is enabled. 0b1 T12R Timer T12 Run Bit 4 4 read-only Stop Timer T12 is stopped. 0b0 Run Timer T12 is running. 0b1 T12PRE Timer T12 Prescaler Bit 3 3 read-write Disabled The additional prescaler for T12 is disabled. 0b0 Enabled The additional prescaler for T12 is enabled. 0b1 T12CLK Timer T12 Input Clock Select 0 2 read-write 1 fT12 = fCCU 0b000 2 fT12 = fCCU / 2 0b001 4 fT12 = fCCU / 4 0b010 8 fT12 = fCCU / 8 0b011 16 fT12 = fCCU / 16 0b100 32 fT12 = fCCU / 32 0b101 64 fT12 = fCCU / 64 0b110 128 fT12 = fCCU / 128 0b111 TCTR2 Timer Control Register 2 0x58 32 T13RSEL Timer T13 External Run Selection 10 11 read-write Disabled The external setting of T13R is disabled. 0b00 Rising edge Bit T13R is set if a rising edge of signal T13HR is detected. 0b01 Falling edge Bit T13R is set if a falling edge of signal T13HR is detected. 0b10 Edge Bit T13R is set if an edge of signal T13HR is detected. 0b11 T12RSEL Timer T12 External Run Selection 8 9 read-write Disabled The external setting of T12R is disabled. 0b00 Rising edge Bit T12R is set if a rising edge of signal T12HR is detected. 0b01 Falling edge Bit T12R is set if a falling edge of signal T12HR is detected. 0b10 Edge Bit T12R is set if an edge of signal T12HR is detected. 0b11 T13TED Timer T13 Trigger Event Direction 5 6 read-write No action 0b00 Up while T12 is counting up 0b01 Down while T12 is counting down 0b10 Independent independent on the count direction of T12 0b11 T13TEC T13 Trigger Event Control 2 4 read-write No action 0b000 Channel 0 set T13R on a T12 compare event on channel 0 0b001 Channel 1 set T13R on a T12 compare event on channel 1 0b010 Channel 2 set T13R on a T12 compare event on channel 2 0b011 Channel 0,1,2 set T13R on any T12 compare event on the channels 0, 1, or 2 0b100 Period-match set T13R upon a period-match of T12 0b101 Zero-match set T13R upon a zero-match of T12 (while counting up) 0b110 CCPOSx set T13R on any edge of inputs CCPOSx 0b111 T13SSC Timer T13 Single Shot Control 1 1 read-write No action No hardware action on T13R 0b0 Enabled The single-shot mode is enabled, the bit T13R is reset by hardware if T13 reaches its period value. In parallel to the reset action of bit T13R, the bit CC63ST is reset. 0b1 T12SSC Timer T12 Single Shot Control 0 0 read-write Disabled The single-shot mode is disabled, no hardware action on T12R. 0b0 Enabled The single shot mode is enabled, the bit T12R is reset by hardware if: - T12 reaches its period value in edge-aligned mode - T12 reaches the value 1 while down counting in center-aligned mode. In parallel to the reset action of bit T12R, the bits CC6xST (x = 0, 1, 2) are reset. 0b1 TCTR4 Timer Control Register 4 0x04 32 T13STD Timer T13 Shadow Transfer Disable 15 15 write-only No action 0b0 STE13 reset STE13 is reset without triggering the shadow transfer. 0b1 T13STR Timer T13 Shadow Transfer Request 14 14 write-only No action 0b0 STE13 set STE13 is set, enabling the shadow transfer. 0b1 T13CNT Timer T13 Count Event 13 13 write-only No action 0b0 Count If enabled (PISEL2), timer T13 counts one step. 0b1 T13RES Timer T13 Reset 10 10 write-only No effect No effect on T13. 0b0 Zero The T13 counter register is reset to zero. The switching of the output signals is according to the switching rules. Setting of T13RES has no impact on bit T13R. 0b1 T13RS Timer T13 Run Set 9 9 write-only No influence T13R is not influenced. 0b0 T13R set T13R is set, T13 counts. 0b1 T13RR Timer T13 Run Reset 8 8 write-only No influence T13R is not influenced. 0b0 T13R cleared T13R is cleared, T13 stops counting. 0b1 T12STD Timer T12 Shadow Transfer Disable 7 7 write-only No action 0b0 STE12 reset STE12 is reset without triggering the shadow transfer. 0b1 T12STR Timer T12 Shadow Transfer Request 6 6 write-only No action 0b0 STE12 set STE12 is set, enabling the shadow transfer. 0b1 T12CNT Timer T12 Count Event 5 5 write-only No action 0b0 Count If enabled (PISEL2), timer T12 counts one step. 0b1 DTRES Dead-Time Counter Reset 3 3 write-only No effect No effect on the dead-time counters. 0b0 Zero The three dead-time counter channels are reset to zero. 0b1 T12RES Timer T12 Reset 2 2 write-only No effect No effect on T12. 0b0 Zero The T12 counter register is reset to zero. The switching of the output signals is according to the switching rules. Setting of T12RES has no impact on bit T12R. 0b1 T12RS Timer T12 Run Set 1 1 write-only No influence T12R is not influenced. 0b0 T12R set T12R is set, T12 counts. 0b1 T12RR Timer T12 Run Reset 0 0 write-only No influence T12R is not influenced. 0b0 T12R cleared T12R is cleared, T12 stops counting. 0b1 TRPCTR Trap Control Register 0x60 32 TRPPEN Trap Pin Enable 15 15 read-write Disabled The trap functionality based on the input pin CTRAP is disabled. A trap can only be generated by software by setting bit TRPF. 0b0 Enabled The trap functionality based on the input pin CTRAP is enabled. A trap can be generated by software by setting bit TRPF or by CTRAP = 0. 0b1 TRPEN13 Trap Enable Control for Timer T13 14 14 read-write Disabled The trap functionality for T13 is disabled. Timer T13 (if selected and enabled) provides PWM functionality even while TRPS = 1. 0b0 Enabled The trap functionality for T13 is enabled. The timer T13 PWM output signal is set to the passive state while TRPS = 1. 0b1 TRPEN Trap Enable Control 8 13 read-write Disabled The trap functionality of the corresponding output signal is disabled. The output state is independent from bit TRPS. 0b0 Enabled The trap functionality of the corresponding output signal is enabled. The output is set to the passive state while TRPS = 1. 0b1 TRPM2 Trap Mode Control Bit 2 2 2 read-write Hardware reset The trap state can be left (return to normal operation = bit TRPS = 0) as soon as the input CTRAP becomes inactive. Bit TRPF is automatically cleared by hardware if the input pin CTRAP becomes 1. Bit TRPS is automatically cleared by hardware if bit TRPF is 0 and if the synchronization condition (according to TRPM10) is detected. 0b0 Software reset The trap state can be left (return to normal operation = bit TRPS = 0) as soon as bit TRPF is reset by software after the input CTRAP becomes inactive (TRPF is not cleared by hardware). Bit TRPS is automatically cleared by hardware if bit TRPF = 0 and if the synchronization condition (according to TRPM10) is detected. 0b1 TRPM10 Trap Mode Control Bits 1, 0 0 1 read-write T12 zero-match The trap state is left (return to normal operation according to TRPM2) when a zero-match of T12 (while counting up) is detected (synchronization to T12). 0b00 T13 zero-match The trap state is left (return to normal operation according to TRPM2) when a zero-match of T13 is detected (synchronization to T13). 0b01 Immediately The trap state is left (return to normal operation according to TRPM2) immediately without any synchronization to T12 or T13. 0b11 CPU CPU 0xE000E000 0x0 0x1000 registers AIRCR Application Interrupt/Reset Control Register 0xD0C 32 VECTKEY Vector Key 16 31 read-write ENDIANNESS Data Endianness 15 15 read-only Little Endian 0b0 Big Endian 0b1 SYSRESETREQ System Reset Request 2 2 write-only No Reset no effect 0b0 Reset request a system level reset 0b1 VECTCLRACTIVE VECTCLRACTIVE 1 1 write-only CCR Configuration Control Register 0xD14 32 STKALIGN STKALIGN 9 9 read-only UNALIGN_TRP UNALIGN_TRP 3 3 read-only CPUID CPU ID Base Register 0xD00 32 IMPLEMENTER Implementer Code 24 31 read-only VARIANT Variant Number 20 23 read-only CONSTANT Constant 16 19 read-only PARTNO Part Number 4 15 read-only REVISION Revision Number 0 3 read-only ICSR Interrupt Control and State Register 0xD04 32 NMIPENDSET NMI Set Pending 31 31 read-write Not Pending on writes, has no effect. On reads, NMI exception is not pending. 0b0 Pending on writes, changes the NMI exception state to pending. On reads, NMI exception is pending. 0b1 PENDSVSET PENDSV Set Pending 28 28 read-write Not Pending on writes, has no effect. On reads, PendSV exception is not pending. 0b0 Pending on writes, changes PendSV exception state to pending. On reads, PendSV is pending. 0b1 PENDSVCLR PENDSV Clear Pending 27 27 write-only No Clear no effect 0b0 Clear remove pending state from the PENDSV exception 0b1 PENDSTSET SysTick Exception Set Pending 26 26 read-write Not Pending on writes, has no effect. On reads, SysTick exception is not pending. 0b0 Pending on writes, changes SysTick exception state to pending. On reads, SysTick exception is pending. 0b1 PENDSTCLR SysTick Exception Clear Pending 25 25 write-only No Clear no effect 0b0 Clear removes the pending state from the SysTick exception 0b1 ISRPENDING Interrupt Pending Flag 22 22 read-only Not Pending interrupt not pending 0b0 Pending interrupt is pending 0b1 VECTPENDING VECTPENDING 12 17 read-only no pending exceptions 0b0 VECTACTIVE VECTACTIVE 0 5 read-only Thread mode 0b0 NVIC_ICER Interrupt Clear-Enable 0x180 32 Int_PORT2 Interrupt Clear for PORT2 23 23 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_MON Interrupt Clear for MON 22 22 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_DU Interrupt Clear for Differential Unit 21 21 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_OPA Interrupt Clear for Current Sense Amplifier 20 20 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_HS Interrupt Clear for High-Side Switch 19 19 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_BDRV Interrupt Clear for Bridge Driver 18 18 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_CP Interrupt Clear for Charge Pump 17 17 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_MATHDIV Interrupt Clear for Math Divider 15 15 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_WAKEUP Interrupt Clear for WAKEUP 14 14 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_EXINT1 Interrupt Clear for External Int 1 13 13 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_EXINT0 Interrupt Clear for External Int 0 12 12 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_UART2 Interrupt Clear for UART2 11 11 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_UART1 Interrupt Clear for UART1 10 10 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_SSC2 Interrupt Clear for SSC2 9 9 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_SSC1 Interrupt Clear for SSC1 8 8 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_CCU6SR3 Interrupt Clear for CCU6 SR3 7 7 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_CCU6SR2 Interrupt Clear for CCU6 SR2 6 6 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_CCU6SR1 Interrupt Clear for CCU6 SR1 5 5 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_CCU6SR0 Interrupt Clear for CCU6 SR0 4 4 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_ADC1 Interrupt Clear for ADC1 3 3 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_ADC2 Interrupt Clear for MU, ADC2 2 2 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_GPT2 Interrupt Clear for GPT2 1 1 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 Int_GPT1 Interrupt Clear for GPT1 0 0 read-write DISABLE on reads the associated interrupt is disabled, no effect on write 0b0 ENABLE on reads the associated interrupt is enabled, on writes the associated interrupt is disabled 0b1 NVIC_ICPR Interrupt Clear-Pending 0x280 32 Int_PORT2 Interrupt Clear Pending for PORT2 23 23 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_MON Interrupt Clear Pending for MON 22 22 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_DU Interrupt Clear Pending for Differential Unit 21 21 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_OPA Interrupt Clear Pending for Current Sense Amplifier 20 20 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_HS Interrupt Clear Pending for High-Side Switch 19 19 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_BDRV Interrupt Clear Pending for Bridge Driver 18 18 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_CP Interrupt Clear Pending for Charge Pump 17 17 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_MATHDIV Interrupt Clear Pending for Math Divider 15 15 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_WAKEUP Interrupt Clear Pending for WAKEUP 14 14 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_EXINT1 Interrupt Clear Pending for External Int 1 13 13 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_EXINT0 Interrupt Clear Pending for External Int 0 12 12 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_UART2 Interrupt Clear Pending for UART2 11 11 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_UART1 Interrupt Clear Pending for UART1 10 10 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_SSC2 Interrupt Clear Pending for SSC2 9 9 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_SSC1 Interrupt Clear Pending for SSC1 8 8 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_CCU6SR3 Interrupt Clear Pending for CCU6 SR3 7 7 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_CCU6SR2 Interrupt Clear Pending for CCU6 SR2 6 6 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_CCU6SR1 Interrupt Clear Pending for CCU6 SR1 5 5 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_CCU6SR0 Interrupt Clear Pending for CCU6 SR0 4 4 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_ADC1 Interrupt Clear Pending for ADC1 3 3 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_ADC2 Interrupt Clear Pending for MU, ADC2 2 2 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_GPT2 Interrupt Clear Pending for GPT2 1 1 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 Int_GPT1 Interrupt Clear Pending for GPT1 0 0 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending on reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 0b1 NVIC_IPR0 Interrupt Priority 0x400 32 PRI_ADC1 Priority for ADC1 30 31 read-write PRI_ADC2 Priority for MU, ADC2 22 23 read-write PRI_GPT2 Priority for GPT2 14 15 read-write PRI_GPT1 Priority for GPT1 6 7 read-write NVIC_IPR1 Interrupt Priority 0x404 32 PRI_CCU6SR3 Priority for CCU6 SR3 30 31 read-write PRI_CCU6SR2 Priority for CCU6 SR2 22 23 read-write PRI_CCU6SR1 Priority for CCU6 SR1 14 15 read-write PRI_CCU6SR0 Priority for CCU6 SR0 6 7 read-write NVIC_IPR2 Interrupt Priority 0x408 32 PRI_UART2 Priority for UART2 30 31 read-write PRI_UART1 Priority for UART1 22 23 read-write PRI_SSC2 Priority for SSC2 14 15 read-write PRI_SSC1 Priority for SSC1 6 7 read-write NVIC_IPR3 Interrupt Priority 0x40C 32 PRI_MATHDIV Priority for Math Divider 30 31 read-write PRI_WAKEUP Priority for WAKEUP 22 23 read-write PRI_EXINT1 Priority for External Int 1 14 15 read-write PRI_EXINT0 Priority for External Int 0 6 7 read-write NVIC_IPR4 Interrupt Priority 0x410 32 PRI_HS Priority for High-Side Switch 30 31 read-write PRI_BDRV Priority for Bridge Driver 22 23 read-write PRI_CP Priority for Charge Pump 14 15 read-write NVIC_IPR5 Interrupt Priority 0x414 32 PRI_PORT2 Priority for PORT2 30 31 read-write PRI_MON Priority for MON 22 23 read-write PRI_DU Priority for Differential Unit 14 15 read-write PRI_OPA Priority for Current Sense Amplifier 6 7 read-write NVIC_ISER Interrupt Set-Enable 0x100 32 Int_PORT2 Interrupt Set for PORT2 23 23 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_MON Interrupt Set for MON 22 22 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_DU Interrupt Set for Differential Unit 21 21 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_OPA Interrupt Set for Current Sense Amplifier 20 20 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_HS Interrupt Set for High-Side Switch 19 19 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_BDRV Interrupt Set for Bridge Driver 18 18 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_CP Interrupt Set for Charge Pump 17 17 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_MATHDIV Interrupt Set for Math Divider 15 15 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_WAKEUP Interrupt Set for WAKEUP 14 14 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_EXINT1 Interrupt Set for External Int 1 13 13 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_EXINT0 Interrupt Set for External Int 0 12 12 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_UART2 Interrupt Set for UART2 11 11 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_UART1 Interrupt Set for UART1 10 10 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_SSC2 Interrupt Set for SSC2 9 9 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_SSC1 Interrupt Set for SSC1 8 8 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_CCU6SR3 Interrupt Set for CCU6 SR3 7 7 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_CCU6SR2 Interrupt Set for CCU6 SR2 6 6 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_CCU6SR1 Interrupt Set for CCU6 SR1 5 5 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_CCU6SR0 Interrupt Set for CCU6 SR0 4 4 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_ADC1 Interrupt Set for ADC1 3 3 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_ADC2 Interrupt Set for MU, ADC2 2 2 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_GPT2 Interrupt Set for GPT2 1 1 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 Int_GPT1 Interrupt Set for GPT1 0 0 read-write DISABLED no effect on write 0b0 ENABLE enables the associated interrupt 0b1 NVIC_ISPR Interrupt Set-Pending 0x200 32 Int_PORT2 Interrupt Set Pending for PORT2 23 23 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_MON Interrupt Set Pending for MON 22 22 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_DU Interrupt Set Pending for Differential Unit 21 21 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_OPA Interrupt Set Pending for Current Sense Amplifier 20 20 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_HS Interrupt Set Pending for High-Side Switch 19 19 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_BDRV Interrupt Set Pending for Bridge Driver 18 18 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_CP Interrupt Set Pending for Charge Pump 17 17 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_MATHDIV Interrupt Set Pending for Math Divider 15 15 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_WAKEUP Interrupt Set Pending for WAKEUP 14 14 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_EXINT1 Interrupt Set Pending for External Int 1 13 13 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_EXINT0 Interrupt Set Pending for External Int 0 12 12 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_UART2 Interrupt Set Pending for UART2 11 11 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_UART1 Interrupt Set Pending for UART1 10 10 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_SSC2 Interrupt Set Pending for SSC2 9 9 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_SSC1 Interrupt Set Pending for SSC1 8 8 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_CCU6SR3 Interrupt Set Pending for CCU6 SR3 7 7 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_CCU6SR2 Interrupt Set Pending for CCU6 SR2 6 6 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_CCU6SR1 Interrupt Set Pending for CCU6 SR1 5 5 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_CCU6SR0 Interrupt Set Pending for CCU6 SR0 4 4 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_ADC1 Interrupt Set Pending for ADC1 3 3 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_ADC2 Interrupt Set Pending for MU, ADC2 2 2 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_GPT2 Interrupt Set Pending for GPT2 1 1 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 Int_GPT1 Interrupt Set Pending for GPT1 0 0 read-write Not Pending on reads the associated interrupt is not pending, no effect on writes 0b0 Pending the associated interrupt is pending 0b1 SCR System Control Register 0xD10 32 SEVONPEND SEVONPEND 4 4 read-write Enabled only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded 0b0 All enabled events and all interrupts, including disabled interrupts, can wake-up the processor 0b1 SLEEPDEEP Sleep Deep 2 2 read-write sleep 0b0 deep sleep 0b1 SLEEPONEXIT Sleep on Exit 1 1 read-write Do Not Sleep do not sleep when returning to Thread mode 0b0 Enter Sleep enter sleep, or deep sleep, on return from an ISR to Thread mode 0b1 SHCSR System Handler Control and State Register 0xD24 32 SVCALLPENDED SVCALLPENDED 15 15 read-write Not Pending SVCall is not pending 0b0 Pending SVCall is pending 0b1 SHPR2 System Handler Priority Register 2 0xD1C 32 PRI_11 Priority of System Handler 11, SVCall 30 31 read-write SHPR3 System Handler Priority Register 3 0xD20 32 PRI_15 Priority of System Handler 15, SysTick 30 31 read-write PRI_14 Priority of System Handler 14, PendSV 22 23 read-write SYSTICK_CALIB SysTick Calibration Value Register 0x01C 32 NOREF No Reference Clock 31 31 read-only SKEW Skew 30 30 read-only TENMS Tenms 0 23 read-only SYSTICK_CSR SysTick Control and Status Register 0x010 32 COUNTFLAG Count Flag 16 16 read-only CLKSOURCE CLK Source 2 2 read-write External external reference clock 0b0 Processor processor clock 0b1 TICKINT TICKINT 1 1 read-write No Exception counting down to 0 does not assert the SysTick exception request. 0b0 Exception counting down to 0 asserts the SysTick exception request. 0b1 ENABLE Enable 0 0 read-write Disable counter disabled. 0b0 Enable counter enabled. 0b1 SYSTICK_CVR SysTick Current Value Register 0x018 32 CURRENT Current 0 23 read-write SYSTICK_RVR SysTick Reload Value Register 0x014 32 RELOAD Reload 0 23 read-write GPT12E GPT12E 0x40010000 0x0 0x4000 registers INTISR0 Interrupt node 0: GPT1 Block 0 INTISR1 Interrupt node 1: GPT2 Block 1 CAPREL Capture/Reload Register 0x1C 32 CAPREL Current reload value or Captured value 0 15 read-write ID Module Identification Register 0x00 32 MOD_TYPE Module Identification Number 8 15 read-only MOD_REV Module Revision Number 0 7 read-only PISEL Port Input Select Register 0x04 32 ISCAPIN Input Select for CAPIN 14 15 read-write CAPINA Signal CAPINA is selected 0b00 CAPINB Signal CAPINB is selected 0b01 CAPINC Signal CAPINC (Read trigger from T3) is selected 0b10 CAPIND Signal CAPIND (Read trigger from T2 or T3 or T4) is selected 0b11 IST6EUD Input Select for T6EUD 13 13 read-write T6EUDA Signal T6EUDA is selected 0b0 T6EUDB Signal T6EUDB is selected 0b1 IST6IN Input Select for T6IN 12 12 read-write T6INA Signal T6INA is selected 0b0 T6INB Signal T6INB is selected 0b1 IST5EUD Input Select for T5EUD 11 11 read-write T5EUDA Signal T5EUDA is selected 0b0 T5EUDB Signal T5EUDB is selected 0b1 IST5IN Input Select for T5IN 10 10 read-write T5INA Signal T5INA is selected 0b0 T5INB Signal T5INB is selected 0b1 IST4EUD Input Select for TEUD 8 9 read-write T4EUDA Signal T4EUDA is selected 0b00 T4EUDB Signal T4EUDB is selected 0b01 T4EUDC Signal T4EUDC is selected 0b10 T4EUDD Signal T4EUDD is selected 0b11 IST4IN Input Select for T4IN 6 7 read-write T4INA Signal T4INA is selected 0b00 T4INB Signal T4INB is selected 0b01 T4INC Signal T4INC is selected 0b10 T4IND Signal T4IND is selected 0b11 IST3EUD Input Select for T3EUD 4 5 read-write T3EUDA Signal T3EUDA is selected 0b00 T3EUDB Signal T3EUDB is selected 0b01 T3EUDC Signal T3EUDC is selected 0b10 T3EUDD Signal T3EUDD is selected 0b11 IST3IN Input Select for T3IN 2 3 read-write T3INA Signal T3INA is selected 0b00 T3INB Signal T3INB is selected 0b01 T3INC Signal T3INC is selected 0b10 T3IND Signal T3IND is selected 0b11 IST2EUD Input Select for T2EUD 1 1 read-write T2EUDA Signal T2EUDA is selected 0b0 T2EUDB Signal T2EUDB is selected 0b1 IST2IN Input Select for T2IN 0 0 read-write T2INA Signal T2INA is selected 0b0 T2INB Signal T2INB is selected 0b1 T2 Timer T2 Count Register 0x20 32 T2 Timer T2 Current Value 0 15 read-write T2CON Timer T2 Control Register 0x08 32 T2DIR Timer T2 Rotation Direction 15 15 read-only Up Timer T2 counts up 0b0 Down Timer T2 counts down 0b1 T2CHDIR Timer T2 Count Direction Change 14 14 read-write No change No change of count direction was detected 0b0 Change A change of count direction was detected 0b1 T2EDGE Timer T2 Edge Detection 13 13 read-write No count No count edge was detected 0b0 Count A count edge was detected 0b1 T2IRIDIS Timer T2 Interrupt Disable 12 12 read-write Enabled Interrupt generation for T2CHDIR and T2EDGE interrupts in Incremental Interface Mode is enabled 0b0 Disabled Interrupt generation for T2CHDIR and T2EDGE interrupts in Incremental Interface Mode is disabled 0b1 T2RC Timer T2 Remote Control 9 9 read-write T2R Timer T2 is controlled by its own run bit T2R 0b0 T3R Timer T2 is controlled by the run bit T3R of core timer T3, not by bit T2R 0b1 T2UDE Timer T2 External Up/Down Enable 8 8 read-write T2UD Count direction is controlled by bit T2UD; input T2EUD is disconnected 0b0 T2EUD Count direction is controlled by input T2EUD 0b1 T2UD Timer T2 Up/Down Control 7 7 read-write Up Timer T2 counts up 0b0 Down Timer T2 counts down 0b1 T2R Timer T2 Input Run Bit 6 6 read-write Stop Timer T2 stops 0b0 Run Timer T2 runs 0b1 T2M Timer T2 Input Mode Control 3 5 read-write value1 Timer Mode 0b000 value2 Counter Mode 0b001 value3 Gated Timer Mode with gate active low 0b010 value4 Gated Timer Mode with gate active high 0b011 value5 Reload Mode 0b100 value6 Capture Mode 0b101 value7 Incremental Interface Mode (Rotation Detection Mode) 0b110 value8 Incremental Interface Mode (Edge Detection Mode) 0b111 T2I Timer T2 Input Parameter Selection 0 2 read-write T3 Timer T3 Count Register 0x24 32 T3 Timer T3 Current Value 0 15 read-write T3CON Timer T3 Control Register 0x0C 32 T3DIR Timer T3 Rotation Direction Flag 15 15 read-only Up Timer T3 counts up 0b0 Down Timer T3 counts down 0b1 T3CHDIR Timer T3 Count Direction Change Flag 14 14 read-write No change No change of count direction was detected 0b0 Change A change of count direction was detected 0b1 T3EDGE Timer T3 Edge Detection Flag 13 13 read-write No count No count edge was detected 0b0 Count A count edge was detected 0b1 BPS1 GPT1 Block Prescaler Control 11 12 read-write 8 fGPT/8 0b00 4 fGPT/4 0b01 32 fGPT/32 0b10 16 fGPT/16 0b11 T3OTL Timer T3 Overflow Toggle Latch 10 10 read-write T3OE Overflow/Underflow Output Enable 9 9 read-write Disabled Alternate Output Function Disabled 0b0 T3OUT State of T3 toggle latch is output on pin T3OUT 0b1 T3UDE Timer T3 External Up/Down Enable 8 8 read-write T3UD Count direction is controlled by bit T3UD; input T3EUD is disconnected 0b0 T3EUD Count direction is controlled by input T3EUD 0b1 T3UD Timer T3 Up/Down Control 7 7 read-write Up Timer T3 counts up 0b0 Down Timer T3 counts down 0b1 T3R Timer T3 Input Run Bit 6 6 read-write Stop Timer T3 stops 0b0 Run Timer T3 runs 0b1 T3M Timer T3 Input Mode Control 3 5 read-write value1 Timer Mode 0b000 value2 Counter Mode 0b001 value3 Gated Timer Mode with gate active low 0b010 value4 Gated Timer Mode with gate active high 0b011 value7 Incremental Interface Mode (Rotation Detection Mode) 0b110 value8 Incremental Interface Mode (Edge Detection Mode) 0b111 T3I Timer T3 Input Parameter Selection 0 2 read-write T4 Timer T4 Count Register 0x28 32 T4 Timer T4 Current Value 0 15 read-write T4CON Timer T4 Control Register 0x10 32 T4RDIR Timer T4 Rotation Direction 15 15 read-only Up Timer T4 counts up 0b0 Down Timer T4 counts down 0b1 T4CHDIR Timer T4 Count Direction Change 14 14 read-write No change No change in count direction was detected 0b0 Change A change in count direction was detected 0b1 T4EDGE Timer T4 Edge Direction 13 13 read-write No count No count edge was detected 0b0 Count A count edge was detected 0b1 T4IRDIS Timer T4 Interrupt Disable 12 12 read-write Enabled Interrupt generation for T4CHDIR and T4EDGE interrupts in Incremental Interface Mode is enabled 0b0 Disabled Interrupt generation for T4CHDIR and T4EDGE interrupts in Incremental Interface Mode is disabled 0b1 CLRT3EN Clear Timer T3 Enable 11 11 read-write No effect No effect of T4IN on Timer T3 0b0 Clear A falling edge on T4In clears timer T3 0b1 CLRT2EN Clear Timer T2 Enable 10 10 read-write No effect No effect of T4EUD on timer T2 0b0 Clear A falling edge on T4EUD clears timer T2 0b1 T4RC Timer T4 Remote Control 9 9 read-write T4R Timer T4 is controlled by its own run bit T4R 0b0 T3R Timer T4 is controlled by the run bit T3R of core timer T3, but not by bit T4R 0b1 T4UDE Timer T4 External Up/Down Enable 8 8 read-write T4UD Count direction is controlled by bit T4UD; input T4EUD is disconnected 0b0 T4EUD Count direction is controlled by input T4EUD 0b1 T4UD Timer T2 Up/Down Control 7 7 read-write Up Timer T2 counts up 0b0 Down Timer T2 counts down 0b1 T4R Timer T4 Input Run Bit 6 6 read-write Stop Timer T4 stops 0b0 Run Timer T4 runs 0b1 T4M Timer T4 Mode Control (Basic Operating Mode) 3 5 read-write value1 Timer Mode 0b000 value2 Counter Mode 0b001 value3 Gated Timer Mode with gate active low 0b010 value4 Gated Timer Mode with gate active high 0b011 value5 Reload Mode 0b100 value6 Capture Mode 0b101 value7 Incremental Interface Mode (Rotation Detection Mode) 0b110 value8 Incremental Interface Mode (Edge Detection Mode) 0b111 T4I Timer T4 Input Parameter Selection 0 2 read-write T5 Timer 5 Count Register 0x2C 32 T5 Timer T5 Current Value 0 15 read-write T5CON Timer T5 Control Register 0x14 32 T5SC Timer T5 Capture Mode Enable 15 15 read-write Disabled Capture into register CAPREL disabled 0b0 Enabled Capture into register CAPREL enabled 0b1 T5CLR Timer T5 Clear Enable Bit 14 14 read-write Not cleared Timer T5 is not cleared on a capture event 0b0 Cleared Timer T5 is cleared on a capture event 0b1 CI Register CAPREL Capture Trigger Selection 12 13 read-write Disabled Capture disabled 0b00 Positive Positive transition (rising edge) on CAPIN or any transition on T3IN 0b01 Negative Negative transition (falling edge) on CAPIN or any transition on T3EUD 0b10 Any Any transition (rising or falling edge) on CAPIN or any transition on T3IN or T3EUD 0b11 CT3 Timer T3 Capture Trigger Enable 10 10 read-write CAPIN Capture trigger from input line CAPIN 0b0 T3IN Capture trigger from T3 input lines T3IN and/or T3EUD 0b1 T5RC Timer T5 Remote Control 9 9 read-write T5R Timer T5 is controlled by its own run bit T5R 0b0 T6R Timer T5 is controlled by the run bit T6R of core timer T6, not by bit T5R 0b1 T5UDE Timer T5 External Up/Down Enable 8 8 read-write T5UD Count direction is controlled by bit T5UD; input T5EUD is disconnected 0b0 T5EUD Count direction is controlled by input T5EUD 0b1 T5UD Timer T2 Up/Down Control 7 7 read-write Up Timer T5 counts up 0b0 Down Timer T5 counts down 0b1 T5R Timer T5 Run Bit 6 6 read-write Stop Timer T5 stops 0b0 Run Timer T5 runs 0b1 T5M Timer T5 Input Mode Control 3 4 read-write value1 Timer Mode 0b00 value2 Counter Mode 0b01 value3 Gated Timer Mode with gate active low 0b10 value4 Gated Timer Mode with gate active high 0b11 T5I Timer T5 Input Parameter Selection 0 2 read-write T6 Timer 6 Count Register 0x30 32 T6 Timer T6 Current Value 0 15 read-write T6CON Timer T6 Control Register 0x18 32 T6SR Timer T6 Reload Mode Enable 15 15 read-write Disabled Reload from register CAPREL disabled 0b0 Enabled Reload from register CAPREL enabled 0b1 T6CLR Timer T6 Clear Enable Bit 14 14 read-write Not cleared Timer T6 is not cleared on a capture event 0b0 Cleared Timer T6 is cleared on a capture event 0b1 BPS2 GPT2 Block Prescaler Control 11 12 read-write 4 fGPT/4 0b00 2 fGPT/2 0b01 16 fGPT/16 0b10 8 fGPT/8 0b11 T6OTL Timer T6 Overflow Toggle Latch 10 10 read-write T6OE Overflow/Underflow Output Enable 9 9 read-write Disabled Alternate Output Function Disabled 0b0 T6OUT State of T6 toggle latch is output on pin T6OUT 0b1 T6UDE Timer T6 External Up/Down Enable 8 8 read-write T6UD Count direction is controlled by bit T6UD; input T6EUD is disconnected 0b0 T6EUD Count direction is controlled by input T6EUD 0b1 T6UD Timer T6 Up/Down Control 7 7 read-write Up Timer T3 counts up 0b0 Down Timer T3 counts down 0b1 T6R Timer T6 Input Run Bit 6 6 read-write Stop Timer T3 stops 0b0 Run Timer T3 runs 0b1 T6M Timer T6 Mode Control 3 5 read-write value1 Timer Mode 0b000 value2 Counter Mode 0b001 value3 Gated Timer Mode with gate active low 0b010 value4 Gated Timer Mode with gate active high 0b011 T6I Timer T6 Input Parameter Selection 0 2 read-write HS HS 0x40024000 0x0 0x4000 registers CTRL High Side Driver Control 0x04 32 HS1_OC_SEL High Side 1 Overcurrent Threshold Selection 12 13 read-write IOCTH0 25 mA min. 0x0 IOCTH1 50 mA min. 0x1 IOCTH2 100 mA min. 0x2 IOCTH3 150 mA min. 0x3 HS1_SR_CTRL_SEL High Side 1 Slew Rate Control select 8 9 read-write Slew Rate 1 Slow Slew Rate 3V/us is enabled 0b00 Slew Rate 2 Fast Slew Rate 40V/us is enabled 0b01 Slew Rate 3 Low EMC Slew Rate 1V/us is enabled (for low EMC emissions) 0b10 HS1_OL_EN High Side 1 Open Load Detection Enable 3 3 read-write DISABLE disable open load detection 0b0 ENABLE enable open load detection 0b1 HS1_ON High Side 1 On 2 2 read-write OFF HS driver off 0b0 ON HS driver on 0b1 HS1_PWM High Side 1 PWM Enable 1 1 read-write DISABLE disables control by PWM input 0b0 ENABLE enables control by PWM input 0b1 HS1_EN High Side 1 Enable 0 0 read-write DISABLE HS circuit power off 0b0 ENABLE HS circuit power on 0b1 IRQCLR High Side Driver Interrupt Status Clear Register 0x0C 32 HS1_OL_SC High Side 1 Open Load Status Clear 14 14 write-only no Clear 0b0 Clear 0b1 HS1_OT_SC High Side 1 Overtemperature Status Clear 13 13 write-only no Clear 0b0 Clear 0b1 HS1_OC_ISC High Side 1 Overcurrent Interrupt Status Clear 7 7 write-only no Clear 0b0 Clear 0b1 HS1_OL_ISC High Side 1 Open Load Interrupt Status Clear 6 6 write-only no Clear 0b0 Clear 0b1 HS1_OT_ISC High Side 1 Overtemperature Interrupt Status Clear 5 5 write-only no Clear 0b0 Clear 0b1 IRQEN High Side Driver Interrupt Enable Register 0x10 32 HS1_OC_IEN High Side 1 Overcurrent Interrupt Enable 7 7 read-write disable 0b0 enable 0b1 HS1_OL_IEN High Side 1 Open Load Interrupt Enable 6 6 read-write disable 0b0 enable 0b1 HS1_OT_IEN High Side 1 Overtemperature Interrupt Enable 5 5 read-write disabled 0b0 enable 0b1 IRQS High Side Driver Interrupt Status 0x08 32 HS1_OL_STS High Side 1 Open Load Status 14 14 read-write no Open Load no open load Condition occurred. 0b0 Open Load open load occurred; switch is not automatically shutdown. Write sets status. 0b1 HS1_OT_STS High Side 1 Overtemperature Status 13 13 read-write no Overtemperature no overtemperature occurred. 0b0 Overtemperature overtemperature occurred; switch is automatically shutdown. Write sets status. 0b1 HS1_OC_IS High Side 1 Overcurrent Interrupt Status 7 7 read-write no Overcurrent no overcurrent Condition occurred. 0b0 Overcurrent overcurrent occurred; switch is automatically shutdown. Write sets status. 0b1 HS1_OL_IS High Side 1 Open Load Interrupt Status 6 6 read-write NORMAL normal load 0b0 OPEN LOAD open load detected, write sets status 0b1 HS1_OT_IS High Side 1 Overtemperature Interrupt Status 5 5 read-write no Overtemperature no overtemperature occurred. 0b0 Overtemperature overtemperature occurred; switch is automatically shutdown. Write sets status 0b1 PWMSRCSEL High Side PWM Source Selection Register 0x24 32 HS1_SRC_SEL HS1 PWM Source Selection 3 5 read-write CC60 PWM output of CCU6 0b000 CC61 PWM output of CCU6 0b001 CC62 PWM output of CCU6 0b010 COUT60 PWM output of CCU6 0b011 COUT61 PWM output of CCU6 0b100 COUT62 PWM output of CCU6 0b101 T3OUT PWM output of GPT12 0b110 TRIM High Side Driver 1 TRIM 0x1C 32 HS1_OC_OT_BTFILT_SEL Blanking Time Filter Select for HS1 overcurrent / overtemperature detection 8 9 read-write 4_us 4 us filter time 0b00 8_us 8 us filter time 0b01 16_us 16 us filter time 0b10 32_us 32 us filter time 0b11 HS1_OL_BTFILT_SEL Blanking Time Filter Select for HS1 open Load detection 0 1 read-write 4_us 4 us filter time 0b00 8_us 8 us filter time 0b01 16_us 16 us filter time 0b10 32_us 32 us filter time 0b11 LIN LIN 0x4801E000 0x0 0x2000 registers CTRL LIN Transceiver Control 0x00 32 HV_MODE LIN Transceiver High Voltage Input - Output Mode 21 21 read-write DISABLE High Voltage Mode Entry is disabled 0b0 ENABLE High Voltage Mode Entry is enabled 0b1 FB_SM3 Feedback Signal 3 for Slope Mode Setting 15 15 read-only FB_SM2 Feedback Signal 2 for Slope Mode Setting 14 14 read-only FB_SM1 Feedback Signal 1 for Slope Mode Setting 13 13 read-only SM LIN Transmitter Slope mode control 11 12 read-write Normal Slope Mode for max. 20 kBaud 0b00 Fast Slope Mode for max. 40 kBaud 0b01 Low Slope Mode for max. 10.4 kBaud 0b10 Flash Mode for max. 150 kBaud# 0b11 RXD Output Signal of Receiver 10 10 read-only TXD LIN Transmitter switch on (only used when LIN_HV_MODE is set) 9 9 read-write Pull Down LIN Line Transmitter is switched on 0b0 Pull Up Resistor is active Transmitter is switched off 0b1 MODE_FB Feedback Signals for LIN Transmitter Mode Settings 4 6 read-only MODE LIN transceiver power mode control 1 2 read-write LIN Sleep Mode LIN module switched to LIN Sleep Mode 0b00 LIN Receive-Only Mode LIN module switched to LIN Receive Only Mode 0b01 LIN Normal Mode LIN module switched to LIN Normal Mode 0b11 EN LIN Transceiver enable 0 0 read-write DISABLE LIN module disable 0b0 ENABLE LIN module enable 0b1 IRQCLR LIN Transceiver Interrupt Status Register Clear 0x08 32 TXD_TMOUT_SC LIN TXD time-out Status Clear 11 11 write-only NO_Clear no time-out cleared 0b0 Clear time-out cleared 0b1 OT_SC LIN Receiver Overtemperature Status Clear 9 9 write-only NO_Clear overtemperature not cleared 0b0 Clear overtemperature cleared 0b1 M_SM_ERR_SC LIN Transceiver Mode Error - Slope Mode Error Status Clear 8 8 write-only NO_Clear overtemperature not cleared 0b0 Clear overtemperature cleared 0b1 TXD_TMOUT_ISC LIN TXD time-out Interrupt Status Clear 6 6 write-only NO_Clear no time-out cleared 0b0 Clear time-out cleared 0b1 OC_ISC LIN Receiver Overcurrent Interrupt Status Clear 5 5 write-only NO_Clear overcurrent status not cleared 0b0 Clear overcurrent status cleared 0b1 OT_ISC LIN Receiver Overtemperature Interrupt Status / Status Clear 4 4 write-only NO_Clear overtemperature not cleared 0b0 Clear overtemperature cleared 0b1 M_SM_ERR_ISC LIN Transceiver Mode Error - Slope Mode Error Interrupt Status Clear 3 3 write-only NO_Clear overtemperature not cleared 0b0 Clear overtemperature cleared 0b1 IRQEN LIN Transceiver Interrupt Enable Register 0x0C 32 TXD_TMOUT_IEN LIN Transceiver TxD-Timeout interrupt enable 6 6 read-write disable 0b0 enable 0b1 OC_IEN LIN Transceiver Overcurrent interrupt enable 5 5 read-write disable 0b0 enable 0b1 OT_IEN LIN Transceiver Overtemperature interrupt enable 4 4 read-write disable 0b0 enable 0b1 M_SM_ERR_IEN LIN Transceiver Mode - Slope Mode Error interrupt enable 3 3 read-write disable 0b0 enable 0b1 IRQS LIN Transceiver Interrupt Status 0x04 32 TXD_TMOUT_STS LIN TXD time-out Status 11 11 read-only NO_TIMEOUT no time-out occurred 0b0 TIMEOUT time-out occurred 0b1 OT_STS LIN Receiver Overtemperature Status 9 9 read-only no Overtemperature overtemperature occurred 0b0 Overtemperature overtemperature occurred 0b1 M_SM_ERR_STS LIN Transceiver Mode Error - Slope Mode Error Status 8 8 read-only no Mode Error - Slope Mode status occurred 0b0 Mode Error status occurred 0b1 TXD_TMOUT_IS LIN TXD time-out Interrupt Status 6 6 read-only NO_TIMEOUT no time-out occurred 0b0 TIMEOUT time-out occurred 0b1 OC_IS LIN Receiver Overcurrent Interrupt Status 5 5 read-only no Overcurrent overcurrent status occurred 0b0 Overcurrent overcurrent status occurred 0b1 OT_IS LIN Receiver Overtemperature Interrupt Status 4 4 read-only no Overtemperature overtemperature occurred 0b0 Overtemperature overtemperature occurred 0b1 M_SM_ERR_IS LIN Transceiver Mode Error - Slope Mode Error Interrupt Status 3 3 read-only no Mode Error - Slope Mode status occurred 0b0 Mode Error status occurred 0b1 MATH MATH 0x48013000 0x0 0x1000 registers INTISR15 Interrupt node 15: Math Div 15 DIVCON Divider Control Register 0x34 32 DVSSRC Divisor Shift Right Count 24 28 read-write DVDSLC Dividend Shift Left Count 16 20 read-write QSDIR Quotient Shift Direction 15 15 read-write Left shift Left shift 0b0 Right Shift Right shift 0b1 QSCNT Quotient Shift Count 8 12 read-write DIVMODE Division Mode 3 4 read-write 32-32 32-bit divide by 32-bit 0b00 32-16 32-bit divide by 16-bit 0b01 16-16 16-bit divide by 16-bit 0b10 USIGN Unsigned Division Enable 2 2 read-write signed Signed division is selected 0b0 unsigned Unsigned division is selected 0b1 STMODE Start Mode 1 1 read-write Auto Calculation is automatically started with a write to DVS register 0b0 Manual Calculation is started by setting the ST bit to 1 0b1 ST Start Bit 0 0 read-write no effect No effect 0b0 Start Start the division operation when STMODE=1# 0b1 DIVST Divider Status Register 0x30 32 BSY Busy Indication 0 0 read-only finish Divider is not running any division operation. 0b0 busy Divider is still running a division operation. 0b1 DVD Dividend Register 0x20 32 VAL Dividend Value 0 31 read-write DVS Divisor Register 0x24 32 VAL Divisor Value 0 31 read-write EVFCR Event Flag Clear Register 0x18 32 DIVERRC Divider Error Event Flag Clear 1 1 write-only no effect No effect. 0b0 clear Clears the Divider error event flag in EVFR register. 0b1 DIVEOCC Divider End of Calculation Event Flag Clear 0 0 write-only no effect No effect. 0b0 clear Clears the Divider end of calculation event flag in EVFR register. 0b1 EVFR Event Flag Register 0x10 32 DIVERR Divider Error Event Flag 1 1 read-only no Error Divider error event has not been detected 0b0 Error Divider error event has been detected 0b1 DIVEOC Divider End of Calculation Event Flag 0 0 read-only no EOC Divider end of calculation event has not been detected. 0b0 EOC Divider end of calculation event has been detected. 0b1 EVIER Event Interupt Enable Register 0x0C 32 DIVERRIEN Divider Error Interrupt Enable 1 1 read-write Disable Divider error interrupt generation is disabled 0b0 Enable Divider error interrupt generation is enabled 0b1 DIVEOCIEN Divider End of Calculation Interrupt Enable 0 0 read-write Disable Divider end of calculation interrupt generation is disabled. 0b0 Enable Divider end of calculation interrupt generation is enabled. 0b1 EVSFR Event Flag Set Register 0x14 32 DIVERRS Divider Error Event Flag Set 1 1 write-only no effect No effect. 0b0 Set Sets the Divider error event flag in EVFR register. Interrupt will be generated if enabled in EVIER register. 0b1 DIVEOCS Divider End of Calculation Event Flag Set 0 0 write-only no effect No effect. 0b0 Set Sets the Divider end of calculation event flag in EVFR register. Interrupt will be generated if enabled in EVIER register. 0b1 GLBCON Global Control Register 0x04 32 MATH_EN Enable Math Module 31 31 read-write Enable Math module is enabled 0b1 Disable Math module is disabled 0b0 SUSCFG Suspend Mode Configuration 16 17 read-write no suspend Suspend mode is never entered. 0b00 hard suspend Hard suspend mode will be entered when CPU is halted. 0b01 soft suspend Soft suspend mode will be entered when CPU is halted. 0b10 DVSRC Divisor Register Result Chaining 3 4 read-write disabled No result chaining is selected 0b00 QUOT QUOT register is the selected source 0b01 RMD RMD register is the selected source 0b10 DVDRC Dividend Register Result Chaining 0 1 read-write disabled No result chaining is selected 0b00 QUOT QUOT register is the selected source 0b01 RMD RMD register is the selected source 0b10 MATH_ID Module Identification Register 0x08 32 MOD_NUMBER Module Number Value 16 31 read-only MOD_TYPE Module Type 8 15 read-only MOD_REV Module Revision Number 0 7 read-only QUOT Quotient Register 0x28 32 VAL Quotient Value 0 31 read-only RMD Remainder Register 0x2C 32 VAL Remainder Value 0 31 read-only MF MF 0x48018000 0x0 0x4000 registers CSA_CTRL Current Sense Amplifier Control Register 0x00 32 CSA_VZERO Current Sense Output Selection 8 8 read-write VOUT CSA output connected to ADC1 Ch13 0b0 VZERO voltage reference connected to ADC1 Ch13 0b1 CSA_MI_EN Enable Module Isolation Testmode 4 4 read-write DISABLE 0b0 ENABLE 0b1 CSA_GAIN Operational Amplifier Gain Setting 1 2 read-write 10 Gain Factor 10 0b00 20 Gain Factor 20 0b01 40 Gain Factor 40 0b10 60 Gain Factor 60 0b11 CSA_EN CSA Enable 0 0 read-write DISABLE OPA switched off 0b0 ENABLE OPA switched on 0b1 REF1_STS Reference 1 Status Register 0x14 32 VREF1V2_UPTHWARN_STS Status for Overvoltage Threshold Measurement of internal VAREF 5 5 read-only UPPER_TRIG_RESET write clears status 0b0 UPPER_TRIG_SET trigger status set 0b1 VREF1V2_LOTHWARN_STS Status for Undervoltage Threshold Measurement of internal VAREF 4 4 read-only UPPER_TRIG_RESET write clears status 0b0 UPPER_TRIG_SET trigger status set 0b1 PMU PMU 0x50004000 0x0 0x1000 registers INTISR14 Interrupt node 14: Wakeup 14 INTISR22 Interrupt node 22: MONx 22 CNF_RST_TFB Reset Blind Time Register 0x06C 32 RST_TFB Reset Pin Blind Time Selection Bits 0 1 read-write RST_TFB_0 0.5 us typ. 0b00 RST_TFB_1 1 us typ. 0b01 RST_TFB_2 5 us typ. 0b10 RST_TFB_3 31 us typ. 0b11 CNF_WAKE_FILTER PMU Wake-up Timing Register 0x0AC 32 CNF_GPIO_FT Wake-up Filter time for General Purpose IO 2 3 read-write 10_us 10 us filter time 0b00 20_us 20 us filter time 0b01 40_us 40 us filter time 0b10 5_us 5 us filter time 0b11 CNF_MON_FT Wake-up Filter time for Monitoring Inputs 1 1 read-write 20_us 20 us filter time 0b0 40_us 40 us filter time 0b1 CNF_LIN_FT Wake-up Filter time for LIN WAKE 0 0 read-write 50_us 50 us filter time 0b0 30_us 30 us filter time 0b1 DRV_CTRL PMU Bridge Driver Control 0x024 32 CNF_OFF CNF_OFF Function 6 7 read-write 400 us 0b00 800 us 0b01 2000 us 0b10 4000 us 0b11 CNF_ON CNF_ON Function 4 5 read-write 50 us 0b00 100 us 0b01 200 us 0b10 400 us 0b11 GL2_HOLD_ON GL2 Hold Mode On 3 3 read-write Disable 0b0 Enable 0b1 GL2_CYC_ON GL2 Cyclic On 2 2 read-write Disable 0b0 Enable 0b1 GL1_HOLD_ON GL1 Hold Mode On 1 1 read-write Disable 0b0 Enable 0b1 GL1_CYC_ON GL1 Cyclic On 0 0 read-write Disable 0b0 Enable 0b1 GPIO_WAKE_STATUS GPIO Port wake status register 0x004 32 GPIO1_STS_4 Wake GPIO1_4 12 12 read-only No wake-up detected 0b0 wake-up detected 0b1 GPIO1_STS_2 Wake GPIO1_2 10 10 read-only No wake-up detected 0b0 wake-up detected 0b1 GPIO1_STS_1 Wake GPIO1_1 9 9 read-only No wake-up detected 0b0 wake-up detected 0b1 GPIO1_STS_0 Wake GPIO1_0 8 8 read-only No wake-up detected 0b0 wake-up detected 0b1 GPIO0_STS_5 Status of GPIO0_5 5 5 read-only No wake-up detected 0b0 wake-up detected 0b1 GPIO0_STS_4 Status of GPIO0_4 4 4 read-only No wake-up detected 0b0 wake-up detected 0b1 GPIO0_STS_3 Status of GPIO0_3 3 3 read-only No wake-up detected 0b0 wake-up detected 0b1 GPIO0_STS_2 Status of GPIO0_2 2 2 read-only No wake-up detected 0b0 wake-up detected 0b1 GPIO0_STS_1 Status of GPIO0_1 1 1 read-only No wake-up detected 0b0 wake-up detected 0b1 GPIO0_STS_0 Status of GPIO0_0 0 0 read-only No wake-up detected 0b0 wake-up detected 0b1 GPUDATA0to3 General Purpose User DATA0to3 0x0C0 32 DATA3 DATA3 Storage Byte 24 31 read-write DATA2 DATA2 Storage Byte 16 23 read-write DATA1 DATA1 Storage Byte 8 15 read-write DATA0 DATA0 Storage Byte 0 7 read-write GPUDATA4to7 General Purpose User DATA4to7 0x0C4 32 DATA7 DATA7 Storage Byte 24 31 read-write DATA6 DATA6 Storage Byte 16 23 read-write DATA5 DATA5 Storage Byte 8 15 read-write DATA4 DATA4 Storage Byte 0 7 read-write GPUDATA8to11 General Purpose User DATA8to11 0x0C8 32 DATA11 DATA11 Storage Byte 24 31 read-write DATA10 DATA10 Storage Byte 16 23 read-write DATA9 DATA9 Storage Byte 8 15 read-write DATA8 DATA8 Storage Byte 0 7 read-write HIGHSIDE_CTRL Highside Control Register 0x05C 32 SPARE Spare 10 10 read-write HS1_CYC_EN High-Side 1 switch enable for cyclic sense 2 2 read-write Disable 0b0 Enable 0b1 LIN_WAKE_EN LIN Wake Enable 0x050 32 LIN_WAKE_EN Lin Wake enable 7 7 read-write Wake Disabled 0b0 Wake enabled 0b1 MON_CNF1 Settings Monitor 0x034 32 MON4_STS MON4 Status Input 31 31 read-only Low MON input has low status 0b0 High MON input has high status 0b1 MON4_NSLEEP_SPARE MON4 Sleep Bit 30 30 read-write Sleep Mode internal MON output forced to 0 0b0 Active Mode internal MON output not forced to 0 0b1 MON4_PU Pull-Up Current Source for MON4 Input Enable 29 29 read-write Disable Pull-up source disabled 0b0 Enable Pull-up source enabled 0b1 MON4_PD Pull-Down Current Source for MON4 Input Enable 28 28 read-write Disable Pull-down source disabled 0b0 Enable Pull-down source enabled 0b1 MON4_CYC MON4 for Cycle Sense Enable 27 27 read-write Disable Cycle Sense disabled 0b0 Enable Cycle Sense enabled 0b1 MON4_RISE MON4 Wake-up on Rising Edge Enable 26 26 read-write Disable Wake-up disabled 0b0 Enable Wake-up enabled 0b1 MON4_FALL MON4 Wake-up on Falling Edge Enable 25 25 read-write Disable Wake-up disabled 0b0 Enable Wake-up enabled 0b1 MON4_EN MON4 Enable 24 24 read-write Disable MON4 disabled 0b0 Enable MON4 enabled 0b1 MON3_STS MON3 Status Input 23 23 read-only Low MON input has low status 0b0 High MON input has high status 0b1 MON3_NSLEEP_SPARE MON3 Sleep Bit 22 22 read-write Sleep Mode internal MON output forced to 0 0b0 Active Mode internal MON output not forced to 0 0b1 MON3_PU Pull-Up Current Source for MON3 Input Enable 21 21 read-write Disable Pull-up source disabled 0b0 Enable Pull-up source enabled 0b1 MON3_PD Pull-Down Current Source for MON3 Input Enable 20 20 read-write Disable Pull-down source disabled 0b0 Enable Pull-down source enabled 0b1 MON3_CYC MON3 for Cycle Sense Enable 19 19 read-write Disable Cycle Sense disabled 0b0 Enable Cycle Sense enabled 0b1 MON3_RISE MON3 Wake-up on Rising Edge Enable 18 18 read-write Disable Wake-up disabled 0b0 Enable Wake-up enabled 0b1 MON3_FALL MON3 Wake-up on Falling Edge Enable 17 17 read-write Disable Wake-up disabled 0b0 Enable Wake-up enabled 0b1 MON3_EN MON3 Enable 16 16 read-write Disable MON3 disabled 0b0 Enable MON3 enabled 0b1 MON2_STS MON2 Status Input 15 15 read-only Low MON input has low status 0b0 High MON input has high status 0b1 MON2_NSLEEP_SPARE MON2 Sleep Bit 14 14 read-write Sleep Mode internal MON output forced to 0 0b0 Active Mode internal MON output not forced to 0 0b1 MON2_PU Pull-Up Current Source for MON2 Input Enable 13 13 read-write Disable Pull-up source disabled 0b0 Enable Pull-up source enabled 0b1 MON2_PD Pull-Down Current Source for MON2 Input Enable 12 12 read-write Disable Pull-down source disabled 0b0 Enable Pull-down source enabled 0b1 MON2_CYC MON2 for Cycle Sense Enable 11 11 read-write Disable Cycle Sense disabled 0b0 Enable Cycle Sense enabled 0b1 MON2_RISE MON2 Wake-up on Rising Edge Enable 10 10 read-write Disable Wake-up disabled 0b0 Enable Wake-up enabled 0b1 MON2_FALL MON2 Wake-up on Falling Edge Enable 9 9 read-write Disable Wake-up disabled 0b0 Enable Wake-up enabled 0b1 MON2_EN MON2 Enable 8 8 read-write Disable MON2 disabled 0b0 Enable MON2 enabled 0b1 MON1_STS MON1 Status Input 7 7 read-only Low MON input has low status 0b0 High MON input has high status 0b1 MON1_NSLEEP_SPARE MON1 Sleep Bit 6 6 read-write Sleep Mode internal MON output forced to 0 0b0 Active Mode internal MON output not forced to 0 0b1 MON1_PU Pull-Up Current Source for MON1 Input Enable 5 5 read-write Disable Pull-up source disabled 0b0 Enable Pull-up source enabled 0b1 MON1_PD Pull-Down Current Source for MON1 Input Enable 4 4 read-write Disable Pull-down source disabled 0b0 Enable Pull-down source enabled 0b1 MON1_CYC MON1 for Cycle Sense Enable 3 3 read-write Disable Cycle Sense disabled 0b0 Enable Cycle Sense enabled 0b1 MON1_RISE MON1 Wake-up on Rising Edge Enable 2 2 read-write Disable Wake-up disabled 0b0 Enable Wake-up enabled 0b1 MON1_FALL MON1 Wake-up on Falling Edge Enable 1 1 read-write Disable Wake-up disabled 0b0 Enable Wake-up enabled 0b1 MON1_EN MON1 Enable 0 0 read-write Disable MON1 disabled 0b0 Enable MON1 enabled 0b1 MON_CNF2 Settings Monitor 0x038 32 MON5_STS MON5 Status Input 7 7 read-only Low MON input has low status 0b0 High MON input has high status 0b1 MON5_NSLEEP_SPARE MON5 Sleep Bit 6 6 read-write Sleep Mode internal MON output forced to 0 0b0 Active Mode internal MON output not forced to 0 0b1 MON5_PU Pull-Up Current Source for MON5 Input Enable 5 5 read-write Disable Pull-up source disabled 0b0 Enable Pull-up source enabled 0b1 MON5_PD Pull-Down Current Source for MON5 Input Enable 4 4 read-write Disable Pull-down source disabled 0b0 Enable Pull-down source enabled 0b1 MON5_CYC MON5 for Cycle Sense Enable 3 3 read-write Disable Cycle Sense disabled 0b0 Enable Cycle Sense enabled 0b1 MON5_RISE MON5 Wake-up on Rising Edge Enable 2 2 read-write Disable Wake-up disabled 0b0 Enable Wake-up enabled 0b1 MON5_FALL MON5 Wake-up on Falling Edge Enable 1 1 read-write Disable Wake-up disabled 0b0 Enable Wake-up enabled 0b1 MON5_EN MON5 Enable 0 0 read-write Disable MON5 disabled 0b0 Enable MON5 enabled 0b1 OT_CTRL Overtemperature Control Register 0x054 32 PMU_OT_EN PMU Overtemperature Detection Enable 7 7 read-write Disable Overtemperature detection disabled 0b0 Enable Overtemperature detection enabled 0b1 PMU_OT_WAKE_EN PMU Wake On Overtemperature Enable 6 6 read-write Disable no Wake-Up on OT condition 0b0 Enable Wake-Up on OT condition 0b1 PMU_OT_INT_EN PMU Overtemperature Interrupt Enable 5 5 read-write No Interrupt Interrupt on OT disabled 0b0 Interrupt Interrupt on OT enabled 0b1 PMU_OT_TH_CNF PMU Overtemperature threshold 0 3 read-write 0 131 degree C 0b0000 1 136 degree C 0b0001 2 141 degree C 0b0010 3 146 degree C 0b0011 4 152 degree C 0b0100 5 157 degree C 0b0101 6 163 degree C 0b0110 7 169 degree C 0b0111 8 175 degree C 0b1000 9 181 degree C 0b1001 10 187 degree C 0b1010 11 193 degree C 0b1011 12 200 degree C 0b1100 13 206 degree C 0b1101 14 214 degree C 0b1110 15 221 degree C 0b1111 PORCFG POR Reset Configuration Register 0x0B4 32 CNF_FILT Configuration for reset filter 0 1 read-write RESET_STS Reset Status Register 0x010 32 LOCKUP Lockup-Reset Flag 10 10 read-write No Reset No Lockup-Reset executed 0b0 Reset Lockup-Reset executed 0b1 PMU_SOFT Soft-Reset Flag 9 9 read-write No Reset No Soft-Reset executed 0b0 Reset Soft-Reset executed 0b1 PMU_IntWDT Internal Watchdog Reset Flag 8 8 read-write No Reset No Internal Watchdog reset executed 0b0 Reset Internal Watchdog reset executed 0b1 PMU_VS_POR Power-On Reset Flag 7 7 read-write No Reset No Power-On reset executed 0b0 Reset Power-On reset executed 0b1 PMU_PIN PIN-Reset Flag 6 6 read-write No Reset No PIN-Reset executed 0b0 Reset PIN-Reset executed 0b1 PMU_ExtWDT External Watchdog (WDT1) Reset Flag 5 5 read-write No Reset No External Watchdog reset executed 0b0 Reset External Watchdog reset executed 0b1 PMU_ClkWDT Clock Watchdog (CLKWDT) Reset Flag 4 4 read-write No Reset No Clock Watchdog reset executed 0b0 Reset Clock Watchdog reset executed 0b1 PMU_LPR Low Priority Resets (see PMU_RST_STS2) 3 3 read-write No Reset No Low Priority reset executed 0b0 Reset Low Priority reset executed 0b1 PMU_SleepEX Flag which indicates a reset caused by Sleep-Exit 2 2 read-write No Reset No reset caused by Sleep-Exit executed 0b0 Reset Reset caused by Sleep-Exit executed 0b1 PMU_WAKE Flag which indicates a reset caused by Stop-Exit 1 1 read-write No Reset No reset caused by Stop-Exit executed 0b0 Reset Reset caused by Stop-Exit executed 0b1 SYS_FAIL Flag which indicates a reset caused by a System Fail reported in the corresponding Fail Register 0 0 read-write No Reset No reset caused by System Fail executed 0b0 Reset Reset caused by System Fail executed 0b1 SLEEP PMU Sleep Behavior Register 0x020 32 CYC_SENSE_S_DEL Sample Delay in Cyclic Sense 24 26 read-write 0 10 us typ. 0b000 1 20 us typ. 0b001 2 30 us typ. 0b010 3 40 us typ. 0b011 4 60 us typ. 0b100 5 80 us typ. 0b101 6 100 us typ. 0b110 7 150 us typ. 0b111 CYC_WAKE_E01 Exponent 20 21 read-write 0 Exponent value is 0 0b00 1 Exponent value is 1 0b01 2 Exponent value is 2 0b10 3 Exponent value is 3 0b11 CYC_WAKE_M03 Mantissa 16 19 read-write 1 Mantissa value is 1 0b0000 16 Mantissa value is 16 0b1111 CYC_SENSE_E01 Exponent 12 13 read-write 0 Exponent value is 0 0b00 1 Exponent value is 1 0b01 2 Exponent value is 2 0b10 3 Exponent value is 3 0b11 CYC_SENSE_M03 Mantissa 8 11 read-write 1 Mantissa value is 1 0b0000 16 Mantissa value is 16 0b1111 CYC_SENSE_EN Enabling Cyclic Sense 3 3 read-write Disable Cyclic Sense disabled 0b0 Enable Cyclic Sense enabled 0b1 CYC_WAKE_EN Enabling Cyclic Wake 2 2 read-write Disable Cyclic Wake disabled 0b0 Enable Cyclic Wake enabled 0b1 EN_0V9_N Enables the reduction of the VDDC regulator output to 0.9 V during Stop-Mode 1 1 read-write Enable Output voltage reduction enabled 0b0 Disable Output voltage reduction disabled 0b1 WAKE_W_RST Wake-up with reset execution 0 0 read-write No Reset Stop-Exit without reset execution 0b0 Reset Stop-Exit with reset execution 0b1 SUPPLY_STS Voltage Reg Status Register 0x008 32 PMU_5V_OVERLOAD_SC Overload at VDDP regulator Status clear 13 13 write-only No Clear Overload status not cleared 0b0 Clear Overload status cleared 0b1 PMU_5V_OVERVOLT_SC Overvoltage at VDDP regulator Status clear 12 12 write-only No Clear Overvoltage status not cleared 0b0 Clear Overvoltage status cleared 0b1 PMU_OVERTEMP_SC Overtemperature Status clear 11 11 write-only No Clear Overtemperature status not cleared 0b0 Clear Overtemperature status cleared 0b1 PMU_1V5_OVERLOAD_SC Overload at VDDC regulator Status clear 9 9 write-only No Clear Overload status not cleared 0b0 Clear Overload status cleared 0b1 PMU_1V5_OVERVOLT_SC Overvoltage at VDDC regulator Status clear 8 8 write-only No Clear Overvoltage status not cleared 0b0 Clear Overvoltage status cleared 0b1 PMU_5V_FAIL_EN Enabling of VDDP status information as interrupt source 6 6 read-write Disable No interrupts are generated 0b0 Enable Interrupts are generated 0b1 PMU_5V_OVERLOAD Overload at VDDP regulator 5 5 read-only No overload 0b0 Overload 0b1 PMU_5V_OVERVOLT Overvoltage at VDDP regulator 4 4 read-only No overvoltage 0b0 Overvoltage 0b1 PMU_OVERTEMP PMU Overtemperature 3 3 read-only No overtemperature 0b0 Overtemperature 0b1 PMU_1V5_FAIL_EN Enabling of VDDC status information as interrupt source 2 2 read-write Disable No interrupts are generated 0b0 Enable Interrupts are generated 0b1 PMU_1V5_OVERLOAD Overload at VDDC regulator 1 1 read-only No overload 0b0 Overload 0b1 PMU_1V5_OVERVOLT Overvoltage at VDDC regulator 0 0 read-only No overvoltage 0b0 Overvoltage 0b1 VDDEXT_CTRL VDDEXT Control 0x00C 32 VDDEXT_OT_SC VDDEXT Supply Overtemperature Status clear 13 13 write-only No Clear VDDEXT Overtemperature status not cleared 0b1 Clear VDDEXT Overtemperature status cleared 0b0 VDDEXT_UV_ISC VDDEXT Supply Undervoltage Interrupt Status clear 12 12 write-only No Clear VDDEXT Undervoltage not cleared 0b1 Clear VDDEXT Undervoltage cleared 0b0 VDDEXT_OT_ISC VDDEXT Supply Overtemperature Interrupt Status clear 11 11 write-only No Clear VDDEXT OverTemperature not cleared 0b1 Clear VDDEXT OverTemperature cleared 0b0 VDDEXT_STABLE VDDEXT Supply Stable 7 7 read-only VDDEXT not in stable condition 0b0 VDDEXT in stable condition 0b1 VDDEXT_OT VDDEXT Supply Overtemperature 6 6 read-only VDDEXT not in overtemperature condition 0b0 VDDEXT in overtemperature condition 0b1 VDDEXT_OT_STS VDDEXT Supply Overtemperature Status 5 5 read-only VDDEXT not in overtemperature condition 0b0 VDDEXT in overtemperature condition 0b1 VDDEXT_UV_IS VDDEXT Supply Undervoltage Interrupt Status 4 4 read-only VDDEXT not in undervoltage condition 0b0 VDDEXT in undervoltage condition 0b1 VDDEXT_OT_IS VDDEXT Supply OverTemperature Interrupt Status 3 3 read-only VDDEXT no overtemperature condition 0b0 VDDEXT overtemperature condition 0b1 VDDEXT_FAIL_EN Enabling of VDDEXT Supply status information as interrupt source 2 2 read-write Disable VDDEXT fail interrupts are disable 0b0 Enable VDDEXT fail Interrupts are enable 0b1 VDDEXT_CYC_EN VDDEXT Supply for Cyclic Sense Enable 1 1 read-write Disable VDDEXT for cyclic sense disable 0b0 Enable VDDEXT for cyclic sense enable 0b1 VDDEXT_ENABLE VDDEXT Supply Enable 0 0 read-write Disable VDDEXT Supply disable 0b0 Enable VDDEXT supply enable 0b1 WAKE_CNF_GPIO0 Wake Configuration GPIO Port 0 Register 0x0BC 32 CYC_5 GPIO0_5 input for cycle sense enable 21 21 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 CYC_4 GPIO0_4 input for cycle sense enable 20 20 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 CYC_3 GPIO0_3 input for cycle sense enable 19 19 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 CYC_2 GPIO0_2 input for cycle sense enable 18 18 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 CYC_1 GPIO0_1 input for cycle sense enable 17 17 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 CYC_0 GPIO0_0 input for cycle sense enable 16 16 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 FA_5 Port 0_5 Wake-up on Falling Edge enable 13 13 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 FA_4 Port 0_4 Wake-up on Falling Edge enable 12 12 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 FA_3 Port 0_3 Wake-up on Falling Edge enable 11 11 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 FA_2 Port 0_2 Wake-up on Falling Edge enable 10 10 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 FA_1 Port 0_1 Wake-up on Falling Edge enable 9 9 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 FA_0 Port 0_0 Wake-up on Falling Edge enable 8 8 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 RI_5 Port 0_5 Wake-up on Rising Edge enable 5 5 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 RI_4 Port 0_4 Wake-up on Rising Edge enable 4 4 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 RI_3 Port 0_3 Wake-up on Rising Edge enable 3 3 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 RI_2 Port 0_2 Wake-up on Rising Edge enable 2 2 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 RI_1 Port 0_1 Wake-up on Rising Edge enable 1 1 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 RI_0 Port 0_0 Wake-up on Rising Edge enable 0 0 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 WAKE_CNF_GPIO1 Wake Configuration GPIO Port 1 Register 0x0CC 32 CYC_4 GPIO1_4 input for cycle sense enable 20 20 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 CYC_2 GPIO1_2 input for cycle sense enable 18 18 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 CYC_1 GPIO1_1 input for cycle sense enable 17 17 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 CYC_0 GPIO1_0 input for cycle sense enable 16 16 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 FA_4 Port 1_4 Wake-up on Falling Edge enable 12 12 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 FA_2 Port 1_2 Wake-up on Falling Edge enable 10 10 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 FA_1 Port 1_1 Wake-up on Falling Edge enable 9 9 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 FA_0 Port 1_0 Wake-up on Falling Edge enable 8 8 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 RI_4 Port 1_4 Wake-up on Rising Edge enable 4 4 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 RI_2 Port 1_2 Wake-up on Rising Edge enable 2 2 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 RI_1 Port 1_1 Wake-up on Rising Edge enable 1 1 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 RI_0 Port 1_0 Wake-up on Rising Edge enable 0 0 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 WAKE_STATUS Main wake status register 0x000 32 VDDEXT_UV Wake VDDEXT Undervoltage 18 18 read-only No wake-up detected 0b0 wake-up detected 0b1 VDDEXT_OT Wake VDDEXT Overtemperature 17 17 read-only No wake-up detected 0b0 wake-up detected 0b1 PMU_OT Wake PMU Overtemperature 16 16 read-only No wake-up detected 0b0 wake-up detected 0b1 MON5_WAKE_STS Status of MON5 12 12 read-only No wake-up detected 0b0 wake-up detected 0b1 MON4_WAKE_STS Status of MON4 11 11 read-only No wake-up detected 0b0 wake-up detected 0b1 MON3_WAKE_STS Status of MON3 10 10 read-only No wake-up detected 0b0 wake-up detected 0b1 MON2_WAKE_STS Status of MON2 9 9 read-only No wake-up detected 0b0 wake-up detected 0b1 MON1_WAKE_STS Status of MON1 8 8 read-only No wake-up detected 0b0 wake-up detected 0b1 GPIO2 Wake-up via GPIO2 which is a logical OR combination of all Wake_STS_GPIO2 bits 6 6 read-only No Wake-up occurred 0b0 Wake-up occurred 0b1 FAIL Wake-up after any Fail, which is a logical OR combination of PMU_OT, VDDEXT_OT, VDDEXT_UV 5 5 read-only No Wake-up occurred 0b0 Wake-up occurred 0b1 CYC_WAKE Wake-up caused by Cyclic Wake 4 4 read-only No Wake-up occurred 0b0 Wake-up occurred 0b1 GPIO1 Wake-up via GPIO1 which is a logical OR combination of all Wake_STS_GPIO1 bits 3 3 read-only No Wake-up occurred 0b0 Wake-up occurred 0b1 GPIO0 Wake-up via GPIO0 which is a logical OR combination of all Wake_STS_GPIO0 bits 2 2 read-only No Wake-up occurred 0b0 Wake-up occurred 0b1 MON Wake-up via MON which is a logical OR combination of all Wake_STS_MON bits 1 1 read-only No Wake-up occurred 0b0 Wake-up occurred 0b1 LIN_WAKE Wake-up via LIN- Message 0 0 read-only No Wake-up occurred 0b0 Wake-up occurred 0b1 WFS WFS System Fail Register 0x070 32 PMU_OT_FAIL PMU Overtemperature Indication Flag 8 8 read-only No Overtemperature PMU ok 0b0 Overtemperature PMU Overtemperature 0b1 LP_CLKWD LP_CLKWD 7 7 read-only ok 0b0 fail 0b1 WDT1_SEQ_FAIL External Watchdog (WDT1) Sequential Fail 6 6 read-only No Fail System working properly 0b0 Sequential Watchdog Fail 5 consecutive watchdog fails 0b1 SYS_OT System Overtemperature Indication Flag 5 5 read-only No Overtemperature System ok 0b0 Overtemperature System Overtemperature 0b1 SYS_CLK_WDT System Clock (fsys)Watchdog Fail 4 4 read-only No System Clock Fail fsys ok 0b0 System Clock Fail fsys failed 0b1 PMU_5V_OVL VDDP Overload Flag 3 3 read-only No Overload VDDP ok 0b0 Overload VDDP Overload 0b1 PMU_1V5_OVL VDDC Overload Flag 2 2 read-only No Overload VDDC ok 0b0 Overload Hall VDDC Overload 0b1 SUPP_TMOUT Supply Time Out 1 1 read-only Main Supply ok VDDP or VDDC are in expected range 0b0 Main Supply fail VDDP or VDDC do not have stable operating point 0b1 SUPP_SHORT Supply Short 0 0 read-only Main Supply ok VDDP or VDDC are in expected range 0b0 Main Supply short VDDP or VDDC are in short circuit condition 0b1 PORT PORT 0x48028000 0x0 0x2000 registers INTISR23 Interrupt node 23: Port 2.x (ADC1) 23 P0_ALTSEL0 Port 0 Alternate Select Register 0 0x14 32 PP5 See 5 5 read-write PP4 See 4 4 read-write PP3 See 3 3 read-write PP2 See 2 2 read-write PP1 See 1 1 read-write PP0 See 0 0 read-write P0_ALTSEL1 Port 0 Alternate Select Register 1 0x18 32 PP5 See 5 5 read-write PP4 See 4 4 read-write PP3 See 3 3 read-write PP2 See 2 2 read-write PP1 See 1 1 read-write PP0 See 0 0 read-write P0_DATA Port 0 Data Register 0x00 32 PP5_STS Port 0 Pin 5 Data Value (read back of Port Data when IO is configured as output) 21 21 read-only 0 Port 0 pin 5 data value = 0 0b0 1 Port 0 pin 5 data value = 1 0b1 PP4_STS Port 0 Pin 4 Data Value (read back of Port Data when IO is configured as output) 20 20 read-only 0 Port 0 pin 4 data value = 0 0b0 1 Port 0 pin 4 data value = 1 0b1 PP3_STS Port 0 Pin 3 Data Value (read back of Port Data when IO is configured as output) 19 19 read-only 0 Port 0 pin 3 data value = 0 0b0 1 Port 0 pin 3 data value = 1 0b1 PP2_STS Port 0 Pin 2 Data Value (read back of Port Data when IO is configured as output) 18 18 read-only 0 Port 0 pin 2 data value = 0 0b0 1 Port 0 pin 2 data value = 1 0b1 PP1_STS Port 0 Pin 1 Data Value (read back of Port Data when IO is configured as output) 17 17 read-only 0 Port 0 pin 1 data value = 0 0b0 1 Port 0 pin 1 data value = 1 0b1 PP0_STS Port 0 Pin 0 Data Value (read back of Port Data when IO is configured as output) 16 16 read-only 0 Port 0 pin 0 data value = 0 0b0 1 Port 0 pin 0 data value = 1 0b1 PP5 Port 0 Pin 5 Data Value 5 5 read-write 0 Port 0 pin 5 data value = 0 0b0 1 Port 0 pin 5 data value = 1 0b1 PP4 Port 0 Pin 4 Data Value 4 4 read-write 0 Port 0 pin 4 data value = 0 0b0 1 Port 0 pin 4 data value = 1 0b1 PP3 Port 0 Pin 3 Data Value 3 3 read-write 0 Port 0 pin 3 data value = 0 0b0 1 Port 0 pin 3 data value = 1 0b1 PP2 Port 0 Pin 2 Data Value 2 2 read-write 0 Port 0 pin 2 data value = 0 0b0 1 Port 0 pin 2 data value = 1 0b1 PP1 Port 0 Pin 1 Data Value 1 1 read-write 0 Port 0 pin 1 data value = 0 0b0 1 Port 0 pin 1 data value = 1 0b1 PP0 Port 0 Pin 0 Data Value 0 0 read-write 0 Port 0 pin 0 data value = 0 0b0 1 Port 0 pin 0 data value = 1 0b1 P0_DIR Port 0 Direction Register 0x04 32 PP5_INEN Port 0 Pin 5 Input Schmitt Trigger enable (only valid if IO is configured as output) 21 21 read-write 0 Schmitt Trigger is disabled 0b0 1 Schmitt Trigger is enabled 0b1 PP4_INEN Port 0 Pin 4 Input Schmitt Trigger enable (only valid if IO is configured as output) 20 20 read-write 0 Schmitt Trigger is disabled 0b0 1 Schmitt Trigger is enabled 0b1 PP3_INEN Port 0 Pin 3 Input Schmitt Trigger enable (only valid if IO is configured as output) 19 19 read-write 0 Schmitt Trigger is disabled 0b0 1 Schmitt Trigger is enabled 0b1 PP2_INEN Port 0 Pin 2 Input Schmitt Trigger enable (only valid if IO is configured as output) 18 18 read-write 0 Schmitt Trigger is disabled 0b0 1 Schmitt Trigger is enabled 0b1 PP1_INEN Port 0 Pin 1 Input Schmitt Trigger enable (only valid if IO is configured as output) 17 17 read-write 0 Schmitt Trigger is disabled 0b0 1 Schmitt Trigger is enabled 0b1 PP0_INEN Port 0 Pin 0 Input Schmitt Trigger enable (only valid if IO is configured as output) 16 16 read-write 0 Schmitt Trigger is disabled 0b0 1 Schmitt Trigger is enabled 0b1 PP5 Port 0 Pin 5 Direction Control 5 5 read-write 0 Direction is set to input 0b0 1 Direction is set to output 0b1 PP4 Port 0 Pin 4 Direction Control 4 4 read-write 0 Direction is set to input 0b0 1 Direction is set to output 0b1 PP3 Port 0 Pin 3 Direction Control 3 3 read-write 0 Direction is set to input 0b0 1 Direction is set to output 0b1 PP2 Port 0 Pin 2 Direction Control 2 2 read-write 0 Direction is set to input 0b0 1 Direction is set to output 0b1 PP1 Port 0 Pin 1 Direction Control 1 1 read-write 0 Direction is set to input 0b0 1 Direction is set to output 0b1 PP0 Port 0 Pin 0 Direction Control 0 0 read-write 0 Direction is set to input 0b0 1 Direction is set to output 0b1 P0_OD Port 0 Open Drain Control Register 0x08 32 PP5 Port 0 Pin 5 Open Drain Mode 5 5 read-write Normal Mode Output is actively driven for 0 and 1 state 0b0 Open Drain Mode Output is actively driven only for 0 state 0b1 PP4 Port 0 Pin 4 Open Drain Mode 4 4 read-write Normal Mode Output is actively driven for 0 and 1 state 0b0 Open Drain Mode Output is actively driven only for 0 state 0b1 PP3 Port 0 Pin 3 Open Drain Mode 3 3 read-write Normal Mode Output is actively driven for 0 and 1 state 0b0 Open Drain Mode Output is actively driven only for 0 state 0b1 PP2 Port 0 Pin 2 Open Drain Mode 2 2 read-write Normal Mode Output is actively driven for 0 and 1 state 0b0 Open Drain Mode Output is actively driven only for 0 state 0b1 PP1 Port 0 Pin 1 Open Drain Mode 1 1 read-write Normal Mode Output is actively driven for 0 and 1 state 0b0 Open Drain Mode Output is actively driven only for 0 state 0b1 PP0 Port 0 Pin 0 Open Drain Mode 0 0 read-write Normal Mode Output is actively driven for 0 and 1 state 0b0 Open Drain Mode Output is actively driven only for 0 state 0b1 P0_PUDEN Port 0 Pull-Up/Pull-Down Enable Register 0x10 32 PP5 Pull-Up/Pull-Down Enable at Port 0 Bit 5 5 5 read-write Disabled Pull-up or Pull-down device is disabled 0b0 Enabled Pull-up or Pull-down device is enabled 0b1 PP4 Pull-Up/Pull-Down Enable at Port 0 Bit 4 4 4 read-write Disabled Pull-up or Pull-down device is disabled 0b0 Enabled Pull-up or Pull-down device is enabled 0b1 PP3 Pull-Up/Pull-Down Enable at Port 0 Bit 3 3 3 read-write Disabled Pull-up or Pull-down device is disabled 0b0 Enabled Pull-up or Pull-down device is enabled 0b1 PP2 Pull-Up/Pull-Down Enable at Port 0 Bit 2 2 2 read-write Disabled Pull-up or Pull-down device is disabled 0b0 Enabled Pull-up or Pull-down device is enabled 0b1 PP1 Pull-Up/Pull-Down Enable at Port 0 Bit 1 1 1 read-write Disabled Pull-up or Pull-down device is disabled 0b0 Enabled Pull-up or Pull-down device is enabled 0b1 PP0 Pull-Up/Pull-Down Enable at Port 0 Bit 0 0 0 read-write Disabled Pull-up or Pull-down device is disabled 0b0 Enabled Pull-up or Pull-down device is enabled 0b1 P0_PUDSEL Port 0 Pull-Up/Pull-Down Select Register 0x0C 32 PP5 Pull-Up/Pull-Down Select Port 0 Bit 5 5 5 read-write Pull-down Pull-down device is selected 0b0 Pull-up Pull-up device is selected 0b1 PP4 Pull-Up/Pull-Down Select Port 0 Bit 4 4 4 read-write Pull-down Pull-down device is selected 0b0 Pull-up Pull-up device is selected 0b1 PP3 Pull-Up/Pull-Down Select Port 0 Bit 3 3 3 read-write Pull-down Pull-down device is selected 0b0 Pull-up Pull-up device is selected 0b1 PP2 Pull-Up/Pull-Down Select Port 0 Bit 2 2 2 read-write Pull-down Pull-down device is selected 0b0 Pull-up Pull-up device is selected 0b1 PP1 Pull-Up/Pull-Down Select Port 0 Bit 1 1 1 read-write Pull-down Pull-down device is selected 0b0 Pull-up Pull-up device is selected 0b1 PP0 Pull-Up/Pull-Down Select Port 0 Bit 0 0 0 read-write Pull-down Pull-down device is selected 0b0 Pull-up Pull-up device is selected 0b1 P1_ALTSEL0 Port 1 Alternate Select Register 0 0x34 32 PP4 See 4 4 read-write PP2 See 2 2 read-write PP1 See 1 1 read-write PP0 See 0 0 read-write P1_ALTSEL1 Port 1 Alternate Select Register 1 0x38 32 PP4 See 4 4 read-write PP2 See 2 2 read-write PP1 See 1 1 read-write PP0 See 0 0 read-write P1_DATA Port 1 Data Register 0x20 32 PP4_STS Port 1 Pin 4 Data Value (read back of Port Data when IO is configured as output) 20 20 read-only 0 Port 0 pin 4 data value = 0 0b0 1 Port 0 pin 4 data value = 1 0b1 PP2_STS Port 1 Pin 2 Data Value (read back of Port Data when IO is configured as output) 18 18 read-only 0 Port 0 pin 2 data value = 0 0b0 1 Port 0 pin 2 data value = 1 0b1 PP1_STS Port 1 Pin 1 Data Value (read back of Port Data when IO is configured as output) 17 17 read-only 0 Port 0 pin 1 data value = 0 0b0 1 Port 0 pin 1 data value = 1 0b1 PP0_STS Port 1 Pin 0 Data Value (read back of Port Data when IO is configured as output) 16 16 read-only 0 Port 0 pin 0 data value = 0 0b0 1 Port 0 pin 0 data value = 1 0b1 PP4 Port 1 Pin 4 Data Value 4 4 read-write 0 Port 0 pin 4 data value = 0 0b0 1 Port 0 pin 4 data value = 1 0b1 PP2 Port 1 Pin 2 Data Value 2 2 read-write 0 Port 0 pin 2 data value = 0 0b0 1 Port 0 pin 2 data value = 1 0b1 PP1 Port 1 Pin 1 Data Value 1 1 read-write 0 Port 0 pin 1 data value = 0 0b0 1 Port 0 pin 1 data value = 1 0b1 PP0 Port 1 Pin 0 Data Value 0 0 read-write 0 Port 0 pin 0 data value = 0 0b0 1 Port 0 pin 0 data value = 1 0b1 P1_DIR Port 1 Direction Register 0x24 32 PP4_INEN Port 1 Pin 4 Input Schmitt Trigger enable (only valid if IO is configured as output) 20 20 read-write 0 Schmitt Trigger is disabled 0b0 1 Schmitt Trigger is enabled 0b1 PP2_INEN Port 1 Pin 2 Input Schmitt Trigger enable (only valid if IO is configured as output) 18 18 read-write 0 Schmitt Trigger is disabled 0b0 1 Schmitt Trigger is enabled 0b1 PP1_INEN Port 1 Pin 1 Input Schmitt Trigger enable (only valid if IO is configured as output) 17 17 read-write 0 Schmitt Trigger is disabled 0b0 1 Schmitt Trigger is enabled 0b1 PP0_INEN Port 1 Pin 0 Input Schmitt Trigger enable (only valid if IO is configured as output) 16 16 read-write 0 Schmitt Trigger is disabled 0b0 1 Schmitt Trigger is enabled 0b1 PP4 Port 1 Pin 4 Direction Control 4 4 read-write Input Direction is set to input 0b0 Output Direction is set to output 0b1 PP2 Port 1 Pin 2 Direction Control 2 2 read-write Input Direction is set to input 0b0 Output Direction is set to output 0b1 PP1 Port 1 Pin 1 Direction Control 1 1 read-write Input Direction is set to input 0b0 Output Direction is set to output 0b1 PP0 Port 1 Pin 0 Direction Control 0 0 read-write Input Direction is set to input 0b0 Output Direction is set to output 0b1 P1_OD Port 1 Open Drain Control Register 0x28 32 PP4 Port 1 Pin 4 Open Drain Mode 4 4 read-write Normal Mode Output is actively driven for 0 and 1 state 0b0 Open Drain Mode Output is actively driven only for 0 state 0b1 PP2 Port 1 Pin 2 Open Drain Mode 2 2 read-write Normal Mode Output is actively driven for 0 and 1 state 0b0 Open Drain Mode Output is actively driven only for 0 state 0b1 PP1 Port 1 Pin 1 Open Drain Mode 1 1 read-write Normal Mode Output is actively driven for 0 and 1 state 0b0 Open Drain Mode Output is actively driven only for 0 state 0b1 PP0 Port 1 Pin 0 Open Drain Mode 0 0 read-write Normal Mode Output is actively driven for 0 and 1 state 0b0 Open Drain Mode Output is actively driven only for 0 state 0b1 P1_PUDEN Port 1 Pull-Up/Pull-Down Enable Register 0x30 32 PP4 Pull-Up/Pull-Down Enable at Port 1 Bit 4 4 4 read-write Disabled Pull-up or Pull-down device is disabled 0b0 Enabled Pull-up or Pull-down device is enabled 0b1 PP2 Pull-Up/Pull-Down Enable at Port 1 Bit 2 2 2 read-write Disabled Pull-up or Pull-down device is disabled 0b0 Enabled Pull-up or Pull-down device is enabled 0b1 PP1 Pull-Up/Pull-Down Enable at Port 1 Bit 1 1 1 read-write Disabled Pull-up or Pull-down device is disabled 0b0 Enabled Pull-up or Pull-down device is enabled 0b1 PP0 Pull-Up/Pull-Down Enable at Port 1 Bit 0 0 0 read-write Disabled Pull-up or Pull-down device is disabled 0b0 Enabled Pull-up or Pull-down device is enabled 0b1 P1_PUDSEL Port 1 Pull-Up/Pull-Down Select Register 0x2C 32 PP4 Pull-Up/Pull-Down Select Port 1 Bit 4 4 4 read-write Pull-down Pull-down device is selected 0b0 Pull-up Pull-up device is selected 0b1 PP2 Pull-Up/Pull-Down Select Port 1 Bit 2 2 2 read-write Pull-down Pull-down device is selected 0b0 Pull-up Pull-up device is selected 0b1 PP1 Pull-Up/Pull-Down Select Port 1 Bit 1 1 1 read-write Pull-down Pull-down device is selected 0b0 Pull-up Pull-up device is selected 0b1 PP0 Pull-Up/Pull-Down Select Port 1 Bit 0 0 0 read-write Pull-down Pull-down device is selected 0b0 Pull-up Pull-up device is selected 0b1 P2_DATA Port 2 Data Register 0x40 32 PP7 Port 2 Pin 7 Data Value 7 7 read-write 0 Port 2 pin 7 data value = 0 0b0 1 Port 2 pin 7 data value = 1 0b1 PP3 Port 2 Pin 3 Data Value 3 3 read-write 0 Port 2 pin 3 data value = 0 0b0 1 Port 2 pin 3 data value = 1 0b1 PP2 Port 2 Pin 2 Data Value 2 2 read-write 0 Port 2 pin 2 data value = 0 0b0 1 Port 2 pin 2 data value = 1 0b1 PP1 Port 2 Pin 1 Data Value 1 1 read-write 0 Port 2 pin 1 data value = 0 0b0 1 Port 2 pin 1 data value = 1 0b1 PP0 Port 2 Pin 0 Data Value 0 0 read-write 0 Port 2 pin 0 data value = 0 0b0 1 Port 2 pin 0 data value = 1 0b1 P2_DIR Port 2 Direction Register 0x44 32 PP7 Port 2 Pin 7 Driver Control 7 7 read-write Enabled Input driver is enabled 0b0 Disabled Input driver is disabled 0b1 PP3 Port 2 Pin 3 Driver Control 3 3 read-write Enabled Input driver is enabled 0b0 Disabled Input driver is disabled 0b1 PP2 Port 2 Pin 2 Driver Control 2 2 read-write Enabled Input driver is enabled 0b0 Disabled Input driver is disabled 0b1 PP1 Port 2 Pin 1 Driver Control 1 1 read-write Enabled Input driver is enabled 0b0 Disabled Input driver is disabled 0b1 PP0 Port 2 Pin 0 Driver Control 0 0 read-write Enabled Input driver is enabled 0b0 Disabled Input driver is disabled 0b1 P2_PUDEN Port 2 Pull-Up/Pull-Down Enable Register 0x50 32 PP7 Pull-Up/Pull-Down Enable at Port 2 Bit 7 7 7 read-write Disabled Pull-up or Pull-down device is disabled 0b0 Enabled Pull-up or Pull-down device is enabled 0b1 PP3 Pull-Up/Pull-Down Enable at Port 2 Bit 3 3 3 read-write Disabled Pull-up or Pull-down device is disabled 0b0 Enabled Pull-up or Pull-down device is enabled 0b1 PP2 Pull-Up/Pull-Down Enable at Port 2 Bit 2 2 2 read-write Disabled Pull-up or Pull-down device is disabled 0b0 Enabled Pull-up or Pull-down device is enabled 0b1 PP1 Pull-Up/Pull-Down Enable at Port 2 Bit 1 1 1 read-write Disabled Pull-up or Pull-down device is disabled 0b0 Enabled Pull-up or Pull-down device is enabled 0b1 PP0 Pull-Up/Pull-Down Enable at Port 2 Bit 0 0 0 read-write Disabled Pull-up or Pull-down device is disabled 0b0 Enabled Pull-up or Pull-down device is enabled 0b1 P2_PUDSEL Port 2 Pull-Up/Pull-Down Select Register 0x4C 32 PP7 Pull-Up/Pull-Down Select Port 2 Bit 7 7 7 read-write Pull-down Pull-down device is selected 0b0 Pull-up Pull-up device is selected 0b1 PP3 Pull-Up/Pull-Down Select Port 2 Bit 3 3 3 read-write Pull-down Pull-down device is selected 0b0 Pull-up Pull-up device is selected 0b1 PP2 Pull-Up/Pull-Down Select Port 2 Bit 2 2 2 read-write Pull-down Pull-down device is selected 0b0 Pull-up Pull-up device is selected 0b1 PP1 Pull-Up/Pull-Down Select Port 2 Bit 1 1 1 read-write Pull-down Pull-down device is selected 0b0 Pull-up Pull-up device is selected 0b1 PP0 Pull-Up/Pull-Down Select Port 2 Bit 0 0 0 read-write Pull-down Pull-down device is selected 0b0 Pull-up Pull-up device is selected 0b1 SCU SCU 0x50005000 0x0 0x1000 registers INTISR12 Interrupt node 12: EINT0 12 INTISR13 Interrupt node 13: EINT1 13 ADC1_CLK ADC1 Peripheral Clock Register 0x06C 32 DPP1_CLK_DIV ADC1 Post processing clock divider 8 9 read-write div 1 Divide by 1 0b00 div 2 Divide by 2 0b01 div 3 Divide by 3 0b10 div 4 Divide by 4 0b11 ADC1_CLK_DIV ADC1 Clock divider 0 3 read-write div 1 Divide by 1 0b0000 div 2 Divide by 2 0b0001 div 3 Divide by 3 0b0010 div 4 Divide by 4 0b0011 div 5 Divide by 5 0b0100 div 6 Divide by 6 0b0101 div 7 Divide by 7 0b0110 div 8 Divide by 8 0b0111 div 15 Divide by 15 0b1110 div 16 Divide by 16 0b1111 APCLK Analog Peripheral Clock Register 0x058 32 CPCLK_DIV Charge Pump Clock Divider 29 29 read-write div 2 divide by 2 0b0 div 1 divide by 1 0b1 CPCLK_SEL Charge Pump Clock Selection 28 28 read-write LP_CLK LP_CLK is selected 0b0 f_sys fsys is selected 0b1 BGCLK_DIV Bandgap Clock Divider 25 25 read-write div 2 divide by 2 0b0 div 1 divide by 1 0b1 BGCLK_SEL Bandgap Clock Selection 24 24 read-write LP_CLK LP_CLK is selected 0b0 f_sys fsys is selected 0b1 APCLK2FAC Slow Down Clock Divider for TFILT_CLK Generation 8 12 read-write div 1 fsys 0b00000 div 2 fsys/2 0b00001 div 3 fsys/3 0b00010 div 4 fsys/4 0b00011 div 5 fsys/5 0b00100 div 6 fsys/6 0b00101 div 7 fsys/7 0b00110 div 8 fsys/8 0b00111 div 9 fsys/9 0b01000 div 10 fsys/10 0b01001 div 11 fsys/11 0b01010 div 12 fsys/12 0b01011 div 31 fsys/31 0b11110 div 32 fsys/32 0b11111 APCLK1FAC Analog Module Clock Factor 0 1 read-write div 1 Divide by 1 0b00 div 2 Divide by 2 0b01 div 3 Divide by 3 0b10 div 4 Divide by 4 0b11 APCLK_CTRL Analog Peripheral Clock Control Register 0x054 32 CLKWDT_IE Clock Watchdog Interrupt Enable 8 8 read-write disabled Interrupt disabled 0b0 enabled Interrupt enabled 0b1 APCLK_SET Set and Overtake Flag for Clock Settings 0 0 read-write ignore Clock Settings are ignored (previous values are held) 0b0 update Clock Settings are overtaken 0b1 APCLK_SCLR Analog Peripheral Clock Status Clear Register 0x064 32 APCLK3SCLR Analog Peripherals Clock 3 Status Clear 16 16 write-only APCLK2SCLR Analog Peripherals Clock Status Clear 8 8 write-only APCLK1SCLR Analog Peripherals Clock Status Clear 0 0 write-only APCLK_STS Analog Peripheral Clock Status Register 0x05C 32 PLL_LOCK PLL LOCK Status 24 24 read-only no lock PLL has not locked 0b0 lock PLL has locked 0b1 BRDRV_CLK_ERR_STS BRDRV CLK Error Status 20 20 read-only no Error no Error writing was not blocked 0b0 Error Error writing was blocked 0b1 APCLK3STS Loss of Clock Status 16 16 read-only no loss No loss of clock 0b0 loss Loss of clock occurred 0b1 APCLK2STS Analog Peripherals Clock Status 8 9 read-only OK The TFILT_CLK clock is in the required range 0b00 Too high The TFILT_CLK clock exceeds the higher limit 0b01 Too low The TFILT_CLK clock exceeds the lower limit 0b10 Out of Limit The TFILT_CLK clock is not inside the specified limit. 0b11 APCLK_ERR_STS APCLK Error Status 4 4 read-only no Error no Error writing was not blocked 0b0 Error Error writing was blocked 0b1 APCLK1STS Analog Peripherals Clock Status 0 1 read-only OK The MI_CLK clock is in the required range 0b00 too high The MI_CLK clock exceeds the higher limit 0b01 too low The MI_CLK clock exceeds the lower limit 0b10 out of limit The MI_CLK clock is not inside the specified limit. 0b11 BCON1 Baud Rate Control Register 1 0x088 32 BR1_PRE Prescaler Bit 1 3 read-write div 1 fDIV = fPCLK 0b000 div 2 fDIV = fPCLK/2 0b001 div 4 fDIV = fPCLK/4 0b010 div 8 fDIV = fPCLK/8 0b011 div 16 fDIV = fPCLK/16 0b100 div 32 fDIV = fPCLK/32 0b101 BR1_R Baud Rate Generator Run Control Bit 0 0 read-write Disable Baud-rate generator disabled. 0b0 Enable Baud-rate generator enabled. 0b1 BCON2 Baud Rate Control Register 2 0x098 32 BR2_PRE Prescaler Bit 1 3 read-write div 1 fDIV = fPCLK 0b000 div 2 fDIV = fPCLK/2 0b001 div 4 fDIV = fPCLK/4 0b010 div 8 fDIV = fPCLK/8 0b011 div 16 fDIV = fPCLK/16 0b100 div 32 fDIV = fPCLK/32 0b101 BR2_R Baud Rate Generator Run Control Bit 0 0 read-write Disable Baud-rate generator disabled. 0b0 Enable Baud-rate generator enabled. 0b1 BG1 Baud Rate Timer/Reload Register 0x090 32 BG1_TIM_VALUE Baud Rate Timer Value 16 26 read-only Bypassed Baud-rate timer is bypassed. 0x000 1 0x001 2 0x002 2046 0x7FE 2047 0x7FF BG1_BR_VALUE Baud Rate Reload Value 0 10 read-write Bypass Baud-rate timer is bypassed. 0x000 1 0x001 2 0x002 2046 0x7FE 2047 0x7FF BG2 Baud Rate Timer/Reload Register 0x0A0 32 BG2_TIM_VALUE Baud Rate Timer Value 16 26 read-only Bypassed Baud-rate timer is bypassed. 0x000 1 0x001 2 0x002 2046 0x7FE 2047 0x7FF BG2_BR_VALUE Baud Rate Reload Value 0 10 read-write Bypass Baud-rate timer is bypassed. 0x000 1 0x001 2 0x002 2046 0x7FE 2047 0x7FF BGL1 Baud Rate Timer/Reload Register, Low Byte 1 0x08C 32 BG1_FD_SEL Fractional Divider Selection 0 4 read-write BGL2 Baud Rate Timer/Reload Register, Low Byte 2 0x09C 32 BG2_FD_SEL Fractional Divider Selection 0 4 read-write BRDRV_CLK ADC1 Peripheral Clock Register 0x150 32 BRDRV_TFILT_DIV Slow Down Clock Divider for TFILT_CLK Generation 8 12 read-write div 1 fsys 0b00000 div 2 fsys/2 0b00001 div 3 fsys/3 0b00010 div 4 fsys/4 0b00011 div 5 fsys/5 0b00100 div 6 fsys/6 0b00101 div 7 fsys/7 0b00110 div 8 fsys/8 0b00111 div 9 fsys/9 0b01000 div 10 fsys/10 0b01001 div 11 fsys/11 0b01010 div 12 fsys/12 0b01011 div 31 fsys/31 0b11110 div 32 fsys/32 0b11111 BRDRV_CLK_DIV Analog Module Clock Factorf 0 1 read-write div 1 Divide by 1 0b00 div 2 Divide by 2 0b01 div 3 Divide by 3 0b10 div 4 Divide by 4 0b11 CMCON1 Clock Control Register 1 0x048 32 PDIV PLL PDIV-Divider: 8 13 read-write 0 P = 4 0 1 P = 4 1 2 P = 4 2 3 P = 4 3 4 P = 4 4 5 P = 5 (default) 5 6 P = 6, ... 6 50 P = 50 50 51 P = 50, ... 51 63 P = 50 63 K1DIV PLL K1-Divider 7 7 read-write div 2 K1 = 2 0b0 div 1 K1 = 1 0b1 K2DIV PLL K2-Divider 4 6 read-write div 2 K2 = 2 (default) 0x0 div 3 K2 = 3 0x1 div 4 K2 = 4 0x2 div 5 K2 = 5 0x3 div 6 K2 = 6 0x4 div 7 K2 = 7 0x5 div 8 K2 = 8 0x6 div 9 K2 = 9 0x7 CLKREL Slow Down Clock Divider for fCCLK Generation 0 3 read-write div 1 fsys 0b0000 div 2 fsys/2 0b0001 div 3 fsys/3 0b0010 div 4 fsys/4 0b0011 div 8 fsys/8 0b0100 div 16 fsys/16 0b0101 div 24 fsys/24 0b0110 div 32 fsys/32 0b0111 div 48 fsys/48 0b1000 div 64 fsys/64 0b1001 div 96 fsys/96 0b1010 div 128 fsys/128 0b1011 div 192 fsys/192 0b1100 div 256 fsys/256 0b1101 div 384 fsys/384 0b1110 div 512 fsys/512 0b1111 CMCON2 Clock Control Register 2 0x04C 32 PBA0CLKREL PBA0 Clock Divider 0 0 read-write div 1 divide by 1 0b0 div 2 divide by 2 0b1 COCON Clock Output Control Register 0x0B4 32 EN CLKOUT Enable 7 7 read-write disable No external clock signal is provided 0b0 enable The configured external clock signal is provided 0b1 COUTS1 Clock Out Source Select Bit 1 6 6 read-write f_cclk fCCLK is selected. 0b0 COUTS0 Based on setting of COUTS0. 0b1 TLEN Toggle Latch Enable 5 5 read-write disable Toggle Latch is disabled. Clock output frequency is chosen by the bit field COREL. 0b0 enable Toggle Latch is enabled. Clock output frequency is half of the frequency that is chosen by the bit field COREL. The resulting output frequency has 50 percent duty cycle. 0b1 COUTS0 Clock Out Source Select Bit 0 4 4 read-write Osc Oscillator output frequency is selected. 0b0 COREL Clock output frequency is chosen by the bit field COREL. 0b1 COREL Clock Output Divider 0 3 read-write div 1 fsys 0b0000 div 2 fsys/2 0b0001 div 3 fsys/3 0b0010 div 4 fsys/4 0b0011 div 6 fsys/6 0b0100 div 8 fsys/8 0b0101 div 10 fsys/10 0b0110 div 12 fsys/12 0b0111 div 14 fsys/14 0b1000 div 16 fsys/16 0b1001 div 18 fsys/18 0b1010 div 20 fsys/20 0b1011 div 24 fsys/24 0b1100 div 32 fsys/32 0b1101 div 36 fsys/36 0b1110 div 40 fsys/40 0b1111 EDCCON Error Detection and Correction Control Register 0x0D4 32 NVMIE NVM Double Bit ECC Error Interrupt Enable 2 2 read-write Disable No NMI is generated when a double bit ECC error occurs reading NVM. 0b0 Enable An NMI is generated when a double bit ECC error occurs reading NVM. 0b1 RIE RAM Double Bit ECC Error Interrupt Enable 0 0 read-write Disable No NMI is generated when a double bit ECC error occurs reading RAM. 0b0 Enable An NMI is generated when a double bit ECC error occurs reading RAM. 0b1 EDCSCLR Error Detection and Correction Status Clear Register 0x10C 32 RSBEC RAM Single Bit Error Clear 4 4 write-only Not cleared A single bit error on RAM is not cleared. 0b0 Cleared A single bit error on RAM is cleared. 0b1 NVMDBEC NVM Double Bit Error Clear 2 2 write-only Not Cleared A double bit error on NVM is not cleared. 0b0 Cleared A double bit error on NVM is cleared. 0b1 RDBEC RAM Double Bit Error Clear 0 0 write-only Not Cleared A double bit error on RAM is not cleared. 0b0 Cleared A double bit error on RAM is cleared. 0b1 EDCSTAT Error Detection and Correction Status Register 0x0D8 32 RSBE RAM Single Bit Error 4 4 read-only No Error No single bit error on RAM has occurred. 0b0 Error A single bit error on RAM has occurred. 0b1 NVMDBE NVM Double Bit Error 2 2 read-only No Error No double bit error on NVM has occurred. 0b0 Error A double bit error on NVM has occurred. 0b1 RDBE RAM Double Bit Error 0 0 read-only No Error No double bit error on RAM has occurred. 0b0 Error A double bit error on RAM has occurred. 0b1 EXICON0 External Interrupt Control Register 0 0x028 32 EXINT2 External Interrupt 2 Trigger Select 4 5 read-write disable Interrupt disabled. 0b00 rising Interrupt on rising edge. 0b01 falling Interrupt on falling edge. 0b10 both Interrupt on both rising and falling edge. 0b11 EXINT1 External Interrupt 1 Trigger Select 2 3 read-write disable Interrupt disabled. 0b00 rising Interrupt on rising edge. 0b01 falling Interrupt on falling edge. 0b10 both Interrupt on both rising and falling edge. 0b11 EXINT0 External Interrupt 0 Trigger Select 0 1 read-write enable Interrupt disabled. 0b00 rising Interrupt on rising edge. 0b01 falling Interrupt on falling edge. 0b10 both Interrupt on both rising and falling edge. 0b11 EXICON1 External Interrupt Control Register 1 0x02C 32 MON4 MON4 Input Trigger Select 6 7 read-write disable external interrupt MON is disabled. 0b00 rising Interrupt on rising edge. 0b01 falling Interrupt on falling edge. 0b10 both Interrupt on both rising and falling edge. 0b11 MON3 MON3 Input Trigger Select 4 5 read-write disable external interrupt MON is disabled. 0b00 rising Interrupt on rising edge. 0b01 falling Interrupt on falling edge. 0b10 both Interrupt on both rising and falling edge. 0b11 MON2 MON2 Input Trigger Select 2 3 read-write disable external interrupt MON is disabled. 0b00 rising Interrupt on rising edge. 0b01 falling Interrupt on falling edge. 0b10 both Interrupt on both rising and falling edge. 0b11 MON1 MON1 Input Trigger Select 0 1 read-write disable external interrupt MON is disabled. 0b00 rising Interrupt on rising edge. 0b01 falling Interrupt on falling edge. 0b10 both Interrupt on both rising and falling edge. 0b11 GPT12ICLR Timer and Counter Control/Status Clear Register 0x180 32 GPT12CRC GPT Module 1 Capture Reload Interrupt Status 5 5 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 GPT2T6C GPT Module 2Timer6 Interrupt Status 4 4 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 GPT2T5C GPT Module 2 Timer5 Interrupt Status 3 3 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 GPT1T4C GPT Module 1 Timer4 Interrupt Status 2 2 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 GPT1T3C GPT Module 1 Timer3 Interrupt Status 1 1 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 GPT1T2C GPT Module 1 Timer 2 Interrupt Status 0 0 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 GPT12IEN General Purpose Timer 12 Interrupt Enable Register 0x15C 32 CRIE General Purpose Timer 12 Capture and Reload Interrupt Enable 5 5 read-write Disable disabled 0b0 Enable enabled 0b1 T6IE General Purpose Timer 12 T6 Interrupt Enable 4 4 read-write Disable disabled 0b0 Enable enabled 0b1 T5IE General Purpose Timer 12 T5 Interrupt Enable 3 3 read-write Disable disabled 0b0 Enable enabled 0b1 T4IE General Purpose Timer 12 T4 Interrupt Enable 2 2 read-write Disable disabled 0b0 Enable enabled 0b1 T3IE General Purpose Timer 12 T3 Interrupt Enable 1 1 read-write Disable disabled 0b0 Enable enabled 0b1 T2IE General Purpose Timer 12 T2 Interrupt Enable 0 0 read-write Disable disabled 0b0 Enable enabled 0b1 GPT12IRC Timer and Counter Control/Status Register 0x160 32 GPT12CR GPT Module 1 Capture Reload Interrupt Status 5 5 read-only No Int No Capture Reload Interrupt has occurred. 0b0 Int Capture Reload Interrupt has occurred. 0b1 GPT2T6 GPT Module 2Timer6 Interrupt Status 4 4 read-only No Int No Timer 6 Interrupt has occurred. 0b0 Int Timer 6 Interrupt has occurred. 0b1 GPT2T5 GPT Module 2 Timer5 Interrupt Status 3 3 read-only No Int No Timer 5 Interrupt has occurred. 0b0 Int Timer 5 Interrupt has occurred. 0b1 GPT1T4 GPT Module 1 Timer4 Interrupt Status 2 2 read-only No Int No Timer 4 Interrupt has occurred. 0b0 Int Timer 4 Interrupt has occurred. 0b1 GPT1T3 GPT Module 1 Timer3 Interrupt Status 1 1 read-only No Int No Timer 3 Interrupt has occurred. 0b0 Int Timer 3 Interrupt has occurred. 0b1 GPT1T2 GPT Module 1 Timer 2 Interrupt Status 0 0 read-only No Int No Timer 2 Interrupt has occurred. 0b0 Int Timer 2 Interrupt has occurred. 0b1 GPT12PISEL GPT12 Peripheral Input Select Register 0x0D0 32 GPT12_SEL CCU6 Trigger Configuration. 5 5 read-write T_21 CCU6_INT is triggered by Timer21 0b0 GPT12 CCU6_INT is triggered by GPT12PISEL.GPT12 0b1 TRIG_CONF CCU6 Trigger Configuration. 4 4 read-write Single Trigger is just for one measurement (default) 0b0 Edge Trigger is present until next input edge (selected by GPT12) - continuous measurement. 0b1 GPT12 GPT12 TIN3B / TIN4D Input Select 0 3 read-write CC60 CC60 0b0000 CC61 CC61 0b0001 CC62 CC62 0b0010 T12 ZM T12 ZM 0b0011 T12 PM T12 PM 0b0100 T12 CM0 T12 CM0 0b0101 T12 CM1 T12 CM1 0b0110 T12 CM2 T12 CM2 0b0111 T13 PM T13 PM 0b1000 T13 ZM T13 ZM 0b1001 T13 CM T13 CM 0b1010 Edge any pos or neg edge on CC60/61/62 0b1011 ID Identity Register 0x0A8 32 PRODID Product ID 3 7 read-only VERID Version ID 0 2 read-only IEN0 Interrupt Enable Register 0 0x01C 32 EA Global Interrupt Mask 31 31 read-write disable All pending interrupt requests (except NMI) are blocked from the core. 0b0 enable Pending interrupt requests are not blocked from the core. 0b1 IRCON0 Interrupt Request Register 0 0x004 32 EXINT2F Interrupt Flag for External Interrupt 2x on falling edge 5 5 read-only Int Interrupt on falling edge event has not occurred. 0b0 no Int Interrupt on falling edge event has occurred. 0b1 EXINT2R Interrupt Flag for External Interrupt 2x on rising edge 4 4 read-only Int Interrupt on rising edge event has not occurred. 0b0 no Int Interrupt on rising edge event has occurred. 0b1 EXINT1F Interrupt Flag for External Interrupt 1x on falling edge 3 3 read-only Int Interrupt on falling edge event has not occurred. 0b0 no Int Interrupt on falling edge event has occurred. 0b1 EXINT1R Interrupt Flag for External Interrupt 1x on rising edge 2 2 read-only Int Interrupt on rising edge event has not occurred. 0b0 no Int Interrupt on rising edge event has occurred. 0b1 EXINT0F Interrupt Flag for External Interrupt 0x on falling edge 1 1 read-only Int Interrupt on falling edge event has not occurred. 0b0 no Int Interrupt on falling edge event has occurred. 0b1 EXINT0R Interrupt Flag for External Interrupt 0x on rising edge 0 0 read-only Int Interrupt on rising edge event has not occurred. 0b0 no Int Interrupt on rising edge event has occurred. 0b1 IRCON0CLR Interrupt Request 0 Clear Register 0x178 32 EXINT2FC Interrupt Flag for External Interrupt 2x on falling edge 5 5 write-only not cleared Interrupt event is not cleared. 0b0 cleared Interrupt event is cleared 0b1 EXINT2RC Interrupt Flag for External Interrupt 2x on rising edge 4 4 write-only not cleared Interrupt event is not cleared. 0b0 cleared Interrupt event is cleared 0b1 EXINT1FC Interrupt Flag for External Interrupt 1x on falling edge 3 3 write-only not cleared Interrupt event is not cleared. 0b0 cleared Interrupt event is cleared 0b1 EXINT1RC Interrupt Flag for External Interrupt 1x on rising edge 2 2 write-only not cleared Interrupt event is not cleared. 0b0 cleared Interrupt event is cleared 0b1 EXINT0FC Interrupt Flag for External Interrupt 0x on falling edge 1 1 write-only not cleared Interrupt event is not cleared. 0b0 cleared Interrupt event is cleared 0b1 EXINT0RC Interrupt Flag for External Interrupt 0x on rising edge 0 0 write-only not cleared Interrupt event is not cleared. 0b0 cleared Interrupt event is cleared 0b1 IRCON1 Interrupt Request Register 1 0x008 32 MON4F Interrupt Flag for MON4x on falling edge 7 7 read-only No Int Interrupt on falling edge event has not occurred. 0b0 Int Interrupt on falling edge event has occurred. 0b1 MON4R Interrupt Flag for MON4x on rising edge 6 6 read-only No Int Interrupt on rising edge event has not occurred. 0b0 Int Interrupt on rising edge event has occurred. 0b1 MON3F Interrupt Flag for MON3x on falling edge 5 5 read-only No Int Interrupt on falling edge event has not occurred. 0b0 Int Interrupt on falling edge event has occurred. 0b1 MON3R Interrupt Flag for MON3x on rising edge 4 4 read-only No Int Interrupt on rising edge event has not occurred. 0b0 Int Interrupt on rising edge event has occurred. 0b1 MON2F Interrupt Flag for MON2x on falling edge 3 3 read-only No Int Interrupt on falling edge event has not occurred. 0b0 Int Interrupt on falling edge event has occurred. 0b1 MON2R Interrupt Flag for MON2x on rising edge 2 2 read-only No Int Interrupt on rising edge event has not occurred. 0b0 Int Interrupt on rising edge event has occurred. 0b1 MON1F Interrupt Flag for MON1x on falling edge 1 1 read-only No Int Interrupt on falling edge event has not occurred. 0b0 Int Interrupt on falling edge event has occurred. 0b1 MON1R Interrupt Flag for MON1x on rising edge 0 0 read-only No Int Interrupt on rising edge event has not occurred. 0b0 Int Interrupt on rising edge event has occurred. 0b1 IRCON1CLR Interrupt Request 1 Clear Register 0x17C 32 MON4FC Interrupt Flag for MON4x on falling edge 7 7 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 MON4RC Interrupt Flag for MON4x on rising edge 6 6 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 MON3FC Interrupt Flag for MON3x on falling edge 5 5 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 MON3RC Interrupt Flag for MON3x on rising edge 4 4 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 MON2FC Interrupt Flag for MON2x on falling edge 3 3 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 MON2RC Interrupt Flag for MON2x on rising edge 2 2 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 MON1FC Interrupt Flag for MON1x on falling edge 1 1 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 MON1RC Interrupt Flag for MON1x on rising edge 0 0 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 IRCON2 Interrupt Request Register 2 0x00C 32 RIR1 Receive Interrupt Flag for SSC1 2 2 read-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 TIR1 Transmit Interrupt Flag for SSC1 1 1 read-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 EIR1 Error Interrupt Flag for SSC1 0 0 read-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 IRCON2CLR Interrupt Request 2 Clear Register 0x190 32 RIR1C Receive Interrupt Flag for SSC1 2 2 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 TIR1C Transmit Interrupt Flag for SSC1 1 1 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 EIR1C Error Interrupt Flag for SSC1 0 0 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 IRCON3 Interrupt Request Register 3 0x010 32 RIR2 Receive Interrupt Flag for SSC2 2 2 read-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 TIR2 Transmit Interrupt Flag for SSC2 1 1 read-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 EIR2 Error Interrupt Flag for SSC2 0 0 read-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 IRCON3CLR Interrupt Request 3 Clear Register 0x194 32 RIR2C Receive Interrupt Flag for SSC2 2 2 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 TIR2C Transmit Interrupt Flag for SSC2 1 1 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 EIR2C Error Interrupt Flag for SSC2 0 0 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 IRCON4 Interrupt Request Register 4 0x014 32 CCU6SR3 Interrupt Flag 1 for CCU6 20 20 read-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 CCU6SR2 Interrupt Flag 1 for CCU6 16 16 read-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 CCU6SR1 Interrupt Flag 1 for CCU6 4 4 read-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 CCU6SR0 Interrupt Flag 1 for CCU6 0 0 read-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 IRCON4CLR Interrupt Request 4 Clear Register 0x198 32 CCU6SR3C Interrupt Flag 1 for CCU6 20 20 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 CCU6SR2C Interrupt Flag 1 for CCU6 16 16 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 CCU6SR1C Interrupt Flag 1 for CCU6 4 4 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 CCU6SR0C Interrupt Flag 1 for CCU6 0 0 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 IRCON5 Interrupt Request Register 5 0x0F0 32 WAKEUP Interrupt Flag for Wakeup 0 0 read-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 IRCON5CLR Interrupt Request 5 Clear Register 0x19C 32 WAKEUPC Clear Flag for Wakeup Interrupt 0 0 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 LINSCLR LIN Status Clear Register 0x0A4 32 ERRSYNC SYN Byte Error Interrupt Flag 5 5 write-only Not cleared Error in SYN Byte not cleared. 0b0 Cleared Error in SYN Byte cleared. 0b1 EOFSYNC End of SYN Byte Interrupt Flag Clear 4 4 write-only Not cleared End of SYN Byte is not cleared. 0b0 Cleared End of SYN Byte is cleared. 0b1 BRKC Break Field Flag Clear 3 3 write-only Not cleared Break Field is not cleared. 0b0 Cleared Break Field is cleared. 0b1 LINST LIN Status Register 0x094 32 SYNEN End of SYN Byte and SYN Byte Error Interrupts Enable 6 6 read-write Disable End of SYN Byte and SYN Byte Error Interrupts are not enabled. 0b0 Enable End of SYN Byte and SYN Byte Error Interrupts are enabled. 0b1 ERRSYN SYN Byte Error Interrupt Flag 5 5 read-only Disable Error is not detected in SYN Byte. 0b0 Enable Error is detected in SYN Byte. 0b1 EOFSYN End of SYN Byte Interrupt Flag 4 4 read-only Disable End of SYN Byte is not detected. 0b0 Enable End of SYN Byte is detected. 0b1 BRK Break Field Flag 3 3 read-only Disable Break Field is not detected. 0b0 Enable Break Field is detected. 0b1 BGSEL Baud Rate Select for Detection 1 2 read-write BRDIS Baud Rate Detection Disable 0 0 read-write Disable Break/Synch detection is enabled. 0b0 Enable Break/Synch detection is disabled. 0b1 MEM_ACC_STS Memory Access Status Register 0x0E4 32 ROM_PROT_ERR ROM Access Protection 4 4 read-only No Error No Protection error 0b0 Error Protection error 0b1 NVM_SFR_ADDR_ERR NVM SFR Address Protection 3 3 read-only No Error No Protection error 0b0 Error Protection error 0b1 NVM_SFR_PROT_ERR NVM SFR Access Protection 2 2 read-only No Error No Protection error 0b0 Error Protection error 0b1 NVM_ADDR_ERR NVM Address Protection 1 1 read-only No Error No Protection error 0b0 Error Protection error 0b1 NVM_PROT_ERR NVM Access Protection 0 0 read-only No Error No Protection error 0b0 Error Protection error 0b1 MEMSTAT Memory Status Register 0x0DC 32 RAM_TEST_MODE RAM Data Mode 22 22 read-write Full RAM test at cold reset executed on the whole RAM 0b0 1K RAM test at cold reset executed only on 1st kb of RAM 0b1 RAM_VAL_KEYS RAM valid keys 20 21 read-write NVM_DATA_MODE NVM Data Mode 18 18 read-write 1 1 Non linearly mapped data sector 0b0 2 2 linearly mapped data sectors. 0b1 NVM_VAL_KEYS NVM valid keys 16 17 read-write SASTATUS Service Algorithm Status 6 7 read-write Success_1 Depending on SECTORINFO, there are two possible outcomes: For SECTORINFO = 00H, NVM initialization is successful and no SA is executed. For SECTORINFO = values other than 00H, SA execution is successful and only one map error is fixed. 0b00 Success_2 SA execution is successful. More than one mapping error is fixed. 0b01 Error_1 SA execution is not successful. Map error exists 0b10 Error_2 NVM initialization failed, SA called but no page to be repaired has been found. Soft error present. 0b11 SECTORINFO Sector Information 0 5 read-write MODIEN1 Peripheral Interrupt Enable Register 1 0x030 32 RIREN2 SSC 2 Receive Interrupt Enable 10 10 read-write Disable Receive interrupt is disabled 0b0 Enable Receive interrupt is enabled 0b1 TIREN2 SSC 2 Transmit Interrupt Enable 9 9 read-write Disable Transmit interrupt is disabled 0b0 Enable Transmit interrupt is enabled 0b1 EIREN2 SSC 2 Error Interrupt Enable 8 8 read-write Disable Error interrupt is disabled 0b0 Enable Error interrupt is enabled 0b1 RIREN1 SSC 1 Receive Interrupt Enable 2 2 read-write Disable Receive interrupt is disabled 0b0 Enable Receive interrupt is enabled 0b1 TIREN1 SSC 1 Transmit Interrupt Enable 1 1 read-write Disable Transmit interrupt is disabled 0b0 Enable Transmit interrupt is enabled 0b1 EIREN1 SSC 1 Error Interrupt Enable 0 0 read-write Disable Error interrupt is disabled 0b0 Enable Error interrupt is enabled 0b1 MODIEN2 Peripheral Interrupt Enable Register 2 0x034 32 TIEN2 UART 2 Transmit Interrupt Enable 7 7 read-write Disable Transmit interrupt is disabled 0b0 Enable Transmit interrupt is enabled 0b1 RIEN2 UART 2 Receive Interrupt Enable 6 6 read-write Disable Receive interrupt is disabled 0b0 Enable Receive interrupt is enabled 0b1 EXINT2_EN External Interrupt 2 Enable 5 5 read-write Disable External interrupt is disabled 0b0 Enable External interrupt is enabled 0b1 TIEN1 UART 1 Transmit Interrupt Enable 1 1 read-write Disable Transmit interrupt is disabled 0b0 Enable Transmit interrupt is enabled 0b1 RIEN1 UART 1 Receive Interrupt Enable 0 0 read-write Disable Receive interrupt is disabled 0b0 Enable Receive interrupt is enabled 0b1 MODIEN3 Peripheral Interrupt Enable Register 3 0x038 32 IE0 External Interrupt Enable 0 0 read-write Disable disabled 0b0 Enable enabled 0b1 MODIEN4 Peripheral Interrupt Enable Register 4 0x03C 32 IE1 External Interrupt Enable 0 0 read-write Disable disabled 0b0 Enable enabled 0b1 MODPISEL Peripheral Input Select Register 0x0B8 32 SSC12_S_MRST_OUTSEL Output selection for SSC12_S_MRST 18 18 read-write SSC1 SSC1_S_MRST 0b0 SSC2 SSC2_S_MRST 0b1 SSC12_M_MTSR_OUTSEL Output selection for SSC12_M_MTSR 17 17 read-write SSC1 SSC1_M_MTSR 0b0 SSC2 SSC2_M_MTSR 0b1 SSC12_M_SCK_OUTSEL Output selection for SSC12_M_SCK 16 16 read-write SSC1 SSC1_M_SCK 0b0 SSC2 SSC2_M_SCK 0b1 U_TX_CONDIS UART1 TxD Connection Disable 7 7 read-write Enable UART1-TX-Output -LIN Transmitter TX Input Connection available. 0b0 Disable UART1-TX-Output -LIN Transmitter TX Input Connection not available (can be stimulated by external port pin). 0b1 URIOS1 UART1 Input/Output Select 6 6 read-write Enable UART1 Receiver Input RXD1_0 (Connection to LIN is available). 0b0 Disable UART1 Receiver Input RXD1_1 (Connection to LIN is not available). 0b1 EXINT2IS External Interrupt 2 Input Select 4 5 read-write EXINT2_0 External Interrupt Input EXINT2_0 is selected. 0b00 EXINT2_1 External Interrupt Input EXINT2_1 is selected. 0b01 EXINT2_2 External Interrupt Input EXINT2_2 is selected. 0b10 EXINT2_3 External Interrupt Input EXINT2_3 is selected. 0b11 EXINT1IS External Interrupt 1 Input Select 2 3 read-write EXINT1_0 External Interrupt Input EXINT1_0 is selected. 0b00 EXINT1_1 External Interrupt Input EXINT1_1 is selected. 0b01 EXINT1_2 External Interrupt Input EXINT1_2 is selected. 0b10 EXINT1_3 External Interrupt Input EXINT1_3 is selected. 0b11 EXINT0IS External Interrupt 0 Input Select 0 1 read-write EXINT0_0 External Interrupt Input EXINT0_0 is selected. 0b00 EXINT0_1 External Interrupt Input EXINT0_1 is selected. 0b01 EXINT0_2 External Interrupt Input EXINT0_2 is selected. 0b10 EXINT0_3 External Interrupt Input EXINT0_3 is selected. 0b11 MODPISEL1 Peripheral Input Select Register 1 0x0BC 32 T21EXCON Timer 21 External Input Control 7 7 read-write MODPISEL Timer 21 Input T21EX is selected by bit field SCU_MODPISEL2.T21EXIS. 0b0 CCU6 Timer 21 Input T21EX is connected to signal from CCU6 (Output >cc6_ch0). 0b1 T2EXCON Timer 2 External Input Control 6 6 read-write MODPISEL Timer 2 Input T2EX is selected by bit field SCU_MODPISEL2.T2EXIS. 0b0 CCU Timer 2 Input T2EX is connected to signal from CCU6 (Output >cc6_cout60). 0b1 MODPISEL2 Peripheral Input Select Register 2 0x0C0 32 T21EXISCNF Timer 21 External Input Select Configuration 10 11 read-write T21EX_x Timer 21 Input T21EX_x is selected. 0b00 MONx MONx Input is selected. 0b01 T21EX_y Timer 21 Input T21EX_x is selected.. 0b10 MONy MONx Input is selected. 0b11 T2EXISCNF Timer 2 External Input Select Configuration 8 9 read-write T2EX_x Timer 2 Input T2EX_x is selected. 0b00 MONx MONx Input is selected. 0b01 T2EX_y Timer 2 Input T2EX_x is selected. 0b10 MONy MONx Input is selected. 0b11 T21EXIS Timer 21 External Input Select 6 7 read-write value0 Timer 21 Input T21EX_0 or MON1 is selected. 0b00 value1 Timer 21 Input T21EX_1 or MON2 is selected. 0b01 value2 Timer 21 Input T21EX_2 or MON3 is selected. 0b10 value3 Timer 21 Input T21EX_3 or MON4 is selected. 0b11 T2EXIS Timer 2 External Input Select 4 5 read-write value0 Timer 2 Input T2EX_0 or MON1 is selected. 0b00 value1 Timer 2 Input T2EX_1 or MON2 is selected. 0b01 value2 Timer 2 Input T2EX_2 or MON3 is selected. 0b10 value3 Timer 2 Input T2EX_3 or MON4 is selected. 0b11 T21IS Timer 21 Input Select 2 3 read-write T21_0 Timer 21 Input T21_0 is selected. 0b00 T21_1 Timer 21 Input T21_1 is selected. 0b01 T21_2 Timer 21 Input T21_2 is selected. 0b10 T2IS Timer 2 Input Select 0 1 read-write T2_0 Timer 2 Input T2_0 is selected. 0b00 T2_1 Timer 2 Input T2_1 is selected. 0b01 T2_2 Timer 2 Input T2_2 is selected. 0b10 MODPISEL3 Peripheral Input Select Register 3 0x0C4 32 URIOS2 UART2 Input/Output Select 6 6 read-write RXTX_0 UART2 Receiver Input RXD2_0 and Transmitter Output TXD2_0 is selected. 0b0 RXTX_1 UART2 Receiver Input RXD2_1 and Transmitter Output TXD2_1 is selected. 0b1 MODPISEL4 Peripheral Input Select Register 4 0x0FC 32 DU4TRIGGEN Differential Unit Trigger Enable 24 26 read-write CC60 CC60 is selected. 0b000 CC61 CC61 is selected. 0b001 CC62 CC62 is selected. 0b010 COUT60 COUT60 is selected. 0b011 COUT61 COUT61 is selected. 0b100 COUT62 COUT62 is selected. 0b101 T3OUT T3OUT is selected. 0b110 COUT63 COUT63 is selected. 0b111 DU3TRIGGEN Differential Unit Trigger Enable 16 18 read-write CC60 CC60 is selected. 0b000 CC61 CC61 is selected. 0b001 CC62 CC62 is selected. 0b010 COUT60 COUT60 is selected. 0b011 COUT61 COUT61 is selected. 0b100 COUT62 COUT62 is selected. 0b101 T3OUT T3OUT is selected. 0b110 COUT63 COUT63 is selected. 0b111 DU2TRIGGEN Differential Unit Trigger Enable 8 10 read-write CC60 CC60 is selected. 0b000 CC61 CC61 is selected. 0b001 CC62 CC62 is selected. 0b010 COUT60 COUT60 is selected. 0b011 COUT61 COUT61 is selected. 0b100 COUT62 COUT62 is selected. 0b101 T3OUT T3OUT is selected. 0b110 COUT63 COUT63 is selected. 0b111 DU1TRIGGEN Differential Unit Trigger Enable 0 2 read-write CC60 CC60 is selected. 0b000 CC61 CC61 is selected. 0b001 CC62 CC62 is selected. 0b010 COUT60 COUT60 is selected. 0b011 COUT61 COUT61 is selected. 0b100 COUT62 COUT62 is selected. 0b101 T3OUT T3OUT is selected. 0b110 COUT63 COUT63 is selected. 0b111 MODSUSP Module Suspend Control Register 0x0C8 32 ADC1_SUSP ADC1 Unit Debug Suspend Bit 10 10 read-write No suspend ADC1 will not be suspended. 0b0 Suspend ADC1 will be suspended. 0b1 MU_SUSP Measurement Unit Debug Suspend Bit 9 9 read-write No Suspend MU will not be suspended. 0b0 Suspend MU will be suspended. 0b1 WDT1SUSP Watchdog Timer 1 Debug Suspend Bit 7 7 read-write No Suspend WDT1 will not be suspended. 0b0 Suspend WDT1 will be suspended. 0b1 T21_SUSP Timer21 Debug Suspend Bit 6 6 read-write No Suspend Timer21 will not be suspended. 0b0 Suspend Timer21 will be suspended. 0b1 GPT12_SUSP GPT12 Debug Suspend Bit 4 4 read-write No Suspend GPT12 will not be suspended. 0b0 Suspend GPT12 will be suspended. 0b1 T2_SUSP Timer2 Debug Suspend Bit 3 3 read-write No Suspend Timer2 will not be suspended. 0b0 Suspend Timer2 will be suspended. 0b1 T13SUSP Timer 13 Debug Suspend Bit 2 2 read-write No Suspend Timer 13 in Capture/Compare Unit will not be suspended. 0b0 Suspend Timer 13 in Capture/Compare Unit will be suspended. 0b1 T12SUSP Timer 12 Debug Suspend Bit 1 1 read-write No Suspend Timer 12 in Capture/Compare Unit will not be suspended. 0b0 Suspend Timer 12 in Capture/Compare Unit will be suspended. 0b1 WDTSUSP SCU Watchdog Timer Debug Suspend Bit 0 0 read-write No Suspend WDT will not be suspended. 0b0 Suspend WDT will be suspended. 0b1 MONIEN Monitoring Input Interrupt Enable Register 0x18C 32 MON4IE MON 4 Interrupt Enable 3 3 read-write Disable disabled 0b0 Enable enabled 0b1 MON3IE MON 3 Interrupt Enable 2 2 read-write Disable disabled 0b0 Enable enabled 0b1 MON2IE MON 2 Interrupt Enable 1 1 read-write Disable disabled 0b0 Enable enabled 0b1 MON1IE MON 1 Interrupt Enable 0 0 read-write Disable disabled 0b0 Enable enabled 0b1 NMICON NMI Control Register 0x024 32 NMISTOF Stack Overflow NMI Enable 8 8 read-write disable Stack overflow NMI is disabled. 0b0 enable Stack overflow NMI is enabled. 0b1 NMISUP Supply Prewarning NMI Enable 7 7 read-write disable Supply NMI is disabled. 0b0 enable Supply NMI is enabled. 0b1 NMIECC ECC Error NMI Enable 6 6 read-write disable ECC Error NMI is disabled. 0b0 enable ECC Error NMI is enabled. 0b1 NMIMAP NVM Map Error NMI Enable 5 5 read-write disable NVM Map Error NMI is disabled. 0b0 enable NVM Map Error NMI is enabled. 0b1 NMIOWD Oscillator Watchdog NMI Enable 4 4 read-write disable Oscillator watchdog NMI is disabled. 0b0 enable Oscillator watchdog NMI is enabled. 0b1 NMIOT NMI OT Enable 3 3 read-write disable NMI OT is disabled. 0b0 enable NMI OT is enabled. 0b1 NMIPLL PLL Loss of Lock NMI Enable 1 1 read-write disable PLL Loss of Lock NMI is disabled. 0b0 enable PLL Loss of Lock NMI is enabled. 0b1 NMIWDT Watchdog Timer NMI Enable 0 0 read-write disable WDT NMI is disabled. 0b0 enable WDT NMI is enabled. 0b1 NMISR NMI Status Register 0x018 32 FNMISTOF Stack Overflow NMI Flag 8 8 read-only no Int No supply prewarning NMI has occurred. 0b0 Int Supply prewarning has occurred. 0b1 FNMISUP Supply Prewarning NMI Flag 7 7 read-only no Int No supply prewarning NMI has occurred. 0b0 Int Supply prewarning has occurred. 0b1 FNMIECC ECC Error NMI Flag 6 6 read-only no Int No uncorrectable ECC error has occurred on NVM, XRAM. 0b0 Int Uncorrectable ECC error has occurred on NVM, RAM. 0b1 FNMIMAP NVM Map Error NMI Flag 5 5 read-only no Int No NVM Map Error NMI has occurred. 0b0 Int NVM Map Error has occurred. 0b1 FNMIOWD Oscillator Watchdog NMI Flag 4 4 read-only no Int No oscillator watchdog NMI has occurred. 0b0 Int Oscillator watchdog event has occurred. 0b1 FNMIOT Overtemperature NMI Flag 3 3 read-only no Int No OT NMI has occurred. 0b0 Int OT NMI event has occurred. 0b1 FNMIPLL PLL NMI Flag 1 1 read-only no Int No PLL NMI has occurred. 0b0 Int PLL loss-of-lock to the external crystal has occurred. 0b1 FNMIWDT Watchdog Timer NMI Flag 0 0 read-only no Int No watchdog NMI has occurred. 0b0 Int WDT prewarning has occurred. 0b1 NMISRCLR NMI Status Clear Register 0x000 32 FNMIMAPC NVM Map Error NMI Flag 5 5 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 FNMIOWDC Oscillator Watchdog NMI Flag 4 4 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 FNMIPLLC PLL NMI Flag 1 1 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 FNMIWDTC Watchdog Timer NMI Flag 0 0 write-only Not Cleared Interrupt event is not cleared. 0b0 Cleared Interrupt event is cleared 0b1 NVM_PROT_STS NVM Protection Status Register 0x0E0 32 DAT_LIN_SIZE Data linear Region Size Definition 26 27 read-only 0K data linear Size is 0K 0b00 4K data linear Size is 4K 0b01 8K data linear Size is 8K 0b10 12K data linear Size is 12K 0b11 CUS_BSL_SIZE CBSL Region Size Definition 24 25 read-only 0K CBSL Size is 0K 0b00 4K CBSL Size is 4K 0b01 8K CBSL Size is 8K 0b10 16K CBSL Size is 16K 0b11 DAT_NL_PW Status of Non-Linear Region Password / Protection 22 22 read-only Not Protected Non-Linear Region Password is not installed; Linear region is not protected. 0b0 Protected Non-Linear Region Password is installed; Linear region is protected. 0b1 DAT_LIN_PW Status of Data linear Region Password / Protection 21 21 read-only Not protected Non-Linear Region Password is not installed; Linear region is not protected. 0b0 Protected Non-Linear Region Password is installed; Linear region is protected. 0b1 COD_LIN_PW Status of Linear Region Password / Protection 20 20 read-only Not Protected Linear Region Password is not installed; Linear region is not protected. 0b0 Protected Linear Region Password is installed; Linear region is protected. 0b1 CUS_BSL_PW Status of CBSL Region Password / Protection 19 19 read-only Not Protected CBSL Region Password is not installed; CBSL region is not protected. 0b0 Protected CBSL Region Password is installed; CBSL region is protected. 0b1 DIS_RDUS_S0 Configuration of NVM Read Protection for Sector 0 with EN_RD_S0 = 0 18 18 read-only Not Protected only active when nvm_read_S0_unsafe_i = 1 and not for nvm_read_S0_unsafe_i = 0 0b0 Protected independent from nvm_read_S0_unsafe_i; Also write accesess to Sector 0 are prevented 0b1 DIS_RDUS Configuration of NVM Read Protection for Sector 1...n with EN_RD_* = 0 17 17 read-only Not Protected only active when nvm_read_unsafe_i = 1 and not for nvm_read_unsafe_i = 0 0b0 Protected independent from nvm_read_unsafe_i; Also write accesess to Sector 1...n are prevented 0b1 EN_RD_S0 NVM Read Protection for Sector 0 16 16 read-only Protected The data in sector 0 can not be read over AHB-Lite Interface 0b0 Not Protected The data in sector 0 can be read over AHB-Lite Interface 0b1 EN_PRG_DAT_NL NVM Protection of Data in Non-Linear Data Sectors 7 7 read-only Protected The data in sectors of the non-linearly mapped area can not be changed 0b0 Not Protected The data in sectors of the non-linearly mapped area can be changed (erased or written) 0b1 EN_RD_DAT_NL NVM Read Protection of Data in Non-Linear Data Sectors 6 6 read-only Protected The data in sectors of the non-linearly mapped area can not be read 0b0 Not Protected The data in sectors of the non-linearly mapped area can be read 0b1 EN_PRG_DAT_LIN NVM Protection of Data in Linear Data Sectors 5 5 read-only Protected The data in sectors of the linearly mapped area can not be changed 0b0 Not Protected The data in sectors of the linearly mapped area can be changed (erased or written) 0b1 EN_RD_DAT_LIN NVM Read Protection of Data in Linear Data Sectors 4 4 read-only Protected The data in sectors of the linearly mapped area can not be read 0b0 Not Protected The data in sectors of the linearly mapped area can be read 0b1 EN_PRG_COD_LIN NVM Protection of Data in Linear Code Sectors 3 3 read-only Protected The data in sectors of the linearly mapped area can not be changed 0b0 Not Protected The data in sectors of the linearly mapped area can be changed (erased or written) 0b1 EN_RD_COD_LIN NVM Read Protection of Data in Linear Code Sectors 2 2 read-only Protected The data in sectors of the linearly mapped area can not be read 0b0 Not Protected The data in sectors of the linearly mapped area can be read 0b1 EN_PRG_CUS_BSL NVM Protection of Data in Customer BSL Region 1 1 read-only Protected The data in region defined by NVMBSL can not be changed 0b0 Not Protected The data in region defined by NVMBSL can be changed (erased or written) 0b1 EN_RD_CUS_BSL NVM Read Protection of Data in Customer BSL Region 0 0 read-only Protected The data in region defined by NVMBSL can not be read 0b0 Not Protected The data in region defined by NVMBSL sectors of can be read 0b1 OSC_CON OSC Control Register 0x0B0 32 XPD XTAL (OSC_HP) Power Down Control 4 4 read-write Enabled XTAL (OSC_HP) is not powered down. 0b0 Power down XTAL (OSC_HP) is powered down. 0b1 OSC2L OSC-Too-Low Condition Flag 3 3 read-only OSC OK fOSC is above threshold. 0b0 OSC too low fOSC is below threshold. 0b1 OSCWDTRST Oscillator Watchdog Reset 2 2 read-write No Reset No effect. 0b0 Reset Reset OSC2L flag and restart the oscillator watchdog of the PLL. 0b1 OSCSS Oscillator Source Select 0 1 read-write f_int_sync PLL internal oscillator OSC_PLL (fINT) is selected synchronously as fR. 0b00 Xtal_sync XTAL (fOSC from OSC_HP) is selected synchronously as fR. 0b01 f_int_async PLL internal oscillator OSC_PLL (fINT) is selected asynchronously as fR. 0b10 P0_POCON0 Port Output Control Register 0x0E8 32 P0_PDM6 P0.6 Port Driver Mode 24 26 read-write Strong-sharp Strong driver and sharp edge mode 0b000 Strong-med Strong driver and medium edge mode 0b001 Strong-soft Strong driver and soft edge mode 0b010 Weak Weak driver 0b011 Medium Medium driver 0b100 P0_PDM5 P0.5 Port Driver Mode 20 22 read-write Strong-sharp Strong driver and sharp edge mode 0b000 Strong-med Strong driver and medium edge mode 0b001 Strong-soft Strong driver and soft edge mode 0b010 Weak Weak driver 0b011 Medium Medium driver 0b100 P0_PDM4 P0.4 Port Driver Mode 16 18 read-write Strong-sharp Strong driver and sharp edge mode 0b000 Strong-med Strong driver and medium edge mode 0b001 Strong-soft Strong driver and soft edge mode 0b010 Weak Weak driver 0b011 Medium Medium driver 0b100 P0_PDM3 P0.3 Port Driver Mode 12 14 read-write Strong-sharp Strong driver and sharp edge mode 0b000 Strong-med Strong driver and medium edge mode 0b001 Strong-soft Strong driver and soft edge mode 0b010 Weak Weak driver 0b011 Medium Medium driver 0b100 P0_PDM2 P0.2 Port Driver Mode 8 10 read-write Strong-sharp Strong driver and sharp edge mode 0b000 Strong-med Strong driver and medium edge mode 0b001 Strong-soft Strong driver and soft edge mode 0b010 Weak Weak driver 0b011 Medium Medium driver 0b100 P0_PDM1 P0.1 Port Driver Mode 4 6 read-write Strong-sharp Strong driver and sharp edge mode 0b000 Strong-med Strong driver and medium edge mode 0b001 Strong-soft Strong driver and soft edge mode 0b010 Weak Weak driver 0b011 Medium Medium driver 0b100 P0_PDM0 P0.0 Port Driver Mode 0 2 read-write Strong-sharp Strong driver and sharp edge mode 0b000 Strong-med Strong driver and medium edge mode 0b001 Strong-soft Strong driver and soft edge mode 0b010 Weak Weak driver 0b011 Medium Medium driver 0b100 P1_POCON0 Port Output Control Register 0x0F8 32 P1_PDM4 P1.4 Port Driver Mode 16 18 read-write Strong-sharp Strong driver and sharp edge mode 0b000 Strong-med Strong driver and medium edge mode 0b001 Strong-soft Strong driver and soft edge mode 0b010 Weak Weak driver 0b011 Medium Medium driver 0b100 P1_PDM2 P1.2 Port Driver Mode 8 10 read-write Weak Weak driver 0b011 Medium Medium driver 0b100 P1_PDM1 P1.1 Port Driver Mode 4 6 read-write Weak Weak driver 0b011 Medium Medium driver 0b100 P1_PDM0 P1.0 Port Driver Mode 0 2 read-write Weak Weak driver 0b011 Medium Medium driver 0b100 PASSWD Password Register 0x0AC 32 PASS Password Bits 3 7 read-write Enable Enables writing of the bit field MODE. 0b11000 Open Opens access to writing of all protected bits. 0b10011 Close Closes access to writing of all protected bits. 0b10101 PROTECT_S Bit-Protection Signal Status Bit 2 2 read-only Not protected Software is able to write to all protected bits. 0b0 Protected Software is unable to write to any protected bits. 0b1 PW_MODE Bit-Protection Scheme Control Bit 0 1 read-write Disable Scheme Disabled 0b00 Enable Scheme Enabled (default) 0b11 PLL_CON PLL Control Register 0x044 32 UNPROT_VCOBYP Unprotect write access of VCO_BYP 19 19 write-only UNPROT_OSCDISC Unprotect write access of OSC_DISC 18 18 write-only NDIV PLL N-Divider 8 15 read-write 0 N = 39, ... 00 38 N = 39 38 39 N = 39, ... 39 80 N = 80 (default), ... 80 200 N = 200 200 201 N = 200, ... 201 255 N = 200 255 VCOBYP PLL VCO Bypass Mode Select 3 3 read-write Normal Normal (or freerunning) operation (default) 0b0 Prescaler Prescaler Mode; VCO is bypassed (PLL output clock is derived from input clock divided by K1-divider) 0b1 OSCDISC Oscillator Disconnect 2 2 read-write Connect Oscillator is connected to the PLL 0b0 Disconnect Oscillator is disconnected to the PLL. 0b1 RESLD Restart Lock Detection 1 1 read-write No reset No effect. 0b0 reset Reset lock flag and restart lock detection. 0b1 LOCK PLL Lock Status Flag 0 0 read-only Not Locked The frequency difference of fREF and fDIV is greater than allowed. The VCO part of the PLL can not lock on a target frequency. 0b0 Locked The frequency difference of fREF and fDIV is small enough to enable a stable VCO operation. 0b1 PMCON Peripheral Management Control Register 0x060 32 T21_DIS T21 Disable Request. Active high. 10 10 read-write Enable T21 is in normal operation. (default) 0b0 Disable Request to disable the T21. 0b1 SSC2_DIS SSC Disable Request. Active high. 8 8 read-write Enable SSC is in normal operation. (default) 0b0 Disable Request to disable the SSC. 0b1 GPT12_DIS General Purpose Timer 12 Disable Request. Active high. 4 4 read-write Enable GPT12 is in normal operation. (default) 0b0 Disable Request to disable the GPT12. 0b1 T2_DIS T2 Disable Request. Active high. 3 3 read-write Enable T2 is in normal operation. (default) 0b0 Disable Request to disable the T2. 0b1 CCU_DIS CCU Disable Request. Active high. 2 2 read-write Enable CCU is in normal operation. (default) 0b0 Disabel Request to disable the CCU. 0b1 SSC1_DIS SSC Disable Request. Active high. 1 1 read-write Enable SSC is in normal operation. (default) 0b0 Disable Request to disable the SSC. 0b1 ADC1_DIS ADC1 Disable Request. Active high. 0 0 read-write Enable ADC1 is in normal operation. (default) 0b0 Disable Request to disable the ADC. 0b1 PMCON0 Power Mode Control Register 0 0x040 32 SD Slow Down Mode Enable. Active High. 3 3 read-write PD Power Down Mode Enable. Active High. 2 2 read-write SL Sleep Mode Enable. Active High. 1 1 read-write XTAL_ON OSC_HP Operation in Power Down Mode 0 0 read-write PD OSC_HP (XTAL) will be put to Power Down mode by hardware in power save mode. 0b0 ON OSC_HP (XTAL) continues to operate in Power Down mode, if enabled by SCU_OSC_CON.XPD. 0b1 RSTCON Reset Control Register 0x068 32 LOCKUP_EN Lockup Reset Enable Flag 7 7 read-write disable Lockup is disabled. 0b0 enable Lockup is enabled. 0b1 LOCKUP Lockup Flag 0 0 read-write disable Lockup Status not active. 0b0 enable Lockup Status active. 0b1 STACK_OVF_ADDR Stack Overflow Control Register 0x148 32 STOF_ADDR_OFF_H Stack Overflow High Address Offset 18 27 read-write STOF_ADDR_OFF_L Stack Overflow Low Address Offset 2 11 read-write STACK_OVF_CTRL Stack Overflow Control Register 0x144 32 STOF_EN Stack Overflow Enable 0 0 read-write Disable stack overflow detection disabled. 0b0 Enable stack overflow detection enabled 0b1 STACK_OVF_STS Stack Overflow Status Register 0x14C 32 STOF_STS Stack Overflow Status 0 0 read-write No Error No stack overflow detected. 0b0 Error stack overflow detected. 0b1 STACK_OVFCLR Stack Overflow Status Clear Register 0x12C 32 STOF_STSC Clear Stack Overflow Status 0 0 write-only Not Cleared stack overflow not cleared. 0b0 Cleared stack overflow cleared. 0b1 SYS_STRTUP_STS System Startup Status Register 0x074 32 PG100TP_CHKS_ERR 100 TP Page Checksum Error 2 2 read-write OK initialisation of trimming parameters from NVM was successfull (checksum was correct) 0b0 Not OK initialisation of trimming parameter from NVM was not successfull (checksum was not correct). As a backup default values form Boot-ROM are used 0b1 MRAMINITSTS Map RAM Initialisation Status 1 1 read-write No Fail Map RAM initialisation was successfull 0b0 Fail Map RAM initialisation was not successfull 0b1 PLL_LOCK_STS PLL LOCK STATUS 0 0 read-write No Fail 0b0 Fail 0b1 SYSCON0 System Control Register 0 0x070 32 SYSCLKSEL System Clock Select 6 7 read-write f_pll The PLL clock output signal fPLL is used 0b00 f_osc The direct clock input from fOSC is used 0b01 f_lpclk The direct low-precision clock input from fLP_CLK is used. 0b10 f_int The direct input from internal oscillator fINTOSC is used 0b11 NVMCLKFAC NVM Access Clock Factor 4 5 read-only div 1 Divide by 1 0b00 div 2 Divide by 2 0b01 div 3 Divide by 3 0b10 div 4 Divide by 4 0b11 TCCR Temperature Compensation Control Register 0x0F4 32 TCC Temperature Compensation Control 0 1 read-write T1 TJ: -40 degree C to 0 degree C 0b00 T2 TJ: 0 degree C to 40 degree C 0b01 T3 TJ: 40 degree C to 80 degree C 0b10 T4 TJ: 80 degree C to 150 degree C 0b11 VTOR Vector Table Reallocation Register 0x020 32 VTOR_BYP Vector Table Bypass Mode 0 1 read-write ROM VTOR is not remapped (ROM) 0b00 RAM VTOR is remapped to RAM 0b01 NVM_BSL VTOR is remapped to NVM 0b10 NVM_LIN VTOR is remapped to NVM 0b11 WAKECON Wakeup Interrupt Control Register 0x0EC 32 WAKEUPEN Wakeup Interrupt Enable 0 0 read-write disable wakeup interrupt is disabled. 0b0 enable wakeup interrupt is enabled. 0b1 WDT Watchdog Timer 0x080 32 WDT Watchdog Timer Current Value 0 15 read-only WDTCON Watchdog Timer Control Register 0x050 32 WINBEN Watchdog Window-Boundary Enable 5 5 read-write Disable Watchdog Window-Boundary feature is disabled. (default) 0b0 Enable Watchdog Window-Boundary feature is enabled. 0b1 WDTPR Watchdog Prewarning Mode Flag 4 4 read-only Normal Normal mode (default after reset) 0b0 Prewarn The Watchdog is operating in Prewarning Mode 0b1 WDTEN WDT Enable 2 2 read-write Disable WDT is disabled 0b0 Enable WDT is enabled 0b1 WDTRS WDT Refresh Start 1 1 read-write WDTIN Watchdog Timer Input Frequency Selection 0 0 read-write DIV 2 Input frequency is fPCLK/2 0b0 DIV 128 Input frequency is fPCLK/128 0b1 WDTREL Watchdog Timer Reload Register 0x078 32 WDTREL Watchdog Timer Reload Value 0 7 read-write WDTWINB Watchdog Window-Boundary Count 0x07C 32 WDTWINB Watchdog Window-Boundary Count Value 0 7 read-write XTAL_CTRL Peripheral Input Select Register 0x100 32 XTALHYSCTRL XTAL Hysteresis Control 4 5 read-write XHYST_0 400mV nom. 0b00 XHYST_1 300mV nom. 0b01 XHYST_2 200mV nom. 0b10 XHYST_3 100mV nom. 0b11 XTALHYSEN XTAL Hysteresis Enable 1 1 read-write Disable Hysteresis is disabled 0b0 Enable Hysteresis is enabled 0b1 XTAL12EN Pins XTAL1/2 Enable Bit 0 0 read-write Disable Pins XTAL1/2 is not available. This setting overrides the .XPD setting. 0b0 Enable Pins XTAL1/2 are available 0b1 SCUPM SCUPM 0x50006000 0x0 0x1000 registers AMCLK_CTRL Analog Module Clock Control Register 0x04 32 CLKWDT_PD_N Clock Watchdog Powerdown 0 0 read-write DISABLE Clock Watchdog disabled 0b0 ENABLE Clock Watchdog enabled 0b1 AMCLK_FREQ_STS Analog Module Clock Frequency Status Register 0x00 32 AMCLK2_FREQ Current frequency of Analog Module Clock 2 (TFILT_CLK) 8 13 read-only AMCLK1_FREQ Current frequency of Analog Module Clock System Clock (MI_CLK) 0 5 read-only AMCLK_TH_HYS Analog Module Clock Limit Register 0x0C 32 AMCLK2_LOW_HYS Analog Module Clock 2 (TFILT_CLK) Lower Hysteresis 30 31 read-write AMCLK2_LOW_TH Analog Module Clock 2 (TFILT_CLK) Lower Limit Threshold 24 29 read-write AMCLK2_UP_HYS Analog Module Clock 2 (TFILT_CLK) Upper Hysteresis 22 23 read-write AMCLK2_UP_TH Analog Module Clock 2 (TFILT_CLK) Upper Limit Threshold 16 21 read-write AMCLK1_LOW_HYS Analog Module Clock 1 (MI_CLK) Lower Hysteresis 14 15 read-write AMCLK1_LOW_TH Analog Module Clock 1 (MI_CLK) Lower Limit Threshold 8 13 read-write AMCLK1_UP_HYS Analog Module Clock 1 (MI_CLK) Upper Hysteresis 6 7 read-write AMCLK1_UP_TH Analog Module Clock 1 (MI_CLK) Upper Limit Threshold 0 5 read-write PCU_CTRL_STS Power Control Unit Control Status Register 0x30 32 CLKLOSS_RES_SD_DIS Loss of Clock Reset Disable 27 27 read-write Enable Loss of Clock Reset Enable 0b0 Disable Loss of Clock Reset Disable 0b1 CLKWDT_RES_SD_DIS Clock Watchdog Reset Disable 26 26 read-write Enable Clock Watchdog Reset Enable 0b0 Disable Clock Watchdog Reset Disable 0b1 CLKLOSS_SD_DIS System Loss of Clock Shutdown Disable (AMCLK3) 25 25 read-write Enable Automatic Shutdown Signal for Power Switches in case of loss of clock 0b0 Disable Automatic Shutdown Signal for Power Switches in case of loss of clock 0b1 SYS_OTWARN_PS_DIS System Overtemperature Warning Power Switches Shutdown Disable 24 24 read-write Enable Automatic Shutdown Signal for Power Switches in case of system overtemperature warning enable 0b0 Disable Automatic Shutdown Signal for Power Switches in case of system overtemperature warning enable 0b1 SYS_VS_OV_SLM_DIS VS Overvoltage Shutdown for Peripherals Disable 14 14 read-write Enable Automatic Shutdown for Power modules in case of VS Overvoltage enabled 0b0 Disable Automatic Shutdown for Power modules in case of VS Overvoltage disabled 0b1 SYS_VS_UV_SLM_DIS VS Undervoltage Shutdown for Peripherals Disable 13 13 read-write Enable Automatic Shutdown for Power modules in case of VS Undervoltage enabled 0b0 Disable Automatic Shutdown for Power modules in case of VS Undervoltage disabled 0b1 LIN_VS_UV_SD_DIS LIN Module VS Undervoltage Transmitter Shutdown 8 8 read-write Enable Automatic Shutdown for Power modules in case of VS Undervoltage enabled 0b0 Disable Automatic Shutdown for Power modules in case of VS Undervoltage disabled 0b1 FAIL_PS_DIS Disable LIN Tx and HS and because of Overtemperature Warning or VS OV/UV 7 7 read-write Switch off Enabled LIN Tx andHS will be turned off when Overtemperature Warning occurs 0b0 Switch off Disabled LIN Tx andHS will be kept on when Overtemperature Warning occurs 0b1 CLKWDT_SD_DIS Power Modules Clock Watchdog Shutdown Disable 1 1 read-write Shutdown Enable Power Devices will be switched off when Clock Watchdog. 0b0 Shutdown Disable Power Devices will not be shutdown when Clock Watchdog occurs 0b1 STCALIB System Tick Calibration Register 0x6C 32 STCALIB System Tick Calibration 0 25 read-write SYS_IRQ_CTRL System Interrupt Control Register 0x28 32 VREF1V2_OV_IE 8 Bit ADC2 Reference Overvoltage Interrupt Enable 13 13 read-write Interrupt is disabled 0b0 Interrupt is enabled 0b1 VREF1V2_UV_IE 8 Bit ADC2 Reference Undervoltage Interrupt Enable 12 12 read-write Interrupt is disabled 0b0 Interrupt is enabled 0b1 SYS_OT_IE System Overtemperature Shutdown Interrupt Enable 9 9 read-write Interrupt is disabled 0b0 Interrupt is enabled 0b1 SYS_OTWARN_IE System Overtemperature Prewarning Interrupt Enable 8 8 read-write Interrupt is disabled 0b0 Interrupt is enabled 0b1 SYS_IS System Interrupt Status Register 0x18 32 SYS_SUPPLY_STS System Supply Status 30 30 read-only OK no status set 0b0 FAIL at least one status set 0b1 VREF1V2_OV_STS 8 Bit ADC2 Reference Overvoltage (ADC2, Channel 5) interrupt status 29 29 read-write OK no interrupt status set 0b0 FAIL at least one interrupt status set 0b1 VREF1V2_UV_STS 8 Bit ADC2 Reference Undervoltage (ADC2, Channel 5) interrstatus 28 28 read-write OK no interrupt status set 0b0 FAIL at least one interrupt status set 0b1 SYS_OT_STS System Overtemperature Shutdown (ADC2, Channel 6) status 25 25 read-write OK no status set 0b0 FAIL at least one status set 0b1 SYS_OTWARN_STS System Overtemperature Prewarning (ADC2, Channel 6) status 24 24 read-write OK no status set 0b0 FAIL at least one status set 0b1 HS_FAIL_STS High Side Driver Fail Status 19 19 read-only OK no status set 0b0 FAIL at least one status set 0b1 DRV_FAIL_STS Gate Driver Fail Status 18 18 read-only OK no status set 0b0 FAIL at least one status set 0b1 CP_FAIL_STS Charge Pump Fail Status 17 17 read-only OK no status set 0b0 FAIL at least one status set 0b1 LIN_FAIL_STS LIN Fail Status 16 16 read-only OK no status set 0b0 FAIL at least one status set 0b1 SYS_SUPPLY_IS System Supply Interrupt Status 14 14 read-only OK no interrupt status set 0b0 FAIL at least one interrupt status set 0b1 VREF1V2_OV_IS 8 Bit ADC2 Reference Overvoltage (ADC2, Channel 5) interrupt status 13 13 read-write OK no interrupt status set 0b0 FAIL at least one interrupt status set 0b1 VREF1V2_UV_IS 8 Bit ADC2 Reference Undervoltage (ADC2, Channel 5) interrupt status 12 12 read-write OK no interrupt status set 0b0 FAIL at least one interrupt status set 0b1 CLKWDT_IS Clock Watchdog Interrupt Status 10 10 read-only OK no interrupt status set 0b0 FAIL at least one interrupt status set 0b1 SYS_OT_IS System Overtemperature Shutdown (ADC2, Channel 8) interrupt status 9 9 read-write OK no interrupt status set 0b0 FAIL at least one interrupt status set 0b1 SYS_OTWARN_IS System Overtemperature Prewarning (ADC2, Channel 8) interrupt status 8 8 read-write OK no interrupt status set 0b0 FAIL at least one interrupt status set 0b1 HS_FAIL_IS High Side Driver Fail Interrupt Status 3 3 read-only OK no status set 0b0 FAIL at least one status set 0b1 DRV_FAIL_IS Gate Driver Fail Interrupt Status 2 2 read-only OK no status set 0b0 FAIL at least one status set 0b1 CP_FAIL_IS Charge Pump Fail Interrupt Status 1 1 read-only OK no status set 0b0 FAIL at least one status set 0b1 LIN_FAIL_IS LIN Fail Interrupt Status 0 0 read-only OK no status set 0b0 FAIL at least one status set 0b1 SYS_ISCLR System Interrupt Status Clear Register 0x14 32 VREF1V2_OV_SC 8 Bit ADC2 Reference Overvoltage Status Clear 29 29 write-only No clear 0b0 Clear 0b1 VREF1V2_UV_SC 8 Bit ADC2 Reference Undervoltage Status Clear 28 28 write-only No clear 0b0 Clear 0b1 SYS_OT_SC System Overtemperature Shutdown Status Clear 25 25 write-only No clear 0b0 Clear 0b1 SYS_OTWARN_SC System Overtemperature Prewarning Status Clear 24 24 write-only No clear 0b0 Clear 0b1 VREF1V2_OV_ISC 8 Bit ADC2 Reference Overvoltage Interrupt Status Clear 13 13 write-only No clear 0b0 Clear 0b1 VREF1V2_UV_ISC 8 Bit ADC2 Reference Undervoltage Interrupt Status Clear 12 12 write-only No clear 0b0 Clear 0b1 SYS_OT_ISC System Overtemperature Shutdown Interrupt Status Clear 9 9 write-only No clear 0b0 Clear 0b1 SYS_OTWARN_ISC System Overtemperature Prewarning Interrupt Status Clear 8 8 write-only No clear 0b0 Clear 0b1 SYS_SUPPLY_IRQ_CLR System Supply Interrupt Status Clear Register 0x24 32 VDD1V5_OV_SC VDDC Overvoltage Status clear 30 30 write-only No Clear 0b0 Clear 0b1 VDD5V_OV_SC VDDP Overvoltage Status clear 28 28 write-only No Clear 0b0 Clear 0b1 VDDEXT_OV_SC VDDEXT Overvoltage Status clear 27 27 write-only No Clear 0b0 Clear 0b1 VS_OV_SC VS Overvoltage Status clear 24 24 write-only No Clear 0b0 Clear 0b1 VDD1V5_UV_SC VDDC Undervoltage Status clear 22 22 write-only No Clear 0b0 Clear 0b1 VDD5V_UV_SC VDDP Undervoltage Status clear 20 20 write-only No Clear 0b0 Clear 0b1 VDDEXT_UV_SC VDDEXT Undervoltage Status clear 19 19 write-only No Clear 0b0 Clear 0b1 VS_UV_SC VS Undervoltage Status clear 16 16 write-only No Clear 0b0 Clear 0b1 VDD1V5_OV_ISC VDDC Overvoltage Interrupt Status clear 14 14 write-only No Clear 0b0 Clear 0b1 VDD5V_OV_ISC VDDP Overvoltage Interrupt Status clear 12 12 write-only No Clear 0b0 Clear 0b1 VDDEXT_OV_ISC VDDEXT Overvoltage Interrupt Status clear 11 11 write-only No Clear 0b0 Clear 0b1 VS_OV_ISC VS Overvoltage Interrupt Status clear 8 8 write-only No Clear 0b0 Clear 0b1 VDD1V5_UV_ISC VDDC Undervoltage Interrupt Status clear 6 6 write-only No Clear 0b0 Clear 0b1 VDD5V_UV_ISC VDDP Undervoltage Interrupt Status clear 4 4 write-only No Clear 0b0 Clear 0b1 VDDEXT_UV_ISC VDDEXT Undervoltage Interrupt Status clear 3 3 write-only No Clear 0b0 Clear 0b1 VS_UV_ISC VS Undervoltage Interrupt Status clear 0 0 write-only No Clear 0b0 Clear 0b1 SYS_SUPPLY_IRQ_CTRL System Supply Interrupt Control Register 0x20 32 VDD1V5_OV_IE VDDC Overvoltage Interrupt Enable 14 14 read-write Disable Interrupt is disabled 0b0 Enable Interrupt is enabled 0b1 VDD5V_OV_IE VDDP Overvoltage Interrupt Enable 12 12 read-write Disable Interrupt is disabled 0b0 Enable Interrupt is enabled 0b1 VDDEXT_OV_IE VDDEXT Overvoltage Interrupt Enable 11 11 read-write Disable Interrupt is disabled 0b0 Enable Interrupt is enabled 0b1 VS_OV_IE VS Overvoltage Interrupt Enable 8 8 read-write Disable Interrupt is disabled 0b0 Enable Interrupt is enabled 0b1 VDD1V5_UV_IE VDDC Undervoltage Interrupt Enable 6 6 read-write Disable Interrupt is disabled 0b0 Enable Interrupt is enabled 0b1 VDD5V_UV_IE VDDP Undervoltage Interrupt Enable 4 4 read-write Disable Interrupt is disabled 0b0 Enable Interrupt is enabled 0b1 VDDEXT_UV_IE VDDEXT Undervoltage Interrupt Enable 3 3 read-write Disable Interrupt is disabled 0b0 Enable Interrupt is enabled 0b1 VS_UV_IE VS Undervoltage Interrupt Enable 0 0 read-write Disable Interrupt is disabled 0b0 Enable Interrupt is enabled 0b1 SYS_SUPPLY_IRQ_STS System Supply Interrupt Status Register 0x1C 32 VDD1V5_OV_STS VDDC Overvoltage Status (ADC2 channel 6) 30 30 read-write No Overvoltage occurred 0b0 Overvoltage occurred 0b1 VDD5V_OV_STS VDDP Overvoltage Status (ADC2 channel 4) 28 28 read-write No Overvoltage occurred 0b0 Overvoltage occurred 0b1 VDDEXT_OV_STS VDDEXT Overvoltage Status (ADC2 channel 3) 27 27 read-write No Overvoltage occurred 0b0 Overvoltage occurred 0b1 VS_OV_STS VS Overvoltage Status (ADC2 channel 0) 24 24 read-write No Overvoltage occurred 0b0 Overvoltage occurred 0b1 VDD1V5_UV_STS VDDC Undervoltage Status (ADC2 channel 6) 22 22 read-write No Undervoltage occurred 0b0 Undervoltage occurred 0b1 VDD5V_UV_STS VDDP Undervoltage Status (ADC2 channel 4) 20 20 read-write No Undervoltage occurred 0b0 Undervoltage occurred 0b1 VDDEXT_UV_STS VDDEXT Undervoltage Status (ADC2 channel 3) 19 19 read-write No Undervoltage occurred 0b0 Undervoltage occurred 0b1 VS_UV_STS VS Undervoltage Status (ADC2 channel 0) 16 16 read-write No Undervoltage occurred 0b0 Undervoltage occurred 0b1 VDD1V5_OV_IS VDDC Overvoltage Interrupt Status (ADC2 channel 6) 14 14 read-write No Overvoltage Interrupt occurred 0b0 Overvoltage Interrupt occurred 0b1 VDD5V_OV_IS VDDP Overvoltage Interrupt Status (ADC2 channel 4) 12 12 read-write No Overvoltage Interrupt occurred 0b0 Overvoltage Interrupt occurred 0b1 VDDEXT_OV_IS VDDEXT Overvoltage Interrupt Status (ADC2 channel 3) 11 11 read-write No Overvoltage Interrupt occurred 0b0 Overvoltage Interrupt occurred 0b1 VS_OV_IS VS Overvoltage Interrupt Status (ADC2 channel 0) 8 8 read-write No Overvoltage Interrupt occurred 0b0 Overvoltage Interrupt occurred 0b1 VDD1V5_UV_IS VDDC Undervoltage Interrupt Status (ADC2 channel 6) 6 6 read-write No Undervoltage Interrupt occurred 0b0 Undervoltage Interrupt occurred 0b1 VDD5V_UV_IS VDDP Undervoltage Interrupt Status (ADC2 channel 4) 4 4 read-write No Undervoltage Interrupt occurred 0b0 Undervoltage Interrupt occurred 0b1 VDDEXT_UV_IS VDDEXT Undervoltage Interrupt Status (ADC2 channel 3) 3 3 read-write No Undervoltage Interrupt occurred 0b0 Undervoltage Interrupt occurred 0b1 VS_UV_IS VS Undervoltage Interrupt Status (ADC2 channel 0) 0 0 read-write No Undervoltage Interrupt occurred 0b0 Undervoltage Interrupt occurred 0b1 WDT1_TRIG WDT1 Watchdog Control Register 0x34 32 SOWCONF Short Open Window Configuration 6 7 read-write DIS Short Open Windows disabled 0x0 SOW1 one successive Short Open Window allowed 0x1 SOW2 two successive Short Open Windows allowed 0x2 SOW3 three successive Short Open Windows allowed 0x3 WDP_SEL Watchdog Period Selection and trigger 0 5 read-write SOW_TRIG trigger short open window 0x00 WP_1 Watchdog period 16 ms 0x01 WP_2 Watchdog period 32 ms 0x02 WP_3 Watchdog period 48 ms, ... 0x03 WP_63 Watchdog period 1008 ms 0x3F SSC1 SSC1 0x48024000 0x0 0x2000 registers INTISR8 Interrupt node 8: SSC1 8 BR Baud Rate Timer Reload Register 0x10 32 BR_VALUE Baud Rate Timer/Reload Register Value 0 15 read-write CON Control Register 0x04 32 BSY Busy Flag 28 28 read-only BE Baud Rate Error Flag 27 27 read-only NO error. 0b0 ERROR More than factor 2 or 0.5 between slave's actual and expected baud rate. 0b1 PE Phase Error Flag 26 26 read-only NO error. 0b0 ERROR Received data changes around sampling clock edge. 0b1 RE Receive Error Flag 25 25 read-only NO error. 0b0 ERROR Reception completed before the receive buffer was read. 0b1 TE Transmit Error Flag 24 24 read-only NO error. 0b0 ERROR Transfer starts with the slave's transmit buffer not being updated. 0b1 BC Bit Count Field 16 19 read-only EN Enable Bit 15 15 read-write Programming Mode Transmission and reception disabled. Access to control bits. 0b0 Operating Mode Transmission and reception enabled. Access to status flags and M/S control. 0b1 MS Master Select 14 14 read-write SLAVE Mode. Operate on shift clock received via SCLK. 0b0 MASTER Mode. Generate shift clock and output it via SCLK. 0b1 AREN Automatic Reset Enable 12 12 read-write N/A No additional action upon a baud rate error. 0b0 RESET The SSC is automatically reset upon a baud rate error. 0b1 BEN Baud Rate Error Enable 11 11 read-write IGNORE baud rate errors. 0b0 CHECK baud rate errors. 0b1 PEN Phase Error Enable 10 10 read-write IGNORE phase errors. 0b0 CHECK phase errors. 0b1 REN Receive Error Enable 9 9 read-write IGNORE receive errors. 0b0 CHECK receive errors. 0b1 TEN Transmit Error Enable 8 8 read-write IGNORE transmit errors. 0b0 CHECK transmit errors. 0b1 LB Loop Back Control 7 7 read-write NORMAL output. 0b0 LB Receive input is connected with transmit output (half-duplex mode). 0b1 PO Clock Polarity Control 6 6 read-write LOW Idle clock line is low, leading clock edge is low-to-high transition. 0b0 HIGH Idle clock line is high, leading clock edge is high-to-low transition. 0b1 PH Clock Phase Control 5 5 read-write SHIFT transmit data on the leading clock edge, latch on trailing edge. 0b0 LATCH receive data on leading clock edge, shift on trailing edge. 0b1 HB Heading Control 4 4 read-write LSB Transmit/Receive LSB First. 0b0 MSB Transmit/Receive MSB First. 0b1 BM Data Width Selection 0 3 read-write 2 Transfer Data Width is 2 (BM+1). 0b0001 16 Transfer Data Width is 16 bits (BM+1). 0b1111 ISRCLR Interrupt Status Register Clear 0x14 32 BECLR Baud Rate Error Flag Clear 11 11 write-only NO No error clear. 0b0 CLEAR Error clear. 0b1 PECLR Phase Error Flag Clear 10 10 write-only NO No error clear. 0b0 CLEAR Error clear. 0b1 RECLR Receive Error Flag Clear 9 9 write-only NO No error clear. 0b0 CLEAR Error clear. 0b1 TECLR Transmit Error Flag Clear 8 8 write-only NO No error clear. 0b0 CLEAR Error clear. 0b1 PISEL Port Input Select Register 0x00 32 GIS Global SSC12 Input Select 4 4 read-write value1 Inputs SSC12_S_SCK_0, SSC12_S_MTSR_0, and SSC12_M_MRST_0 are selected if CIS, SIS or MIS_O is 1. 0b0 value2 Inputs SSC12_S_SCK_1, SSC12_S_MTSR_1, and SSC12_M_MRST_1 are selected if CIS, SIS or MIS_O is 1. See 0b1 MIS_1 Master Mode Input Select Bit 1 (Master Mode only) 3 3 read-write value1 Default, Inputs selected according to MIS_0. 0b0 value2 Do not use, Connects to unused pins. 0b1 CIS Clock Input Select (Slave Mode only) 2 2 read-write SSCx_S_SCK (x = 1 or 2, dependant form current SSC), see . 0b0 SSC12_S_SCK_x (x=0 or 1). See . 0b1 SIS Slave Mode Input Select (Slave Mode only) 1 1 read-write SSCx_S_MTSR (x = 1 or 2, dependant form current SSC), see . 0b0 SSC12_S_MTSR_x (x=0 or 1). See . 0b1 MIS_0 Master Mode Input Select Bit 0 (Master Mode only) 0 0 read-write SSCx_M_MRST (x = 1 or 2, dependant form current SSC), see . 0b0 SSC12_M_MRST_x (x=0 or 1). See . 0b1 RB Receiver Buffer Register 0x0C 32 RB_VALUE Receive Data Register Value 0 15 read-only TB Transmitter Buffer Register 0x08 32 TB_VALUE Transmit Data Register Value 0 15 read-write SSC2 SSC2 0x48026000 0x0 0x2000 registers INTISR9 Interrupt node 9: SSC2 9 BR Baud Rate Timer Reload Register 0x10 32 BR_VALUE Baud Rate Timer/Reload Register Value 0 15 read-write CON Control Register 0x04 32 BSY Busy Flag 28 28 read-only BE Baud Rate Error Flag 27 27 read-only NO error. 0b0 ERROR More than factor 2 or 0.5 between slave's actual and expected baud rate. 0b1 PE Phase Error Flag 26 26 read-only NO error. 0b0 ERROR Received data changes around sampling clock edge. 0b1 RE Receive Error Flag 25 25 read-only NO error. 0b0 ERROR Reception completed before the receive buffer was read. 0b1 TE Transmit Error Flag 24 24 read-only NO error. 0b0 ERROR Transfer starts with the slave's transmit buffer not being updated. 0b1 BC Bit Count Field 16 19 read-only EN Enable Bit 15 15 read-write Programming Mode Transmission and reception disabled. Access to control bits. 0b0 Operating Mode Transmission and reception enabled. Access to status flags and M/S control. 0b1 MS Master Select 14 14 read-write SLAVE Mode. Operate on shift clock received via SCLK. 0b0 MASTER Mode. Generate shift clock and output it via SCLK. 0b1 AREN Automatic Reset Enable 12 12 read-write N/A No additional action upon a baud rate error. 0b0 RESET The SSC is automatically reset upon a baud rate error. 0b1 BEN Baud Rate Error Enable 11 11 read-write IGNORE baud rate errors. 0b0 CHECK baud rate errors. 0b1 PEN Phase Error Enable 10 10 read-write IGNORE phase errors. 0b0 CHECK phase errors. 0b1 REN Receive Error Enable 9 9 read-write IGNORE receive errors. 0b0 CHECK receive errors. 0b1 TEN Transmit Error Enable 8 8 read-write IGNORE transmit errors. 0b0 CHECK transmit errors. 0b1 LB Loop Back Control 7 7 read-write NORMAL output. 0b0 LB Receive input is connected with transmit output (half-duplex mode). 0b1 PO Clock Polarity Control 6 6 read-write LOW Idle clock line is low, leading clock edge is low-to-high transition. 0b0 HIGH Idle clock line is high, leading clock edge is high-to-low transition. 0b1 PH Clock Phase Control 5 5 read-write SHIFT transmit data on the leading clock edge, latch on trailing edge. 0b0 LATCH receive data on leading clock edge, shift on trailing edge. 0b1 HB Heading Control 4 4 read-write LSB Transmit/Receive LSB First. 0b0 MSB Transmit/Receive MSB First. 0b1 BM Data Width Selection 0 3 read-write 2 Transfer Data Width is 2 (BM+1). 0b0001 16 Transfer Data Width is 16 bits (BM+1). 0b1111 ISRCLR Interrupt Status Register Clear 0x14 32 BECLR Baud Rate Error Flag Clear 11 11 write-only NO No error clear. 0b0 CLEAR Error clear. 0b1 PECLR Phase Error Flag Clear 10 10 write-only NO No error clear. 0b0 CLEAR Error clear. 0b1 RECLR Receive Error Flag Clear 9 9 write-only NO No error clear. 0b0 CLEAR Error clear. 0b1 TECLR Transmit Error Flag Clear 8 8 write-only NO No error clear. 0b0 CLEAR Error clear. 0b1 PISEL Port Input Select Register 0x00 32 GIS Global SSC12 Input Select 4 4 read-write value1 Inputs SSC12_S_SCK_0, SSC12_S_MTSR_0, and SSC12_M_MRST_0 are selected if CIS, SIS or MIS_O is 1. 0b0 value2 Inputs SSC12_S_SCK_1, SSC12_S_MTSR_1, and SSC12_M_MRST_1 are selected if CIS, SIS or MIS_O is 1. See 0b1 MIS_1 Master Mode Input Select Bit 1 (Master Mode only) 3 3 read-write value1 Default, Inputs selected according to MIS_0. 0b0 value2 Do not use, Connects to unused pins. 0b1 CIS Clock Input Select (Slave Mode only) 2 2 read-write SSCx_S_SCK (x = 1 or 2, dependant form current SSC), see . 0b0 SSC12_S_SCK_x (x=0 or 1). See . 0b1 SIS Slave Mode Input Select (Slave Mode only) 1 1 read-write SSCx_S_MTSR (x = 1 or 2, dependant form current SSC), see . 0b0 SSC12_S_MTSR_x (x=0 or 1). See . 0b1 MIS_0 Master Mode Input Select Bit 0 (Master Mode only) 0 0 read-write SSCx_M_MRST (x = 1 or 2, dependant form current SSC), see . 0b0 SSC12_M_MRST_x (x=0 or 1). See . 0b1 RB Receiver Buffer Register 0x0C 32 RB_VALUE Receive Data Register Value 0 15 read-only TB Transmitter Buffer Register 0x08 32 TB_VALUE Transmit Data Register Value 0 15 read-write TIMER2 TIMER2 0x48004000 0x0 0x1000 registers CNT Timer 2 Count Register 0x10 32 T2H Timer 2 Value 8 15 read-write T2L Timer 2 Value 0 7 read-write CON Timer 2 Control Register 0x00 32 TF2 Timer 2 Overflow/Underflow Flag 7 7 read-only EXF2 Timer 2 External Flag 6 6 read-only EXEN2 Timer 2 External Enable Control 3 3 read-write DISABLED External events are disabled. 0b0 ENABLED External events are enabled in Capture/Reload Mode. 0b1 TR2 Timer 2 Start/Stop Control 2 2 read-write STOP Timer 2. 0b0 START Timer 2. 0b1 C_T2 Timer or Counter Select 1 1 read-write Timer function selected. 0b0 Count upon negative edge at pin T2. 0b1 CP_RL2 Capture/Reload Select 0 0 read-write Reload upon overflow or upon negative/positive transition at pin T2EX (when EXEN2 = 1). 0b0 Capture Timer 2 data register contents on the negative/positive transition at pin T2EX, provided EXEN2 = 1.The negative or positive transition at Pin T2EX is selected by bit EDGESEL. 0b1 CON1 Timer 2 Control Register 1 0x1C 32 TF2EN Overflow/Underflow Interrupt Enable 1 1 read-write DISABLE Overflow/underflow interrupt. 0b0 ENABLE Overflow/underflow interrupt. 0b1 EXF2EN External Interrupt Enable 0 0 read-write DISABLE External interrupt. 0b0 ENABLE External interrupt 0b1 ICLR Timer 2 Interrupt Clear Register 0x18 32 TF2CLR Overflow/Underflow Interrupt Clear Flag 7 7 write-only N/A Overflow/underflow interrupt is not cleared. 0b0 Clear Overflow/underflow interrupt 0b1 EXF2CLR External Interrupt Clear Flag 6 6 write-only N/A External interrupt is not cleared. 0b0 Clear External interrupt 0b1 MOD Timer 2 Mode Register 0x04 32 T2REGS Edge Select for Timer 2 External Start 7 7 read-write FALLING The falling edge at Pin T2EX is selected. 0b0 RISING The rising edge at Pin T2EX is selected. 0b1 T2RHEN Timer 2 External Start Enable 6 6 read-write DISABLED Timer 2 External Start is disabled. 0b0 ENABLED Timer 2 External Start is enabled. 0b1 EDGESEL Edge Select in Capture Mode/Reload Mode 5 5 read-write FALLING The falling edge at Pin T2EX is selected. 0b0 RISING The rising edge at Pin T2EX is selected. 0b1 PREN Prescaler Enable 4 4 read-write DISABLED Prescaler is disabled and the 2 or 12 divider takes effect. 0b0 ENABLED Prescaler is enabled (see T2PRE bit) and the 2 or 12 divider is bypassed. 0b1 T2PRE Timer 2 Prescaler Bit 1 3 read-write DIV1 fT2 = fsys 0b000 DIV2 fT2 = fsys / 2 0b001 DIV4 DfT2 = fsys / 4 0b010 DIV8 fT2 = fsys / 8 0b011 DIV16 fT2 = fsys / 16 0b100 DIV32 fT2 = fsys / 32 0b101 DIV64 fT2 = fsys / 64 0b110 DIV128 fT2 = fsys / 128 0b111 DCEN Up/Down Counter Enable 0 0 read-write DISABLED Up/Down Counter function is disabled 0b0 ENABLED Up/Down Counter function is enabled and controlled by pin T2EX (Up = 1, Down = 0) 0b1 RC Timer 2 Reload/Capture Register 0x08 32 RCH2 Reload/Capture Value 8 15 read-write RCL2 Reload/Capture Value 0 7 read-write TIMER21 TIMER21 0x48005000 0x0 0x1000 registers CNT Timer 2 Count Register 0x10 32 T2H Timer 2 Value 8 15 read-write T2L Timer 2 Value 0 7 read-write CON Timer 2 Control Register 0x00 32 TF2 Timer 2 Overflow/Underflow Flag 7 7 read-only EXF2 Timer 2 External Flag 6 6 read-only EXEN2 Timer 2 External Enable Control 3 3 read-write DISABLED External events are disabled. 0b0 ENABLED External events are enabled in Capture/Reload Mode. 0b1 TR2 Timer 2 Start/Stop Control 2 2 read-write STOP Timer 2. 0b0 START Timer 2. 0b1 C_T2 Timer or Counter Select 1 1 read-write Timer function selected. 0b0 Count upon negative edge at pin T2. 0b1 CP_RL2 Capture/Reload Select 0 0 read-write Reload upon overflow or upon negative/positive transition at pin T2EX (when EXEN2 = 1). 0b0 Capture Timer 2 data register contents on the negative/positive transition at pin T2EX, provided EXEN2 = 1.The negative or positive transition at Pin T2EX is selected by bit EDGESEL. 0b1 CON1 Timer 2 Control Register 1 0x1C 32 TF2EN Overflow/Underflow Interrupt Enable 1 1 read-write DISABLE Overflow/underflow interrupt. 0b0 ENABLE Overflow/underflow interrupt. 0b1 EXF2EN External Interrupt Enable 0 0 read-write DISABLE External interrupt. 0b0 ENABLE External interrupt 0b1 ICLR Timer 2 Interrupt Clear Register 0x18 32 TF2CLR Overflow/Underflow Interrupt Clear Flag 7 7 write-only N/A Overflow/underflow interrupt is not cleared. 0b0 Clear Overflow/underflow interrupt 0b1 EXF2CLR External Interrupt Clear Flag 6 6 write-only N/A External interrupt is not cleared. 0b0 Clear External interrupt 0b1 MOD Timer 2 Mode Register 0x04 32 T2REGS Edge Select for Timer 2 External Start 7 7 read-write FALLING The falling edge at Pin T2EX is selected. 0b0 RISING The rising edge at Pin T2EX is selected. 0b1 T2RHEN Timer 2 External Start Enable 6 6 read-write DISABLED Timer 2 External Start is disabled. 0b0 ENABLED Timer 2 External Start is enabled. 0b1 EDGESEL Edge Select in Capture Mode/Reload Mode 5 5 read-write FALLING The falling edge at Pin T2EX is selected. 0b0 RISING The rising edge at Pin T2EX is selected. 0b1 PREN Prescaler Enable 4 4 read-write DISABLED Prescaler is disabled and the 2 or 12 divider takes effect. 0b0 ENABLED Prescaler is enabled (see T2PRE bit) and the 2 or 12 divider is bypassed. 0b1 T2PRE Timer 2 Prescaler Bit 1 3 read-write DIV1 fT2 = fsys 0b000 DIV2 fT2 = fsys / 2 0b001 DIV4 DfT2 = fsys / 4 0b010 DIV8 fT2 = fsys / 8 0b011 DIV16 fT2 = fsys / 16 0b100 DIV32 fT2 = fsys / 32 0b101 DIV64 fT2 = fsys / 64 0b110 DIV128 fT2 = fsys / 128 0b111 DCEN Up/Down Counter Enable 0 0 read-write DISABLED Up/Down Counter function is disabled 0b0 ENABLED Up/Down Counter function is enabled and controlled by pin T2EX (Up = 1, Down = 0) 0b1 RC Timer 2 Reload/Capture Register 0x08 32 RCH2 Reload/Capture Value 8 15 read-write RCL2 Reload/Capture Value 0 7 read-write UART1 UART1 0x48020000 0x0 0x2000 registers INTISR10 Interrupt node 10: UART1(ASC,LIN), Timer2 10 SBUF Serial Data Buffer 0x04 32 VAL Serial Interface Buffer Register 0 7 read-write SCON Serial Channel Control Register 0x00 32 SM0 Serial Port Operating Mode Selection 7 7 read-write SM1 Serial Port Operating Mode Selection 6 6 read-write SM2 Enable Serial Port Multiprocessor Communication in Modes 2 and 3 5 5 read-write REN Enable Receiver of Serial Port 4 4 read-write Disable Serial reception is disabled. 0b0 Enable Serial reception is enabled. 0b1 TB8 Serial Port Transmitter Bit 9 3 3 read-write RB8 Serial Port Receiver Bit 9 2 2 read-write TI Transmit Interrupt Flag 1 1 read-write RI Receive Interrupt Flag 0 0 read-write SCONCLR Serial Channel Control Clear Register 0x08 32 RB8CLR SCON.RB8 Clear Flag 2 2 write-only No Clear RB8 Flag is not cleared. 0b0 Clear RB8 Flag is cleared. 0b1 TICLR SCON.TI Clear Flag 1 1 write-only No Clear TI Flag is not cleared. 0b0 Clear TI Flag is cleared. 0b1 RICLR SCON.RI Clear Flag 0 0 write-only No Clear RI Flag is not cleared. 0b0 Clear RI Flag is cleared. 0b1 UART2 UART2 0x48022000 0x0 0x2000 registers INTISR11 Interrupt node 11: UART2, Timer21 11 SBUF Serial Data Buffer 0x04 32 VAL Serial Interface Buffer Register 0 7 read-write SCON Serial Channel Control Register 0x00 32 SM0 Serial Port Operating Mode Selection 7 7 read-write SM1 Serial Port Operating Mode Selection 6 6 read-write SM2 Enable Serial Port Multiprocessor Communication in Modes 2 and 3 5 5 read-write REN Enable Receiver of Serial Port 4 4 read-write Disable Serial reception is disabled. 0b0 Enable Serial reception is enabled. 0b1 TB8 Serial Port Transmitter Bit 9 3 3 read-write RB8 Serial Port Receiver Bit 9 2 2 read-write TI Transmit Interrupt Flag 1 1 read-write RI Receive Interrupt Flag 0 0 read-write SCONCLR Serial Channel Control Clear Register 0x08 32 RB8CLR SCON.RB8 Clear Flag 2 2 write-only No Clear RB8 Flag is not cleared. 0b0 Clear RB8 Flag is cleared. 0b1 TICLR SCON.TI Clear Flag 1 1 write-only No Clear TI Flag is not cleared. 0b0 Clear TI Flag is cleared. 0b1 RICLR SCON.RI Clear Flag 0 0 write-only No Clear RI Flag is not cleared. 0b0 Clear RI Flag is cleared. 0b1