S6E2CC 1.1 S6E2CC 8 32 32 read-write 0x00000000 0x00000000 FLASH_IF Flash Memory FLASH_IF 0x40000000 0x0 0xC registers 0x10 0x8 registers 0x20 0xC registers 0x30 0x4 registers 0x100 0x4 registers 0x110 0x10 registers FLASH 119 FASZR Flash Access Size Register 0x00 32 read-write 0x00000002 0x00000003 ASZ Access Size 0 1 read-write FRWTR Flash Read Wait Register 0x04 32 read-write 0x00000002 0x00000003 RWT Read Wait Cycle 0 1 read-write FSTR Flash Status Register 0x08 32 read-only 0x00000000 0x00000007 ERR Flash ECC Error 2 2 read-write HNG Flash Hang 1 1 read-only RDY Flash Rdy 0 0 read-only FSYNDN Flash Sync Down Register 0x10 32 read-write 0x00000000 0x00000007 SD Sync Down 0 2 read-write FBFCR Flash Buffer Control Register 0x14 32 read-write 0x00000000 0x00000003 BS Buffer Status 1 1 read-only BE Buffer Enable 0 0 read-write FICR Flash Interrupt Control Register 0x20 32 read-write 0x00000000 0x00000007 ERRIE Flash ECC Error Interrupt Enable 2 2 read-write HANGIE Flash HANG Interrupt Enable 1 1 read-write RDYIE Flash RDY Interrupt Enable 0 0 read-write FISR Flash Interrupt Status Register 0x24 32 read-write 0x00000000 0x00000007 ERRIF Flash ECC Error Interrupt Flag 2 2 read-only HANGIF Flash HANG Interrupt Flag 1 1 read-only RDYIF Flash RDY Interrupt Flag 0 0 read-only FICLR Flash Interrupt Clear Register 0x28 32 write-only 0x00000000 0x00000007 ERRIC Flash ECC Error Interrupt Clear 2 2 read-write HANGIC Flash HANG Interrupt Clear 1 1 read-write RDYIC Flash RDY Interrupt Clear 0 0 read-write DFCTRLR Dual Flash mode Control Register 0x30 32 read-write 0x00000000 0xFFFF0003 WKEY Write Key 16 31 read-write RME Re-Map Enable 1 1 read-write DFE Dual Flash mode Enable 0 0 read-write CRTRMM CR Trimming Data Mirror Register 0x100 32 read-only 0x00000000 0x00000000 TTRMM Temperature CR Trimming Data Mirror 16 20 read-only TRMM CR Trimming Data Mirror 0 9 read-only FGPDM1 Flash General Purpose Data Mirror Register1 0x110 32 read-only 0x00000000 0xFFFFFFFF GPD1 General Purpose Data1 0 31 read-only FGPDM2 Flash General Purpose Data Mirror Register2 0x114 32 read-only 0x00000000 0xFFFFFFFF GPD2 General Purpose Data2 0 31 read-only FGPDM3 Flash General Purpose Data Mirror Register3 0x118 32 read-only 0x00000000 0xFFFFFFFF GPD3 General Purpose Data3 0 31 read-only FGPDM4 Flash General Purpose Data Mirror Register4 0x11C 32 read-only 0x00000000 0xFFFFFFFF GPD4 General Purpose Data4 0 31 read-only DUALFLASH_IF Dual Flash Memory DUALFLASH_IF 0x40000400 0x0 0x4 registers 0x4 0x4 registers 0x8 0x4 registers DFASZR Dual Flash Access Size Register 0x00 32 read-write 0x00000002 0x00000003 DASZ Dual Flash Access Size 0 1 read-write DFRWTR Dual Flash Read Wait Register 0x04 32 read-write 0x00000003 0x00000003 DRWT Dual Flash Read Wait Cycle 0 1 read-write DFSTR Dual Flash ECC Error 0x08 32 read-write 0x00000000 0x00000007 DFERR Dual Flash ECC Error 2 2 read-write DFHNG Dual Flash Hang 1 1 read-only DFRDY Dual Flash Rdy 0 0 read-only UNIQUE_ID Unique ID UNIQUE_ID 0x40000200 0x0 0x4 registers 0x4 0x4 registers UIDR0 Unique ID Register 0 0x0 32 read-only 0x00000000 0xFFFFFFF0 UID Unique ID 27 through 0 4 31 read-only UIDR1 Unique ID Register 1 0x4 32 read-only 0x00000000 0x00001FFF UID Unique ID 40 through 28 0 12 read-only ECC_CAPTURE ECC Capture Address ECC_CAPTURE 0x40000300 0x0 0x4 registers FERRAD Flash ECC Error Address Capture Register 0x0 32 read-only 0x00000000 0x007FFFFF ERRAD Flash ECC Error Address Capture 0 22 read-only CRG Clock Unit Registers CRG 0x40010000 0x0 0x70 registers CSV 0 TIM 59 SCM_CTL System Clock Mode Control Register 0x0 32 read-write 0x00 0xFA RCS Master clock switch control bits 5 7 read-write PLLE PLL oscillation enable bit 4 4 read-write SOSCE Sub clock oscillation enable bit 3 3 read-write MOSCE Main clock oscillation enable bit 1 1 read-write SCM_STR System Clock Mode Status Register 0x4 32 read-only 0x00 0xFA RCM Master clock selection bits 5 7 read-only PLRDY PLL oscillation stable bit 4 4 read-only SORDY Sub clock oscillation stable bit 3 3 read-only MORDY Main clock oscillation stable bit 1 1 read-only STB_CTL Standby Mode Control Register 0x8 32 read-write 0x00000000 0xFFFF0017 KEY Standby mode control write control bit 16 31 read-write SPL Standby pin level setting bit 4 4 read-write DSTM Deep standby mode select bit 2 2 read-write STM Standby mode selection bit 0 1 read-write RST_STR Reset Cause Register 0xC 32 read-only 0x0001 0x01F3 SRST Software reset flag 8 8 read-only FCSR Flag for anomalous frequency detection reset 7 7 read-only CSVR Clock failure detection reset flag 6 6 read-only HWDT Hardware watchdog reset flag 5 5 read-only SWDT Software watchdog reset flag 4 4 read-only INITX INITX pin input reset flag 1 1 read-only PONR Power-on reset/low-voltage detection reset flag 0 0 read-only BSC_PSR Base Clock Prescaler Register 0x10 32 read-write 0x00 0x07 BSR Base clock frequency division ratio setting bit 0 2 read-write APBC0_PSR APB0 Prescaler Register 0x14 32 read-write 0x00 0x03 APBC0 APB0 bus clock frequency division ratio setting bit 0 1 read-write APBC1_PSR APB1 Prescaler Register 0x18 32 read-write 0x80 0x93 APBC1EN APB1 clock enable bit 7 7 read-write APBC1RST APB1 bus reset control bit 4 4 read-write APBC1 APB1 bus clock frequency division ratio setting bit 0 1 read-write APBC2_PSR APB2 Prescaler Register 0x1C 32 read-write 0x80 0x93 APBC2EN APB2 clock enable bit 7 7 read-write APBC2RST APB2 bus reset control bit 4 4 read-write APBC2 APB2 bus clock frequency division ratio setting bit 0 1 read-write SWC_PSR Software Watchdog Clock Prescaler Register 0x20 32 read-write 0x00 0x03 SWDS Software watchdog clock frequency division ratio setting bit 0 1 read-write TTC_PSR Trace Clock Prescaler Register 0x28 32 read-write 0x00 0x03 TTC Trace clock frequency division ratio setting bit 0 1 read-write CSW_TMR Clock Stabilization Wait Time Register 0x30 32 read-write 0x00 0xFF SOWT Sub clock stabilization wait time setup bit 4 7 read-write MOWT Main clock stabilization wait time setup bit 0 3 read-write PSW_TMR PLL Clock Stabilization Wait Time Setup Register 0x34 32 read-write 0x00 0x17 PINC PLL input clock select bit 4 4 read-write POWT PLL clock stabilization wait time setup bit 0 2 read-write PLL_CTL1 PLL Control Register 1 0x38 32 read-write 0x00 0xFF PLLK PLL input clock frequency division ratio setting bit 4 7 read-write PLLM PLL VCO clock frequency division ratio setting bit 0 3 read-write PLL_CTL2 PLL Control Register 2 0x3C 32 read-write 0x00 0x3F PLLN PLL feedback frequency division ratio setting bit 0 5 read-write CSV_CTL CSV control register 0x40 32 read-write 0x7003 0x7303 FCD FCS count cycle setting bits 12 14 read-write FCSRE FCS reset output enable bit 9 9 read-write FCSDE FCS function enable bit 8 8 read-write SCSVE Sub CSV function enable bit 1 1 read-write MCSVE Main CSV function enable bit 0 0 read-write CSV_STR CSV status register 0x44 32 read-only 0x00 0x03 SCMF Sub clock failure detection flag 1 1 read-only MCMF Main clock failure detection flag 0 0 read-only FCSWH_CTL Frequency detection window setting register 0x48 32 read-write 0xFFFF 0xFFFF FWH Frequency detection window setting bits (Upper) 0 15 read-write FCSWL_CTL Frequency detection window setting register 0x4C 32 read-write 0x0000 0xFFFF FWL Frequency detection window setting bits (Lower) 0 15 read-write FCSWD_CTL Frequency detection counter register 0x50 32 read-only 0x0000 0xFFFF FWD Frequency detection count data 0 15 read-only DBWDT_CTL Debug Break Watchdog Timer Control Register 0x54 32 read-write 0x00 0xA0 DPHWBE HW-WDG debug mode break bit 7 7 read-write DPSWBE SW-WDG debug mode break bit 5 5 read-write INT_ENR Interrupt Enable Register 0x60 32 read-write 0x00 0x27 FCSE Anomalous frequency detection interrupt enable bit 5 5 read-write PCSE PLL oscillation stabilization completion interrupt enable bit 2 2 read-write SCSE Sub oscillation stabilization completion interrupt enable bit 1 1 read-write MCSE Main oscillation stabilization completion interrupt enable bit 0 0 read-write INT_STR Interrupt Status Register 0x64 32 read-only 0x00 0x27 FCSI Anomalous frequency detection interrupt status bit 5 5 read-only PCSI PLL oscillation stabilization completion interrupt status bit 2 2 read-only SCSI Sub oscillation stabilization completion interrupt status bit 1 1 read-only MCSI Main oscillation stabilization completion interrupt status bit 0 0 read-only INT_CLR Interrupt Clear Register 0x68 32 write-only 0x00 0x27 FCSC Anomalous frequency detection interrupt cause clear bit 5 5 write-only PCSC PLL oscillation stabilization completion interrupt cause clear bit 2 2 write-only SCSC Sub oscillation stabilization completion interrupt cause clear bit 1 1 write-only MCSC Main oscillation stabilization completion interrupt cause clear bit 0 0 write-only CRTRIM CR Trimming Registers CRTRIM 0x4002E000 0x0 0x1 registers 0x4 0x2 registers 0x8 0x1 registers 0xC 0x4 registers MCR_PSR High-speed CR oscillation Frequency Division Setup Register 0x0 8 read-write 0x01 0x07 CSR High-speed CR oscillation frequency division ratio setting bits 0 2 read-write MCR_FTRM High-speed CR oscillation Frequency Trimming Register 0x4 16 read-write 0x01EF 0x03FF TRD Frequency trimming setup bits 0 9 read-write MCR_TTRM High-speed CR oscillation Temperature Trimming Register 0x8 8 read-write 0x10 0x1F TRT Temperature trimming setup bits 0 4 read-write MCR_RLR High-Speed CR Oscillation Register Write-Protect Register 0xC 32 read-write 0x00000001 0xFFFFFFFF TRMLCK Register write-protect bits 0 31 read-write SWWDT Software Watchdog Timer SWWDT 0x40012000 0x0 0x4 registers 0x4 0x4 registers 0x8 0x1 registers 0xC 0x4 registers 0x10 0x1 registers 0x18 0x1 registers 0xC00 0x4 registers SWDT 1 WDOGLOAD Software Watchdog Timer Load Register 0x0 32 read-write 0xFFFFFFFF 0xFFFFFFFF WDOGVALUE Software Watchdog Timer Value Register 0x4 32 read-only 0xFFFFFFFF 0xFFFFFFFF WDOGCONTROL Software Watchdog Timer Control Register 0x8 8 read-write 0x00 0x1F SPM Software Watchdog window watchdog mode enable bit 4 4 read-write TWD Timing window setting bit of the software watchdog 2 3 read-write RESEN Reset enable bit of the software watchdog 1 1 read-write INTEN Interrupt and counter enable bit of the software watchdog 0 0 read-write WDOGINTCLR Software Watchdog Timer Clear Register 0xC 32 read-write 0xFFFFFFFF 0xFFFFFFFF WDOGRIS Software Watchdog Timer Interrupt Status Register 0x10 8 read-only 0x00 0x01 RIS Software watchdog interrupt status bit 0 0 read-only WDOGSPMC Software Watchdog Timer Window Watchdog Mode Control Register 0x18 8 read-write 0x00 0x01 TGR Software watchdog trigger type bit 0 0 read-only WDOGLOCK Software Watchdog Timer Lock Register 0xC00 32 read-write 0x00000000 0xFFFFFFFF HWWDT Hardware Watchdog Timer HWWDT 0x40011000 0x0 0x4 registers 0x4 0x4 registers 0x8 0x1 registers 0xC 0x1 registers 0x10 0x1 registers 0xC00 0x4 registers WDG_LDR Hardware Watchdog Timer Load Register 0x0 32 read-write 0x0000FFFF 0xFFFFFFFF WDG_VLR Hardware Watchdog Timer Value Register 0x4 32 read-only 0x00000000 0xFFFFFFFF WDG_CTL Hardware Watchdog Timer Control Register 0x8 8 read-write 0x03 0x03 RESEN Hardware watchdog reset enable bit 1 1 read-write INTEN Hardware watchdog interrupt and counter enable bit 0 0 read-write WDG_ICL Hardware Watchdog Timer Clear Register 0xC 8 read-write 0xFF 0x00 WDG_RIS Hardware Watchdog Timer Interrupt Status Register 0x10 8 read-only 0xFF 0x00 RIS Hardware watchdog interrupt status bit 0 0 read-only WDG_LCK Hardware Watchdog Timer Lock Register 0xC00 32 read-write 0x00000001 0xFFFFFFFF DTIM Dual Timer DTIM 0x40015000 0x0 0x1C registers 0x20 0x1C registers DT1_2 47 TIMER1LOAD Load Register DualTimer1 0x0 32 read-write 0x00000000 0xFFFFFFFF TIMER1VALUE Value Register 0x4 32 read-only 0xFFFFFFFF 0xFFFFFFFF TIMER1CONTROL Control Register 0x8 32 read-write 0x00000020 0x000000EF TimerEn Enable bit 7 7 read-write TimerMode Mode bit 6 6 read-write IntEnable Interrupt enable bit 5 5 read-write TimerPre Prescale bits 2 3 read-write TimerSize Counter size bit 1 1 read-write OneShot One-shot mode bit 0 0 read-write TIMER1INTCLR Interrupt Clear Register 0xC 32 write-only 0x00000000 0x00000000 TIMER1RIS Interrupt Status Register 0x10 32 read-only 0x00000000 0x00000001 TIMER1RIS Interrupt Status Register bit 0 0 read-only TIMER1MIS Masked Interrupt Status Register 0x14 32 read-only 0x00000000 0x00000001 TIMER1MIS Masked Interrupt Status bit 0 0 read-only TIMER1BGLOAD Background Load Register 0x18 32 read-write 0x00000000 0xFFFFFFFF TIMER2LOAD Load Register 0x20 TIMER2VALUE Value Register 0x24 TIMER2CONTROL Control Register 0x28 TIMER2INTCLR Interrupt Clear Register 0x2C TIMER2RIS Interrupt Status Register 0x30 TIMER2MIS Masked Interrupt Status Register 0x34 TIMER2BGLOAD Background Load Register 0x38 MFT0 Multifunction Timer 0 MFT0 0x40020000 0x0 0x1ED registers WFG0_DTIF0 21 FRT0_PEAK 24 FRT0_ZERO 25 ICU0 26 OCU0 27 FRT_TCCP0 FRT-ch.0 Cycle Setting Register 0x142 16 read-write 0xFFFF 0xFFFF FRT_TCDT0 FRT-ch.0 Count Value Register 0x146 16 read-write 0x0000 0xFFFF FRT_TCSA0 FRT-ch.0 Control Register A 0x148 16 read-write 0x0040 0xE3FF ECKE Uses an external input clock (FRCK) as FRT's count clock 15 15 read-write IRQZF zero interrupt flag 14 14 read-write IRQZE "Generates interrupt, when ""1"" is set to TCSA.IRQZF" 13 13 read-write ICLR interrupt flag 9 9 read-write ICRE "Generates interrupt when ""1"" is set to TCSA.ICLR" 8 8 read-write BFE Enables TCCP's buffer function 7 7 read-write STOP Puts FRT in stopping state 6 6 read-write MODE FRT's count mode 5 5 read-write SCLR FRT operation state initialization request 4 4 write-only CLK FRT clock cycle 0 3 read-write FRT_TCSC0 FRT-ch.0 Control Register C 0x14A 16 read-write 0x0000 0xFFFF MSPC Current counter value of a Peak value detection mask counter 12 15 read-only MSZC Current counter value of a Zero value detection mask counter 8 11 read-only MSPI Masked Peak value detection number 4 7 read-write MSZI Masked Zero value detection number 0 3 read-write FRT_TCCP1 FRT-ch.1 Cycle Setting Register 0x14E FRT_TCDT1 FRT-ch.1 Count Value Register 0x152 FRT_TCSA1 FRT-ch.1 Control Register A 0x154 FRT_TCSC1 FRT-ch.1 Control Register C 0x156 FRT_TCCP2 FRT-ch.2 Cycle Setting Register 0x15A FRT_TCDT2 FRT-ch.2 Count Value Register 0x15E FRT_TCSA2 FRT-ch.2 Control Register A 0x160 FRT_TCSC2 FRT-ch.2 Control Register C 0x162 FRT_TCAL FRT Simultaneous Start Control Register 0x164 32 read-write 0x00000000 0x0000FFFF SCLR22 Mirror register of the SCLR bit located in TCSA2 register of MFT-unit2 24 24 write-only SCLR21 Mirror register of the SCLR bit located in TCSA1 register of MFT-unit2 23 23 write-only SCLR20 Mirror register of the SCLR bit located in TCSA0 register of MFT-unit2 22 22 write-only SCLR12 Mirror register of the SCLR bit located in TCSA2 register of MFT-unit1 21 21 write-only SCLR11 Mirror register of the SCLR bit located in TCSA1 register of MFT-unit1 20 20 write-only SCLR10 Mirror register of the SCLR bit located in TCSA0 register of MFT-unit1 19 19 write-only SCLR02 Mirror register of the SCLR bit located in TCSA2 register of MFT-unit0 18 18 write-only SCLR01 Mirror register of the SCLR bit located in TCSA1 register of MFT-unit0 17 17 write-only SCLR00 Mirror register of the SCLR bit located in TCSA0 register of MFT-unit0 16 16 write-only STOP22 Mirror register of the STOP bit located in TCSA2 register of MFT-unit2 8 8 read-write STOP21 Mirror register of the STOP bit located in TCSA1 register of MFT-unit2 7 7 read-write STOP20 Mirror register of the STOP bit located in TCSA0 register of MFT-unit2 6 6 read-write STOP12 Mirror register of the STOP bit located in TCSA2 register of MFT-unit1 5 5 read-write STOP11 Mirror register of the STOP bit located in TCSA1 register of MFT-unit1 4 4 read-write STOP10 Mirror register of the STOP bit located in TCSA0 register of MFT-unit1 3 3 read-write STOP02 Mirror register of the STOP bit located in TCSA2 register of MFT-unit0 2 2 read-write STOP01 Mirror register of the STOP bit located in TCSA1 register of MFT-unit0 1 1 read-write STOP00 Mirror register of the STOP bit located in TCSA0 register of MFT-unit0 0 0 read-write OCU_OCCP0 OCU ch.0 Compare Value Store Register 0x102 16 read-write 0x0000 0xFFFF OCU_OCCP1 OCU ch.1 Compare Value Store Register 0x106 OCU_OCCP2 OCU ch.2 Compare Value Store Register 0x10A OCU_OCCP3 OCU ch.3 Compare Value Store Register 0x10E OCU_OCCP4 OCU ch.4 Compare Value Store Register 0x112 OCU_OCCP5 OCU ch.5 Compare Value Store Register 0x116 OCU_OCSA10 OCU ch.0/1 Control Register A 0x118 8 read-write 0x00 0xF3 IOP1 Indicates that a match has already been detected between FRT's count value and OCCP(1) value at OCU ch.(1). 7 7 read-write IOP0 Indicates that a match has already been detected between FRT's count value and OCCP(0) value at OCU ch.(0). 6 6 read-write IOE1 "Generates interrupt, when ""1"" is set to OCSA.IOP1" 5 5 read-write IOE0 "Generates interrupt, when ""1"" is set to OCSA.IOP0" 4 4 read-write CST1 Enables the operation of OCU ch.(1) 1 1 read-write CST0 Enables the operation of OCU ch.(0) 0 0 read-write OCU_OCSB10 OCU ch.0/1 Control Register B 0x119 8 read-write 0x00 0x93 FM4 selects FM4 mode for operating mode 7 7 read-write CMOD selects OCU's operation mode in combination with OCSC.MOD0 to MOD5 4 4 read-write OTD1 Indicates that the RT(1) output pin is in the High-level output state. 1 1 read-write OTD0 Indicates that the RT(0) output pin is in the High-level output state. 0 0 read-write OCU_OCSD10 OCU ch.0/1 Control Register D 0x11A 16 read-write 0x0000 0x3FFF OFEX1 extends the matching determination conditions of the connected FRT with the OCCP(1) register value 13 13 read-write OFEX0 extends the matching determination conditions of the connected FRT with the OCCP(0) register value 12 12 read-write OEBM1 sets the linked transfer settings with the FRT interrupt mask counter 11 11 read-write OEBM0 sets the linked transfer settings with the FRT interrupt mask counter 10 10 read-write OPBM1 sets the linked transfer settings with the FRT interrupt mask counter 9 9 read-write OPBM0 sets the linked transfer settings with the FRT interrupt mask counter 8 8 read-write OCSE1BUFE Enable buffer register function of OCSE(1) 6 7 read-write OCSE0BUFE Enable buffer register function of OCSE(0) 4 5 read-write OCCP1BUFE Enable buffer register function of OCCP(1) 2 3 read-write OCCP0BUFE Enable buffer register function of OCCP(0) 0 1 read-write OCU_OCSA32 OCU ch.2/3 Control Register A 0x11C OCU_OCSB32 OCU ch.2/3 Control Register B 0x11D OCU_OCSD32 OCU ch.2/3 Control Register D 0x11E OCU_OCSA54 OCU ch.4/5 Control Register A 0x120 OCU_OCSB54 OCU ch.4/5 Control Register B 0x121 OCU_OCSD54 OCU ch.4/5 Control Register D 0x122 OCU_OCSC OCU Control Register C 0x124 16 read-write 0x0000 0x3F00 MOD5 OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD 13 13 read-write MOD4 OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD 12 12 read-write MOD3 OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD 11 11 read-write MOD2 OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD 10 10 read-write MOD1 OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD 9 9 read-write MOD0 OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD 8 8 read-write OCU_OCSE0 OCU ch.0 Control Register E 0x128 16 read-write 0x0000 0xFFFF OCSE specify the setting conditions of the OCU's matching detection register (IOP0) 0 15 read-write OCU_OCSE1 OCU ch.1 Control Register E 0x12C 32 read-write 0x00000000 0xFFFFFFFF OCSE specify the setting conditions of the OCU's matching detection register (IOP0/IOP1) 0 31 read-write OCU_OCSE2 OCU ch.2 Control Register E 0x130 OCU_OCSE3 OCU ch.3 Control Register E 0x134 OCU_OCSE4 OCU ch.4 Control Register E 0x138 OCU_OCSE5 OCU ch.5 Control Register E 0x13C OCU_OCFS10 OCU ch.0/1 Connecting FRT Select Register 0x168 8 read-write 0x00 0xFF FSO1 Connects FRT ch.x to OCU ch.1 4 7 read-write FSO0 Connects FRT ch.x to OCU ch.0 0 3 read-write OCU_OCFS32 OCU ch.2/3 Connecting FRT Select Register 0x169 OCU_OCFS54 OCU ch.4/5 Connecting FRT Select Register 0x16A WFG_WFTF10 Pulse Counter Value Register for WFG ch.0/1 0x18E 16 read-write 0x0000 0xFFFF WFG_WFTA10 WFG Timer Value Register for WFG ch.0/1 0x190 16 read-write 0x0000 0xFFFF WFG_WFTB10 WFG Timer Value Register for WFG ch.0/1 0x192 16 read-write 0x0000 0xFFFF WFG_WFTF32 Pulse Counter Value Register for WFG ch.2/3 0x196 16 read-write 0x0000 0xFFFF WFG_WFTA32 WFG Timer Value Register for WFG ch.2/3 0x198 16 read-write 0x0000 0xFFFF WFG_WFTB32 WFG Timer Value Register for WFG ch.2/3 0x19A 16 read-write 0x0000 0xFFFF WFG_WFTF54 Pulse Counter Value Register for WFG ch.4/5 0x19E 16 read-write 0x0000 0xFFFF WFG_WFTA54 WFG Timer Value Register for WFG ch.4/5 0x1A0 16 read-write 0x0000 0xFFFF WFG_WFTB54 WFG Timer Value Register for WFG ch.4/5 0x1A2 16 read-write 0x0000 0xFFFF WFG_WFSA10 WFG Control Register A for WFG ch.0/1 0x1A4 16 read-write 0x0000 0x3FFF DMOD 1specifies polarity for RTO(0) and RTO(1) signal outputs 12 13 read-write PGEN specifies how to reflect the CH_PPG signal for each channel of the WFG 10 11 read-write PSEL select the PPG timer unit to be used for each channel of the WFG 8 9 read-write GTEN selects the output conditions for the CH_GATE output signal of the WFG 6 7 read-write TMD select the WFG's operation mode 3 5 read-write DCK set the count clock cycle for the WFG timer and Pulse counter 0 2 read-write WFG_WFSA32 WFG Control Register A for WFG ch.2/3 0x1A8 WFG_WFSA54 WFG Control Register A for WFG ch.4/5 0x1AC WFG_WFIR WFG Interrupt Control Register 0x1B0 16 read-write 0x0000 0xFFFF TMIS54 stops the WFG54 reload timer and clears TMIF54 15 15 write-only TMIE54 stops the WFG54 reload timer and clears TMIF54 14 14 read-write TMIC54 clears TIMF54 bit 13 13 write-only TMIF54 detects the event of WFG54 reload timer interrupt occurrence 12 12 read-only TMIS32 stops the WFG32 reload timer and clears TMIF32 11 11 write-only TMIE32 1stops the WFG32 reload timer and clears TMIF32 10 10 read-write TMIC32 clears TIMF32 bit 9 9 write-only TMIF32 detects the event of WFG32 reload timer interrupt occurrence 8 8 read-only TMIS10 stops the WFG10 reload timer and clears TMIF10 7 7 write-only TMIE10 starts WFG10 reload timer and checks the operation state of it. 6 6 read-write TMIC10 clears TIMF10 bit 5 5 write-only TMIF10 detects the event of WFG10 reload timer interrupt occurrence 4 4 read-only DTICB clears DTIFB bit. 3 3 write-only DTIFB detects DTTIX signal input via analog noise filter 2 2 read-only DTICA clears the DTIFA interrupt flag 1 1 write-only DTIFA detects the event of DTTIX signal input via digital noise-canceller 0 0 read-only WFG_NZCL NZCL Control Register 0x1B4 16 read-write 0x0000 0x73BF WIM54 selects whether a WFG54 reload timer interrupt is masked when the WFIR.TMIF54 flag is set 14 14 read-write WIM32 selects whether a WFG32 reload timer interrupt is masked when the WFIR.TMIF32 flag is set 13 13 read-write WIM10 selects whether a WFG10 reload timer interrupt is masked when the WFIR.TMIF10 flag is set 12 12 read-write DIMB selects whether a DTIF interrupt is masked when the WFIR.TIFDTIFB flag is set 9 9 read-write DIMA selects whether a DTIF interrupt is masked when the WFIR.DTIFA flag is set 8 8 read-write DHOLD selects whether the RTO output signal of WFG is held when the DTIF interrupt signal is asserted 7 7 read-write DTIEB Enables the path from DTTIX pin to analog noise filter 5 5 read-write SDTI sets the WFIR.DTIFA register by writing to the register from the CPU 4 4 write-only NWS set the noise-canceling width for a digital noise-canceller 1 3 read-write DTIEA Enables the path for digital noise filter from DTTIX pin 0 0 read-write ICU_ICFS10 ICU ch.0/1 Connecting FRT Select Register 0x16C 8 read-write 0x00 0xFF FSI1 Connects FRT ch.x to ICU ch.(1) 4 7 read-write FSI0 Connects FRT ch.x to ICU ch.(0) 0 3 read-write ICU_ICFS32 ICU ch.2/3 Connecting FRT Select Register 0x16D ICU_ICCP0 ICU-ch.0 Capture Value Store Register 0x176 16 read-only 0x0000 0x0000 ICU_ICCP1 ICU-ch.1 Capture Value Store Register 0x17A ICU_ICCP2 ICU-ch.2 Capture Value Store Register 0x17E ICU_ICCP3 ICU-ch.3 Capture Value Store Register 0x182 ICU_ICSA10 ICU ch.0/1 Control Register A 0x184 8 read-write 0x00 0xFF ICP1 Indicates that a valid edge has been detected at ICU ch.(1) and the capture operation has been performed 7 7 read-write ICP0 Indicates that a valid edge has been detected at ICU ch.(0) and the capture operation has been performed 6 6 read-write ICE1 "Generates interrupt, when ""1"" is set to ICSA.ICP1." 5 5 read-write ICE0 "Generates interrupt, when ""1"" is set to ICSA.ICP0." 4 4 read-write EG1 enables/disables the operation of ICU-ch.(1) and selects a valid edge(s) 2 3 read-write EG0 enables/disables the operation of ICU-ch.(0) and selects a valid edge(s) 0 1 read-write ICU_ICSB10 ICU ch.0/1 Control Register B 0x185 8 read-only 0x00 0x03 IEI1 indicates the latest valid edge of ICU ch.(1) 1 1 read-only IEI0 indicates the latest valid edge of ICU ch.(0) 0 0 read-only ICU_ICSA32 ICU ch.2/3 Control Register A 0x188 ICU_ICSB32 ICU ch.2/3 Control Register B 0x189 ADCMP_ACFS10 ADCMP ch.0/1 Connecting FRT Select Register 0x170 8 read-write 0x00 0xFF FSA1 specify the FRT to be connected to ADCMP ch.(1) 4 7 read-write FSA0 specify the FRT to be connected to ADCMP ch.(0) 0 3 read-write ADCMP_ACFS32 ADCMP ch.2/3 Connecting FRT Select Register 0x171 ADCMP_ACFS54 ADCMP ch.4/5 Connecting FRT Select Register 0x172 ADCMP_ACMP0 ADCMP ch.0 Compare Value Store Register 0x1BA 16 read-write 0x0000 0xFFFF ACMP 0 0 15 read-write ADCMP_ACMP1 ADCMP ch.1 Compare Value Store Register 0x1BE ADCMP_ACMP2 ADCMP ch.2 Compare Value Store Register 0x1C2 ADCMP_ACMP3 ADCMP ch.3 Compare Value Store Register 0x1C6 ADCMP_ACMP4 ADCMP ch.4 Compare Value Store Register 0x1CA ADCMP_ACMP5 ADCMP ch.5 Compare Value Store Register 0x1CE ADCMP_ACSA ADCMP Control Register A 0x1D0 16 read-write 0x0000 0x3F3F SEL54 selects compatible operation of ADCMP ch.5 and ch.4 with FM3 Family products 12 13 read-write SEL32 selects compatible operation of ADCMP ch.3 and ch.2 with FM3 Family products 10 11 read-write SEL10 selects compatible operation of ADCMP ch.1 and ch.0 with FM3 Family products 8 9 read-write CE54 enables/disables compatibility of ADCMP ch.5 and ch.4 with FM3 Family products 4 5 read-write CE32 enables/disables compatibility of ADCMP ch.3 and ch.2 with FM3 Family products 2 3 read-write CE10 enables/disables compatibility of ADCMP ch.1 and ch.0 with FM3 Family products 0 1 read-write ADCMP_ACSC0 ADCMP ch.0 Control Register C 0x1D4 8 read-write 0x00 0x3F APBM sets the linked transfer with the FRT interrupt mask counter 5 5 read-write ADSEL specify the destinations of ADC start signals that are output by ADCMP 2 4 read-write BUFE select enable/disable and transfer timing for buffer function of the ACMP register. 0 1 read-write ADCMP_ACSD0 ADCMP ch.0 Control Register D 0x1D5 8 read-write 0x00 0xF3 ZE enables/disables the operation of the ADCMP when the FRT is "0x0000" 7 7 read-write UE enables/disables the operation of the ADCMP that is counting up for the connected FRT 6 6 read-write PE enables/disables the operation of the ADCMP that is counting down at the Peak value of the connected FRT 5 5 read-write DE enables/disables the operation of the ADCMP that is counting down for the connected FRT 4 4 read-write OCUS selects the OCU OCCP register that will become the start for offset start 1 1 read-write AMOD selects operation mode for ADCMP 0 0 read-write ADCMP_ACMC0 ADCMP ch.0 Mask Compare Value Storage Register 0x1D6 8 read-write 0x00 0xCF MPCE specifies whether a comparison is performed with the FRT peak interrupt mask counter 7 7 read-write MZCE specifies whether a comparison is performed with the FRT zero interrupt mask counter 6 6 read-write AMC specifies the value to be compared with the FRT interrupt mask counter 0 3 read-write ADCMP_ACSC1 ADCMP ch.1 Control Register C 0x1D8 ADCMP_ACSD1 ADCMP ch.1 Control Register D 0x1D9 ADCMP_ACMC1 ADCMP ch.1 Mask Compare Value Storage Register 0x1DA ADCMP_ACSC2 ADCMP ch.2 Control Register C 0x1DC ADCMP_ACSD2 ADCMP ch.2 Control Register D 0x1DD ADCMP_ACMC2 ADCMP ch.2 Mask Compare Value Storage Register 0x1DE ADCMP_ACSC3 ADCMP ch.3 Control Register C 0x1E0 ADCMP_ACSD3 ADCMP ch.3 Control Register D 0x1E1 ADCMP_ACMC3 ADCMP ch.3 Mask Compare Value Storage Register 0x1E2 ADCMP_ACSC4 ADCMP ch.4 Control Register C 0x1E4 ADCMP_ACSD4 ADCMP ch.4 Control Register D 0x1E5 ADCMP_ACMC4 ADCMP ch.4 Mask Compare Value Storage Register 0x1E6 ADCMP_ACSC5 ADCMP ch.5 Control Register C 0x1E8 ADCMP_ACSD5 ADCMP ch.5 Control Register D 0x1E9 ADCMP_ACMC5 ADCMP ch.5 Mask Compare Value Storage Register 0x1EA FRT_TCSD ERROR!!!!!!!!!!!!!!!!!!!! 0x1EC 8 read-write 0x00 0x03 OFMD2 ERROR!!!!!!!!!!!!!!!!!!!! 1 1 read-write OFMD1 ERROR!!!!!!!!!!!!!!!!!!!! 0 0 read-write MFT1 0x40021000 WFG1_DTIF1 22 FRT1_PEAK 28 FRT1_ZERO 29 ICU1 30 OCU1 31 MFT2 0x40022000 WFG2_DTIF2 23 FRT2_PEAK 32 FRT2_ZERO 33 ICU2 34 OCU2 35 MFT_PPG PPG Configuration MFT_PPG 0x40024000 0x0 0x2 registers 0x8 0x2 registers 0xC 0x1 registers 0x10 0x2 registers 0x14 0x1 registers 0x20 0x2 registers 0x28 0x2 registers 0x2C 0x1 registers 0x30 0x2 registers 0x34 0x1 registers 0x40 0x2 registers 0x48 0x2 registers 0x4C 0x1 registers 0x50 0x2 registers 0x54 0x1 registers 0x100 0x2 registers 0x104 0x2 registers 0x140 0x2 registers 0x144 0x2 registers 0x200 0x2 registers 0x204 0x2 registers 0x208 0x2 registers 0x20C 0x2 registers 0x210 0x2 registers 0x214 0x2 registers 0x218 0x1 registers 0x240 0x2 registers 0x244 0x2 registers 0x248 0x2 registers 0x24C 0x2 registers 0x250 0x2 registers 0x254 0x2 registers 0x258 0x1 registers 0x280 0x2 registers 0x284 0x2 registers 0x288 0x2 registers 0x28C 0x2 registers 0x290 0x2 registers 0x294 0x2 registers 0x298 0x1 registers 0x2C0 0x2 registers 0x2C4 0x2 registers 0x2C8 0x2 registers 0x2CC 0x2 registers 0x2D0 0x2 registers 0x2D4 0x2 registers 0x2D8 0x1 registers 0x300 0x2 registers 0x304 0x2 registers 0x308 0x2 registers 0x30C 0x2 registers 0x310 0x2 registers 0x314 0x2 registers 0x318 0x1 registers 0x340 0x2 registers 0x344 0x2 registers 0x348 0x2 registers 0x34C 0x2 registers 0x350 0x2 registers 0x354 0x2 registers 0x358 0x1 registers PPG00_02_04 36 PPG08_10_12 37 PPG16_18_20 38 TTCR0 PPG Start Trigger Control Register 0 0x0 16 read-write 0xF000 0xFF00 TRG6O PPG6 trigger stop bit 15 15 read-write TRG4O PPG4 trigger stop bit 14 14 read-write TRG2O PPG2 trigger stop bit 13 13 read-write TRG0O PPG0 trigger stop bit 12 12 read-write CS0 8-bit UP counter clock select bits for comparison 10 11 read-write MONI0 8-bit UP counter operation state monitor bit for comparison 9 9 read-only STR0 8-bit UP counter operation enable bit for comparison 8 8 read-write TTCR1 PPG Start Trigger Control Register 1 0x20 16 read-write 0xF000 0xFF00 TRG7O PPG7 trigger stop bit 15 15 read-write TRG5O PPG5 trigger stop bit 14 14 read-write TRG3O PPG3 trigger stop bit 13 13 read-write TRG1O PPG1 trigger stop bit 12 12 read-write CS1 8-bit UP counter clock select bits for comparison 10 11 read-write MONI1 8-bit UP counter operation state monitor bit for comparison 9 9 read-only STR1 8-bit UP counter operation enable bit for comparison 8 8 read-write TTCR2 PPG Start Trigger Control Register 2 0x40 16 read-write 0xF000 0xFF00 TRG22O PPG22 trigger stop bit 15 15 read-write TRG20O PPG20 trigger stop bit 14 14 read-write TRG18O PPG18 trigger stop bit 13 13 read-write TRG16O PPG16 trigger stop bit 12 12 read-write CS2 8-bit UP counter clock select bits for comparison 10 11 read-write MONI2 8-bit UP counter operation state monitor bit for comparison 9 9 read-only STR2 8-bit UP counter operation enable bit for comparison 8 8 read-write COMP0 PPG Compare Register 0 0x08 16 read-write 0x0000 0xFF00 COMP2 PPG Compare Register 2 0x0C 8 read-write 0x00 0xFF COMP4 PPG Compare Register 4 0x10 COMP6 PPG Compare Register 6 0x14 COMP1 PPG Compare Register 1 0x28 COMP3 PPG Compare Register 3 0x2C COMP5 PPG Compare Register 5 0x30 COMP7 PPG Compare Register 7 0x34 COMP8 PPG Compare Register 8 0x48 COMP10 PPG Compare Register 10 0x4C COMP12 PPG Compare Register 12 0x50 COMP14 PPG Compare Register 14 0x54 TRG PPG Start Register 0 0x100 16 read-write 0x0000 0xFFFF PEN15 PPG15 Start Trigger bit 15 15 read-write PEN14 PPG14 Start Trigger bit 14 14 read-write PEN13 PPG13 Start Trigger bit 13 13 read-write PEN12 PPG12 Start Trigger bit 12 12 read-write PEN11 PPG11 Start Trigger bit 11 11 read-write PEN10 PPG10 Start Trigger bit 10 10 read-write PEN09 PPG9 Start Trigger bit 9 9 read-write PEN08 PPG8 Start Trigger bit 8 8 read-write PEN07 PPG7 Start Trigger bit 7 7 read-write PEN06 PPG6 Start Trigger bit 6 6 read-write PEN05 PPG5 Start Trigger bit 5 5 read-write PEN04 PPG4 Start Trigger bit 4 4 read-write PEN03 PPG3 Start Trigger bit 3 3 read-write PEN02 PPG2 Start Trigger bit 2 2 read-write PEN01 PPG1 Start Trigger bit 1 1 read-write PEN00 PPG0 Start Trigger bit 0 0 read-write TRG1 PPG Start Register 1 0x140 16 read-write 0x00 0xFF PEN23 PPG23 Start Trigger bit 7 7 read-write PEN22 PPG22 Start Trigger bit 6 6 read-write PEN21 PPG21 Start Trigger bit 5 5 read-write PEN20 PPG20 Start Trigger bit 4 4 read-write PEN19 PPG19 Start Trigger bit 3 3 read-write PEN18 PPG18 Start Trigger bit 2 2 read-write PEN17 PPG17 Start Trigger bit 1 1 read-write PEN16 PPG16 Start Trigger bit 0 0 read-write REVC Output Reverse Register 0 0x104 16 read-write 0x0000 0xFFFF REV15 PPG15 Output Reverse Enable bit 15 15 read-write REV14 PPG14 Output Reverse Enable bit 14 14 read-write REV13 PPG13 Output Reverse Enable bit 13 13 read-write REV12 PPG12 Output Reverse Enable bit 12 12 read-write REV11 PPG11 Output Reverse Enable bit 11 11 read-write REV10 PPG10 Output Reverse Enable bit 10 10 read-write REV09 PPG9 Output Reverse Enable bit 9 9 read-write REV08 PPG8 Output Reverse Enable bit 8 8 read-write REV07 PPG7 Output Reverse Enable bit 7 7 read-write REV06 PPG6 Output Reverse Enable bit 6 6 read-write REV05 PPG5 Output Reverse Enable bit 5 5 read-write REV04 PPG4 Output Reverse Enable bit 4 4 read-write REV03 PPG3 Output Reverse Enable bit 3 3 read-write REV02 PPG2 Output Reverse Enable bit 2 2 read-write REV01 PPG1 Output Reverse Enable bit 1 1 read-write REV00 PPG0 Output Reverse Enable bit 0 0 read-write REVC1 Output Reverse Register 1 0x144 16 read-write 0x00 0xFF REV23 PPG23 Output Reverse Enable bit 7 7 read-write REV22 PPG22 Output Reverse Enable bit 6 6 read-write REV21 PPG21 Output Reverse Enable bit 5 5 read-write REV20 PPG20 Output Reverse Enable bit 4 4 read-write REV19 PPG19 Output Reverse Enable bit 3 3 read-write REV18 PPG18 Output Reverse Enable bit 2 2 read-write REV17 PPG17 Output Reverse Enable bit 1 1 read-write REV16 PPG16 Output Reverse Enable bit 0 0 read-write PPGC0 PPG Operation Mode Control Register 0 0x201 8 read-write 0x00 0xFF PIE PPG Interrupt Enable bit 7 7 read-write PUF PPG Counter Underflow bit 6 6 read-write INTM Interrupt Mode Select bit 5 5 read-write PCS PPG DOWN Counter Operation Clock Select bits 3 4 read-write MD PPG Operation Mode Set bits 1 2 read-write TTRG PPG start trigger select bit 0 0 read-write PPGC1 PPG Operation Mode Control Register 1 0x200 PPGC2 PPG Operation Mode Control Register 2 0x205 PPGC3 PPG Operation Mode Control Register 3 0x204 PPGC4 PPG Operation Mode Control Register 4 0x241 PPGC5 PPG Operation Mode Control Register 5 0x240 PPGC6 PPG Operation Mode Control Register 6 0x245 PPGC7 PPG Operation Mode Control Register 7 0x244 PPGC8 PPG Operation Mode Control Register 8 0x281 PPGC9 PPG Operation Mode Control Register 9 0x280 PPGC10 PPG Operation Mode Control Register 10 0x285 PPGC11 PPG Operation Mode Control Register 11 0x284 PPGC12 PPG Operation Mode Control Register 12 0x2C1 PPGC13 PPG Operation Mode Control Register 13 0x2C0 PPGC14 PPG Operation Mode Control Register 14 0x2C5 PPGC15 PPG Operation Mode Control Register 15 0x2C4 PPGC16 PPG Operation Mode Control Register 16 0x301 PPGC17 PPG Operation Mode Control Register 17 0x300 PPGC18 PPG Operation Mode Control Register 18 0x305 PPGC19 PPG Operation Mode Control Register 19 0x304 PPGC20 PPG Operation Mode Control Register 20 0x341 PPGC21 PPG Operation Mode Control Register 21 0x340 PPGC22 PPG Operation Mode Control Register 22 0x345 PPGC23 PPG Operation Mode Control Register 23 0x344 PRLH0 PPG0 Reload Registers High 0x209 8 read-write 0x00 0x00 PRLH Reload Registers High 0 7 read-write PRLL0 PPG0 Reload Registers Low 0x208 8 read-write 0x00 0x00 PRLL Reload Registers Low 0 7 read-write PRLH1 PPG1 Reload Registers High 0x20D PRLL1 PPG1 Reload Registers Low 0x20C PRLH2 PPG2 Reload Registers High 0x211 PRLL2 PPG2 Reload Registers Low 0x210 PRLH3 PPG3 Reload Registers High 0x215 PRLL3 PPG3 Reload Registers Low 0x214 PRLH4 PPG4 Reload Registers High 0x249 PRLL4 PPG4 Reload Registers Low 0x248 PRLH5 PPG5 Reload Registers High 0x24D PRLL5 PPG5 Reload Registers Low 0x24C PRLH6 PPG6 Reload Registers High 0x251 PRLL6 PPG6 Reload Registers Low 0x250 PRLH7 PPG7 Reload Registers High 0x255 PRLL7 PPG7 Reload Registers Low 0x254 PRLH8 PPG8 Reload Registers High 0x289 PRLL8 PPG8 Reload Registers Low 0x288 PRLH9 PPG9 Reload Registers High 0x28D PRLL9 PPG9 Reload Registers Low 0x28C PRLH10 PPG10 Reload Registers High 0x291 PRLL10 PPG10 Reload Registers Low 0x290 PRLH11 PPG11 Reload Registers High 0x295 PRLL11 PPG11 Reload Registers Low 0x294 PRLH12 PPG12 Reload Registers High 0x2C9 PRLL12 PPG12 Reload Registers Low 0x2C8 PRLH13 PPG13 Reload Registers High 0x2CD PRLL13 PPG13 Reload Registers Low 0x2CC PRLH14 PPG14 Reload Registers High 0x2D1 PRLL14 PPG14 Reload Registers Low 0x2D0 PRLH15 PPG15 Reload Registers High 0x2D5 PRLL15 PPG15 Reload Registers Low 0x2D4 PRLH16 PPG16 Reload Registers High 0x309 PRLL16 PPG16 Reload Registers Low 0x308 PRLH17 PPG17 Reload Registers High 0x30D PRLL17 PPG17 Reload Registers Low 0x30C PRLH18 PPG18 Reload Registers High 0x311 PRLL18 PPG18 Reload Registers Low 0x310 PRLH19 PPG19 Reload Registers High 0x315 PRLL19 PPG19 Reload Registers Low 0x314 PRLH20 PPG20 Reload Registers High 0x349 PRLL20 PPG20 Reload Registers Low 0x348 PRLH21 PPG21 Reload Registers High 0x34D PRLL21 PPG21 Reload Registers Low 0x34C PRLH22 PPG22 Reload Registers High 0x351 PRLL22 PPG22 Reload Registers Low 0x350 PRLH23 PPG23 Reload Registers High 0x355 PRLL23 PPG23 Reload Registers Low 0x354 GATEC0 PPG Gate Function Control Registers 0 0x218 8 read-write 0x00 0x33 STRG2 Select a trigger for PPG2 5 5 read-write EDGE2 Select Start Effective Level for PPG2 4 4 read-write STRG0 Select a trigger for PPG0 1 1 read-write EDGE0 Select Start Effective Level for PPG0 0 0 read-write GATEC4 PPG Gate Function Control Registers 4 0x258 8 read-write 0x00 0x33 STRG6 Select a trigger for PPG6 5 5 read-write EDGE6 Select Start Effective Level for PPG6 4 4 read-write STRG4 Select a trigger for PPG4 1 1 read-write EDGE4 Select Start Effective Level for PPG4 0 0 read-write GATEC8 PPG Gate Function Control Registers 8 0x298 8 read-write 0x00 0x33 STRG10 Select a trigger for PPG10 5 5 read-write EDGE10 Select Start Effective Level for PPG10 4 4 read-write STRG8 Select a trigger for PPG8 1 1 read-write EDGE8 Select Start Effective Level for PPG8 0 0 read-write GATEC12 PPG Gate Function Control Registers 12 0x2D8 8 read-write 0x00 0x33 STRG14 Select a trigger for PPG14 5 5 read-write EDGE14 Select Start Effective Level for PPG14 4 4 read-write STRG12 Select a trigger for PPG12 1 1 read-write EDGE12 Select Start Effective Level for PPG12 0 0 read-write GATEC16 PPG Gate Function Control Registers 16 0x318 8 read-write 0x00 0x33 STRG18 Select a trigger for PPG18 5 5 read-write EDGE18 Select Start Effective Level for PPG18 4 4 read-write STRG16 Select a trigger for PPG16 1 1 read-write EDGE16 Select Start Effective Level for PPG16 0 0 read-write GATEC20 PPG Gate Function Control Registers 20 0x358 8 read-write 0x00 0x33 STRG22 Select a trigger for PPG22 5 5 read-write EDGE22 Select Start Effective Level for PPG22 4 4 read-write STRG20 Select a trigger for PPG20 1 1 read-write EDGE20 Select Start Effective Level for PPG20 0 0 read-write BTIOSEL03 Base Timer I/O Select BTIOSEL03 0x40025100 0x0 0x2 registers BTSEL0123 I/O Select Register 0x00 16 read-write 0x0000 0xFF00 SEL23_ I/O select bits for Ch.2/Ch.3 12 15 read-write SEL01_ I/O select bits for Ch.0/Ch.1 8 11 read-write BTIOSEL47 Base Timer I/O Select BTIOSEL47 0x40025300 0x0 0x2 registers 0x0 0x2 registers BTSEL4567 I/O Select Register 0x00 16 read-write 0x0000 0xFF00 SEL67_ I/O select bits for Ch.6/Ch.7 12 15 read-write SEL45_ I/O select bits for Ch.4/Ch.5 8 11 read-write BTIOSEL8B Base Timer I/O Select BTIOSEL8B 0x40025500 0x0 0x2 registers BTSEL89AB I/O Select Register 0x0 16 read-write 0x0 0xFF00 SELAB_ I/O select bits for Ch.A/Ch.B 12 15 read-write SEL89_ I/O select bits for Ch.8/Ch.9 8 11 read-write BTIOSELCF Base Timer I/O Select BTIOSELCF 0x40025700 0x0 0x2 registers BTSELCDEF I/O Select Register 0x0 16 read-write 0x0 0xFF00 SELEF_ I/O select bits for Ch.E/Ch.F 12 15 read-write SELCD_ I/O select bits for Ch.C/Ch.D 8 11 read-write SBSSR Software-based Simultaneous Startup Register SBSSR 0x40025F00 0x0FC 0x2 registers BTSSSR Software-based Simultaneous Startup Register 0xFC 16 write-only 0x0000 0x0000 SSSR15 Bit15 of BTSSSR 15 15 write-only SSSR14 Bit14 of BTSSSR 14 14 write-only SSSR13 Bit13 of BTSSSR 13 13 write-only SSSR12 Bit12 of BTSSSR 12 12 write-only SSSR11 Bit11 of BTSSSR 11 11 write-only SSSR10 Bit10 of BTSSSR 10 10 write-only SSSR9 Bit9 of BTSSSR 9 9 write-only SSSR8 Bit8 of BTSSSR 8 8 write-only SSSR7 Bit7 of BTSSSR 7 7 write-only SSSR6 Bit6 of BTSSSR 6 6 write-only SSSR5 Bit5 of BTSSSR 5 5 write-only SSSR4 Bit4 of BTSSSR 4 4 write-only SSSR3 Bit3 of BTSSSR 3 3 write-only SSSR2 Bit2 of BTSSSR 2 2 write-only SSSR1 Bit1 of BTSSSR 1 1 write-only SSSR0 Bit0 of BTSSSR 0 0 write-only BT0 Base Timer 0 BT0 0x40025000 0x0 0x2 registers 0x4 0x2 registers 0x8 0x2 registers 0xC 0x2 registers 0x10 0x2 registers BT0 39 PWM_TMCR Timer Control Register PWM 0x0C 16 read-write 0x0000 0x7F7F CKS2_0 Count clock selection bit 12 14 read-write RTGEN Restart enable bit 11 11 read-write PMSK Pulse output mask bit 10 10 read-write EGS Trigger input edge selection bits 8 9 read-write FMD Timer function selection bits 4 6 read-write OSEL Output polarity specification bit 3 3 read-write MDSE Mode selection bit 2 2 read-write CTEN Count operation enable bit 1 1 read-write STRG Software trigger bit 0 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write 0x00 0x01 CKS3 Count clock selection bit 0 0 read-write PWM_STC Status Control Register PWM 0x10 8 read-write 0x00 0x77 TGIE Trigger interrupt request enable bit 6 6 read-write DTIE Duty match interrupt request enable bit 5 5 read-write UDIE Underflow interrupt request enable bit 4 4 read-write TGIR Trigger interrupt request bit 2 2 read-write DTIR Duty match interrupt request bit 1 1 read-write UDIR Underflow interrupt request bit 0 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x00 16 read-write 0x0000 0x0000 PWM_PDUT PWM Duty Set Register PWM 0x04 16 read-write 0x0000 0x0000 PWM_TMR Timer Register PWM 0x08 16 read-only 0x0000 0xFFFF PPG_TMCR Timer Control Register PPG 0x0C 16 read-write 0x0000 0x7F7F CKS2_0 Count clock selection bit 12 14 read-write RTGEN Restart enable bit 11 11 read-write PMSK Pulse output mask bit 10 10 read-write EGS Trigger input edge selection bits 8 9 read-write FMD Timer function selection bits 4 6 read-write OSEL Output polarity specification bit 3 3 read-write MDSE Mode selection bit 2 2 read-write CTEN Count operation enable bit 1 1 read-write STRG Software trigger bit 0 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write 0x00 0x01 CKS3 Count clock selection bit 0 0 read-write PPG_STC Status Control Register PPG 0x10 8 read-write 0x00 0x55 TGIE Trigger interrupt request enable bit 6 6 read-write UDIE Underflow interrupt request enable bit 4 4 read-write TGIR Trigger interrupt request bit 2 2 read-write UDIR Underflow interrupt request bit 0 0 read-write PPG_PRLL LOW Width Reload Register PPG 0x00 16 read-write 0x0000 0x0000 PPG_PRLH HIGH Width Reload Register PPG 0x04 16 read-write 0x0000 0x0000 PPG_TMR Timer Register PPG 0x08 16 read-only 0x0000 0xFFFF RT_TMCR Timer Control Register RT 0x0C 16 read-write 0x0000 0x73FF CKS2_0 Count clock selection bit 12 14 read-write EGS Trigger input edge selection bits 8 9 read-write T32 32-bit timer selection bit 7 7 read-write FMD Timer function selection bits 4 6 read-write OSEL Output polarity specification bit 3 3 read-write MDSE Mode selection bit 2 2 read-write CTEN Timer enable bit 1 1 read-write STRG Software trigger bit 0 0 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write 0x00 0x81 GATE Gate Input Enable bit 7 7 read-write CKS3 Count clock selection bit 0 0 read-write RT_STC Status Control Register RT 0x10 8 read-write 0x00 0x55 TGIE Trigger interrupt request enable bit 6 6 read-write UDIE Underflow interrupt request enable bit 4 4 read-write TGIR Trigger interrupt request bit 2 2 read-write UDIR Underflow interrupt request bit 0 0 read-write RT_PCSR PWM Cycle Set Register RT 0x00 16 read-write 0x0000 0x0000 RT_TMR Timer Register RT 0x08 16 read-only 0x0000 0x0000 PWC_TMCR Timer Control Register PWC 0x0C 16 read-write 0x0000 0x77F6 CKS2_0 Count clock selection bit 12 14 read-write EGS Measurement edge selection bits 8 10 read-write T32 32-bit timer selection bit 7 7 read-write FMD Timer function selection bits 4 6 read-write MDSE Mode selection bit 2 2 read-write CTEN Timer enable bit 1 1 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write 0x00 0x01 CKS3 Count clock selection bit 0 0 read-write PWC_STC Status Control Register PWC 0x10 8 read-write 0x00 0xD5 ERR Error flag bit 7 7 read-only EDIE Measurement completion interrupt request enable bit 6 6 read-write OVIE Overflow interrupt request enable bit 4 4 read-write EDIR Measurement completion interrupt request bit 2 2 read-only OVIR Overflow interrupt request bit 0 0 read-write PWC_DTBF Data Buffer Register PWC 0x04 16 read-only 0x0000 0xFFFF BT1 0x40025040 BT1 40 BT2 0x40025080 BT2 41 BT3 0x400250C0 BT3 42 BT4 0x40025200 BT4 43 BT5 0x40025240 BT5 44 BT6 0x40025280 BT6 45 BT7 0x400252C0 BT7 46 BT8 0x40025400 BT8 98 BT9 0x40025440 BT9 99 BT10 0x40025480 BT10 100 BT11 0x400254C0 BT11 101 BT12 0x40025600 BT12_13_14_15 102 BT13 0x40025640 BT14 0x40025680 BT15 0x400256C0 QPRC0 Quadrature Position/Revolution Counter 0 QPRC0 0x40026000 0x0 0x2 registers 0x4 0x2 registers 0x8 0x2 registers 0xC 0x2 registers 0x10 0x2 registers 0x14 0x2 registers 0x18 0x2 registers 0x1C 0x2 registers 0x3C 0x2 registers 0x3E 0x2 registers QPRC0 19 QPCR QPRC Position Count Register 0x00 16 read-write 0x0000 0xFFFF QRCR QPRC Revolution Count Register 0x04 16 read-write 0x0000 0xFFFF QPCCR QPRC Position Counter Compare Register 0x08 16 read-write 0x0000 0xFFFF QPRCR QPRC Position and Revolution Counter Compare Register 0x0C 16 read-write 0x0000 0xFFFF QMPR QPRC Maximum Position Register 0x10 16 read-write 0xFFFF 0xFFFF QICRL Low-Order Bytes of QPRC Interrupt Control Register 0x14 8 read-write 0x00 0xFF ZIIF Zero index interrupt request flag bit 7 7 read-write OFDF Overflow interrupt request flag bit 6 6 read-write UFDF Underflow interrupt request flag bit 5 5 read-write OUZIE "Overflow, underflow, or zero index interrupt enable bit" 4 4 read-write QPRCMF PC and RC match interrupt request flag bit 3 3 read-write QPRCMIE PC and RC match interrupt enable bit 2 2 read-write QPCMF PC match interrupt request flag bit 1 1 read-write QPCMIE PC match interrupt enable bit 0 0 read-write QICRH High-Order Bytes of QPRC Interrupt Control Register 0x15 8 read-write 0x00 0x3F QPCNRCMF PC match and RC match interrupt request flag bit 5 5 read-write QPCNRCMIE PC match and RC match interrupt enable bit 4 4 read-write DIROU Last position counter flow direction bit 3 3 read-only DIRPC Last position counter direction bit 2 2 read-only CDCF Count inversion interrupt request flag bit 1 1 read-write CDCIE Count inversion interrupt enable bit 0 0 read-write QCR QPRC Control Register 0x18 16 read-write 0x0000 0xFFFF CGE Detection edge selection bits 14 15 read-write BES BIN detection edge selection bits 12 13 read-write AES AIN detection edge selection bits 10 11 read-write PCRM Position counter reset mask bits 8 9 read-write SWAP Swap bit 7 7 read-write RSEL Register function selection bit 6 6 read-write CGSC Count clear or gate selection bit 5 5 read-write PSTP Position counter stop bit 4 4 read-write RCM Revolution counter mode bits 2 3 read-write PCM Position counter mode bits 0 1 read-write QECR QPRC Extension Control Register 0x1C 16 read-write 0x0000 0x000F PEC Phase edge change bit 3 3 read-write ORNGIE Outrange interrupt enable bit 2 2 read-write ORNGF Outrange interrupt request flag bit 1 1 read-write ORNGMD Outrange mode selection bit 0 0 read-write QPRCRR Quad Counter Position Rotation Count Register 0x3C 32 read-only 0x00000000 0xFFFFFFFF QRCRR Quad counter rotation count display bit 16 31 read-only QPCRR Quad counter position count display bit 0 15 read-only QPRC1 0x40026040 QPRC1 20 QPRC2 0x40026080 QPRC2 96 QPRC3 0x400260C0 QPRC3 97 QPRC0_NF Quadrature Position/Revolution Counter 0 Noise Filter QPRC0_NF 0x40026100 0x0 0x1 registers 0x4 0x1 registers 0x8 0x1 registers NFCTLA AIN Noise Control Register 0x0 8 read-write 0x00 0x37 AINMD Mask bit 5 5 read-write AINLV Input invert bit 4 4 read-write AINNWS Noise filter width select bits 0 2 read-write NFCTLB BIN Noise Control Register 0x4 8 read-write 0x00 0x37 BINMD Mask bit 5 5 read-write BINLV Input invert bit 4 4 read-write BINNWS Noise filter width select bits 0 2 read-write NFCTLZ ZIN Noise Control Register 0x8 8 read-write 0x00 0x37 ZINMD Mask bit 5 5 read-write ZINLV Input invert bit 4 4 read-write ZINNWS Noise filter width select bits 0 2 read-write QPRC1_NF 0x40026110 QPRC2_NF 0x40026120 QPRC3_NF 0x40026130 ADC0 ADC0 Registers ADC0 0x40027000 0x0 0x2 registers 0x8 0x2 registers 0xC 0x4 registers 0x10 0x2 registers 0x14 0x2 registers 0x18 0x2 registers 0x1C 0x4 registers 0x20 0x1 registers 0x24 0x1 registers 0x26 0x2 registers 0x28 0x2 registers 0x2C 0x2 registers 0x30 0x2 registers 0x34 0x1 registers 0x38 0x2 registers 0x3C 0x2 registers 0x44 0x1 registers 0x48 0x1 registers 0x4C 0x2 registers 0x50 0x4 registers ADC0 76 ADCR A/D Control Register 0x1 8 read-write 0x00 0xEF SCIF Scan conversion interrupt request bit 7 7 read-write PCIF Priority conversion interrupt request bit 6 6 read-write CMPIF Conversion result comparison interrupt request bit 5 5 read-write SCIE Scan conversion interrupt enable bit 3 3 read-write PCIE Priority conversion interrupt enable bit 2 2 read-write CMPIE Conversion result comparison interrupt enable bit 1 1 read-write OVRIE FIFO overrun interrupt enable bit 0 0 read-write ADSR A/D Status Register 0x0 8 read-write 0x00 0xC7 ADSTP A/D conversion forced stop bit 7 7 read-write FDAS FIFO data placement selection bit 6 6 read-write PCNS Priority conversion pending flag 2 2 read-write PCS Priority conversion status flag 1 1 read-write SCS Scan conversion status flag 0 0 read-write SCCR Scan Conversion Control Register 0x9 8 read-write 0x80 0xF7 SEMP Scan conversion FIFO empty bit 7 7 read-only SFUL Scan conversion FIFO full bit 6 6 read-only SOVR Scan conversion overrun flag 5 5 read-write SFCLR Scan conversion FIFO clear bit 4 4 read-write RPT Scan conversion repeat bit 2 2 read-write SHEN Scan conversion timer start enable bit 1 1 read-write SSTR Scan conversion start bit 0 0 read-write SFNS Scan Conversion FIFO Stage Count Setup Register 0x8 8 read-write 0x00 0x0F SFS Scan conversion FIFO stage count setting bit 0 3 read-write SCFD Scan Conversion FIFO Data Register 0xC 32 read-only 0x00000000 0xFFF0131F SD Scan conversion result 20 31 read-only INVL A/D conversion result disable bit 12 12 read-only RS Scan conversion start factor 8 9 read-only SC Conversion input channel bits 0 4 read-only SCIS3 Scan Conversion Input Selection Register 3 0x11 8 read-write 0x00 0xFF AN31 Bit7 of SCIS3 7 7 read-write AN30 Bit6 of SCIS3 6 6 read-write AN29 Bit5 of SCIS3 5 5 read-write AN28 Bit4 of SCIS3 4 4 read-write AN27 Bit3 of SCIS3 3 3 read-write AN26 Bit2 of SCIS3 2 2 read-write AN25 Bit1 of SCIS3 1 1 read-write AN24 Bit0 of SCIS3 0 0 read-write SCIS2 Scan Conversion Input Selection Register 2 0x10 8 read-write 0x00 0xFF AN23 Bit7 of SCIS2 7 7 read-write AN22 Bit6 of SCIS2 6 6 read-write AN21 Bit5 of SCIS2 5 5 read-write AN20 Bit4 of SCIS2 4 4 read-write AN19 Bit3 of SCIS2 3 3 read-write AN18 Bit2 of SCIS2 2 2 read-write AN17 Bit1 of SCIS2 1 1 read-write AN16 Bit0 of SCIS2 0 0 read-write SCIS1 Scan Conversion Input Selection Register 1 0x15 8 read-write 0x00 0xFF AN15 Bit7 of SCIS1 7 7 read-write AN14 Bit6 of SCIS1 6 6 read-write AN13 Bit5 of SCIS1 5 5 read-write AN12 Bit4 of SCIS1 4 4 read-write AN11 Bit3 of SCIS1 3 3 read-write AN10 Bit2 of SCIS1 2 2 read-write AN9 Bit1 of SCIS1 1 1 read-write AN8 Bit0 of SCIS1 0 0 read-write SCIS0 Scan Conversion Input Selection Register 0 0x14 8 read-write 0x00 0xFF AN7 Bit7 of SCIS0 7 7 read-write AN6 Bit6 of SCIS0 6 6 read-write AN5 Bit5 of SCIS0 5 5 read-write AN4 Bit4 of SCIS0 4 4 read-write AN3 Bit3 of SCIS0 3 3 read-write AN2 Bit2 of SCIS0 2 2 read-write AN1 Bit1 of SCIS0 1 1 read-write AN0 Bit0 of SCIS0 0 0 read-write PFNS Priority Conversion FIFO Stage Count Setup Register 0x18 8 read-write 0x00 0x33 TEST Test bits 4 5 read-only PFS Priority conversion FIFO stage count setting bits 0 1 read-write PCCR Priority Conversion Control Register 0x19 8 read-write 0x80 0xFF PEMP Priority conversion FIFO empty bit 7 7 read-only PFUL Priority conversion FIFO full bit 6 6 read-only POVR Priority conversion overrun flag 5 5 read-write PFCLR Priority conversion FIFO clear bit 4 4 read-write ESCE External trigger analog input selection bit 3 3 read-write PEEN Priority conversion external start enable bit 2 2 read-write PHEN Priority conversion timer start enable bit 1 1 read-write PSTR Priority conversion start bit 0 0 read-write PCFD Priority Conversion FIFO Data Register 0x1C 32 read-only 0x00000000 0xFFF0171F PD Priority conversion result 20 31 read-only INVL A/D conversion result disable bit 12 12 read-only RS Scan conversion start factor 8 10 read-only PC Conversion input channel bits 0 4 read-only PCIS Priority Conversion Input Selection Register 0x20 8 read-write 0x00 0xFF P2A Priority level 2 analog input selection 3 7 read-write P1A Priority level 1 analog input selection 0 2 read-write CMPCR A/D Comparison Control Register 0x24 8 read-write 0x00 0xFF CMPEN Conversion result comparison function operation enable bit 7 7 read-write CMD1 Comparison mode 1 6 6 read-write CMD0 Comparison mode 0 5 5 read-write CCH Comparison target analog input channel 0 4 read-write CMPD A/D Comparison Value Setup Register 0x26 16 read-write 0x0000 0xFFC0 CMAD A/D conversion result value setting bits 6 15 read-write ADSS3 Sampling Time Selection Register 3 0x29 8 read-write 0x00 0xFF TS31 Bit7 of ADSS3 7 7 read-write TS30 Bit6 of ADSS3 6 6 read-write TS29 Bit5 of ADSS3 5 5 read-write TS28 Bit4 of ADSS3 4 4 read-write TS27 Bit3 of ADSS3 3 3 read-write TS26 Bit2 of ADSS3 2 2 read-write TS25 Bit1 of ADSS3 1 1 read-write TS24 Bit0 of ADSS3 0 0 read-write ADSS2 Sampling Time Selection Register 2 0x28 8 read-write 0x00 0xFF TS23 Bit7 of ADSS2 7 7 read-write TS22 Bit6 of ADSS2 6 6 read-write TS21 Bit5 of ADSS2 5 5 read-write TS20 Bit4 of ADSS2 4 4 read-write TS19 Bit3 of ADSS2 3 3 read-write TS18 Bit2 of ADSS2 2 2 read-write TS17 Bit1 of ADSS2 1 1 read-write TS16 Bit0 of ADSS2 0 0 read-write ADSS1 Sampling Time Selection Register 1 0x2D 8 read-write 0x00 0xFF TS15 Bit7 of ADSS1 7 7 read-write TS14 Bit6 of ADSS1 6 6 read-write TS13 Bit5 of ADSS1 5 5 read-write TS12 Bit4 of ADSS1 4 4 read-write TS11 Bit3 of ADSS1 3 3 read-write TS10 Bit2 of ADSS1 2 2 read-write TS9 Bit1 of ADSS1 1 1 read-write TS8 Bit0 of ADSS1 0 0 read-write ADSS0 Sampling Time Selection Register 0 0x2C 8 read-write 0x00 0xFF TS7 Bit7 of ADSS0 7 7 read-write TS6 Bit6 of ADSS0 6 6 read-write TS5 Bit5 of ADSS0 5 5 read-write TS4 Bit4 of ADSS0 4 4 read-write TS3 Bit3 of ADSS0 3 3 read-write TS2 Bit2 of ADSS0 2 2 read-write TS1 Bit1 of ADSS0 1 1 read-write TS0 Bit0 of ADSS0 0 0 read-write ADST1 Sampling Time Setup Register 1 0x30 8 read-write 0x10 0xFF STX1 Sampling time N times setting bits 5 7 read-write ST1 Sampling time setting bits 0 4 read-write ADST0 Sampling Time Setup Register 0 0x31 8 read-write 0x10 0xFF STX0 Sampling time N times setting bits 5 7 read-write ST0 Sampling time setting bits 0 4 read-write ADCT Frequency Division Ratio Setup Register 0x34 8 read-write 0x07 0x07 CT Frequency division ratio setting bits 0 7 read-write PRTSL Priority Conversion Timer Trigger Selection Register 0x38 8 read-write 0x00 0x0F PRTSL Priority conversion timer trigger selection bit 0 3 read-write SCTSL Scan Conversion Timer Trigger Selection Register 0x39 8 read-write 0x00 0x0F SCTSL Scan conversion timer trigger selection bit 0 3 read-write ADCEN A/D Operation Enable Setup Register 0x3C 16 read-write 0xFF00 0xFF03 ENBLTIME Operation enable state transition cycle selection bits 8 15 read-write READY A/D operation enable state bit 1 1 read-only ENBL A/D operation enable bit 0 0 read-write WCMRCOT Range Comparison Threshold Excess Flag Register 0x44 8 read-write 0x00 0x01 RCOOF Threshold excess flag bit 0 0 read-write WCMRCIF Range Comparison Flag Register 0x48 8 read-write 0x00 0x01 RCINT Range comparison interrupt factor flag 0 0 read-write WCMPCR Range Comparison Control Register 0x4C 8 read-write 0x20 0xFC RCOCD Continuous detection specification count/state indication bits 5 7 read-write RCOIRS Selection bit of within-range and out-of- range confirmation 4 4 read-write RCOIE Range comparison interrupt request enable bit 3 3 read-write RCOE Range comparison execution enable bit 2 2 read-write WCMPSR Range Comparison Channel Select Register 0x4D 8 read-write 0x00 0x3F WCMD Comparison mode select bit 5 5 read-write WCCH Comparison target analog input channel 0 4 read-write WCMPDL Lower Limit Threshold Setup Register 0x50 16 read-write 0x0000 0xFFC0 CMLD Lower limit threshold bits 6 15 read-write WCMPDH Upper Limit Setup Register 0x52 16 read-write 0x0000 0xFFC0 CMHD Upper limit threshold bits 6 15 read-write ADC1 0x40027100 ADC1 77 ADC2 0x40027200 ADC2 111 DAC0 D/A Converter 0 DAC0 0x40033000 0x0 0x1 registers 0x4 0x2 registers DACR D/A Control Register 0x0 8 read-write 0x0 0x33 DDAS 10-bit mode data allocation selection bit 5 5 read-write DAC10 10-bit mode 4 4 read-write DRDY D/A converter operation enable state bit 1 1 read-only DAE D/A converter operating enable bit 0 0 read-write DADR D/A Data Register 0x4 16 read-write 0x0 0x0 DA D/A Data Register 0 11 read-write DAC1 0x40033008 EXTI External Interrupt and NMI Control EXTI 0x40030000 0x0 0x4 registers 0x4 0x4 registers 0x8 0x4 registers 0xC 0x4 registers 0x10 0x4 registers 0x14 0x1 registers 0x18 0x1 registers EXINT0 11 EXINT1 12 EXINT2 13 EXINT3 14 EXINT4 15 EXINT5 16 EXINT6 17 EXINT7 18 EXINT8 51 EXINT9 52 EXINT10 53 EXINT11 54 EXINT12 55 EXINT13 56 EXINT14 57 EXINT15 58 EXINT16_17_18_19 92 EXINT20_21_22_23 93 EXINT24_25_26_27 94 EXINT28_29_30_31 95 ENIR Enable Interrupt Request Register 0x0 32 read-write 0x0 0xFFFFFFFF EN31 Bit31 of ENIR 31 31 read-write EN30 Bit30 of ENIR 30 30 read-write EN29 Bit29 of ENIR 29 29 read-write EN28 Bit28 of ENIR 28 28 read-write EN27 Bit27 of ENIR 27 27 read-write EN26 Bit26 of ENIR 26 26 read-write EN25 Bit25 of ENIR 25 25 read-write EN24 Bit24 of ENIR 24 24 read-write EN23 Bit23 of ENIR 23 23 read-write EN22 Bit22 of ENIR 22 22 read-write EN21 Bit21 of ENIR 21 21 read-write EN20 Bit20 of ENIR 20 20 read-write EN19 Bit19 of ENIR 19 19 read-write EN18 Bit18 of ENIR 18 18 read-write EN17 Bit17 of ENIR 17 17 read-write EN16 Bit16 of ENIR 16 16 read-write EN15 Bit15 of ENIR 15 15 read-write EN14 Bit14 of ENIR 14 14 read-write EN13 Bit13 of ENIR 13 13 read-write EN12 Bit12 of ENIR 12 12 read-write EN11 Bit11 of ENIR 11 11 read-write EN10 Bit10 of ENIR 10 10 read-write EN9 Bit9 of ENIR 9 9 read-write EN8 Bit8 of ENIR 8 8 read-write EN7 Bit7 of ENIR 7 7 read-write EN6 Bit6 of ENIR 6 6 read-write EN5 Bit5 of ENIR 5 5 read-write EN4 Bit4 of ENIR 4 4 read-write EN3 Bit3 of ENIR 3 3 read-write EN2 Bit2 of ENIR 2 2 read-write EN1 Bit1 of ENIR 1 1 read-write EN0 Bit0 of ENIR 0 0 read-write EIRR External Interrupt Request Register 0x4 32 read-only 0x0 0x0 ER31 Bit31 of EIRR 31 31 read-only ER30 Bit30 of EIRR 30 30 read-only ER29 Bit29 of EIRR 29 29 read-only ER28 Bit28 of EIRR 28 28 read-only ER27 Bit27 of EIRR 27 27 read-only ER26 Bit26 of EIRR 26 26 read-only ER25 Bit25 of EIRR 25 25 read-only ER24 Bit24 of EIRR 24 24 read-only ER23 Bit23 of EIRR 23 23 read-only ER22 Bit22 of EIRR 22 22 read-only ER21 Bit21 of EIRR 21 21 read-only ER20 Bit20 of EIRR 20 20 read-only ER19 Bit19 of EIRR 19 19 read-only ER18 Bit18 of EIRR 18 18 read-only ER17 Bit17 of EIRR 17 17 read-only ER16 Bit16 of EIRR 16 16 read-only ER15 Bit15 of EIRR 15 15 read-only ER14 Bit14 of EIRR 14 14 read-only ER13 Bit13 of EIRR 13 13 read-only ER12 Bit12 of EIRR 12 12 read-only ER11 Bit11 of EIRR 11 11 read-only ER10 Bit10 of EIRR 10 10 read-only ER9 Bit9 of EIRR 9 9 read-only ER8 Bit8 of EIRR 8 8 read-only ER7 Bit7 of EIRR 7 7 read-only ER6 Bit6 of EIRR 6 6 read-only ER5 Bit5 of EIRR 5 5 read-only ER4 Bit4 of EIRR 4 4 read-only ER3 Bit3 of EIRR 3 3 read-only ER2 Bit2 of EIRR 2 2 read-only ER1 Bit1 of EIRR 1 1 read-only ER0 Bit0 of EIRR 0 0 read-only EICL External Interrupt Clear Register 0x8 32 read-write 0xFFFFFFFF 0xFFFFFFFF ECL31 Bit31 of EICL 31 31 read-write ECL30 Bit30 of EICL 30 30 read-write ECL29 Bit29 of EICL 29 29 read-write ECL28 Bit28 of EICL 28 28 read-write ECL27 Bit27 of EICL 27 27 read-write ECL26 Bit26 of EICL 26 26 read-write ECL25 Bit25 of EICL 25 25 read-write ECL24 Bit24 of EICL 24 24 read-write ECL23 Bit23 of EICL 23 23 read-write ECL22 Bit22 of EICL 22 22 read-write ECL21 Bit21 of EICL 21 21 read-write ECL20 Bit20 of EICL 20 20 read-write ECL19 Bit19 of EICL 19 19 read-write ECL18 Bit18 of EICL 18 18 read-write ECL17 Bit17 of EICL 17 17 read-write ECL16 Bit16 of EICL 16 16 read-write ECL15 Bit15 of EICL 15 15 read-write ECL14 Bit14 of EICL 14 14 read-write ECL13 Bit13 of EICL 13 13 read-write ECL12 Bit12 of EICL 12 12 read-write ECL11 Bit11 of EICL 11 11 read-write ECL10 Bit10 of EICL 10 10 read-write ECL9 Bit9 of EICL 9 9 read-write ECL8 Bit8 of EICL 8 8 read-write ECL7 Bit7 of EICL 7 7 read-write ECL6 Bit6 of EICL 6 6 read-write ECL5 Bit5 of EICL 5 5 read-write ECL4 Bit4 of EICL 4 4 read-write ECL3 Bit3 of EICL 3 3 read-write ECL2 Bit2 of EICL 2 2 read-write ECL1 Bit1 of EICL 1 1 read-write ECL0 Bit0 of EICL 0 0 read-write ELVR External Interrupt Level Register 0xC 32 read-write 0x0 0xFFFFFFFF LB15 Bit31 of ELVR 31 31 read-write LA15 Bit30 of ELVR 30 30 read-write LB14 Bit29 of ELVR 29 29 read-write LA14 Bit28 of ELVR 28 28 read-write LB13 Bit27 of ELVR 27 27 read-write LA13 Bit26 of ELVR 26 26 read-write LB12 Bit25 of ELVR 25 25 read-write LA12 Bit24 of ELVR 24 24 read-write LB11 Bit23 of ELVR 23 23 read-write LA11 Bit22 of ELVR 22 22 read-write LB10 Bit21 of ELVR 21 21 read-write LA10 Bit20 of ELVR 20 20 read-write LB9 Bit19 of ELVR 19 19 read-write LA9 Bit18 of ELVR 18 18 read-write LB8 Bit17 of ELVR 17 17 read-write LA8 Bit16 of ELVR 16 16 read-write LB7 Bit15 of ELVR 15 15 read-write LA7 Bit14 of ELVR 14 14 read-write LB6 Bit13 of ELVR 13 13 read-write LA6 Bit12 of ELVR 12 12 read-write LB5 Bit11 of ELVR 11 11 read-write LA5 Bit10 of ELVR 10 10 read-write LB4 Bit9 of ELVR 9 9 read-write LA4 Bit8 of ELVR 8 8 read-write LB3 Bit7 of ELVR 7 7 read-write LA3 Bit6 of ELVR 6 6 read-write LB2 Bit5 of ELVR 5 5 read-write LA2 Bit4 of ELVR 4 4 read-write LB1 Bit3 of ELVR 3 3 read-write LA1 Bit2 of ELVR 2 2 read-write LB0 Bit1 of ELVR 1 1 read-write LA0 Bit0 of ELVR 0 0 read-write ELVR1 External Interrupt Level Register 1 0x10 32 read-write 0x0 0xFFFFFFFF LB31 Bit31 of ELVR1 31 31 read-write LA31 Bit30 of ELVR1 30 30 read-write LB30 Bit29 of ELVR1 29 29 read-write LA30 Bit28 of ELVR1 28 28 read-write LB29 Bit27 of ELVR1 27 27 read-write LA29 Bit26 of ELVR1 26 26 read-write LB28 Bit25 of ELVR1 25 25 read-write LA28 Bit24 of ELVR1 24 24 read-write LB27 Bit23 of ELVR1 23 23 read-write LA27 Bit22 of ELVR1 22 22 read-write LB26 Bit21 of ELVR1 21 21 read-write LA26 Bit20 of ELVR1 20 20 read-write LB25 Bit19 of ELVR1 19 19 read-write LA25 Bit18 of ELVR1 18 18 read-write LB24 Bit17 of ELVR1 17 17 read-write LA24 Bit16 of ELVR1 16 16 read-write LB23 Bit15 of ELVR1 15 15 read-write LA23 Bit14 of ELVR1 14 14 read-write LB22 Bit13 of ELVR1 13 13 read-write LA22 Bit12 of ELVR1 12 12 read-write LB21 Bit11 of ELVR1 11 11 read-write LA21 Bit10 of ELVR1 10 10 read-write LB20 Bit9 of ELVR1 9 9 read-write LA20 Bit8 of ELVR1 8 8 read-write LB19 Bit7 of ELVR1 7 7 read-write LA19 Bit6 of ELVR1 6 6 read-write LB18 Bit5 of ELVR1 5 5 read-write LA18 Bit4 of ELVR1 4 4 read-write LB17 Bit3 of ELVR1 3 3 read-write LA17 Bit2 of ELVR1 2 2 read-write LB16 Bit1 of ELVR1 1 1 read-write LA16 Bit0 of ELVR1 0 0 read-write NMIRR Non Maskable Interrupt Request Register 0x14 8 read-only 0x0 0x1 NR NMI interrupt request detection bit 0 0 read-only NMICL Non Maskable Interrupt Clear Register 0x18 8 read-write 0x1 0x1 NCL NMI interrupt cause clear bit 0 0 read-write INTREQ Interrupts INTREQ 0x40031000 0x0 0x4 registers 0x10 0x1 registers 0x14 0x1 registers 0x110 0x20 registers 0x200 0x204 registers DRQSEL DMA Request Selection Register 0x0 32 read-write 0x0 0xFFFFFFFF EXINT3 External pin interrupt ch.3 31 31 read-write EXINT2 External pin interrupt ch.2 30 30 read-write EXINT1 External pin interrupt ch.1 29 29 read-write EXINT0 External pin interrupt ch.0 28 28 read-write MFS7TX MFS ch.7 transmission interrupt 27 27 read-write MFS7RX MFS ch.7 reception interrupt 26 26 read-write MFS6TX MFS ch.6 transmission interrupt 25 25 read-write MFS6RX MFS ch.6 reception interrupt 24 24 read-write MFS5TX MFS ch.5 transmission interrupt 23 23 read-write MFS5RX MFS ch.5 reception interrupt 22 22 read-write MFS4TX MFS ch.4 transmission interrupt 21 21 read-write MFS4RX MFS ch.4 reception interrupt 20 20 read-write MFS3TX MFS ch.3 transmission interrupt 19 19 read-write MFS3RX MFS ch.3 reception interrupt 18 18 read-write MFS2TX MFS ch.2 transmission interrupt 17 17 read-write MFS2RX MFS ch.2 reception interrupt 16 16 read-write MFS1TX MFS ch.1 transmission interrupt 15 15 read-write MFS1RX MFS ch.1 reception interrupt 14 14 read-write MFS0TX MFS ch.0 transmission interrupt 13 13 read-write MFS0RX MFS ch.0 reception interrupt. 12 12 read-write IRQ0BT6 Base timer ch.6 source 0 (IRQ0) interrupt 11 11 read-write IRQ0BT4 Base timer ch.4 source 0 (IRQ0) interrupt 10 10 read-write IRQ0BT2 Base timer ch.2 source 0 (IRQ0) interrupt 9 9 read-write IRQ0BT0 Base timer ch.6 source 0 (IRQ0) interrupt 8 8 read-write ADCSCAN2 A/D converter unit 2 scan conversion interrupt 7 7 read-write ADCSCAN1 A/D converter unit 1 scan conversion interrupt 6 6 read-write ADCSCAN0 A/D converter unit 0 scan conversion interrupt 5 5 read-write USBEP5 USB ch.0 function endpoint 5 DRQ interrupt 4 4 read-write USBEP4 USB ch.0 function endpoint 4 DRQ interrupt 3 3 read-write USBEP3 USB ch.0 function endpoint 3 DRQ interrupt 2 2 read-write USBEP2 USB ch.0 function endpoint 2 DRQ interrupt 1 1 read-write USBEP1 USB ch.0 function endpoint 1 DRQ interrupt 0 0 read-write ODDPKS USB ch.0 Odd Packet Size DMA Enable Register 0x10 8 read-write 0x0 0x1F ODDPKS4 "If the transfer destination address of DMAC is USB.EP5DT, the bit width of the last transfer data is converted to Byte." 4 4 read-write ODDPKS3 "If the transfer destination address of DMAC is USB.EP4DT, the bit width of the last transfer data is converted to Byte." 3 3 read-write ODDPKS2 "If the transfer destination address of DMAC is USB.EP3DT, the bit width of the last transfer data is converted to Byte." 2 2 read-write ODDPKS1 "If the transfer destination address of DMAC is USB.EP2DT, the bit width of the last transfer data is converted to Byte." 1 1 read-write ODDPKS0 "If the transfer destination address of DMAC is USB.EP1DT, the bit width of the last transfer data is converted to Byte." 0 0 read-write ODDPKS1 USB ch.1 Odd Packet Size DMA Enable Register 0x14 8 read-write 0x0 0x1F ODDPKS14 "If the transfer destination address of DMAC is USB.EP5DT, the bit width of the last transfer data is converted to Byte." 4 4 read-write ODDPKS13 "If the transfer destination address of DMAC is USB.EP4DT, the bit width of the last transfer data is converted to Byte." 3 3 read-write ODDPKS12 "If the transfer destination address of DMAC is USB.EP3DT, the bit width of the last transfer data is converted to Byte." 2 2 read-write ODDPKS11 "If the transfer destination address of DMAC is USB.EP2DT, the bit width of the last transfer data is converted to Byte." 1 1 read-write ODDPKS10 "If the transfer destination address of DMAC is USB.EP1DT, the bit width of the last transfer data is converted to Byte." 0 0 read-write IRQ003SEL Relocate Interrupt Selection Register (IRQ003) 0x110 32 read-write 0x0 0x00FF00FF SELBIT Bit7 of the interrupt source is moved to bit7 of the relocate interrupt. 16 23 read-write SELIRQ specify the IRQ no. of a peripheral interrupt to be relocated 0 7 read-write IRQ004SEL Relocate Interrupt Selection Register (IRQ004) 0x114 32 read-write 0x0 0x00FF00FF SELBIT Bit7 of the interrupt source is moved to bit7 of the relocate interrupt. 16 23 read-write SELIRQ specify the IRQ no. of a peripheral interrupt to be relocated 0 7 read-write IRQ005SEL Relocate Interrupt Selection Register (IRQ005) 0x118 32 read-write 0x0 0x00FF00FF SELBIT Bit7 of the interrupt source is moved to bit7 of the relocate interrupt. 16 23 read-write SELIRQ specify the IRQ no. of a peripheral interrupt to be relocated 0 7 read-write IRQ006SEL Relocate Interrupt Selection Register (IRQ006) 0x11C 32 read-write 0x0 0x00FF00FF SELBIT Bit7 of the interrupt source is moved to bit7 of the relocate interrupt. 16 23 read-write SELIRQ specify the IRQ no. of a peripheral interrupt to be relocated 0 7 read-write IRQ007SEL Relocate Interrupt Selection Register (IRQ007) 0x120 32 read-write 0x0 0x00FF00FF SELBIT Bit7 of the interrupt source is moved to bit7 of the relocate interrupt. 16 23 read-write SELIRQ specify the IRQ no. of a peripheral interrupt to be relocated 0 7 read-write IRQ008SEL Relocate Interrupt Selection Register (IRQ008) 0x124 32 read-write 0x0 0x00FF00FF SELBIT Bit7 of the interrupt source is moved to bit7 of the relocate interrupt. 16 23 read-write SELIRQ specify the IRQ no. of a peripheral interrupt to be relocated 0 7 read-write IRQ009SEL Relocate Interrupt Selection Register (IRQ009) 0x128 32 read-write 0x0 0x00FF00FF SELBIT Bit7 of the interrupt source is moved to bit7 of the relocate interrupt. 16 23 read-write SELIRQ specify the IRQ no. of a peripheral interrupt to be relocated 0 7 read-write IRQ010SEL Relocate Interrupt Selection Register (IRQ010) 0x12C 32 read-write 0x0 0x00FF00FF SELBIT Bit7 of the interrupt source is moved to bit7 of the relocate interrupt. 16 23 read-write SELIRQ specify the IRQ no. of a peripheral interrupt to be relocated 0 7 read-write EXC02MON EXC02 batch read register 0x200 32 read-only 0x0 0x3 HWINT Interrupt request of the hardware watchdog timer 1 1 read-only NMI Interrupt request of the NMIX external pin 0 0 read-only IRQ000MON IRQ000 Batch Read Register 0x204 32 read-only 0x0 0x1 FCSINT Interrupt request of the anomalous frequency detected by the CSV 0 0 read-only IRQ001MON IRQ001 Batch Read Register 0x208 32 read-only 0x0 0x1 SWWDTINT interrupt request of the software watchdog timer 0 0 read-only IRQ002MON IRQ002 Batch Read Register 0x20C 32 read-only 0x0 0x1 LVDINT Low-voltage detection (LVD) interrupt request 0 0 read-only IRQ003MON IRQ003 Batch Read Register 0x210 32 read-only 0x0 0xFF IRQBIT7 interrupt request of the interrupt selected in bit7 of IRQ003SEL Register 7 7 read-only IRQBIT6 interrupt request of the interrupt selected in bit6 of IRQ003SEL Register 6 6 read-only IRQBIT5 interrupt request of the interrupt selected in bit5 of IRQ003SEL Register 5 5 read-only IRQBIT4 interrupt request of the interrupt selected in bit4 of IRQ003SEL Register 4 4 read-only IRQBIT3 interrupt request of the interrupt selected in bit3 of IRQ003SEL Register 3 3 read-only IRQBIT2 interrupt request of the interrupt selected in bit2 of IRQ003SEL Register 2 2 read-only IRQBIT1 interrupt request of the interrupt selected in bit1 of IRQ003SEL Register 1 1 read-only IRQBIT0 interrupt request of the interrupt selected in bit0 of IRQ003SEL Register 0 0 read-only IRQ004MON IRQ004 Batch Read Register 0x214 32 read-only 0x0 0xFF IRQBIT7 interrupt request of the interrupt selected in bit7 of IRQ004SEL Register 7 7 read-only IRQBIT6 interrupt request of the interrupt selected in bit6 of IRQ004SEL Register 6 6 read-only IRQBIT5 interrupt request of the interrupt selected in bit5 of IRQ004SEL Register 5 5 read-only IRQBIT4 interrupt request of the interrupt selected in bit4 of IRQ004SEL Register 4 4 read-only IRQBIT3 interrupt request of the interrupt selected in bit3 of IRQ004SEL Register 3 3 read-only IRQBIT2 interrupt request of the interrupt selected in bit2 of IRQ004SEL Register 2 2 read-only IRQBIT1 interrupt request of the interrupt selected in bit1 of IRQ004SEL Register 1 1 read-only IRQBIT0 interrupt request of the interrupt selected in bit0 of IRQ004SEL Register 0 0 read-only IRQ005MON IRQ005 Batch Read Register 0x218 32 read-only 0x0 0xFF IRQBIT7 interrupt request of the interrupt selected in bit7 of IRQ005SEL Register 7 7 read-only IRQBIT6 interrupt request of the interrupt selected in bit6 of IRQ005SEL Register 6 6 read-only IRQBIT5 interrupt request of the interrupt selected in bit5 of IRQ005SEL Register 5 5 read-only IRQBIT4 interrupt request of the interrupt selected in bit4 of IRQ005SEL Register 4 4 read-only IRQBIT3 interrupt request of the interrupt selected in bit3 of IRQ005SEL Register 3 3 read-only IRQBIT2 interrupt request of the interrupt selected in bit2 of IRQ005SEL Register 2 2 read-only IRQBIT1 interrupt request of the interrupt selected in bit1 of IRQ005SEL Register 1 1 read-only IRQBIT0 interrupt request of the interrupt selected in bit0 of IRQ005SEL Register 0 0 read-only IRQ006MON IRQ006 Batch Read Register 0x21C 32 read-only 0x0 0xFF IRQBIT7 interrupt request of the interrupt selected in bit7 of IRQ006SEL Register 7 7 read-only IRQBIT6 interrupt request of the interrupt selected in bit6 of IRQ006SEL Register 6 6 read-only IRQBIT5 interrupt request of the interrupt selected in bit5 of IRQ006SEL Register 5 5 read-only IRQBIT4 interrupt request of the interrupt selected in bit4 of IRQ006SEL Register 4 4 read-only IRQBIT3 interrupt request of the interrupt selected in bit3 of IRQ006SEL Register 3 3 read-only IRQBIT2 interrupt request of the interrupt selected in bit2 of IRQ006SEL Register 2 2 read-only IRQBIT1 interrupt request of the interrupt selected in bit1 of IRQ006SEL Register 1 1 read-only IRQBIT0 interrupt request of the interrupt selected in bit0 of IRQ006SEL Register 0 0 read-only IRQ007MON IRQ007 Batch Read Register 0x220 32 read-only 0x0 0xFF IRQBIT7 interrupt request of the interrupt selected in bit7 of IRQ007SEL Register 7 7 read-only IRQBIT6 interrupt request of the interrupt selected in bit6 of IRQ007SEL Register 6 6 read-only IRQBIT5 interrupt request of the interrupt selected in bit5 of IRQ007SEL Register 5 5 read-only IRQBIT4 interrupt request of the interrupt selected in bit4 of IRQ007SEL Register 4 4 read-only IRQBIT3 interrupt request of the interrupt selected in bit3 of IRQ007SEL Register 3 3 read-only IRQBIT2 interrupt request of the interrupt selected in bit2 of IRQ007SEL Register 2 2 read-only IRQBIT1 interrupt request of the interrupt selected in bit1 of IRQ007SEL Register 1 1 read-only IRQBIT0 interrupt request of the interrupt selected in bit0 of IRQ007SEL Register 0 0 read-only IRQ008MON IRQ008 Batch Read Register 0x224 32 read-only 0x0 0xFF IRQBIT7 interrupt request of the interrupt selected in bit7 of IRQ008SEL Register 7 7 read-only IRQBIT6 interrupt request of the interrupt selected in bit6 of IRQ008SEL Register 6 6 read-only IRQBIT5 interrupt request of the interrupt selected in bit5 of IRQ008SEL Register 5 5 read-only IRQBIT4 interrupt request of the interrupt selected in bit4 of IRQ008SEL Register 4 4 read-only IRQBIT3 interrupt request of the interrupt selected in bit3 of IRQ008SEL Register 3 3 read-only IRQBIT2 interrupt request of the interrupt selected in bit2 of IRQ008SEL Register 2 2 read-only IRQBIT1 interrupt request of the interrupt selected in bit1 of IRQ008SEL Register 1 1 read-only IRQBIT0 interrupt request of the interrupt selected in bit0 of IRQ008SEL Register 0 0 read-only IRQ009MON IRQ009 Batch Read Register 0x228 32 read-only 0x0 0xFF IRQBIT7 interrupt request of the interrupt selected in bit7 of IRQ009SEL Register 7 7 read-only IRQBIT6 interrupt request of the interrupt selected in bit6 of IRQ009SEL Register 6 6 read-only IRQBIT5 interrupt request of the interrupt selected in bit5 of IRQ009SEL Register 5 5 read-only IRQBIT4 interrupt request of the interrupt selected in bit4 of IRQ009SEL Register 4 4 read-only IRQBIT3 interrupt request of the interrupt selected in bit3 of IRQ009SEL Register 3 3 read-only IRQBIT2 interrupt request of the interrupt selected in bit2 of IRQ009SEL Register 2 2 read-only IRQBIT1 interrupt request of the interrupt selected in bit1 of IRQ009SEL Register 1 1 read-only IRQBIT0 interrupt request of the interrupt selected in bit0 of IRQ009SEL Register 0 0 read-only IRQ010MON IRQ010 Batch Read Register 0x22C 32 read-only 0x0 0xFF IRQBIT7 interrupt request of the interrupt selected in bit7 of IRQ010SEL Register 7 7 read-only IRQBIT6 interrupt request of the interrupt selected in bit6 of IRQ010SEL Register 6 6 read-only IRQBIT5 interrupt request of the interrupt selected in bit5 of IRQ010SEL Register 5 5 read-only IRQBIT4 interrupt request of the interrupt selected in bit4 of IRQ010SEL Register 4 4 read-only IRQBIT3 interrupt request of the interrupt selected in bit3 of IRQ010SEL Register 3 3 read-only IRQBIT2 interrupt request of the interrupt selected in bit2 of IRQ010SEL Register 2 2 read-only IRQBIT1 interrupt request of the interrupt selected in bit1 of IRQ010SEL Register 1 1 read-only IRQBIT0 interrupt request of the interrupt selected in bit0 of IRQ010SEL Register 0 0 read-only IRQ011MON IRQ011 Batch Read Register 0x230 32 read-only 0x0 0x1 EXTINT Interrupt request of the external pin interrupt ch.0 0 0 read-only IRQ012MON IRQ012 Batch Read Register 0x234 32 read-only 0x0 0x1 EXTINT Interrupt request of the external pin interrupt ch.1 0 0 read-only IRQ013MON IRQ013 Batch Read Register 0x238 32 read-only 0x0 0x1 EXTINT Interrupt request of the external pin interrupt ch.2 0 0 read-only IRQ014MON IRQ014 Batch Read Register 0x23C 32 read-only 0x0 0x1 EXTINT Interrupt request of the external pin interrupt ch.3 0 0 read-only IRQ015MON IRQ015 Batch Read Register 0x240 32 read-only 0x0 0x1 EXTINT Interrupt request of the external pin interrupt ch.4 0 0 read-only IRQ016MON IRQ016 Batch Read Register 0x244 32 read-only 0x0 0x1 EXTINT Interrupt request of the external pin interrupt ch.5 0 0 read-only IRQ017MON IRQ017 Batch Read Register 0x248 32 read-only 0x0 0x1 EXTINT Interrupt request of the external pin interrupt ch.6 0 0 read-only IRQ018MON IRQ018 Batch Read Register 0x24C 32 read-only 0x0 0x1 EXTINT Interrupt request of the external pin interrupt ch.7 0 0 read-only IRQ019MON IRQ019 Batch Read Register 0x250 32 read-only 0x0 0x3F QUDINT5 PC match and RC match interrupt request of QPRC ch.0 5 5 read-only QUDINT4 Out-of-range interrupt request of QPRC ch.0QPRC ch.0 4 4 read-only QUDINT3 Count inversion interrupt request of QPRC ch.0 3 3 read-only QUDINT2 Overflow / underflow / zero index interrupt request of QPRC ch.0 2 2 read-only QUDINT1 PC and RC match interrupt request of QPRC ch.0 1 1 read-only QUDINT0 PC match interrupt request of QPRC ch.0 0 0 read-only IRQ020MON IRQ020 Batch Read Register 0x254 32 read-only 0x0 0x3F QUDINT5 PC match and RC match interrupt request of QPRC ch.1 5 5 read-only QUDINT4 Out-of-range interrupt request of QPRC ch.1QPRC ch.1 4 4 read-only QUDINT3 Count inversion interrupt request of QPRC ch.1 3 3 read-only QUDINT2 Overflow / underflow / zero index interrupt request of QPRC ch.1 2 2 read-only QUDINT1 PC and RC match interrupt request of QPRC ch.1 1 1 read-only QUDINT0 PC match interrupt request of QPRC ch.1 0 0 read-only IRQ021MON IRQ021 Batch Read Register 0x258 32 read-only 0x0 0x0F WAVEINT3 Interrupt request of WFG timer 54 of the MFT unit 0 3 3 read-only WAVEINT2 Interrupt request of WFG timer 32 of the MFT unit 0 2 2 read-only WAVEINT1 Interrupt request of WFG timer 10 of the MFT unit 0 1 1 read-only WAVEINT0 Interrupt request of the DTIF (motor emergency stop) of the MFT unit 0 0 0 read-only IRQ022MON IRQ022 Batch Read Register 0x25C 32 read-only 0x0 0x0F WAVEINT3 Interrupt request of WFG timer 54 of the MFT unit 1 3 3 read-only WAVEINT2 Interrupt request of WFG timer 32 of the MFT unit 1 2 2 read-only WAVEINT1 Interrupt request of WFG timer 10 of the MFT unit 1 1 1 read-only WAVEINT0 Interrupt request of the DTIF (motor emergency stop) of the MFT unit 1 0 0 read-only IRQ023MON IRQ023 Batch Read Register 0x260 32 read-only 0x0 0x0F WAVEINT3 Interrupt request of WFG timer 54 of the MFT unit 2 3 3 read-only WAVEINT2 Interrupt request of WFG timer 32 of the MFT unit 2 2 2 read-only WAVEINT1 Interrupt request of WFG timer 10 of the MFT unit 2 1 1 read-only WAVEINT0 Interrupt request of the DTIF (motor emergency stop) of the MFT unit 2 0 0 read-only IRQ024MON IRQ024 Batch Read Register 0x264 32 read-only 0x0 0x07 FRT_PEAK_INT2 FRT ch.2 peak value detection interrupt request of the MFT unit 0 2 2 read-only FRT_PEAK_INT1 FRT ch.1 peak value detection interrupt request of the MFT unit 0 1 1 read-only FRT_PEAK_INT0 FRT ch.0 peak value detection interrupt request of the MFT unit 0 0 0 read-only IRQ025MON IRQ025 Batch Read Register 0x268 32 read-only 0x0 0x07 FRT_ZERO_INT2 FRT ch.2 zero detection interrupt request of the MFT unit 0 2 2 read-only FRT_ZERO_INT1 FRT ch.1 zero detection interrupt request of the MFT unit 0 1 1 read-only FRT_ZERO_INT0 FRT ch.0 zero detection interrupt request of the MFT unit 0 0 0 read-only IRQ026MON IRQ026 Batch Read Register 0x26C 32 read-only 0x0 0x0F ICUINT3 ICU ch.3 input edge detection interrupt request of the MFT unit 0 3 3 read-only ICUINT2 ICU ch.2 input edge detection interrupt request of the MFT unit 0 2 2 read-only ICUINT1 ICU ch.1 input edge detection interrupt request of the MFT unit 0 1 1 read-only ICUINT0 ICU ch.0 input edge detection interrupt request of the MFT unit 0 0 0 read-only IRQ027MON IRQ027 Batch Read Register 0x270 32 read-only 0x0 0x3F OCUINT5 OCU ch.5 match detection interrupt request of the MFT unit 0 5 5 read-only OCUINT4 OCU ch.4 match detection interrupt request of the MFT unit 0 4 4 read-only OCUINT3 OCU ch.3 match detection interrupt request of the MFT unit 0 3 3 read-only OCUINT2 OCU ch.2 match detection interrupt request of the MFT unit 0 2 2 read-only OCUINT1 OCU ch.1 match detection interrupt request of the MFT unit 0 1 1 read-only OCUINT0 OCU ch.0 match detection interrupt request of the MFT unit 0 0 0 read-only IRQ028MON IRQ028 Batch Read Register 0x274 32 read-only 0x0 0x07 FRT_PEAK_INT2 FRT ch.2 peak value detection interrupt request of the MFT unit 1 2 2 read-only FRT_PEAK_INT1 FRT ch.1 peak value detection interrupt request of the MFT unit 1 1 1 read-only FRT_PEAK_INT0 FRT ch.0 peak value detection interrupt request of the MFT unit 1 0 0 read-only IRQ029MON IRQ029 Batch Read Register 0x278 32 read-only 0x0 0x07 FRT_ZERO_INT2 FRT ch.2 zero detection interrupt request of the MFT unit 1 2 2 read-only FRT_ZERO_INT1 FRT ch.1 zero detection interrupt request of the MFT unit 1 1 1 read-only FRT_ZERO_INT0 FRT ch.0 zero detection interrupt request of the MFT unit 1 0 0 read-only IRQ030MON IRQ030 Batch Read Register 0x27C 32 read-only 0x0 0x0F ICUINT3 ICU ch.3 input edge detection interrupt request of the MFT unit 1 3 3 read-only ICUINT2 ICU ch.2 input edge detection interrupt request of the MFT unit 1 2 2 read-only ICUINT1 ICU ch.1 input edge detection interrupt request of the MFT unit 1 1 1 read-only ICUINT0 ICU ch.0 input edge detection interrupt request of the MFT unit 1 0 0 read-only IRQ031MON IRQ031 Batch Read Register 0x280 32 read-only 0x0 0x3F OCUINT5 OCU ch.5 match detection interrupt request of the MFT unit 1 5 5 read-only OCUINT4 OCU ch.4 match detection interrupt request of the MFT unit 1 4 4 read-only OCUINT3 OCU ch.3 match detection interrupt request of the MFT unit 1 3 3 read-only OCUINT2 OCU ch.2 match detection interrupt request of the MFT unit 1 2 2 read-only OCUINT1 OCU ch.1 match detection interrupt request of the MFT unit 1 1 1 read-only OCUINT0 OCU ch.0 match detection interrupt request of the MFT unit 1 0 0 read-only IRQ032MON IRQ032 Batch Read Register 0x284 32 read-only 0x0 0x07 FRT_PEAK_INT2 FRT ch.2 peak value detection interrupt request of the MFT unit 2 2 2 read-only FRT_PEAK_INT1 FRT ch.1 peak value detection interrupt request of the MFT unit 2 1 1 read-only FRT_PEAK_INT0 FRT ch.0 peak value detection interrupt request of the MFT unit 2 0 0 read-only IRQ033MON IRQ033 Batch Read Register 0x288 32 read-only 0x0 0x07 FRT_ZERO_INT2 FRT ch.2 zero detection interrupt request of the MFT unit 2 2 2 read-only FRT_ZERO_INT1 FRT ch.1 zero detection interrupt request of the MFT unit 2 1 1 read-only FRT_ZERO_INT0 FRT ch.0 zero detection interrupt request of the MFT unit 2 0 0 read-only IRQ034MON IRQ034 Batch Read Register 0x28C 32 read-only 0x0 0x0F ICUINT3 ICU ch.3 input edge detection interrupt request of the MFT unit 2 3 3 read-only ICUINT2 ICU ch.2 input edge detection interrupt request of the MFT unit 2 2 2 read-only ICUINT1 ICU ch.1 input edge detection interrupt request of the MFT unit 2 1 1 read-only ICUINT0 ICU ch.0 input edge detection interrupt request of the MFT unit 2 0 0 read-only IRQ035MON IRQ035 Batch Read Register 0x290 32 read-only 0x0 0x3F OCUINT5 OCU ch.5 match detection interrupt request of the MFT unit 2 5 5 read-only OCUINT4 OCU ch.4 match detection interrupt request of the MFT unit 2 4 4 read-only OCUINT3 OCU ch.3 match detection interrupt request of the MFT unit 2 3 3 read-only OCUINT2 OCU ch.2 match detection interrupt request of the MFT unit 2 2 2 read-only OCUINT1 OCU ch.1 match detection interrupt request of the MFT unit 2 1 1 read-only OCUINT0 OCU ch.0 match detection interrupt request of the MFT unit 2 0 0 read-only IRQ036MON IRQ036 Batch Read Register 0x294 32 read-only 0x0 0x07 PPGINT2 Interrupt request of the PPG ch.4 2 2 read-only PPGINT1 Interrupt request of the PPG ch.2 1 1 read-only PPGINT0 Interrupt request of the PPG ch.0 0 0 read-only IRQ037MON IRQ037 Batch Read Register 0x298 32 read-only 0x0 0x07 PPGINT2 Interrupt request of the PPG ch.12 2 2 read-only PPGINT1 Interrupt request of the PPG ch.10 1 1 read-only PPGINT0 Interrupt request of the PPG ch.8 0 0 read-only IRQ038MON IRQ038 Batch Read Register 0x29C 32 read-only 0x0 0x07 PPGINT2 Interrupt request of the PPG ch.20 2 2 read-only PPGINT1 Interrupt request of the PPG ch.18 1 1 read-only PPGINT0 Interrupt request of the PPG ch.16 0 0 read-only IRQ039MON IRQ039 Batch Read Register 0x2A0 32 read-only 0x0 0x03 BTINT1 Interrupt request of source 1 (IRQ1) of the base timer ch.0 1 1 read-only BTINT0 Interrupt request of source 0 (IRQ0) of the base timer ch.0 0 0 read-only IRQ040MON IRQ040 Batch Read Register 0x2A4 32 read-only 0x0 0x03 BTINT1 Interrupt request of source 1 (IRQ1) of the base timer ch.1 1 1 read-only BTINT0 Interrupt request of source 0 (IRQ0) of the base timer ch.1 0 0 read-only IRQ041MON IRQ041 Batch Read Register 0x2A8 32 read-only 0x0 0x03 BTINT1 Interrupt request of source 1 (IRQ1) of the base timer ch.2 1 1 read-only BTINT0 Interrupt request of source 0 (IRQ0) of the base timer ch.2 0 0 read-only IRQ042MON IRQ042 Batch Read Register 0x2AC 32 read-only 0x0 0x03 BTINT1 Interrupt request of source 1 (IRQ1) of the base timer ch.3 1 1 read-only BTINT0 Interrupt request of source 0 (IRQ0) of the base timer ch.3 0 0 read-only IRQ043MON IRQ043 Batch Read Register 0x2B0 32 read-only 0x0 0x03 BTINT1 Interrupt request of source 1 (IRQ1) of the base timer ch.4 1 1 read-only BTINT0 Interrupt request of source 0 (IRQ0) of the base timer ch.4 0 0 read-only IRQ044MON IRQ044 Batch Read Register 0x2B4 32 read-only 0x0 0x03 BTINT1 Interrupt request of source 1 (IRQ1) of the base timer ch.5 1 1 read-only BTINT0 Interrupt request of source 0 (IRQ0) of the base timer ch.5 0 0 read-only IRQ045MON IRQ045 Batch Read Register 0x2B8 32 read-only 0x0 0x03 BTINT1 Interrupt request of source 1 (IRQ1) of the base timer ch.6 1 1 read-only BTINT0 Interrupt request of source 0 (IRQ0) of the base timer ch.6 0 0 read-only IRQ046MON IRQ046 Batch Read Register 0x2BC 32 read-only 0x0 0x03 BTINT1 Interrupt request of source 1 (IRQ1) of the base timer ch.7 1 1 read-only BTINT0 Interrupt request of source 0 (IRQ0) of the base timer ch.7 0 0 read-only IRQ047MON IRQ047 Batch Read Register 0x2C0 32 read-only 0x0 0x03 TIMINT2 Dual timer TIMINT2 interrupt request 1 1 read-only TIMINT1 Dual timer TIMINT1 interrupt request 0 0 read-only IRQ048MON IRQ048 Batch Read Register 0x2C4 32 read-only 0x0 0x01 WCINT Interrupt request of the watch counter 0 0 read-only IRQ049MON IRQ049 Batch Read Register 0x2C8 32 read-only 0x0 0x01 BMEMCS External bus output error interrupt request 0 0 read-only IRQ050MON IRQ050 Batch Read Register 0x2CC 32 read-only 0x0 0x01 RTCINT Interrupt request of the RTC$ 0 0 read-only IRQ051MON IRQ051 Batch Read Register 0x2D0 32 read-only 0x0 0x1 EXTINT Interrupt request of the external pin interrupt ch.8 0 0 read-only IRQ052MON IRQ052 Batch Read Register 0x2D4 32 read-only 0x0 0x1 EXTINT Interrupt request of the external pin interrupt ch.9 0 0 read-only IRQ053MON IRQ053 Batch Read Register 0x2D8 32 read-only 0x0 0x1 EXTINT Interrupt request of the external pin interrupt ch.10 0 0 read-only IRQ054MON IRQ054 Batch Read Register 0x2DC 32 read-only 0x0 0x1 EXTINT Interrupt request of the external pin interrupt ch.11 0 0 read-only IRQ055MON IRQ055 Batch Read Register 0x2E0 32 read-only 0x0 0x1 EXTINT Interrupt request of the external pin interrupt ch.12 0 0 read-only IRQ056MON IRQ056 Batch Read Register 0x2E4 32 read-only 0x0 0x1 EXTINT Interrupt request of the external pin interrupt ch.13 0 0 read-only IRQ057MON IRQ057 Batch Read Register 0x2E8 32 read-only 0x0 0x1 EXTINT Interrupt request of the external pin interrupt ch.14 0 0 read-only IRQ058MON IRQ058 Batch Read Register 0x2EC 32 read-only 0x0 0x1 EXTINT Interrupt request of the external pin interrupt ch.15 0 0 read-only IRQ059MON IRQ059 Batch Read Register 0x2F0 32 read-only 0x0 0x1F IPLLINT PLL of I2S oscillation stabilization wait completion interrupt 4 4 read-only UPLLINT PLL of USB / Ethernet oscillation stabilization wait completion interrupt 3 3 read-only MPLLINT Main PLL oscillation stabilization wait completion interrupt 2 2 read-only SOSCINT Sub clock oscillation stabilization wait completion interrupt 1 1 read-only MOSCINT Main clock oscillation stabilization wait completion interrupt 0 0 read-only IRQ060MON IRQ060 Batch Read Register 0x2F4 32 read-only 0x0 0x1 MFSRINT Reception interrupt request of the MFS ch.0 0 0 read-only IRQ061MON IRQ061 Batch Read Register 0x2F8 32 read-only 0x0 0x3 MFSINT1 Status interrupt request of the MFS ch.0 1 1 read-only MFSINT0 Transmission interrupt request of the MFS ch.0 0 0 read-only IRQ062MON IRQ062 Batch Read Register 0x2FC 32 read-only 0x0 0x1 MFSRINT Reception interrupt request of the MFS ch.1 0 0 read-only IRQ063MON IRQ063 Batch Read Register 0x300 32 read-only 0x0 0x3 MFSINT1 Status interrupt request of the MFS ch.1 1 1 read-only MFSINT0 Transmission interrupt request of the MFS ch.1 0 0 read-only IRQ064MON IRQ064 Batch Read Register 0x304 32 read-only 0x0 0x1 MFSRINT Reception interrupt request of the MFS ch.2 0 0 read-only IRQ065MON IRQ065 Batch Read Register 0x308 32 read-only 0x0 0x3 MFSINT1 Status interrupt request of the MFS ch.2 1 1 read-only MFSINT0 Transmission interrupt request of the MFS ch.2 0 0 read-only IRQ066MON IRQ066 Batch Read Register 0x30C 32 read-only 0x0 0x1 MFSRINT Reception interrupt request of the MFS ch.3 0 0 read-only IRQ067MON IRQ067 Batch Read Register 0x310 32 read-only 0x0 0x3 MFSINT1 Status interrupt request of the MFS ch.3 1 1 read-only MFSINT0 Transmission interrupt request of the MFS ch.3 0 0 read-only IRQ068MON IRQ068 Batch Read Register 0x314 32 read-only 0x0 0x1 MFSRINT Reception interrupt request of the MFS ch.4 0 0 read-only IRQ069MON IRQ069 Batch Read Register 0x318 32 read-only 0x0 0x3 MFSINT1 Status interrupt request of the MFS ch.4 1 1 read-only MFSINT0 Transmission interrupt request of the MFS ch.4 0 0 read-only IRQ070MON IRQ070 Batch Read Register 0x31C 32 read-only 0x0 0x1 MFSRINT Reception interrupt request of the MFS ch.5 0 0 read-only IRQ071MON IRQ071 Batch Read Register 0x320 32 read-only 0x0 0x3 MFSINT1 Status interrupt request of the MFS ch.5 1 1 read-only MFSINT0 Transmission interrupt request of the MFS ch.5 0 0 read-only IRQ072MON IRQ072 Batch Read Register 0x324 32 read-only 0x0 0x1 MFSRINT Reception interrupt request of the MFS ch.6 0 0 read-only IRQ073MON IRQ073 Batch Read Register 0x328 32 read-only 0x0 0x3 MFSINT1 Status interrupt request of the MFS ch.6 1 1 read-only MFSINT0 Transmission interrupt request of the MFS ch.6 0 0 read-only IRQ074MON IRQ074 Batch Read Register 0x32C 32 read-only 0x0 0x1 MFSRINT Reception interrupt request of the MFS ch.7 0 0 read-only IRQ075MON IRQ075 Batch Read Register 0x330 32 read-only 0x0 0x3 MFSINT1 Status interrupt request of the MFS ch.7 1 1 read-only MFSINT0 Transmission interrupt request of the MFS ch.7 0 0 read-only IRQ076MON IRQ076 Batch Read Register 0x334 32 read-only 0x0 0x1F ADCINT4 Range comparison result interrupt request of the A/D converter unit 0 4 4 read-only ADCINT3 Conversion result comparison interrupt request of the A/D converter unit 0 3 3 read-only ADCINT2 FIFO overrun interrupt request of the A/D converter unit 0 2 2 read-only ADCINT1 Scan conversion interrupt request of the A/D converter unit 0 1 1 read-only ADCINT0 Priority conversion interrupt request of the A/D converter unit 0 0 0 read-only IRQ077MON IRQ077 Batch Read Register 0x338 32 read-only 0x0 0x1F ADCINT4 Range comparison result interrupt request of the A/D converter unit 1 4 4 read-only ADCINT3 Conversion result comparison interrupt request of the A/D converter unit 1 3 3 read-only ADCINT2 FIFO overrun interrupt request of the A/D converter unit 1 2 2 read-only ADCINT1 Scan conversion interrupt request of the A/D converter unit 1 1 1 read-only ADCINT0 Priority conversion interrupt request of the A/D converter unit 1 0 0 read-only IRQ078MON IRQ078 Batch Read Register 0x33C 32 read-only 0x0 0x1F USB_DRQ_INT4 Endpoint 5 DRQ interrupt request of the USB ch.0 4 4 read-only USB_DRQ_INT3 Endpoint 4 DRQ interrupt request of the USB ch.0 3 3 read-only USB_DRQ_INT2 Endpoint 3 DRQ interrupt request of the USB ch.0 2 2 read-only USB_DRQ_INT1 Endpoint 2 DRQ interrupt request of the USB ch.0 1 1 read-only USB_DRQ_INT0 Endpoint 1 DRQ interrupt request of the USB ch.0 0 0 read-only IRQ079MON IRQ079 Batch Read Register 0x340 32 read-only 0x0 0x3F USB_INT5 SOFIRQ/CMPIRQ interrupt request of the USB ch.0 5 5 read-only USB_INT4 DIRQ/URPIRQ/RWKIRQ/CNNIRQ interrupt request of the USB ch.0 4 4 read-only USB_INT3 SPK interrupt request of the USB ch.0 3 3 read-only USB_INT2 SUSP/SOF/BRST/CONF/WKUP interrupt request of the USB ch.0 2 2 read-only USB_INT1 Endpoint 0 DRQO interrupt request of the USB ch.0 1 1 read-only USB_INT0 Endpoint 0 DRQI interrupt request of the USB ch.0 0 0 read-only IRQ080MON IRQ080 Batch Read Register 0x344 32 read-only 0x0 0x1 CANINT Interrupt request of the CAN ch.0 0 0 read-only IRQ081MON IRQ081 Batch Read Register 0x348 32 read-only 0x0 0x1F CAN1INT CAN-FD 1 interrupt request 4 4 read-only CAN0INT CAN-FD 0 interrupt request 3 3 read-only CANSEINT Single bit error interrupt request of the CAN-FD 2 2 read-only CANDEINT Double bit error interrupt request of the CAN-FD 1 1 read-only CANINT Interrupt request of the CAN ch.1 0 0 read-only IRQ082MON IRQ082 Batch Read Register 0x34C 32 read-only 0x0 0x7 MACLPI LPI interrupt request of the Ethernet MAC 2 2 read-only MACPMT PMT interrupt request of the Ethernet MAC 1 1 read-only MACSBD SBD interrupt request of the Ethernet MAC 0 0 read-only IRQ083MON IRQ083 Batch Read Register 0x350 32 read-only 0x0 0x1 DMACINT Interrupt request of the DMAC ch.0 0 0 read-only IRQ084MON IRQ084 Batch Read Register 0x354 32 read-only 0x0 0x1 DMACINT Interrupt request of the DMAC ch.1 0 0 read-only IRQ085MON IRQ085 Batch Read Register 0x358 32 read-only 0x0 0x1 DMACINT Interrupt request of the DMAC ch.2 0 0 read-only IRQ086MON IRQ086 Batch Read Register 0x35C 32 read-only 0x0 0x1 DMACINT Interrupt request of the DMAC ch.3 0 0 read-only IRQ087MON IRQ087 Batch Read Register 0x360 32 read-only 0x0 0x1 DMACINT Interrupt request of the DMAC ch.4 0 0 read-only IRQ088MON IRQ088 Batch Read Register 0x364 32 read-only 0x0 0x1 DMACINT Interrupt request of the DMAC ch.5 0 0 read-only IRQ089MON IRQ089 Batch Read Register 0x368 32 read-only 0x0 0x1 DMACINT Interrupt request of the DMAC ch.6 0 0 read-only IRQ090MON IRQ090 Batch Read Register 0x36C 32 read-only 0x0 0x1 DMACINT Interrupt request of the DMAC ch.7 0 0 read-only IRQ091MON IRQ091 Batch Read Register 0x370 32 read-only 0x0 0x3 DSTCINT1 DSTC ERINT interrupt request 1 1 read-only DSTCINT0 DSTC SWINT interrupt request 0 0 read-only IRQ092MON IRQ092 Batch Read Register 0x374 32 read-only 0x0 0x0F EXTINT3 Interrupt request of the external pin interrupt ch.19 3 3 read-only EXTINT2 Interrupt request of the external pin interrupt ch.18 2 2 read-only EXTINT1 Interrupt request of the external pin interrupt ch.17 1 1 read-only EXTINT0 Interrupt request of the external pin interrupt ch.16 0 0 read-only IRQ093MON IRQ093 Batch Read Register 0x378 32 read-only 0x0 0x0F EXTINT3 Interrupt request of the external pin interrupt ch.23 3 3 read-only EXTINT2 Interrupt request of the external pin interrupt ch.22 2 2 read-only EXTINT1 Interrupt request of the external pin interrupt ch.21 1 1 read-only EXTINT0 Interrupt request of the external pin interrupt ch.20 0 0 read-only IRQ094MON IRQ094 Batch Read Register 0x37C 32 read-only 0x0 0x0F EXTINT3 Interrupt request of the external pin interrupt ch.27 3 3 read-only EXTINT2 Interrupt request of the external pin interrupt ch.26 2 2 read-only EXTINT1 Interrupt request of the external pin interrupt ch.25 1 1 read-only EXTINT0 Interrupt request of the external pin interrupt ch.24 0 0 read-only IRQ095MON IRQ095 Batch Read Register 0x380 32 read-only 0x0 0x0F EXTINT3 Interrupt request of the external pin interrupt ch.31 3 3 read-only EXTINT2 Interrupt request of the external pin interrupt ch.30 2 2 read-only EXTINT1 Interrupt request of the external pin interrupt ch.29 1 1 read-only EXTINT0 Interrupt request of the external pin interrupt ch.28 0 0 read-only IRQ096MON IRQ096 Batch Read Register 0x384 32 read-only 0x0 0x3F QUDINT5 PC match and RC match interrupt request of QPRC ch.2 5 5 read-only QUDINT4 Out-of-range interrupt request of QPRC ch.2QPRC ch.2 4 4 read-only QUDINT3 Count inversion interrupt request of QPRC ch.2 3 3 read-only QUDINT2 Overflow / underflow / zero index interrupt request of QPRC ch.2 2 2 read-only QUDINT1 PC and RC match interrupt request of QPRC ch.2 1 1 read-only QUDINT0 PC match interrupt request of QPRC ch.2 0 0 read-only IRQ097MON IRQ097 Batch Read Register 0x388 32 read-only 0x0 0x3F QUDINT5 PC match and RC match interrupt request of QPRC ch.3 5 5 read-only QUDINT4 Out-of-range interrupt request of QPRC ch.3QPRC ch.3 4 4 read-only QUDINT3 Count inversion interrupt request of QPRC ch.3 3 3 read-only QUDINT2 Overflow / underflow / zero index interrupt request of QPRC ch.3 2 2 read-only QUDINT1 PC and RC match interrupt request of QPRC ch.3 1 1 read-only QUDINT0 PC match interrupt request of QPRC ch.3 0 0 read-only IRQ098MON IRQ098 Batch Read Register 0x38C 32 read-only 0x0 0x03 BTINT1 Interrupt request of source 1 (IRQ1) of the base timer ch.8 1 1 read-only BTINT0 Interrupt request of source 0 (IRQ0) of the base timer ch.8 0 0 read-only IRQ099MON IRQ099 Batch Read Register 0x390 32 read-only 0x0 0x03 BTINT1 Interrupt request of source 1 (IRQ1) of the base timer ch.9 1 1 read-only BTINT0 Interrupt request of source 0 (IRQ0) of the base timer ch.9 0 0 read-only IRQ100MON IRQ100 Batch Read Register 0x394 32 read-only 0x0 0x03 BTINT1 Interrupt request of source 1 (IRQ1) of the base timer ch.10 1 1 read-only BTINT0 Interrupt request of source 0 (IRQ0) of the base timer ch.10 0 0 read-only IRQ101MON IRQ101 Batch Read Register 0x398 32 read-only 0x0 0x03 BTINT1 Interrupt request of source 1 (IRQ1) of the base timer ch.11 1 1 read-only BTINT0 Interrupt request of source 0 (IRQ0) of the base timer ch.11 0 0 read-only IRQ102MON IRQ102 Batch Read Register 0x39C 32 read-only 0x0 0xFF BTINT7 Interrupt request of source 1 (IRQ1) of the base timer ch.15 7 7 read-only BTINT6 Interrupt request of source 0 (IRQ0) of the base timer ch.15 6 6 read-only BTINT5 Interrupt request of source 1 (IRQ1) of the base timer ch.14 5 5 read-only BTINT4 Interrupt request of source 0 (IRQ0) of the base timer ch.14 4 4 read-only BTINT3 Interrupt request of source 1 (IRQ1) of the base timer ch.13 3 3 read-only BTINT2 Interrupt request of source 0 (IRQ0) of the base timer ch.13 2 2 read-only BTINT1 Interrupt request of source 1 (IRQ1) of the base timer ch.12 1 1 read-only BTINT0 Interrupt request of source 0 (IRQ0) of the base timer ch.12 0 0 read-only IRQ103MON IRQ103 Batch Read Register 0x3A0 32 read-only 0x0 0x1 MFSRINT Reception interrupt request of the MFS ch.8 0 0 read-only IRQ104MON IRQ104 Batch Read Register 0x3A4 32 read-only 0x0 0x3 MFSINT1 Status interrupt request of the MFS ch.8 1 1 read-only MFSINT0 Transmission interrupt request of the MFS ch.8 0 0 read-only IRQ105MON IRQ105 Batch Read Register 0x3A8 32 read-only 0x0 0x1 MFSRINT Reception interrupt request of the MFS ch.9 0 0 read-only IRQ106MON IRQ106 Batch Read Register 0x3AC 32 read-only 0x0 0x3 MFSINT1 Status interrupt request of the MFS ch.9 1 1 read-only MFSINT0 Transmission interrupt request of the MFS ch.9 0 0 read-only IRQ107MON IRQ107 Batch Read Register 0x3B0 32 read-only 0x0 0x1 MFSRINT Reception interrupt request of the MFS ch.10 0 0 read-only IRQ108MON IRQ108 Batch Read Register 0x3B4 32 read-only 0x0 0x3 MFSINT1 Status interrupt request of the MFS ch.10 1 1 read-only MFSINT0 Transmission interrupt request of the MFS ch.10 0 0 read-only IRQ109MON IRQ109 Batch Read Register 0x3B8 32 read-only 0x0 0x1 MFSRINT Reception interrupt request of the MFS ch.11 0 0 read-only IRQ110MON IRQ110 Batch Read Register 0x3BC 32 read-only 0x0 0x3 MFSINT1 Status interrupt request of the MFS ch.11 1 1 read-only MFSINT0 Transmission interrupt request of the MFS ch.11 0 0 read-only IRQ111MON IRQ111 Batch Read Register 0x3C0 32 read-only 0x0 0x1F ADCINT4 Range comparison result interrupt request of the A/D converter unit 2 4 4 read-only ADCINT3 Conversion result comparison interrupt request of the A/D converter unit 2 3 3 read-only ADCINT2 FIFO overrun interrupt request of the A/D converter unit 2 2 2 read-only ADCINT1 Scan conversion interrupt request of the A/D converter unit 2 1 1 read-only ADCINT0 Priority conversion interrupt request of the A/D converter unit 2 0 0 read-only IRQ112MON IRQ112 Batch Read Register 0x3C4 32 read-only 0x0 0x3F CANDINT Interrupt request of DSTC transfer end interrupt of CAN-FD 5 5 read-only PCRCDINT Interrupt request of DSTC transfer end interrupt of Programmable CRC 4 4 read-only QSPIDINT1 Interrupt request of DSTC transfer end interrupt of Quad SPI(transmission) 3 3 read-only QSPIDINT0 Interrupt request of DSTC transfer end interrupt of Quad SPI(reception) 2 2 read-only I2SDINT1 Interrupt request of DSTC transfer end interrupt of I2S(transmission) 1 1 read-only I2SDINT0 Interrupt request of DSTC transfer end interrupt of I2S(reception) 0 0 read-only IRQ113MON IRQ113 Batch Read Register 0x3C8 32 read-only 0x0 0x3F RCEC0INT ERROR!!!!!!!!!!!!!!!!!!!! 5 5 read-only USB_DRQ_INT4 ERROR!!!!!!!!!!!!!!!!!!!! 4 4 read-only USB_DRQ_INT3 ERROR!!!!!!!!!!!!!!!!!!!! 3 3 read-only USB_DRQ_INT2 ERROR!!!!!!!!!!!!!!!!!!!! 2 2 read-only USB_DRQ_INT1 ERROR!!!!!!!!!!!!!!!!!!!! 1 1 read-only USB_DRQ_INT0 ERROR!!!!!!!!!!!!!!!!!!!! 0 0 read-only IRQ114MON ERROR!!!!!!!!!!!!!!!!!!!! 0x3CC 32 read-only 0x0 0x7F RCEC1INT ERROR!!!!!!!!!!!!!!!!!!!! 6 6 read-only USB_INT5 ERROR!!!!!!!!!!!!!!!!!!!! 5 5 read-only USB_INT4 ERROR!!!!!!!!!!!!!!!!!!!! 4 4 read-only USB_INT3 ERROR!!!!!!!!!!!!!!!!!!!! 3 3 read-only USB_INT2 ERROR!!!!!!!!!!!!!!!!!!!! 2 2 read-only USB_INT1 ERROR!!!!!!!!!!!!!!!!!!!! 1 1 read-only USB_INT0 ERROR!!!!!!!!!!!!!!!!!!!! 0 0 read-only IRQ115MON ERROR!!!!!!!!!!!!!!!!!!!! 0x3D0 32 read-only 0x0 0x07 QSPIINT2 ERROR!!!!!!!!!!!!!!!!!!!! 2 2 read-only QSPIINT1 ERROR!!!!!!!!!!!!!!!!!!!! 1 1 read-only QSPIINT0 ERROR!!!!!!!!!!!!!!!!!!!! 0 0 read-only IRQ116MON ERROR!!!!!!!!!!!!!!!!!!!! 0x3D4 32 read-only 0x0 0x0 IRQ117MON ERROR!!!!!!!!!!!!!!!!!!!! 0x3D8 32 read-only 0x0 0x3 PRGCRC ERROR!!!!!!!!!!!!!!!!!!!! 1 1 read-only I2SINT ERROR!!!!!!!!!!!!!!!!!!!! 0 0 read-only IRQ118MON ERROR!!!!!!!!!!!!!!!!!!!! 0x3DC 32 read-only 0x0 0x3 SDINT1 ERROR!!!!!!!!!!!!!!!!!!!! 1 1 read-only SDINT0 ERROR!!!!!!!!!!!!!!!!!!!! 0 0 read-only IRQ119MON ERROR!!!!!!!!!!!!!!!!!!!! 0x3E0 32 read-only 0x0 0x1 FLINT ERROR!!!!!!!!!!!!!!!!!!!! 0 0 read-only IRQ120MON ERROR!!!!!!!!!!!!!!!!!!!! 0x3E4 32 read-only 0x0 0x1 MFSRINT ERROR!!!!!!!!!!!!!!!!!!!! 0 0 read-only IRQ121MON ERROR!!!!!!!!!!!!!!!!!!!! 0x3E8 32 read-only 0x0 0x3 MFSINT1 ERROR!!!!!!!!!!!!!!!!!!!! 1 1 read-only MFSINT0 ERROR!!!!!!!!!!!!!!!!!!!! 0 0 read-only IRQ122MON ERROR!!!!!!!!!!!!!!!!!!!! 0x3EC 32 read-only 0x0 0x1 MFSRINT ERROR!!!!!!!!!!!!!!!!!!!! 0 0 read-only IRQ123MON ERROR!!!!!!!!!!!!!!!!!!!! 0x3F0 32 read-only 0x0 0x3 MFSINT1 ERROR!!!!!!!!!!!!!!!!!!!! 1 1 read-only MFSINT0 ERROR!!!!!!!!!!!!!!!!!!!! 0 0 read-only IRQ124MON ERROR!!!!!!!!!!!!!!!!!!!! 0x3F4 32 read-only 0x0 0x1 MFSRINT ERROR!!!!!!!!!!!!!!!!!!!! 0 0 read-only IRQ125MON ERROR!!!!!!!!!!!!!!!!!!!! 0x3F8 32 read-only 0x0 0x3 MFSINT1 ERROR!!!!!!!!!!!!!!!!!!!! 1 1 read-only MFSINT0 ERROR!!!!!!!!!!!!!!!!!!!! 0 0 read-only IRQ126MON ERROR!!!!!!!!!!!!!!!!!!!! 0x3FC 32 read-only 0x0 0x1 MFSRINT ERROR!!!!!!!!!!!!!!!!!!!! 0 0 read-only IRQ127MON ERROR!!!!!!!!!!!!!!!!!!!! 0x400 32 read-only 0x0 0x3 MFSINT1 ERROR!!!!!!!!!!!!!!!!!!!! 1 1 read-only MFSINT0 ERROR!!!!!!!!!!!!!!!!!!!! 0 0 read-only HDMICEC0 HDMI-CEC ch.0 HDMICEC0 0x40034000 0x0 0x1 registers 0x4 0x1 registers 0x8 0x1 registers 0xC 0x1 registers 0x40 0x2 registers 0x44 0x2 registers 0x49 0x1 registers 0x4C 0x2 registers 0x50 0x2 registers 0x54 0x2 registers 0x58 0x2 registers 0x5C 0x2 registers 0x61 0x1 registers 0x64 0x2 registers USB1_HDMICEC0 113 TXCTRL Transmission Control Register 0x0 8 read-write 0x00 0x3D IBREN Bus error detection interrupt enable bit 5 5 read-write ITSTEN transmission status interrupt enable bit 4 4 read-write EOM EOM setting bit 3 3 read-write START START setting bit 2 2 read-write TXEN Transmission operation enable bit 0 0 read-write TXDATA Transmission Data Register 0x4 8 read-write 0x00 0xFF TXDATA Transmission Data 0 7 read-write TXSTS Transmission Status Register 0x8 8 read-write 0x00 0x31 IBR Bus error detection interrupt request bit 5 5 read-write ITST Transmission status interrupt request bit 4 4 read-write ACKSV ACK cycle value bit 0 0 read-write SFREE Signal Free Time Setting Register 0xC 8 read-write 0x00 0x0F SFREE Signal free time setting bits 0 3 read-write RCST Reception Interrupt Control Register 0x40 8 read-write 0x00 0xFF STIE Start bit interrupt enable bit 7 7 read-write ACKIE ACK interrupt enable bit 6 6 read-write OVFIE Counter overflow interrupt enable bit 5 5 read-write OVFSEL Counter overflow detection condition setting bit 4 4 read-write ST Start bit detection bit 3 3 read-write ACK ACK: ACK detection bit 2 2 read-write EOM EOM detection bit 1 1 read-write OVF Counter overflow detection bit 0 0 read-write RCCR Reception Control Register 0x41 8 read-write 0x00 0x8F THSEL Threshold selection bit 7 7 read-write ADRCE Address comparison enable bit 3 3 read-write MOD Operation mode setting bits 1 2 read-write EN Operation enable bit 0 0 read-write RCDAHW "H" Width Setting Register A 0x44 8 read-write 0x00 0xFF RCDAHW "H" Width Setting A 0 7 read-write RCSHW Start Bit "H" Width Setting Register 0x45 8 read-write 0x00 0xFF RCSHW Start Bit "H" Width Setting 0 7 read-write RCDBHW "H" Width Setting Register B 0x49 8 read-write 0x00 0xFF RCDBHW "H" Width Setting B 0 7 read-write RCADR2 Device Address Setting Register 2 0x4C 8 read-write 0x00 0x1F RCADR2 Device Address 2 0 4 read-write RCADR1 Device Address Setting Register 1 0x4D 8 read-write 0x00 0x1F RCADR1 Device Address 1 0 4 read-write RCDTHL Data Save Register (High-Low) 0x50 8 read-only 0x00 0xFF RCDTHL RCDTHL 0 7 read-only RCDTHH Data Save Register (High-High) 0x51 8 read-only 0x00 0xFF RCDTHH RCDTHH 0 7 read-only RCDTLL Data Save Register (Low-Low) 0x54 8 read-only 0x00 0xFF RCDTLL RCDTLL 0 7 read-only RCDTLH Data Save Register (Low-High) 0x55 8 read-only 0x00 0xFF RCDTLH RCDTLH 0 7 read-only RCCKD Clock Division Setting Register 0x58 16 read-write 0x0000 0x1FFF CKSEL Operating clock selection bit 12 12 read-write CKDIV Operating clock division setting bits 0 11 read-write RCRHW Repeat Code "H" Width Setting Register 0x5C 8 read-write 0x00 0xFF RCRHW "Repeat code "H" width setting bits" 0 7 read-write RCRC Repeat Code Interrupt Control Register 0x5D 8 read-write 0x00 0x11 RCIE Repeat Code Interrupt enable bit 4 4 read-write RC Repeat code detection flag bit 0 0 read-write RCLE Data Bit Width Violation Control Register 0x61 8 read-write 0x00 0xFB LELIE Maximum data bit width violation interrupt enable bit 7 7 read-write LESIE Minimum data bit width violation interrupt enable bit 6 6 read-write LELE Maximum data bit width violation detection enable bit 5 5 read-write LESE Minimum data bit width violation detection enable bit 4 4 read-write EPE Error pulse output enable bit 3 3 read-write LEL Maximum data bit width violation detection flag bit 1 1 read-write LES Minimum data bit width violation detection flag bit 0 0 read-write RCLESW Minimum Data Bit Width Setting Register 0x64 8 read-write 0x00 0xFF RCLESW Minimum data bit width setting bits 0 7 read-write RCLELW Maximum Data Bit Width Setting Register 0x65 8 read-write 0x00 0xFF RCLELW Maximum data bit width setting bits 0 7 read-write HDMICEC1 0x40034100 USB1_HOST_HDMICEC1 114 GPIO 0 GPIO 0x4006F000 0x0 0x780 registers PFR0 Port Function Setting Register 0 0x0 32 read-write 0x0000001F 0x000071F P0A Bit10 of PFR0 10 10 read-write P09 Bit9 of PFR0 9 9 read-write P08 Bit8 of PFR0 8 8 read-write P04 Bit4 of PFR0 4 4 read-write P03 Bit3 of PFR0 3 3 read-write P02 Bit2 of PFR0 2 2 read-write P01 Bit1 of PFR0 1 1 read-write P00 Bit0 of PFR0 0 0 read-write PFR1 Port Function Setting Register 1 0x4 32 read-write 0x0 0x0000FFFF P1F Bit15 of PFR1 15 15 read-write P1E Bit14 of PFR1 14 14 read-write P1D Bit13 of PFR1 13 13 read-write P1C Bit12 of PFR1 12 12 read-write P1B Bit11 of PFR1 11 11 read-write P1A Bit10 of PFR1 10 10 read-write P19 Bit9 of PFR1 9 9 read-write P18 Bit8 of PFR1 8 8 read-write P17 Bit7 of PFR1 7 7 read-write P16 Bit6 of PFR1 6 6 read-write P15 Bit5 of PFR1 5 5 read-write P14 Bit4 of PFR1 4 4 read-write P13 Bit3 of PFR1 3 3 read-write P12 Bit2 of PFR1 2 2 read-write P11 Bit1 of PFR1 1 1 read-write P10 Bit0 of PFR1 0 0 read-write PFR2 Port Function Setting Register 2 0x8 32 read-write 0x0 0x000007FF P2A Bit10 of PFR2 10 10 read-write P29 Bit9 of PFR2 9 9 read-write P28 Bit8 of PFR2 8 8 read-write P27 Bit7 of PFR2 7 7 read-write P26 Bit6 of PFR2 6 6 read-write P25 Bit5 of PFR2 5 5 read-write P24 Bit4 of PFR2 4 4 read-write P23 Bit3 of PFR2 3 3 read-write P22 Bit2 of PFR2 2 2 read-write P21 Bit1 of PFR2 1 1 read-write P20 Bit0 of PFR2 0 0 read-write PFR3 Port Function Setting Register 3 0xC 32 read-write 0x0 0x00007FFF P3E Bit14 of PFR3 14 14 read-write P3D Bit13 of PFR3 13 13 read-write P3C Bit12 of PFR3 12 12 read-write P3B Bit11 of PFR3 11 11 read-write P3A Bit10 of PFR3 10 10 read-write P39 Bit9 of PFR3 9 9 read-write P38 Bit8 of PFR3 8 8 read-write P37 Bit7 of PFR3 7 7 read-write P36 Bit6 of PFR3 6 6 read-write P35 Bit5 of PFR3 5 5 read-write P34 Bit4 of PFR3 4 4 read-write P33 Bit3 of PFR3 3 3 read-write P32 Bit2 of PFR3 2 2 read-write P31 Bit1 of PFR3 1 1 read-write P30 Bit0 of PFR3 0 0 read-write PFR4 Port Function Setting Register 4 0x10 32 read-write 0x0 0x00007FFF P4E Bit14 of PFR4 14 14 read-write P4D Bit13 of PFR4 13 13 read-write P4C Bit12 of PFR4 12 12 read-write P4B Bit11 of PFR4 11 11 read-write P4A Bit10 of PFR4 10 10 read-write P49 Bit9 of PFR4 9 9 read-write P48 Bit8 of PFR4 8 8 read-write P47 Bit7 of PFR4 7 7 read-write P46 Bit6 of PFR4 6 6 read-write P45 Bit5 of PFR4 5 5 read-write P44 Bit4 of PFR4 4 4 read-write P43 Bit3 of PFR4 3 3 read-write P42 Bit2 of PFR4 2 2 read-write P41 Bit1 of PFR4 1 1 read-write P40 Bit0 of PFR4 0 0 read-write PFR5 Port Function Setting Register 5 0x14 32 read-write 0x0 0x0000FFFF P5F Bit15 of PFR5 15 15 read-write P5E Bit14 of PFR5 14 14 read-write P5D Bit13 of PFR5 13 13 read-write P5C Bit12 of PFR5 12 12 read-write P5B Bit11 of PFR5 11 11 read-write P5A Bit10 of PFR5 10 10 read-write P59 Bit9 of PFR5 9 9 read-write P58 Bit8 of PFR5 8 8 read-write P57 Bit7 of PFR5 7 7 read-write P56 Bit6 of PFR5 6 6 read-write P55 Bit5 of PFR5 5 5 read-write P54 Bit4 of PFR5 4 4 read-write P53 Bit3 of PFR5 3 3 read-write P52 Bit2 of PFR5 2 2 read-write P51 Bit1 of PFR5 1 1 read-write P50 Bit0 of PFR5 0 0 read-write PFR6 Port Function Setting Register 6 0x18 32 read-write 0x0 0x00007FFF P6E Bit14 of PFR6 14 14 read-write P6D Bit13 of PFR6 13 13 read-write P6C Bit12 of PFR6 12 12 read-write P6B Bit11 of PFR6 11 11 read-write P6A Bit10 of PFR6 10 10 read-write P69 Bit9 of PFR6 9 9 read-write P68 Bit8 of PFR6 8 8 read-write P67 Bit7 of PFR6 7 7 read-write P66 Bit6 of PFR6 6 6 read-write P65 Bit5 of PFR6 5 5 read-write P64 Bit4 of PFR6 4 4 read-write P63 Bit3 of PFR6 3 3 read-write P62 Bit2 of PFR6 2 2 read-write P61 Bit1 of PFR6 1 1 read-write P60 Bit0 of PFR6 0 0 read-write PFR7 Port Function Setting Register 7 0x1C 32 read-write 0x0 0x00007FFF P7E Bit14 of PFR7 14 14 read-write P7D Bit13 of PFR7 13 13 read-write P7C Bit12 of PFR7 12 12 read-write P7B Bit11 of PFR7 11 11 read-write P7A Bit10 of PFR7 10 10 read-write P79 Bit9 of PFR7 9 9 read-write P78 Bit8 of PFR7 8 8 read-write P77 Bit7 of PFR7 7 7 read-write P76 Bit6 of PFR7 6 6 read-write P75 Bit5 of PFR7 5 5 read-write P74 Bit4 of PFR7 4 4 read-write P73 Bit3 of PFR7 3 3 read-write P72 Bit2 of PFR7 2 2 read-write P71 Bit1 of PFR7 1 1 read-write P70 Bit0 of PFR7 0 0 read-write PFR8 Port Function Setting Register 8 0x20 32 read-write 0x0 0x0000000F P83 Bit3 of PFR8 3 3 read-write P82 Bit2 of PFR8 2 2 read-write P81 Bit1 of PFR8 1 1 read-write P80 Bit0 of PFR8 0 0 read-write PFR9 32 0x24 32 read-write 0x0 0x000000FF P97 Bit7 of PFR9 7 7 read-write P96 Bit6 of PFR9 6 6 read-write P95 Bit5 of PFR9 5 5 read-write P94 Bit4 of PFR9 4 4 read-write P93 Bit3 of PFR9 3 3 read-write P92 Bit2 of PFR9 2 2 read-write P91 Bit1 of PFR9 1 1 read-write P90 Bit0 of PFR9 0 0 read-write PFRA 32 0x28 32 read-write 0x0 0x0000FFFF PAF Bit15 of PFRA 15 15 read-write PAE Bit14 of PFRA 14 14 read-write PAD Bit13 of PFRA 13 13 read-write PAC Bit12 of PFRA 12 12 read-write PAB Bit11 of PFRA 11 11 read-write PAA Bit10 of PFRA 10 10 read-write PA9 Bit9 of PFRA 9 9 read-write PA8 Bit8 of PFRA 8 8 read-write PA7 Bit7 of PFRA 7 7 read-write PA6 Bit6 of PFRA 6 6 read-write PA5 Bit5 of PFRA 5 5 read-write PA4 Bit4 of PFRA 4 4 read-write PA3 Bit3 of PFRA 3 3 read-write PA2 Bit2 of PFRA 2 2 read-write PA1 Bit1 of PFRA 1 1 read-write PA0 Bit0 of PFRA 0 0 read-write PFRB 32 0x2C 32 read-write 0x0 0x0000FFFF PBF Bit15 of PFRB 15 15 read-write PBE Bit14 of PFRB 14 14 read-write PBD Bit13 of PFRB 13 13 read-write PBC Bit12 of PFRB 12 12 read-write PBB Bit11 of PFRB 11 11 read-write PBA Bit10 of PFRB 10 10 read-write PB9 Bit9 of PFRB 9 9 read-write PB8 Bit8 of PFRB 8 8 read-write PB7 Bit7 of PFRB 7 7 read-write PB6 Bit6 of PFRB 6 6 read-write PB5 Bit5 of PFRB 5 5 read-write PB4 Bit4 of PFRB 4 4 read-write PB3 Bit3 of PFRB 3 3 read-write PB2 Bit2 of PFRB 2 2 read-write PB1 Bit1 of PFRB 1 1 read-write PB0 Bit0 of PFRB 0 0 read-write PFRC 32 0x30 32 read-write 0x0 0x0000FFFF PCF Bit15 of PFRC 15 15 read-write PCE Bit14 of PFRC 14 14 read-write PCD Bit13 of PFRC 13 13 read-write PCC Bit12 of PFRC 12 12 read-write PCB Bit11 of PFRC 11 11 read-write PCA Bit10 of PFRC 10 10 read-write PC9 Bit9 of PFRC 9 9 read-write PC8 Bit8 of PFRC 8 8 read-write PC7 Bit7 of PFRC 7 7 read-write PC6 Bit6 of PFRC 6 6 read-write PC5 Bit5 of PFRC 5 5 read-write PC4 Bit4 of PFRC 4 4 read-write PC3 Bit3 of PFRC 3 3 read-write PC2 Bit2 of PFRC 2 2 read-write PC1 Bit1 of PFRC 1 1 read-write PC0 Bit0 of PFRC 0 0 read-write PFRD 32 0x34 32 read-write 0x0 0x00000007 PD2 Bit2 of PFRD 2 2 read-write PD1 Bit1 of PFRD 1 1 read-write PD0 Bit0 of PFRD 0 0 read-write PFRE Port Function Setting Register E 0x38 32 read-write 0x0 0x0000000B PE3 Bit3 of PFRE 3 3 read-write PE2 Bit2 of PFRE 2 2 read-write PE0 Bit0 of PFRE 0 0 read-write PFRF 32 0x3C 32 read-write 0x0 0x00001FFF PFC Bit12 of PFRF 12 12 read-write PFB Bit11 of PFRF 11 11 read-write PFA Bit10 of PFRF 10 10 read-write PF9 Bit9 of PFRF 9 9 read-write PF8 Bit8 of PFRF 8 8 read-write PF7 Bit7 of PFRF 7 7 read-write PF6 Bit6 of PFRF 6 6 read-write PF5 Bit5 of PFRF 5 5 read-write PF4 Bit4 of PFRF 4 4 read-write PF3 Bit3 of PFRF 3 3 read-write PF2 Bit2 of PFRF 2 2 read-write PF1 Bit1 of PFRF 1 1 read-write PF0 Bit0 of PFRF 0 0 read-write PCR0 Pull-up Setting Register 0 0x100 PCR1 Pull-up Setting Register 1 0x104 PCR2 Pull-up Setting Register 2 0x108 PCR3 Pull-up Setting Register 3 0x10C PCR4 Pull-up Setting Register 4 0x110 PCR5 Pull-up Setting Register 5 0x114 PCR6 Pull-up Setting Register 6 0x118 PCR7 Pull-up Setting Register 7 0x11C PCR8 Pull-up Setting Register 8 0x120 PCR9 Pull-up Setting Register 9 0x124 PCRA Pull-up Setting Register A 0x128 PCRB Pull-up Setting Register B 0x12C PCRC Pull-up Setting Register C 0x130 PCRD Pull-up Setting Register D 0x134 PCRE Pull-up Setting Register E 0x138 PCRF Pull-up Setting Register F 0x13C DDR0 Port input/output Direction Setting Register 0 0x200 32 read-write 0x0 0x00007FFF P0E Bit14 of DDR0 14 14 read-write P0D Bit13 of DDR0 13 13 read-write P0C Bit12 of DDR0 12 12 read-write P0B Bit11 of DDR0 11 11 read-write P0A Bit10 of DDR0 10 10 read-write P09 Bit9 of DDR0 9 9 read-write P08 Bit8 of DDR0 8 8 read-write P07 Bit7 of DDR0 7 7 read-write P06 Bit6 of DDR0 6 6 read-write P05 Bit5 of DDR0 5 5 read-write P04 Bit4 of DDR0 4 4 read-write P03 Bit3 of DDR0 3 3 read-write P02 Bit2 of DDR0 2 2 read-write P01 Bit1 of DDR0 1 1 read-write P00 Bit0 of DDR0 0 0 read-write DDR1 Port input/output Direction Setting Register 1 0x204 DDR2 Port input/output Direction Setting Register 2 0x208 DDR3 Port input/output Direction Setting Register 3 0x20C DDR4 Port input/output Direction Setting Register 4 0x210 DDR5 Port input/output Direction Setting Register 5 0x214 DDR6 Port input/output Direction Setting Register 6 0x218 DDR7 Port input/output Direction Setting Register 7 0x21C DDR8 Port input/output Direction Setting Register 8 0x220 DDR9 Port input/output Direction Setting Register 9 0x224 DDRA Port input/output Direction Setting Register A 0x228 DDRB Port input/output Direction Setting Register B 0x22C DDRC Port input/output Direction Setting Register C 0x230 DDRD Port input/output Direction Setting Register D 0x234 DDRE Port input/output Direction Setting Register E 0x238 DDRF Port input/output Direction Setting Register F 0x23C PDIR0 Port Input Data Register 0 0x300 PDIR1 Port Input Data Register 1 0x304 PDIR2 Port Input Data Register 2 0x308 PDIR3 Port Input Data Register 3 0x30C PDIR4 Port Input Data Register 4 0x310 PDIR5 Port Input Data Register 5 0x314 PDIR6 Port Input Data Register 6 0x318 PDIR7 Port Input Data Register 7 0x31C PDIR8 Port Input Data Register 8 0x320 PDIR9 Port Input Data Register 9 0x324 PDIRA Port Input Data Register A 0x328 PDIRB Port Input Data Register B 0x32C PDIRC Port Input Data Register C 0x330 PDIRD Port Input Data Register D 0x334 PDIRE Port Input Data Register E 0x338 PDIRF Port Input Data Register F 0x33C PDOR0 Port Output Data Register 0 0x400 PDOR1 Port Output Data Register 1 0x404 PDOR2 Port Output Data Register 2 0x408 PDOR3 Port Output Data Register 3 0x40C PDOR4 Port Output Data Register 4 0x410 PDOR5 Port Output Data Register 5 0x414 PDOR6 Port Output Data Register 6 0x418 PDOR7 Port Output Data Register 7 0x41C PDOR8 Port Output Data Register 8 0x420 PDOR9 Port Output Data Register 9 0x424 PDORA Port Output Data Register A 0x428 PDORB Port Output Data Register B 0x42C PDORC Port Output Data Register C 0x430 PDORD Port Output Data Register D 0x434 PDORE Port Output Data Register E 0x438 PDORF Port Output Data Register F 0x43C ADE Analog Input Setting Register 0x500 32 read-write 0xFFFFFFFF 0xFFFFFFFF AN31 Bit31 of ADE 31 31 read-write AN30 Bit30 of ADE 30 30 read-write AN29 Bit29 of ADE 29 29 read-write AN28 Bit28 of ADE 28 28 read-write AN27 Bit27 of ADE 27 27 read-write AN26 Bit26 of ADE 26 26 read-write AN25 Bit25 of ADE 25 25 read-write AN24 Bit24 of ADE 24 24 read-write AN23 Bit23 of ADE 23 23 read-write AN22 Bit22 of ADE 22 22 read-write AN21 Bit21 of ADE 21 21 read-write AN20 Bit20 of ADE 20 20 read-write AN19 Bit19 of ADE 19 19 read-write AN18 Bit18 of ADE 18 18 read-write AN17 Bit17 of ADE 17 17 read-write AN16 Bit16 of ADE 16 16 read-write AN15 Bit15 of ADE 15 15 read-write AN14 Bit14 of ADE 14 14 read-write AN13 Bit13 of ADE 13 13 read-write AN12 Bit12 of ADE 12 12 read-write AN11 Bit11 of ADE 11 11 read-write AN10 Bit10 of ADE 10 10 read-write AN09 Bit9 of ADE 9 9 read-write AN08 Bit8 of ADE 8 8 read-write AN07 Bit7 of ADE 7 7 read-write AN06 Bit6 of ADE 6 6 read-write AN05 Bit5 of ADE 5 5 read-write AN04 Bit4 of ADE 4 4 read-write AN03 Bit3 of ADE 3 3 read-write AN02 Bit2 of ADE 2 2 read-write AN01 Bit1 of ADE 1 1 read-write AN00 Bit0 of ADE 0 0 read-write SPSR Special Port Setting Register 0x580 32 read-write 0x00000004 0x0000003C USB1C USB (ch.1) Pin Setting bit 5 5 read-write USB0C USB (ch.0) Pin Setting bit 4 4 read-write MAINXC Main Clock (Oscillation) Pin Setting bits 2 3 read-write EPFR00 Extended Pin Function Setting Register 00 0x600 32 read-write 0x00030000 0x0F0322F7 TRC3E TRACED Function Select bit 3 27 27 read-write TRC2E TRACED Function Select bit 2 26 26 read-write TRC1E TRACED Function Select bit 1 25 25 read-write TRC0E TRACED Function Select bit 0 24 24 read-write JTAGEN1S JTAG Function Select bit 1 17 17 read-write JTAGEN0B JTAG Function Select bit 0 16 16 read-write USBP1E USB ch.1 Function Select bit 1 13 13 read-write USBP0E USB ch.0 Function Select bit 1 9 9 read-write SUBOUTE Sub clock divide output function select bit 6 7 read-write RTCCOE RTC clock output select bit 4 5 read-write CROUTE Internal high-speed CR Oscillation Output Function Select bit 1 2 read-write NMIS NMIX Function Select bit 0 0 read-write EPFR01 Extended Pin Function Setting Register 01 0x604 32 read-write 0x0 0xFFFF1FFF IC03S IC03 Input Select bits 29 31 read-write IC02S IC02 Input Select bits 26 28 read-write IC01S IC01 Input Select bits 23 25 read-write IC00S IC00 Input Select bits 20 22 read-write FRCK0S FRCK0 Input Select bits 18 19 read-write DTTI0S DTTIX0 Input Select bits 16 17 read-write DTTI0C DTTIX0 Function Select bit 12 12 read-write RTO05E RTO05 Output Select bits 10 11 read-write RTO04E RTO04 Output Select bits 8 9 read-write RTO03E RTO03 Output Select bits 6 7 read-write RTO02E RTO02 Output Select bits 4 5 read-write RTO01E RTO01 Output Select bits 2 3 read-write RTO00E RTO00 Output Select bits 0 1 read-write EPFR02 Extended Pin Function Setting Register 02 0x608 32 read-write 0x0 0xFFFF1FFF IC13S IC13 Input Select bits 29 31 read-write IC12S IC13 Input Select bits 26 28 read-write IC11S IC13 Input Select bits 23 25 read-write IC10S IC13 Input Select bits 20 22 read-write FRCK1S FRCK1 Input Select bits 18 19 read-write DTTI1S DTTIX1 Input Select bits 16 17 read-write DTTI1C DTTIX1 Function Select bit 12 12 read-write RTO15E RTO15 Output Select bits 10 11 read-write RTO14E RTO14 Output Select bits 8 9 read-write RTO13E RTO13 Output Select bits 6 7 read-write RTO12E RTO12 Output Select bits 4 5 read-write RTO11E RTO11 Output Select bits 2 3 read-write RTO10E RTO10 Output Select bits 0 1 read-write EPFR03 Extended Pin Function Setting Register 03 0x60C 32 read-write 0x0 0xFFFF1FFF IC23S IC23 Input Select bits 29 31 read-write IC22S IC23 Input Select bits 26 28 read-write IC21S IC23 Input Select bits 23 25 read-write IC20S IC23 Input Select bits 20 22 read-write FRCK2S FRCK2 Input Select bits 18 19 read-write DTTI2S DTTIX2 Input Select bits 16 17 read-write DTTI2C DTTIX2 Function Select bit 12 12 read-write RTO25E RTO25 Output Select bits 10 11 read-write RTO24E RTO24 Output Select bits 8 9 read-write RTO23E RTO23 Output Select bits 6 7 read-write RTO22E RTO22 Output Select bits 4 5 read-write RTO21E RTO21 Output Select bits 2 3 read-write RTO20E RTO20 Output Select bits 0 1 read-write EPFR04 Extended Pin Function Setting Register 04 0x610 32 read-write 0x0 0x3F3C3F7C TIOB3S TIOB3 Input Select bits 28 29 read-write TIOA3E TIOA3 Output Select bits 26 27 read-write TIOA3S TIOA3 Input Select bits 24 25 read-write TIOB2S TIOB2 Input Select bits 20 21 read-write TIOA2E TIOA2 Output Select bits 18 19 read-write TIOB1S TIOB1 Input Select bits 12 13 read-write TIOA1E TIOA1 Output Select bits 10 11 read-write TIOA1S TIOA1 Input Select bits 8 9 read-write TIOB0S TIOB0 Input Select bits 4 6 read-write TIOA0E TIOA0 Output Select bits 2 3 read-write EPFR05 Extended Pin Function Setting Register 05 0x614 32 read-write 0x0 0x3F3C3F3C TIOB7S TIOB7 Input Select bits 28 29 read-write TIOA7E TIOA7 Output Select bits 26 27 read-write TIOA7S TIOA7 Input Select bits 24 25 read-write TIOB6S TIOB6 Input Select bits 20 21 read-write TIOA6E TIOA6 Output Select bits 18 19 read-write TIOB5S TIOB5 Input Select bits 12 13 read-write TIOA5E TIOA5 Output Select bits 10 11 read-write TIOA5S TIOA5 Input Select bits 8 9 read-write TIOB4S TIOB4 Input Select bits 4 5 read-write TIOA4E TIOA4 Output Select bits 2 3 read-write EPFR06 Extended Pin Function Setting Register 06 0x618 32 read-write 0x0 0xFFFFFFFF EINT15S External Interrupt 15 Input Select bits 30 31 read-write EINT14S External Interrupt 14 Input Select bits 28 29 read-write EINT13S External Interrupt 13 Input Select bits 26 27 read-write EINT12S External Interrupt 12 Input Select bits 24 25 read-write EINT11S External Interrupt 11 Input Select bits 22 23 read-write EINT10S External Interrupt 10 Input Select bits 20 21 read-write EINT09S External Interrupt 09 Input Select bits 18 19 read-write EINT08S External Interrupt 08 Input Select bits 16 17 read-write EINT07S External Interrupt 07 Input Select bits 14 15 read-write EINT06S External Interrupt 06 Input Select bits 12 13 read-write EINT05S External Interrupt 05 Input Select bits 10 11 read-write EINT04S External Interrupt 04 Input Select bits 8 9 read-write EINT03S External Interrupt 03 Input Select bits 6 7 read-write EINT02S External Interrupt 02 Input Select bits 4 5 read-write EINT01S External Interrupt 01 Input Select bits 2 3 read-write EINT00S External Interrupt 00 Input Select bits 0 1 read-write EPFR07 Extended Pin Function Setting Register 07 0x61C 32 read-write 0x0 0x0FFFFFF0 SCK3B SCK3 Input/Output Select bits 26 27 read-write SOT3B SOT3 Input/Output Select bits 24 25 read-write SIN3S SIN3 Input Select bits 22 23 read-write SCK2B SCK2 Input/Output Select bits 20 21 read-write SOT2B SOT2 Input/Output Select bits 18 19 read-write SIN2S SIN2 Input Select bits 16 17 read-write SCK1B SCK1 Input/Output Select bits 14 15 read-write SOT1B SOT1 Input/Output Select bits 12 13 read-write SIN1S SIN1 Input Select bits 10 11 read-write SCK0B SCK0 Input/Output Select bits 8 9 read-write SOT0B SOT0 Input/Output Select bits 6 7 read-write SIN0S SIN0 Input Select bits 4 5 read-write EPFR08 Extended Pin Function Setting Register 08 0x620 32 read-write 0x0 0xFFFFFFFF CTS5S CTS5 Input/Output Select bits 30 31 read-write RTS5E RTS5 Input/Output Select bits 28 29 read-write SCK7B SCK7 Input/Output Select bits 26 27 read-write SOT7B SOT7 Input/Output Select bits 24 25 read-write SIN7S SIN7 Input Select bits 22 23 read-write SCK6B SCK6 Input/Output Select bits 20 21 read-write SOT6B SOT6 Input/Output Select bits 18 19 read-write SIN6S SIN6 Input Select bits 16 17 read-write SCK5B SCK5 Input/Output Select bits 14 15 read-write SOT5B SOT5 Input/Output Select bits 12 13 read-write SIN5S SIN5 Input Select bits 10 11 read-write SCK4B SCK4 Input/Output Select bits 8 9 read-write SOT4B SOT4 Input/Output Select bits 6 7 read-write SIN4S SIN4 Input Select bits 4 5 read-write CTS4S CTS4 Input/Output Select bits 2 3 read-write RTS4E RTS4 Input/Output Select bits 0 1 read-write EPFR09 Extended Pin Function Setting Register 09 0x624 32 read-write 0x0 0xFFFFFFFF CTX1E CTX1E Output Select bits 30 31 read-write CRX1S CRX1S Input Select bits 28 29 read-write CTX0E CTX0E Output Select bits 26 27 read-write CRX0S CRX0S Input Select bits 24 25 read-write ADTRG2S ADTRG2 Input Select bits 20 23 read-write ADTRG1S ADTRG1 Input Select bits 16 19 read-write ADTRG0S ADTRG0 Input Select bits 12 15 read-write QZIN1S QZIN1S Input Select bits 10 11 read-write QBIN1S QBIN1S Input Select bits 8 9 read-write QAIN1S QAIN1S Input Select bits 6 7 read-write QZIN0S QZIN0S Input Select bits 4 5 read-write QBIN0S QBIN0S Input Select bits 2 3 read-write QAIN0S QAIN0S Input Select bits$ 0 1 read-write EPFR10 Extended Pin Function Setting Register 10 0x628 32 read-write 0x0 0xFFFFFFFF UEA24E UEA24E Output Select bit 31 31 read-write UEA23E UEA23E Output Select bit 30 30 read-write UEA22E UEA22E Output Select bit 29 29 read-write UEA21E UEA21E Output Select bit 28 28 read-write UEA20E UEA20E Output Select bit 27 27 read-write UEA19E UEA19E Output Select bit 26 26 read-write UEA18E UEA18E Output Select bit 25 25 read-write UEA17E UEA17E Output Select bit 24 24 read-write UEA16E UEA16E Output Select bit 23 23 read-write UEA15E UEA15E Output Select bit 22 22 read-write UEA14E UEA14E Output Select bit 21 21 read-write UEA13E UEA13E Output Select bit 20 20 read-write UEA12E UEA12E Output Select bit 19 19 read-write UEA11E UEA11E Output Select bit 18 18 read-write UEA10E UEA10E Output Select bit 17 17 read-write UEA09E UEA09E Output Select bit 16 16 read-write UEA08E UEA08E Output Select bit 15 15 read-write UEAOOE UEAOOE Output Select bit 14 14 read-write UECS7E UECS7E Output Select bit 13 13 read-write UECS6E UECS6E Output Select bit 12 12 read-write UECS5E UECS5E Output Select bit 11 11 read-write UECS4E UECS4E Output Select bit 10 10 read-write UECS3E UECS3E Output Select bit 9 9 read-write UECS2E UECS2E Output Select bit 8 8 read-write UECS1E UECS1E Output Select bit 7 7 read-write UEFLSE UEFLSE Output Select bit 6 6 read-write UEOEXE UEOEXE Output Select bit 5 5 read-write UEDQME UEDQME Output Select bit 4 4 read-write UEWEXE UEWEXE Output Select bit 3 3 read-write UECLKE UECLKE Output Select bit 2 2 read-write UEDTHB UEDTHB Input/Output Select bit 1 1 read-write UEDEFB UEDEFB Input/Output Select bit 0 0 read-write EPFR11 Extended Pin Function Setting Register 11 0x62C 32 read-write 0x0 0x03FFFFFF UERLC UERLC relocation select bit 25 25 read-write UED15B UED15B Input/Output Select bit 24 24 read-write UED14B UED14B Input/Output Select bit 23 23 read-write UED13B UED13B Input/Output Select bit 22 22 read-write UED12B UED12B Input/Output Select bit 21 21 read-write UED11B UED11B Input/Output Select bit 20 20 read-write UED10B UED10B Input/Output Select bit 19 19 read-write UED09B UED09B Input/Output Select bit 18 18 read-write UED08B UED08B Input/Output Select bit 17 17 read-write UED07B UED07B Input/Output Select bit 16 16 read-write UED06B UED06B Input/Output Select bit 15 15 read-write UED05B UED05B Input/Output Select bit 14 14 read-write UED04B UED04B Input/Output Select bit 13 13 read-write UED03B UED03B Input/Output Select bit 12 12 read-write UED02B UED02B Input/Output Select bit 11 11 read-write UED01B UED01B Input/Output Select bit 10 10 read-write UED00B UED00B Input/Output Select bit 9 9 read-write UEA07E UEA07E Output Select bit 8 8 read-write UEA06E UEA06E Output Select bit 7 7 read-write UEA05E UEA05E Output Select bit 6 6 read-write UEA04E UEA04E Output Select bit 5 5 read-write UEA03E UEA03E Output Select bit 4 4 read-write UEA02E UEA02E Output Select bit 3 3 read-write UEA01E UEA01E Output Select bit 2 2 read-write UECS0E UEA00E Output Select bit 1 1 read-write UEALEE UEALEE Output Select bit 0 0 read-write EPFR12 Extended Pin Function Setting Register 12 0x630 32 read-write 0x0 0x3F3C3F3C TIOB11S TIOB11 Input Select bits 28 29 read-write TIOA11E TIOA11 Output Select bits 26 27 read-write TIOA11S TIOA11 Input Select bits 24 25 read-write TIOB10S TIOB10 Input Select bits 20 21 read-write TIOA10E TIOA10 Output Select bits 18 19 read-write TIOB9S TIOB9 Input Select bits 12 13 read-write TIOA9E TIOA9 Output Select bits 10 11 read-write TIOA9S TIOA9 Input Select bits 8 9 read-write TIOB8S TIOB8 Input Select bits 4 5 read-write TIOA8E TIOA8 Output Select bits 2 3 read-write EPFR13 Extended Pin Function Setting Register 13 0x634 32 read-write 0x0 0x3F3C3F3C TIOB15S TIOB15 Input Select bits 28 29 read-write TIOA15E TIOA15 Output Select bits 26 27 read-write TIOA15S TIOA15 Input Select bits 24 25 read-write TIOB14S TIOB14 Input Select bits 20 21 read-write TIOA14E TIOA14 Output Select bits 18 19 read-write TIOB13S TIOB13 Input Select bits 12 13 read-write TIOA13E TIOA13 Output Select bits 10 11 read-write TIOA13S TIOA13 Input Select bits 8 9 read-write TIOB12S TIOB12 Input Select bits 4 5 read-write TIOA12E TIOA12 Output Select bits 2 3 read-write EPFR14 Extended Pin Function Setting Register 14 0x638 32 read-write 0x0 0x3FFC003F E_SPLC Input cutoff Select bit in Standby of input Pin for Ethernet-MAC 28 29 read-write E_PSE PPS0_PPS1 Output Select bit for Ethernet-MAC 27 27 read-write E_CKE E_COUT Output Select bit 26 26 read-write E_MD1B E_MDO1 I/O Select bit 25 25 read-write E_MD0B E_MDO0 I/O Select bit 24 24 read-write E_MC1B E_MDC1 I/O Select bit 23 23 read-write E_MC0E E_MDC0 Output Select bit 22 22 read-write E_TE1E E_TXER0_TXEN1 Output Select bit 21 21 read-write E_TE0E E_TXEN0 Output Select bit 20 20 read-write E_TD1E E_TX02_TX10, E_TX03_TX11 Output Select bit 19 19 read-write E_TD0E E_TX00, E_TX01 Output Select bit 18 18 read-write QZIN2S QDU-ch.2 ZIN Input Pin bits 4 5 read-write QBIN2S QDU-ch.2 BIN Input Pin bits 2 3 read-write QAIN2S QDU-ch.2 AIN Input Pin bits 0 1 read-write EPFR15 Extended Pin Function Setting Register 15 0x63C 32 read-write 0x0 0xFFFFFFFF EINT31S External Interrupt 31 Input Select bits 30 31 read-write EINT30S External Interrupt 30 Input Select bits 28 29 read-write EINT29S External Interrupt 29 Input Select bits 26 27 read-write EINT28S External Interrupt 28 Input Select bits 24 25 read-write EINT27S External Interrupt 27 Input Select bits 22 23 read-write EINT26S External Interrupt 26 Input Select bits 20 21 read-write EINT25S External Interrupt 25 Input Select bits 18 19 read-write EINT24S External Interrupt 24 Input Select bits 16 17 read-write EINT23S External Interrupt 23 Input Select bits 14 15 read-write EINT22S External Interrupt 22 Input Select bits 12 13 read-write EINT21S External Interrupt 21 Input Select bits 10 11 read-write EINT20S External Interrupt 20 Input Select bits 8 9 read-write EINT19S External Interrupt 19 Input Select bits 6 7 read-write EINT18S External Interrupt 18 Input Select bits 4 5 read-write EINT17S External Interrupt 17 Input Select bits 2 3 read-write EINT16S External Interrupt 16 Input Select bits 0 1 read-write EPFR16 Extended Pin Function Setting Register 16 0x640 32 read-write 0x00000000 0x3FFFFFFF SFMPBC MFS ch.B I2C FastMode+ Select bit 29 29 read-write SFMPAC MFS ch.A I2C FastMode+ Select bit 28 28 read-write SCK11B SCK11 Input/Output Select bits 26 27 read-write SOT11B SOT11 Input/Output Select bits 24 25 read-write SIN11S SIN11 Input Select bits 22 23 read-write SCK10B SCK10 Input/Output Select bits 20 21 read-write SOT10B SOT10 Input/Output Select bits 18 19 read-write SIN10S SIN10 Input Select bits 16 17 read-write SCK9B SCK9 Input/Output Select bits 14 15 read-write SOT9B SOT9 Input/Output Select bits 12 13 read-write SIN9S SIN9 Input Select bits 10 11 read-write SCK8B SCK8 Input/Output Select bits 8 9 read-write SOT8B SOT8 Input/Output Select bits 6 7 read-write SIN8S SIN8 Input Select bits 4 5 read-write SCS7B SCS7 Input/Output Select bits 2 3 read-write SCS6B SCS6 Select bits 0 1 read-write EPFR17 Extended Pin Function Setting Register 17 0x644 32 read-write 0x00000000 0x0FFFFFF0 SCK15B SCK15 Input/Output Select bits 26 27 read-write SOT15B SOT15 Input/Output Select bits 24 25 read-write SIN15S SIN15 Input Select bits 22 23 read-write SCK14B SCK14 Input/Output Select bits 20 21 read-write SOT14B SOT14 Input/Output Select bits 18 19 read-write SIN14S SIN14 Input Select bits 16 17 read-write SCK13B SCK13 Input/Output Select bits 14 15 read-write SOT13B SOT13 Input/Output Select bits 12 13 read-write SIN13S SIN13 Input Select bits 10 11 read-write SCK12B SCK12 Input/Output Select bits 8 9 read-write SOT12B SOT12 Input/Output Select bits 6 7 read-write SIN12S SIN12 Input Select bits 4 5 read-write EPFR18 Extended Pin Function Setting Register 18 0x648 32 read-write 0x00000000 0x3FFFC3FF SDWPS S_WP input select bits 28 29 read-write SDCDS S_CD input select bits 26 27 read-write SDDATA3B S_CD input select bits 24 25 read-write SDDATA2B S_CD input select bits 22 23 read-write SDDATA1B S_CD input select bits 20 21 read-write SDDATA0B S_CD input select bits 18 19 read-write SDCMDB S_CMD input/output select bits 16 17 read-write SDCLKE S_CLK output select bits 14 15 read-write QZIN3S QDU-ch3 ZIN input select bits 8 9 read-write QBIN3S QDU-ch3 BIN input select bits 6 7 read-write QAIN3S QDU-ch3 AIN input select bits 4 5 read-write CECR1B CEC1 Input/Output Select bit 2 3 read-write CECR0B CEC0 Input/Output Select bit 0 1 read-write EPFR19 Extended Pin Function Setting Register 19 0x64C 32 read-write 0x00000000 0x00000000 EPFR20 Extended Pin Function Setting Register 20 0x650 32 read-write 0x0 0x01FFFFFF UED31B UED31B input/output select bit 24 24 read-write UED30B UED30B input/output select bit 23 23 read-write UED29B UED29B input/output select bit 22 22 read-write UED28B UED28B input/output select bit 21 21 read-write UED27B UED27B input/output select bit 20 20 read-write UED26B UED26B input/output select bit 19 19 read-write UED25B UED25B input/output select bit 18 18 read-write UED24B UED24B input/output select bit 17 17 read-write UED23B UED23B input/output select bit 16 16 read-write UED22B UED22B input/output select bit 15 15 read-write UED21B UED21B input/output select bit 14 14 read-write UED20B UED20B input/output select bit 13 13 read-write UED19B UED19B input/output select bit 12 12 read-write UED18B UED18B input/output select bit 11 11 read-write UED17B UED17B input/output select bit 10 10 read-write UED16B UED16B input/output select bit 9 9 read-write UEDTHHB UEDTHHB input/output select bit 8 8 read-write UEDQM3E UEDQM3E output select bit 7 7 read-write UEDQM2E UEDQM2E output select bit 6 6 read-write UECSXE UECSXE output select bit 5 5 read-write UEDWEXE UEDWEXE output select bit 4 4 read-write UECASE UECASE output select bit 3 3 read-write UERASE UERASE output select bit 2 2 read-write UESMCEE UESMCEE output select bit 1 1 read-write UESMCKE UESMCKE output select bit 0 0 read-write EPFR21 Extended Pin Function Setting Register 21 0x654 32 read-write 0x00000000 0x00000000 EPFR22 Extended Pin Function Setting Register 22 0x658 32 read-write 0x00000000 0x00000000 EPFR23 Extended Pin Function Setting Register 23 0x65C 32 read-write 0x00000000 0x0000FFFF SCS73E SCS73 Input Select bits 14 15 read-write SCS72E SCS72 Input Select bits 12 13 read-write SCS71E SCS71 Input Select bits 10 11 read-write SCS70E SCS70 Input Select bits 8 9 read-write SCS63E SCS63 Input Select bits 6 7 read-write SCS62E SCS62 Input Select bits 4 5 read-write SCS61E SCS61 Input Select bits 2 3 read-write SCS60E SCS60 Input Select bits 0 1 read-write EPFR24 Extended Pin Function Setting Register 24 0x660 32 read-write 0x00000000 0x00000FFF I2SM4_SDO0E I2SDO0 Output Select bits 10 11 read-write I2SM4_SDI0S I2SDI0 Input Select bits 8 9 read-write I2SM4_WS0B I2SWS0 Input/Output Select bits 6 7 read-write I2SM4_SCK0B I2SCK0 Input/Output Select bits 4 5 read-write I2SM4_MCLK0E I2SMCLK0 Output Select bits 2 3 read-write I2SM4_MCLK0S I2SMCLK0 Input Select bits 0 1 read-write EPFR25 Extended Pin Function Setting Register 25 0x664 32 read-write 0x00000000 0x0000000F MCTX2E TX2 Output Select bits 2 3 read-write MCRX2S RX2 Input Select bits 0 1 read-write EPFR26 Extended Pin Function Setting Register 26 0x668 32 read-write 0x00000000 0x0003FFFF Q_IO3B Q_IO3 Input Select bits 16 17 read-write Q_IO2B Q_IO2 Input Select bits 14 15 read-write Q_IO1B Q_IO1 Input Select bits 12 13 read-write Q_IO0B Q_IO0 Input Select bits 10 11 read-write Q_CS3E Q_CS3 Input Select bits 8 9 read-write Q_CS2E Q_CS2 Input Select bits 6 7 read-write Q_CS1E Q_CS1 Input Select bits 4 5 read-write Q_CS0E Q_CS0 Input Select bits 2 3 read-write Q_SCKE Q_SCK Input Select bits 0 1 read-write PZR0 Port Pseudo Open Drain Setting Register 0 0x700 PZR1 Port Pseudo Open Drain Setting Register 1 0x704 PZR2 Port Pseudo Open Drain Setting Register 2 0x708 PZR3 Port Pseudo Open Drain Setting Register 3 0x70C PZR4 Port Pseudo Open Drain Setting Register 4 0x710 PZR5 Port Pseudo Open Drain Setting Register 5 0x714 PZR6 Port Pseudo Open Drain Setting Register 6 0x718 PZR7 Port Pseudo Open Drain Setting Register 7 0x71C PZR8 Port Pseudo Open Drain Setting Register 8 0x720 PZR9 Port Pseudo Open Drain Setting Register 9 0x724 PZRA Port Pseudo Open Drain Setting Register A 0x728 PZRB Port Pseudo Open Drain Setting Register B 0x72C PZRC Port Pseudo Open Drain Setting Register C 0x730 PZRD Port Pseudo Open Drain Setting Register D 0x734 PZRE Port Pseudo Open Drain Setting Register E 0x738 PZRF Port Pseudo Open Drain Setting Register F 0x73C PDSR0 /dr 0x740 PDSR1 /dr 0x744 PDSR2 /dr 0x748 PDSR3 /dr 0x74C PDSR4 /dr 0x750 PDSR5 /dr 0x754 PDSR6 /dr 0x758 PDSR7 /dr 0x75C PDSR8 /dr 0x760 PDSR9 /dr 0x764 PDSRA /dr 0x768 PDSRB /dr 0x76C PDSRC /dr 0x770 PDSRD /dr 0x774 PDSRE /dr 0x778 PDSRF /dr 0x77C LVD Low-voltage Detection LVD 0x40035000 0x0 0x1 registers 0x4 0x1 registers 0x8 0x1 registers 0xC 0x5 registers LVD 2 LVD_CTL Low-voltage Detection Voltage Control Register 0x0 8 read-write 0x40 0xFC LVDIE Low-voltage detection interrupt enable bit 7 7 read-write SVHI Low-voltage detection interrupt voltage setting bits 2 6 read-write LVD_STR Low-voltage Detection Interrupt Factor Register 0x4 8 read-only 0x00 0x80 LVDIR Low-voltage detection interrupt factor bit 7 7 read-only LVD_CLR Low-voltage Detection Interrupt Factor Clear Register 0x8 8 read-write 0x80 0x80 LVDCL Low-voltage detection interrupt factor clear bit 7 7 read-write LVD_RLR Low-voltage Detection Voltage Protection Register 0xC 32 read-write 0x00000001 0xFFFFFFFF LVDLCK Low-voltage Detection Voltage Control Register protection bits 0 31 read-write LVD_STR2 Low-voltage Detection Circuit Status Register 0x10 8 read-only 0x40 0x80 LVDIRDY Low-voltage detection interrupt status flag 7 7 read-only DS Low Power Consumption Mode DS 0x40035100 0x4 0x1 registers 0x700 0x1 registers 0x704 0x1 registers 0x708 0x2 registers 0x70C 0x2 registers 0x710 0x1 registers 0x714 0x1 registers 0x800 0x16 registers RCK_CTL Sub Clock Control Register 0x4 8 read-write 0x01 0x03 CECCKE CEC clock control bit 1 1 read-write RTCCKE RTC clock control bit 0 0 read-write PMD_CTL RTC Mode Control Register 0x700 8 read-write 0x00 0x01 RTCE RTC mode control bit 0 0 read-write WRFSR Deep Standby Return Cause Register 1 0x704 8 read-write 0x00 0x03 WLVDH Low-voltage detection reset return bit 1 1 read-write WINITX INITX pin input reset return bit 0 0 read-write WIFSR Deep Standby Return Cause Register 2 0x708 16 read-only 0x0000 0x00FF WUI5 WKUP pin input return bit 5 7 7 read-only WUI4 WKUP pin input return bit 4 6 6 read-only WUI3 WKUP pin input return bit 3 5 5 read-only WUI2 WKUP pin input return bit 2 4 4 read-only WUI1 WKUP pin input return bit 1 3 3 read-only WUI0 WKUP pin input return bit 0 2 2 read-only WLVDI LVD interrupt return bit 1 1 read-only WRTCI RTC interrupt return bit 0 0 read-only WIER Deep Standby Return Enable Register 0x70C 16 read-write 0x0000 0x00FB WUI5E WKUP pin input return enable bit 5 7 7 read-write WUI4E WKUP pin input return enable bit 4 6 6 read-write WUI3E WKUP pin input return enable bit 3 5 5 read-write WUI2E WKUP pin input return enable bit 2 4 4 read-write WUI1E WKUP pin input return enable bit 1 3 3 read-write WLVDE LVD interrupt return enable bit 1 1 read-write WRTCE RTC interrupt return enable bit 0 0 read-write WILVR WKUP Pin Input Level Register 0x710 8 read-write 0x00 0x1F WUI5LV WKUP pin input level select bit 5 4 4 read-write WUI4LV WKUP pin input level select bit 4 3 3 read-write WUI3LV WKUP pin input level select bit 3 2 2 read-write WUI2LV WKUP pin input level select bit 2 1 1 read-write WUI1LV WKUP pin input level select bit 1 0 0 read-write DSRAMR Deep Standby RAM Retention Register 0x714 8 read-write 0x00 0x03 SRAMR On-chip SRAM retention control bits 0 1 read-write BUR01 Backup Registers from 1 0x800 8 read-write 0x00 0xFF BUR02 Backup Registers from 2 0x801 8 read-write 0x00 0xFF BUR03 Backup Registers from 3 0x802 8 read-write 0x00 0xFF BUR04 Backup Registers from 4 0x803 8 read-write 0x00 0xFF BUR05 Backup Registers from 5 0x804 8 read-write 0x00 0xFF BUR06 Backup Registers from 6 0x805 8 read-write 0x00 0xFF BUR07 Backup Registers from 7 0x806 8 read-write 0x00 0xFF BUR08 Backup Registers from 8 0x807 8 read-write 0x00 0xFF BUR09 Backup Registers from 9 0x808 8 read-write 0x00 0xFF BUR10 Backup Registers from 10 0x809 8 read-write 0x00 0xFF BUR11 Backup Registers from 11 0x80A 8 read-write 0x00 0xFF BUR12 Backup Registers from 12 0x80B 8 read-write 0x00 0xFF BUR13 Backup Registers from 13 0x80C 8 read-write 0x00 0xFF BUR14 Backup Registers from 14 0x80D 8 read-write 0x00 0xFF BUR15 Backup Registers from 15 0x80E 8 read-write 0x00 0xFF BUR16 Backup Registers from 16 0x80F 8 read-write 0x00 0xFF MFS0 Multi-function Serial Interface 0 MFS0 0x40038000 0x0 0x2 registers 0x4 0x2 registers 0x8 0x2 registers 0xC 0x2 registers 0x10 0x2 registers 0x0 0x2 registers 0x4 0x2 registers 0x8 0x2 registers 0xC 0x2 registers 0x10 0x2 registers 0x14 0x2 registers 0x18 0x2 registers 0x1C 0x2 registers 0x20 0x2 registers 0x24 0x2 registers 0x28 0x2 registers 0x2C 0x2 registers 0x30 0x2 registers 0x34 0x2 registers 0x38 0x1 registers 0x3C 0x2 registers 0x40 0x2 registers MFS0_RX 60 MFS0_TX 61 UART_SCR Serial Control Register UART 0x1 8 read-write 0x00 0x9F UPCL Programmable Clear bit 7 7 read-write RIE Received interrupt enable bit 4 4 read-write TIE Transmit interrupt enable bit 3 3 read-write TBIE Transmit bus idle interrupt enable bit 2 2 read-write RXE Received operation enable bit 1 1 read-write TXE Transmission operation enable bit 0 0 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write 0x00 0xED MD Operation mode set bit 5 7 read-write SBL Stop bit length select bit 3 3 read-write BDS Transfer direction select bit 2 2 read-write SOE Serial data output enable bit 0 0 read-write UART_SSR Serial Status Register UART 0x5 8 read-write 0x03 0xBF REC Received error flag clear bit 7 7 read-write PE Parity error flag bit (only functions in operation mode 0) 5 5 read-only FRE Framing error flag bit 4 4 read-only ORE Overrun error flag bit 3 3 read-only RDRF Received data full flag bit 2 2 read-only TDRE Transmit data empty flag bit 1 1 read-only TBI Transmit bus idle flag 0 0 read-only UART_ESCR Extended Communication Control Register UART 0x4 8 read-write 0x00 0xFF FLWEN Flow control enable bit 7 7 read-write ESBL Extension stop bit length select bit 6 6 read-write INV Inverted serial data format bit 5 5 read-write PEN Parity enable bit (only functions in operation mode 0) 4 4 read-write P Parity select bit (only functions in operation mode 0) 3 3 read-write L Data length select bit 0 2 read-write UART_RDR Received Data Register UART 0x8 16 read-only 0x0000 0x01FF D Data 0 8 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only 0x01FF 0x01FF D Data 0 8 write-only UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write 0x0000 0xFFFF EXT External clock select bit 15 15 read-write BGR1 Baud Rate Generator Registers 1 8 14 read-write BGR0 Baud Rate Generator Registers 0 0 7 read-write UART_FCR1 FIFO Control Register 1 UART 0x15 8 read-write 0x04 0x1F FLSTE Re-transmission data lost detect enable bit 4 4 read-write FRIIE Received FIFO idle detection enable bit 3 3 read-write FDRQ Transmit FIFO data request bit 2 2 read-write FTIE Transmit FIFO interrupt enable bit 1 1 read-write FSEL FIFO select bit 0 0 read-write UART_FCR0 FIFO Control Register 0 UART 0x14 8 read-write 0x00 0x7F FLST FIFO re-transmit data lost flag bit 6 6 read-only FLD FIFO pointer reload bit 5 5 read-write FSET FIFO pointer save bit 4 4 read-write FCL2 FIFO2 reset bit 3 3 read-write FCL1 FIFO1 reset bit 2 2 read-write FE2 FIFO2 operation enable bit 1 1 read-write FE1 FIFO1 operation enable bit 0 0 read-write UART_FBYTE1 FIFO Byte Register 1 UART 0x18 8 read-write 0x00 0xFF UART_FBYTE2 FIFO Byte Register 2 UART 0x19 8 read-write 0x00 0xFF CSIO_SCR Serial Control Register CSIO 0x1 8 read-write 0x00 0xFF UPCL Programmable clear bit 7 7 read-write MS Master/Slave function select bit 6 6 read-write SPI SPI corresponding bit 5 5 read-write RIE Received interrupt enable bit 4 4 read-write TIE Transmit interrupt enable bit 3 3 read-write TBIE Transmit bus idle interrupt enable bit 2 2 read-write RXE Data received enable bit 1 1 read-write TXE Data transmission enable bit 0 0 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write 0x00 0xEF MD Operation mode set bits 5 7 read-write SCINV Serial clock invert bit 3 3 read-write BDS Transfer direction select bit 2 2 read-write SCKE Master mode serial clock output enable bit 1 1 read-write SOE Serial data output enable bit 0 0 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write 0x03 0x9F REC Received error flag clear bit 7 7 read-write AWC Access Width Control bit 4 4 read-write ORE Overrun error flag bit 3 3 read-only RDRF Received data full flag bit 2 2 read-only TDRE Transmit data empty flag bit 1 1 read-only TBI Transmit bus idle flag bit 0 0 read-only CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write 0x00 0xFF SOP Serial output pin set bit 7 7 read-write L3 Bit3 of Data length select bits 6 6 read-write CSFE Serial Chip Select Format enable bit 5 5 read-write WT Data transmit/received wait select bits 3 4 read-write L Data length select bits 0 2 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only 0x0000 0xFFFF D Data 0 15 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only 0xFFFF 0xFFFF D Data 0 15 write-only CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write 0x0000 0x7FFF BGR1 Baud Rate Generator Registers 1 8 14 read-write BGR0 Baud Rate Generator Registers 0 0 7 read-write CSIO_FCR1 FIFO Control Register 1 CSIO 0x15 8 read-write 0x04 0x1F FLSTE Re-transmission data lost detect enable bit 4 4 read-write FRIIE Received FIFO idle detection enable bit 3 3 read-write FDRQ Transmit FIFO data request bit 2 2 read-write FTIE Transmit FIFO interrupt enable bit 1 1 read-write FSEL FIFO select bit 0 0 read-write CSIO_FCR0 FIFO Control Register 0 CSIO 0x14 8 read-write 0x00 0x7F FLST FIFO re-transmit data lost flag bit 6 6 read-only FLD FIFO pointer reload bit 5 5 read-write FSET FIFO pointer save bit 4 4 read-write FCL2 FIFO2 reset bit 3 3 read-write FCL1 FIFO1 reset bit 2 2 read-write FE2 FIFO2 operation enable bit 1 1 read-write FE1 FIFO1 operation enable bit 0 0 read-write CSIO_FBYTE1 FIFO Byte Register 1 CSIO 0x18 8 read-write 0x00 0xFF CSIO_FBYTE2 FIFO Byte Register 2 CSIO 0x19 8 read-write 0x00 0xFF CSIO_SCSTR0 Serial Chip Select Timing Register 0 CSIO 0x1C 8 read-write 0x00 0xFF CSHD Serial Chip Select Hold Delay bits 0 7 read-write CSIO_SCSTR1 Serial Chip Select Timing Register 1 CSIO 0x1D 8 read-write 0x00 0xFF CSSU Serial Chip Select Setup Delay bits 0 7 read-write CSIO_SCSTR2 Serial Chip Select Timing Registers 2/3 CSIO 0x20 16 read-write 0x0000 0xFFFF CSDS Serial Chip Deselect bits 0 15 read-write CSIO_SCSTR3 Serial Chip Select Timing Registers 3 CSIO 0x21 8 read-write 0x00 0xFF CSIO_SACSR Serial Support Control Register CSIO 0x24 16 read-write 0x0000 0x39DF TBEEN Transfer Byte Error Enable bit 13 13 read-write CSEIE Chip Select Error Interupt Enable bit 12 12 read-write CSE Chip Select Error Flag 11 11 read-write TINT Timer Interrupt Flag 8 8 read-write TINTE Timer Interrupt Enable bit 7 7 read-write TSYNE Synchronous Transmission Enable bit 6 6 read-write TDIV Timer Operation Clock Division bit 1 4 read-write TMRE Serial Timer Enable bit 0 0 read-write CSIO_STMR Serial Timer Register CSIO 0x28 16 read-only 0x0000 0xFFFF TM Timer Data bits 0 15 read-only CSIO_STMCR Serial Timer Comparison Register CSIO 0x2C 16 read-write 0x0000 0xFFFF TC Compare bits 0 15 read-write CSIO_SCSCR Serial Chip Select Control Status Register CSIO 0x30 16 read-write 0x0020 0xFFFF SST Serial Chip Select Active Start bit 14 15 read-write SED Serial Chip Select Active End bit 12 13 read-write SCD Serial Chip Select Active Display bit 10 11 read-write SCAM Serial Chip Select Active Hold bit 9 9 read-write CDIV Serial Chip Select Timing Operation Clock Division bit 6 8 read-write CSLVL Serial Chip Select Level Setting bit 5 5 read-write CSEN3 Serial Chip Select Enable bit with SCS3 pin 4 4 read-write CSEN2 Serial Chip Select Enable bit with SCS2 pin 3 3 read-write CSEN1 Serial Chip Select Enable bit with SCS1 pin 2 2 read-write CSEN0 Serial Chip Select Enable bit with SCS0 pin 1 1 read-write CSOE Serial Chip Select Output Enable bit 0 0 read-write CSIO_SCSFR0 Serial Chip Select Format Register 0 CSIO 0x34 8 read-write 0x00 0xFF CS1CSLVL Serial Chip Select 1 Level Setting bit 7 7 read-write CS1SCINV Serial Clock Invert bit of Serial Chip Select 1 6 6 read-write CS1SPI SPI corresponding bit of Serial Chip Select 1 5 5 read-write CS1L Transfer direction select bit of Serial Chip Select 1 0 4 read-write CSIO_SCSFR1 Serial Chip Select Format Register 1 CSIO 0x35 8 read-write 0x00 0xFF CS2CSLVL Serial Chip Select 2 Level Setting bit 7 7 read-write CS2SCINV Serial Clock Invert bit of Serial Chip Select 2 6 6 read-write CS2SPI SPI corresponding bit of Serial Chip Select 2 5 5 read-write CS2L Transfer direction select bit of Serial Chip Select 2 0 4 read-write CSIO_SCSFR2 Serial Chip Select Format Register 2 CSIO 0x38 8 read-write 0x00 0xFF CS3CSLVL Serial Chip Select 3 Level Setting bit 7 7 read-write CS3SCINV Serial Clock Invert bit of Serial Chip Select 3 6 6 read-write CS3SPI SPI corresponding bit of Serial Chip Select 3 5 5 read-write CS3L Transfer direction select bit of Serial Chip Select 3 0 4 read-write CSIO_TBYTE0 Transfer Byte Register 0 CSIO 0x3C 8 read-write 0x00 0xFF CSIO_TBYTE1 Transfer Byte Register 1 CSIO 0x3D 8 read-write 0x00 0xFF CSIO_TBYTE2 Transfer Byte Register 2 CSIO 0x40 8 read-write 0x00 0xFF CSIO_TBYTE3 Transfer Byte Register 3 CSIO 0x41 8 read-write 0x00 0xFF LIN_SCR Serial Control Register LIN 0x1 8 read-write 0x00 0xFF UPCL Programmable clear bit 7 7 read-write MS Master/Slave function select bit 6 6 read-write LBR LIN Break Field setting bit (valid in master mode only) 5 5 read-write RIE Received interrupt enable bit 4 4 read-write TIE Transmit interrupt enable bit 3 3 read-write TBIE Transmit bus idle interrupt enable bit 2 2 read-write RXE Data reception enable bit 1 1 read-write TXE Data transmission enable bit 0 0 read-write LIN_SMR Serial Mode Register LIN 0x0 8 read-write 0x00 0xF9 MD Operation mode setting bits 5 7 read-write WUCR Wake-up control bit 4 4 read-write SBL Stop bit length select bit 3 3 read-write SOE Serial data output enable bit 0 0 read-write LIN_SSR Serial Status Register LIN 0x5 8 read-write 0x03 0xBF REC Received Error flag clear bit 7 7 read-write LBD LIN Break field detection flag bit 5 5 read-write FRE Framing error flag bit 4 4 read-only ORE Overrun error flag bit 3 3 read-only RDRF Received data full flag bit 2 2 read-only TDRE Transmit data empty flag bit 1 1 read-only TBI Transmit bus idle flag bit 0 0 read-only LIN_ESCR Extended Communication Control Register LIN 0x4 8 read-write 0x00 0xDF ESBL Extended stop bit length select bit 6 6 read-write LBIE LIN Break field detect interrupt enable bit 4 4 read-write LBL LIN Break field length select bits (valid in master mode only) 2 3 read-write DEL LIN Break delimiter length select bits (valid in master mode only) 0 1 read-write LIN_RDR Received Data Register LIN 0x8 16 read-only 0x0000 0x00FF D Data 0 7 read-only LIN_TDR Transmit Data Register LIN 0x8 16 write-only 0x00FF 0x00FF D Data 0 7 write-only LIN_BGR Baud Rate Generator Registers LIN 0xC 16 read-write 0x0000 0xFFFF EXT External clock select bit 15 15 read-write BGR1 Baud Rate Generator Registers 1 8 14 read-write BGR0 Baud Rate Generator Registers 0 0 7 read-write LIN_FCR1 FIFO Control Register 1 LIN 0x15 8 read-write 0x04 0x1F FLSTE Re-transmission data lost detect enable bit 4 4 read-write FRIIE Received FIFO idle detection enable bit 3 3 read-write FDRQ Transmit FIFO data request bit 2 2 read-write FTIE Transmit FIFO interrupt enable bit 1 1 read-write FSEL FIFO select bit 0 0 read-write LIN_FCR0 FIFO Control Register 0 LIN 0x14 8 read-write 0x00 0x7F FLST FIFO re-transmit data lost flag bit 6 6 read-only FLD FIFO pointer reload bit 5 5 read-write FSET FIFO pointer save bit 4 4 read-write FCL2 FIFO2 reset bit 3 3 read-write FCL1 FIFO1 reset bit 2 2 read-write FE2 FIFO2 operation enable bit 1 1 read-write FE1 FIFO1 operation enable bit 0 0 read-write LIN_FBYTE1 FIFO Byte Register 1 LIN 0x18 8 read-write 0x00 0xFF LIN_FBYTE2 FIFO Byte Register 2 LIN 0x19 8 read-write 0x00 0xFF I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write 0x00 0xFF MSS Master/slave select bit 7 7 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 6 read-write ACKE Data byte acknowledge enable bit 5 5 read-write WSEL Wait selection bit 4 4 read-write CNDE Condition detection interrupt enable bit 3 3 read-write INTE Interrupt enable bit 2 2 read-write BER Bus error flag bit 1 1 read-only INT interrupt flag bit 0 0 read-write I2C_SMR Serial Mode Register I2C 0x0 8 read-write 0x00 0xEC MD operation mode set bits 5 7 read-write RIE Received interrupt enable bit 3 3 read-write TIE Transmit interrupt enable bit 2 2 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write 0x00 0xFF FBT First byte bit 7 7 read-only RACK Acknowledge flag bit 6 6 read-only RSA Reserved address detection bit 5 5 read-only TRX Data direction bit 4 4 read-only AL Arbitration lost bit 3 3 read-only RSC Iteration start condition check bit 2 2 read-write SPC Stop condition check bit 1 1 read-write BB Bus state bit 0 0 read-only I2C_SSR Serial Status Register I2C 0x5 8 read-write 0x03 0xFF REC Received error flag clear bit 7 7 read-write TSET Transmit empty flag set bit 6 6 read-write DMA DMA mode enable bit 5 5 read-write TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 4 read-write ORE Overrun error flag bit 3 3 read-only RDRF Received data full flag bit 2 2 read-only TDRE Transmit data empty flag bit 1 1 read-only TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 0 read-only I2C_RDR Received Data Register I2C 0x8 16 read-only 0x0000 0x00FF D Data 0 7 read-only I2C_TDR Transmit Data Register I2C 0x8 16 write-only 0x00FF 0x00FF D Data 0 7 write-only I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write 0x0000 0x7FFF BGR1 Baud Rate Generator Registers 1 8 14 read-write BGR0 Baud Rate Generator Registers 0 0 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write 0x7F 0xFF EN I2C interface operation enable bit 7 7 read-write SM Slave address mask bits 0 6 read-write I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write 0x00 0xFF SAEN Slave address enable bit 7 7 read-write SA 7-bit slave address 0 6 read-write I2C_FCR1 FIFO Control Register 1 I2C 0x15 8 read-write 0x04 0x1F FLSTE Re-transmission data lost detect enable bit 4 4 read-write FRIIE Received FIFO idle detection enable bit 3 3 read-write FDRQ Transmit FIFO data request bit 2 2 read-write FTIE Transmit FIFO interrupt enable bit 1 1 read-write FSEL FIFO select bit 0 0 read-write I2C_FCR0 FIFO Control Register 0 I2C 0x14 8 read-write 0x00 0x7F FLST FIFO re-transmit data lost flag bit 6 6 read-only FLD FIFO pointer reload bit 5 5 read-write FSET FIFO pointer save bit 4 4 read-write FCL2 FIFO2 reset bit 3 3 read-write FCL1 FIFO1 reset bit 2 2 read-write FE2 FIFO2 operation enable bit 1 1 read-write FE1 FIFO1 operation enable bit 0 0 read-write I2C_FBYTE1 FIFO Byte Register 1 I2C 0x18 8 read-write 0x0000 0xFFFF I2C_FBYTE2 FIFO Byte Register 2 I2C 0x19 8 read-write 0x0000 0xFFFF I2C_NFCR Noise Filter Control Register I2C 0x1C 8 read-write 0x00 0x1F NFT Noise Filter Time Select bits 0 4 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write 0x0C 0x3F SDAS SDA status bit 5 5 read-write SCLS SCL status bit 4 4 read-write SDAC SDA output control bit 3 3 read-write SCLC SCL output control bit 2 2 read-write SOCE Serial output enabled bit 1 1 read-write BEC Bus error control bit 0 0 read-write MFS1 0x40038100 MFS1_RX 62 MFS1_TX 63 MFS2 0x40038200 MFS2_RX 64 MFS2_TX 65 MFS3 0x40038300 MFS3_RX 66 MFS3_TX 67 MFS4 0x40038400 MFS4_RX 68 MFS4_TX 69 MFS5 0x40038500 MFS5_RX 70 MFS5_TX 71 MFS6 0x40038600 MFS6_RX 72 MFS6_TX 73 MFS7 0x40038700 MFS7_RX 74 MFS7_TX 75 MFS8 0x40038800 MFS8_RX 103 MFS8_TX 104 MFS9 0x40038900 MFS9_RX 105 MFS9_TX 106 MFS10 0x40038A00 MFS10_RX 107 MFS10_TX 108 MFS11 0x40038B00 MFS11_RX 109 MFS11_TX 110 MFS12 0x40038C00 MFS12_RX 120 MFS12_TX 121 MFS13 0x40038D00 MFS13_RX 122 MFS13_TX 123 MFS14 0x40038E00 MFS14_RX 124 MFS14_TX 125 MFS15 0x40038F00 MFS15_RX 126 MFS15_TX 127 CRC CRC Registers CRC 0x40039000 0x0 0x1 registers 0x4 0x4 registers 0x8 0x4 registers 0xC 0x4 registers CRCCR CRC Control Register 0x0 8 read-write 0x00 0x7F FXOR Initialization bit 6 6 read-write CRCLSF Final XOR control bit 5 5 read-write CRCLTE CRC result bit-order setting bit 4 4 read-write LSBFST CRC result byte-order setting bit 3 3 read-write LTLEND Bit-order setting bit 2 2 read-write CRC32 Byte-order setting bit 1 1 read-write INIT CRC mode selection bit 0 0 read-write CRCINIT Initial Value Register 0x4 32 read-write 0xFFFFFFFF 0xFFFFFFFF D Initial value 0 31 read-write CRCIN Input Data Register 0x8 32 read-write 0x00000000 0xFFFFFFFF D Input data 0 31 read-write CRCR CRC Register 0xC 32 read-only 0xFFFFFFFF 0xFFFFFFFF D CRC Data 0 31 read-only WC Watch Counter WC 0x4003A000 0x0 0x3 registers 0x10 0x2 registers 0x14 0x1 registers WC 48 WCRD Watch Counter Read Register 0x0 8 read-only 0x00 0x3F CTR Counter read bits 0 5 read-only WCRL Watch Counter Reload Register 0x01 8 read-write 0x00 0x3F RLC Counter reload value setting bits 0 5 read-write WCCR Watch Counter Control Register 0x02 8 read-write 0x00 0xCF WCEN Watch counter operation enable bit 7 7 read-write WCOP Watch counter operating state flag 6 6 read-only CS Count clock select bits 2 3 read-write WCIE Interrupt request enable bit 1 1 read-write WCIF Interrupt request flag bit 0 0 read-write CLK_SEL Clock Selection Register 0x10 16 read-write 0x0000 0x0703 SEL_OUT Output clock selection bit 8 10 read-write SEL_IN Input clock selection bit 0 1 read-write CLK_EN Division Clock Enable Register 0x14 8 read-write 0x00 0x03 CLK_EN_R Division clock enable read bit 1 1 read-write CLK_EN Division clock enable bit 0 0 read-write RTC REAL-TIME CLOCK RTC 0x4003B000 0x0 0x1B1 registers 0x200 0x80 registers RTC 50 WTCR10 Control Register 10 0x100 8 read-write 0x00 0xFD TRANS Transfer flag bit 7 7 read-only BUSY Busy bit 6 6 read-only SCRST Sub second generation/1-second generation counter reset bit 5 5 read-write SCST 1-second clock output stop bit 4 4 read-write SRST RTC reset bit 3 3 read-write RUN RTC count block operation bit 2 2 read-only ST Start bit 0 0 read-write WTCR11 Control Register 11 0x104 8 read-write 0x00 0x1F YEN Alarm year register enable bit 4 4 read-write MOEN Alarm month register enable bit 3 3 read-write DEN Alarm day register enable bit 2 2 read-write HEN Alarm hour register enable bit 1 1 read-write MIEN Alarm minute register enable bit 0 0 read-write WTCR12 Control Register 12 0x108 8 read-write 0x00 0xFF INTCRI Year/month/date/hour/minute/second/day of the week counter value read completion interrupt flag bit 7 7 read-write INTERI Time rewrite error interrupt flag bit 6 6 read-write INTALI Alarm coincidence flag bit 5 5 read-write INTTMI Timer underflow detection flag bit 4 4 read-write INTHI Every hour flag bit 3 3 read-write INTMI Every minute flag bit 2 2 read-write INTSI Every second flag bit 1 1 read-write INTSSI Every 0.5-second flag bit 0 0 read-write WTCR13 Control Register 13 0x10C 8 read-write 0x00 0xFF INTCRIE Year/month/date/hour/minute/second/day of the week counter value read completion interrupt enable bit 7 7 read-write INTERIE Time rewrite error interrupt enable bit 6 6 read-write INTALIE Alarm coincidence interrupt enable bit 5 5 read-write INTTMIE Timer underflow interrupt enable bit 4 4 read-write INTHIE Every hour interrupt enable bit 3 3 read-write INTMIE Every minute interrupt enable bit 2 2 read-write INTSIE Every second interrupt enable bit 1 1 read-write INTSSIE Every 0.5-second interrupt enable bit 0 0 read-write WTCR20 Control Register 20 0x110 32 read-write 0x00 0x3F PWRITE VBAT PORT save control bit 5 5 read-write PREAD VBAT PORT recall control bit 4 4 read-write BWRITE Back up register save control bit 3 3 read-write BREAD Back up register recall control bit 2 2 read-write CWRITE RTC setting save control bit 1 1 read-write CREAD RTC setting recall control bit 0 0 read-write WTCR21 Control Register 21 0x114 32 read-write 0x00 0x07 TMRUN Timer counter operation bit 2 2 read-only TMEN Timer counter control bit 1 1 read-write TMST Timer counter start bit 0 0 read-write WTSR Second Register 0x11C 8 read-write 0x00 0x7F TS 2nd digit of the second information 4 6 read-write S 1st digit of the second information 0 3 read-write WTMIR Minute Register 0x120 8 read-write 0x00 0x7F TMI 2nd digit of the minute information 4 6 read-write MI 1st digit of the minute information 0 3 read-write WTHR Hour register 0x124 8 read-write 0x00 0x3F TH 2nd digit of the hour information 4 5 read-write H 1st digit of the hour information 0 3 read-write WTDR Day Register 0x128 8 read-write 0x00 0x3F TD 2nd digit of the day information 4 5 read-write D 1st digit of the day information 0 3 read-write WTDW Day of the Week Register 0x12C 8 read-write 0x00 0x7 DW Day of the week information 0 2 read-write WTMOR Month Register 0x130 8 read-write 0x00 0x1F TMO0 2nd digit of the month information 4 4 read-write MO 1st digit of the month information 0 3 read-write WTYR Year Register 0x134 8 read-write 0x00 0xFF TY 2nd digit of the year information 4 7 read-write Y 1st digit of the year information 0 3 read-write ALMIR Alarm Minute Register 0x138 8 read-write 0x00 0x7F TAMI 2nd digit of the alarm-set minute information 4 6 read-write AMI 1st digit of the alarm-set minute information 0 3 read-write ALHR Alarm Hour Register 0x13C 8 read-write 0x00 0x3F TAH 2nd digit of the alarm-set hour information 4 5 read-write AH 1st digit of the alarm-set hour information 0 3 read-write ALDR Alarm Date Register 0x140 8 read-write 0x00 0x3F TAD 2nd digit of the alarm-set date information 4 5 read-write AD 1st digit of the alarm-set date information 0 3 read-write ALMOR Alarm Month Register 0x144 8 read-write 0x00 0x1F TAMO0 2nd digit of the alarm-set month information 4 4 read-write AMO 1st digit of the alarm-set month information 0 3 read-write ALYR Alarm Years Register 0x148 8 read-write 0x00 0xFF TAY 2nd digit of the alarm-set year information 4 7 read-write AY 1st digit of the alarm-set year information 0 3 read-write WTTR0 Timer Setting Register 0 0x14C 8 read-write 0x00 0xFF TM Timer Setting Register 0 7 read-write WTTR1 Timer Setting Register 1 0x150 8 read-write 0x00 0xFF TM Timer Setting Register 0 7 read-write WTTR2 Timer Setting Register 2 0x154 8 read-write 0x00 0x03 TM Timer Setting Register 0 1 read-write WTCAL0 Frequency Correction Value Setting Register 0 0x158 8 read-write 0x00 0xFF WTCAL0 Frequency correction value setting bits 0 0 7 read-write WTCAL1 Frequency Correction Value Setting Register 1 0x15C 8 read-write 0x00 0x03 WTCAL1 Frequency correction value setting bits 1 0 1 read-write WTCALEN Frequency Correction Enable Register 0x160 8 read-write 0x00 0x01 WTCALEN Frequency correction enable bit 0 0 read-write WTDIV Division Ratio Setting Register 0x164 8 read-write 0x00 0x0F WTDIV Division ration setting bits 0 3 read-write WTDIVEN Divider Output Enable Register 0x168 8 read-write 0x00 0x03 WTDIVRDY Divider state bit 1 1 read-only WTDIVEN Divider enable bit 0 0 read-write WTCALPRD Frequency Correction Period Setting Register 0x16C 8 read-write 0x13 0x3F WTCALPRD Frequency correction value setting bits 0 5 read-write WTCOSEL RTCCO Output Selection Register 0x170 8 read-write 0x00 0x01 WTCOSEL RTCCO output selection bit 0 0 read-write VB_CLKDIV VB_CLKDIV Register 0x174 8 read-write 0x07 0xFF DIV Transfer clock set bits 0 7 read-write WTOSCCNT WTOSCCNT Register 0x178 8 read-write 0x01 0x03 SOSCNTL Cooperative operation control bit 1 1 read-write SOSCEX Oscillation enable bit 0 0 read-write CCS CCS Register 0x17C 8 read-write 0x08 0xFF CCS Oscillation sustain current set bits 0 7 read-write CCB CCB Register 0x180 8 read-write 0x10 0xFF CCB Oscillation boost current set bits 0 7 read-write BOOST BOOST Register 0x188 8 read-write 0x03 0x03 BOOST Oscillation boost time set bits 0 1 read-write EWKUP EWKUP Register 0x18C 8 read-write 0x00 0x01 WUP0 Wakeup request bit 0 0 read-write VDET VDET Register 0x190 8 read-write 0x80 0x80 PON Power-on bit 7 7 read-write HIBRST HIBRST Register 0x198 8 read-write 0x00 0x01 HIBRST Hibernation start bit 0 0 read-write VBPFR Port Function Set Register 0x19C 8 read-write 0x1C 0x3F SPSR Oscillation pin function set bits 4 5 read-write VPFR3 Port function of P46/X0A pin set bit 3 3 read-write VPFR2 Port function of P47/X1A pin set bit 2 2 read-write VPFR1 Port function of P49/VWAKEUP pin set bit 1 1 read-write VPFR0 Port function of P48/VREGCTL pin set bit 0 0 read-write VBPCR Pull-up Set Register 0x1A0 8 read-write 0x00 0x0F VPCR3 P46/X0A pin pull-up set bit 3 3 read-write VPCR2 P47/X1A pin pull-up set bit 2 2 read-write VPCR1 P49/VWAKEUP pin pull-up set bit 1 1 read-write VPCR0 P48/VREGCTL pin pull-up set bit 0 0 read-write VBDDR Port I/O Direction Set Register 0x1A4 8 read-write 0x00 0x0F VDDR3 Port direction of P46/X0A pin set bit 3 3 read-write VDDR2 Port direction of P47/X1A pin set bit 2 2 read-write VDDR1 Port direction of P49/VWAKEUP pin set bit 1 1 read-write VDDR0 Port direction of P48/VREGCTL pin set bit 0 0 read-write VBDIR Port Input Data Register 0x1A8 8 read-write 0x00 0x0F VDIR3 Port input data of P46/X0A pin bit 3 3 read-write VDIR2 Port input data of P47/X1A pin bit 2 2 read-write VDIR1 Port input data of P49/VWAKEUP pin bit 1 1 read-write VDIR0 Port input data of P48/VREGCTL pin bit 0 0 read-write VBDOR Port Output Data Register 0x1AC 8 read-write 0x0F 0x0F VDOR3 Port output data of P46/X0A pin bit 3 3 read-write VDOR2 Port output data of P47/X1A pin bit 2 2 read-write VDOR1 Port output data of P49/VWAKEUP pin bit 1 1 read-write VDOR0 Port output data of P48/VREGCTL pin bit 0 0 read-write VBPZR Port Pseudo-Open Drain Set Register 0x1B0 8 read-write 0x03 0x03 VPZR1 P49/VWAKEUP pin pseudo-open drain set bit 1 1 read-write VPZR0 P48/VREGCTL pin pseudo-open drain set bit 0 0 read-write BREG00 Backup Register 0x200 8 read-write 0x00 0xFF BREG01 Backup Register 0x201 8 read-write 0x00 0xFF BREG02 Backup Register 0x202 8 read-write 0x00 0xFF BREG03 Backup Register 0x203 8 read-write 0x00 0xFF BREG04 Backup Register 0x204 8 read-write 0x00 0xFF BREG05 Backup Register 0x205 8 read-write 0x00 0xFF BREG06 Backup Register 0x206 8 read-write 0x00 0xFF BREG07 Backup Register 0x207 8 read-write 0x00 0xFF BREG08 Backup Register 0x208 8 read-write 0x00 0xFF BREG09 Backup Register 0x209 8 read-write 0x00 0xFF BREG0A Backup Register 0x20A 8 read-write 0x00 0xFF BREG0B Backup Register 0x20B 8 read-write 0x00 0xFF BREG0C Backup Register 0x20C 8 read-write 0x00 0xFF BREG0D Backup Register 0x20D 8 read-write 0x00 0xFF BREG0E Backup Register 0x20E 8 read-write 0x00 0xFF BREG0F Backup Register 0x20F 8 read-write 0x00 0xFF BREG10 Backup Register 0x210 8 read-write 0x00 0xFF BREG11 Backup Register 0x211 8 read-write 0x00 0xFF BREG12 Backup Register 0x212 8 read-write 0x00 0xFF BREG13 Backup Register 0x213 8 read-write 0x00 0xFF BREG14 Backup Register 0x214 8 read-write 0x00 0xFF BREG15 Backup Register 0x215 8 read-write 0x00 0xFF BREG16 Backup Register 0x216 8 read-write 0x00 0xFF BREG17 Backup Register 0x217 8 read-write 0x00 0xFF BREG18 Backup Register 0x218 8 read-write 0x00 0xFF BREG19 Backup Register 0x219 8 read-write 0x00 0xFF BREG1A Backup Register 0x21A 8 read-write 0x00 0xFF BREG1B Backup Register 0x21B 8 read-write 0x00 0xFF BREG1C Backup Register 0x21C 8 read-write 0x00 0xFF BREG1D Backup Register 0x21D 8 read-write 0x00 0xFF BREG1E Backup Register 0x21E 8 read-write 0x00 0xFF BREG1F Backup Register 0x21F 8 read-write 0x00 0xFF BREG20 Backup Register 0x220 8 read-write 0x00 0xFF BREG21 Backup Register 0x221 8 read-write 0x00 0xFF BREG22 Backup Register 0x222 8 read-write 0x00 0xFF BREG23 Backup Register 0x223 8 read-write 0x00 0xFF BREG24 Backup Register 0x224 8 read-write 0x00 0xFF BREG25 Backup Register 0x225 8 read-write 0x00 0xFF BREG26 Backup Register 0x226 8 read-write 0x00 0xFF BREG27 Backup Register 0x227 8 read-write 0x00 0xFF BREG28 Backup Register 0x228 8 read-write 0x00 0xFF BREG29 Backup Register 0x229 8 read-write 0x00 0xFF BREG2A Backup Register 0x22A 8 read-write 0x00 0xFF BREG2B Backup Register 0x22B 8 read-write 0x00 0xFF BREG2C Backup Register 0x22C 8 read-write 0x00 0xFF BREG2D Backup Register 0x22D 8 read-write 0x00 0xFF BREG2E Backup Register 0x22E 8 read-write 0x00 0xFF BREG2F Backup Register 0x22F 8 read-write 0x00 0xFF BREG30 Backup Register 0x230 8 read-write 0x00 0xFF BREG31 Backup Register 0x231 8 read-write 0x00 0xFF BREG32 Backup Register 0x232 8 read-write 0x00 0xFF BREG33 Backup Register 0x233 8 read-write 0x00 0xFF BREG34 Backup Register 0x234 8 read-write 0x00 0xFF BREG35 Backup Register 0x235 8 read-write 0x00 0xFF BREG36 Backup Register 0x236 8 read-write 0x00 0xFF BREG37 Backup Register 0x237 8 read-write 0x00 0xFF BREG38 Backup Register 0x238 8 read-write 0x00 0xFF BREG39 Backup Register 0x239 8 read-write 0x00 0xFF BREG3A Backup Register 0x23A 8 read-write 0x00 0xFF BREG3B Backup Register 0x23B 8 read-write 0x00 0xFF BREG3C Backup Register 0x23C 8 read-write 0x00 0xFF BREG3D Backup Register 0x23D 8 read-write 0x00 0xFF BREG3E Backup Register 0x23E 8 read-write 0x00 0xFF BREG3F Backup Register 0x23F 8 read-write 0x00 0xFF BREG40 Backup Register 0x240 8 read-write 0x00 0xFF BREG41 Backup Register 0x241 8 read-write 0x00 0xFF BREG42 Backup Register 0x242 8 read-write 0x00 0xFF BREG43 Backup Register 0x243 8 read-write 0x00 0xFF BREG44 Backup Register 0x244 8 read-write 0x00 0xFF BREG45 Backup Register 0x245 8 read-write 0x00 0xFF BREG46 Backup Register 0x246 8 read-write 0x00 0xFF BREG47 Backup Register 0x247 8 read-write 0x00 0xFF BREG48 Backup Register 0x248 8 read-write 0x00 0xFF BREG49 Backup Register 0x249 8 read-write 0x00 0xFF BREG4A Backup Register 0x24A 8 read-write 0x00 0xFF BREG4B Backup Register 0x24B 8 read-write 0x00 0xFF BREG4C Backup Register 0x24C 8 read-write 0x00 0xFF BREG4D Backup Register 0x24D 8 read-write 0x00 0xFF BREG4E Backup Register 0x24E 8 read-write 0x00 0xFF BREG4F Backup Register 0x24F 8 read-write 0x00 0xFF BREG50 Backup Register 0x250 8 read-write 0x00 0xFF BREG51 Backup Register 0x251 8 read-write 0x00 0xFF BREG52 Backup Register 0x252 8 read-write 0x00 0xFF BREG53 Backup Register 0x253 8 read-write 0x00 0xFF BREG54 Backup Register 0x254 8 read-write 0x00 0xFF BREG55 Backup Register 0x255 8 read-write 0x00 0xFF BREG56 Backup Register 0x256 8 read-write 0x00 0xFF BREG57 Backup Register 0x257 8 read-write 0x00 0xFF BREG58 Backup Register 0x258 8 read-write 0x00 0xFF BREG59 Backup Register 0x259 8 read-write 0x00 0xFF BREG5A Backup Register 0x25A 8 read-write 0x00 0xFF BREG5B Backup Register 0x25B 8 read-write 0x00 0xFF BREG5C Backup Register 0x25C 8 read-write 0x00 0xFF BREG5D Backup Register 0x25D 8 read-write 0x00 0xFF BREG5E Backup Register 0x25E 8 read-write 0x00 0xFF BREG5F Backup Register 0x25F 8 read-write 0x00 0xFF BREG60 Backup Register 0x260 8 read-write 0x00 0xFF BREG61 Backup Register 0x261 8 read-write 0x00 0xFF BREG62 Backup Register 0x262 8 read-write 0x00 0xFF BREG63 Backup Register 0x263 8 read-write 0x00 0xFF BREG64 Backup Register 0x264 8 read-write 0x00 0xFF BREG65 Backup Register 0x265 8 read-write 0x00 0xFF BREG66 Backup Register 0x266 8 read-write 0x00 0xFF BREG67 Backup Register 0x267 8 read-write 0x00 0xFF BREG68 Backup Register 0x268 8 read-write 0x00 0xFF BREG69 Backup Register 0x269 8 read-write 0x00 0xFF BREG6A Backup Register 0x26A 8 read-write 0x00 0xFF BREG6B Backup Register 0x26B 8 read-write 0x00 0xFF BREG6C Backup Register 0x26C 8 read-write 0x00 0xFF BREG6D Backup Register 0x26D 8 read-write 0x00 0xFF BREG6E Backup Register 0x26E 8 read-write 0x00 0xFF BREG6F Backup Register 0x26F 8 read-write 0x00 0xFF BREG70 Backup Register 0x270 8 read-write 0x00 0xFF BREG71 Backup Register 0x271 8 read-write 0x00 0xFF BREG72 Backup Register 0x272 8 read-write 0x00 0xFF BREG73 Backup Register 0x273 8 read-write 0x00 0xFF BREG74 Backup Register 0x274 8 read-write 0x00 0xFF BREG75 Backup Register 0x275 8 read-write 0x00 0xFF BREG76 Backup Register 0x276 8 read-write 0x00 0xFF BREG77 Backup Register 0x277 8 read-write 0x00 0xFF BREG78 Backup Register 0x278 8 read-write 0x00 0xFF BREG79 Backup Register 0x279 8 read-write 0x00 0xFF BREG7A Backup Register 0x27A 8 read-write 0x00 0xFF BREG7B Backup Register 0x27B 8 read-write 0x00 0xFF BREG7C Backup Register 0x27C 8 read-write 0x00 0xFF BREG7D Backup Register 0x27D 8 read-write 0x00 0xFF BREG7E Backup Register 0x27E 8 read-write 0x00 0xFF BREG7F Backup Register 0x27F 8 read-write 0x00 0xFF LCR Low-speed CR Prescaler LCR 0x4003C000 0x0 0x1 registers LCR_PRSLD Low-speed CR Prescaler Control Register 0x0 8 read-write 0x00 0x3F LCR_PRSLD Low-speed CR Prescaler Load 0 5 read-write CLK_GATING Peripheral Clock Gating CLK_GATING 0x4003C100 0x0 0x4 registers 0x4 0x4 registers 0x10 0x4 registers 0x14 0x4 registers 0x20 0x4 registers 0x24 0x4 registers CKEN0 Peripheral Function Clock Control Register 0 0x0 32 read-write 0x150FFFFF 0x150FFFFF GIOCK Settings for operation clock supplying and gating to GPIO function 28 28 read-write EXBCK Settings for operation clock supplying and gating of external bus interface function 26 26 read-write DMACK Supplying and gating settings of DMAC operation clock 24 24 read-write ADCCK3 Settings for operation clock supplying and gating to A/D converter unit 3 19 19 read-write ADCCK2 Settings for operation clock supplying and gating to A/D converter unit 2 18 18 read-write ADCCK1 Settings for operation clock supplying and gating to A/D converter unit 1 17 17 read-write ADCCK0 Settings for operation clock supplying and gating to A/D converter unit 0 16 16 read-write MFSCK15 Settings for operation clock supply and gating to multi-function serial interface ch.15 15 15 read-write MFSCK14 Settings for operation clock supply and gating to multi-function serial interface ch.14 14 14 read-write MFSCK13 Settings for operation clock supply and gating to multi-function serial interface ch.13 13 13 read-write MFSCK12 Settings for operation clock supply and gating to multi-function serial interface ch.12 12 12 read-write MFSCK11 Settings for operation clock supply and gating to multi-function serial interface ch.11 11 11 read-write MFSCK10 Settings for operation clock supply and gating to multi-function serial interface ch.10 10 10 read-write MFSCK9 Settings for operation clock supply and gating to multi-function serial interface ch.9 9 9 read-write MFSCK8 Settings for operation clock supply and gating to multi-function serial interface ch.8 8 8 read-write MFSCK7 Settings for operation clock supply and gating to multi-function serial interface ch.7 7 7 read-write MFSCK6 Settings for operation clock supply and gating to multi-function serial interface ch.6 6 6 read-write MFSCK5 Settings for operation clock supply and gating to multi-function serial interface ch.5 5 5 read-write MFSCK4 Settings for operation clock supply and gating to multi-function serial interface ch.4 4 4 read-write MFSCK3 Settings for operation clock supply and gating to multi-function serial interface ch.3 3 3 read-write MFSCK2 Settings for operation clock supply and gating to multi-function serial interface ch.2 2 2 read-write MFSCK1 Settings for operation clock supply and gating to multi-function serial interface ch.1 1 1 read-write MFSCK0 Settings for operation clock supply and gating to multi-function serial interface ch.0 0 0 read-write MRST0 Peripheral Function Reset Control Register 0 0x4 32 read-write 0x00000000 0x050FFFFF EXBRST Reset control for external bus interface 26 26 read-write DMARST Reset control of DMAC 24 24 read-write ADCRST3 Reset control of A/D converter unit 3 19 19 read-write ADCRST2 Reset control of A/D converter unit 2 18 18 read-write ADCRST1 Reset control of A/D converter unit 1 17 17 read-write ADCRST0 Reset control of A/D converter unit 0 16 16 read-write MFSRST15 Control of software reset of multi-function serial interface ch.15 15 15 read-write MFSRST14 Control of software reset of multi-function serial interface ch.14 14 14 read-write MFSRST13 Control of software reset of multi-function serial interface ch.13 13 13 read-write MFSRST12 Control of software reset of multi-function serial interface ch.12 12 12 read-write MFSRST11 Control of software reset of multi-function serial interface ch.11 11 11 read-write MFSRST10 Control of software reset of multi-function serial interface ch.10 10 10 read-write MFSRST9 Control of software reset of multi-function serial interface ch.9 9 9 read-write MFSRST8 Control of software reset of multi-function serial interface ch.8 8 8 read-write MFSRST7 Control of software reset of multi-function serial interface ch.7 7 7 read-write MFSRST6 Control of software reset of multi-function serial interface ch.6 6 6 read-write MFSRST5 Control of software reset of multi-function serial interface ch.5 5 5 read-write MFSRST4 Control of software reset of multi-function serial interface ch.4 4 4 read-write MFSRST3 Control of software reset of multi-function serial interface ch.3 3 3 read-write MFSRST2 Control of software reset of multi-function serial interface ch.2 2 2 read-write MFSRST1 Control of software reset of multi-function serial interface ch.1 1 1 read-write MFSRST0 Control of software reset of multi-function serial interface ch.0 0 0 read-write CKEN1 Peripheral Function Clock Control Register 1 0x10 32 read-write 0x000F0F0F 0x000F0F0F QDUCK3 Reset control of quad counter unit 3 19 19 read-write QDUCK2 Reset control of quad counter unit 2 18 18 read-write QDUCK1 Reset control of quad counter unit 1 17 17 read-write QDUCK0 Reset control of quad counter unit 0 16 16 read-write MFTCK3 Settings for operation clock supply and gating of multi-function timer 3 and PPG 24/26/28/30 11 11 read-write MFTCK2 Settings for operation clock supply and gating of multi-function timer 2 and PPG 16/18/20/22 10 10 read-write MFTCK1 Settings for operation clock supply and gating of multi-function timer 1 and PPG 8/10/12/14 9 9 read-write MFTCK0 Settings for operation clock supply and gating of multi-function timer 0 and PPG 0/2/4/6 8 8 read-write BTMCK3 Settings operation clock supply and gating to base timer 12/13/14/15 3 3 read-write BTMCK2 Settings operation clock supply and gating to base timer 8/9/10/11 2 2 read-write BTMCK1 Settings operation clock supply and gating to base timer 4/5/6/7 1 1 read-write BTMCK0 Settings operation clock supply and gating to base timer 0/1/2/3 0 0 read-write MRST1 Peripheral Function Reset Control Register 1 0x14 32 read-write 0x00000000 0x000F0F0F QDURST3 Reset control of quad counter unit 3 19 19 read-write QDURST2 Reset control of quad counter unit 2 18 18 read-write QDURST1 Reset control of quad counter unit 1 17 17 read-write QDURST0 Reset control of quad counter unit 0 16 16 read-write MFTRST3 Control of multi-function timer 3 and PPG 24/26/28/30 reset control 11 11 read-write MFTRST2 Control of multi-function timer 2 and PPG 16/18/20/22 reset control 10 10 read-write MFTRST1 Control of multi-function timer 1 and PPG 8/10/12/14 reset control 9 9 read-write MFTRST0 Control of multi-function timer 0 and PPG 0/2/4/6 reset control 8 8 read-write BTMRST3 Reset control of base timer 12/13/14/15 3 3 read-write BTMRST2 Reset control of base timer 8/9/10/11 2 2 read-write BTMRST1 Reset control of base timer 4/5/6/7 1 1 read-write BTMRST0 Reset control of base timer 0/1/2/3 0 0 read-write CKEN2 Peripheral Function Clock Control Register 2 0x20 32 read-write 0x03100070 0x13130173 QSPICK 28 28 28 read-write CECCK1 25 25 25 read-write CECCK0 24 24 24 read-write PCRCCK 20 20 20 read-write I2SCK1 17 17 17 read-write I2SCK0 16 16 16 read-write SDCCK Settings for operation clock supply and gating to SD card interface 8 8 read-write CANCK2 Settings for operation clock supply and gating to SD card interface 6 6 read-write CANCK1 Settings for clock supply and gating to CAN controller ch.1 5 5 read-write CANCK0 Settings for clock supply and gating to CAN controller ch.0 4 4 read-write USBCK1 Settings for operation clock supply and gating of USB(function/host) ch.1 1 1 read-write USBCK0 Settings for operation clock supply and gating of USB(function/host) ch.0 0 0 read-write MRST2 Peripheral Function Reset Control Register 2 0x24 32 read-write 0x00000000 0x13130173 QSPIRST 28 28 28 read-write CECRST1 25 25 25 read-write CECRST0 24 24 24 read-write PCRCRST 20 20 20 read-write I2SRST1 17 17 17 read-write I2SRST0 16 16 16 read-write SDCRST Reset control of SD card interface 8 8 read-write CANRST2 Reset control of SD card interface 6 6 read-write CANRST1 Reset control of CAN controller ch.1 5 5 read-write CANRST0 Reset control of CAN controller ch.0 4 4 read-write USBRST1 Reset control of USB (function/host) ch.1 1 1 read-write USBRST0 Reset control of USB (function/host) ch.0 0 0 read-write PLL_CONTROL Main PLL Control PLL_CONTROL 0x4003C800 0x0 0x8 registers SSCTL1 SSCTL1 0x0 32 read-write 0x00000000 0x00000031 SSCTL2 SSCTL2 0x4 32 read-write 0x00000000 0x000003FF EXBUS External Bus Interface EXBUS 0x4003F000 0x0 0x80 registers 0x100 0x14 registers 0x200 0x4 registers 0x300 0x14 registers EXTBUS_ERR 49 MODE0 Mode Register 0 0x0 32 read-write 0x00000000 0x3BFF MOEXEUP select how to set the MOEX width 13 13 read-write MPXCSOF select a CS assertion from the start of accessing to the end of address output 12 12 read-write MPXDOFF select whether or not the address is output to the data lines in multiplex mode 11 11 read-write ALEINV set up the polarity of the ALE signal 9 9 read-write MPXMODE select operation bus mode 8 8 read-write SHRTDOUT select to which idle cycle the write data output is extended 7 7 read-write RDY control the external RDY function 6 6 read-write PAGE NOR Flash memory page access mode 5 5 read-write NAND NAND Flash memory mode 4 4 read-write WEOFF disable the write enable signal (MWEX) operation 3 3 read-write RBMON Read Byte Mask ON 2 2 read-write WDTH specify Data Width 0 1 read-write MODE1 Mode Register 1 0x4 MODE2 Mode Register 2 0x8 MODE3 Mode Register 3 0xC MODE4 Mode Register 4 0x10 MODE5 Mode Register 5 0x14 MODE6 Mode Register 6 0x18 MODE7 Mode Register 7 0x1C TIM0 Timing Register 0 0x20 32 read-write 0x055FF00F 0xFFFFFFFF WIDLC Write Idle Cycle 28 31 read-write WWEC Write Enable Cycle 24 27 read-write WADC Write Address Setup cycle 20 23 read-write WACC Write Access Cycle 16 19 read-write RIDLC Read Idle Cycle 12 15 read-write FRADC First Read Address Cycle 8 11 read-write RADC Read Address Setup cycle 4 7 read-write RACC Read Access Cycle 0 3 read-write TIM1 Timing Register 1 0x24 TIM2 Timing Register 2 0x28 TIM3 Timing Register 3 0x2C TIM4 Timing Register 4 0x30 TIM5 Timing Register 5 0x34 TIM6 Timing Register 6 0x38 TIM7 Timing Register 7 0x3C AREA0 Area Register 0 0x40 32 read-write 0x000F0000 0x007F00FF MASK address mask 16 22 read-write ADDR Address 0 7 read-write AREA1 Area Register 1 0x44 32 read-write 0x000F0010 0x007F00FF MASK address mask 16 22 read-write ADDR Address 0 7 read-write AREA2 Area Register 2 0x48 32 read-write 0x000F0020 0x007F00FF MASK address mask 16 22 read-write ADDR Address 0 7 read-write AREA3 Area Register 3 0x4C 32 read-write 0x000F0030 0x007F00FF MASK address mask 16 22 read-write ADDR Address 0 7 read-write AREA4 Area Register 4 0x50 32 read-write 0x000F0040 0x007F00FF MASK address mask 16 22 read-write ADDR Address 0 7 read-write AREA5 Area Register 5 0x54 32 read-write 0x000F0050 0x007F00FF MASK address mask 16 22 read-write ADDR Address 0 7 read-write AREA6 Area Register 6 0x58 32 read-write 0x000F0060 0x007F00FF MASK address mask 16 22 read-write ADDR Address 0 7 read-write AREA7 Area Register 7 0x5C 32 read-write 0x000F0070 0x007F00FF MASK address mask 16 22 read-write ADDR Address 0 7 read-write ATIM0 ALE Timing Register 0 0x60 32 read-write 0x0000045F 0x0000FFFF ALEW Address Latch Enable Width 8 11 read-write ALES Address Latch Enable Setup cycle 4 7 read-write ALC Address Latch Cycle 0 3 read-write ATIM1 ALE Timing Register 1 0x64 ATIM2 ALE Timing Register 2 0x68 ATIM3 ALE Timing Register 3 0x6C ATIM4 ALE Timing Register 4 0x70 ATIM5 ALE Timing Register 5 0x74 ATIM6 ALE Timing Register 6 0x78 ATIM7 ALE Timing Register 7 0x7C SDMODE SDRAM Mode Register 0x100 32 read-write 0x00001300 0x0001FF37 MSDCLKOFF MSDCLK OFF 16 16 read-write BASEL Bank Address Select 12 15 read-write RASEL Row Address Select 8 11 read-write CASEL Column Address Select 4 5 read-write ROFF Refresh OFF 2 2 read-write PDON Power Down ON 1 1 read-write SDON SDRAM ON 0 0 read-write REFTIM Refresh Timer Register 0x104 32 read-write 0x00000033 0x01FFFFFF PREF Pre-Refresh 24 24 read-write NREF Number of Refresh 16 23 read-write REFC Refresh Count 0 15 read-write PWRDWN Power Down Count Register 0x108 32 read-write 0x00000000 0x0000FFFF PDC Power Down Count 0 15 read-write SDTIM SDRAM Timing Register 0x10C 32 read-write 0x00420000 0x83FFFFF3 BOFF Buffer readout bit 31 31 read-write TDPL Data-in to Precharge Lead Time 24 25 read-write TREFC Refresh Cycle time 20 23 read-write TRAS RAS active time 16 19 read-write TRCD RAS-CAS Delay 12 15 read-write TRP RAS Precharge time 8 11 read-write TRC RAS Cycle time 4 7 read-write CL CAS Latency 0 1 read-write SDCMD SDRAM Command Register 0x110 32 read-write 0x00000000 0x801FFFFF PEND Pend 31 31 read-only SDCKE SDRAM CKE 20 20 read-write SDCS SDRAM Chip Select 19 19 read-write SDRAS SDRAM RAS 18 18 read-write SDCAS SDRAM CAS 17 17 read-write SDWE SDRAM Write Enable 16 16 read-write SDAD SDRAM ADress 0 15 read-write MEMCERR Memory Controller Register 0x200 32 read-write 0x00000000 0x0000000F SDION SDRAM error Interrupt ON 3 3 read-write SFION SRAM/Flash error Interrupt ON 2 2 read-write SDER SDRAM Error 1 1 read-write SFER SRAM/Flash Error 0 0 read-write DCLKR Division Clock Register 0x300 32 read-write 0x0000000F 0x0000001F MCLKON MCLK ON 4 4 read-write MDIV MCLK Division Ratio Setup 0 3 read-write EST Error Status Register 0x304 32 read-only 0x00000000 0x00000001 WERR WERR 0 0 read-only WEAD Write Error Address Register 0x308 32 read-only 0x00000000 0xFFFFFFFF ADDR ADDR 0 31 read-only ESCLR Error Status Clear Register 0x30C 32 write-only 0x00000001 0x00000001 WERRCLR Write Error Clear 0 0 write-only AMODE Access Mode Register 0x310 32 read-write 0x00000001 0x00000001 WAEN WAEN 0 0 read-write USBETHERCLK USB/Ethernet Clock USBETHERCLK 0x40036000 0x0 0x1 registers 0x4 0x1 registers 0x8 0x1 registers 0xC 0x1 registers 0x10 0x1 registers 0x14 0x1 registers 0x18 0x1 registers 0x1C 0x1 registers 0x20 0x1 registers 0x24 0x1 registers 0x28 0x1 registers 0x2C 0x1 registers 0x30 0x1 registers 0x34 0x1 registers UCCR USB/Ethernet-PLL Clock Control Register 0x00 8 read-write 0x00 0x7F ECSEL1 Ethernet clock selection bit 1 7 7 read-write ECSEL0 Ethernet clock selection bit 0 6 6 read-write ECEN Ethernet clock output enable bit 4 4 read-write UCEN1 USB1 clock output enable bit 3 3 read-write UCSEL1 USB1 clock selection bit 2 2 read-write UCSEL0 USB0 clock selection bit 1 1 read-write UCEN0 USB0 clock output enable bit 0 0 read-write UPCR1 USB/Ethernet-PLL Control Register 1 0x04 8 read-write 0x00 0x03 UPINC USB/Ethernet-PLL input clock selection bit 1 1 read-write UPLLEN USB/Ethernet-PLL oscillation enable bit 0 0 read-write UPCR2 USB/Ethernet-PLL Control Register 2 0x08 8 read-write 0x00 0x07 UPOWT USB/Ethernet-PLL oscillation stabilization wait time setting bit 0 2 read-write UPCR3 USB/Ethernet-PLL Control Register 3 0x0C 8 read-write 0x00 0x1F UPLLK Frequency division ratio (K) setting bit of the USB/Ethernet-PLL clock 0 4 read-write UPCR4 USB/Ethernet-PLL Control Register 4 0x10 8 read-write 0x3B 0x7F UPLLN Frequency division ratio (N) setting bit of the USB/Ethernet-PLL clock 0 6 read-write UP_STR USB/Ethernet-PLL Status Register 0x14 8 read-only 0x00 0x01 UPRDY USB/Ethernet-PLL oscillation stabilization bit 0 0 read-only UPINT_ENR USB/Ethernet-PLL Interrupt Source Enable Register 0x18 8 read-write 0x00 0x01 UPCSE USB/Ethernet-PLL oscillation stabilization wait complete interrupt enable bit 0 0 read-write UPINT_CLR USB/Ethernet-PLL Interrupt Source Clear Register 0x1C 8 write-only 0x00 0x01 UPCSC USB/Ethernet-PLL oscillation stabilization interrupt source clear bit 0 0 write-only UPINT_STR ERROR!!!!!!!!!!!!!!!!!!!! 0x20 8 read-only 0x00 0x01 UPCSI ERROR!!!!!!!!!!!!!!!!!!!! 0 0 read-only UPCR5 ERROR!!!!!!!!!!!!!!!!!!!! 0x24 8 read-write 0x04 0x0F UPLLM ERROR!!!!!!!!!!!!!!!!!!!! 0 3 read-write UPCR6 ERROR!!!!!!!!!!!!!!!!!!!! 0x28 8 read-write 0x02 0x0F UBSR ERROR!!!!!!!!!!!!!!!!!!!! 0 3 read-write UPCR7 ERROR!!!!!!!!!!!!!!!!!!!! 0x2C 8 read-write 0x00 0x01 EPLLEN ERROR!!!!!!!!!!!!!!!!!!!! 0 0 read-write USBEN0 ERROR!!!!!!!!!!!!!!!!!!!! 0x30 8 read-write 0x00 0x01 USBEN0 ERROR!!!!!!!!!!!!!!!!!!!! 0 0 read-write USBEN1 ERROR!!!!!!!!!!!!!!!!!!!! 0x34 8 read-write 0x00 0x01 USBEN1 ERROR!!!!!!!!!!!!!!!!!!!! 0 0 read-write USB0 USB0 Function USB0 0x40040000 0x2100 0x2 registers 0x2104 0x2 registers 0x2108 0x2 registers 0x210C 0x2 registers 0x2110 0x2 registers 0x2114 0x2 registers 0x2118 0x2 registers 0x211C 0x1 registers 0x2120 0x2 registers 0x2124 0x2 registers 0x2128 0x2 registers 0x212C 0x2 registers 0x2130 0x2 registers 0x2134 0x2 registers 0x2138 0x2 registers 0x213C 0x2 registers 0x2140 0x2 registers 0x2144 0x2 registers 0x2148 0x2 registers 0x214C 0x2 registers 0x2150 0x2 registers 0x2154 0x2 registers 0x2158 0x2 registers 0x215C 0x2 registers 0x2160 0x2 registers 0x2164 0x2 registers 0x2168 0x2 registers 0x216C 0x2 registers 0x2170 0x2 registers 0x2174 0x2 registers USB0 78 USB0_HOST 79 UDCC UDC Control Register 0x2120 16 read-write 0x00A0 0x00FB RST Function Reset bit 7 7 read-write RESUM Resume Setting bit 6 6 read-write HCONX Host Connection bit 5 5 read-write USTP USB Operating Clock Stop bit 4 4 read-write STALCLREN Endpoint 1 to 5 STAL bit Clear Select bit 3 3 read-write RFBK Data Toggle Mode Select bit 1 1 read-write PWC Power Control bit 0 0 read-write EP0C EP0 Control Register 0x2124 16 read-write 0x0040 0x027F STAL Endpoint 0 Stall Setting bit 9 9 read-write PKS0 Packet Size Endpoint 0 Setting bits 0 6 read-write EP1C EP1 Control Register 0x2128 16 read-write 0x6100 0xFFFF EPEN Endpoint Enable bit 15 15 read-write TYPE Endpoint Transfer Type Select bits 13 14 read-write DIR Endpoint Transfer Direction Select bit 12 12 read-write DMAE DMA Automatic Transfer Enable bit 11 11 read-write NULE Null Automatic Transfer Enable bit 10 10 read-write STAL Endpoint Stall Setting bit 9 9 read-write PKS Packet Size Setting bits 0 8 read-write EP2C EP2 Control Register 0x212C 16 read-write 0x6040 0xFE7F EPEN Endpoint Enable bit 15 15 read-write TYPE Endpoint Transfer Type Select bits 13 14 read-write DIR Endpoint Transfer Direction Select bit 12 12 read-write DMAE DMA Automatic Transfer Enable bit 11 11 read-write NULE Null Automatic Transfer Enable bit 10 10 read-write STAL Endpoint Stall Setting bit 9 9 read-write PKS Packet Size Setting bits 0 6 read-write EP3C EP3 Control Register 0x2130 EP4C EP4 Control Register 0x2134 EP5C EP5 Control Register 0x2138 TMSP Time Stamp Register 0x213C 16 read-only 0x0000 0x07FF TMSP Time Stamp bits 0 10 read-only UDCS UDC Status Register 0x2140 8 read-write 0x00 0x3F SUSP Suspend detection bit 5 5 read-write SOF SOF Detection bit 4 4 read-write BRST Bus Reset Detection bit 3 3 read-write WKUP Wake-up Detection bit 2 2 read-write SETP Setup Stage Detection bit 1 1 read-write CONF Configuration Detection bit 0 0 read-write UDCIE UDC Interrupt Enable Register 0x2141 8 read-write 0x00 0x3F SUSPIE Suspend Interrupt Enable bit 5 5 read-write SOFIE SOF Reception Interrupt Enable bit 4 4 read-write BRSTIE Bus Reset Enable bit 3 3 read-write WKUPIE Wake-up Interrupt Enable bit 2 2 read-write CONFN Configuration Number Indication bit 1 1 read-only CONFIE Configuration Interrupt Enable bit 0 0 read-write EP0IS EP0I Status Register 0x2144 16 read-write 0x8400 0xC400 BFINI Send Buffer Initialization bit 15 15 read-write DRQIIE Send Data Interrupt Enable bit 14 14 read-write DRQI Send/Receive Data Interrupt Request bit 10 10 read-write EP0OS EP0O Status Register 0x2148 16 read-write 0x8000 0xE67F BFINI Receive Buffer Initialization bit 15 15 read-write DRQOIE Receive Data Interrupt Enable bit 14 14 read-write SPKIE Short Packet Interrupt Enable bit 13 13 read-write DRQO Receive Data Interrupt Request bit 10 10 read-write SPK Short Packet Interrupt Request bit 9 9 read-write SIZE Packet Size Indication bit 0 6 read-only EP1S EP1 Status Register 0x214C 16 read-write 0x8000 0xEFFF BFINI Send/Receive Buffer Initialization bit 15 15 read-write DRQIE Packet Transfer Interrupt Enable bit 14 14 read-write SPKIE Short Packet Interrupt Enable bit 13 13 read-write BUSY Busy Flag bit 11 11 read-only DRQ Packet Transfer Interrupt Request bit 10 10 read-write SPK Short Packet Interrupt Request bit 9 9 read-write SIZE packet SIZE 0 8 read-only EP2S EP2 Status Register 0x2150 16 read-write 0x8000 0xEFFF BFINI Send/Receive Buffer Initialization bit 15 15 read-write DRQIE Packet Transfer Interrupt Enable bit 14 14 read-write SPKIE Short Packet Interrupt Enable bit 13 13 read-write BUSY Busy Flag bit 11 11 read-only DRQ Packet Transfer Interrupt Request bit 10 10 read-write SPK Short Packet Interrupt Request bit 9 9 read-write SIZE packet SIZE 0 6 read-only EP3S EP3 Status Register 0x2154 EP4S EP4 Status Register 0x2158 EP5S EP5 Status Register 0x215C EP0DT EP0 Data Register 0x2160 16 read-write 0x0000 0x0000 BFDT Endpoint Send/Receive Buffer Data 0 15 read-write EP1DT EP1 Data Register 0x2164 EP2DT EP2 Data Register 0x2168 EP3DT EP3 Data Register 0x216C EP4DT EP4 Data Register 0x2170 EP5DT EP5 Data Register 0x2174 HCNT Host Control Register 0x2100 16 read-write 0x0100 0x07FF SOFSTEP SOF interrupt occurrence selection bit 10 10 read-write CANCEL token cancellation enable bit 9 9 read-write RETRY retry enable bit 8 8 read-write RWKIRE resume interrupt enable bit 7 7 read-write URIRE bus reset interrupt enable bit 6 6 read-write CMPIRE token completion interrupt enable bit 5 5 read-write CNNIRE device connection detection interrupt enable bit 4 4 read-write DIRE device disconnection detection interrupt enable bit 3 3 read-write SOFIRE SOF interrupt enable bit 2 2 read-write URST bus reset bit 1 1 read-write HOST host mode bit 0 0 read-write HIRQ Host Interrupt Register 0x2104 8 read-write 0x00 0xBF TCAN token cancellation flag 7 7 read-write RWKIRQ remote Wake-up end flag 5 5 read-write URIRQ bus reset end flag 4 4 read-write CMPIRQ token completion flag 3 3 read-write CNNIRQ device connection detection flag 2 2 read-write DIRQ device disconnection detection flag 1 1 read-write SOFIRQ SOF starting flag 0 0 read-write HERR Host Error Status Register 0x2105 8 read-write 0x03 0xFF LSTSOF lost SOF flag 7 7 read-write RERR receive error flag 6 6 read-write TOUT timeout flag 5 5 read-write CRC CRC error flag 4 4 read-write TGERR toggle error flag 3 3 read-write STUFF stuffing error flag 2 2 read-write HS handshake status flags 0 1 read-write HSTATE Host Status Register 0x2108 8 read-write 0x12 0x3F ALIVE specify the keep-alive function in the low-speed mode 5 5 read-write CLKSEL USB operation clock selection bit 4 4 read-write SOFBUSY SOF busy flag 3 3 read-write SUSP suspend setting bit 2 2 read-write TMODE transmission mode flag 1 1 read-only CSTAT connection status flag 0 0 read-only HFCOMP SOF Interrupt Frame Compare Register 0x2109 8 read-write 0x00 0xFF FRAMECOMP frame compare data 0 7 read-write HRTIMER Retry Timer Setup Register 0x210C 16 read-write 0x0000 0xFFFF RTIMER1 retry timer setting 1 8 15 read-write RTIMER0 retry timer setting 0 0 7 read-write HRTIMER2 Retry Timer Setup Register 2 0x2110 8 read-write 0x00 0x03 RTIMER2 retry timer setting 2 0 1 read-write HADR Host Address Register 0x2111 8 read-write 0x00 0x7F ADDRESS Host Address 0 6 read-write HEOF EOF Setup Register 0x2114 16 read-write 0x0000 0x3FFF EOF1 End Frame 1 8 13 read-write EOF0 End Frame 0 0 7 read-write HFRAME Frame Setup Register 0x2118 16 read-write 0x0000 0x07FF FRAME1 Frame Setup 1 8 10 read-write FRAME0 Frame Setup 0 0 7 read-write HTOKEN Host Token Endpoint Register 0x211C 8 read-write 0x00 0xFF TGGL toggle bit 7 7 read-write TKNEN token enable bits 4 6 read-write ENDPT endpoint bits 0 3 read-write USB1 0x40050000 USB1_HDMICEC0 113 USB1_HOST_HDMICEC1 114 DMAC DMAC Registers DMAC 0x40060000 0x0 0x4 registers 0x10 0x80 registers DMAC0 83 DMAC1 84 DMAC2 85 DMAC3 86 DMAC4 87 DMAC5 88 DMAC6 89 DMAC7 90 DMACR Entire DMAC Configuration Register 0x0 32 read-write 0x00000000 0xDF000000 DE DMA Enable (all-channel operation enable bit) 31 31 read-write DS DMA Stop 30 30 read-write PR Priority Rotation 28 28 read-write DH DMA Halt (All-channel pause bit) 24 27 read-write DMACA0 Configuration A Register 0x10 32 read-write 0x00000000 0xFF9FFFFF EB Enable bit (individual-channel operation enable bit) 31 31 read-write PB Pause bit (individual-channel pause bit) 30 30 read-write ST Software Trigger 29 29 read-write IS Input Select 23 28 read-write BC Block Count 16 19 read-write TC Transfer Count 0 15 read-write DMACB0 Configuration B Register 0x14 32 read-write 0x00000000 0x3FFF0001 MS Mode Select 28 29 read-write TW Transfer Width 26 27 read-write FS Fixed Source 25 25 read-write FD Fixed Destination 24 24 read-write RC Reload Count (BC/TC reload) 23 23 read-write RS Reload Source 22 22 read-write RD Reload Destination 21 21 read-write EI Error Interrupt (unsuccessful transfer completion interrupt enable) 20 20 read-write CI Completion Interrupt (successful transfer completion interrupt enable) 19 19 read-write SS Stop Status (stop status notification) 16 18 read-write EM Enable bit Mask (EB bit clear mask) 0 0 read-write DMACSA0 Transfer Source Address Register 0x18 32 read-write 0x00000000 0xFFFFFFFF DMACDA0 Transfer Destination Address Register 0x1C 32 read-write 0x00000000 0xFFFFFFFF DMACA1 Configuration A Register 1 0x20 DMACB1 Configuration B Register 1 0x24 DMACSA1 Transfer Source Address Register 1 0x28 DMACDA1 Transfer Destination Address Register 1 0x2C DMACA2 Configuration A Register 2 0x30 DMACB2 Configuration B Register 2 0x34 DMACSA2 Transfer Source Address Register 2 0x38 DMACDA2 Transfer Destination Address Register 2 0x3C DMACA3 Configuration A Register 3 0x40 DMACB3 Configuration B Register 3 0x44 DMACSA3 Transfer Source Address Register 3 0x48 DMACDA3 Transfer Destination Address Register 3 0x4C DMACA4 Configuration A Register 4 0x50 DMACB4 Configuration B Register 4 0x54 DMACSA4 Transfer Source Address Register 4 0x58 DMACDA4 Transfer Destination Address Register 4 0x5C DMACA5 Configuration A Register 5 0x60 DMACB5 Configuration B Register 5 0x64 DMACSA5 Transfer Source Address Register 5 0x68 DMACDA5 Transfer Destination Address Register 5 0x6C DMACA6 Configuration A Register 6 0x70 DMACB6 Configuration B Register 6 0x74 DMACSA6 Transfer Source Address Register 6 0x78 DMACDA6 Transfer Destination Address Register 6 0x7C DMACA7 Configuration A Register 7 0x80 DMACB7 Configuration B Register 7 0x84 DMACSA7 Transfer Source Address Register 7 0x88 DMACDA7 Transfer Destination Address Register 7 0x8C DSTC DSTC registers DSTC 0x40061000 0x0 0xB0 registers DSTC 91 DESTP Descriptor top address Register 0x0 32 read-write 0x00000000 0xFFFFFFFF HWDESP Hardware DES pointer Register 0x4 32 read-write 0x00000000 0x3FFF00FF HWDESP HWDESP 16 29 read-write CHANNEL CHANNEL 0 7 read-write CMD Command Register 0x8 8 read-write 0x01 0xFF CFG Configuration Register 0x9 8 read-write 0x40 0x7F SWPR Software transfer priority 4 6 read-write ESTE Error stop enable 3 3 read-write RBDIS Read skip buffer disable 2 2 read-write ERINTE Error interrupt enable 1 1 read-write SWINTE Software interrupt enable 0 0 read-write SWTR Software trigger Register 0xA 16 read-write 0x0000 0xFFFF SWST Software status 15 15 read-only SWREQ Software request 14 14 read-only SWDESP Software DES pointer 0 13 read-write MONERS MONERS Register 0xC 32 read-write 0x00000000 0x3FFFFF5F EDESP Error DES pointer 16 29 read-only ECH Error hardware channel 8 15 read-only EHS Error hardware software 6 6 read-only ESTOP Error stop 4 4 read-only DER Double error 3 3 read-only EST Error status 0 2 read-only DREQENB0 DMA request enable Register 0 0x10 32 read-write 0x00000000 0xFFFFFFFF DREQENB1 DMA request enable Register 1 0x14 DREQENB2 DMA request enable Register 2 0x18 DREQENB3 DMA request enable Register 3 0x1C DREQENB4 DMA request enable Register 4 0x20 DREQENB5 DMA request enable Register 5 0x24 DREQENB6 DMA request enable Register 6 0x28 DREQENB7 DMA request enable Register 7 0x2C HWINT0 Hardware transfer interrupt Register 0 0x30 32 read-write 0x00000000 0xFFFFFFFF HWINT1 Hardware transfer interrupt Register 1 0x34 HWINT2 Hardware transfer interrupt Register 2 0x38 HWINT3 Hardware transfer interrupt Register 3 0x3C HWINT4 Hardware transfer interrupt Register 4 0x40 HWINT5 Hardware transfer interrupt Register 5 0x44 HWINT6 Hardware transfer interrupt Register 6 0x48 HWINT7 Hardware transfer interrupt Register 7 0x4C HWINTCLR0 Hardware transfer interrupt clear Register 0 0x50 32 read-write 0x00000000 0xFFFFFFFF HWINTCLR1 Hardware transfer interrupt clear Register 1 0x54 HWINTCLR2 Hardware transfer interrupt clear Register 2 0x58 HWINTCLR3 Hardware transfer interrupt clear Register 3 0x5C HWINTCLR4 Hardware transfer interrupt clear Register 4 0x60 HWINTCLR5 Hardware transfer interrupt clear Register 5 0x64 HWINTCLR6 Hardware transfer interrupt clear Register 6 0x68 HWINTCLR7 Hardware transfer interrupt clear Register 7 0x6C DQMSK0 DMA request mask Register 0 0x70 32 read-write 0x00000000 0xFFFFFFFF DQMSK1 DMA request mask Register 1 0x74 DQMSK2 DMA request mask Register 2 0x78 DQMSK3 DMA request mask Register 3 0x7C DQMSK4 DMA request mask Register 4 0x80 DQMSK5 DMA request mask Register 5 0x84 DQMSK6 DMA request mask Register 6 0x88 DQMSK7 DMA request mask Register 7 0x8C DQMSKCLR0 DMA request mask clear Register 0 0x90 32 read-write 0x00000000 0xFFFFFFFF DQMSKCLR1 DMA request mask clear Register 1 0x94 DQMSKCLR2 DMA request mask clear Register 2 0x98 DQMSKCLR3 DMA request mask clear Register 3 0x9C DQMSKCLR4 DMA request mask clear Register 4 0xA0 DQMSKCLR5 DMA request mask clear Register 5 0xA4 DQMSKCLR6 DMA request mask clear Register 6 0xA8 DQMSKCLR7 DMA request mask clear Register 7 0xAC CANPRES CAN Prescaler Register CANPRES 0x40037000 0x0 0x1 registers CANPRE CAN Prescaler Register 0x0 8 read-write 0x0B 0x0F CANPRE CAN prescaler setting bits 0 3 read-write CAN0 CAN0 Registers CAN0 0x40062000 0x0 0xE registers 0x10 0xE registers 0x20 0x8 registers 0x30 0x8 registers 0x40 0xE registers 0x50 0x8 registers 0x60 0x8 registers 0x80 0x4 registers 0x90 0x4 registers 0xA0 0x4 registers 0xB0 0x4 registers CAN0 80 CTRLR CAN Control Register 0x0 16 read-write 0x0001 0x00EF TEST Test mode enable bit 7 7 read-write CCE Bit Timing Register write enable bit 6 6 read-write DAR Automatic retransmission disable bit 5 5 read-write EIE Error interrupt code enable bit 3 3 read-write SIE Status interrupt code enable bit 2 2 read-write IE Interrupt enable bit 1 1 read-write INIT Initialization bit 0 0 read-write STATR CAN Status Register 0x2 16 read-write 0x0000 0x00FF BOFF Busoff bit 7 7 read-only EWARN Warning bit 6 6 read-only EPASS Error passive bit 5 5 read-only RXOK Successful message reception bit 4 4 read-write TXOK Successful message transmission bit 3 3 read-write LEC Last error code bits 0 2 read-write ERRCNT CAN Error Counter 0x4 16 read-only 0x0000 0x0000 RP Receive error passive indication 15 15 read-only REC Receive error counter 8 14 read-only TEC Send error counter 0 7 read-only BTR CAN Bit Timing Register 0x6 16 read-write 0x2301 0x7FFF TSEG2 Time segment 2 setting bits 12 14 read-write TSEG1 Time segment 1 setting bits 8 11 read-write SJW Resynchronization jump width setting bits 6 7 read-write BRP Baud rate prescaler setting bits 0 5 read-write INTR CAN Interrupt Register 0x8 16 read-only 0x0000 0xFFFF INTID Interrupt Code 0 15 read-only TESTR CAN Test Register 0xA 16 read-write 0x0000 0x00F4 RX Rx pin monitor bit 7 7 read-only TX TX pin control bit 5 6 read-write LBACK Loop back mode 4 4 read-write SILENT Silent mode 3 3 read-write BASIC Basic mode 2 2 read-write BRPER CAN Prescaler Extension Register 0xC 16 read-write 0x0000 0x000F BRPE Baud rate prescaler extension bit 0 3 read-write IF1CREQ IF1 Command Request Register 0x10 16 read-write 0x0001 0x80FF BUSY Busy flag bit 15 15 read-write MESSAGENUMBER Message number 0 7 read-write IF1CMSK IF1 Command Mask Register 0x12 16 read-write 0x0000 0x00FF WRRD Writing or reading control bit 7 7 read-write MASK Mask data update bit 6 6 read-write ARB Arbitration data update bit 5 5 read-write CONTROL Control data update bit 4 4 read-write CIP Interrupt clear bit 3 3 read-write NEWDAT Message transmission request bit 2 2 read-write DATAA Data 0-3 update bit 1 1 read-write DATAB Data 4-7 update bit 0 0 read-write IF1MSK1 IF1 Mask Registers 1 0x14 16 read-write 0xFFFF 0xFFFF MSK15 Msk15 15 15 read-write MSK14 Msk14 14 14 read-write MSK13 Msk13 13 13 read-write MSK12 Msk12 12 12 read-write MSK11 Msk11 11 11 read-write MSK10 Msk10 10 10 read-write MSK9 Msk9 9 9 read-write MSK8 Msk8 8 8 read-write MSK7 Msk7 7 7 read-write MSK6 Msk6 6 6 read-write MSK5 Msk5 5 5 read-write MSK4 Msk4 4 4 read-write MSK3 Msk3 3 3 read-write MSK2 Msk2 2 2 read-write MSK1 Msk1 1 1 read-write MSK0 Msk0 0 0 read-write IF1MSK2 IF1 Mask Registers 2 0x16 16 read-write 0xFFFF 0xDFFF MXTD MXtd 15 15 read-write MDIR MDir 14 14 read-write MSK28 Msk28 12 12 read-write MSK27 Msk27 11 11 read-write MSK26 Msk26 10 10 read-write MSK25 Msk25 9 9 read-write MSK24 Msk24 8 8 read-write MSK23 Msk23 7 7 read-write MSK22 Msk22 6 6 read-write MSK21 Msk21 5 5 read-write MSK20 Msk20 4 4 read-write MSK19 Msk19 3 3 read-write MSK18 Msk18 2 2 read-write MSK17 Msk17 1 1 read-write MSK16 Msk16 0 0 read-write IF1ARB1 IF1 Arbitration Registers 1 0x18 16 read-write 0x0000 0xFFFF ID15 ID15 15 15 read-write ID14 ID14 14 14 read-write ID13 ID13 13 13 read-write ID12 ID12 12 12 read-write ID11 ID11 11 11 read-write ID10 ID10 10 10 read-write ID9 ID9 9 9 read-write ID8 ID8 8 8 read-write ID7 ID7 7 7 read-write ID6 ID6 6 6 read-write ID5 ID5 5 5 read-write ID4 ID4 4 4 read-write ID3 ID3 3 3 read-write ID2 ID2 2 2 read-write ID1 ID1 1 1 read-write ID0 ID0 0 0 read-write IF1ARB2 IF1 Arbitration Registers 2 0x1A 16 read-write 0x0000 0xFFFF MSGVAL MsgVal 15 15 read-write XTD Xtd 14 14 read-write DIR Dir 13 13 read-write ID28 ID28 12 12 read-write ID27 ID27 11 11 read-write ID26 ID26 10 10 read-write ID25 ID25 9 9 read-write ID24 ID24 8 8 read-write ID23 ID23 7 7 read-write ID22 ID22 6 6 read-write ID21 ID21 5 5 read-write ID20 ID20 4 4 read-write ID19 ID19 3 3 read-write ID18 ID18 2 2 read-write ID17 ID17 1 1 read-write ID16 ID16 0 0 read-write IF1MCTR IF1 Message Control Register 0x1C 16 read-write 0x0000 0xFF8F NEWDAT NewDat 15 15 read-write MSGLST MsgLst 14 14 read-write INTPND IntPnd 13 13 read-write UMASK UMask 12 12 read-write TXIE TxIE 11 11 read-write RXIE RxIE 10 10 read-write RMTEN RmtEn 9 9 read-write TXRQST TxRqst 8 8 read-write EOB EoB 7 7 read-write DLC DLC 0 3 read-write IF1DTA1_L IF1 Data Registers A1 0x20 16 read-write 0x0000 0xFF8F DATA_1_ Data(1) 8 15 read-write DATA_0_ Data(0) 0 7 read-write IF1DTA2_L IF1 Data Registers A2 0x22 16 read-write 0x0000 0xFFFF DATA_3_ Data(3) 8 15 read-write DATA_2_ Data(2) 0 7 read-write IF1DTB1_L IF1 Data Registers B1 0x24 16 read-write 0x0000 0xFFFF DATA_5_ Data(5) 8 15 read-write DATA_4_ Data(4) 0 7 read-write IF1DTB2_L IF1 Data Registers B2 0x26 16 read-write 0x0000 0xFFFF DATA_7_ Data(7) 8 15 read-write DATA_6_ Data(6) 0 7 read-write IF1DTA2_B IF1 Data Registers A2 0x30 16 read-write 0x0000 0xFFFF DATA_2_ Data(2) 8 15 read-write DATA_3_ Data(3) 0 7 read-write IF1DTA1_B IF1 Data Registers A1 0x32 16 read-write 0x0000 0xFFFF DATA_0_ Data(0) 8 15 read-write DATA_1_ Data(1) 0 7 read-write IF1DTB2_B IF1 Data Registers B2 0x34 16 read-write 0x0000 0xFFFF DATA_6_ Data(6) 8 15 read-write DATA_7_ Data(7) 0 7 read-write IF1DTB1_B IF1 Data Registers B1 0x36 16 read-write 0x0000 0xFFFF DATA_4_ Data(4) 8 15 read-write DATA_5_ Data(5) 0 7 read-write IF2CREQ IF2 Command Request Register 0x40 16 read-write 0x0001 0x80FF BUSY Busy flag bit 15 15 read-write MESSAGENUMBER Message number 0 7 read-write IF2CMSK IF2 Command Mask Register 0x42 16 read-write 0x0000 0x00FF WRRD Writing or reading control bit 7 7 read-write MASK Mask data update bit 6 6 read-write ARB Arbitration data update bit 5 5 read-write CONTROL Control data update bit 4 4 read-write CIP Interrupt clear bit 3 3 read-write NEWDAT Message transmission request bit 2 2 read-write DATAA Data 0-3 update bit 1 1 read-write DATAB Data 4-7 update bit 0 0 read-write IF2MSK1 IF2 Mask Registers 1 0x44 16 read-write 0xFFFF 0xFFFF MSK15 Msk15 15 15 read-write MSK14 Msk14 14 14 read-write MSK13 Msk13 13 13 read-write MSK12 Msk12 12 12 read-write MSK11 Msk11 11 11 read-write MSK10 Msk10 10 10 read-write MSK9 Msk9 9 9 read-write MSK8 Msk8 8 8 read-write MSK7 Msk7 7 7 read-write MSK6 Msk6 6 6 read-write MSK5 Msk5 5 5 read-write MSK4 Msk4 4 4 read-write MSK3 Msk3 3 3 read-write MSK2 Msk2 2 2 read-write MSK1 Msk1 1 1 read-write MSK0 Msk0 0 0 read-write IF2MSK2 IF2 Mask Registers 2 0x46 16 read-write 0xDFFF 0xFFFF MXTD MXtd 15 15 read-write MDIR MDir 14 14 read-write MSK28 Msk28 12 12 read-write MSK27 Msk27 11 11 read-write MSK26 Msk26 10 10 read-write MSK25 Msk25 9 9 read-write MSK24 Msk24 8 8 read-write MSK23 Msk23 7 7 read-write MSK22 Msk22 6 6 read-write MSK21 Msk21 5 5 read-write MSK20 Msk20 4 4 read-write MSK19 Msk19 3 3 read-write MSK18 Msk18 2 2 read-write MSK17 Msk17 1 1 read-write MSK16 Msk16 0 0 read-write IF2ARB1 IF2 Arbitration Registers 1 0x48 16 read-write 0x0000 0xFFFF ID15 ID15 15 15 read-write ID14 ID14 14 14 read-write ID13 ID13 13 13 read-write ID12 ID12 12 12 read-write ID11 ID11 11 11 read-write ID10 ID10 10 10 read-write ID9 ID9 9 9 read-write ID8 ID8 8 8 read-write ID7 ID7 7 7 read-write ID6 ID6 6 6 read-write ID5 ID5 5 5 read-write ID4 ID4 4 4 read-write ID3 ID3 3 3 read-write ID2 ID2 2 2 read-write ID1 ID1 1 1 read-write ID0 ID0 0 0 read-write IF2ARB2 IF2 Arbitration Registers 2 0x4A 16 read-write 0x0000 0xFFFF MSGVAL MsgVal 15 15 read-write XTD Xtd 14 14 read-write DIR Dir 13 13 read-write ID28 ID28 12 12 read-write ID27 ID27 11 11 read-write ID26 ID26 10 10 read-write ID25 ID25 9 9 read-write ID24 ID24 8 8 read-write ID23 ID23 7 7 read-write ID22 ID22 6 6 read-write ID21 ID21 5 5 read-write ID20 ID20 4 4 read-write ID19 ID19 3 3 read-write ID18 ID18 2 2 read-write ID17 ID17 1 1 read-write ID16 ID16 0 0 read-write IF2MCTR IF2 Message Control Register 0x4C 16 read-write 0x0000 0xFF8F NEWDAT NewDat 15 15 read-write MSGLST MsgLst 14 14 read-write INTPND IntPnd 13 13 read-write UMASK UMask 12 12 read-write TXIE TxIE 11 11 read-write RXIE RxIE 10 10 read-write RMTEN RmtEn 9 9 read-write TXRQST TxRqst 8 8 read-write EOB EoB 7 7 read-write DLC DLC 0 3 read-write IF2DTA1_L IF2 Data Registers A1 0x50 16 read-write 0x0000 0xFFFF DATA_1_ Data(1) 8 15 read-write DATA_0_ Data(0) 0 7 read-write IF2DTA2_L IF2 Data Registers A2 0x52 16 read-write 0x0000 0xFFFF DATA_3_ Data(3) 8 15 read-write DATA_2_ Data(2) 0 7 read-write IF2DTB1_L IF2 Data Registers B1 0x54 16 read-write 0x0000 0xFFFF DATA_5_ Data(5) 8 15 read-write DATA_4_ Data(4) 0 7 read-write IF2DTB2_L IF2 Data Registers B2 0x56 16 read-write 0x0000 0xFFFF DATA_7_ Data(7) 8 15 read-write DATA_6_ Data(6) 0 7 read-write IF2DTA2_B IF2 Data Registers A2 0x60 16 read-write 0x0000 0xFFFF DATA_2_ Data(2) 8 15 read-write DATA_3_ Data(3) 0 7 read-write IF2DTA1_B IF2 Data Registers A1 0x62 16 read-write 0x0000 0xFFFF DATA_0_ Data(0) 8 15 read-write DATA_1_ Data(1) 0 7 read-write IF2DTB2_B IF2 Data Registers B2 0x64 16 read-write 0x0000 0xFFFF DATA_6_ Data(6) 8 15 read-write DATA_7_ Data(7) 0 7 read-write IF2DTB1_B IF2 Data Registers B1 0x66 16 read-write 0x0000 0xFFFF DATA_4_ Data(4) 8 15 read-write DATA_5_ Data(5) 0 7 read-write TREQR1 CAN Transmit Request Registers 1 0x80 16 read-only 0x0000 0xFFFF TXRQST16 Bit15 of TREQR1 15 15 read-only TXRQST15 Bit14 of TREQR1 14 14 read-only TXRQST14 Bit13 of TREQR1 13 13 read-only TXRQST13 Bit12 of TREQR1 12 12 read-only TXRQST12 Bit11 of TREQR1 11 11 read-only TXRQST11 Bit10 of TREQR1 10 10 read-only TXRQST10 Bit9 of TREQR1 9 9 read-only TXRQST9 Bit8 of TREQR1 8 8 read-only TXRQST8 Bit7 of TREQR1 7 7 read-only TXRQST7 Bit6 of TREQR1 6 6 read-only TXRQST6 Bit5 of TREQR1 5 5 read-only TXRQST5 Bit4 of TREQR1 4 4 read-only TXRQST4 Bit3 of TREQR1 3 3 read-only TXRQST3 Bit2 of TREQR1 2 2 read-only TXRQST2 Bit1 of TREQR1 1 1 read-only TXRQST1 Bit0 of TREQR1 0 0 read-only TREQR2 CAN Transmit Request Registers 2 0x82 16 read-only 0x0000 0xFFFF TXRQST32 Bit15 of TREQR2 15 15 read-only TXRQST31 Bit14 of TREQR2 14 14 read-only TXRQST30 Bit13 of TREQR2 13 13 read-only TXRQST29 Bit12 of TREQR2 12 12 read-only TXRQST28 Bit11 of TREQR2 11 11 read-only TXRQST27 Bit10 of TREQR2 10 10 read-only TXRQST26 Bit9 of TREQR2 9 9 read-only TXRQST25 Bit8 of TREQR2 8 8 read-only TXRQST24 Bit7 of TREQR2 7 7 read-only TXRQST23 Bit6 of TREQR2 6 6 read-only TXRQST22 Bit5 of TREQR2 5 5 read-only TXRQST21 Bit4 of TREQR2 4 4 read-only TXRQST20 Bit3 of TREQR2 3 3 read-only TXRQST19 Bit2 of TREQR2 2 2 read-only TXRQST18 Bit1 of TREQR2 1 1 read-only TXRQST17 Bit0 of TREQR2 0 0 read-only NEWDT1 CAN New Data Registers 1 0x90 16 read-only 0x0000 0xFFFF NEWDAT16 Bit15 of NEWDT1 15 15 read-only NEWDAT15 Bit14 of NEWDT1 14 14 read-only NEWDAT14 Bit13 of NEWDT1 13 13 read-only NEWDAT13 Bit12 of NEWDT1 12 12 read-only NEWDAT12 Bit11 of NEWDT1 11 11 read-only NEWDAT11 Bit10 of NEWDT1 10 10 read-only NEWDAT10 Bit9 of NEWDT1 9 9 read-only NEWDAT9 Bit8 of NEWDT1 8 8 read-only NEWDAT8 Bit7 of NEWDT1 7 7 read-only NEWDAT7 Bit6 of NEWDT1 6 6 read-only NEWDAT6 Bit5 of NEWDT1 5 5 read-only NEWDAT5 Bit4 of NEWDT1 4 4 read-only NEWDAT4 Bit3 of NEWDT1 3 3 read-only NEWDAT3 Bit2 of NEWDT1 2 2 read-only NEWDAT2 Bit1 of NEWDT1 1 1 read-only NEWDAT1 Bit0 of NEWDT1 0 0 read-only NEWDT2 CAN New Data Registers 2 0x92 16 read-only 0x0000 0xFFFF NEWDAT32 Bit15 of NEWDT2 15 15 read-only NEWDAT31 Bit14 of NEWDT2 14 14 read-only NEWDAT30 Bit13 of NEWDT2 13 13 read-only NEWDAT29 Bit12 of NEWDT2 12 12 read-only NEWDAT28 Bit11 of NEWDT2 11 11 read-only NEWDAT27 Bit10 of NEWDT2 10 10 read-only NEWDAT26 Bit9 of NEWDT2 9 9 read-only NEWDAT25 Bit8 of NEWDT2 8 8 read-only NEWDAT24 Bit7 of NEWDT2 7 7 read-only NEWDAT23 Bit6 of NEWDT2 6 6 read-only NEWDAT22 Bit5 of NEWDT2 5 5 read-only NEWDAT21 Bit4 of NEWDT2 4 4 read-only NEWDAT20 Bit3 of NEWDT2 3 3 read-only NEWDAT19 Bit2 of NEWDT2 2 2 read-only NEWDAT18 Bit1 of NEWDT2 1 1 read-only NEWDAT17 Bit0 of NEWDT2 0 0 read-only INTPND1 CAN Interrupt Pending Registers 1 0xA0 16 read-only 0x0000 0xFFFF INTPND16 Bit15 of INTPND1 15 15 read-only INTPND15 Bit14 of INTPND1 14 14 read-only INTPND14 Bit13 of INTPND1 13 13 read-only INTPND13 Bit12 of INTPND1 12 12 read-only INTPND12 Bit11 of INTPND1 11 11 read-only INTPND11 Bit10 of INTPND1 10 10 read-only INTPND10 Bit9 of INTPND1 9 9 read-only INTPND9 Bit8 of INTPND1 8 8 read-only INTPND8 Bit7 of INTPND1 7 7 read-only INTPND7 Bit6 of INTPND1 6 6 read-only INTPND6 Bit5 of INTPND1 5 5 read-only INTPND5 Bit4 of INTPND1 4 4 read-only INTPND4 Bit3 of INTPND1 3 3 read-only INTPND3 Bit2 of INTPND1 2 2 read-only INTPND2 Bit1 of INTPND1 1 1 read-only INTPND1 Bit0 of INTPND1 0 0 read-only INTPND2 CAN Interrupt Pending Registers 2 0xA2 16 read-only 0x0000 0xFFFF INTPND32 Bit15 of INTPND2 15 15 read-only INTPND31 Bit14 of INTPND2 14 14 read-only INTPND30 Bit13 of INTPND2 13 13 read-only INTPND29 Bit12 of INTPND2 12 12 read-only INTPND28 Bit11 of INTPND2 11 11 read-only INTPND27 Bit10 of INTPND2 10 10 read-only INTPND26 Bit9 of INTPND2 9 9 read-only INTPND25 Bit8 of INTPND2 8 8 read-only INTPND24 Bit7 of INTPND2 7 7 read-only INTPND23 Bit6 of INTPND2 6 6 read-only INTPND22 Bit5 of INTPND2 5 5 read-only INTPND21 Bit4 of INTPND2 4 4 read-only INTPND20 Bit3 of INTPND2 3 3 read-only INTPND19 Bit2 of INTPND2 2 2 read-only INTPND18 Bit1 of INTPND2 1 1 read-only INTPND17 Bit0 of INTPND2 0 0 read-only MSGVAL1 CAN Message Valid Registers 1 0xB0 16 read-only 0x0000 0xFFFF MSGVAL16 Bit15 of MSGVAL1 15 15 read-only MSGVAL15 Bit14 of MSGVAL1 14 14 read-only MSGVAL14 Bit13 of MSGVAL1 13 13 read-only MSGVAL13 Bit12 of MSGVAL1 12 12 read-only MSGVAL12 Bit11 of MSGVAL1 11 11 read-only MSGVAL11 Bit10 of MSGVAL1 10 10 read-only MSGVAL10 Bit9 of MSGVAL1 9 9 read-only MSGVAL9 Bit8 of MSGVAL1 8 8 read-only MSGVAL8 Bit7 of MSGVAL1 7 7 read-only MSGVAL7 Bit6 of MSGVAL1 6 6 read-only MSGVAL6 Bit5 of MSGVAL1 5 5 read-only MSGVAL5 Bit4 of MSGVAL1 4 4 read-only MSGVAL4 Bit3 of MSGVAL1 3 3 read-only MSGVAL3 Bit2 of MSGVAL1 2 2 read-only MSGVAL2 Bit1 of MSGVAL1 1 1 read-only MSGVAL1 Bit0 of MSGVAL1 0 0 read-only MSGVAL2 CAN Message Valid Registers 2 0xB2 16 read-only 0x0000 0xFFFF MSGVAL32 Bit15 of MSGVAL2 15 15 read-only MSGVAL31 Bit14 of MSGVAL2 14 14 read-only MSGVAL30 Bit13 of MSGVAL2 13 13 read-only MSGVAL29 Bit12 of MSGVAL2 12 12 read-only MSGVAL28 Bit11 of MSGVAL2 11 11 read-only MSGVAL27 Bit10 of MSGVAL2 10 10 read-only MSGVAL26 Bit9 of MSGVAL2 9 9 read-only MSGVAL25 Bit8 of MSGVAL2 8 8 read-only MSGVAL24 Bit7 of MSGVAL2 7 7 read-only MSGVAL23 Bit6 of MSGVAL2 6 6 read-only MSGVAL22 Bit5 of MSGVAL2 5 5 read-only MSGVAL21 Bit4 of MSGVAL2 4 4 read-only MSGVAL20 Bit3 of MSGVAL2 3 3 read-only MSGVAL19 Bit2 of MSGVAL2 2 2 read-only MSGVAL18 Bit1 of MSGVAL2 1 1 read-only MSGVAL17 Bit0 of MSGVAL2 0 0 read-only CAN1 0x40063000 CAN1 81 CANFD CAN FD Registers CANFD 0x40070000 0x0 0x4 registers 0x4 0x4 registers 0x8 0x4 registers 0xC 0x4 registers 0x10 0x4 registers 0x14 0x4 registers 0x18 0x4 registers 0x1C 0x4 registers 0x20 0x4 registers 0x24 0x4 registers 0x28 0x4 registers 0x2C 0x4 registers 0x30 0x4 registers 0x34 0x1 registers 0x35 0x1 registers 0x38 0x1 registers 0x39 0x1 registers 0x3A 0x1 registers 0x3B 0x1 registers 0x3C 0x2 registers 0x3E 0x2 registers 0x40 0x4 registers 0x44 0x4 registers 0x50 0x64 registers 0x90 0x64 registers 0xD0 0x4 registers 0xD4 0x4 registers 0xD8 0x4 registers 0xDC 0x4 registers 0xE0 0x4 registers 0xE4 0x4 registers 0xF0 0x4 registers 0xF4 0x4 registers 0xF8 0x4 registers 0x200 0x20 registers CREL Core Release Register 0x00 32 read-only 0x30130506 0xFFFFFFFF REL Core Release 28 31 read-only STEP Step of Core Release 24 27 read-only SUBSTEP Sub-step of Core Release 20 23 read-only YEAR Time Stamp Year 16 19 read-only MON Time Stamp Month 8 15 read-only DAY Time Stamp Day 0 7 read-only ENDN Endian Register 0x04 32 read-only 0x87654321 0xFFFFFFFF ETV Endianness Test Value 0 31 read-only FBTP Fast Bit Timing and Prescaler Register 0x0C 32 read-write 0x00000000 0x1F9F0F73 TDCO Transceiver Delay Compensation Offset 24 28 read-write TDC Transceiver Delay Compensation 23 23 read-write FBRP Fast Baud Rate Prescaler 16 20 read-write FTSEG1 Fast time segment before sample point 8 11 read-write FTSEG2 Fast time segment after sample point 4 6 read-write FSJW Fast (Re) Synchronization Jump Width 0 1 read-write TEST Test Register 0x10 32 read-write 0x00000000 0x00003FF0 TDCV Transceiver Delay Compensation Value 8 13 read-only RX Receive Pin 7 7 read-write TX Control of Transmit Pin 5 6 read-write LBCK Loop Back Mode 4 4 read-write RWD RAM Watchdog 0x14 32 read-write 0x00000000 0x0000FFFF WDV Watchdog Value 8 15 read-only WDC Watchdog Configuration 0 7 read-write CCCR CC Control Register 0x18 32 read-write 0x00000001 0x00007FFF TXP Transmit Pause 14 14 read-write FDBS CAN FD Bit Rate Switching 13 13 read-only FDO CAN FD Operation 12 12 read-only CMR CAN Mode Request 10 11 read-write CME CAN Mode Enable 8 9 read-write TEST Test Mode Enable 7 7 read-write DAR Disable Automatic Retransmission 6 6 read-write MON Bus Monitoring Mode 5 5 read-write CSR Clock Stop Request 4 4 read-write CSA Clock Stop Acknowledge 3 3 read-only ASM Restricted Operation Mode 2 2 read-write CCE Configuration Change Enable 1 1 read-write INIT Initialization 0 0 read-write BTP Bit Timing and Prescaler Register 0x1C 32 read-write 0x00000A33 0x03FF3FFF BRP Baud Rate Prescaler 16 25 read-write TSEG1 Time segment before sample point 8 13 read-write TSEG2 Time segment after sample point 4 7 read-write SJW (Re) Synchronization Jump Width 0 3 read-write TSCC Timestamp Counter Configuration 0x20 32 read-write 0x00000000 0x000F0003 TCP Timestamp Counter Prescaler 16 19 read-write TSS Timestamp Select 0 1 read-write TSCV Timestamp Counter Value 0x24 32 read-write 0x00000000 0x0000FFFF TSC Timestamp Counter 0 15 read-write TOCC Timeout Counter Configuration 0x28 32 read-write 0x00000000 0xFFFF0007 TOP Timeout Period 16 31 read-write TOS Timeout Select 1 2 read-write ETOC Enable Timeout Counter 0 0 read-write TOCV Timeout Counter Value 0x2C 32 read-write 0x0000FFFF 0x0000FFFF TOC Timeout Counter 0 15 read-write ECR Error Counter Register 0x40 32 read-only 0x00000000 0x00FFFFFF CEL CAN Error Logging 16 23 read-only RP Receive Error Passive 15 15 read-only REC Receive Error Counter 8 14 read-only TEC Transmit Error Counter 0 7 read-only PSR Protocol Status Register 0x44 32 read-only 0x00000707 0x00FFFFFF REDL Received a CAN FD Message 13 13 read-only RBRS BRS flag of last received CAN FD Message 12 12 read-only RESI ESI flag of last received CAN FD Message 11 11 read-only FLEC Fast Last Error Code 8 10 read-only BO Bus_Off Status 7 7 read-only EW Warning Status 6 6 read-only EP Error Passive 5 5 read-only ACT Activity 3 4 read-only LEC Last Error Code 0 2 read-only IR Interrupt Register 0x50 32 read-write 0x00000000 0xFFFFFFFF STE Stuff Error 31 31 read-write FOE Format Error 30 30 read-write ACKE Acknowledge Error 29 29 read-write BE Bit Error 28 28 read-write CRCE CRC Error 27 27 read-write WDI Watchdog Interrupt 26 26 read-write BO Bus_Off Status 25 25 read-write EW Warning Status 24 24 read-write EP Error Passive 23 23 read-write ELO Error Logging Overflow 22 22 read-write BEU Bit Error Uncorrected 21 21 read-write BEC Bit Error Corrected 20 20 read-write DRX Message stored to Dedicated Rx Buffer 19 19 read-write TOO Timeout Occurred 18 18 read-write MRAF Message RAM Access Failure 17 17 read-write TSW Timestamp Wraparound 16 16 read-write TEFL Tx Event FIFO Element Lost 15 15 read-write TEFF Tx Event FIFO Full 14 14 read-write TEFW Tx Event FIFO Watermark Reached 13 13 read-write TEFN Tx Event FIFO New Entry 12 12 read-write TFE Tx FIFO Empty 11 11 read-write TCF Transmission Cancellation Finished 10 10 read-write TC Transmission Completed 9 9 read-write HPM High Priority Message 8 8 read-write RF1L Rx FIFO 1 Message Lost 7 7 read-write RF1F Rx FIFO 1 Full 6 6 read-write RF1W Rx FIFO 1 Watermark Reached 5 5 read-write RF1N Rx FIFO 1 New Message 4 4 read-write RF0L Rx FIFO 0 Message Lost 3 3 read-write RF0F Rx FIFO 0 Full 2 2 read-write RF0W Rx FIFO 0 Watermark Reached 1 1 read-write RF0N Rx FIFO 0 New Message 0 0 read-write IE Interrupt Enable 0x54 32 read-write 0x00000000 0xFFFFFFFF STEE Stuff Error Interrupt Enable 31 31 read-write FOEE Format Error Interrupt Enable 30 30 read-write ACKEE Acknowledge Error Interrupt Enable 29 29 read-write BEE Bit Error Interrupt Enable 28 28 read-write CRCEE CRC Error Interrupt Enable 27 27 read-write WDIE Watchdog Interrupt Interrupt Enable 26 26 read-write BOE Bus_Off Status Interrupt Enable 25 25 read-write EWE Warning Status Interrupt Enable 24 24 read-write EPE Error Passive Interrupt Enable 23 23 read-write ELOE Error Logging Overflow Interrupt Enable 22 22 read-write BEUE Bit Error Uncorrected Interrupt Enable 21 21 read-write BECE Bit Error Corrected Interrupt Enable 20 20 read-write DRXE Message stored to Dedicated Rx Buffer Interrupt Enable 19 19 read-write TOOE Timeout Occurred Interrupt Enable 18 18 read-write MRAFE Message RAM Access Failure Interrupt Enable 17 17 read-write TSWE Timestamp Wraparound Interrupt Enable 16 16 read-write TEFLE Tx Event FIFO Element Lost Interrupt Enable 15 15 read-write TEFFE Tx Event FIFO Full Interrupt Enable 14 14 read-write TEFWE Tx Event FIFO Watermark Reached Interrupt Enable 13 13 read-write TEFNE Tx Event FIFO New Entry Interrupt Enable 12 12 read-write TFEE Tx FIFO Empty Interrupt Enable 11 11 read-write TCFE Transmission Cancellation Finished Interrupt Enable 10 10 read-write TCE Transmission Completed Interrupt Enable 9 9 read-write HPME High Priority Message Interrupt Enable 8 8 read-write RF1LE Rx FIFO 1 Message Lost Interrupt Enable 7 7 read-write RF1FE Rx FIFO 1 Full Interrupt Enable 6 6 read-write RF1WE Rx FIFO 1 Watermark Reached Interrupt Enable 5 5 read-write RF1NE Rx FIFO 1 New Message Interrupt Enable 4 4 read-write RF0LE Rx FIFO 0 Message Lost Interrupt Enable 3 3 read-write RF0FE Rx FIFO 0 Full Interrupt Enable 2 2 read-write RF0WE Rx FIFO 0 Watermark Reached Interrupt Enable 1 1 read-write RF0NE Rx FIFO 0 New Message Interrupt Enable 0 0 read-write ILS Interrupt Line Select 0x58 32 read-write 0x00000000 0xFFFFFFFF STEL Stuff Error Interrupt Line 31 31 read-write FOEL Format Error Interrupt Line 30 30 read-write ACKEL Acknowledge Error Interrupt Line 29 29 read-write BEL Bit Error Interrupt Line 28 28 read-write CRCEL CRC Error Interrupt Line 27 27 read-write WDIL Watchdog Interrupt Interrupt Line 26 26 read-write BOL Bus_Off Status Interrupt Line 25 25 read-write EWL Warning Status Interrupt Line 24 24 read-write EPL Error Passive Interrupt Line 23 23 read-write ELOL Error Logging Overflow Interrupt Line 22 22 read-write BEUL Bit Error Uncorrected Interrupt Line 21 21 read-write BECL Bit Error Corrected Interrupt Line 20 20 read-write DRXL Message stored to Dedicated Rx Buffer Interrupt Line 19 19 read-write TOOL Timeout Occurred Interrupt Line 18 18 read-write MRAFL Message RAM Access Failure Interrupt Line 17 17 read-write TSWL Timestamp Wraparound Interrupt Line 16 16 read-write TEFLL Tx Event FIFO Element Lost Interrupt Line 15 15 read-write TEFFL Tx Event FIFO Full Interrupt Line 14 14 read-write TEFWL Tx Event FIFO Watermark Reached Interrupt Line 13 13 read-write TEFNL Tx Event FIFO New Entry Interrupt Line 12 12 read-write TFEL Tx FIFO Empty Interrupt Line 11 11 read-write TCFL Transmission Cancellation Finished Interrupt Line 10 10 read-write TCL Transmission Completed Interrupt Line 9 9 read-write HPML High Priority Message Interrupt Line 8 8 read-write RF1LL Rx FIFO 1 Message Lost Interrupt Line 7 7 read-write RF1FL Rx FIFO 1 Full Interrupt Line 6 6 read-write RF1WL Rx FIFO 1 Watermark Reached Interrupt Line 5 5 read-write RF1NL Rx FIFO 1 New Message Interrupt Line 4 4 read-write RF0LL Rx FIFO 0 Message Lost Interrupt Line 3 3 read-write RF0FL Rx FIFO 0 Full Interrupt Line 2 2 read-write RF0WL Rx FIFO 0 Watermark Reached Interrupt Line 1 1 read-write RF0NL Rx FIFO 0 New Message Interrupt Line 0 0 read-write ILE Interrupt Line Enable 0x5C 32 read-write 0x00000000 0x00000003 EINT1 Enable Interrupt Line 1 1 1 read-write EINT0 Enable Interrupt Line 0 0 0 read-write GFC Global Filter Configuration 0x80 32 read-write 0x00000000 0x0000003F ANFS Accept Non-matching Frames Standard 4 5 read-write ANFE Accept Non-matching Frames Extended 2 3 read-write RRFS Reject Remote Frames Standard 1 1 read-write RRFE Reject Remote Frames Extended 0 0 read-write SIDFC Standard ID Filter Configuration 0x84 32 read-write 0x00000000 0x00FFFFFC LSS List Size Standard 16 23 read-write FLSSA Filter List Standard Start Address 2 15 read-write XIDFC Extended ID Filter Configuration 0x88 32 read-write 0x00000000 0x007FFFFC LSE List Size Extended 16 22 read-write FLESA Filter List Extended Start Address 2 15 read-write XIDAM Extended ID AND Mask 0x90 32 read-write 0x1FFFFFFF 0x1FFFFFFF EIDM Extended ID Mask 0 28 read-write HPMS High Priority Message Status 0x94 32 read-only 0x00000000 0x0000FFFF FLST Filter List 15 15 read-only FIDX Filter Index 8 14 read-only MSI Message Storage Indicator 6 7 read-only BIDX Buffer Index 0 5 read-only NDAT1 New Data 1 0x98 32 read-only 0x00000000 0xFFFFFFFF ND31 New Data flag of Rx Buffer 31 31 31 read-write ND30 New Data flag of Rx Buffer 30 30 30 read-write ND29 New Data flag of Rx Buffer 29 29 29 read-write ND28 New Data flag of Rx Buffer 28 28 28 read-write ND27 New Data flag of Rx Buffer 27 27 27 read-write ND26 New Data flag of Rx Buffer 26 26 26 read-write ND25 New Data flag of Rx Buffer 25 25 25 read-write ND24 New Data flag of Rx Buffer 24 24 24 read-write ND23 New Data flag of Rx Buffer 23 23 23 read-write ND22 New Data flag of Rx Buffer 22 22 22 read-write ND21 New Data flag of Rx Buffer 21 21 21 read-write ND20 New Data flag of Rx Buffer 20 20 20 read-write ND19 New Data flag of Rx Buffer 19 19 19 read-write ND18 New Data flag of Rx Buffer 18 18 18 read-write ND17 New Data flag of Rx Buffer 17 17 17 read-write ND16 New Data flag of Rx Buffer 16 16 16 read-write ND15 New Data flag of Rx Buffer 15 15 15 read-write ND14 New Data flag of Rx Buffer 14 14 14 read-write ND13 New Data flag of Rx Buffer 13 13 13 read-write ND12 New Data flag of Rx Buffer 12 12 12 read-write ND11 New Data flag of Rx Buffer 11 11 11 read-write ND10 New Data flag of Rx Buffer 10 10 10 read-write ND9 New Data flag of Rx Buffer 9 9 9 read-write ND8 New Data flag of Rx Buffer 8 8 8 read-write ND7 New Data flag of Rx Buffer 7 7 7 read-write ND6 New Data flag of Rx Buffer 6 6 6 read-write ND5 New Data flag of Rx Buffer 5 5 5 read-write ND4 New Data flag of Rx Buffer 4 4 4 read-write ND3 New Data flag of Rx Buffer 3 3 3 read-write ND2 New Data flag of Rx Buffer 2 2 2 read-write ND1 New Data flag of Rx Buffer 1 1 1 read-write ND0 New Data flag of Rx Buffer 0 0 0 read-write NDAT2 New Data 2 0x9C 32 read-only 0x00000000 0xFFFFFFFF ND63 New Data flag of Rx Buffer 63 31 31 read-write ND62 New Data flag of Rx Buffer 62 30 30 read-write ND61 New Data flag of Rx Buffer 61 29 29 read-write ND60 New Data flag of Rx Buffer 60 28 28 read-write ND59 New Data flag of Rx Buffer 59 27 27 read-write ND58 New Data flag of Rx Buffer 58 26 26 read-write ND57 New Data flag of Rx Buffer 57 25 25 read-write ND56 New Data flag of Rx Buffer 56 24 24 read-write ND55 New Data flag of Rx Buffer 55 23 23 read-write ND54 New Data flag of Rx Buffer 54 22 22 read-write ND53 New Data flag of Rx Buffer 53 21 21 read-write ND52 New Data flag of Rx Buffer 52 20 20 read-write ND51 New Data flag of Rx Buffer 51 19 19 read-write ND50 New Data flag of Rx Buffer 50 18 18 read-write ND49 New Data flag of Rx Buffer 49 17 17 read-write ND48 New Data flag of Rx Buffer 48 16 16 read-write ND47 New Data flag of Rx Buffer 47 15 15 read-write ND46 New Data flag of Rx Buffer 46 14 14 read-write ND45 New Data flag of Rx Buffer 45 13 13 read-write ND44 New Data flag of Rx Buffer 44 12 12 read-write ND43 New Data flag of Rx Buffer 43 11 11 read-write ND42 New Data flag of Rx Buffer 42 10 10 read-write ND41 New Data flag of Rx Buffer 41 9 9 read-write ND40 New Data flag of Rx Buffer 40 8 8 read-write ND39 New Data flag of Rx Buffer 39 7 7 read-write ND38 New Data flag of Rx Buffer 38 6 6 read-write ND37 New Data flag of Rx Buffer 37 5 5 read-write ND36 New Data flag of Rx Buffer 36 4 4 read-write ND35 New Data flag of Rx Buffer 35 3 3 read-write ND34 New Data flag of Rx Buffer 34 2 2 read-write ND33 New Data flag of Rx Buffer 33 1 1 read-write ND32 New Data flag of Rx Buffer 32 0 0 read-write RXF0C Rx FIFO 0 Configuration 0xA0 32 read-write 0x00000000 0xFF7FFFFC F0OM FIFO 0 Operation Mode 31 31 read-write F0WM Rx FIFO 0 Watermark 24 30 read-write F0S Rx FIFO 0 Size 16 22 read-write F0SA Rx FIFO 0 Start Address 2 15 read-write RXF0S Rx FIFO 0 Status 0xA4 32 read-only 0x00000000 0x033F3F7F RF0L Rx FIFO 0 Message Lost 25 25 read-only F0F Rx FIFO 0 Full 24 24 read-only F0PI Rx FIFO 0 Put Index 16 21 read-only F0GI Rx FIFO 0 Get Index 8 13 read-only F0FL Rx FIFO 0 Fill Level 0 6 read-only RXF0A Rx FIFO 0 Acknowledge 0xA8 32 read-write 0x00000000 0x0000003F F0AI Rx FIFO 0 Acknowledge Index 0 5 read-write RXBC Rx Buffer Configuration 0xAC 32 read-write 0x00000000 0x0000FFFC RBSA 2 2 15 read-write RXF1C Rx FIFO 1 Configuration 0xB0 32 read-write 0x00000000 0xFF7FFFFC F1OM FIFO 1 Operation Mode 31 31 read-write F1WM Rx FIFO 1 Watermark 24 30 read-write F1S Rx FIFO 1 Size 16 22 read-write F1SA Rx FIFO 1 Start Address 2 15 read-write RXF1S Rx FIFO 1 Status 0xB4 32 read-only 0x00000000 0xC33F3F7F DMS Debug Message Status 30 31 read-only RF1L FIFO 1 Message Lost 25 25 read-only F1F Rx FIFO 1 Full 24 24 read-only F1PI Rx FIFO 1 Put Index 16 21 read-only F1GI Rx FIFO 1 Get Index 8 13 read-only F1FL Rx FIFO 1 Fill Level 0 6 read-only RXF1A Rx FIFO 1 Acknowledge 0xB8 32 read-write 0x00000000 0x0000003F F1AI Rx FIFO 1 Acknowledge Index 0 5 read-write RXESC Rx Buffer/FIFO Element Size Configuration 0xBC 32 read-write 0x00000000 0x00000777 RBDS Rx Buffer Data Field Size 8 10 read-write F1DS Rx FIFO 1 Data Field Size 4 6 read-write F0DS Rx FIFO 0 Data Field Size 0 2 read-write TXBC Tx Buffer Configuration 0xC0 32 read-write 0x00000000 0x7F3FFFFC TFQM Tx FIFO/Queue Mode 30 30 read-write TFQS Transmit FIFO/Queue Size 24 29 read-write NDTB Number of Dedicated Transmit Buffers 16 21 read-write TBSA Tx Buffers Start Address 2 15 read-write TXFQS Tx FIFO/Queue Status 0xC4 32 read-only 0x00000000 0x003F1F3F TFQF Tx FIFO/Queue Full 21 21 read-only TFQPI Tx FIFO/Queue Put Index 16 20 read-only TFGI Tx FIFO Get Index 8 12 read-only TFFL Tx FIFO Free Level 0 5 read-only TXESC Tx Buffer Element Size Configuration 0xC8 32 read-only 0x00000000 0x00000007 TBDS Tx Buffer Data Field Size 0 2 read-write TXBRP Tx Buffer Request Pending 0xCC 32 read-only 0x00000000 0xFFFFFFFF TRP31 Transmission Request Pending of Tx Buffer 31 31 31 read-only TRP30 Transmission Request Pending of Tx Buffer 30 30 30 read-only TRP29 Transmission Request Pending of Tx Buffer 29 29 29 read-only TRP28 Transmission Request Pending of Tx Buffer 28 28 28 read-only TRP27 Transmission Request Pending of Tx Buffer 27 27 27 read-only TRP26 Transmission Request Pending of Tx Buffer 26 26 26 read-only TRP25 Transmission Request Pending of Tx Buffer 25 25 25 read-only TRP24 Transmission Request Pending of Tx Buffer 24 24 24 read-only TRP23 Transmission Request Pending of Tx Buffer 23 23 23 read-only TRP22 Transmission Request Pending of Tx Buffer 22 22 22 read-only TRP21 Transmission Request Pending of Tx Buffer 21 21 21 read-only TRP20 Transmission Request Pending of Tx Buffer 20 20 20 read-only TRP19 Transmission Request Pending of Tx Buffer 19 19 19 read-only TRP18 Transmission Request Pending of Tx Buffer 18 18 18 read-only TRP17 Transmission Request Pending of Tx Buffer 17 17 17 read-only TRP16 Transmission Request Pending of Tx Buffer 16 16 16 read-only TRP15 Transmission Request Pending of Tx Buffer 15 15 15 read-only TRP14 Transmission Request Pending of Tx Buffer 14 14 14 read-only TRP13 Transmission Request Pending of Tx Buffer 13 13 13 read-only TRP12 Transmission Request Pending of Tx Buffer 12 12 12 read-only TRP11 Transmission Request Pending of Tx Buffer 11 11 11 read-only TRP10 Transmission Request Pending of Tx Buffer 10 10 10 read-only TRP9 Transmission Request Pending of Tx Buffer 9 9 9 read-only TRP8 Transmission Request Pending of Tx Buffer 8 8 8 read-only TRP7 Transmission Request Pending of Tx Buffer 7 7 7 read-only TRP6 Transmission Request Pending of Tx Buffer 6 6 6 read-only TRP5 Transmission Request Pending of Tx Buffer 5 5 5 read-only TRP4 Transmission Request Pending of Tx Buffer 4 4 4 read-only TRP3 Transmission Request Pending of Tx Buffer 3 3 3 read-only TRP2 Transmission Request Pending of Tx Buffer 2 2 2 read-only TRP1 Transmission Request Pending of Tx Buffer 1 1 1 read-only TRP0 Transmission Request Pending of Tx Buffer 0 0 0 read-only TXBAR Tx Buffer Add Request 0xD0 32 read-only 0x00000000 0xFFFFFFFF AR31 Add Request of Tx Buffer 31 31 31 read-write AR30 Add Request of Tx Buffer 30 30 30 read-write AR29 Add Request of Tx Buffer 29 29 29 read-write AR28 Add Request of Tx Buffer 28 28 28 read-write AR27 Add Request of Tx Buffer 27 27 27 read-write AR26 Add Request of Tx Buffer 26 26 26 read-write AR25 Add Request of Tx Buffer 25 25 25 read-write AR24 Add Request of Tx Buffer 24 24 24 read-write AR23 Add Request of Tx Buffer 23 23 23 read-write AR22 Add Request of Tx Buffer 22 22 22 read-write AR21 Add Request of Tx Buffer 21 21 21 read-write AR20 Add Request of Tx Buffer 20 20 20 read-write AR19 Add Request of Tx Buffer 19 19 19 read-write AR18 Add Request of Tx Buffer 18 18 18 read-write AR17 Add Request of Tx Buffer 17 17 17 read-write AR16 Add Request of Tx Buffer 16 16 16 read-write AR15 Add Request of Tx Buffer 15 15 15 read-write AR14 Add Request of Tx Buffer 14 14 14 read-write AR13 Add Request of Tx Buffer 13 13 13 read-write AR12 Add Request of Tx Buffer 12 12 12 read-write AR11 Add Request of Tx Buffer 11 11 11 read-write AR10 Add Request of Tx Buffer 10 10 10 read-write AR9 Add Request of Tx Buffer 9 9 9 read-write AR8 Add Request of Tx Buffer 8 8 8 read-write AR7 Add Request of Tx Buffer 7 7 7 read-write AR6 Add Request of Tx Buffer 6 6 6 read-write AR5 Add Request of Tx Buffer 5 5 5 read-write AR4 Add Request of Tx Buffer 4 4 4 read-write AR3 Add Request of Tx Buffer 3 3 3 read-write AR2 Add Request of Tx Buffer 2 2 2 read-write AR1 Add Request of Tx Buffer 1 1 1 read-write AR0 Add Request of Tx Buffer 0 0 0 read-write TXBCR Tx Buffer Cancellation Request 0xD4 32 read-only 0x00000000 0xFFFFFFFF CR31 Cancellation Request of Tx Buffer 31 31 31 read-write CR30 Cancellation Request of Tx Buffer 30 30 30 read-write CR29 Cancellation Request of Tx Buffer 29 29 29 read-write CR28 Cancellation Request of Tx Buffer 28 28 28 read-write CR27 Cancellation Request of Tx Buffer 27 27 27 read-write CR26 Cancellation Request of Tx Buffer 26 26 26 read-write CR25 Cancellation Request of Tx Buffer 25 25 25 read-write CR24 Cancellation Request of Tx Buffer 24 24 24 read-write CR23 Cancellation Request of Tx Buffer 23 23 23 read-write CR22 Cancellation Request of Tx Buffer 22 22 22 read-write CR21 Cancellation Request of Tx Buffer 21 21 21 read-write CR20 Cancellation Request of Tx Buffer 20 20 20 read-write CR19 Cancellation Request of Tx Buffer 19 19 19 read-write CR18 Cancellation Request of Tx Buffer 18 18 18 read-write CR17 Cancellation Request of Tx Buffer 17 17 17 read-write CR16 Cancellation Request of Tx Buffer 16 16 16 read-write CR15 Cancellation Request of Tx Buffer 15 15 15 read-write CR14 Cancellation Request of Tx Buffer 14 14 14 read-write CR13 Cancellation Request of Tx Buffer 13 13 13 read-write CR12 Cancellation Request of Tx Buffer 12 12 12 read-write CR11 Cancellation Request of Tx Buffer 11 11 11 read-write CR10 Cancellation Request of Tx Buffer 10 10 10 read-write CR9 Cancellation Request of Tx Buffer 9 9 9 read-write CR8 Cancellation Request of Tx Buffer 8 8 8 read-write CR7 Cancellation Request of Tx Buffer 7 7 7 read-write CR6 Cancellation Request of Tx Buffer 6 6 6 read-write CR5 Cancellation Request of Tx Buffer 5 5 5 read-write CR4 Cancellation Request of Tx Buffer 4 4 4 read-write CR3 Cancellation Request of Tx Buffer 3 3 3 read-write CR2 Cancellation Request of Tx Buffer 2 2 2 read-write CR1 Cancellation Request of Tx Buffer 1 1 1 read-write CR0 Cancellation Request of Tx Buffer 0 0 0 read-write TXBTO Tx Buffer Transmission Occurred 0xD8 32 read-only 0x00000000 0xFFFFFFFF TO31 Transmission Occurred of Tx Buffer 31 31 31 read-only TO30 Transmission Occurred of Tx Buffer 30 30 30 read-only TO29 Transmission Occurred of Tx Buffer 29 29 29 read-only TO28 Transmission Occurred of Tx Buffer 28 28 28 read-only TO27 Transmission Occurred of Tx Buffer 27 27 27 read-only TO26 Transmission Occurred of Tx Buffer 26 26 26 read-only TO25 Transmission Occurred of Tx Buffer 25 25 25 read-only TO24 Transmission Occurred of Tx Buffer 24 24 24 read-only TO23 Transmission Occurred of Tx Buffer 23 23 23 read-only TO22 Transmission Occurred of Tx Buffer 22 22 22 read-only TO21 Transmission Occurred of Tx Buffer 21 21 21 read-only TO20 Transmission Occurred of Tx Buffer 20 20 20 read-only TO19 Transmission Occurred of Tx Buffer 19 19 19 read-only TO18 Transmission Occurred of Tx Buffer 18 18 18 read-only TO17 Transmission Occurred of Tx Buffer 17 17 17 read-only TO16 Transmission Occurred of Tx Buffer 16 16 16 read-only TO15 Transmission Occurred of Tx Buffer 15 15 15 read-only TO14 Transmission Occurred of Tx Buffer 14 14 14 read-only TO13 Transmission Occurred of Tx Buffer 13 13 13 read-only TO12 Transmission Occurred of Tx Buffer 12 12 12 read-only TO11 Transmission Occurred of Tx Buffer 11 11 11 read-only TO10 Transmission Occurred of Tx Buffer 10 10 10 read-only TO9 Transmission Occurred of Tx Buffer 9 9 9 read-only TO8 Transmission Occurred of Tx Buffer 8 8 8 read-only TO7 Transmission Occurred of Tx Buffer 7 7 7 read-only TO6 Transmission Occurred of Tx Buffer 6 6 6 read-only TO5 Transmission Occurred of Tx Buffer 5 5 5 read-only TO4 Transmission Occurred of Tx Buffer 4 4 4 read-only TO3 Transmission Occurred of Tx Buffer 3 3 3 read-only TO2 Transmission Occurred of Tx Buffer 2 2 2 read-only TO1 Transmission Occurred of Tx Buffer 1 1 1 read-only TO0 Transmission Occurred of Tx Buffer 0 0 0 read-only TXBCF Tx Buffer Cancellation Finished 0xDC 32 read-only 0x00000000 0xFFFFFFFF CF31 Cancellation Finished of Tx Buffer 31 31 31 read-only CF30 Cancellation Finished of Tx Buffer 30 30 30 read-only CF29 Cancellation Finished of Tx Buffer 29 29 29 read-only CF28 Cancellation Finished of Tx Buffer 28 28 28 read-only CF27 Cancellation Finished of Tx Buffer 27 27 27 read-only CF26 Cancellation Finished of Tx Buffer 26 26 26 read-only CF25 Cancellation Finished of Tx Buffer 25 25 25 read-only CF24 Cancellation Finished of Tx Buffer 24 24 24 read-only CF23 Cancellation Finished of Tx Buffer 23 23 23 read-only CF22 Cancellation Finished of Tx Buffer 22 22 22 read-only CF21 Cancellation Finished of Tx Buffer 21 21 21 read-only CF20 Cancellation Finished of Tx Buffer 20 20 20 read-only CF19 Cancellation Finished of Tx Buffer 19 19 19 read-only CF18 Cancellation Finished of Tx Buffer 18 18 18 read-only CF17 Cancellation Finished of Tx Buffer 17 17 17 read-only CF16 Cancellation Finished of Tx Buffer 16 16 16 read-only CF15 Cancellation Finished of Tx Buffer 15 15 15 read-only CF14 Cancellation Finished of Tx Buffer 14 14 14 read-only CF13 Cancellation Finished of Tx Buffer 13 13 13 read-only CF12 Cancellation Finished of Tx Buffer 12 12 12 read-only CF11 Cancellation Finished of Tx Buffer 11 11 11 read-only CF10 Cancellation Finished of Tx Buffer 10 10 10 read-only CF9 Cancellation Finished of Tx Buffer 9 9 9 read-only CF8 Cancellation Finished of Tx Buffer 8 8 8 read-only CF7 Cancellation Finished of Tx Buffer 7 7 7 read-only CF6 Cancellation Finished of Tx Buffer 6 6 6 read-only CF5 Cancellation Finished of Tx Buffer 5 5 5 read-only CF4 Cancellation Finished of Tx Buffer 4 4 4 read-only CF3 Cancellation Finished of Tx Buffer 3 3 3 read-only CF2 Cancellation Finished of Tx Buffer 2 2 2 read-only CF1 Cancellation Finished of Tx Buffer 1 1 1 read-only CF0 Cancellation Finished of Tx Buffer 0 0 0 read-only TXBTIE Tx Buffer Transmission Interrupt Enable 0xE0 32 read-only 0x00000000 0xFFFFFFFF TIE31 Transmission Interrupt Enable of Tx Buffer 31 31 31 read-write TIE30 Transmission Interrupt Enable of Tx Buffer 30 30 30 read-write TIE29 Transmission Interrupt Enable of Tx Buffer 29 29 29 read-write TIE28 Transmission Interrupt Enable of Tx Buffer 28 28 28 read-write TIE27 Transmission Interrupt Enable of Tx Buffer 27 27 27 read-write TIE26 Transmission Interrupt Enable of Tx Buffer 26 26 26 read-write TIE25 Transmission Interrupt Enable of Tx Buffer 25 25 25 read-write TIE24 Transmission Interrupt Enable of Tx Buffer 24 24 24 read-write TIE23 Transmission Interrupt Enable of Tx Buffer 23 23 23 read-write TIE22 Transmission Interrupt Enable of Tx Buffer 22 22 22 read-write TIE21 Transmission Interrupt Enable of Tx Buffer 21 21 21 read-write TIE20 Transmission Interrupt Enable of Tx Buffer 20 20 20 read-write TIE19 Transmission Interrupt Enable of Tx Buffer 19 19 19 read-write TIE18 Transmission Interrupt Enable of Tx Buffer 18 18 18 read-write TIE17 Transmission Interrupt Enable of Tx Buffer 17 17 17 read-write TIE16 Transmission Interrupt Enable of Tx Buffer 16 16 16 read-write TIE15 Transmission Interrupt Enable of Tx Buffer 15 15 15 read-write TIE14 Transmission Interrupt Enable of Tx Buffer 14 14 14 read-write TIE13 Transmission Interrupt Enable of Tx Buffer 13 13 13 read-write TIE12 Transmission Interrupt Enable of Tx Buffer 12 12 12 read-write TIE11 Transmission Interrupt Enable of Tx Buffer 11 11 11 read-write TIE10 Transmission Interrupt Enable of Tx Buffer 10 10 10 read-write TIE9 Transmission Interrupt Enable of Tx Buffer 9 9 9 read-write TIE8 Transmission Interrupt Enable of Tx Buffer 8 8 8 read-write TIE7 Transmission Interrupt Enable of Tx Buffer 7 7 7 read-write TIE6 Transmission Interrupt Enable of Tx Buffer 6 6 6 read-write TIE5 Transmission Interrupt Enable of Tx Buffer 5 5 5 read-write TIE4 Transmission Interrupt Enable of Tx Buffer 4 4 4 read-write TIE3 Transmission Interrupt Enable of Tx Buffer 3 3 3 read-write TIE2 Transmission Interrupt Enable of Tx Buffer 2 2 2 read-write TIE1 Transmission Interrupt Enable of Tx Buffer 1 1 1 read-write TIE0 Transmission Interrupt Enable of Tx Buffer 0 0 0 read-write TXBCIE Tx Buffer Cancellation Finished Interrupt Enable 0xE4 32 read-only 0x00000000 0xFFFFFFFF CFIE31 Cancellation Finished Interrupt Enable of Tx Buffer 31 31 31 read-write CFIE30 Cancellation Finished Interrupt Enable of Tx Buffer 30 30 30 read-write CFIE29 Cancellation Finished Interrupt Enable of Tx Buffer 29 29 29 read-write CFIE28 Cancellation Finished Interrupt Enable of Tx Buffer 28 28 28 read-write CFIE27 Cancellation Finished Interrupt Enable of Tx Buffer 27 27 27 read-write CFIE26 Cancellation Finished Interrupt Enable of Tx Buffer 26 26 26 read-write CFIE25 Cancellation Finished Interrupt Enable of Tx Buffer 25 25 25 read-write CFIE24 Cancellation Finished Interrupt Enable of Tx Buffer 24 24 24 read-write CFIE23 Cancellation Finished Interrupt Enable of Tx Buffer 23 23 23 read-write CFIE22 Cancellation Finished Interrupt Enable of Tx Buffer 22 22 22 read-write CFIE21 Cancellation Finished Interrupt Enable of Tx Buffer 21 21 21 read-write CFIE20 Cancellation Finished Interrupt Enable of Tx Buffer 20 20 20 read-write CFIE19 Cancellation Finished Interrupt Enable of Tx Buffer 19 19 19 read-write CFIE18 Cancellation Finished Interrupt Enable of Tx Buffer 18 18 18 read-write CFIE17 Cancellation Finished Interrupt Enable of Tx Buffer 17 17 17 read-write CFIE16 Cancellation Finished Interrupt Enable of Tx Buffer 16 16 16 read-write CFIE15 Cancellation Finished Interrupt Enable of Tx Buffer 15 15 15 read-write CFIE14 Cancellation Finished Interrupt Enable of Tx Buffer 14 14 14 read-write CFIE13 Cancellation Finished Interrupt Enable of Tx Buffer 13 13 13 read-write CFIE12 Cancellation Finished Interrupt Enable of Tx Buffer 12 12 12 read-write CFIE11 Cancellation Finished Interrupt Enable of Tx Buffer 11 11 11 read-write CFIE10 Cancellation Finished Interrupt Enable of Tx Buffer 10 10 10 read-write CFIE9 Cancellation Finished Interrupt Enable of Tx Buffer 9 9 9 read-write CFIE8 Cancellation Finished Interrupt Enable of Tx Buffer 8 8 8 read-write CFIE7 Cancellation Finished Interrupt Enable of Tx Buffer 7 7 7 read-write CFIE6 Cancellation Finished Interrupt Enable of Tx Buffer 6 6 6 read-write CFIE5 Cancellation Finished Interrupt Enable of Tx Buffer 5 5 5 read-write CFIE4 Cancellation Finished Interrupt Enable of Tx Buffer 4 4 4 read-write CFIE3 Cancellation Finished Interrupt Enable of Tx Buffer 3 3 3 read-write CFIE2 Cancellation Finished Interrupt Enable of Tx Buffer 2 2 2 read-write CFIE1 Cancellation Finished Interrupt Enable of Tx Buffer 1 1 1 read-write CFIE0 Cancellation Finished Interrupt Enable of Tx Buffer 0 0 0 read-write TXEFC Tx Event FIFO Configuration 0xF0 32 read-write 0x00000000 0x3F3FFFFC EFWM Event FIFO Watermark 24 29 read-write EFS Event FIFO Size 16 21 read-write EFSA Event FIFO Start Address 2 15 read-write TXFS Tx Event FIFO Status 0xF4 32 read-only 0x00000000 0x031F1F3F TEFL Tx Event FIFO Element Lost 25 25 read-only EFF Event FIFO Full 24 24 read-only EFPI Event FIFO Put Index 16 20 read-only EFGI Event FIFO Get Index 8 12 read-only EFFL Event FIFO Fill Level 0 5 read-only TXFA Tx Event FIFO Acknowledge 0xF8 32 read-write 0x00000000 0x0000001F EFAI Event FIFO Acknowledge Index 0 4 read-write FDECR CAN FD ECC Error Control Register 0x200 8 read-write 0x00 0x0F CEIV ECC check disable bit 3 3 read-write CEREN ECC error response enable bit 2 2 read-write DEIE Double-bit error factor interrupt enable bit 1 1 read-write SEIE Single-bit error factor interrupt enable bit 0 0 read-write FDESR CAN FD ECC Error Status Register 0x201 8 read-only 0x00 0x03 DEI Double-bit error occurrence bit 1 1 read-only SEI Single-bit error occurrence bit 0 0 read-only FDSEAR CAN FD ECC Single-bit Error Address Register 0x202 16 read-only 0x0000 0xFFFF SRA Single-bit error Message RAM address bits 0 15 read-only FDESCR CAN FD ECC Error Status Clear Register 0x205 8 read-only 0x00 0x03 DEIC Double-bit error clear bit 1 1 write-only SEIC Sngle-bit error clear bit 0 0 write-only FDDEAR CAN FD ECC Double-bit Error Address Register 0x206 16 read-only 0x0000 0xFFFF DRA Double-bit error Message RAM address bits 0 15 read-only TSCNTR Time Stamp Control Register 0x210 16 write-only 0x0000 0x0001 CCLR Counter clear bit 0 0 write-only TSMDR Time Stamp Mode Register 0x212 16 read-write 0x0000 0x0001 CNTEN Counter enable bit 0 0 read-write TSDIVR Time Stamp Divider Register 0x214 32 read-write 0x00000000 0x0000FFFF CDIV Counter clock division ratio setting bit 0 15 read-write TSCDTR Time Stamp Counter Data Register 0x218 16 read-only 0x0000 0xFFFF CNT Counter value bits 0 15 read-only TSCPCLR Time Stamp Compare Clear Register 0x21A 16 read-write 0x0000 0xFFFF CMP Compare clear setting bits 0 15 read-write ETHERNET_MAC0 Ethernet-MAC 0 ETHERNET_MAC0 0x40064000 0x0 0x1058 registers ETHER0 82 MCR MAC Configuration Register 0x0 32 read-write 0x00000000 0x03FFFFFC CST CRC stripping for Type frames 25 25 read-write TC Transmit Configuration in RGMII 24 24 read-write WD Watchdog Disable 23 23 read-write JD Jabber Disable 22 22 read-write BE Frame Burst Enable 21 21 read-write JE Jumbo Frame Enable 20 20 read-write IFG Inter-Frame GAP 17 19 read-write DCRS Disable Carrier Sense During Transaction 16 16 read-write PS Port Select 15 15 read-write FES Speed 14 14 read-write DO Disable Receive Own 13 13 read-write LM Loop-back Mode 12 12 read-write DM Duplex mode 11 11 read-write IPC Checksum Offload 10 10 read-write DR Disable Retry 9 9 read-write LUD Link Up/Down in RGMII 8 8 read-write ACS Automatic Pad/CRC Stripping 7 7 read-write BL Back-off Limit 5 6 read-write DC Deferral Check 4 4 read-write TE Transmitter Enable 3 3 read-write RE Receiver Enable 2 2 read-write MFFR MAC Frame Filter Register 0x4 32 read-write 0x00000000 0x800007FF RA Receive All 31 31 read-write HPF Hash or Perfect Filter 10 10 read-write SAF Source Address Filter 9 9 read-write SAIF Source Address Inverse Filter 8 8 read-write PCF Pass Control Frames 6 7 read-write DB Disable Broadcast Frames 5 5 read-write PM Pass All Multicast 4 4 read-write DAIF DA Inverse Filtering 3 3 read-write HMC Hash Multicast 2 2 read-write HUC Hash Unicast 1 1 read-write PR Promiscuous Mode 0 0 read-write MHTRH MAC Hash Table Register (High) 0x8 32 read-write 0x00000000 0xFFFFFFFF HTH the upper 32 bits of the hash table in the HTH 0 31 read-write MHTRL MAC Hash Table Register (Low) 0xC 32 read-write 0x00000000 0xFFFFFFFF HTL the lower 32 bits of the hash table in the HTL 0 31 read-write GAR GMII/MII Address Register 0x10 32 read-write 0x00000000 0x0000FFFF PA Physical Layer Address 11 15 read-write GR GMII Register 6 10 read-write CR Application Clock Range 2 5 read-write GW GMII/MII Write 1 1 read-write GB GMII/MII Busy 0 0 read-write GDR GMII/MII Data Register 0x14 32 read-write 0x00000000 0x0000FFFF GD GMII/MII Data Register 0 15 read-write FCR Flow Control Register 0x18 32 read-write 0x00000000 0xFFFF00BF PT Pause Time 16 31 read-write DZPQ Disable Zero-Quanta Pause 7 7 read-write PLT Pause Low Threshold 4 5 read-write UP Unicast Pause Frame detect 3 3 read-write RFE Receive Flow Control Enable 2 2 read-write TFE Transmit Flow Control Enable 1 1 read-write FCB_BPA Flow Control Busy/Backpressure Activate 0 0 read-write VTR VLAN TAG Register 0x1C 32 read-write 0x00000000 0x0001FFFF ETV Enable 12-Bit VLAN Tag Comparison 16 16 read-write VL VLAN Tag Identifier 0 15 read-write RWFFR Remote Wake-up Frame Filter Register 0x28 32 read-write 0x00000000 0xFFFFFFFF RWFFR Remote Wake-up Frame Filter Register 0 31 read-write PMTR PMT Register 0x2C 32 read-write 0x00000000 0x80000267 RWFFRPR Remote Wake-up Frame Filter Register Pointer Reset 31 31 read-write GU Global Unicast 9 9 read-write WPR Wake Up Frame Receive 6 6 read-write MPR Magic Packet Received 5 5 read-write WFE Wake-Up Frame Enable 2 2 read-write MPE Magic Packet Enable 1 1 read-write PD Power Down 0 0 read-write LPICSR LPI Control and Status Register 0x30 32 read-write 0x00000000 0x000F030F LPITXA LPI TX Automate 19 19 read-write PLSEN PHY Link Status Enable 18 18 read-write PLS PHY Link Status 17 17 read-write LPIEN LPI Enable 16 16 read-write RLPIST Receive LPI State 9 9 read-only TLPIST Transmit LPI State 8 8 read-only RLPIEX Receive LPI Exit 3 3 read-only RLPIEN Receive LPI Entry 2 2 read-only TLPIEX Transmit LPI Exit 1 1 read-only TLPIEN Transmit LPI Entry 0 0 read-only LPITCR LPI Timers Control Register 0x34 32 read-write 0x03E80000 0x03FFFFFF LIT LPI LS TIMER 16 25 read-write TWT LPI TW TIMER 0 15 read-write ISR Interrupt Status Register 0x38 32 read-only 0x00000000 0x000006F9 LPIIS LPI Interrupt Status 10 10 read-only TSIS Time Stamp Interrupt Status 9 9 read-only COIS MMC Receive Checksum Offload Interrupt Status 7 7 read-only TIS MMC Transmit Interrupt Status 6 6 read-only RIS MMC Receive Interrupt Status 5 5 read-only MIS MMC Interrupt Status 4 4 read-only PIS PMT Interrupt Status 3 3 read-only RGIS RGMII Interrupt Status 0 0 read-only IMR Interrupt Mask Register 0x3C 32 read-write 0x00000000 0x00000609 LPIIM LPI Interrupt Mask 10 10 read-write TSIM Time Stamp Interrupt Mask 9 9 read-write PIM PMT Interrupt Mask 3 3 read-write RGIM RGMII Interrupt Mask 0 0 read-write MAR0H MAC Address0 Register (High) 0x40 32 read-write 0x8000FFFF 0x8000FFFF MO Must be one 31 31 read-only A0 MAC Address0 0 15 read-write MAR0L MAC Address0 Register (Low) 0x44 32 read-write 0xFFFFFFFF 0xFFFFFFFF A0 MAC Address0 0 31 read-write MAR1H MAC Address1 Register -High 0x48 32 read-write 0x0000FFFF 0xFF00FFFF AE Address Enable 31 31 read-write SA Source Address 30 30 read-write MBC Mask Byte Control 24 29 read-write A MAC Address 0 15 read-write MAR1L MAC Address1 Register -Low 0x4C 32 read-write 0xFFFFFFFF 0xFFFFFFFF A MAC Address 0 31 read-write MAR2H MAC Address2 Register -High 0x50 MAR2L MAC Address2 Register -Low 0x54 MAR3H MAC Address3 Register -High 0x58 MAR3L MAC Address3 Register -Low 0x5C MAR4H MAC Address4 Register -High 0x60 MAR4L MAC Address4 Register -Low 0x64 MAR5H MAC Address5 Register -High 0x68 MAR5L MAC Address5 Register -Low 0x6C MAR6H MAC Address6 Register -High 0x70 MAR6L MAC Address6 Register -Low 0x74 MAR7H MAC Address7 Register -High 0x78 MAR7L MAC Address7 Register -Low 0x7C MAR8H MAC Address8 Register -High 0x80 MAR8L MAC Address8 Register -Low 0x84 MAR9H MAC Address9 Register -High 0x88 MAR9L MAC Address9 Register -Low 0x8C MAR10H MAC Address10 Register -High 0x90 MAR10L MAC Address10 Register -Low 0x94 MAR11H MAC Address11 Register -High 0x98 MAR11L MAC Address11 Register -Low 0x9C MAR12H MAC Address12 Register -High 0xA0 MAR12L MAC Address12 Register -Low 0xA4 MAR13H MAC Address13 Register -High 0xA8 MAR13L MAC Address13 Register -Low 0xAC MAR14H MAC Address14 Register -High 0xB0 MAR14L MAC Address14 Register -Low 0xB4 MAR15H MAC Address15 Register -High 0xB8 MAR15L MAC Address15 Register -Low 0xBC RGSR RGMII Status Register) 0xD8 32 read-only 0x00000000 0x0000000F LS Link Status 3 3 read-only LSP Link Speed 1 2 read-only LM Link Mode 0 0 read-only mmc_cntl MMC Control Register 0x100 32 read-write 0x00000000 0x0000003F mmc_intr_rx Receive Interrupt Register 0x104 32 read-only 0x00000000 0x00FFFFFF mmc_intr_tx MMC Transmit Interrupt Register 0x108 32 read-only 0x00000000 0x01FFFFFF mmc_intr_mask_rx MMC Receive Interrupt Mask Register 0x10C 32 read-write 0x00000000 0x00FFFFFF mmc_intr_mask_tx MMC Transmit Interrupt Mask Register 0x110 32 read-write 0x00000000 0x01FFFFFF txoctetcount_gb "Number of bytes transmitted, exclusive of preamble and retried bytes, in good and bad frames" 0x114 32 read-only 0x00000000 0xFFFFFFFF txframecount_gb "Number of good and bad frames transmitted, exclusive of retried frames" 0x118 32 read-only 0x00000000 0xFFFFFFFF txbroadcastframes_g Number of good broadcast frames transmitted 0x11C 32 read-only 0x00000000 0xFFFFFFFF txmulticastframes_g Number of good multicast frames transmitted 0x120 32 read-only 0x00000000 0xFFFFFFFF tx64octets_gb "Number of good and bad frames transmitted with length of 64 bytes, exclusive of preamble and retried frames" 0x124 32 read-only 0x00000000 0xFFFFFFFF tx65to127octets_gb "Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames" 0x128 32 read-only 0x00000000 0xFFFFFFFF tx128to255octets_gb "Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames" 0x12C 32 read-only 0x00000000 0xFFFFFFFF tx256to511octets_gb "Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames" 0x130 32 read-only 0x00000000 0xFFFFFFFF tx512to1023octets_gb "Number of good and bad frames transmitted with length between 512 and 1023 (inclusive) bytes, exclusive of preamble and retried frames" 0x134 32 read-only 0x00000000 0xFFFFFFFF tx1024tomaxoctets_gb "Number of good and bad frames transmitted with length between 1024 and Maxsize (inclusive) bytes, exclusive of preamble and retried frames" 0x138 32 read-only 0x00000000 0xFFFFFFFF txunicastframes_gb Number of good and bad unicast frames transmitted 0x13C 32 read-only 0x00000000 0xFFFFFFFF txmulticastframes_gb Number of good and bad multicast frames transmitted 0x140 32 read-only 0x00000000 0xFFFFFFFF txbroadcastframes_gb Number of good and bad broadcast frames transmitted 0x144 32 read-only 0x00000000 0xFFFFFFFF txunderflowerror Number of frames aborted due to frame underflow error 0x148 32 read-only 0x00000000 0xFFFFFFFF txsinglecol_g Number of successfully transmitted frames after a single collision in Half-duplex mode 0x14C 32 read-only 0x00000000 0xFFFFFFFF txmulticol_g Number of successfully transmitted frames after more than a single collision in Half-duplex mode 0x150 32 read-only 0x00000000 0xFFFFFFFF txdeferred Number of successfully transmitted frames after a deferral in Half-duplex mode. 0x154 32 read-only 0x00000000 0xFFFFFFFF txlatecol Number of frames aborted due to late collision error. 0x158 32 read-only 0x00000000 0xFFFFFFFF txexesscol Number of frames aborted due to excessive (16) collision errors. 0x15C 32 read-only 0x00000000 0xFFFFFFFF txcarriererror Number of frames aborted due to carrier sense error (no carrier or loss of carrier). 0x160 32 read-only 0x00000000 0xFFFFFFFF txoctetcount_g "Number of bytes transmitted, exclusive of preamble, in good frames only. " 0x164 32 read-only 0x00000000 0xFFFFFFFF txframecount_g Number of good frames transmitted. 0x168 32 read-only 0x00000000 0xFFFFFFFF txexecessdef_g Number of frames aborted due to excessive deferral error (deferred for more than two max-sized frame times). 0x16C 32 read-only 0x00000000 0xFFFFFFFF txpauseframes Number of good PAUSE frames transmitted. 0x170 32 read-only 0x00000000 0xFFFFFFFF txvlanframes_g "Number of good VLAN frames transmitted, exclusive of retried frames. " 0x174 32 read-only 0x00000000 0xFFFFFFFF rxframecount_gb Number of good and bad frames received. 0x180 32 read-only 0x00000000 0xFFFFFFFF rxoctetcount_gb "Number of bytes received, exclusive of preamble, in good and bad frames. " 0x184 32 read-only 0x00000000 0xFFFFFFFF rxoctetcount_g "Number of bytes received, exclusive of preamble, only in good frames. " 0x188 32 read-only 0x00000000 0xFFFFFFFF rxbroadcastframes_g Number of good broadcast frames received. 0x18C 32 read-only 0x00000000 0xFFFFFFFF rxmulticastframes_g Number of good multicast frames received. 0x190 32 read-only 0x00000000 0xFFFFFFFF rxcrcerror Number of frames received with CRC error. 0x194 32 read-only 0x00000000 0xFFFFFFFF rxallignmenterror Number of frames received with alignment (dribble) error. Valid only in 10/100 mode. 0x198 32 read-only 0x00000000 0xFFFFFFFF rxrunterror Number of frames received with runt (64 bytes and CRC error) error. 0x19C 32 read-only 0x00000000 0xFFFFFFFF rxjabbererror Number of frames received with length greater than 1518 bytes with CRC error. 0x1A0 32 read-only 0x00000000 0xFFFFFFFF rxundersize_g "Number of frames received with length less than 64 bytes, without any errors. " 0x1A4 32 read-only 0x00000000 0xFFFFFFFF rxoversize_g Number of frames received with length greater than the maxsize without error. 0x1A8 32 read-only 0x00000000 0xFFFFFFFF rx64octets_gb "Number of good and bad frames received with length 64 bytes, exclusive of preamble. " 0x1AC 32 read-only 0x00000000 0xFFFFFFFF rx65to127octets_gb "Number of good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble. " 0x1B0 32 read-only 0x00000000 0xFFFFFFFF rx128to255octets_gb "Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. " 0x1B4 32 read-only 0x00000000 0xFFFFFFFF rx256to511octets_gb "Number of good and bad frames received with length between 256 and 511 (inclusive) bytes, exclusive of preamble. " 0x1B8 32 read-only 0x00000000 0xFFFFFFFF rx512to1023octets_gb "Number of good and bad frames received with length between 512 and 1023 (inclusive) bytes, exclusive of preamble. " 0x1BC 32 read-only 0x00000000 0xFFFFFFFF rx1024tomaxoctets_gb "Number of good and bad frames received with length between 1024 and maxsize (inclusive) bytes, exclusive of preamble. " 0x1C0 32 read-only 0x00000000 0xFFFFFFFF rxunicastframes_g Number of good unicast frames received. 0x1C4 32 read-only 0x00000000 0xFFFFFFFF rxlengtherror "Number of frames received with length error (Length type field is not the frame size), for all frames with valid length field. " 0x1C8 32 read-only 0x00000000 0xFFFFFFFF rxoutofrangetype Number of frames received with length/type field not equal to the valid frame size (>1500) 0x1CC 32 read-only 0x00000000 0xFFFFFFFF rxpauseframes Number of good and valid PAUSE frames received. 0x1D0 32 read-only 0x00000000 0xFFFFFFFF rxfifooverflow Number of missed received frames due to FIFO overflow. 0x1D4 32 read-only 0x00000000 0xFFFFFFFF rxvlanframes_gb Number of good and bad VLAN frames received. 0x1D8 32 read-only 0x00000000 0xFFFFFFFF rxwatchdogerror Number of frames received with error due to watchdog timeout error (frames with a data load larger than 2048 bytes). 0x1DC 32 read-only 0x00000000 0xFFFFFFFF mmc_ipc_intr_mask_rx MMC Receive Checksum Offload Interrupt Mask Register 0x200 32 read-write 0x00000000 0x3FFF3FFF mmc_ipc_intr_rx MMC Receive Checksum Offload Interrupt Register 0x208 32 read-only 0x00000000 0x3FFF3FFF rxipv4_gd_frms "Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload " 0x210 32 read-only 0x00000000 0xFFFFFFFF rxipv4_hdrerr_frms "Number of IPv4 datagrams received with header errors (checksum, length, or version mismatch) " 0x214 32 read-only 0x00000000 0xFFFFFFFF rxipv4_nopay_frms "Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine " 0x218 32 read-only 0x00000000 0xFFFFFFFF rxipv4_frag_frms Number of good IPv4 datagrams with fragmentation 0x21C 32 read-only 0x00000000 0xFFFFFFFF rxipv4_udsbl_frms Number of good IPv4 datagrams received that had a UDP payload with checksum disabled 0x220 32 read-only 0x00000000 0xFFFFFFFF rxipv6_gd_frms "Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads " 0x224 32 read-only 0x00000000 0xFFFFFFFF rxipv6_hdrerr_frms Number of IPv6 datagrams received with header errors (length or version mismatch) 0x228 32 read-only 0x00000000 0xFFFFFFFF rxipv6_nopay_frms "Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers " 0x22C 32 read-only 0x00000000 0xFFFFFFFF rxudp_gd_frms Number of good IP datagrams with a good UDP payload. This counter is not updated when the rxipv4_udsbl_frms counter is incremented. 0x230 32 read-only 0x00000000 0xFFFFFFFF rxudp_err_frms Number of good IP datagrams whose UDP payload has a checksum error 0x234 32 read-only 0x00000000 0xFFFFFFFF rxtcp_gd_frms Number of good IP datagrams with a good TCP payload 0x238 32 read-only 0x00000000 0xFFFFFFFF rxtcp_err_frms Number of good IP datagrams whose TCP payload has a checksum error 0x23C 32 read-only 0x00000000 0xFFFFFFFF rxicmp_gd_frms Number of good IP datagrams with a good ICMP payload 0x240 32 read-only 0x00000000 0xFFFFFFFF rxicmp_err_frms Number of good IP datagrams whose ICMP payload has a checksum error 0x244 32 read-only 0x00000000 0xFFFFFFFF rxipv4_gd_octets "Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter or in the octet counters listed below). " 0x250 32 read-only 0x00000000 0xFFFFFFFF rxipv4_hdrerr_octets "Number of bytes received in IPv4 datagrams with header errors (checksum, length, version mismatch). The value in the Length field of IPv4 header is used to update this counter. " 0x254 32 read-only 0x00000000 0xFFFFFFFF rxipv4_nopay_octets "Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv4 header's Length field is used to update this counter. " 0x258 32 read-only 0x00000000 0xFFFFFFFF rxipv4_frag_octets Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 header's Length field is used to update this counter. 0x25C 32 read-only 0x00000000 0xFFFFFFFF rxipv4_udsbl_octets Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. 0x260 32 read-only 0x00000000 0xFFFFFFFF rxipv6_gd_octets "Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data" 0x264 32 read-only 0x00000000 0xFFFFFFFF rxipv6_hdrerr_octets "Number of bytes received in IPv6 datagrams with header errors (length, version mismatch). The value in the IPv6 header's Length field is used to update this counter. " 0x268 32 read-only 0x00000000 0xFFFFFFFF rxipv6_nopay_octets "Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv6 header's Length field is used to update this counter. " 0x26C 32 read-only 0x00000000 0xFFFFFFFF rxudp_gd_octets Number of bytes received in a good UDP segment. This counter (and the counters below) does not count IP header bytes. 0x270 32 read-only 0x00000000 0xFFFFFFFF rxudp_err_octets Number of bytes received in a UDP segment that had checksum errors 0x274 32 read-only 0x00000000 0xFFFFFFFF rxtcp_gd_octets Number of bytes received in a good TCP segment 0x278 32 read-only 0x00000000 0xFFFFFFFF rxtcp_err_octets Number of bytes received in a TCP segment with checksum errors 0x27C 32 read-only 0x00000000 0xFFFFFFFF rxicmp_gd_octets Number of bytes received in a good ICMP segment 0x280 32 read-only 0x00000000 0xFFFFFFFF rxicmp_err_octets Number of bytes received in an ICMP segment with checksum errors 0x284 32 read-only 0x00000000 0xFFFFFFFF TSCR Time Stamp Control Register 0x700 32 read-write 0x00002000 0x0107FF3F ATSFC Auxiliary Snapshot FIFO Clear 24 24 read-write TSENMF Enable MAC address for PTP frame filtering 18 18 read-write TSPS SelectPTP packets for taking snapshots 16 17 read-write TSMRM Enable Snapshot for Messages Relevant to Master 15 15 read-write TETSEM Enable Time Stamp Snapshot for Event Messages 14 14 read-write TSIP4E Enable Time Stamp Snapshot for IPv4 frames 13 13 read-write TSIP6E Enable Time Stamp Snapshot for IPv6 frames 12 12 read-write TETSP Enable Time Stamp Snapshot for PTP over Ethernet frames 11 11 read-write TSV2E Enable PTP packet snooping for version 2 format 10 10 read-write TSDB Time Stamp Digital or Binary rollover control 9 9 read-write TSEA Enable Time Stamp for All Frames 8 8 read-write TARU Addend Register Update 5 5 read-write TITE Time Stamp Interrupt Trigger Enable 4 4 read-write TSU Time Stamp Update 3 3 read-write TSI Time Stamp Initialize 2 2 read-write TFCU Time Stamp Fine or Coarse Update 1 1 read-write TSE Time Stamp Enable 0 0 read-write SSIR Sub-Second Increment Register 0x704 32 read-write 0x00000000 0x000000FF SSINC Sub-Second Increment Value 0 7 read-write STSR System Time - Seconds Register 0x708 32 read-only 0x00000000 0xFFFFFFFF TSS Time Stamp Second 0 31 read-only STNR System Time - Nanoseconds Register 0x70C 32 read-only 0x00000000 0x7FFFFFFF TSSS Time Stamp Sub-Seconds 0 30 read-only STSUR System Time - Seconds Update Register 0x710 32 read-write 0x00000000 0xFFFFFFFF TSS Time Stamp Second 0 31 read-write STNUR System Time - Nanoseconds Update Register 0x714 32 read-write 0x00000000 0xFFFFFFFF ADDSUB Add or Subtract Time 31 31 read-write TSSS Time Stamp Sub-Seconds 0 30 read-write TSAR Time Stamp Addend Register 0x718 32 read-write 0x00000000 0xFFFFFFFF TSAR Time Stamp Addend Register 0 31 read-write TTSR Target Time Seconds Register 0x71C 32 read-write 0x00000000 0xFFFFFFFF TSTR Target Time Stamp Seconds Register 0 31 read-write TTNR Target Time Nanoseconds Register 0x720 32 read-write 0x00000000 0x7FFFFFFF TSTR Target Time Stamp Nanoseconds Register 0 30 read-write STHWSR System Time - Higher Word Seconds Register 0x724 32 read-write 0x00000000 0x0000FFFF TSHWR Time Stamp Higher Word Register 0 15 read-write TSR Time Stamp Status Register 0x728 32 read-only 0x00000000 0x0F00000F ATSNS Auxiliary Time Stamp Number of Snapshots 25 27 read-only ATSSTM Auxiliary Time Stamp Snapshot Trigger Missed 24 24 read-only TRGTER Timestamp Target Time Error 3 3 read-only ATSTS Auxiliary Time Stamp Trigger Snapshot 2 2 read-only TSTART Time Stamp Target Time Reached 1 1 read-only TSSOVF Time Stamp Seconds Overflow 0 0 read-only PPSCR PPS Control Register 0x72C 32 read-write 0x00000000 0x0000000F PPSCTRL Controls the frequency of the PPS output 0 3 read-only ATNR Auxiliary Time Stamp - Nanoseconds Register 0x730 32 read-only 0x00000000 0x7FFFFFFF ATN ATN 0 30 read-only ATSR Auxiliary Time Stamp - Seconds Register 0x734 32 read-only 0x00000000 0xFFFFFFFF ATS ATS 0 31 read-only MAR16H MAC Address16 Register -High 0x800 MAR16L MAC Address16 Register -Low 0x804 MAR17H MAC Address17 Register -High 0x808 MAR17L MAC Address17 Register -Low 0x80C MAR18H MAC Address18 Register -High 0x810 MAR18L MAC Address18 Register -Low 0x814 MAR19H MAC Address19 Register -High 0x818 MAR19L MAC Address19 Register -Low 0x81C MAR20H MAC Address20 Register -High 0x820 MAR20L MAC Address20 Register -Low 0x824 MAR21H MAC Address21 Register -High 0x828 MAR21L MAC Address21 Register -Low 0x82C MAR22H MAC Address22 Register -High 0x830 MAR22L MAC Address22 Register -Low 0x834 MAR23H MAC Address23 Register -High 0x838 MAR23L MAC Address23 Register -Low 0x83C MAR24H MAC Address24 Register -High 0x840 MAR24L MAC Address24 Register -Low 0x844 MAR25H MAC Address25 Register -High 0x848 MAR25L MAC Address25 Register -Low 0x84C MAR26H MAC Address26 Register -High 0x850 MAR26L MAC Address26 Register -Low 0x854 MAR27H MAC Address27 Register -High 0x858 MAR27L MAC Address27 Register -Low 0x85C MAR28H MAC Address28 Register -High 0x860 MAR28L MAC Address28 Register -Low 0x864 MAR29H MAC Address29 Register -High 0x868 MAR29L MAC Address29 Register -Low 0x86C MAR30H MAC Address30 Register -High 0x870 MAR30L MAC Address30 Register -Low 0x874 MAR31H MAC Address31 Register -High 0x878 MAR31L MAC Address31 Register -Low 0x87C BMR Bus Mode Register 0x1000 32 read-write 0x00020101 0x0FFFFFFF TXPR Transmit Priority 27 27 read-write MB Mixed Burst 26 26 read-write AAL Address-Aligned Beats 25 25 read-write _8XPBL 8xPBL Mode 24 24 read-write USP Use Separate PBL 23 23 read-write RPBL RxDMA PBL 17 22 read-write FB Fixed Burst 16 16 read-write PR Rx:Tx priority ratio 14 15 read-write PBL Programmable Burst Length 8 13 read-write ATDS Alternate Descriptor Size 7 7 read-write DSL Descriptor Skip Length 2 6 read-write DA DMA Arbitration scheme 1 1 read-write SWR Software Reset 0 0 read-write TPDR Transmit Poll Demand Register) 0x1004 32 read-write 0x00000000 0xFFFFFFFF TPD Transmit Poll Demand 0 31 read-write RPDR Receive Poll Demand Register 0x1008 32 read-write 0x00000000 0xFFFFFFFF RPD Receive Poll Demand 0 31 read-write RDLAR Receive Descriptor List Address Register) 0x100C 32 read-write 0x00000000 0xFFFFFFFC SRL Start of Receive List 2 31 read-write TDLAR Transmit Descriptor List Address Register 0x1010 32 read-write 0x00000000 0xFFFFFFFC STL Start of Transmit List 2 31 read-write SR Status Register 0x1014 32 read-only 0x00000000 0x7FFFE7FF GLPII GMAC LPI Interrupt 30 30 read-only TTI Time-Stamp Trigger Interrupt 29 29 read-only GPI GMAC PMT Interrupt 28 28 read-only GMI GMAC MMC Interrupt 27 27 read-only GLI GMAC Line interface Interrupt 26 26 read-only EB Error Bits 23 25 read-only TS Transmit Process State 20 22 read-only RS Receive Process State 17 19 read-only NIS Normal Interrupt Summary 16 16 read-only AIS Abnormal Interrupt Summary 15 15 read-only ERI Early Receive Interrupt 14 14 read-only FBI Fatal Bus Error Interrupt 13 13 read-only ETI Early Transmit Interrupt 10 10 read-only RWT Receive Watchdog Timeout 9 9 read-only RPS Receive process Stopped 8 8 read-only RU Receive Buffer Unavailable 7 7 read-only RI Receive Interrupt 6 6 read-only UNF Transmit underflow 5 5 read-only OVF Receive Overflow 4 4 read-only TJT Transmit Jabber Timeout 3 3 read-only TU Transmit Buffer Unavailable 2 2 read-only TPS Transmit Process Stopped 1 1 read-only TI Transmit Interrupt 0 0 read-only OMR Operation Mode Register 0x1018 32 read-write 0x00000000 0x0731E0DE DT Disable Dropping of TCP/IP Checksum Error Frames 26 26 read-write RSF Receive Store and Forward 25 25 read-write DFF Disable Flushing of Received Frames 24 24 read-write TSF Transmit Store Forward 21 21 read-write FTF Flush Transmit FIFO 20 20 read-write TTC Transmit Threshold Control 14 16 read-write ST Start/Stop Transmission Command 13 13 read-write FEF Forward Error Frames 7 7 read-write FUF Forward Undersized Good Frames 6 6 read-write RTC Receive Threshold Control 3 4 read-write OSF Operate on Second Frame 2 2 read-write SR Start/Stop Receive 1 1 read-write IER Interrupt Enable Register 0x101C 32 read-write 0x00000000 0x0001E7FF NIE Normal Interrupt Summary Enable 16 16 read-write AIE Abnormal Interrupt Summary Enable 15 15 read-write ERE Early Receive Interrupt Enable 14 14 read-write FBE Fatal Bus Error Enable 13 13 read-write ETE Early Transmit Interrupt Enable 10 10 read-write RWE Receive Watchdog Timeout Enable 9 9 read-write RSE Receive Process Stopped Enable 8 8 read-write RUE Receive Buffer Unavailable Enable 7 7 read-write RIE Receive Interrupt Enable 6 6 read-write UNE Transmit underflow Enable 5 5 read-write OVE Receive Overflow Enable 4 4 read-only TJE Transmit Jabber Timeout 3 3 read-write TUE Transmit Buffer Unavailable 2 2 read-write TSE Transmit Process Stopped 1 1 read-write TIE Transmit Interrupt 0 0 read-write MFBOCR Missed Frame and Buffer Overflow Counter Register 0x1020 32 read-only 0x00000000 0x1FFFFFFF ONMFF Overflow NMFF 28 28 read-only NMFF Number of Missed frame by Ethernet-MAC 17 27 read-only ONMFH Overflow NMFH 16 16 read-only NMFH Number of Missed frame by HOST 0 15 read-only RIWTR Receive Interrupt Watchdog Timer Register 0x1024 32 read-only 0x00000000 0x000000FF RIWT RI Watchdog Timer count 0 7 read-only AHBSR AHB Status Register 0x102C 32 read-only 0x00000000 0x00000001 AHBS AHB Status 0 0 read-only CHTDR Current Host Transmit Descriptor Register 0x1048 32 read-only 0x00000000 0xFFFFFFFF HTDAP Host Transmit Descriptor Address Pointer 0 31 read-only CHRDR Current Host Receive Descriptor Register 0x104C 32 read-only 0x00000000 0xFFFFFFFF HRDAP Host Receive Descriptor Address Pointer 0 31 read-only CHTBAR Current Host Transmit Buffer Address Register 0x1050 32 read-only 0x00000000 0xFFFFFFFF HTBAR Host Transmit Buffer Address Register 0 31 read-only CHRBAR Current Host Receive Buffer Address Register 0x1054 32 read-only 0x00000000 0xFFFFFFFF HRBAR Host Receive Buffer Address Register 0 31 read-only ETHERNET_CONTROL Ethernet system control ETHERNET_CONTROL 0x40066000 0x0 0x4 registers 0x8 0x4 registers ETH_MODE Mode Select Register 0x0 32 read-write 0x00000000 0x10000301 PPSSEL Select either of the system time counter pulse outputs of the Ethernet-MAC PTP function to output to E_PPS0_PPS1 pin 28 28 read-write RST1 reset signal against Ethernet-MAC (ch.1) 9 9 read-write RST0 reset signal against Ethernet-MAC (ch.0) 8 8 read-write IFMODE Mode selector 0 0 read-write ETH_CLKG Clock Gating Register 0x8 32 read-write 0x00000000 0x00000003 MACEN Select the system clock supply to Ethernet-MAC 0 1 read-write I2SPRE I2S Clock Generation I2SPRE 0x4003D000 0x0 0x4 registers 0x4 0x4 registers 0x8 0x4 registers 0xC 0x4 registers 0x10 0x4 registers 0x14 0x4 registers 0x18 0x4 registers 0x1C 0x4 registers 0x20 0x4 registers 0x24 0x4 registers TIM 59 ICCR I2S Clock Control Register 0x0 32 read-write 0x00000000 0x00000003 ICSEL I2S clock selection bit 1 1 read-write ICEN I2S clock output enable bit 0 0 read-write IPCR1 I2S-PLL Control Register 1 0x4 32 read-write 0x00000000 0x00000001 IPLLEN I2S-PLL oscillation enable bit 0 0 read-write IPCR2 I2S-PLL Control Register 2 0x8 32 read-write 0x00000000 0x00000007 IPOWT I2S-PLL oscillation stabilization wait time setting bits 0 2 read-write IPCR3 I2S-PLL Control Register 3 0xC 32 read-write 0x00000001 0x0000001F IPLLK Frequency division ratio (K) setting bits of the I2S-PLL clock 0 4 read-write IPCR4 I2S-PLL Control Register 4 0x10 32 read-write 0x0000001F 0x0000007F IPLLN Frequency division ratio (N) setting bits of the I2S-PLL clock 0 6 read-write IP_STR I2S-PLL Status Register 0x14 32 read-write 0x00000000 0x00000001 IPRDY I2S-PLL oscillation stabilization bit 0 0 read-only IPINT_ENR I2S-PLL Interrupt Factor Enable Register 0x18 32 read-write 0x00000000 0x00000001 IPCSE I2S-PLL oscillation stabilization wait complete interrupt enable bit 0 0 read-write IPINT_CLR I2S-PLL Interrupt Factor Status Register 0x1C 32 read-write 0x00000000 0x00000001 IPCSC I2S-PLL interrupt factor status bit 0 0 write-only IPINT_STR I2S-PLL Interrupt Factor Clear Register 0x20 32 read-write 0x00000000 0x00000001 IPCSI I2S-PLL oscillation stabilization interrupt factor clear bit 0 0 read-only IPCR5 I2S-PLL Control Register 5 0x24 32 read-write 0x00000018 0x0000007F IPLLM Frequency division ratio (M) setting bits of the I2S-PLL clock 0 6 read-write I2S0 I2S I2S0 0x4006C000 0x0 0x4 registers 0x4 0x4 registers 0x8 0x4 registers 0xC 0x4 registers 0x10 0x4 registers 0x14 0x4 registers 0x18 0x4 registers 0x1C 0x4 registers 0x20 0x4 registers 0x24 0x4 registers 0x28 0x4 registers 0x2C 0x4 registers PRGCRC_I2S 117 RXFDAT Receive FIFO Register 0x0 32 read-only 0x00000000 0xFFFFFFFF RXDATA Words received from the serial bus are written to the receive FIFO 0 31 read-only TXFDAT Transmit FIFO Register 0x4 32 read-write 0x00000000 0xFFFFFFFF TXDATA As long as the transmit FIFO is not full, the words to be transmitted can be written. 0 31 write-only CNTREG Control Register 0x8 32 read-write 0x00000000 0xFFFF7FFF CKRT When operating in master mode, this sets the clock division ratio for output. 26 31 read-write OVHD Following the valid data of the frame, it can insert OVERHEAD bits to enable adjustment of the frame rate. 16 25 read-write MSKB This sets the serial output data of the invalid transmit frames 14 14 read-write MSMD This sets master or slave mode. 13 13 read-write SBFN This specifies the subframe configuration (number of subframes) of the frame 12 12 read-write RHLL This sets the FIFO word configuration to one or two words 11 11 read-write ECKM In master mode, this selects the base clock divider. 10 10 read-write BEXT When the receive word length is smaller than the FIFO word length, this sets the upper bit extension mode. 9 9 read-write FRUN This sets the output mode of the frame sync signal 8 8 read-write MLSB This sets word bit shift order 7 7 read-write TXDIS This enables or disables the transmit function 6 6 read-write RXDIS This enables or disables the receive function 5 5 read-write SMPL This specifies the point where data is sampled 4 4 read-write CPOL This specifies the I2SCK polarity where drive sampling of the serial data is performed 3 3 read-write FSPH This specifies the phase for I2SWS frame data 2 2 read-write FSLN This specifies the pulse width of I2SWS 1 1 read-write FSPL This sets the polarity of the I2SWS pin 0 0 read-write MCR0REG Channel Control Register 0 0xC 32 read-write 0x00000000 0x7FFF7FFF S1CHN This sets the number of channels for subframe 1 26 30 read-write S1CHL This sets the channel length of the channels that make up subframe 1 21 25 read-write S1WDL This sets the word length of the channels that make up subframe 1 16 20 read-write S0CHN This sets the number of channels for subframe 0 10 14 read-write S0CHL This sets the channel length of the channels that make up subframe 1 5 9 read-write S0WDL This sets the word length of the channels that make up subframe 1 0 4 read-write MCR1REG Channel Control Register 1 0x10 32 read-write 0x00000000 0xFFFFFFFF S0CH31 This controls the enable/disable state of the channel 31 in subframe 0 31 31 read-write S0CH30 This controls the enable/disable state of the channel 30 in subframe 0 30 30 read-write S0CH29 This controls the enable/disable state of the channel 29 in subframe 0 29 29 read-write S0CH28 This controls the enable/disable state of the channel 28 in subframe 0 28 28 read-write S0CH27 This controls the enable/disable state of the channel 27 in subframe 0 27 27 read-write S0CH26 This controls the enable/disable state of the channel 26 in subframe 0 26 26 read-write S0CH25 This controls the enable/disable state of the channel 25 in subframe 0 25 25 read-write S0CH24 This controls the enable/disable state of the channel 24 in subframe 0 24 24 read-write S0CH23 This controls the enable/disable state of the channel 23 in subframe 0 23 23 read-write S0CH22 This controls the enable/disable state of the channel 22 in subframe 0 22 22 read-write S0CH21 This controls the enable/disable state of the channel 21 in subframe 0 21 21 read-write S0CH20 This controls the enable/disable state of the channel 20 in subframe 0 20 20 read-write S0CH19 This controls the enable/disable state of the channel 19 in subframe 0 19 19 read-write S0CH18 This controls the enable/disable state of the channel 18 in subframe 0 18 18 read-write S0CH17 This controls the enable/disable state of the channel 17 in subframe 0 17 17 read-write S0CH16 This controls the enable/disable state of the channel 16 in subframe 0 16 16 read-write S0CH15 This controls the enable/disable state of the channel 15 in subframe 0 15 15 read-write S0CH14 This controls the enable/disable state of the channel 14 in subframe 0 14 14 read-write S0CH13 This controls the enable/disable state of the channel 13 in subframe 0 13 13 read-write S0CH12 This controls the enable/disable state of the channel 12 in subframe 0 12 12 read-write S0CH11 This controls the enable/disable state of the channel 11 in subframe 0 11 11 read-write S0CH10 This controls the enable/disable state of the channel 10 in subframe 0 10 10 read-write S0CH09 This controls the enable/disable state of the channel 9 in subframe 0 09 09 read-write S0CH08 This controls the enable/disable state of the channel 8 in subframe 0 08 08 read-write S0CH07 This controls the enable/disable state of the channel 7 in subframe 0 07 07 read-write S0CH06 This controls the enable/disable state of the channel 6 in subframe 0 06 06 read-write S0CH05 This controls the enable/disable state of the channel 5 in subframe 0 05 05 read-write S0CH04 This controls the enable/disable state of the channel 4 in subframe 0 04 04 read-write S0CH03 This controls the enable/disable state of the channel 3 in subframe 0 03 03 read-write S0CH02 This controls the enable/disable state of the channel 2 in subframe 0 02 02 read-write S0CH01 This controls the enable/disable state of the channel 1 in subframe 0 01 01 read-write S0CH00 This controls the enable/disable state of the channel 0 in subframe 0 00 00 read-write MCR2REG Channel Control Register 2 0x14 32 read-write 0x00000000 0xFFFFFFFF S1CH31 This controls the enable/disable state of the channel 31 in subframe 1 31 31 read-write S1CH30 This controls the enable/disable state of the channel 30 in subframe 1 30 30 read-write S1CH29 This controls the enable/disable state of the channel 29 in subframe 1 29 29 read-write S1CH28 This controls the enable/disable state of the channel 28 in subframe 1 28 28 read-write S1CH27 This controls the enable/disable state of the channel 27 in subframe 1 27 27 read-write S1CH26 This controls the enable/disable state of the channel 26 in subframe 1 26 26 read-write S1CH25 This controls the enable/disable state of the channel 25 in subframe 1 25 25 read-write S1CH24 This controls the enable/disable state of the channel 24 in subframe 1 24 24 read-write S1CH23 This controls the enable/disable state of the channel 23 in subframe 1 23 23 read-write S1CH22 This controls the enable/disable state of the channel 22 in subframe 1 22 22 read-write S1CH21 This controls the enable/disable state of the channel 21 in subframe 1 21 21 read-write S1CH20 This controls the enable/disable state of the channel 20 in subframe 1 20 20 read-write S1CH19 This controls the enable/disable state of the channel 19 in subframe 1 19 19 read-write S1CH18 This controls the enable/disable state of the channel 18 in subframe 1 18 18 read-write S1CH17 This controls the enable/disable state of the channel 17 in subframe 1 17 17 read-write S1CH16 This controls the enable/disable state of the channel 16 in subframe 1 16 16 read-write S1CH15 This controls the enable/disable state of the channel 15 in subframe 1 15 15 read-write S1CH14 This controls the enable/disable state of the channel 14 in subframe 1 14 14 read-write S1CH13 This controls the enable/disable state of the channel 13 in subframe 1 13 13 read-write S1CH12 This controls the enable/disable state of the channel 12 in subframe 1 12 12 read-write S1CH11 This controls the enable/disable state of the channel 11 in subframe 1 11 11 read-write S1CH10 This controls the enable/disable state of the channel 10 in subframe 1 10 10 read-write S1CH09 This controls the enable/disable state of the channel 9 in subframe 1 09 09 read-write S1CH08 This controls the enable/disable state of the channel 8 in subframe 1 08 08 read-write S1CH07 This controls the enable/disable state of the channel 7 in subframe 1 07 07 read-write S1CH06 This controls the enable/disable state of the channel 6 in subframe 1 06 06 read-write S1CH05 This controls the enable/disable state of the channel 5 in subframe 1 05 05 read-write S1CH04 This controls the enable/disable state of the channel 4 in subframe 1 04 04 read-write S1CH03 This controls the enable/disable state of the channel 3 in subframe 1 03 03 read-write S1CH02 This controls the enable/disable state of the channel 2 in subframe 1 02 02 read-write S1CH01 This controls the enable/disable state of the channel 1 in subframe 1 01 01 read-write S1CH00 This controls the enable/disable state of the channel 0 in subframe 1 00 00 read-write OPRREG Operation Control Register 0x18 32 read-write 0x00000000 0x01010001 RXENB This sets the enabled/disabled state of the receive operation 24 24 read-write TXENB This sets the enabled/disabled state of the transmit operation 16 16 read-write START This enables or disables the I2S interface 0 0 read-write SRST Soft Reset Register 0x1C 32 read-write 0x00000000 0x00000001 SRST Soft reset bit 0 0 read-write INTCNT Interrupt Control Register 0x20 32 read-write 0x7F3F0000 0x7F3F0F3F TXUD1M This bit masks the transmit FIFO underflow interrupt 30 30 read-write TBERM This bit masks the transmit channel block size error interrupt 29 29 read-write FERRM This bit masks the frame error interrupt mask 28 28 read-write TXUD0M This bit masks the transmit FIFO underflow interrupt 27 27 read-write TXOVM This bit masks the transmit FIFO overflow interrupt 26 26 read-write TXFDM This bit masks the transmit DMA request 25 25 read-write TXFIM This bit masks the transmit FIFO interrupt 24 24 read-write RBERM This bit masks the receive channel block size error interrupt 21 21 read-write RXUDM This bit masks the receive FIFO underflow interrupt 20 20 read-write RXOVM This bit masks the receive FIFO overflow interrupt 19 19 read-write EOPM This bit masks the interrupts by EOPI of the STATUS register 18 18 read-write RXFDM This bit masks the receive DMA request 17 17 read-write RXFIM This bit masks the receive FIFO interrupt 16 16 read-write TFTH This bit sets the transmit FIFO threshold value 8 11 read-write RPTMR This is the bit for setting the packet receive completion timer 4 5 read-write RFTH This bit sets the receive FIFO threshold value 0 3 read-write STATUS Status Register 0x24 32 read-write 0x00000000 0xFF0FFFFF TBERR If the block size of the DMA transmit channel is set to a value larger than the transmit FIFO threshold value, this bit is set to 1. 31 31 read-only RBERR If the block size of the DMA receive channel is set to a value larger than the receive FIFO threshold value, this bit is set to 1. 30 30 read-only FERR This indicates that a frame error has occurred 29 29 read-write TXUDR1 This is set to 1 when the transmit FIFO underflows at the frame start 28 28 read-write TXUDR0 This is set to 1 when the transmit FIFO underflows during frame transmission 27 27 read-write TXOVR This is set to 1 when the transmit FIFO overflows 26 26 read-write RXUDR This is set to 1 when the receive FIFO underflows 25 25 read-write RXOVR This is set to 1 when the receive FIFO overflows 24 24 read-write EOPI This is the interrupt flag based on the receive timer 19 19 read-write BSY This indicates the status of the serial transmit control unit 18 18 read-only TXFI This is set to 1 when the transmit FIFO empty slot meets or exceeds the threshold value 17 17 read-only RXFI This is set to 1 when the receive FIFO data count meets or exceeds the threshold value 16 16 read-only TXNUM This indicates the data count in the transmit FIFO 8 15 read-only RXNUM This indicates the data count in the receive FIFO 0 7 read-only DMAACT DMA Startup Register 0x28 32 read-write 0x00000000 0x01010101 TL1E0 This sets the operation mode of TXDREQ 24 24 read-write TDMACT This bit is enabled when the same register TL1E0=0 16 16 read-write RL1E0 This sets the operation mode of RXDREQ 8 8 read-write RDMACT This bit is enabled when the same register RL1E0=0 0 0 read-write TSTREG Test Register 0x2C 32 read-write 0x00000000 0x00000001 LBMD This sets the loopback mode 0 0 read-write SDIF SD Card Interface SDIF 0x4006E000 0x0 0x1000 registers SD 118 DUMMY Dummy 0x0 32 read-write 0x00 0x00 PCRC 0 PCRC 0x40080000 0x0 0x4 registers 0x4 0x4 registers 0x8 0x4 registers 0xC 0x4 registers 0x10 0x4 registers 0x14 0x4 registers PRGCRC_I2S 117 PRGCRC_POLY CRC Computing Generator Polynomial Register 0x0 32 read-write 0x04C11DB7 0xFFFFFFFF PRGCRC_SEED CRC Computing Initial Value Register 0x4 32 read-write 0xFFFFFFFF 0xFFFFFFFF PRGCRC_FXOR CRC Computing Resault XOR Value Register 0x8 32 read-write 0xFFFFFFFF 0xFFFFFFFF PRGCRC_CFG CRC Computing Configuration Register 0xC 32 read-write 0x00E00000 0xFFFFFFFF LOCK Lock 28 28 read-only CDEN DMA request enable 26 26 read-write CIEN Interrupt request enable 25 25 read-write CIRQ Interrupt request 24 24 read-only SZ Input data size 22 23 read-write TEST Test 16 21 read-write FI Input data format 10 11 read-write FO output data format 8 9 read-write CIRQCLR Interrupt request clear 0 0 write-only PRGCRC_WR CRC Computing Input Data Register 0x10 32 read-write 0x00000000 0xFFFFFFFF PRGCRC_RD CRC Computing Output Data Register 0x14 32 read-write 0x00000000 0xFFFFFFFF HSSPI HI-SPEED SPI Controller HSSPI 0xD0000000 0x0 0x4 registers 0x4 0x4 registers 0x8 0x4 registers 0xC 0x4 registers 0x10 0x4 registers 0x14 0x4 registers 0x18 0x4 registers 0x1C 0x4 registers 0x20 0x4 registers 0x24 0x4 registers 0x28 0x4 registers 0x2C 0x4 registers 0x30 0x4 registers 0x34 0x1 registers 0x35 0x1 registers 0x38 0x1 registers 0x39 0x1 registers 0x3A 0x1 registers 0x3B 0x1 registers 0x3C 0x2 registers 0x3E 0x2 registers 0x40 0x4 registers 0x4C 0x4 registers 0x50 0x64 registers 0x90 0x64 registers 0xD0 0x4 registers 0xD4 0x4 registers 0xD8 0x4 registers 0xDC 0x32 registers 0xFC 0x4 registers 0x400 0x1 registers 0x404 0x1 registers HSSPI 115 MCTRL Control Register 0x00 32 read-write 0x00000000 0x00000033 SYNCON Synchronizer circuit operation bit 5 5 read-write MES Module enable status bit 4 4 read-only CSEN Command sequencer mode enable bit 1 1 read-write MEN Module enable bit 0 0 read-write PCC0 Peripheral Communication Setting Register 0 0x04 32 read-write 0x00000000 0x007FFFFF RDDSEL Read deselect time setting bits 21 22 read-write WRDSEL Write or different command deselect time setting bits 17 20 read-write SAFESYNC Safe synchronization bit 16 16 read-write CDRS Clock division ratio setting bits 9 15 read-write SENDIAN Endian setting bit 8 8 read-write SDIR Shift direction setting bit 7 7 read-write SS2CD Slave-select-to-clock-start delay time setting bit 5 6 read-write SSPOL Slave select polarity setting bit 4 4 read-write RTM Timing compensation setting bit 3 3 read-write ACES Serial data transmission/reception timing setting bit 2 2 read-write CPOL Serial clock polarity setting bit 1 1 read-write CPHA Clock phase setting bit 0 0 read-write PCC1 Peripheral Communication Setting Registers 1 0x08 PCC2 Peripheral Communication Setting Registers 2 0x0C PCC3 Peripheral Communication Setting Registers 3 0x10 TXF Transmission Interrupt Factor Register 0x14 32 read-only 0x00000000 0x0000007F TSSRS Slave select released detection bit 6 6 read-only TFMTS TX-FIFO-exceeded-threshold detection bit 5 5 read-only TFLETS TX-FIFO-less-than-or-equal-to-threshold detection bit 4 4 read-only TFUS TX-FIFO underrun detection bit 3 3 read-only TFOS TX-FIFO overrun detection bit 2 2 read-only TFES TX-FIFO and shift register empty detection bit 1 1 read-only TFFS TX-FIFO full detection bit 0 0 read-only TXE Transmission Interrupt Enable Register 0x18 32 read-write 0x00000000 0x0000007F TSSRE Slave select released detection interrupt enable bit 6 6 read-write TFMTE TX-FIFO-exceeded-threshold detection interrupt enable bit 5 5 read-write TFLETE TX-FIFO-less-than-or-equal-to-threshold detection interrupt enable bit 4 4 read-write TFUE TX-FIFO underrun detection interrupt enable bit 3 3 read-write TFOE TX-FIFO overrun detection interrupt enable bit 2 2 read-write TFEE TX-FIFO and shift register empty detection interrupt enable bit 1 1 read-write TFFE TX-FIFO full detection interrupt enable bit 0 0 read-write TXC Transmission Interrupt Clear Register 0x1C 32 write-only 0x00000000 0x0000007F TSSRC Slave select released detection clear bit 6 6 write-only TFMTC TX-FIFO-exceeded-threshold detection clear bit 5 5 write-only TFLETC TX-FIFO-less-than-or-equal-to-threshold detection clear bit 4 4 write-only TFUC TX-FIFO underrun detection clear bit 3 3 write-only TFOC TX-FIFO overrun detection clear bit 2 2 write-only TFEC TX-FIFO and shift register empty detection clear bit 1 1 write-only TFFC TX-FIFO full detection clear bit 0 0 write-only RXF Reception Interrupt Factor Register 0x20 32 read-only 0x00000000 0x0000007F RSSRS Slave select released detection bit 6 6 read-only RFMTS RX-FIFO-exceeded-threshold detection bit 5 5 read-only RFLETS RX-FIFO-less-than-or-equal-to-threshold detection bit 4 4 read-only RFUS RX-FIFO underrun detection bit 3 3 read-only RFOS RX-FIFO overrun detection bit 2 2 read-only RFES RX-FIFO empty detection bit 1 1 read-only RFFS RX-FIFO full detection bit 0 0 read-only RXE Reception Interrupt Enable Register 0x24 32 read-write 0x00000000 0x0000007F RSSRE Slave select released detection interrupt enable bit 6 6 read-write RFMTE RX-FIFO-exceeded-threshold detection interrupt enable bit 5 5 read-write RFLETE RX-FIFO-less-than-or-equal-to-threshold detection interrupt enable bit 4 4 read-write RFUE RX-FIFO underrun detection interrupt enable bit 3 3 read-write RFOE RX-FIFO overrun detection interrupt enable bit 2 2 read-write RFEE RX-FIFO and shift register empty-state detection interrupt enable bit 1 1 read-write RFFE RX-FIFO full detection interrupt enable bit 0 0 read-write RXC Interrupt Clear Register 0x28 32 write-only 0x00000000 0x0000007F RSSRC Slave select released detection clear bit 6 6 write-only RFMTC RX-FIFO-exceeded-threshold detection clear bit 5 5 write-only RFLETC RX-FIFO-less-than-or-equal-to-threshold detection clear bit 4 4 write-only RFUC RX-FIFO underrun detection clear bit 3 3 write-only RFOC RX-FIFO overrun detection clear bit 2 2 write-only RFEC RX-FIFO and shift register empty-state detection clear bit 1 1 write-only RFFC RX-FIFO full detection clear bit 0 0 write-only FAULTF Fault Interrupt Factor Register 0x2C 32 read-only 0x00000000 0x0000001F DRCBSFS DRCBSFS 4 4 read-only DWCBSFS DWCBSFS 3 3 read-only PVFS Protection violation fault detection bit 2 2 read-only WAFS Write access fault detection bit 1 1 read-only UMAFS Unmapped memory access fault detection bit 0 0 read-only FAULTC Fault Interrupt Clear Register 0x30 32 write-only 0x00000000 0x0000001F DRCBSFC DRCBSFC 4 4 write-only DWCBSFC DWCBSFC 3 3 write-only PVFC Protection violation fault detection clear bit 2 2 write-only WAFC Write access fault detection clear bit 1 1 write-only UMAFC Unmapped memory access fault detection clear bit 0 0 write-only DMCFG Direct Mode Setting Register 0x34 8 read-write 0x01 0x02 SSDC Slave select deassertion setting bit 1 1 read-write DMDMAEN DMDMAEN 0x35 8 read-write 0x00 0x03 TXDMAEN TXDMAEN 1 1 read-write RXDMAEN RXDMAEN 0 0 read-write DMSTART Direct Mode Transfer Start Control Register 0x38 8 read-write 0x00 0x01 START Transfer start bit 0 0 read-write DMSTOP Direct Mode Transfer Stop Control Register 0x39 8 read-write 0x00 0x01 STOP Transfer stop bit 0 0 read-write DMPSEL Direct Mode Slave Select Register 0x3A 8 read-write 0x00 0x03 PSEL Peripheral select bits 0 1 read-write DMTRP Direct Mode Transfer Protocol Setting Register 0x3B 8 read-write 0x00 0x0F TRP Transfer protocol setting bits 0 3 read-write DMBCC Direct Mode Transfer Byte Count Setting Register 0x3C 16 read-write 0x0000 0xFFFF BCC Transferred byte count setting value 0 15 read-write DMBCS Direct Mode Transfer Remaining Count Register 0x3E 16 read-only 0x0000 0xFFFF BCS Number of remaining bytes to transfer 0 15 read-only DMSTATUS Direct Mode Status Register 0x40 32 read-only 0x00000000 0x001F1F03 TXFLEVEL Remaining TX-FIFO data indication bits 16 20 read-only RXFLEVEL Remaining RX-FIFO data indication bits 8 12 read-only TXACTIVE Transmission status bit 1 1 read-only RXACTIVE Reception status bit 0 0 read-only FIFOCFG FIFO Setting Register 0x4C 32 read-write 0x00000077 0x00001FFF TXFLSH TX-FIFO clear bit 12 12 write-only RXFLSH RX-FIFO clear bit 11 11 write-only TXCTRL TX-FIFO transmission data control bit 10 10 read-write FWIDTH FIFO bit width setting value 8 9 read-write TXFTH TX-FIFO threshold 4 7 read-write RXFTH RX-FIFO threshold 0 3 read-write TXFIFO0 TX-FIFO0 Register 0x50 32 write-only 0x00000000 0xFFFFFFFF TXDATA TX-FIFO0 write data 0 31 write-only TXFIFO1 TX-FIFO1 Register 0x54 TXFIFO2 TX-FIFO2 Register 0x58 TXFIFO3 TX-FIFO3 Register 0x5C TXFIFO4 TX-FIFO4 Register 0x60 TXFIFO5 TX-FIFO5 Register 0x64 TXFIFO6 TX-FIFO6 Register 0x68 TXFIFO7 TX-FIFO7 Register 0x6C TXFIFO8 TX-FIFO8 Register 0x70 TXFIFO9 TX-FIFO9 Register 0x74 TXFIFO10 TX-FIFO10 Register 0x78 TXFIFO11 TX-FIFO11 Register 0x7C TXFIFO12 TX-FIFO12 Register 0x80 TXFIFO13 TX-FIFO13 Register 0x84 TXFIFO14 TX-FIFO14 Register 0x88 TXFIFO15 TX-FIFO15 Register 0x8C RXFIFO0 RX-FIFO0 Register 0x90 32 read-only 0x00000000 0xFFFFFFFF RXDATA RX-FIFO0 read data 0 31 read-only RXFIFO1 RX-FIFO1 read data 0x94 RXFIFO2 RX-FIFO2 read data 0x98 RXFIFO3 RX-FIFO3 read data 0x9C RXFIFO4 RX-FIFO4 read data 0xA0 RXFIFO5 RX-FIFO5 read data 0xA4 RXFIFO6 RX-FIFO6 read data 0xA8 RXFIFO7 RX-FIFO7 read data 0xAC RXFIFO8 RX-FIFO8 read data 0xB0 RXFIFO9 RX-FIFO9 read data 0xB4 RXFIFO10 RX-FIFO10 read data 0xB8 RXFIFO11 RX-FIFO11 read data 0xBC RXFIFO12 RX-FIFO12 read data 0xC0 RXFIFO13 RX-FIFO13 read data 0xC4 RXFIFO14 RX-FIFO14 read data 0xC8 RXFIFO15 RX-FIFO15 read data 0xCC CSCFG 32 0xD0 32 read-write 0x00000000 0x000F0F07 MSEL Memory device selection bits 16 19 read-write SSEL3EN Slave select 3 enable bit 11 11 read-write SSEL2EN Slave select 2 enable bit 10 10 read-write SSEL1EN Slave select 1 enable bit 9 9 read-write SSEL0EN Slave select 0 enable bit 8 8 read-write MBM SPI data width setting bits 1 2 read-write SRAM Readable/Writable or Read only selection bit 0 0 read-write CSITIME Command Sequencer Idle Timer Setting Register 0xD4 32 read-write 0x0000FFFF 0x0000FFFF ITIME Idle timer setting value 0 15 read-write CSAEXT Command Sequencer Address Extension Register 0xD8 32 read-write 0x00000000 0xFFFFE000 AEXT Address extension bits 13 31 read-write RDCSDC0 Read Command Sequence Data/Control Register 0 0xDC 16 read-write 0x0000 0xFF0F RDCSDATA Read command sequencer data/control setting values 8 15 read-write CONT Continuous instruction setting bit 3 3 read-write TRP Serial interface width control bits 1 2 read-write DEC Decode control bit 0 0 read-write RDCSDC1 Read Command Sequence Data/Control Register 1 0xDE RDCSDC2 Read Command Sequence Data/Control Register 2 0xE0 RDCSDC3 Read Command Sequence Data/Control Register 3 0xE2 RDCSDC4 Read Command Sequence Data/Control Register 4 0xE4 RDCSDC5 Read Command Sequence Data/Control Register 5 0xE6 RDCSDC6 Read Command Sequence Data/Control Register 6 0xE8 RDCSDC7 Read Command Sequence Data/Control Register 7 0xEA WRCSDC0 Write Command Sequence Data/Control Register 0 0xEC 16 read-write 0x0000 0xFF0F WRCSDATA Write command sequencer data/control setting values 8 15 read-write CONT Continuous instruction setting bit 3 3 read-write TRP Serial interface width control bits 1 2 read-write DEC Decode control bit 0 0 read-write WRCSDC1 Write Command Sequence Data/Control Register 1 0xEE WRCSDC2 Write Command Sequence Data/Control Register 2 0xF0 WRCSDC3 Write Command Sequence Data/Control Register 3 0xF2 WRCSDC4 Write Command Sequence Data/Control Register 4 0xF4 WRCSDC5 Write Command Sequence Data/Control Register 5 0xF6 WRCSDC6 Write Command Sequence Data/Control Register 6 0xF8 WRCSDC7 Write Command Sequence Data/Control Register 7 0xFA MID Module Identification Register 0xFC 32 read-only 0x00000630 0xFFFFFFFF MID Module identification information bits 0 31 read-only QDCLKR QDCLKR 0x400 8 read-write 0x0F 0x0F QHDIV QHDIV 0 3 read-write DBCNT DBCNT 0x404 8 read-write 0x00 0x03 TXDBEN TXDBEN 1 1 read-write RXDBEN RXDBEN 0 0 read-write