MB9AF1AxM 1.1 MB9AF1AxM 8 32 32 read-write 0x00000000 0x00000000 FLASH_IF Flash Memory FLASH_IF 0x40000000 0x0 0x4 registers 0x8 0x4 registers 0x10 0x4 registers 0x100 0x4 registers FASZR Flash Access Size Register 0x00 32 read-write 0x00000002 0x00000003 ASZ Flash Access Size 0 1 read-write FSTR Flash Status Register 0x08 32 read-only 0x00000000 0x00000003 HNG Flash Hang flag 1 1 read-only RDY Flash Rdy 0 0 read-only FSYNDN Flash Sync Down Register 0x10 32 read-write 0x00000000 0x00000007 SD Flash Sync 0 2 read-write CRTRMM CR Trimming Data Mirror Register 0x100 32 read-only 0x00000000 0x00000000 TRMM CR Trimming Data Mirror 0 9 read-only CRG Clock Unit Registers CRG 0x40010000 0x0 0x1 registers 0x4 0x1 registers 0x8 0x6 registers 0x10 0x1 registers 0x14 0x1 registers 0x18 0x1 registers 0x1C 0x1 registers 0x20 0x1 registers 0x28 0x1 registers 0x30 0x1 registers 0x34 0x1 registers 0x38 0x1 registers 0x3C 0x1 registers 0x40 0x2 registers 0x44 0x1 registers 0x48 0x2 registers 0x4C 0x2 registers 0x50 0x2 registers 0x54 0x1 registers 0x60 0x1 registers 0x64 0x1 registers 0x68 0x1 registers CSV 0 OSC_PLL_RTC 23 SCM_CTL System Clock Mode Control Register 0x0 8 read-write 0x00 0xFA RCS Master clock switch control bits 5 7 read-write PLLE PLL oscillation enable bit 4 4 read-write SOSCE Sub clock oscillation enable bit 3 3 read-write MOSCE Main clock oscillation enable bit 1 1 read-write SCM_STR System Clock Mode Status Register 0x4 8 read-only 0x00 0xFA RCM Master clock selection bits 5 7 read-only PLRDY PLL oscillation stable bit 4 4 read-only SORDY Sub clock oscillation stable bit 3 3 read-only MORDY Main clock oscillation stable bit 1 1 read-only BSC_PSR Base Clock Prescaler Register 0x10 8 read-write 0x00 0x07 BSR Base clock frequency division ratio setting bit 0 2 read-write APBC0_PSR APB0 Prescaler Register 0x14 8 read-write 0x00 0x03 APBC0 APB0 bus clock frequency division ratio setting bit 0 1 read-write APBC1_PSR APB1 Prescaler Register 0x18 8 read-write 0x80 0x93 APBC1EN APB1 clock enable bit 7 7 read-write APBC1RST APB1 bus reset control bit 4 4 read-write APBC1 APB1 bus clock frequency division ratio setting bit 0 1 read-write APBC2_PSR APB2 Prescaler Register 0x1C 8 read-write 0x80 0x93 APBC2EN APB2 clock enable bit 7 7 read-write APBC2RST APB2 bus reset control bit 4 4 read-write APBC2 APB2 bus clock frequency division ratio setting bit 0 1 read-write SWC_PSR Software Watchdog Clock Prescaler Register 0x20 8 read-write 0x00 0x03 TESTB TEST bit 7 7 read-write SWDS Software watchdog clock frequency division ratio setting bit 0 1 read-write TTC_PSR Trace Clock Prescaler Register 0x28 8 read-write 0x00 0x03 TTC Trace clock frequency division ratio setting bit 0 1 read-write CSW_TMR Clock Stabilization Wait Time Register 0x30 8 read-write 0x00 0x7F SOWT Sub clock stabilization wait time setup bit 4 6 read-write MOWT Main clock stabilization wait time setup bit 0 3 read-write PSW_TMR PLL Clock Stabilization Wait Time Setup Register 0x34 8 read-write 0x00 0x17 PINC PLL input clock select bit 4 4 read-write POWT PLL clock stabilization wait time setup bit 0 2 read-write PLL_CTL1 PLL Control Register 1 0x38 8 read-write 0x00 0xFF PLLK PLL input clock frequency division ratio setting bit 4 7 read-write PLLM PLL VCO clock frequency division ratio setting bit 0 3 read-write PLL_CTL2 PLL Control Register 2 0x3C 8 read-write 0x00 0x3F PLLN PLL feedback frequency division ratio setting bit 0 5 read-write DBWDT_CTL Debug Break Watchdog Timer Control Register 0x54 8 read-write 0x00 0xA0 DPHWBE HW-WDG debug mode break bit 7 7 read-write DPSWBE SW-WDG debug mode break bit 5 5 read-write INT_ENR Interrupt Enable Register 0x60 8 read-write 0x00 0x27 FCSE Anomalous frequency detection interrupt enable bit 5 5 read-write PCSE PLL oscillation stabilization completion interrupt enable bit 2 2 read-write SCSE Sub oscillation stabilization completion interrupt enable bit 1 1 read-write MCSE Main oscillation stabilization completion interrupt enable bit 0 0 read-write INT_STR Interrupt Status Register 0x64 8 read-only 0x00 0x27 FCSI Anomalous frequency detection interrupt status bit 5 5 read-only PCSI PLL oscillation stabilization completion interrupt status bit 2 2 read-only SCSI Sub oscillation stabilization completion interrupt status bit 1 1 read-only MCSI Main oscillation stabilization completion interrupt status bit 0 0 read-only INT_CLR Interrupt Clear Register 0x68 8 write-only 0x00 0x27 FCSC Anomalous frequency detection interrupt cause clear bit 5 5 write-only PCSC PLL oscillation stabilization completion interrupt cause clear bit 2 2 write-only SCSC Sub oscillation stabilization completion interrupt cause clear bit 1 1 write-only MCSC Main oscillation stabilization completion interrupt cause clear bit 0 0 write-only RST_STR Reset Cause Register 0xC 16 read-only 0x0001 0x01FB SRST Software reset flag 8 8 read-only FCSR Flag for anomalous frequency detection reset 7 7 read-only CSVR Clock failure detection reset flag 6 6 read-only HWDT Hardware watchdog reset flag 5 5 read-only SWDT Software watchdog reset flag 4 4 read-only LVDH Low-voltage detection reset flag 3 3 read-only INITX INITX pin input reset flag 1 1 read-only PONR Power-on reset/low-voltage detection reset flag 0 0 read-only STB_CTL Standby Mode Control Register 0x8 32 read-write 0x00000000 0xFFFF0017 KEY Standby mode control write control bit 16 31 read-write SPL Standby pin level setting bit 4 4 read-write DSTM Deep standby mode select bit 2 2 read-write STM Standby mode selection bit 0 1 read-write CSV_CTL CSV control register 0x40 16 read-write 0x7003 0x7303 FCD FCS count cycle setting bits 12 14 read-write FCSRE FCS reset output enable bit 9 9 read-write FCSDE FCS function enable bit 8 8 read-write SCSVE Sub CSV function enable bit 1 1 read-write MCSVE Main CSV function enable bit 0 0 read-write CSV_STR CSV status register 0x44 8 read-only 0x00 0x03 SCMF Sub clock failure detection flag 1 1 read-only MCMF Main clock failure detection flag 0 0 read-only FCSWH_CTL Frequency detection window setting register 0x48 16 read-write 0xFFFF 0xFFFF FCSWL_CTL Frequency detection window setting register 0x4C 16 read-write 0x0000 0xFFFF FCSWD_CTL Frequency detection counter register 0x50 16 read-only 0x0000 0xFFFF CRTRIM CR Trimming Registers CRTRIM 0x4002E000 0x0 0x1 registers 0x4 0x2 registers 0xC 0x4 registers MCR_PSR High-speed CR oscillation Frequency Division Setup Register 0x0 8 read-write 0x01 0x07 CSR High-speed CR oscillation frequency division ratio setting bits 0 2 read-write MCR_FTRM High-speed CR oscillation Frequency Trimming Register 0x4 16 read-write 0x0180 0x03FF TRD Frequency trimming setup bits 0 9 read-write MCR_RLR High-Speed CR Oscillation Register Write-Protect Register 0xC 32 read-write 0x00000001 0xFFFFFFFF TRMLCK Register write-protect bits 0 31 read-write SWWDT Software Watchdog Timer SWWDT 0x40012000 0x0 0x4 registers 0x4 0x4 registers 0x8 0x1 registers 0xC 0x4 registers 0x10 0x1 registers 0xC00 0x4 registers SWDT 1 WDOGLOAD Software Watchdog Timer Load Register 0x0 32 read-write 0xFFFFFFFF 0xFFFFFFFF WDOGVALUE Software Watchdog Timer Value Register 0x4 32 read-only 0xFFFFFFFF 0xFFFFFFFF WDOGCONTROL Software Watchdog Timer Control Register 0x8 8 read-write 0x00 0x03 RESEN Reset enable bit of the software watchdog 1 1 read-write INTEN Interrupt and counter enable bit of the software watchdog 0 0 read-write WDOGINTCLR Software Watchdog Timer Clear Register 0xC 32 read-write 0xFFFFFFFF 0xFFFFFFFF WDOGRIS Software Watchdog Timer Interrupt Status Register 0x10 8 read-only 0x00 0x01 RIS Software watchdog interrupt status bit 0 0 read-only WDOGLOCK Software Watchdog Timer Lock Register 0xC00 32 read-write 0x00000000 0xFFFFFFFF HWWDT Hardware Watchdog Timer HWWDT 0x40011000 0x0 0x4 registers 0x4 0x4 registers 0x8 0x4 registers 0xC 0x1 registers 0x10 0x1 registers 0xC00 0x4 registers WDG_LDR Hardware Watchdog Timer Load Register 0x0 32 read-write 0x0000FFFF 0xFFFFFFFF WDG_VLR Hardware Watchdog Timer Value Register 0x4 32 read-only 0x00000000 0xFFFFFFFF WDG_CTL Hardware Watchdog Timer Control Register 0x8 8 read-write 0x03 0x03 RESEN Hardware watchdog reset enable bit 1 1 read-write INTEN Hardware watchdog interrupt and counter enable bit 0 0 read-write WDG_ICL Hardware Watchdog Timer Clear Register 0xC 8 read-write 0xFF 0x00 WDG_RIS Hardware Watchdog Timer Interrupt Status Register 0x10 8 read-only 0xFF 0x00 RIS Hardware watchdog interrupt status bit 0 0 read-only WDG_LCK Hardware Watchdog Timer Lock Register 0xC00 32 read-write 0x00000001 0xFFFFFFFF MFT0 Multifunction Timer 0 MFT0 0x40020000 0x0 0x2 registers 0x4 0x2 registers 0x8 0x2 registers 0xC 0x2 registers 0x10 0x2 registers 0x14 0x2 registers 0x18 0x2 registers 0x1C 0x2 registers 0x20 0x2 registers 0x24 0x2 registers 0x28 0x2 registers 0x2C 0x2 registers 0x30 0x2 registers 0x34 0x2 registers 0x38 0x2 registers 0x3C 0x2 registers 0x40 0x2 registers 0x44 0x2 registers 0x48 0x2 registers 0x4C 0x2 registers 0x50 0x2 registers 0x54 0x2 registers 0x58 0x2 registers 0x5C 0x1 registers 0x60 0x2 registers 0x68 0x2 registers 0x6C 0x2 registers 0x70 0x2 registers 0x74 0x2 registers 0x78 0x2 registers 0x7C 0x2 registers 0x80 0x2 registers 0x84 0x2 registers 0x88 0x2 registers 0x8C 0x2 registers 0x90 0x2 registers 0x94 0x2 registers 0x98 0x2 registers 0x9C 0x2 registers 0xA0 0x2 registers 0xA4 0x2 registers 0xA8 0x2 registers 0xAC 0x2 registers 0xB0 0x2 registers 0xB4 0x2 registers 0xB8 0x1 registers 0xBC 0x2 registers 0xC0 0x2 registers WFG 3 FRTIM 25 INCAP 26 OUTCOMP 27 FRT_TCSA0 FRT-ch.0 Control Register A 0x30 16 read-write 0x0040 0xE3FF CLK FRT clock cycle 0 3 read-write SCLR FRT operation state initialization request 4 4 write-only MODE FRT's count mode 5 5 read-write STOP Puts FRT in stopping state 6 6 read-write BFE Enables TCCP's buffer function 7 7 read-write ICRE "Generates interrupt when ""1"" is set to TCSA.ICLR" 8 8 read-write ICLR interrupt flag 9 9 read-write IRQZE "Generates interrupt, when ""1"" is set to TCSA.IRQZF" 13 13 read-write IRQZF zero interrupt flag 14 14 read-write ECKE Uses an external input clock (FRCK) as FRT's count clock 15 15 read-write FRT_TCSA1 FRT-ch.1 Control Register A 0x40 FRT_TCSA2 FRT-ch.2 Control Register A 0x50 FRT_TCSB0 FRT-ch.0 Control Register B 0x34 16 read-write 0x0000 0x0007 AD2E Outputs AD conversion start signal to ADCunit2 upon Zero value detection by FRT 2 2 read-write AD1E Outputs AD conversion start signal to ADCunit1 upon Zero value detection by FRT 1 1 read-write AD0E Outputs AD conversion start signal to ADCunit0 upon Zero value detection by FRT 0 0 read-write FRT_TCSB1 FRT-ch.1 Control Register B 0x44 FRT_TCSB2 FRT-ch.2 Control Register B 0x54 FRT_TCCP0 FRT-ch.0 Cycle Setting Register 0x28 16 read-write 0xFFFF 0xFFFF FRT_TCCP1 FRT-ch.1 Cycle Setting Register 0x38 FRT_TCCP2 FRT-ch.2 Cycle Setting Register 0x48 FRT_TCDT0 FRT-ch.0 Count Value Register 0x2C 16 read-write 0x0000 0xFFFF FRT_TCDT1 FRT-ch.1 Count Value Register 0x3C FRT_TCDT2 FRT-ch.2 Count Value Register 0x4C OCU_OCFS10 "OCU ch.1,0 Connecting FRT Select Register" 0x58 8 read-write 0x00 0xFF FSO0 Connects FRT ch.x to OCU ch.0 0 3 read-write FSO1 Connects FRT ch.x to OCU ch.1 4 7 read-write OCU_OCFS32 "OCU ch.3,2 Connecting FRT Select Register" 0x59 OCU_OCFS54 "OCU ch.5,4 Connecting FRT Select Register" 0x5C OCU_OCSA10 "OCU ch.1,0 Control Register A" 0x18 8 read-write 0x0C 0xFF CST0 Enables the operation of OCU ch.(0) 0 0 read-write CST1 Enables the operation of OCU ch.(1) 1 1 read-write BDIS0 Disables the buffer function of the OCCP(0) register 2 2 read-write BDIS1 Disables the buffer function of the OCCP(1) register 3 3 read-write IOE0 "Generates interrupt, when ""1"" is set to OCSA.IOP0" 4 4 read-write IOE1 "Generates interrupt, when ""1"" is set to OCSA.IOP1" 5 5 read-write IOP0 Indicates that a match has already been detected between FRT's count value and OCCP(0) value at OCU ch.(0). 6 6 read-write IOP1 Indicates that a match has already been detected between FRT's count value and OCCP(1) value at OCU ch.(1). 7 7 read-write OCU_OCSA32 "OCU ch.3,2 Control Register A" 0x1C OCU_OCSA54 "OCU ch.5,4 Control Register A" 0x20 OCU_OCSB10 "OCU ch.1,0 Control Register B" 0x19 8 read-write 0x60 0x73 OTD0 Indicates that the RT(0) output pin is in the High-level output state. 0 0 read-write OTD1 Indicates that the RT(1) output pin is in the High-level output state. 1 1 read-write CMOD selects OCU's operation mode in combination with OCSC.MOD0 to MOD5 4 4 read-write BTS0 Performs buffer transfer of the OCCP(0) register upon Peak value detection by FRT 5 5 read-write BTS1 Performs buffer transfer of the OCCP(1) register upon Peak value detection by FRT 6 6 read-write OCU_OCSB32 "OCU ch.3,2 Control Register B" 0x1D OCU_OCSB54 "OCU ch.5,4 Control Register B" 0x21 OCU_OCSC OCU Control Register C 0x24 16 read-write 0x0000 0x3F00 MOD0 OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD 8 8 read-write MOD1 OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD 9 9 read-write MOD2 OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD 10 10 read-write MOD3 OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD 11 11 read-write MOD4 OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD 12 12 read-write MOD5 OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD 13 13 read-write OCU_OCCP0 OCU ch.0 Compare Value Store Register 0x0 16 read-write 0x0000 0xFFFF OCU_OCCP1 OCU ch.1 Compare Value Store Register 0x4 OCU_OCCP2 OCU ch.2 Compare Value Store Register 0x8 OCU_OCCP3 OCU ch.3 Compare Value Store Register 0xC OCU_OCCP4 OCU ch.4 Compare Value Store Register 0x10 OCU_OCCP5 OCU ch.5 Compare Value Store Register 0x14 WFG_WFSA10 WFG ch.10 Control Register A 0x8C 16 read-write 0x0000 0x1FFF DCK clock cycle of the WFG timer 0 2 read-write TMD WFG's operation mode 3 5 read-write GTEN the CH_GATE signal for each channel of WFG 6 7 read-write PSEL the PPG timer unit to be used at each channel of WFG 8 9 read-write PGEN specifies how to reflect the CH_PPG signal that is input to each channel of WFG on WFG output 10 11 read-write DMOD specifies which polarity will be used to output the non-overlap signal 12 12 read-write WFG_WFSA32 WFG ch.32 Control Register A 0x90 WFG_WFSA54 WFG ch.54 Control Register A 0x94 WFG_WFTM10 WFG ch.10 Timer Value Register 0x80 16 read-write 0x0000 0xFFFF WFG_WFTM32 WFG ch.32 Timer Value Register 0x84 WFG_WFTM54 WFG ch.54 Timer Value Register 0x88 WFG_NZCL NZCL Control Register 0x9C 16 read-write 0x0000 0x001F DTIE DTIF interrupt enable 0 0 read-write NWS noise-canceling width of the noise-canceller for the DTTIX pin 1 3 read-write SDTI Forcibly generates DTIF interrupt 4 4 write-only WFG_WFIR WFG Interrupt Control Register 0x98 16 read-write 0x0000 0xFFF3 DTIF Indicates that DTIF interrupt has been generated. 0 0 read-only DTIC Clears WFIR.DTIF and deasserts the DTIF interrupt signal. 1 1 write-only TMIF10 Indicates that WFG10 timer interrupt has been generated. 4 4 read-only TMIC10 Clears WFIR.TMIF10 and deasserts the WFG10 timer interrupt signal. 5 5 write-only TMIE10 Starts the WFG10 timer 6 6 read-write TMIS10 Stops the WFG10 timer 7 7 write-only TMIF32 Indicates that WFG32 timer interrupt has been generated. 8 8 read-only TMIC32 Clears WFIR.TMIF32 and deasserts the WFG32 timer interrupt signal. 9 9 write-only TMIE32 Starts the WFG32 timer 10 10 read-write TMIS32 Stops the WFG32 timer 11 11 write-only TMIF54 Indicates that WFG54 timer interrupt has been generated. 12 12 read-only TMIC54 Clears WFIR.TMIF54 and deasserts the WFG54 timer interrupt signal. 13 13 write-only TMIE54 Starts the WFG54 timer 14 14 read-write TMIS54 Stops the WFG54 timer 15 15 write-only ICU_ICFS10 "ICU ch.1,0 Connecting FRT Select Register" 0x60 8 read-write 0x00 0xFF FSI0 Connects FRT ch.x to ICU ch.(0) 0 3 read-write FSI1 Connects FRT ch.x to ICU ch.(1) 4 7 read-write ICU_ICFS32 "ICU ch.3,2 Connecting FRT Select Register" 0x61 ICU_ICSA10 "ICU ch.1,0 Control Register A" 0x78 8 read-write 0x00 0xFF EG0 enables/disables the operation of ICU-ch.(0) and selects a valid edge(s) 0 1 read-write EG1 enables/disables the operation of ICU-ch.(1) and selects a valid edge(s) 2 3 read-write ICE0 "Generates interrupt, when ""1"" is set to ICSA.ICP0." 4 4 read-write ICE1 "Generates interrupt, when ""1"" is set to ICSA.ICP1." 5 5 read-write ICP0 Indicates that a valid edge has been detected at ICU ch.(0) and the capture operation has been performed 6 6 read-write ICP1 Indicates that a valid edge has been detected at ICU ch.(1) and the capture operation has been performed 7 7 read-write ICU_ICSA32 "ICU ch.3,2 Control Register A" 0x7C ICU_ICSB10 "ICU ch.1,0 Control Register B" 0x79 8 read-only 0x00 0x03 IEI0 indicates the latest valid edge of ICU-ch.(0) 0 0 read-only IEI1 indicates the latest valid edge of ICU-ch.(1) 1 1 read-only ICU_ICSB32 "ICU ch.3,2 Control Register B" 0x7D ICU_ICCP0 ICU ch.0 Capture value store register 0x68 16 read-only 0x0000 0x0000 ICU_ICCP1 ICU ch.1 Capture value store register 0x6C ICU_ICCP2 ICU ch.2 Capture value store register 0x70 ICU_ICCP3 ICU ch.3 Capture value store register 0x74 ADCMP_ACSA ADCMP Control Register A 0xBC 16 read-write 0x0000 0x3F3F CE0 enable or disable the operation of ADCMP-ch.0 and select the FRT to be connected 0 1 read-write CE1 enable or disable the operation of ADCMP-ch.1 and select the FRT to be connected 2 3 read-write CE2 enable or disable the operation of ADCMP-ch.2 and select the FRT to be connected 4 5 read-write SEL0 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.0 8 9 read-write SEL1 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.1 10 11 read-write SEL2 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.2 12 13 read-write ADCMP_ACSB ADCMP Control Register B 0xB8 8 read-write 0x07 0x77 BDIS0 Disables the buffer function of the ACCP0 and ACCPDN0 registers 0 0 read-write BDIS1 Disables the buffer function of the ACCP1 and ACCPDN1 registers 1 1 read-write BDIS2 Disables the buffer function of the ACCP2 and ACCPDN2 registers 2 2 read-write BTS0 Performs buffer transfer of the ACCP0 and ACCPDN0 registers upon Peak value detection by FRT 4 4 read-write BTS1 Performs buffer transfer of the ACCP1 and ACCPDN1 registers upon Peak value detection by FRT 5 5 read-write BTS2 Performs buffer transfer of the ACCP2 and ACCPDN2 registers upon Peak value detection by FRT 6 6 read-write ADCMP_ACCP0 ADCMP ch.0 Compare Value Store Register 0xA0 16 read-write 0x0000 0xFFFF ADCMP_ACCP1 ADCMP ch.1 Compare Value Store Register 0xA8 ADCMP_ACCP2 ADCMP ch.2 Compare Value Store Register 0xB0 ADCMP_ACCPDN0 ADCMP ch.0 Compare Value Store Register 0xA4 16 read-write 0x0000 0xFFFF ADCMP_ACCPDN1 ADCMP ch.1 Compare Value Store Register 0xAC ADCMP_ACCPDN2 ADCMP ch.2 Compare Value Store Register 0xB4 ADCMP_ATSA ADC Start Trigger Select Register 0xC0 16 read-write 0x0000 0x3F3F AD0S selects the start signal to be used to start the scan conversion of ADC unit0 0 1 read-write AD1S selects the start signal to be used to start the scan conversion of ADC unit1 2 3 read-write AD2S selects the start signal to be used to start the scan conversion of ADC unit2 4 5 read-write AD0P selects the start signal to be used to start priority conversion of ADC unit0 8 9 read-write AD1P selects the start signal to be used to start priority conversion of ADC unit1 10 11 read-write AD2P selects the start signal to be used to start priority conversion of ADC unit2 12 13 read-write BTIOSEL03 Base Timer I/O Select BTIOSEL03 0x40025100 0x0 0x2 registers BTSEL0123 I/O Select Register 0x00 16 read-write 0x0000 0xFF00 SEL23_ I/O select bits for Ch.2/Ch.3 12 15 read-write SEL01_ I/O select bits for Ch.0/Ch.1 8 11 read-write BTIOSEL47 Base Timer I/O Select BTIOSEL47 0x40025300 0x0 0x2 registers 0x0 0x2 registers BTSEL4567 I/O Select Register 0x00 16 read-write 0x0000 0xFF00 SEL67_ I/O select bits for Ch.6/Ch.7 12 15 read-write SEL45_ I/O select bits for Ch.4/Ch.5 8 11 read-write SBSSR Software-based Simultaneous Startup Register SBSSR 0x40025F00 0x0FC 0x2 registers BTSSSR Software-based Simultaneous Startup Register 0xFC 16 write-only 0x0000 0x0000 SSSR15 Bit15 of BTSSSR 15 15 write-only SSSR14 Bit14 of BTSSSR 14 14 write-only SSSR13 Bit13 of BTSSSR 13 13 write-only SSSR12 Bit12 of BTSSSR 12 12 write-only SSSR11 Bit11 of BTSSSR 11 11 write-only SSSR10 Bit10 of BTSSSR 10 10 write-only SSSR9 Bit9 of BTSSSR 9 9 write-only SSSR8 Bit8 of BTSSSR 8 8 write-only SSSR7 Bit7 of BTSSSR 7 7 write-only SSSR6 Bit6 of BTSSSR 6 6 write-only SSSR5 Bit5 of BTSSSR 5 5 write-only SSSR4 Bit4 of BTSSSR 4 4 write-only SSSR3 Bit3 of BTSSSR 3 3 write-only SSSR2 Bit2 of BTSSSR 2 2 write-only SSSR1 Bit1 of BTSSSR 1 1 write-only SSSR0 Bit0 of BTSSSR 0 0 write-only BT0 Base Timer 0 BT0 0x40025000 0x0 0x2 registers 0x4 0x2 registers 0x8 0x2 registers 0xC 0x2 registers 0x10 0x2 registers BTIM 28 PWM_TMCR Timer Control Register PWM 0x0C 16 read-write 0x0000 0x7F7F CKS2_0 Count clock selection bit 12 14 read-write RTGEN Restart enable bit 11 11 read-write PMSK Pulse output mask bit 10 10 read-write EGS Trigger input edge selection bits 8 9 read-write FMD Timer function selection bits 4 6 read-write OSEL Output polarity specification bit 3 3 read-write MDSE Mode selection bit 2 2 read-write CTEN Count operation enable bit 1 1 read-write STRG Software trigger bit 0 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write 0x00 0x01 CKS3 Count clock selection bit 0 0 read-write PWM_STC Status Control Register PWM 0x10 8 read-write 0x00 0x77 TGIE Trigger interrupt request enable bit 6 6 read-write DTIE Duty match interrupt request enable bit 5 5 read-write UDIE Underflow interrupt request enable bit 4 4 read-write TGIR Trigger interrupt request bit 2 2 read-write DTIR Duty match interrupt request bit 1 1 read-write UDIR Underflow interrupt request bit 0 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x00 16 read-write 0x0000 0x0000 PWM_PDUT PWM Duty Set Register PWM 0x04 16 read-write 0x0000 0x0000 PWM_TMR Timer Register PWM 0x08 16 read-only 0x0000 0xFFFF PPG_TMCR Timer Control Register PPG 0x0C 16 read-write 0x0000 0x7F7F CKS2_0 Count clock selection bit 12 14 read-write RTGEN Restart enable bit 11 11 read-write PMSK Pulse output mask bit 10 10 read-write EGS Trigger input edge selection bits 8 9 read-write FMD Timer function selection bits 4 6 read-write OSEL Output polarity specification bit 3 3 read-write MDSE Mode selection bit 2 2 read-write CTEN Count operation enable bit 1 1 read-write STRG Software trigger bit 0 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write 0x00 0x01 CKS3 Count clock selection bit 0 0 read-write PPG_STC Status Control Register PPG 0x10 8 read-write 0x00 0x55 TGIE Trigger interrupt request enable bit 6 6 read-write UDIE Underflow interrupt request enable bit 4 4 read-write TGIR Trigger interrupt request bit 2 2 read-write UDIR Underflow interrupt request bit 0 0 read-write PPG_PRLL LOW Width Reload Register PPG 0x00 16 read-write 0x0000 0x0000 PPG_PRLH HIGH Width Reload Register PPG 0x04 16 read-write 0x0000 0x0000 PPG_TMR Timer Register PPG 0x08 16 read-only 0x0000 0xFFFF RT_TMCR Timer Control Register RT 0x0C 16 read-write 0x0000 0x73FF CKS2_0 Count clock selection bit 12 14 read-write EGS Trigger input edge selection bits 8 9 read-write T32 32-bit timer selection bit 7 7 read-write FMD Timer function selection bits 4 6 read-write OSEL Output polarity specification bit 3 3 read-write MDSE Mode selection bit 2 2 read-write CTEN Timer enable bit 1 1 read-write STRG Software trigger bit 0 0 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write 0x00 0x01 CKS3 Count clock selection bit 0 0 read-write RT_STC Status Control Register RT 0x10 8 read-write 0x00 0x55 TGIE Trigger interrupt request enable bit 6 6 read-write UDIE Underflow interrupt request enable bit 4 4 read-write TGIR Trigger interrupt request bit 2 2 read-write UDIR Underflow interrupt request bit 0 0 read-write RT_PCSR PWM Cycle Set Register RT 0x00 16 read-write 0x0000 0x0000 RT_TMR Timer Register RT 0x08 16 read-only 0x0000 0x0000 PWC_TMCR Timer Control Register PWC 0x0C 16 read-write 0x0000 0x77F6 CKS2_0 Count clock selection bit 12 14 read-write EGS Measurement edge selection bits 8 10 read-write T32 32-bit timer selection bit 7 7 read-write FMD Timer function selection bits 4 6 read-write MDSE Mode selection bit 2 2 read-write CTEN Timer enable bit 1 1 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write 0x00 0x01 CKS3 Count clock selection bit 0 0 read-write PWC_STC Status Control Register PWC 0x10 8 read-write 0x00 0xD5 ERR Error flag bit 7 7 read-only EDIE Measurement completion interrupt request enable bit 6 6 read-write OVIE Overflow interrupt request enable bit 4 4 read-write EDIR Measurement completion interrupt request bit 2 2 read-only OVIR Overflow interrupt request bit 0 0 read-write PWC_DTBF Data Buffer Register PWC 0x04 16 read-only 0x0000 0xFFFF BT1 0x40025040 BT2 0x40025080 BT3 0x400250C0 BT4 0x40025200 BT5 0x40025240 BT6 0x40025280 BT7 0x400252C0 MFT_PPG PPG Configuration MFT_PPG 0x40024000 0x0 0x2 registers 0x8 0x2 registers 0xC 0x1 registers 0x10 0x2 registers 0x14 0x1 registers 0x100 0x2 registers 0x104 0x2 registers 0x200 0x2 registers 0x204 0x2 registers 0x208 0x2 registers 0x20C 0x2 registers 0x210 0x2 registers 0x214 0x2 registers 0x218 0x1 registers 0x240 0x2 registers 0x244 0x2 registers 0x248 0x2 registers 0x24C 0x2 registers 0x250 0x2 registers 0x254 0x2 registers 0x258 0x1 registers 0x380 0x1 registers PPG 22 TTCR0 PPG Start Trigger Control Register 0 0x0 16 read-write 0xF000 0xFF00 TRG6O PPG6 trigger stop bit 15 15 read-write TRG4O PPG4 trigger stop bit 14 14 read-write TRG2O PPG2 trigger stop bit 13 13 read-write TRG0O PPG0 trigger stop bit 12 12 read-write CS0 8-bit UP counter clock select bits for comparison 10 11 read-write MONI0 8-bit UP counter operation state monitor bit for comparison 9 9 read-only STR0 8-bit UP counter operation enable bit for comparison 8 8 read-write COMP0 PPG Compare Register 0 0x08 16 read-write 0x0000 0xFF00 COMP2 PPG Compare Register 2 0x0C 8 read-write 0x00 0xFF COMP4 PPG Compare Register 4 0x10 COMP6 PPG Compare Register 6 0x14 TRG PPG Start Register 0 0x100 16 read-write 0x00 0xFF PEN07 PPG7 Start Trigger bit 7 7 read-write PEN06 PPG6 Start Trigger bit 6 6 read-write PEN05 PPG5 Start Trigger bit 5 5 read-write PEN04 PPG4 Start Trigger bit 4 4 read-write PEN03 PPG3 Start Trigger bit 3 3 read-write PEN02 PPG2 Start Trigger bit 2 2 read-write PEN01 PPG1 Start Trigger bit 1 1 read-write PEN00 PPG0 Start Trigger bit 0 0 read-write REVC Output Reverse Register 0 0x104 16 read-write 0x00 0xFF REV07 PPG7 Output Reverse Enable bit 7 7 read-write REV06 PPG6 Output Reverse Enable bit 6 6 read-write REV05 PPG5 Output Reverse Enable bit 5 5 read-write REV04 PPG4 Output Reverse Enable bit 4 4 read-write REV03 PPG3 Output Reverse Enable bit 3 3 read-write REV02 PPG2 Output Reverse Enable bit 2 2 read-write REV01 PPG1 Output Reverse Enable bit 1 1 read-write REV00 PPG0 Output Reverse Enable bit 0 0 read-write PPGC0 PPG Operation Mode Control Register 0 0x201 8 read-write 0x00 0xFF PIE PPG Interrupt Enable bit 7 7 read-write PUF PPG Counter Underflow bit 6 6 read-write INTM Interrupt Mode Select bit 5 5 read-write PCS PPG DOWN Counter Operation Clock Select bits 3 4 read-write MD PPG Operation Mode Set bits 1 2 read-write TTRG PPG start trigger select bit 0 0 read-write PPGC1 PPG Operation Mode Control Register 1 0x200 PPGC2 PPG Operation Mode Control Register 2 0x205 PPGC3 PPG Operation Mode Control Register 3 0x204 PPGC4 PPG Operation Mode Control Register 4 0x241 PPGC5 PPG Operation Mode Control Register 5 0x240 PPGC6 PPG Operation Mode Control Register 6 0x245 PPGC7 PPG Operation Mode Control Register 7 0x244 PRLH0 PPG0 Reload Registers High 0x209 8 read-write 0x00 0x00 PRLH Reload Registers High 0 7 read-write PRLL0 PPG0 Reload Registers Low 0x208 8 read-write 0x00 0x00 PRLL Reload Registers Low 0 7 read-write PRLH1 PPG1 Reload Registers High 0x20D PRLL1 PPG1 Reload Registers Low 0x20C PRLH2 PPG2 Reload Registers High 0x211 PRLL2 PPG2 Reload Registers Low 0x210 PRLH3 PPG3 Reload Registers High 0x215 PRLL3 PPG3 Reload Registers Low 0x214 PRLH4 PPG4 Reload Registers High 0x249 PRLL4 PPG4 Reload Registers Low 0x248 PRLH5 PPG5 Reload Registers High 0x24D PRLL5 PPG5 Reload Registers Low 0x24C PRLH6 PPG6 Reload Registers High 0x251 PRLL6 PPG6 Reload Registers Low 0x250 PRLH7 PPG7 Reload Registers High 0x255 PRLL7 PPG7 Reload Registers Low 0x254 GATEC0 PPG Gate Function Control Registers 0 0x218 8 read-write 0x00 0x33 STRG2 Select a trigger for PPG2 5 5 read-write EDGE2 Select Start Effective Level for PPG2 4 4 read-write STRG0 Select a trigger for PPG0 1 1 read-write EDGE0 Select Start Effective Level for PPG0 0 0 read-write GATEC4 PPG Gate Function Control Registers 4 0x258 8 read-write 0x00 0x33 STRG6 Select a trigger for PPG6 5 5 read-write EDGE6 Select Start Effective Level for PPG6 4 4 read-write STRG4 Select a trigger for PPG4 1 1 read-write EDGE4 Select Start Effective Level for PPG4 0 0 read-write IGBTC IGBT Mode Control Register 0x380 8 read-write 0x00 0xFF IGATIH Stop prohibition mode selection in output active bit 7 7 read-write IGNFW Noise filter width selection bit 4 6 read-write IGOSEL Output level selection bit 2 3 read-write IGTRGLV Trigger input level selection bit 1 1 read-write IGBTMD IGBT mode selection bit 0 0 read-write ADC0 ADC0 Registers ADC0 0x40027000 0x0 0x2 registers 0x8 0x2 registers 0xC 0x4 registers 0x10 0x2 registers 0x14 0x2 registers 0x18 0x2 registers 0x1C 0x4 registers 0x20 0x1 registers 0x24 0x1 registers 0x26 0x2 registers 0x28 0x2 registers 0x2C 0x2 registers 0x30 0x2 registers 0x34 0x1 registers 0x38 0x2 registers 0x3C 0x2 registers ADC0 24 ADCR A/D Control Register 0x1 8 read-write 0x00 0xEF SCIF Scan conversion interrupt request bit 7 7 read-write PCIF Priority conversion interrupt request bit 6 6 read-write CMPIF Conversion result comparison interrupt request bit 5 5 read-write SCIE Scan conversion interrupt enable bit 3 3 read-write PCIE Priority conversion interrupt enable bit 2 2 read-write CMPIE Conversion result comparison interrupt enable bit 1 1 read-write OVRIE FIFO overrun interrupt enable bit 0 0 read-write ADSR A/D Status Register 0x0 8 read-write 0x00 0xC7 ADSTP A/D conversion forced stop bit 7 7 read-write FDAS FIFO data placement selection bit 6 6 read-write PCNS Priority conversion pending flag 2 2 read-write PCS Priority conversion status flag 1 1 read-write SCS Scan conversion status flag 0 0 read-write SCCR Scan Conversion Control Register 0x9 8 read-write 0x80 0xF7 SEMP Scan conversion FIFO empty bit 7 7 read-only SFUL Scan conversion FIFO full bit 6 6 read-only SOVR Scan conversion overrun flag 5 5 read-write SFCLR Scan conversion FIFO clear bit 4 4 read-write RPT Scan conversion repeat bit 2 2 read-write SHEN Scan conversion timer start enable bit 1 1 read-write SSTR Scan conversion start bit 0 0 read-write SFNS Scan Conversion FIFO Stage Count Setup Register 0x8 8 read-write 0x00 0x0F SFS Scan conversion FIFO stage count setting bit 0 3 read-write SCFD Scan Conversion FIFO Data Register 0xC 32 read-only 0x00000000 0xFFF0131F SD Scan conversion result 20 31 read-only INVL A/D conversion result disable bit 12 12 read-only RS Scan conversion start factor 8 9 read-only SC Conversion input channel bits 0 4 read-only SCIS3 Scan Conversion Input Selection Register 3 0x11 8 read-write 0x00 0xFF AN31 Bit7 of SCIS3 7 7 read-write AN30 Bit6 of SCIS3 6 6 read-write AN29 Bit5 of SCIS3 5 5 read-write AN28 Bit4 of SCIS3 4 4 read-write AN27 Bit3 of SCIS3 3 3 read-write AN26 Bit2 of SCIS3 2 2 read-write AN25 Bit1 of SCIS3 1 1 read-write AN24 Bit0 of SCIS3 0 0 read-write SCIS2 Scan Conversion Input Selection Register 2 0x10 8 read-write 0x00 0xFF AN23 Bit7 of SCIS2 7 7 read-write AN22 Bit6 of SCIS2 6 6 read-write AN21 Bit5 of SCIS2 5 5 read-write AN20 Bit4 of SCIS2 4 4 read-write AN19 Bit3 of SCIS2 3 3 read-write AN18 Bit2 of SCIS2 2 2 read-write AN17 Bit1 of SCIS2 1 1 read-write AN16 Bit0 of SCIS2 0 0 read-write SCIS1 Scan Conversion Input Selection Register 1 0x15 8 read-write 0x00 0xFF AN15 Bit7 of SCIS1 7 7 read-write AN14 Bit6 of SCIS1 6 6 read-write AN13 Bit5 of SCIS1 5 5 read-write AN12 Bit4 of SCIS1 4 4 read-write AN11 Bit3 of SCIS1 3 3 read-write AN10 Bit2 of SCIS1 2 2 read-write AN9 Bit1 of SCIS1 1 1 read-write AN8 Bit0 of SCIS1 0 0 read-write SCIS0 Scan Conversion Input Selection Register 0 0x14 8 read-write 0x00 0xFF AN7 Bit7 of SCIS0 7 7 read-write AN6 Bit6 of SCIS0 6 6 read-write AN5 Bit5 of SCIS0 5 5 read-write AN4 Bit4 of SCIS0 4 4 read-write AN3 Bit3 of SCIS0 3 3 read-write AN2 Bit2 of SCIS0 2 2 read-write AN1 Bit1 of SCIS0 1 1 read-write AN0 Bit0 of SCIS0 0 0 read-write PFNS Priority Conversion FIFO Stage Count Setup Register 0x18 8 read-write 0x00 0x33 TEST Test bits 4 5 read-only PFS Priority conversion FIFO stage count setting bits 0 1 read-write PCCR Priority Conversion Control Register 0x19 8 read-write 0x80 0xFF PEMP Priority conversion FIFO empty bit 7 7 read-only PFUL Priority conversion FIFO full bit 6 6 read-only POVR Priority conversion overrun flag 5 5 read-write PFCLR Priority conversion FIFO clear bit 4 4 read-write ESCE External trigger analog input selection bit 3 3 read-write PEEN Priority conversion external start enable bit 2 2 read-write PHEN Priority conversion timer start enable bit 1 1 read-write PSTR Priority conversion start bit 0 0 read-write PCFD Priority Conversion FIFO Data Register 0x1C 32 read-only 0x00000000 0xFFF0171F PD Priority conversion result 20 31 read-only INVL A/D conversion result disable bit 12 12 read-only RS Scan conversion start factor 8 10 read-only PC Conversion input channel bits 0 4 read-only PCIS Priority Conversion Input Selection Register 0x20 8 read-write 0x00 0xFF P2A Priority level 2 analog input selection 3 7 read-write P1A Priority level 1 analog input selection 0 2 read-write CMPCR A/D Comparison Control Register 0x24 8 read-write 0x00 0xFF CMPEN Conversion result comparison function operation enable bit 7 7 read-write CMD1 Comparison mode 1 6 6 read-write CMD0 Comparison mode 0 5 5 read-write CCH Comparison target analog input channel 0 4 read-write CMPD A/D Comparison Value Setup Register 0x26 16 read-write 0x0000 0xFFC0 CMAD A/D conversion result value setting bits 6 15 read-write ADSS3 Sampling Time Selection Register 3 0x29 8 read-write 0x00 0xFF TS31 Bit7 of ADSS3 7 7 read-write TS30 Bit6 of ADSS3 6 6 read-write TS29 Bit5 of ADSS3 5 5 read-write TS28 Bit4 of ADSS3 4 4 read-write TS27 Bit3 of ADSS3 3 3 read-write TS26 Bit2 of ADSS3 2 2 read-write TS25 Bit1 of ADSS3 1 1 read-write TS24 Bit0 of ADSS3 0 0 read-write ADSS2 Sampling Time Selection Register 2 0x28 8 read-write 0x00 0xFF TS23 Bit7 of ADSS2 7 7 read-write TS22 Bit6 of ADSS2 6 6 read-write TS21 Bit5 of ADSS2 5 5 read-write TS20 Bit4 of ADSS2 4 4 read-write TS19 Bit3 of ADSS2 3 3 read-write TS18 Bit2 of ADSS2 2 2 read-write TS17 Bit1 of ADSS2 1 1 read-write TS16 Bit0 of ADSS2 0 0 read-write ADSS1 Sampling Time Selection Register 1 0x2D 8 read-write 0x00 0xFF TS15 Bit7 of ADSS1 7 7 read-write TS14 Bit6 of ADSS1 6 6 read-write TS13 Bit5 of ADSS1 5 5 read-write TS12 Bit4 of ADSS1 4 4 read-write TS11 Bit3 of ADSS1 3 3 read-write TS10 Bit2 of ADSS1 2 2 read-write TS9 Bit1 of ADSS1 1 1 read-write TS8 Bit0 of ADSS1 0 0 read-write ADSS0 Sampling Time Selection Register 0 0x2C 8 read-write 0x00 0xFF TS7 Bit7 of ADSS0 7 7 read-write TS6 Bit6 of ADSS0 6 6 read-write TS5 Bit5 of ADSS0 5 5 read-write TS4 Bit4 of ADSS0 4 4 read-write TS3 Bit3 of ADSS0 3 3 read-write TS2 Bit2 of ADSS0 2 2 read-write TS1 Bit1 of ADSS0 1 1 read-write TS0 Bit0 of ADSS0 0 0 read-write ADST1 Sampling Time Setup Register 1 0x30 8 read-write 0x10 0xFF STX1 Sampling time N times setting bits 5 7 read-write ST1 Sampling time setting bits 0 4 read-write ADST0 Sampling Time Setup Register 0 0x31 8 read-write 0x10 0xFF STX0 Sampling time N times setting bits 5 7 read-write ST0 Sampling time setting bits 0 4 read-write ADCT Comparison Time Setup Register 0x34 8 read-write 0x07 0x07 CT Compare clock frequency division ratio setting bits 0 7 read-write PRTSL Priority Conversion Timer Trigger Selection Register 0x38 8 read-write 0x00 0x0F PRTSL Priority conversion timer trigger selection bit 0 3 read-write SCTSL Scan Conversion Timer Trigger Selection Register 0x39 8 read-write 0x00 0x0F SCTSL Scan conversion timer trigger selection bit 0 3 read-write ADCEN A/D Operation Enable Setup Register 0x3C 16 read-write 0xFF00 0xFF03 ENBLTIME Basic cycle selection bit 8 15 read-write READY A/D operation enable state bit 1 1 read-only ENBL A/D operation enable bit 0 0 read-write DAC D/A Converter DAC 0x40028000 0x0 0x3 registers 0x4 0x3 registers DADR0 D/A Data Register 0x0 16 read-write 0x0 0x0 DA9 Bit9 of DADR0 9 9 read-write DA8 Bit8 of DADR0 8 8 read-write DA7 Bit7 of DADR0 7 7 read-write DA6 Bit6 of DADR0 6 6 read-write DA5 Bit5 of DADR0 5 5 read-write DA4 Bit4 of DADR0 4 4 read-write DA3 Bit3 of DADR0 3 3 read-write DA2 Bit2 of DADR0 2 2 read-write DA1 Bit1 of DADR0 1 1 read-write DA0 Bit0 of DADR0 0 0 read-write DACR0 D/A Control Register 0x2 8 read-write 0x0 0x0 DAE D/A converter operation enable bit 0 0 read-write DADR1 D/A Data Register 0x4 16 read-write 0x0 0x0 DA9 Bit9 of DADR1 9 9 read-write DA8 Bit8 of DADR1 8 8 read-write DA7 Bit7 of DADR1 7 7 read-write DA6 Bit6 of DADR1 6 6 read-write DA5 Bit5 of DADR1 5 5 read-write DA4 Bit4 of DADR1 4 4 read-write DA3 Bit3 of DADR1 3 3 read-write DA2 Bit2 of DADR1 2 2 read-write DA1 Bit1 of DADR1 1 1 read-write DA0 Bit0 of DADR1 0 0 read-write DACR1 D/A Control Register 0x6 8 read-write 0x0 0x0 DAE D/A converter operation enable bit 0 0 read-write EXTI External Interrupt and NMI Control EXTI 0x40030000 0x0 0x2 registers 0x4 0x2 registers 0x8 0x2 registers 0xC 0x4 registers 0x14 0x1 registers 0x18 0x1 registers EXTINT0_7 4 EXTINT8_15 5 ENIR Enable Interrupt Request Register 0x0 16 read-write 0x0000 0xC1FF EN15 Bit15 of ENIR 15 15 read-write EN14 Bit14 of ENIR 14 14 read-write EN8 Bit8 of ENIR 8 8 read-write EN7 Bit7 of ENIR 7 7 read-write EN6 Bit6 of ENIR 6 6 read-write EN5 Bit5 of ENIR 5 5 read-write EN4 Bit4 of ENIR 4 4 read-write EN3 Bit3 of ENIR 3 3 read-write EN2 Bit2 of ENIR 2 2 read-write EN1 Bit1 of ENIR 1 1 read-write EN0 Bit0 of ENIR 0 0 read-write EIRR External Interrupt Request Register 0x4 16 read-only 0x0000 0x0000 ER15 Bit15 of EIRR 15 15 read-only ER14 Bit14 of EIRR 14 14 read-only ER8 Bit8 of EIRR 8 8 read-only ER7 Bit7 of EIRR 7 7 read-only ER6 Bit6 of EIRR 6 6 read-only ER5 Bit5 of EIRR 5 5 read-only ER4 Bit4 of EIRR 4 4 read-only ER3 Bit3 of EIRR 3 3 read-only ER2 Bit2 of EIRR 2 2 read-only ER1 Bit1 of EIRR 1 1 read-only ER0 Bit0 of EIRR 0 0 read-only EICL External Interrupt Clear Register 0x8 16 read-write 0xFFFF 0xC1FF ECL15 Bit15 of EICL 15 15 read-write ECL14 Bit14 of EICL 14 14 read-write ECL8 Bit8 of EICL 8 8 read-write ECL7 Bit7 of EICL 7 7 read-write ECL6 Bit6 of EICL 6 6 read-write ECL5 Bit5 of EICL 5 5 read-write ECL4 Bit4 of EICL 4 4 read-write ECL3 Bit3 of EICL 3 3 read-write ECL2 Bit2 of EICL 2 2 read-write ECL1 Bit1 of EICL 1 1 read-write ECL0 Bit0 of EICL 0 0 read-write ELVR External Interrupt Level Register 0xC 32 read-write 0x00000000 0xF003FFFF LB15 Bit31 of ELVR 31 31 read-write LA15 Bit30 of ELVR 30 30 read-write LB14 Bit29 of ELVR 29 29 read-write LA14 Bit28 of ELVR 28 28 read-write LB8 Bit17 of ELVR 17 17 read-write LA8 Bit16 of ELVR 16 16 read-write LB7 Bit15 of ELVR 15 15 read-write LA7 Bit14 of ELVR 14 14 read-write LB6 Bit13 of ELVR 13 13 read-write LA6 Bit12 of ELVR 12 12 read-write LB5 Bit11 of ELVR 11 11 read-write LA5 Bit10 of ELVR 10 10 read-write LB4 Bit9 of ELVR 9 9 read-write LA4 Bit8 of ELVR 8 8 read-write LB3 Bit7 of ELVR 7 7 read-write LA3 Bit6 of ELVR 6 6 read-write LB2 Bit5 of ELVR 5 5 read-write LA2 Bit4 of ELVR 4 4 read-write LB1 Bit3 of ELVR 3 3 read-write LA1 Bit2 of ELVR 2 2 read-write LB0 Bit1 of ELVR 1 1 read-write LA0 Bit0 of ELVR 0 0 read-write NMIRR Non Maskable Interrupt Request Register 0x14 8 read-only 0x00 0x01 NR NMI interrupt request detection bit 0 0 read-only NMICL Non Maskable Interrupt Clear Register 0x18 8 read-write 0x01 0x01 NCL NMI interrupt cause clear bit 0 0 read-write INTREQ Interrupts INTREQ 0x40031000 0x10 0x94 registers EXC02MON EXC02 batch read register 0x10 32 read-only 0x0 0x3 HWINT Hardware watchdog timer interrupt request 1 1 read-only NMI External NMIX pin interrupt request 0 0 read-only IRQ00MON IRQ00 Batch Read Register 0x14 32 read-only 0x0 0x1 FCSINT Anomalous frequency detection by CSV interrupt request 0 0 read-only IRQ01MON IRQ01 Batch Read Register 0x18 32 read-only 0x0 0x1 SWWDTINT Software watchdog timer interrupt request 0 0 read-only IRQ02MON IRQ02 Batch Read Register 0x1C 32 read-only 0x0 0x1 LVDINT Low voltage detection (LVD) interrupt request 0 0 read-only IRQ03MON IRQ03 Batch Read Register 0x20 32 read-only 0x0 0xF WAVE0INT3 WFG timer 54 interrupt request in MFT unit 0 3 3 read-only WAVE0INT2 WFG timer 32 interrupt request in MFT unit 0 2 2 read-only WAVE0INT1 WFG timer 10 interrupt request in MFT unit 0 1 1 read-only WAVE0INT0 DTIF (motor emergency stop) interrupt request in MFT unit 0 0 0 read-only IRQ04MON IRQ04 Batch Read Register 0x24 32 read-only 0x0 0xFF EXTINT7 Interrupt request on external interrupt ch.7 7 7 read-only EXTINT6 Interrupt request on external interrupt ch.6 6 6 read-only EXTINT5 Interrupt request on external interrupt ch.5 5 5 read-only EXTINT4 Interrupt request on external interrupt ch.4 4 4 read-only EXTINT3 Interrupt request on external interrupt ch.3 3 3 read-only EXTINT2 Interrupt request on external interrupt ch.2 2 2 read-only EXTINT1 Interrupt request on external interrupt ch.1 1 1 read-only EXTINT0 Interrupt request on external interrupt ch.0 0 0 read-only IRQ05MON IRQ05 Batch Read Register 0x28 32 read-only 0x0 0xC1 EXTINT15 Interrupt request on external interrupt ch.15 7 7 read-only EXTINT14 Interrupt request on external interrupt ch.14 6 6 read-only EXTINT8 Interrupt request on external interrupt ch.8 0 0 read-only IRQ06MON IRQ06 Batch Read Register 0x2C 32 read-only 0x0 0x1 MFSINT Reception interrupt request on MFS ch.0 0 0 read-only IRQ07MON IRQ07 Batch Read Register 0x30 32 read-only 0x0 0x3 MFSINT1 Status interrupt request on MFS ch.0 1 1 read-only MFSINT0 Transmission interrupt request on MFS ch.0 0 0 read-only IRQ08MON IRQ08 Batch Read Register 0x34 32 read-only 0x0 0x1 MFSINT Reception interrupt request on MFS ch.1 0 0 read-only IRQ09MON IRQ9 Batch Read Register 0x38 32 read-only 0x0 0x3 MFSINT1 Status interrupt request on MFS ch.1 1 1 read-only MFSINT0 Transmission interrupt request on MFS ch.1 0 0 read-only IRQ10MON IRQ10 Batch Read Register 0x3C 32 read-only 0x0 0x1 MFSINT Reception interrupt request on MFS ch.2 0 0 read-only IRQ11MON IRQ11 Batch Read Register 0x40 32 read-only 0x0 0x3 MFSINT1 Status interrupt request on MFS ch.2 1 1 read-only MFSINT0 Transmission interrupt request on MFS ch.2 0 0 read-only IRQ12MON IRQ12 Batch Read Register 0x44 32 read-only 0x0 0x1 MFSINT Reception interrupt request on MFS ch.3 0 0 read-only IRQ13MON IRQ13 Batch Read Register 0x48 32 read-only 0x0 0x3 MFSINT1 Status interrupt request on MFS ch.3 1 1 read-only MFSINT0 Transmission interrupt request on MFS ch.3 0 0 read-only IRQ14MON IRQ14 Batch Read Register 0x4C 32 read-only 0x0 0x1 MFSINT Reception interrupt request on MFS ch.4 0 0 read-only IRQ15MON IRQ15 Batch Read Register 0x50 32 read-only 0x0 0x3 MFSINT1 Status interrupt request on MFS ch.4 1 1 read-only MFSINT0 Transmission interrupt request on MFS ch.4 0 0 read-only IRQ16MON IRQ16 Batch Read Register 0x54 32 read-only 0x0 0x1 MFSINT Reception interrupt request on MFS ch.5 0 0 read-only IRQ17MON IRQ17 Batch Read Register 0x58 32 read-only 0x0 0x3 MFSINT1 Status interrupt request on MFS ch.5 1 1 read-only MFSINT0 Transmission interrupt request on MFS ch.5 0 0 read-only IRQ18MON IRQ18 Batch Read Register 0x5C 32 read-only 0x0 0x1 MFSINT Reception interrupt request on MFS ch.6 0 0 read-only IRQ19MON IRQ19 Batch Read Register 0x60 32 read-only 0x0 0x3 MFSINT1 Status interrupt request on MFS ch.6 1 1 read-only MFSINT0 Transmission interrupt request on MFS ch.6 0 0 read-only IRQ20MON IRQ20 Batch Read Register 0x64 32 read-only 0x0 0x1 MFSINT Reception interrupt request on MFS ch.7 0 0 read-only IRQ21MON IRQ21 Batch Read Register 0x68 32 read-only 0x0 0x3 MFSINT1 Status interrupt request on MFS ch.7 1 1 read-only MFSINT0 Transmission interrupt request on MFS ch.7 0 0 read-only IRQ22MON IRQ22 Batch Read Register 0x6C 32 read-only 0x0 0x7 PPGINT2 Interrupt request on PPG ch.4 2 2 read-only PPGINT1 Interrupt request on PPG ch.2 1 1 read-only PPGINT0 Interrupt request on PPG ch.0 0 0 read-only IRQ23MON IRQ23 Batch Read Register 0x70 32 read-only 0x0 0x27 RTCINT RTC interrupt request 5 5 read-only MPLLINT Stabilization wait completion interrupt request for main PLL oscillation 2 2 read-only SOSCINT Stabilization wait completion interrupt request for sub-clock oscillation 1 1 read-only MOSCINT Stabilization wait completion interrupt request for main clock oscillation 0 0 read-only IRQ24MON IRQ24 Batch Read Register 0x74 32 read-only 0x0 0xF ADCINT3 Conversion result comparison interrupt request in the corresponding A/D unit 0. 3 3 read-only ADCINT2 FIFO overrun interrupt request in the corresponding A/D unit 0. 2 2 read-only ADCINT1 Scan conversion interrupt request in the corresponding A/D unit 0. 1 1 read-only ADCINT0 Priority conversion interrupt request in the corresponding A/D unit 0. 0 0 read-only IRQ25MON IRQ25 Batch Read Register 0x78 32 read-only 0x0 0x03F FRT0INT5 Zero detection interrupt request on the free run timer ch.2 in the MFT unit 0 5 5 read-only FRT0INT4 Zero detection interrupt request on the free run timer ch.1 in the MFT unit 0 4 4 read-only FRT0INT3 Zero detection interrupt request on the free run timer ch.0 in the MFT unit 0 3 3 read-only FRT0INT2 Peak value detection interrupt request on the free run timer ch.2 in the MFT unit 0 2 2 read-only FRT0INT1 Peak value detection interrupt request on the free run timer ch.1 in the MFT unit 0 1 1 read-only FRT0INT0 Peak value detection interrupt request on the free run timer ch.0 in the MFT unit 0 0 0 read-only IRQ26MON IRQ26 Batch Read Register 0x7C 32 read-only 0x0 0x0F ICU0INT3 Interrupt request on the input capture ch.3 in the MFT unit 0 3 3 read-only ICU0INT2 Interrupt request on the input capture ch.2 in the MFT unit 0 2 2 read-only ICU0INT1 Interrupt request on the input capture ch.1 in the MFT unit 0 1 1 read-only ICU0INT0 Interrupt request on the input capture ch.0 in the MFT unit 0 0 0 read-only IRQ27MON IRQ27 Batch Read Register 0x80 32 read-only 0x0 0x03F OCU0INT5 Interrupt request on the output compare ch.5 in the MFT unit 0 5 5 read-only OCU0INT4 Interrupt request on the output compare ch.4 in the MFT unit 0 4 4 read-only OCU0INT3 Interrupt request on the output compare ch.3 in the MFT unit 0 3 3 read-only OCU0INT2 Interrupt request on the output compare ch.2 in the MFT unit 0 2 2 read-only OCU0INT1 Interrupt request on the output compare ch.1 in the MFT unit 0 1 1 read-only OCU0INT0 Interrupt request on the output compare ch.0 in the MFT unit 0 0 0 read-only IRQ28MON IRQ28 Batch Read Register 0x84 32 read-write 0x0 0xFFFF BTINT15 IRQ1 interrupt request on the base timer ch.7 15 15 read-only BTINT14 IRQ0 interrupt request on the base timer ch.7 14 14 read-only BTINT13 IRQ1 interrupt request on the base timer ch.6 13 13 read-only BTINT12 IRQ0 interrupt request on the base timer ch.6 12 12 read-only BTINT11 IRQ1 interrupt request on the base timer ch.5 11 11 read-only BTINT10 IRQ0 interrupt request on the base timer ch.5 10 10 read-only BTINT9 IRQ1 interrupt request on the base timer ch.4 9 9 read-only BTINT8 IRQ0 interrupt request on the base timer ch.4 8 8 read-only BTINT7 IRQ1 interrupt request on the base timer ch.3 7 7 read-only BTINT6 IRQ0 interrupt request on the base timer ch.3 6 6 read-only BTINT5 IRQ1 interrupt request on the base timer ch.2 5 5 read-only BTINT4 IRQ0 interrupt request on the base timer ch.2 4 4 read-only BTINT3 IRQ1 interrupt request on the base timer ch.1 3 3 read-only BTINT2 IRQ0 interrupt request on the base timer ch.1 2 2 read-only BTINT1 IRQ1 interrupt request on the base timer ch.0 1 1 read-only BTINT0 IRQ0 interrupt request on the base timer ch.0 0 0 read-only IRQ30MON IRQ30 Batch Read Register 0x8C 32 read-write 0x0 0x20 RCEC0INT Interrupt request for HDMI-CEC/Remote Control Reception ch.0 5 5 read-only IRQ31MON IRQ31 Batch Read Register 0x90 32 read-write 0x0 0x40 RCEC1INT Interrupt request for HDMI-CEC/Remote Control Reception ch.1 6 6 read-only GPIO General-purpose I/O ports GPIO 0x40033000 0x0 0x740 registers PFR0 Port function setting register 0 0x0 32 read-write 0x0000001F 0x0000FC9F PF Bit15 of PFR0 15 15 read-write PE Bit14 of PFR0 14 14 read-write PD Bit13 of PFR0 13 13 read-write PC Bit12 of PFR0 12 12 read-write PB Bit11 of PFR0 11 11 read-write PA Bit10 of PFR0 10 10 read-write P7 Bit7 of PFR0 7 7 read-write P4 Bit4 of PFR0 4 4 read-write P3 Bit3 of PFR0 3 3 read-write P2 Bit2 of PFR0 2 2 read-write P1 Bit1 of PFR0 1 1 read-write P0 Bit0 of PFR0 0 0 read-write PFR1 Port function setting register 1 0x4 32 read-write 0x0 0x00000FFF PB Bit11 of PFR1 11 11 read-write PA Bit10 of PFR1 10 10 read-write P9 Bit9 of PFR1 9 9 read-write P8 Bit8 of PFR1 8 8 read-write P7 Bit7 of PFR1 7 7 read-write P6 Bit6 of PFR1 6 6 read-write P5 Bit5 of PFR1 5 5 read-write P4 Bit4 of PFR1 4 4 read-write P3 Bit3 of PFR1 3 3 read-write P2 Bit2 of PFR1 2 2 read-write P1 Bit1 of PFR1 1 1 read-write P0 Bit0 of PFR1 0 0 read-write PFR2 Port function setting register 2 0x8 32 read-write 0x0 0x0000000F P3 Bit3 of PFR2 3 3 read-write P2 Bit2 of PFR2 2 2 read-write P1 Bit1 of PFR2 1 1 read-write P0 Bit0 of PFR2 0 0 read-write PFR3 Port function setting register 3 0xC 32 read-write 0x0 0x0000FE0F PF Bit15 of PFR3 15 15 read-write PE Bit14 of PFR3 14 14 read-write PD Bit13 of PFR3 13 13 read-write PC Bit12 of PFR3 12 12 read-write PB Bit11 of PFR3 11 11 read-write PA Bit10 of PFR3 10 10 read-write P9 Bit9 of PFR3 9 9 read-write P3 Bit3 of PFR3 3 3 read-write P2 Bit2 of PFR3 2 2 read-write P1 Bit1 of PFR3 1 1 read-write P0 Bit0 of PFR3 0 0 read-write PFR4 Port function setting register 4 0x10 32 read-write 0x0 0x00007FF0 PE Bit14 of PFR4 14 14 read-write PD Bit13 of PFR4 13 13 read-write PC Bit12 of PFR4 12 12 read-write PB Bit11 of PFR4 11 11 read-write PA Bit10 of PFR4 10 10 read-write P9 Bit9 of PFR4 9 9 read-write P8 Bit8 of PFR4 8 8 read-write P7 Bit7 of PFR4 7 7 read-write P6 Bit6 of PFR4 6 6 read-write P5 Bit5 of PFR4 5 5 read-write P4 Bit4 of PFR4 4 4 read-write PFR5 Port function setting register 5 0x14 32 read-write 0x0 0x7F P6 Bit6 of PFR5 6 6 read-write P5 Bit5 of PFR5 5 5 read-write P4 Bit4 of PFR5 4 4 read-write P3 Bit3 of PFR5 3 3 read-write P2 Bit2 of PFR5 2 2 read-write P1 Bit1 of PFR5 1 1 read-write P0 Bit0 of PFR5 0 0 read-write PFR6 Port function setting register 6 0x18 32 read-write 0x0 0xF P3 Bit3 of PFR6 3 3 read-write P2 Bit2 of PFR6 2 2 read-write P1 Bit1 of PFR6 1 1 read-write P0 Bit0 of PFR6 0 0 read-write PFR8 Port function setting register 8 0x20 32 read-write 0x0 0x7 P2 Bit2 of PFR8 2 2 read-write P1 Bit1 of PFR8 1 1 read-write P0 Bit0 of PFR8 0 0 read-write PFRE Port function setting register E 0x38 32 read-write 0x0 0xB P3 Bit2 of PFRE 3 3 read-write P2 Bit1 of PFRE 2 2 read-write P0 Bit0 of PFRE 0 0 read-write PCR0 Pull-up Setting Register 0 0x100 PCR1 Pull-up Setting Register 1 0x104 PCR2 Pull-up Setting Register 2 0x108 PCR3 Pull-up Setting Register 3 0x10C PCR4 Pull-up Setting Register 4 0x110 PCR5 Pull-up Setting Register 5 0x114 PCR6 Pull-up Setting Register 6 0x118 PCRE Pull-up Setting Register E 0x138 DDR0 Port input/output direction setting register 0 0x200 32 read-write 0x0 0x0000FC9F PF Bit15 of DDR0 15 15 read-write PE Bit14 of DDR0 14 14 read-write PD Bit13 of DDR0 13 13 read-write PC Bit12 of DDR0 12 12 read-write PB Bit11 of DDR0 11 11 read-write PA Bit10 of DDR0 10 10 read-write P7 Bit7 of DDR0 7 7 read-write P4 Bit4 of DDR0 4 4 read-write P3 Bit3 of DDR0 3 3 read-write P2 Bit2 of DDR0 2 2 read-write P1 Bit1 of DDR0 1 1 read-write P0 Bit0 of DDR0 0 0 read-write DDR1 Port input/output direction setting register 1 0x204 DDR2 Port input/output direction setting register 2 0x208 DDR3 Port input/output direction setting register 3 0x20C DDR4 Port input/output direction setting register 4 0x210 DDR5 Port input/output direction setting register 5 0x214 DDR6 Port input/output direction setting register 6 0x218 DDR8 Port input/output direction setting register 8 0x220 DDRE Port input/output direction setting register E 0x238 PDIR0 Port input data register 0 0x300 PDIR1 Port input data register 1 0x304 PDIR2 Port input data register 2 0x308 PDIR3 Port input data register 3 0x30C PDIR4 Port input data register 4 0x310 PDIR5 Port input data register 5 0x314 PDIR6 Port input data register 6 0x318 PDIR8 Port input data register 8 0x320 PDIRE Port input data register E 0x338 PDOR0 Port output data register 0 0x400 PDOR1 Port output data register 1 0x404 PDOR2 Port output data register 2 0x408 PDOR3 Port output data register 3 0x40C PDOR4 Port output data register 4 0x410 PDOR5 Port output data register 5 0x414 PDOR6 Port output data register 6 0x418 PDOR8 Port output data register 8 0x420 PDORE Port output data register E 0x438 ADE Analog input setting register 0x500 32 read-write 0x00000FFF 0x00000FFF AN11 Bit11 of ADE 11 11 read-write AN10 Bit10 of ADE 10 10 read-write AN9 Bit9 of ADE 9 9 read-write AN8 Bit8 of ADE 8 8 read-write AN7 Bit7 of ADE 7 7 read-write AN6 Bit6 of ADE 6 6 read-write AN5 Bit5 of ADE 5 5 read-write AN4 Bit4 of ADE 4 4 read-write AN3 Bit3 of ADE 3 3 read-write AN2 Bit2 of ADE 2 2 read-write AN1 Bit1 of ADE 1 1 read-write AN0 Bit0 of ADE 0 0 read-write SPSR Special port setting register 0x580 32 read-write 0x5 0x5 MAINXC Main clock(oscillation) pin setting bit 2 2 read-write SUBXC Sub clock(oscillation) pin setting bit 0 0 read-write EPFR00 Extended pin function setting register 00 0x600 32 read-write 0x30000 0x300F7 JTAGEN1S JTAG function select bit1 17 17 read-write JTAGEN0B JTAG function select bit0 16 16 read-write SUBOUTE Sub clock divide output function select bit 6 7 read-write RTCCOE RTC clock output select bit 4 5 read-write CROUTE Internal high-speed CR oscillation output function select bit 1 2 read-write NMIS NMIX function select bit 0 0 read-write EPFR01 Extended pin function setting register 01 0x604 32 read-write 0x0 0xFFFF1FFF IC03S IC03 input select bit 29 31 read-write IC02S IC02 input select bit 26 28 read-write IC01S IC01 input select bit 23 25 read-write IC00S IC00 input select bit 20 22 read-write FRCK0S FRCK0 input select bit 18 19 read-write DTTI0S DTTIX0 input select bit 16 17 read-write DTTI0C DTTIX0 function select bit 12 12 read-write RTO05E RTO05E output select bit 10 11 read-write RTO04E RTO04E output select bit 8 9 read-write RTO03E RTO03E output select bit 6 7 read-write RTO02E RTO02E output select bit 4 5 read-write RTO01E RTO01E output select bit 2 3 read-write RTO00E RTO00E output select bit 0 1 read-write EPFR04 Extended pin function setting register 04 0x610 32 read-write 0x0 0x3F3C3F7C TIOB3S TIOB3 input select bit 28 29 read-write TIOA3E TIOA3E output select bit 26 27 read-write TIOA3S TIOA3 input select bit 24 25 read-write TIOB2S TIOB2 input select bit 20 21 read-write TIOA2E TIOA2 output select bit 18 19 read-write TIOB1S TIOB1 input select bit 12 13 read-write TIOA1E TIOA1E output select bit 10 11 read-write TIOA1S TIOA1 input select bit 8 9 read-write TIOB0S TIOB0 input select bit 4 6 read-write TIOA0E TIOA0 output select bit 2 3 read-write EPFR05 Extended pin function setting register 05 0x614 32 read-write 0x0 0x3F3C3F3C TIOB7S TIOB7 input select Bit 28 29 read-write TIOA7E TIOA7E output select bit 26 27 read-write TIOA7S TIOA7 input select bit 24 25 read-write TIOB6S TIOB6 input select bit 20 21 read-write TIOA6E TIOA6 output select bit 18 19 read-write TIOB5S TIOB5 input select bit 12 13 read-write TIOA5E TIOA5E output select bit 10 11 read-write TIOA5S TIOA5 input select bit 8 9 read-write TIOB4S TIOB4 input select bit 4 5 read-write TIOA4E TIOA4 output select bit 2 3 read-write EPFR06 Extended pin function setting register 06 0x618 32 read-write 0x0 0xF003FFFF EINT15S External interrupt 15 input select bit 30 31 read-write EINT14S External interrupt 14 input select bit 28 29 read-write EINT08S External interrupt 8 input select bit 16 17 read-write EINT07S External interrupt 7 input select bit 14 15 read-write EINT06S External interrupt 6 input select bit 12 13 read-write EINT05S External interrupt 5 input select bit 10 11 read-write EINT04S External interrupt 4 input select bit 8 9 read-write EINT03S External interrupt 3 input select bit 6 7 read-write EINT02S External interrupt 2 input select bit 4 5 read-write EINT01S External interrupt 1 input select bit 2 3 read-write EINT00S External interrupt 0 input select bit 0 1 read-write EPFR07 Extended pin function setting register 07 0x61C 32 read-write 0x0 0x0FFFFFF0 SCK3B SCK3 input/output select bit 26 27 read-write SOT3B SOT3B input/output select bit 24 25 read-write SIN3S SIN3S input select bit 22 23 read-write SCK2B SCK2 input/output select bit 20 21 read-write SOT2B SOT2B input/output select bit 18 19 read-write SIN2S SIN2S input select bit 16 17 read-write SCK1B SCK1 input/output select bit 14 15 read-write SOT1B SCK1B input/output select bit 12 13 read-write SIN1S SIN1S input select bit 10 11 read-write SCK0B SCK0 input/output select bit 8 9 read-write SOT0B SOT0B input/output select bit 6 7 read-write SIN0S SIN0S input select bit 4 5 read-write EPFR08 Extended pin function setting register 08 0x620 32 read-write 0x0 0x0FFFFFFF SCK7B SCK7 input/output select bit 26 27 read-write SOT7B SOT7B input/output select bit 24 25 read-write SIN7S SIN7S input select bit 22 23 read-write SCK6B SCK6 input/output select bit 20 21 read-write SOT6B SOT6B input/output select bit 18 19 read-write SIN6S SIN6S input select bit 16 17 read-write SCK5B SCK5 input/output select bit 14 15 read-write SOT5B SOT5B input/output select bit 12 13 read-write SIN5S SIN5S input select bit 10 11 read-write SCK4B SCK4 input/output select bit 8 9 read-write SOT4B SOT4B input/output select bit 6 7 read-write SIN4S SIN4S input select bit 4 5 read-write CTS4S CTS4S Input Select bits 2 3 read-write RTS4E RTS4E Output Select bits 0 1 read-write EPFR09 Extended pin function setting register 09 0x624 32 read-write 0x0 0x0000F000 ADTRG0S ADTRG0 input select bit 12 15 read-write EPFR14 Extended pin function setting register 14 0x638 32 read-write 0x0 0xC0000000 CEC1B CEC1 Input/Output Select bit 31 31 read-write CEC0B CEC0 Input/Output Select bit 30 30 read-write PZR0 Port Pseudo Open Drain Setting Register 0 0x700 32 read-write 0x0 0x00003000 PC Bit12 of PZR0 12 12 read-write PB Bit11 of PZR0 11 11 read-write PZR6 Port Pseudo Open Drain Setting Register 6 0x718 32 read-write 0x0 0x00000001 P0 Bit0 of PZR6 0 0 read-write PZR8 Port Pseudo Open Drain Setting Register 8 0x720 32 read-write 0x0 0x00000006 P2 Bit2 of PZR8 2 2 read-write P1 Bit1 of PZR8 1 1 read-write HDMICEC0 HDMI-CEC ch.0 HDMICEC0 0x40034000 0x0 0x1 registers 0x4 0x1 registers 0x8 0x1 registers 0xC 0x1 registers 0x40 0x2 registers 0x44 0x2 registers 0x49 0x1 registers 0x4C 0x2 registers 0x50 0x2 registers 0x54 0x2 registers 0x58 0x2 registers 0x5C 0x2 registers 0x61 0x1 registers 0x64 0x2 registers HDMICEC0 30 TXCTRL Transmission Control Register 0x0 8 read-write 0x00 0x3D IBREN Bus error detection interrupt enable bit 5 5 read-write ITSTEN transmission status interrupt enable bit 4 4 read-write EOM EOM setting bit 3 3 read-write START START setting bit 2 2 read-write TXEN Transmission operation enable bit 0 0 read-write TXDATA Transmission Data Register 0x4 8 read-write 0x00 0xFF TXDATA Transmission Data 0 7 read-write TXSTS Transmission Status Register 0x8 8 read-write 0x00 0x31 IBR Bus error detection interrupt request bit 5 5 read-write ITST Transmission status interrupt request bit 4 4 read-write ACKSV ACK cycle value bit 0 0 read-write SFREE Signal Free Time Setting Register 0xC 8 read-write 0x00 0x0F SFREE Signal free time setting bits 0 3 read-write RCST Reception Interrupt Control Register 0x40 8 read-write 0x00 0xFF STIE Start bit interrupt enable bit 7 7 read-write ACKIE ACK interrupt enable bit 6 6 read-write OVFIE Counter overflow interrupt enable bit 5 5 read-write OVFSEL Counter overflow detection condition setting bit 4 4 read-write ST Start bit detection bit 3 3 read-write ACK ACK: ACK detection bit 2 2 read-write EOM EOM detection bit 1 1 read-write OVF Counter overflow detection bit 0 0 read-write RCCR Reception Control Register 0x41 8 read-write 0x00 0x8F THSEL Threshold selection bit 7 7 read-write ADRCE Address comparison enable bit 3 3 read-write MOD1 Operation mode setting bits 2 2 read-write MOD0 Operation mode setting bits 1 1 read-write EN Operation enable bit 0 0 read-write RCDAHW "H" Width Setting Register A 0x44 8 read-write 0x00 0xFF RCDAHW "H" Width Setting A 0 7 read-write RCSHW Start Bit "H" Width Setting Register 0x45 8 read-write 0x00 0xFF RCSHW Start Bit "H" Width Setting 0 7 read-write RCDBHW "H" Width Setting Register B 0x49 8 read-write 0x00 0xFF RCDBHW "H" Width Setting B 0 7 read-write RCADR2 Device Address Setting Register 2 0x4C 8 read-write 0x00 0x1F RCADR2 Device Address 2 0 4 read-write RCADR1 Device Address Setting Register 1 0x4D 8 read-write 0x00 0x1F RCADR1 Device Address 1 0 4 read-write RCDTHL Data Save Register (High-Low) 0x50 8 read-only 0x00 0xFF RCDTHL RCDTHL 0 7 read-only RCDTHH Data Save Register (High-High) 0x51 8 read-only 0x00 0xFF RCDTHH RCDTHH 0 7 read-only RCDTLL Data Save Register (Low-Low) 0x54 8 read-only 0x00 0xFF RCDTLL RCDTLL 0 7 read-only RCDTLH Data Save Register (Low-High) 0x55 8 read-only 0x00 0xFF RCDTLH RCDTLH 0 7 read-only RCCKD Clock Division Setting Register 0x58 16 read-write 0x0000 0x1FFF CKSEL Operating clock selection bit 12 12 read-write CKDIV Operating clock division setting bits 0 11 read-write RCRHW Repeat Code "H" Width Setting Register 0x5C 8 read-write 0x00 0xFF RCRHW "Repeat code "H" width setting bits" 0 7 read-write RCRC Repeat Code Interrupt Control Register 0x5D 8 read-write 0x00 0x11 RCIE Repeat Code Interrupt enable bit 4 4 read-write RC Repeat code detection flag bit 0 0 read-write RCLE Data Bit Width Violation Control Register 0x61 8 read-write 0x00 0xFB LELIE Maximum data bit width violation interrupt enable bit 7 7 read-write LESIE Minimum data bit width violation interrupt enable bit 6 6 read-write LELE Maximum data bit width violation detection enable bit 5 5 read-write LESE Minimum data bit width violation detection enable bit 4 4 read-write EPE Error pulse output enable bit 3 3 read-write LEL Maximum data bit width violation detection flag bit 1 1 read-write LES Minimum data bit width violation detection flag bit 0 0 read-write RCLESW Minimum Data Bit Width Setting Register 0x64 8 read-write 0x00 0xFF RCLESW Minimum data bit width setting bits 0 7 read-write RCLELW Maximum Data Bit Width Setting Register 0x65 8 read-write 0x00 0xFF RCLELW Maximum data bit width setting bits 0 7 read-write HDMICEC1 0x40034100 HDMICEC1 31 LVD Low-voltage Detection LVD 0x40035000 0x0 0x2 registers 0x4 0x1 registers 0x8 0x1 registers 0xC 0x5 registers LVD 2 LVD_CTL Low-voltage Detection Voltage Control Register 0x0 16 read-write 0x8400 0xBCBE LVDRE Low-voltage detection reset operation enable bit 15 15 read-write SVHR Low-voltage detection reset voltage setting bits 10 13 read-write LVDIE Low-voltage detection interrupt enable bit 7 7 read-write SVHI Low-voltage detection interrupt voltage setting bits 2 5 read-write LVDIM Low-voltage detection interrupt low power mode select bit 1 1 read-write LVD_STR Low-voltage Detection Interrupt Register 0x4 8 read-only 0x00 0x80 LVDIR Low-voltage detection interrupt bit 7 7 read-only LVD_CLR Low-voltage Detection Interrupt Clear Register 0x8 8 read-write 0x80 0x80 LVDCL Low-voltage detection interrupt clear bit 7 7 read-write LVD_RLR Low-voltage Detection Voltage Protection Register 0xC 32 read-write 0x00000001 0xFFFFFFFF LVDLCK Low-voltage Detection Voltage Control Register protection bits 0 31 read-write LVD_STR2 Low-voltage Detection Circuit Status Register 0x10 8 read-only 0x40 0xC0 LVDIRDY Low-voltage detection interrupt status flag 7 7 read-only LVDRRDY Low-voltage detection reset status flag 6 6 read-only DS Low Power Consumption Mode DS 0x40035100 0x4 0x1 registers 0x700 0x1 registers 0x704 0x1 registers 0x708 0x2 registers 0x70C 0x2 registers 0x710 0x1 registers 0x800 0x16 registers RCK_CTL Sub Clock Control Register 0x4 8 read-write 0x01 0x03 CECCKE CEC clock control bit 1 1 read-write RTCCKE RTC clock control bit 0 0 read-write PMD_CTL RTC Mode Control Register 0x700 8 read-write 0x00 0x01 RTCE RTC mode control bit 0 0 read-write WRFSR Deep Standby Return Cause Register 1 0x704 8 read-write 0x00 0x03 WLVDH Low-voltage detection reset return bit 1 1 read-write WINITX INITX pin input reset return bit 0 0 read-write WIFSR Deep Standby Return Cause Register 2 0x708 16 read-only 0x0000 0x033F WCEC1I CEC ch.1 interrupt return bit 9 9 read-only WCEC0I CEC ch.0 interrupt return bit 8 8 read-only WUI3 WKUP pin input return bit 3 5 5 read-only WUI2 WKUP pin input return bit 2 4 4 read-only WUI1 WKUP pin input return bit 1 3 3 read-only WUI0 WKUP pin input return bit 0 2 2 read-only WLVDI LVD interrupt return bit 1 1 read-only WRTCI RTC interrupt return bit 0 0 read-only WIER Deep Standby Return Enable Register 0x70C 16 read-write 0x0000 0x033B WCEC1E HDMI-CEC/ Remote Control Reception ch.1 interrupt return enable bit 9 9 read-write WCEC0E HDMI-CEC/ Remote Control Reception ch.0 interrupt return enable bit 8 8 read-write WUI3E WKUP pin input return enable bit 3 5 5 read-write WUI2E WKUP pin input return enable bit 2 4 4 read-write WUI1E WKUP pin input return enable bit 1 3 3 read-write WLVDE LVD interrupt return enable bit 1 1 read-write WRTCE RTC interrupt return enable bit 0 0 read-write WILVR WKUP Pin Input Level Register 0x710 8 read-write 0x00 0x07 WUI3LV WKUP pin input level select bit 3 2 2 read-write WUI2LV WKUP pin input level select bit 2 1 1 read-write WUI1LV WKUP pin input level select bit 1 0 0 read-write BUR01 Backup Registers from 1 0x800 8 read-write 0x00 0xFF BUR02 Backup Registers from 2 0x801 8 read-write 0x00 0xFF BUR03 Backup Registers from 3 0x802 8 read-write 0x00 0xFF BUR04 Backup Registers from 4 0x803 8 read-write 0x00 0xFF BUR05 Backup Registers from 5 0x804 8 read-write 0x00 0xFF BUR06 Backup Registers from 6 0x805 8 read-write 0x00 0xFF BUR07 Backup Registers from 7 0x806 8 read-write 0x00 0xFF BUR08 Backup Registers from 8 0x807 8 read-write 0x00 0xFF BUR09 Backup Registers from 9 0x808 8 read-write 0x00 0xFF BUR10 Backup Registers from 10 0x809 8 read-write 0x00 0xFF BUR11 Backup Registers from 11 0x80A 8 read-write 0x00 0xFF BUR12 Backup Registers from 12 0x80B 8 read-write 0x00 0xFF BUR13 Backup Registers from 13 0x80C 8 read-write 0x00 0xFF BUR14 Backup Registers from 14 0x80D 8 read-write 0x00 0xFF BUR15 Backup Registers from 15 0x80E 8 read-write 0x00 0xFF BUR16 Backup Registers from 16 0x80F 8 read-write 0x00 0xFF MFS0 Multi-function Serial Interface 0 MFS0 0x40038000 0x0 0x2 registers 0x4 0x2 registers 0x8 0x2 registers 0xC 0x2 registers 0x10 0x2 registers 0x1D 0x1 registers MFS0RX 6 MFS0TX 7 UART_SCR Serial Control Register UART 0x1 8 read-write 0x00 0x9F UPCL Programmable Clear bit 7 7 read-write RIE Received interrupt enable bit 4 4 read-write TIE Transmit interrupt enable bit 3 3 read-write TBIE Transmit bus idle interrupt enable bit 2 2 read-write RXE Received operation enable bit 1 1 read-write TXE Transmission operation enable bit 0 0 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write 0x00 0xFD MD Operation mode set bit 5 7 read-write WUCR Wake-up control bit 4 4 read-write SBL Stop bit length select bit 3 3 read-write BDS Transfer direction select bit 2 2 read-write SOE Serial data output enable bit 0 0 read-write UART_SSR Serial Status Register UART 0x5 8 read-write 0x03 0xBF REC Received error flag clear bit 7 7 read-write PE Parity error flag bit (only functions in operation mode 0) 5 5 read-only FRE Framing error flag bit 4 4 read-only ORE Overrun error flag bit 3 3 read-only RDRF Received data full flag bit 2 2 read-only TDRE Transmit data empty flag bit 1 1 read-only TBI Transmit bus idle flag 0 0 read-only UART_ESCR Extended Communication Control Register UART 0x4 8 read-write 0x00 0xFF FLWEN Flow control enable bit 7 7 read-write ESBL Extension stop bit length select bit 6 6 read-write INV Inverted serial data format bit 5 5 read-write PEN Parity enable bit (only functions in operation mode 0) 4 4 read-write P Parity select bit (only functions in operation mode 0) 3 3 read-write L Data length select bit 0 2 read-write UART_RDR Received Data Register UART 0x8 16 read-only 0x0000 0x01FF UART_TDR Transmit Data Register UART 0x8 16 write-only 0x01FF 0x01FF UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write 0x0000 0xFFFF EXT External clock select bit 15 15 read-write BGR1 Baud Rate Generator Registers 1 8 14 read-write BGR0 Baud Rate Generator Registers 0 0 7 read-write CSIO_SCR Serial Control Register CSIO 0x1 8 read-write 0x00 0xFF UPCL Programmable clear bit 7 7 read-write MS Master/Slave function select bit 6 6 read-write SPI SPI corresponding bit 5 5 read-write RIE Received interrupt enable bit 4 4 read-write TIE Transmit interrupt enable bit 3 3 read-write TBIE Transmit bus idle interrupt enable bit 2 2 read-write RXE Data received enable bit 1 1 read-write TXE Data transmission enable bit 0 0 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write 0x00 0xFF MD Operation mode set bits 5 7 read-write WUCR Wake-up control bit 4 4 read-write SCINV Serial clock invert bit 3 3 read-write BDS Transfer direction select bit 2 2 read-write SCKE Master mode serial clock output enable bit 1 1 read-write SOE Serial data output enable bit 0 0 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write 0x03 0x8F REC Received error flag clear bit 7 7 read-write ORE Overrun error flag bit 3 3 read-only RDRF Received data full flag bit 2 2 read-only TDRE Transmit data empty flag bit 1 1 read-only TBI Transmit bus idle flag bit 0 0 read-only CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write 0x00 0x9F SOP Serial output pin set bit 7 7 read-write WT Data transmit/received wait select bits 3 4 read-write L Data length select bits 0 2 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only 0x0000 0x01FF CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only 0x01FF 0x01FF CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write 0x0000 0x7FFF BGR1 Baud Rate Generator Registers 1 8 14 read-write BGR0 Baud Rate Generator Registers 0 0 7 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write 0x00 0xFF MSS Master/slave select bit 7 7 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 6 read-write ACKE Data byte acknowledge enable bit 5 5 read-write WSEL Wait selection bit 4 4 read-write CNDE Condition detection interrupt enable bit 3 3 read-write INTE Interrupt enable bit 2 2 read-write BER Bus error flag bit 1 1 read-only INT interrupt flag bit 0 0 read-write I2C_SMR Serial Mode Register I2C 0x0 8 read-write 0x00 0xFC MD operation mode set bits 5 7 read-write WUCR Wake-up control bit 4 4 read-write RIE Received interrupt enable bit 3 3 read-write TIE Transmit interrupt enable bit 2 2 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write 0x00 0xFF FBT First byte bit 7 7 read-only RACK Acknowledge flag bit 6 6 read-only RSA Reserved address detection bit 5 5 read-only TRX Data direction bit 4 4 read-only AL Arbitration lost bit 3 3 read-only RSC Iteration start condition check bit 2 2 read-write SPC Stop condition check bit 1 1 read-write BB Bus state bit 0 0 read-only I2C_SSR Serial Status Register I2C 0x5 8 read-write 0x03 0xFF REC Received error flag clear bit 7 7 read-write TSET Transmit empty flag set bit 6 6 read-write DMA DMA mode enable bit 5 5 read-write TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 4 read-write ORE Overrun error flag bit 3 3 read-only RDRF Received data full flag bit 2 2 read-only TDRE Transmit data empty flag bit 1 1 read-only TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 0 read-only I2C_RDR Received Data Register I2C 0x8 16 read-only 0x0000 0x00FF I2C_TDR Transmit Data Register I2C 0x8 16 write-only 0x00FF 0x00FF I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write 0x7F 0xFF EN I2C interface operation enable bit 7 7 read-write SM Slave address mask bits 0 6 read-write I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write 0x00 0xFF SAEN Slave address enable bit 7 7 read-write SA 7-bit slave address 0 6 read-write I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write 0x0000 0x7FFF BGR1 Baud Rate Generator Registers 1 8 14 read-write BGR0 Baud Rate Generator Registers 0 0 7 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write 0x0C 0x3F SDAS SDA status bit 5 5 read-write SCLS SCL status bit 4 4 read-write SDAC SDA output control bit 3 3 read-write SCLC SCL output control bit 2 2 read-write SOCE Serial output enabled bit 1 1 read-write BEC Bus error control bit 0 0 read-write MFS1 0x40038100 MFS1RX 8 MFS1TX 9 MFS2 0x40038200 MFS2RX 10 MFS2TX 11 MFS3 0x40038300 MFS3RX 12 MFS3TX 13 MFS4 0x40038400 MFS4RX 14 MFS4TX 15 MFS5 0x40038500 MFS5RX 16 MFS5TX 17 MFS6 0x40038600 MFS6RX 18 MFS6TX 19 MFS7 0x40038700 MFS7RX 20 MFS7TX 21 RTC REAL-TIME CLOCK RTC 0x4003B000 0x0 0x13 registers 0x15 0x3 registers 0x19 0x2 registers 0x1C 0x4 registers 0x20 0x2 registers 0x24 0x3 registers 0x28 0x2 registers 0x2C 0x1 registers 0x30 0x1 registers WTCR1 Control Register 1 0x0 32 read-write 0x00000000 0xFFFF1F7D INTCRIE Year/month/date/hour/minute/second/day of the week counter value read completion interrupt enable bit 31 31 read-write INTERIE Time rewrite error interrupt enable bit 30 30 read-write INTALIE Alarm interrupt enable bit 29 29 read-write INTTMIE Timer interrupt enable bit 28 28 read-write INTHIE 1-hour interrupt enable bit 27 27 read-write INTMIE 1-minute interrupt enable bit 26 26 read-write INTSIE 1-second interrupt enable bit 25 25 read-write INTSSIE 0.5-second interrupt enable bit 24 24 read-write INTCRI Year/month/date/hour/minute/second/day of the week counter value read completion interrupt flag bit 23 23 read-write INTERI Time rewrite error interrupt flag bit 22 22 read-write INTALI Alarm interrupt flag bit 21 21 read-write INTTMI Timer interrupt flag bit 20 20 read-write INTHI 1-hour interrupt flag bit 19 19 read-write INTMI 1-minute interrupt flag bit 18 18 read-write INTSI 1-second interrupt flag bit 17 17 read-write INTSSI 0.5-second interrupt flag bit 16 16 read-write YEN Alarm year register enable bit 12 12 read-write MOEN Alarm month register enable bit 11 11 read-write DEN Alarm date register enable bit 10 10 read-write HEN Alarm hour register enable bit 9 9 read-write MIEN Alarm minute register enable bit 8 8 read-write BUSY Busy bit 6 6 read-only SCRST Sub second generation/1-second generation counter reset bit 5 5 read-write SCST 1-second clock output stop bit 4 4 read-write SRST RTC reset bit 3 3 read-write RUN RTC count block operation bit 2 2 read-only ST Start bit 0 0 read-write WTCR2 Control Register 2 0x4 32 read-write 0x00000000 0x00000701 TMRUN Timer counter operation bit 10 10 read-only TMEN Timer counter control bit 9 9 read-write TMST Timer counter start bit 8 8 read-write CREAD Year/month/date/hour/minute/second/day of the week counter value read control bit 0 0 read-write WTBR Counter Cycle Setting Register 0x8 32 read-write 0x00000000 0x00FFFFFF BR23 Bit23 of WTBR 23 23 read-write BR22 Bit22 of WTBR 22 22 read-write BR21 Bit21 of WTBR 21 21 read-write BR20 Bit20 of WTBR 20 20 read-write BR19 Bit19 of WTBR 19 19 read-write BR18 Bit18 of WTBR 18 18 read-write BR17 Bit17 of WTBR 17 17 read-write BR16 Bit16 of WTBR 16 16 read-write BR15 Bit15 of WTBR 15 15 read-write BR14 Bit14 of WTBR 14 14 read-write BR13 Bit13 of WTBR 13 13 read-write BR12 Bit12 of WTBR 12 12 read-write BR11 Bit11 of WTBR 11 11 read-write BR10 Bit10 of WTBR 10 10 read-write BR9 Bit9 of WTBR 9 9 read-write BR8 Bit8 of WTBR 8 8 read-write BR7 Bit7 of WTBR 7 7 read-write BR6 Bit6 of WTBR 6 6 read-write BR5 Bit5 of WTBR 5 5 read-write BR4 Bit4 of WTBR 4 4 read-write BR3 Bit3 of WTBR 3 3 read-write BR2 Bit2 of WTBR 2 2 read-write BR1 Bit1 of WTBR 1 1 read-write BR0 Bit0 of WTBR 0 0 read-write WTDR Date Register 0xF 8 read-write 0x00 0x3F TD the second digit of the date 4 5 read-write D the first digit of the date 0 3 read-write WTHR Hour register 0xE 8 read-write 0x00 0x3F TH the second digit of the hour 4 5 read-write H the first digit of the hour 0 3 read-write WTMIR Minute Register 0xD 8 read-write 0x00 0x7F TMI the second digit of the minute 4 6 read-write MI the first digit of the minute 0 3 read-write WTSR Second Register 0xC 8 read-write 0x00 0x7F TS the second digit of the second 4 6 read-write S the first digit of the second 0 3 read-write WTYR Year Register 0x12 8 read-write 0x00 0xFF TY the second digit of the year 4 7 read-write Y the first digit of the year 0 3 read-write WTMOR Month Register 0x11 8 read-write 0x00 0x1F TMO0 the second digit in the month 4 4 read-write MO the first digit of the month 0 3 read-write WTDW Day of the Week Register 0x10 8 read-write 0x00 0x7 DW Day of the week 0 2 read-write ALDR Alarm Date Register 0x17 8 read-write 0x00 0x3F TAD the second digit of the alarm-set date 4 5 read-write AD the first digit of the alarm-set date 0 3 read-write ALHR Alarm Hour Register 0x16 8 read-write 0x00 0x3F TAH the second digit of the alarm-set hour 4 5 read-write AH the first digit of the alarm-set hour 0 3 read-write ALMIR Alarm Minute Register 0x15 8 read-write 0x00 0x7F TAMI the second digit of the alarm-set minute 4 6 read-write AMI the first digit of the alarm-set minute 0 3 read-write ALYR Alarm Years Register 0x1A 8 read-write 0x00 0xFF TAY the second digit of the alarm-set year 4 7 read-write AY the first digit of the alarm-set year 0 3 read-write ALMOR Alarm Month Register 0x19 8 read-write 0x00 0x1F TAMO0 the second digit of the alarm-set month 4 4 read-write AMO the first digit of the alarm-set month 0 3 read-write WTTR Timer Setting Register 0x1C 32 read-write 0x00000000 0x0003FFFF TM17 Bit17 of WTTR 17 17 read-write TM16 Bit16 of WTTR 16 16 read-write TM15 Bit15 of WTTR 15 15 read-write TM14 Bit14 of WTTR 14 14 read-write TM13 Bit13 of WTTR 13 13 read-write TM12 Bit12 of WTTR 12 12 read-write TM11 Bit11 of WTTR 11 11 read-write TM10 Bit10 of WTTR 10 10 read-write TM9 Bit9 of WTTR 9 9 read-write TM8 Bit8 of WTTR 8 8 read-write TM7 Bit7 of WTTR 7 7 read-write TM6 Bit6 of WTTR 6 6 read-write TM5 Bit5 of WTTR 5 5 read-write TM4 Bit4 of WTTR 4 4 read-write TM3 Bit3 of WTTR 3 3 read-write TM2 Bit2 of WTTR 2 2 read-write TM1 Bit1 of WTTR 1 1 read-write TM0 Bit0 of WTTR 0 0 read-write WTCLKS Clock Selection Register 0x20 8 read-write 0x00 0x01 WTCLKS Input clock selection bit 0 0 read-write WTCLKM Selection Clock Status Register 0x21 8 read-only 0x00 0x03 WTCLKM Clock selection status bit 0 1 read-only WTCAL Frequency Correction Value Setting Register 0x24 16 read-write 0x0000 0x03FF WTCAL Frequency correction value 0 9 read-write WTCALEN Frequency Correction Enable Register 0x26 8 read-write 0x00 0x01 WTCALEN Frequency correction enable bit 0 0 read-write WTDIV Divider Ratio Setting Register 0x28 8 read-write 0x00 0x0F WTDIV Divider ratio 0 3 read-write WTDIVEN Divider Output Enable Register 0x29 8 read-write 0x00 0x03 WTDIVRDY Divider status bit 1 1 read-only WTDIVEN Divider enable bit 0 0 read-write WTCALPRD Frequency Correction Cycle Setting Register 0x2C 8 read-write 0x13 0x3F WTCALPRD frequency correction value 0 5 read-write WTCOSEL RTCCO Output Selection Register 0x30 8 read-write 0x00 0x01 WTCOSEL RTCCO output selection bit 0 0 read-write