Freescale Semiconductor, Inc. Freescale Kinetis_W MKW30Z4 1.6 MKW30Z4 Freescale Microcontroller Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. 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CM0PLUS r0p0 little false false true 2 false 8 32 FTFA_FlashConfig Flash configuration field NV_ 0x400 0 0xE registers BACKKEY3 Backdoor Comparison Key 3. 0 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY2 Backdoor Comparison Key 2. 0x1 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY1 Backdoor Comparison Key 1. 0x2 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY0 Backdoor Comparison Key 0. 0x3 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY7 Backdoor Comparison Key 7. 0x4 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY6 Backdoor Comparison Key 6. 0x5 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY5 Backdoor Comparison Key 5. 0x6 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY4 Backdoor Comparison Key 4. 0x7 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only FPROT3 Non-volatile P-Flash Protection 1 - Low Register 0x8 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FPROT2 Non-volatile P-Flash Protection 1 - High Register 0x9 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FPROT1 Non-volatile P-Flash Protection 0 - Low Register 0xA 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FPROT0 Non-volatile P-Flash Protection 0 - High Register 0xB 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FSEC Non-volatile Flash Security Register 0xC 8 read-only 0xFF 0xFF SEC Flash Security 0 2 read-only 10 MCU security status is unsecure #10 11 MCU security status is secure #11 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 10 Freescale factory access denied #10 11 Freescale factory access granted #11 MEEN no description available 4 2 read-only 10 Mass erase is disabled #10 11 Mass erase is enabled #11 KEYEN Backdoor Key Security Enable 6 2 read-only 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 FOPT Non-volatile Flash Option Register 0xD 8 read-only 0xFF 0xFF LPBOOT0 no description available 0 1 read-only 00 Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. #0 01 Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. #1 NMI_DIS no description available 2 1 read-only 00 NMI interrupts are always blocked #0 01 NMI_b pin/interrupts reset default to enabled #1 RESET_PIN_CFG no description available 3 1 read-only 00 RESET pin is disabled following a POR and cannot be enabled as reset function #0 01 RESET_b pin is dedicated #1 LPBOOT1 no description available 4 1 read-only 00 Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. #0 01 Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. #1 FAST_INIT no description available 5 1 read-only 00 Slower initialization #0 01 Fast Initialization #1 DMA DMA Controller DMA_ 0x40008000 0x100 0x40 registers DMA0 0 DMA1 1 DMA2 2 DMA3 3 SAR0 Source Address Register 0x100 32 read-write 0 0xFFFFFFFF SAR SAR 0 32 read-write DAR0 Destination Address Register 0x104 32 read-write 0 0xFFFFFFFF DAR DAR 0 32 read-write DSR_BCR0 DMA Status Register / Byte Count Register 0x108 32 read-write 0 0xFFFFFFFF BCR BCR 0 24 read-write DONE Transactions Done 24 1 read-write 0 DMA transfer is not yet complete. Writing a 0 has no effect. #0 1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits. #1 BSY Busy 25 1 read-only 0 DMA channel is inactive. Cleared when the DMA has finished the last transaction. #0 1 BSY is set the first time the channel is enabled after a transfer is initiated. #1 REQ Request 26 1 read-only 0 No request is pending or the channel is currently active. Cleared when the channel is selected. #0 1 The DMA channel has a transfer remaining and the channel is not selected. #1 BED Bus Error on Destination 28 1 read-only 0 No bus error occurred. #0 1 The DMA channel terminated with a bus error during the write portion of a transfer. #1 BES Bus Error on Source 29 1 read-only 0 No bus error occurred. #0 1 The DMA channel terminated with a bus error during the read portion of a transfer. #1 CE Configuration Error 30 1 read-only 0 No configuration error exists. #0 1 A configuration error has occurred. #1 DSR0 DMA_DSR0 register. 0x10B 8 read-write 0 0xFF DCR0 DMA Control Register 0x10C 32 read-write 0 0xFFFFFFFF LCH2 Link Channel 2 0 2 read-write 00 DMA Channel 0 #00 01 DMA Channel 1 #01 10 DMA Channel 2 #10 11 DMA Channel 3 #11 LCH1 Link Channel 1 2 2 read-write 00 DMA Channel 0 #00 01 DMA Channel 1 #01 10 DMA Channel 2 #10 11 DMA Channel 3 #11 LINKCC Link Channel Control 4 2 read-write 00 No channel-to-channel linking #00 01 Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0. #01 10 Perform a link to channel LCH1 after each cycle-steal transfer #10 11 Perform a link to channel LCH1 after the BCR decrements to 0. #11 D_REQ Disable Request 7 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the BCR is exhausted. #1 DMOD Destination Address Modulo 8 4 read-write 0000 Buffer disabled #0000 0001 Circular buffer size is 16 bytes #0001 0010 Circular buffer size is 32 bytes #0010 0011 Circular buffer size is 64 bytes #0011 0100 Circular buffer size is 128 bytes #0100 0101 Circular buffer size is 256 bytes #0101 0110 Circular buffer size is 512 bytes #0110 0111 Circular buffer size is 1 KB #0111 1000 Circular buffer size is 2 KB #1000 1001 Circular buffer size is 4 KB #1001 1010 Circular buffer size is 8 KB #1010 1011 Circular buffer size is 16 KB #1011 1100 Circular buffer size is 32 KB #1100 1101 Circular buffer size is 64 KB #1101 1110 Circular buffer size is 128 KB #1110 1111 Circular buffer size is 256 KB #1111 SMOD Source Address Modulo 12 4 read-write 0000 Buffer disabled #0000 0001 Circular buffer size is 16 bytes. #0001 0010 Circular buffer size is 32 bytes. #0010 0011 Circular buffer size is 64 bytes. #0011 0100 Circular buffer size is 128 bytes. #0100 0101 Circular buffer size is 256 bytes. #0101 0110 Circular buffer size is 512 bytes. #0110 0111 Circular buffer size is 1 KB. #0111 1000 Circular buffer size is 2 KB. #1000 1001 Circular buffer size is 4 KB. #1001 1010 Circular buffer size is 8 KB. #1010 1011 Circular buffer size is 16 KB. #1011 1100 Circular buffer size is 32 KB. #1100 1101 Circular buffer size is 64 KB. #1101 1110 Circular buffer size is 128 KB. #1110 1111 Circular buffer size is 256 KB. #1111 START Start Transfer 16 1 write-only 0 DMA inactive #0 1 The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0. #1 DSIZE Destination Size 17 2 read-write 00 32-bit #00 01 8-bit #01 10 16-bit #10 11 Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) #11 DINC Destination Increment 19 1 read-write 0 No change to the DAR after a successful transfer. #0 1 The DAR increments by 1, 2, 4 depending upon the size of the transfer. #1 SSIZE Source Size 20 2 read-write 00 32-bit #00 01 8-bit #01 10 16-bit #10 11 Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) #11 SINC Source Increment 22 1 read-write 0 No change to SAR after a successful transfer. #0 1 The SAR increments by 1, 2, 4 as determined by the transfer size. #1 EADREQ Enable asynchronous DMA requests 23 1 read-write 0 Disabled #0 1 Enabled #1 AA Auto-align 28 1 read-write 0 Auto-align disabled #0 1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC. #1 CS Cycle Steal 29 1 read-write 0 DMA continuously makes read/write transfers until the BCR decrements to 0. #0 1 Forces a single read/write transfer per request. #1 ERQ Enable Peripheral Request 30 1 read-write 0 Peripheral request is ignored. #0 1 Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled. #1 EINT Enable Interrupt on Completion of Transfer 31 1 read-write 0 No interrupt is generated. #0 1 SINT asserts. Interrupt signal is enabled. #1 SAR1 Source Address Register 0x110 32 read-write 0 0xFFFFFFFF SAR SAR 0 32 read-write DAR1 Destination Address Register 0x114 32 read-write 0 0xFFFFFFFF DAR DAR 0 32 read-write DSR_BCR1 DMA Status Register / Byte Count Register 0x118 32 read-write 0 0xFFFFFFFF BCR BCR 0 24 read-write DONE Transactions Done 24 1 read-write 0 DMA transfer is not yet complete. Writing a 0 has no effect. #0 1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits. #1 BSY Busy 25 1 read-only 0 DMA channel is inactive. Cleared when the DMA has finished the last transaction. #0 1 BSY is set the first time the channel is enabled after a transfer is initiated. #1 REQ Request 26 1 read-only 0 No request is pending or the channel is currently active. Cleared when the channel is selected. #0 1 The DMA channel has a transfer remaining and the channel is not selected. #1 BED Bus Error on Destination 28 1 read-only 0 No bus error occurred. #0 1 The DMA channel terminated with a bus error during the write portion of a transfer. #1 BES Bus Error on Source 29 1 read-only 0 No bus error occurred. #0 1 The DMA channel terminated with a bus error during the read portion of a transfer. #1 CE Configuration Error 30 1 read-only 0 No configuration error exists. #0 1 A configuration error has occurred. #1 DSR1 DMA_DSR1 register. 0x11B 8 read-write 0 0xFF DCR1 DMA Control Register 0x11C 32 read-write 0 0xFFFFFFFF LCH2 Link Channel 2 0 2 read-write 00 DMA Channel 0 #00 01 DMA Channel 1 #01 10 DMA Channel 2 #10 11 DMA Channel 3 #11 LCH1 Link Channel 1 2 2 read-write 00 DMA Channel 0 #00 01 DMA Channel 1 #01 10 DMA Channel 2 #10 11 DMA Channel 3 #11 LINKCC Link Channel Control 4 2 read-write 00 No channel-to-channel linking #00 01 Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0. #01 10 Perform a link to channel LCH1 after each cycle-steal transfer #10 11 Perform a link to channel LCH1 after the BCR decrements to 0. #11 D_REQ Disable Request 7 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the BCR is exhausted. #1 DMOD Destination Address Modulo 8 4 read-write 0000 Buffer disabled #0000 0001 Circular buffer size is 16 bytes #0001 0010 Circular buffer size is 32 bytes #0010 0011 Circular buffer size is 64 bytes #0011 0100 Circular buffer size is 128 bytes #0100 0101 Circular buffer size is 256 bytes #0101 0110 Circular buffer size is 512 bytes #0110 0111 Circular buffer size is 1 KB #0111 1000 Circular buffer size is 2 KB #1000 1001 Circular buffer size is 4 KB #1001 1010 Circular buffer size is 8 KB #1010 1011 Circular buffer size is 16 KB #1011 1100 Circular buffer size is 32 KB #1100 1101 Circular buffer size is 64 KB #1101 1110 Circular buffer size is 128 KB #1110 1111 Circular buffer size is 256 KB #1111 SMOD Source Address Modulo 12 4 read-write 0000 Buffer disabled #0000 0001 Circular buffer size is 16 bytes. #0001 0010 Circular buffer size is 32 bytes. #0010 0011 Circular buffer size is 64 bytes. #0011 0100 Circular buffer size is 128 bytes. #0100 0101 Circular buffer size is 256 bytes. #0101 0110 Circular buffer size is 512 bytes. #0110 0111 Circular buffer size is 1 KB. #0111 1000 Circular buffer size is 2 KB. #1000 1001 Circular buffer size is 4 KB. #1001 1010 Circular buffer size is 8 KB. #1010 1011 Circular buffer size is 16 KB. #1011 1100 Circular buffer size is 32 KB. #1100 1101 Circular buffer size is 64 KB. #1101 1110 Circular buffer size is 128 KB. #1110 1111 Circular buffer size is 256 KB. #1111 START Start Transfer 16 1 write-only 0 DMA inactive #0 1 The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0. #1 DSIZE Destination Size 17 2 read-write 00 32-bit #00 01 8-bit #01 10 16-bit #10 11 Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) #11 DINC Destination Increment 19 1 read-write 0 No change to the DAR after a successful transfer. #0 1 The DAR increments by 1, 2, 4 depending upon the size of the transfer. #1 SSIZE Source Size 20 2 read-write 00 32-bit #00 01 8-bit #01 10 16-bit #10 11 Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) #11 SINC Source Increment 22 1 read-write 0 No change to SAR after a successful transfer. #0 1 The SAR increments by 1, 2, 4 as determined by the transfer size. #1 EADREQ Enable asynchronous DMA requests 23 1 read-write 0 Disabled #0 1 Enabled #1 AA Auto-align 28 1 read-write 0 Auto-align disabled #0 1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC. #1 CS Cycle Steal 29 1 read-write 0 DMA continuously makes read/write transfers until the BCR decrements to 0. #0 1 Forces a single read/write transfer per request. #1 ERQ Enable Peripheral Request 30 1 read-write 0 Peripheral request is ignored. #0 1 Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled. #1 EINT Enable Interrupt on Completion of Transfer 31 1 read-write 0 No interrupt is generated. #0 1 SINT asserts. Interrupt signal is enabled. #1 SAR2 Source Address Register 0x120 32 read-write 0 0xFFFFFFFF SAR SAR 0 32 read-write DAR2 Destination Address Register 0x124 32 read-write 0 0xFFFFFFFF DAR DAR 0 32 read-write DSR_BCR2 DMA Status Register / Byte Count Register 0x128 32 read-write 0 0xFFFFFFFF BCR BCR 0 24 read-write DONE Transactions Done 24 1 read-write 0 DMA transfer is not yet complete. Writing a 0 has no effect. #0 1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits. #1 BSY Busy 25 1 read-only 0 DMA channel is inactive. Cleared when the DMA has finished the last transaction. #0 1 BSY is set the first time the channel is enabled after a transfer is initiated. #1 REQ Request 26 1 read-only 0 No request is pending or the channel is currently active. Cleared when the channel is selected. #0 1 The DMA channel has a transfer remaining and the channel is not selected. #1 BED Bus Error on Destination 28 1 read-only 0 No bus error occurred. #0 1 The DMA channel terminated with a bus error during the write portion of a transfer. #1 BES Bus Error on Source 29 1 read-only 0 No bus error occurred. #0 1 The DMA channel terminated with a bus error during the read portion of a transfer. #1 CE Configuration Error 30 1 read-only 0 No configuration error exists. #0 1 A configuration error has occurred. #1 DSR2 DMA_DSR2 register. 0x12B 8 read-write 0 0xFF DCR2 DMA Control Register 0x12C 32 read-write 0 0xFFFFFFFF LCH2 Link Channel 2 0 2 read-write 00 DMA Channel 0 #00 01 DMA Channel 1 #01 10 DMA Channel 2 #10 11 DMA Channel 3 #11 LCH1 Link Channel 1 2 2 read-write 00 DMA Channel 0 #00 01 DMA Channel 1 #01 10 DMA Channel 2 #10 11 DMA Channel 3 #11 LINKCC Link Channel Control 4 2 read-write 00 No channel-to-channel linking #00 01 Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0. #01 10 Perform a link to channel LCH1 after each cycle-steal transfer #10 11 Perform a link to channel LCH1 after the BCR decrements to 0. #11 D_REQ Disable Request 7 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the BCR is exhausted. #1 DMOD Destination Address Modulo 8 4 read-write 0000 Buffer disabled #0000 0001 Circular buffer size is 16 bytes #0001 0010 Circular buffer size is 32 bytes #0010 0011 Circular buffer size is 64 bytes #0011 0100 Circular buffer size is 128 bytes #0100 0101 Circular buffer size is 256 bytes #0101 0110 Circular buffer size is 512 bytes #0110 0111 Circular buffer size is 1 KB #0111 1000 Circular buffer size is 2 KB #1000 1001 Circular buffer size is 4 KB #1001 1010 Circular buffer size is 8 KB #1010 1011 Circular buffer size is 16 KB #1011 1100 Circular buffer size is 32 KB #1100 1101 Circular buffer size is 64 KB #1101 1110 Circular buffer size is 128 KB #1110 1111 Circular buffer size is 256 KB #1111 SMOD Source Address Modulo 12 4 read-write 0000 Buffer disabled #0000 0001 Circular buffer size is 16 bytes. #0001 0010 Circular buffer size is 32 bytes. #0010 0011 Circular buffer size is 64 bytes. #0011 0100 Circular buffer size is 128 bytes. #0100 0101 Circular buffer size is 256 bytes. #0101 0110 Circular buffer size is 512 bytes. #0110 0111 Circular buffer size is 1 KB. #0111 1000 Circular buffer size is 2 KB. #1000 1001 Circular buffer size is 4 KB. #1001 1010 Circular buffer size is 8 KB. #1010 1011 Circular buffer size is 16 KB. #1011 1100 Circular buffer size is 32 KB. #1100 1101 Circular buffer size is 64 KB. #1101 1110 Circular buffer size is 128 KB. #1110 1111 Circular buffer size is 256 KB. #1111 START Start Transfer 16 1 write-only 0 DMA inactive #0 1 The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0. #1 DSIZE Destination Size 17 2 read-write 00 32-bit #00 01 8-bit #01 10 16-bit #10 11 Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) #11 DINC Destination Increment 19 1 read-write 0 No change to the DAR after a successful transfer. #0 1 The DAR increments by 1, 2, 4 depending upon the size of the transfer. #1 SSIZE Source Size 20 2 read-write 00 32-bit #00 01 8-bit #01 10 16-bit #10 11 Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) #11 SINC Source Increment 22 1 read-write 0 No change to SAR after a successful transfer. #0 1 The SAR increments by 1, 2, 4 as determined by the transfer size. #1 EADREQ Enable asynchronous DMA requests 23 1 read-write 0 Disabled #0 1 Enabled #1 AA Auto-align 28 1 read-write 0 Auto-align disabled #0 1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC. #1 CS Cycle Steal 29 1 read-write 0 DMA continuously makes read/write transfers until the BCR decrements to 0. #0 1 Forces a single read/write transfer per request. #1 ERQ Enable Peripheral Request 30 1 read-write 0 Peripheral request is ignored. #0 1 Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled. #1 EINT Enable Interrupt on Completion of Transfer 31 1 read-write 0 No interrupt is generated. #0 1 SINT asserts. Interrupt signal is enabled. #1 SAR3 Source Address Register 0x130 32 read-write 0 0xFFFFFFFF SAR SAR 0 32 read-write DAR3 Destination Address Register 0x134 32 read-write 0 0xFFFFFFFF DAR DAR 0 32 read-write DSR_BCR3 DMA Status Register / Byte Count Register 0x138 32 read-write 0 0xFFFFFFFF BCR BCR 0 24 read-write DONE Transactions Done 24 1 read-write 0 DMA transfer is not yet complete. Writing a 0 has no effect. #0 1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits. #1 BSY Busy 25 1 read-only 0 DMA channel is inactive. Cleared when the DMA has finished the last transaction. #0 1 BSY is set the first time the channel is enabled after a transfer is initiated. #1 REQ Request 26 1 read-only 0 No request is pending or the channel is currently active. Cleared when the channel is selected. #0 1 The DMA channel has a transfer remaining and the channel is not selected. #1 BED Bus Error on Destination 28 1 read-only 0 No bus error occurred. #0 1 The DMA channel terminated with a bus error during the write portion of a transfer. #1 BES Bus Error on Source 29 1 read-only 0 No bus error occurred. #0 1 The DMA channel terminated with a bus error during the read portion of a transfer. #1 CE Configuration Error 30 1 read-only 0 No configuration error exists. #0 1 A configuration error has occurred. #1 DSR3 DMA_DSR3 register. 0x13B 8 read-write 0 0xFF DCR3 DMA Control Register 0x13C 32 read-write 0 0xFFFFFFFF LCH2 Link Channel 2 0 2 read-write 00 DMA Channel 0 #00 01 DMA Channel 1 #01 10 DMA Channel 2 #10 11 DMA Channel 3 #11 LCH1 Link Channel 1 2 2 read-write 00 DMA Channel 0 #00 01 DMA Channel 1 #01 10 DMA Channel 2 #10 11 DMA Channel 3 #11 LINKCC Link Channel Control 4 2 read-write 00 No channel-to-channel linking #00 01 Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0. #01 10 Perform a link to channel LCH1 after each cycle-steal transfer #10 11 Perform a link to channel LCH1 after the BCR decrements to 0. #11 D_REQ Disable Request 7 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the BCR is exhausted. #1 DMOD Destination Address Modulo 8 4 read-write 0000 Buffer disabled #0000 0001 Circular buffer size is 16 bytes #0001 0010 Circular buffer size is 32 bytes #0010 0011 Circular buffer size is 64 bytes #0011 0100 Circular buffer size is 128 bytes #0100 0101 Circular buffer size is 256 bytes #0101 0110 Circular buffer size is 512 bytes #0110 0111 Circular buffer size is 1 KB #0111 1000 Circular buffer size is 2 KB #1000 1001 Circular buffer size is 4 KB #1001 1010 Circular buffer size is 8 KB #1010 1011 Circular buffer size is 16 KB #1011 1100 Circular buffer size is 32 KB #1100 1101 Circular buffer size is 64 KB #1101 1110 Circular buffer size is 128 KB #1110 1111 Circular buffer size is 256 KB #1111 SMOD Source Address Modulo 12 4 read-write 0000 Buffer disabled #0000 0001 Circular buffer size is 16 bytes. #0001 0010 Circular buffer size is 32 bytes. #0010 0011 Circular buffer size is 64 bytes. #0011 0100 Circular buffer size is 128 bytes. #0100 0101 Circular buffer size is 256 bytes. #0101 0110 Circular buffer size is 512 bytes. #0110 0111 Circular buffer size is 1 KB. #0111 1000 Circular buffer size is 2 KB. #1000 1001 Circular buffer size is 4 KB. #1001 1010 Circular buffer size is 8 KB. #1010 1011 Circular buffer size is 16 KB. #1011 1100 Circular buffer size is 32 KB. #1100 1101 Circular buffer size is 64 KB. #1101 1110 Circular buffer size is 128 KB. #1110 1111 Circular buffer size is 256 KB. #1111 START Start Transfer 16 1 write-only 0 DMA inactive #0 1 The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0. #1 DSIZE Destination Size 17 2 read-write 00 32-bit #00 01 8-bit #01 10 16-bit #10 11 Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) #11 DINC Destination Increment 19 1 read-write 0 No change to the DAR after a successful transfer. #0 1 The DAR increments by 1, 2, 4 depending upon the size of the transfer. #1 SSIZE Source Size 20 2 read-write 00 32-bit #00 01 8-bit #01 10 16-bit #10 11 Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) #11 SINC Source Increment 22 1 read-write 0 No change to SAR after a successful transfer. #0 1 The SAR increments by 1, 2, 4 as determined by the transfer size. #1 EADREQ Enable asynchronous DMA requests 23 1 read-write 0 Disabled #0 1 Enabled #1 AA Auto-align 28 1 read-write 0 Auto-align disabled #0 1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC. #1 CS Cycle Steal 29 1 read-write 0 DMA continuously makes read/write transfers until the BCR decrements to 0. #0 1 Forces a single read/write transfer per request. #1 ERQ Enable Peripheral Request 30 1 read-write 0 Peripheral request is ignored. #0 1 Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled. #1 EINT Enable Interrupt on Completion of Transfer 31 1 read-write 0 No interrupt is generated. #0 1 SINT asserts. Interrupt signal is enabled. #1 FTFA Flash Memory Interface FTFA_ 0x40020000 0 0x2C registers FTFA 5 FSTAT Flash Status Register 0 8 read-write 0 0xFF MGSTAT0 Memory Controller Command Completion Status Flag 0 1 read-only FPVIOL Flash Protection Violation Flag 4 1 read-write 0 No protection violation detected #0 1 Protection violation detected #1 ACCERR Flash Access Error Flag 5 1 read-write 0 No access error detected #0 1 Access error detected #1 RDCOLERR Flash Read Collision Error Flag 6 1 read-write 0 No collision error detected #0 1 Collision error detected #1 CCIF Command Complete Interrupt Flag 7 1 read-write 0 Flash command in progress #0 1 Flash command has completed #1 FCNFG Flash Configuration Register 0x1 8 read-write 0 0xFF ERSSUSP Erase Suspend 4 1 read-write 0 No suspend requested #0 1 Suspend the current Erase Flash Sector command execution. #1 ERSAREQ Erase All Request 5 1 read-only 0 No request or request complete #0 1 Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state. #1 RDCOLLIE Read Collision Error Interrupt Enable 6 1 read-write 0 Read collision error interrupt disabled #0 1 Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]). #1 CCIE Command Complete Interrupt Enable 7 1 read-write 0 Command complete interrupt disabled #0 1 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. #1 FSEC Flash Security Register 0x2 8 read-only 0 0 SEC Flash Security 0 2 read-only 00 MCU security status is secure. #00 01 MCU security status is secure. #01 10 MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.) #10 11 MCU security status is secure. #11 FSLACC Factory Security Level Access Code 2 2 read-only 00 NXP factory access granted #00 01 NXP factory access denied #01 10 NXP factory access denied #10 11 NXP factory access granted #11 MEEN Mass Erase Enable 4 2 read-only 00 Mass erase is enabled #00 01 Mass erase is enabled #01 10 Mass erase is disabled #10 11 Mass erase is enabled #11 KEYEN Backdoor Key Security Enable 6 2 read-only 00 Backdoor key access disabled #00 01 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) #01 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 FOPT Flash Option Register 0x3 8 read-only 0 0 OPT Nonvolatile Option 0 8 read-only 12 0x1 3,2,1,0,7,6,5,4,B,A,9,8 FCCOB%s Flash Common Command Object Registers 0x4 8 read-write 0 0xFF CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write 4 0x1 3,2,1,0 FPROT%s Program Flash Protection Registers 0x10 8 read-write 0 0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 8 0x1 H3,H2,H1,H0,L3,L2,L1,L0 XACC%s Execute-only Access Registers 0x18 8 read-only 0 0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 8 0x1 H3,H2,H1,H0,L3,L2,L1,L0 SACC%s Supervisor-only Access Registers 0x20 8 read-only 0 0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 FACSS Flash Access Segment Size Register 0x28 8 read-only 0 0 SGSIZE Segment Size 0 8 read-only FACSN Flash Access Segment Number Register 0x2B 8 read-only 0 0 NUMSG Number of Segments Indicator 0 8 read-only 100000 Program flash memory is divided into 32 segments (64 Kbytes, 128 Kbytes) #100000 101000 Program flash memory is divided into 40 segments (160 Kbytes) #101000 1000000 Program flash memory is divided into 64 segments (256 Kbytes, 512 Kbytes) #1000000 DMAMUX0 DMA channel multiplexor DMAMUX0_ 0x40021000 0 0x4 registers 4 0x1 0,1,2,3 CHCFG%s Channel Configuration register 0 8 read-write 0 0xFF SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 LPUART0_Rx_Signal #10 3 LPUART0_Tx_Signal #11 16 SPI0_Rx_Signal #10000 17 SPI0_Tx_Signal #10001 18 SPI1_Rx_Signal #10010 19 SPI1_Tx_Signal #10011 20 AESA_Input_FIFO_Signal #10100 21 AESA_Output_FIFO_Signal #10101 22 I2C0_Signal #10110 23 I2C1_Signal #10111 24 TPM0_Channel0_Signal #11000 25 TPM0_Channel1_Signal #11001 26 TPM0_Channel2_Signal #11010 27 TPM0_Channel3_Signal #11011 32 TPM1_Channel0_Signal #100000 33 TPM1_Channel1_Signal #100001 34 TPM2_Channel0_Signal #100010 35 TPM2_Channel1_Signal #100011 40 ADC0_Signal #101000 42 CMP0_Signal #101010 45 DAC0_Signal #101101 47 CMT_Signal #101111 49 PortA_Signal #110001 50 PortB_Signal #110010 51 PortC_Signal #110011 54 TPM0_Overflow_Signal #110110 55 TPM1_Overflow_Signal #110111 56 TPM2_Overflow_Signal #111000 57 TSI0_Signal #111001 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 TRNG0 RNG 0x40029000 0 0xF8 registers TRNG0 13 TRNG0_MCTL RNG Miscellaneous Control Register 0 32 read-write 0x12001 0xFFFFFFFF SAMP_MODE Sample Mode 0 2 read-write 00 use Von Neumann data into both Entropy shifter and Statistical Checker #00 01 use raw data into both Entropy shifter and Statistical Checker #01 10 use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker #10 OSC_DIV Oscillator Divide 2 2 read-write 00 use ring oscillator with no divide #00 01 use ring oscillator divided-by-2 #01 10 use ring oscillator divided-by-4 #10 11 use ring oscillator divided-by-8 #11 UNUSED This bit is unused but write-able. Must be left as zero. 4 1 read-write TRNG_ACC TRNG Access Mode 5 1 read-write RST_DEF Reset Defaults 6 1 write-only FOR_SCLK Force System Clock 7 1 read-write FCT_FAIL Read only: Frequency Count Fail 8 1 read-only FCT_VAL Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT. 9 1 read-only ENT_VAL Read only: Entropy Valid 10 1 read-only TST_OUT Read only: Test point inside ring oscillator. 11 1 read-only ERR Read: Error status 12 1 read-write TSTOP_OK TRNG_OK_TO_STOP 13 1 read-only PRGM Programming Mode Select 16 1 read-write TRNG0_SCMISC RNG Statistical Check Miscellaneous Register 0x4 32 read-write 0x1001F 0xFFFFFFFF LRUN_MAX LONG RUN MAX LIMIT 0 8 read-write RTY_CT RETRY COUNT 16 4 read-write TRNG0_PKRRNG RNG Poker Range Register 0x8 32 read-write 0x9A3 0xFFFFFFFF PKR_RNG Poker Range 0 16 read-write TRNG0_PKRMAX RNG Poker Maximum Limit Register TRNG0 0xC 32 read-write 0x6920 0xFFFFFFFF PKR_MAX Poker Maximum Limit 0 24 read-write TRNG0_PKRSQ RNG Poker Square Calculation Result Register TRNG0 0xC 32 read-only 0 0xFFFFFFFF PKR_SQ Poker Square Calculation Result 0 24 read-only TRNG0_SDCTL RNG Seed Control Register 0x10 32 read-write 0xC8009C4 0xFFFFFFFF SAMP_SIZE Sample Size 0 16 read-write ENT_DLY Entropy Delay 16 16 read-write TRNG0_SBLIM RNG Sparse Bit Limit Register TRNG0 0x14 32 read-write 0x3F 0xFFFFFFFF SB_LIM Sparse Bit Limit 0 10 read-write TRNG0_TOTSAM RNG Total Samples Register TRNG0 0x14 32 read-only 0 0xFFFFFFFF TOT_SAM Total Samples 0 20 read-only TRNG0_FRQMIN RNG Frequency Count Minimum Limit Register 0x18 32 read-write 0x640 0xFFFFFFFF FRQ_MIN Frequency Count Minimum Limit 0 22 read-write TRNG0_FRQCNT RNG Frequency Count Register TRNG0 0x1C 32 read-only 0 0xFFFFFFFF FRQ_CT Frequency Count 0 22 read-only TRNG0_FRQMAX RNG Frequency Count Maximum Limit Register TRNG0 0x1C 32 read-write 0x6400 0xFFFFFFFF FRQ_MAX Frequency Counter Maximum Limit 0 22 read-write TRNG0_SCMC RNG Statistical Check Monobit Count Register TRNG0 0x20 32 read-only 0 0xFFFFFFFF MONO_CT Monobit Count 0 16 read-only TRNG0_SCML RNG Statistical Check Monobit Limit Register TRNG0 0x20 32 read-write 0x10C0568 0xFFFFFFFF MONO_MAX Monobit Maximum Limit 0 16 read-write MONO_RNG Monobit Range 16 16 read-write TRNG0_SCR1C RNG Statistical Check Run Length 1 Count Register TRNG0 0x24 32 read-only 0 0xFFFFFFFF R1_0_CT Runs of Zero, Length 1 Count 0 15 read-only R1_1_CT Runs of One, Length 1 Count 16 15 read-only TRNG0_SCR1L RNG Statistical Check Run Length 1 Limit Register TRNG0 0x24 32 read-write 0xB20195 0xFFFFFFFF RUN1_MAX Run Length 1 Maximum Limit 0 15 read-write RUN1_RNG Run Length 1 Range 16 15 read-write TRNG0_SCR2C RNG Statistical Check Run Length 2 Count Register TRNG0 0x28 32 read-only 0 0xFFFFFFFF R2_0_CT Runs of Zero, Length 2 Count 0 14 read-only R2_1_CT Runs of One, Length 2 Count 16 14 read-only TRNG0_SCR2L RNG Statistical Check Run Length 2 Limit Register TRNG0 0x28 32 read-write 0x7A00DC 0xFFFFFFFF RUN2_MAX Run Length 2 Maximum Limit 0 14 read-write RUN2_RNG Run Length 2 Range 16 14 read-write TRNG0_SCR3C RNG Statistical Check Run Length 3 Count Register TRNG0 0x2C 32 read-only 0 0xFFFFFFFF R3_0_CT Runs of Zeroes, Length 3 Count 0 13 read-only R3_1_CT Runs of Ones, Length 3 Count 16 13 read-only TRNG0_SCR3L RNG Statistical Check Run Length 3 Limit Register TRNG0 0x2C 32 read-write 0x58007D 0xFFFFFFFF RUN3_MAX Run Length 3 Maximum Limit 0 13 read-write RUN3_RNG Run Length 3 Range 16 13 read-write TRNG0_SCR4C RNG Statistical Check Run Length 4 Count Register TRNG0 0x30 32 read-only 0 0xFFFFFFFF R4_0_CT Runs of Zero, Length 4 Count 0 12 read-only R4_1_CT Runs of One, Length 4 Count 16 12 read-only TRNG0_SCR4L RNG Statistical Check Run Length 4 Limit Register TRNG0 0x30 32 read-write 0x40004B 0xFFFFFFFF RUN4_MAX Run Length 4 Maximum Limit 0 12 read-write RUN4_RNG Run Length 4 Range 16 12 read-write TRNG0_SCR5C RNG Statistical Check Run Length 5 Count Register TRNG0 0x34 32 read-only 0 0xFFFFFFFF R5_0_CT Runs of Zero, Length 5 Count 0 11 read-only R5_1_CT Runs of One, Length 5 Count 16 11 read-only TRNG0_SCR5L RNG Statistical Check Run Length 5 Limit Register TRNG0 0x34 32 read-write 0x2E002F 0xFFFFFFFF RUN5_MAX Run Length 5 Maximum Limit 0 11 read-write RUN5_RNG Run Length 5 Range 16 11 read-write TRNG0_SCR6PC RNG Statistical Check Run Length 6+ Count Register TRNG0 0x38 32 read-only 0 0xFFFFFFFF R6P_0_CT Runs of Zero, Length 6+ Count 0 11 read-only R6P_1_CT Runs of One, Length 6+ Count 16 11 read-only TRNG0_SCR6PL RNG Statistical Check Run Length 6+ Limit Register TRNG0 0x38 32 read-write 0x2E002F 0xFFFFFFFF RUN6P_MAX Run Length 6+ Maximum Limit 0 11 read-write RUN6P_RNG Run Length 6+ Range 16 11 read-write TRNG0_STATUS RNG Status Register 0x3C 32 read-only 0 0xFFFFFFFF TF1BR0 Test Fail, 1-Bit Run, Sampling 0s. If TF1BR0=1, the 1-Bit Run, Sampling 0s Test has failed. 0 1 read-only TF1BR1 Test Fail, 1-Bit Run, Sampling 1s. If TF1BR1=1, the 1-Bit Run, Sampling 1s Test has failed. 1 1 read-only TF2BR0 Test Fail, 2-Bit Run, Sampling 0s. If TF2BR0=1, the 2-Bit Run, Sampling 0s Test has failed. 2 1 read-only TF2BR1 Test Fail, 2-Bit Run, Sampling 1s. If TF2BR1=1, the 2-Bit Run, Sampling 1s Test has failed. 3 1 read-only TF3BR0 Test Fail, 3-Bit Run, Sampling 0s. If TF3BR0=1, the 3-Bit Run, Sampling 0s Test has failed. 4 1 read-only TF3BR1 Test Fail, 3-Bit Run, Sampling 1s. If TF3BR1=1, the 3-Bit Run, Sampling 1s Test has failed. 5 1 read-only TF4BR0 Test Fail, 4-Bit Run, Sampling 0s. If TF4BR0=1, the 4-Bit Run, Sampling 0s Test has failed. 6 1 read-only TF4BR1 Test Fail, 4-Bit Run, Sampling 1s. If TF4BR1=1, the 4-Bit Run, Sampling 1s Test has failed. 7 1 read-only TF5BR0 Test Fail, 5-Bit Run, Sampling 0s. If TF5BR0=1, the 5-Bit Run, Sampling 0s Test has failed. 8 1 read-only TF5BR1 Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed. 9 1 read-only TF6PBR0 Test Fail, 6 Plus Bit Run, Sampling 0s 10 1 read-only TF6PBR1 Test Fail, 6 Plus Bit Run, Sampling 1s 11 1 read-only TFSB Test Fail, Sparse Bit. If TFSB=1, the Sparse Bit Test has failed. 12 1 read-only TFLR Test Fail, Long Run. If TFLR=1, the Long Run Test has failed. 13 1 read-only TFP Test Fail, Poker. If TFP=1, the Poker Test has failed. 14 1 read-only TFMB Test Fail, Mono Bit. If TFMB=1, the Mono Bit Test has failed. 15 1 read-only RETRY_CT RETRY COUNT 16 4 read-only TRNG0_ENT0 RNG TRNG Entropy Read Register 0x40 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT1 RNG TRNG Entropy Read Register 0x44 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT2 RNG TRNG Entropy Read Register 0x48 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT3 RNG TRNG Entropy Read Register 0x4C 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT4 RNG TRNG Entropy Read Register 0x50 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT5 RNG TRNG Entropy Read Register 0x54 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT6 RNG TRNG Entropy Read Register 0x58 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT7 RNG TRNG Entropy Read Register 0x5C 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT8 RNG TRNG Entropy Read Register 0x60 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT9 RNG TRNG Entropy Read Register 0x64 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT10 RNG TRNG Entropy Read Register 0x68 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT11 RNG TRNG Entropy Read Register 0x6C 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT12 RNG TRNG Entropy Read Register 0x70 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT13 RNG TRNG Entropy Read Register 0x74 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT14 RNG TRNG Entropy Read Register 0x78 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT15 RNG TRNG Entropy Read Register 0x7C 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_PKRCNT10 RNG Statistical Check Poker Count 1 and 0 Register 0x80 32 read-only 0 0xFFFFFFFF PKR_0_CT Poker 0h Count 0 16 read-only PKR_1_CT Poker 1h Count 16 16 read-only TRNG0_PKRCNT32 RNG Statistical Check Poker Count 3 and 2 Register 0x84 32 read-only 0 0xFFFFFFFF PKR_2_CT Poker 2h Count 0 16 read-only PKR_3_CT Poker 3h Count 16 16 read-only TRNG0_PKRCNT54 RNG Statistical Check Poker Count 5 and 4 Register 0x88 32 read-only 0 0xFFFFFFFF PKR_4_CT Poker 4h Count 0 16 read-only PKR_5_CT Poker 5h Count 16 16 read-only TRNG0_PKRCNT76 RNG Statistical Check Poker Count 7 and 6 Register 0x8C 32 read-only 0 0xFFFFFFFF PKR_6_CT Poker 6h Count 0 16 read-only PKR_7_CT Poker 7h Count 16 16 read-only TRNG0_PKRCNT98 RNG Statistical Check Poker Count 9 and 8 Register 0x90 32 read-only 0 0xFFFFFFFF PKR_8_CT Poker 8h Count 0 16 read-only PKR_9_CT Poker 9h Count 16 16 read-only TRNG0_PKRCNTBA RNG Statistical Check Poker Count B and A Register 0x94 32 read-only 0 0xFFFFFFFF PKR_A_CT Poker Ah Count 0 16 read-only PKR_B_CT Poker Bh Count 16 16 read-only TRNG0_PKRCNTDC RNG Statistical Check Poker Count D and C Register 0x98 32 read-only 0 0xFFFFFFFF PKR_C_CT Poker Ch Count 0 16 read-only PKR_D_CT Poker Dh Count 16 16 read-only TRNG0_PKRCNTFE RNG Statistical Check Poker Count F and E Register 0x9C 32 read-only 0 0xFFFFFFFF PKR_E_CT Poker Eh Count 0 16 read-only PKR_F_CT Poker Fh Count 16 16 read-only TRNG0_SEC_CFG RNG Security Configuration Register 0xB0 32 read-write 0 0xFFFFFFFF SH0 Reserved. DRNG specific, not applicable to this version. 0 1 read-write 0 See DRNG version. #0 1 See DRNG version. #1 NO_PRGM If set the TRNG registers cannot be programmed 1 1 read-write 0 Programability of registers controlled only by the RNG Miscellaneous Control Register's access mode bit. #0 1 Overides RNG Miscellaneous Control Register access mode and prevents TRNG register programming. #1 SK_VAL Reserved. DRNG-specific, not applicable to this version. 2 1 read-write 0 See DRNG version. #0 1 See DRNG version. #1 TRNG0_INT_CTRL RNG Interrupt Control Register 0xB4 32 read-write 0xFFFFFFFF 0xFFFFFFFF HW_ERR Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. 0 1 read-write 0 Corresponding bit of INT_STATUS cleared. #0 1 Corresponding bit of INT_STATUS active. #1 ENT_VAL Same behavior as bit 0 above. 1 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 FRQ_CT_FAIL Same behavior as bit 0 above. 2 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 UNUSED Reserved but writeable. 3 29 read-write TRNG0_INT_MASK RNG Mask Register 0xB8 32 read-write 0 0xFFFFFFFF HW_ERR Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. 0 1 read-write 0 Corresponding interrupt of INT_STATUS is masked. #0 1 Corresponding bit of INT_STATUS is active. #1 ENT_VAL Same behavior as bit 0 above. 1 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 FRQ_CT_FAIL Same behavior as bit 0 above. 2 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 TRNG0_INT_STATUS RNG Interrupt Status Register 0xBC 32 read-write 0 0xFFFFFFFF HW_ERR Read: Error status 0 1 read-only 0 no error #0 1 error detected. #1 ENT_VAL Read only: Entropy Valid 1 1 read-only 0 Busy generation entropy. Any value read is invalid. #0 1 TRNG can be stopped and entropy is valid if read. #1 FRQ_CT_FAIL Read only: Frequency Count Fail 2 1 read-write 0 No hardware nor self test frequency errors. #0 1 The frequency counter has detected a failure. #1 TRNG0_VID1 RNG Version ID Register (MS) 0xF0 32 read-only 0x300100 0xFFFFFFFF RNG_MIN_REV Shows the Freescale IP's Minor revision of the TRNG. 0 8 read-only 0x00 Minor revision number for TRNG. #0 RNG_MAJ_REV Shows the Freescale IP's Major revision of the TRNG. 8 8 read-only 0x01 Major revision number for TRNG. #1 RNG_IP_ID Shows the Freescale IP ID. 16 16 read-only TRNG0_VID2 RNG Version ID Register (LS) 0xF4 32 read-only 0 0xFFFFFFFF RNG_CONFIG_OPT Shows the Freescale IP's Configuaration options for the TRNG. 0 8 read-only 0x00 TRNG_CONFIG_OPT for TRNG. #0 RNG_ECO_REV Shows the Freescale IP's ECO revision of the TRNG. 8 8 read-only 0x00 TRNG_ECO_REV for TRNG. #0 RNG_INTG_OPT Shows the Freescale integration options for the TRNG. 16 8 read-only 0x00 INTG_OPT for TRNG. #0 RNG_ERA Shows the Freescale compile options for the TRNG. 24 8 read-only 0x00 COMPILE_OPT for TRNG. #0 SPI0 Serial Peripheral Interface SPI SPI0_ 0x4002C000 0 0x8C registers SPI0 10 MCR Module Configuration Register 0 32 read-write 0x4001 0xFFFFFFFF HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 SMPL_PT Sample Point 8 2 read-write 00 0 protocol clock cycles between SCK edge and SIN sample #00 01 1 protocol clock cycle between SCK edge and SIN sample #01 10 2 protocol clock cycles between SCK edge and SIN sample #10 CLR_RXF CLR_RXF 10 1 write-only 0 Do not clear the RX FIFO counter. #0 1 Clear the RX FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the TX FIFO counter. #0 1 Clear the TX FIFO counter. #1 DIS_RXF Disable Receive FIFO 12 1 read-write 0 RX FIFO is enabled. #0 1 RX FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 TX FIFO is enabled. #0 1 TX FIFO is disabled. #1 MDIS Module Disable 14 1 read-write 0 Enables the module clocks. #0 1 Allows external logic to disable the module clocks. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on the module. #0 1 Doze mode disables the module. #1 PCSIS Peripheral Chip Select x Inactive State 16 4 read-write 0 The inactive state of PCSx is low. #0000 1 The inactive state of PCSx is high. #0001 ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 MTFE Modified Transfer Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in Debug mode. #0 1 Halt serial transfers in Debug mode. #1 DCONF SPI Configuration. 28 2 read-only 00 SPI #00 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 Enables Slave mode #0 1 Enables Master mode #1 TCR Transfer Count Register 0x8 32 read-write 0 0xFFFFFFFF SPI_TCNT SPI Transfer Counter 16 16 read-write 2 0x4 0,1 CTAR%s Clock and Transfer Attributes Register (In Master Mode) SPI0 0xC 32 read-write 0x78000000 0xFFFFFFFF BR Baud Rate Scaler 0 4 read-write DT Delay After Transfer Scaler 4 4 read-write ASC After SCK Delay Scaler 8 4 read-write CSSCK PCS to SCK Delay Scaler 12 4 read-write PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 CTAR_SLAVE Clock and Transfer Attributes Register (In Slave Mode) SPI0 0xC 32 read-write 0x78000000 0xFFFFFFFF CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write SR Status Register 0x2C 32 read-write 0x2000000 0xFFFFFFFF POPNXTPTR Pop Next Pointer 0 4 read-only RXCTR RX FIFO Counter 4 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXCTR TX FIFO Counter 12 4 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 RX FIFO is empty. #0 1 RX FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 TX FIFO is full. #0 1 TX FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No TX FIFO underflow. #0 1 TX FIFO underflow has occurred. #1 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 TXRXS TX and RX Status 30 1 read-write 0 Transmit and receive operations are disabled (The module is in Stopped state). #0 1 Transmit and receive operations are enabled (The module is in Running state). #1 TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 RSER DMA/Interrupt Request Select and Enable Register 0x30 32 read-write 0 0xFFFFFFFF RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled. #0 1 RFDF interrupt or DMA requests are enabled. #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 EOQF_RE Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 PUSHR PUSH TX FIFO Register In Master Mode SPI0 0x34 32 read-write 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-write PCS Select which PCS signals are to be asserted for the transfer 16 4 read-write 0 Negate the PCS[x] signal #0000 1 Assert the PCS[x] signal. #0001 CTCNT Clear Transfer Counter 26 1 read-write 0 Do not clear the TCR[TCNT] field. #0 1 Clear the TCR[TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 CTAS Clock and Transfer Attributes Select 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 PUSHR_SLAVE PUSH TX FIFO Register In Slave Mode SPI0 0x34 32 read-write 0 0xFFFFFFFF TXDATA Transmit Data 0 32 read-write POPR POP RX FIFO Register 0x38 32 read-only 0 0xFFFFFFFF RXDATA Received Data 0 32 read-only 4 0x4 0,1,2,3 TXFR%s Transmit FIFO Registers 0x3C 32 read-only 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-only TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only 4 0x4 0,1,2,3 RXFR%s Receive FIFO Registers 0x7C 32 read-only 0 0xFFFFFFFF RXDATA Receive Data 0 32 read-only SPI1 Serial Peripheral Interface SPI SPI1_ 0x4002D000 0 0x8C registers SPI1 29 MCR Module Configuration Register 0 32 read-write 0x4001 0xFFFFFFFF HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 SMPL_PT Sample Point 8 2 read-write 00 0 protocol clock cycles between SCK edge and SIN sample #00 01 1 protocol clock cycle between SCK edge and SIN sample #01 10 2 protocol clock cycles between SCK edge and SIN sample #10 CLR_RXF CLR_RXF 10 1 write-only 0 Do not clear the RX FIFO counter. #0 1 Clear the RX FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the TX FIFO counter. #0 1 Clear the TX FIFO counter. #1 DIS_RXF Disable Receive FIFO 12 1 read-write 0 RX FIFO is enabled. #0 1 RX FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 TX FIFO is enabled. #0 1 TX FIFO is disabled. #1 MDIS Module Disable 14 1 read-write 0 Enables the module clocks. #0 1 Allows external logic to disable the module clocks. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on the module. #0 1 Doze mode disables the module. #1 PCSIS Peripheral Chip Select x Inactive State 16 4 read-write 0 The inactive state of PCSx is low. #0000 1 The inactive state of PCSx is high. #0001 ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 MTFE Modified Transfer Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in Debug mode. #0 1 Halt serial transfers in Debug mode. #1 DCONF SPI Configuration. 28 2 read-only 00 SPI #00 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 Enables Slave mode #0 1 Enables Master mode #1 TCR Transfer Count Register 0x8 32 read-write 0 0xFFFFFFFF SPI_TCNT SPI Transfer Counter 16 16 read-write 2 0x4 0,1 CTAR%s Clock and Transfer Attributes Register (In Master Mode) SPI1 0xC 32 read-write 0x78000000 0xFFFFFFFF BR Baud Rate Scaler 0 4 read-write DT Delay After Transfer Scaler 4 4 read-write ASC After SCK Delay Scaler 8 4 read-write CSSCK PCS to SCK Delay Scaler 12 4 read-write PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 CTAR_SLAVE Clock and Transfer Attributes Register (In Slave Mode) SPI1 0xC 32 read-write 0x78000000 0xFFFFFFFF CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write SR Status Register 0x2C 32 read-write 0x2000000 0xFFFFFFFF POPNXTPTR Pop Next Pointer 0 4 read-only RXCTR RX FIFO Counter 4 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXCTR TX FIFO Counter 12 4 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 RX FIFO is empty. #0 1 RX FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 TX FIFO is full. #0 1 TX FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No TX FIFO underflow. #0 1 TX FIFO underflow has occurred. #1 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 TXRXS TX and RX Status 30 1 read-write 0 Transmit and receive operations are disabled (The module is in Stopped state). #0 1 Transmit and receive operations are enabled (The module is in Running state). #1 TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 RSER DMA/Interrupt Request Select and Enable Register 0x30 32 read-write 0 0xFFFFFFFF RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled. #0 1 RFDF interrupt or DMA requests are enabled. #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 EOQF_RE Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 PUSHR PUSH TX FIFO Register In Master Mode SPI1 0x34 32 read-write 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-write PCS Select which PCS signals are to be asserted for the transfer 16 4 read-write 0 Negate the PCS[x] signal #0000 1 Assert the PCS[x] signal. #0001 CTCNT Clear Transfer Counter 26 1 read-write 0 Do not clear the TCR[TCNT] field. #0 1 Clear the TCR[TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 CTAS Clock and Transfer Attributes Select 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 PUSHR_SLAVE PUSH TX FIFO Register In Slave Mode SPI1 0x34 32 read-write 0 0xFFFFFFFF TXDATA Transmit Data 0 32 read-write POPR POP RX FIFO Register 0x38 32 read-only 0 0xFFFFFFFF RXDATA Received Data 0 32 read-only 4 0x4 0,1,2,3 TXFR%s Transmit FIFO Registers 0x3C 32 read-only 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-only TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only 4 0x4 0,1,2,3 RXFR%s Receive FIFO Registers 0x7C 32 read-only 0 0xFFFFFFFF RXDATA Receive Data 0 32 read-only PIT Periodic Interrupt Timer PIT_ 0x40037000 0 0x120 registers PIT 22 MCR PIT Module Control Register 0 32 read-write 0x6 0xFFFFFFFF FRZ Freeze 0 1 read-write 0 Timers continue to run in Debug mode. #0 1 Timers are stopped in Debug mode. #1 MDIS Module Disable - (PIT section) 1 1 read-write 0 Clock for standard PIT timers is enabled. #0 1 Clock for standard PIT timers is disabled. #1 LTMR64H PIT Upper Lifetime Timer Register 0xE0 32 read-only 0 0xFFFFFFFF LTH Life Timer value 0 32 read-only LTMR64L PIT Lower Lifetime Timer Register 0xE4 32 read-only 0 0xFFFFFFFF LTL Life Timer value 0 32 read-only 2 0x10 0,1 LDVAL%s Timer Load Value Register 0x100 32 read-write 0 0xFFFFFFFF TSV Timer Start Value 0 32 read-write 2 0x10 0,1 CVAL%s Current Timer Value Register 0x104 32 read-only 0 0xFFFFFFFF TVL Current Timer Value 0 32 read-only 2 0x10 0,1 TCTRL%s Timer Control Register 0x108 32 read-write 0 0xFFFFFFFF TEN Timer Enable 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is enabled. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 CHN Chain Mode 2 1 read-write 0 Timer is not chained. #0 1 Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. #1 2 0x10 0,1 TFLG%s Timer Flag Register 0x10C 32 read-write 0 0xFFFFFFFF TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 TPM0 Timer/PWM Module TPM TPM0_ 0x40038000 0 0x88 registers TPM0 17 SC Status and Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CMOD Clock Mode Selection 3 2 read-write 00 TPM counter is disabled #00 01 TPM counter increments on every TPM counter clock #01 10 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock #10 CPWMS Center-Aligned PWM Select 5 1 read-write 0 TPM counter operates in up counting mode. #0 1 TPM counter operates in up-down counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling or DMA request. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 DMA DMA Enable 8 1 read-write 0 Disables DMA transfers. #0 1 Enables DMA transfers. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter value 0 16 read-write MOD Modulo 0x8 32 read-write 0xFFFF 0xFFFFFFFF MOD Modulo value 0 16 read-write 4 0x8 0,1,2,3 C%sSC Channel (n) Status and Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 4 0x8 0,1,2,3 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write STATUS Capture and Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 TOF Timer Overflow Flag 8 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 COMBINE Combine Channel Register 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels 0 and 1 0 1 read-write 0 Channels 0 and 1 are independent. #0 1 Channels 0 and 1 are combined. #1 COMSWAP0 Combine Channel 0 and 1 Swap 1 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 COMBINE1 Combine Channels 2 and 3 8 1 read-write 0 Channels 2 and 3 are independent. #0 1 Channels 2 and 3 are combined. #1 COMSWAP1 Combine Channels 2 and 3 Swap 9 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 POL Channel Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FILTER Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Filter Value 0 4 read-write CH1FVAL Channel 1 Filter Value 4 4 read-write CH2FVAL Channel 2 Filter Value 8 4 read-write CH3FVAL Channel 3 Filter Value 12 4 read-write QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Enables the quadrature decoder mode 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 TOFDIR Indicates if the TOF bit was set on the top or the bottom of counting. 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). #1 QUADIR Counter Direction in Quadrature Decode Mode 2 1 read-only 0 Counter direction is decreasing (counter decrement). #0 1 Counter direction is increasing (counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase encoding mode. #0 1 Count and direction encoding mode. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF DOZEEN Doze Enable 5 1 read-write 0 Internal TPM counter continues in Doze mode. #0 1 Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. #1 DBGMODE Debug Mode 6 2 read-write 00 TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. #00 11 TPM counter continues in debug mode. #11 GTBSYNC Global Time Base Synchronization 8 1 read-write 0 Global timebase synchronization disabled. #0 1 Global timebase synchronization enabled. #1 GTBEEN Global time base enable 9 1 read-write 0 All channels use the internally generated TPM counter as their timebase #0 1 All channels use an externally generated global timebase as their timebase #1 CSOT Counter Start on Trigger 16 1 read-write 0 TPM counter starts to increment immediately, once it is enabled. #0 1 TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. #1 CSOO Counter Stop On Overflow 17 1 read-write 0 TPM counter continues incrementing or decrementing after overflow #0 1 TPM counter stops incrementing or decrementing after overflow. #1 CROT Counter Reload On Trigger 18 1 read-write 0 Counter is not reloaded due to a rising edge on the selected input trigger #0 1 Counter is reloaded when a rising edge is detected on the selected input trigger #1 CPOT Counter Pause On Trigger 19 1 read-write TRGPOL Trigger Polarity 22 1 read-write 0 Trigger is active high. #0 1 Trigger is active low. #1 TRGSRC Trigger Source 23 1 read-write 0 Trigger source selected by TRGSEL is external. #0 1 Trigger source selected by TRGSEL is internal (channel pin input capture). #1 TRGSEL Trigger Select 24 4 read-write 0001 Channel 0 pin input capture #0001 0010 Channel 1 pin input capture #0010 0011 Channel 0 or Channel 1 pin input capture #0011 0100 Channel 2 pin input capture #0100 0101 Channel 0 or Channel 2 pin input capture #0101 0110 Channel 1 or Channel 2 pin input capture #0110 0111 Channel 0 or Channel 1 or Channel 2 pin input capture #0111 1000 Channel 3 pin input capture #1000 1001 Channel 0 or Channel 3 pin input capture #1001 1010 Channel 1 or Channel 3 pin input capture #1010 1011 Channel 0 or Channel 1 or Channel 3 pin input capture #1011 1100 Channel 2 or Channel 3 pin input capture #1100 1101 Channel 0 or Channel 2 or Channel 3 pin input capture #1101 1110 Channel 1 or Channel 2 or Channel 3 pin input capture #1110 1111 Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture #1111 TPM1 Timer/PWM Module TPM TPM1_ 0x40039000 0 0x88 registers TPM1 18 SC Status and Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CMOD Clock Mode Selection 3 2 read-write 00 TPM counter is disabled #00 01 TPM counter increments on every TPM counter clock #01 10 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock #10 CPWMS Center-Aligned PWM Select 5 1 read-write 0 TPM counter operates in up counting mode. #0 1 TPM counter operates in up-down counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling or DMA request. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 DMA DMA Enable 8 1 read-write 0 Disables DMA transfers. #0 1 Enables DMA transfers. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter value 0 16 read-write MOD Modulo 0x8 32 read-write 0xFFFF 0xFFFFFFFF MOD Modulo value 0 16 read-write 2 0x8 0,1 C%sSC Channel (n) Status and Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 2 0x8 0,1 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write STATUS Capture and Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 TOF Timer Overflow Flag 8 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 COMBINE Combine Channel Register 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels 0 and 1 0 1 read-write 0 Channels 0 and 1 are independent. #0 1 Channels 0 and 1 are combined. #1 COMSWAP0 Combine Channel 0 and 1 Swap 1 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 COMBINE1 Combine Channels 2 and 3 8 1 read-write 0 Channels 2 and 3 are independent. #0 1 Channels 2 and 3 are combined. #1 COMSWAP1 Combine Channels 2 and 3 Swap 9 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 POL Channel Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FILTER Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Filter Value 0 4 read-write CH1FVAL Channel 1 Filter Value 4 4 read-write CH2FVAL Channel 2 Filter Value 8 4 read-write CH3FVAL Channel 3 Filter Value 12 4 read-write QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Enables the quadrature decoder mode 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 TOFDIR Indicates if the TOF bit was set on the top or the bottom of counting. 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). #1 QUADIR Counter Direction in Quadrature Decode Mode 2 1 read-only 0 Counter direction is decreasing (counter decrement). #0 1 Counter direction is increasing (counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase encoding mode. #0 1 Count and direction encoding mode. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF DOZEEN Doze Enable 5 1 read-write 0 Internal TPM counter continues in Doze mode. #0 1 Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. #1 DBGMODE Debug Mode 6 2 read-write 00 TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. #00 11 TPM counter continues in debug mode. #11 GTBSYNC Global Time Base Synchronization 8 1 read-write 0 Global timebase synchronization disabled. #0 1 Global timebase synchronization enabled. #1 GTBEEN Global time base enable 9 1 read-write 0 All channels use the internally generated TPM counter as their timebase #0 1 All channels use an externally generated global timebase as their timebase #1 CSOT Counter Start on Trigger 16 1 read-write 0 TPM counter starts to increment immediately, once it is enabled. #0 1 TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. #1 CSOO Counter Stop On Overflow 17 1 read-write 0 TPM counter continues incrementing or decrementing after overflow #0 1 TPM counter stops incrementing or decrementing after overflow. #1 CROT Counter Reload On Trigger 18 1 read-write 0 Counter is not reloaded due to a rising edge on the selected input trigger #0 1 Counter is reloaded when a rising edge is detected on the selected input trigger #1 CPOT Counter Pause On Trigger 19 1 read-write TRGPOL Trigger Polarity 22 1 read-write 0 Trigger is active high. #0 1 Trigger is active low. #1 TRGSRC Trigger Source 23 1 read-write 0 Trigger source selected by TRGSEL is external. #0 1 Trigger source selected by TRGSEL is internal (channel pin input capture). #1 TRGSEL Trigger Select 24 4 read-write 0001 Channel 0 pin input capture #0001 0010 Channel 1 pin input capture #0010 0011 Channel 0 or Channel 1 pin input capture #0011 0100 Channel 2 pin input capture #0100 0101 Channel 0 or Channel 2 pin input capture #0101 0110 Channel 1 or Channel 2 pin input capture #0110 0111 Channel 0 or Channel 1 or Channel 2 pin input capture #0111 1000 Channel 3 pin input capture #1000 1001 Channel 0 or Channel 3 pin input capture #1001 1010 Channel 1 or Channel 3 pin input capture #1010 1011 Channel 0 or Channel 1 or Channel 3 pin input capture #1011 1100 Channel 2 or Channel 3 pin input capture #1100 1101 Channel 0 or Channel 2 or Channel 3 pin input capture #1101 1110 Channel 1 or Channel 2 or Channel 3 pin input capture #1110 1111 Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture #1111 TPM2 Timer/PWM Module TPM TPM2_ 0x4003A000 0 0x88 registers TPM2 19 SC Status and Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CMOD Clock Mode Selection 3 2 read-write 00 TPM counter is disabled #00 01 TPM counter increments on every TPM counter clock #01 10 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock #10 CPWMS Center-Aligned PWM Select 5 1 read-write 0 TPM counter operates in up counting mode. #0 1 TPM counter operates in up-down counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling or DMA request. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 DMA DMA Enable 8 1 read-write 0 Disables DMA transfers. #0 1 Enables DMA transfers. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter value 0 16 read-write MOD Modulo 0x8 32 read-write 0xFFFF 0xFFFFFFFF MOD Modulo value 0 16 read-write 2 0x8 0,1 C%sSC Channel (n) Status and Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 2 0x8 0,1 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write STATUS Capture and Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 TOF Timer Overflow Flag 8 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 COMBINE Combine Channel Register 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels 0 and 1 0 1 read-write 0 Channels 0 and 1 are independent. #0 1 Channels 0 and 1 are combined. #1 COMSWAP0 Combine Channel 0 and 1 Swap 1 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 COMBINE1 Combine Channels 2 and 3 8 1 read-write 0 Channels 2 and 3 are independent. #0 1 Channels 2 and 3 are combined. #1 COMSWAP1 Combine Channels 2 and 3 Swap 9 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 POL Channel Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FILTER Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Filter Value 0 4 read-write CH1FVAL Channel 1 Filter Value 4 4 read-write CH2FVAL Channel 2 Filter Value 8 4 read-write CH3FVAL Channel 3 Filter Value 12 4 read-write QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Enables the quadrature decoder mode 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 TOFDIR Indicates if the TOF bit was set on the top or the bottom of counting. 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). #1 QUADIR Counter Direction in Quadrature Decode Mode 2 1 read-only 0 Counter direction is decreasing (counter decrement). #0 1 Counter direction is increasing (counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase encoding mode. #0 1 Count and direction encoding mode. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF DOZEEN Doze Enable 5 1 read-write 0 Internal TPM counter continues in Doze mode. #0 1 Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. #1 DBGMODE Debug Mode 6 2 read-write 00 TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. #00 11 TPM counter continues in debug mode. #11 GTBSYNC Global Time Base Synchronization 8 1 read-write 0 Global timebase synchronization disabled. #0 1 Global timebase synchronization enabled. #1 GTBEEN Global time base enable 9 1 read-write 0 All channels use the internally generated TPM counter as their timebase #0 1 All channels use an externally generated global timebase as their timebase #1 CSOT Counter Start on Trigger 16 1 read-write 0 TPM counter starts to increment immediately, once it is enabled. #0 1 TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. #1 CSOO Counter Stop On Overflow 17 1 read-write 0 TPM counter continues incrementing or decrementing after overflow #0 1 TPM counter stops incrementing or decrementing after overflow. #1 CROT Counter Reload On Trigger 18 1 read-write 0 Counter is not reloaded due to a rising edge on the selected input trigger #0 1 Counter is reloaded when a rising edge is detected on the selected input trigger #1 CPOT Counter Pause On Trigger 19 1 read-write TRGPOL Trigger Polarity 22 1 read-write 0 Trigger is active high. #0 1 Trigger is active low. #1 TRGSRC Trigger Source 23 1 read-write 0 Trigger source selected by TRGSEL is external. #0 1 Trigger source selected by TRGSEL is internal (channel pin input capture). #1 TRGSEL Trigger Select 24 4 read-write 0001 Channel 0 pin input capture #0001 0010 Channel 1 pin input capture #0010 0011 Channel 0 or Channel 1 pin input capture #0011 0100 Channel 2 pin input capture #0100 0101 Channel 0 or Channel 2 pin input capture #0101 0110 Channel 1 or Channel 2 pin input capture #0110 0111 Channel 0 or Channel 1 or Channel 2 pin input capture #0111 1000 Channel 3 pin input capture #1000 1001 Channel 0 or Channel 3 pin input capture #1001 1010 Channel 1 or Channel 3 pin input capture #1010 1011 Channel 0 or Channel 1 or Channel 3 pin input capture #1011 1100 Channel 2 or Channel 3 pin input capture #1100 1101 Channel 0 or Channel 2 or Channel 3 pin input capture #1101 1110 Channel 1 or Channel 2 or Channel 3 pin input capture #1110 1111 Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture #1111 ADC0 Analog-to-Digital Converter ADC0_ 0x4003B000 0 0x70 registers ADC0 15 2 0x4 A,B SC1%s ADC Status and Control Registers 1 0 32 read-write 0x1F 0xFFFFFFFF ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11010 When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11101 When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. #11101 11110 When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. #11110 11111 Module is disabled. #11111 DIFF Differential Mode Enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 AIEN Interrupt Enable 6 1 read-write 0 Conversion complete interrupt is disabled. #0 1 Conversion complete interrupt is enabled. #1 COCO Conversion Complete Flag 7 1 read-only 0 Conversion is not completed. #0 1 Conversion is completed. #1 CFG1 ADC Configuration Register 1 0x8 32 read-write 0 0xFFFFFFFF ADICLK Input Clock Select 0 2 read-write 00 Bus clock #00 01 Bus clock divided by 2(BUSCLK/2) #01 10 Alternate clock (ALTCLK) #10 11 Asynchronous clock (ADACK) #11 MODE Conversion mode selection 2 2 read-write 00 When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. #00 01 When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output. #01 10 When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output #10 11 When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output #11 ADLSMP Sample Time Configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 ADIV Clock Divide Select 5 2 read-write 00 The divide ratio is 1 and the clock rate is input clock. #00 01 The divide ratio is 2 and the clock rate is (input clock)/2. #01 10 The divide ratio is 4 and the clock rate is (input clock)/4. #10 11 The divide ratio is 8 and the clock rate is (input clock)/8. #11 ADLPC Low-Power Configuration 7 1 read-write 0 Normal power configuration. #0 1 Low-power configuration. The power is reduced at the expense of maximum clock speed. #1 CFG2 ADC Configuration Register 2 0xC 32 read-write 0 0xFFFFFFFF ADLSTS Long Sample Time Select 0 2 read-write 00 Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. #00 01 12 extra ADCK cycles; 16 ADCK cycles total sample time. #01 10 6 extra ADCK cycles; 10 ADCK cycles total sample time. #10 11 2 extra ADCK cycles; 6 ADCK cycles total sample time. #11 ADHSC High-Speed Configuration 2 1 read-write 0 Normal conversion sequence selected. #0 1 High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. #1 ADACKEN Asynchronous Clock Output Enable 3 1 read-write 0 Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. #0 1 Asynchronous clock and clock output is enabled regardless of the state of the ADC. #1 MUXSEL ADC Mux Select 4 1 read-write 0 ADxxa channels are selected. #0 1 ADxxb channels are selected. #1 2 0x4 A,B R%s ADC Data Result Register 0x10 32 read-only 0 0xFFFFFFFF D Data result 0 16 read-only 2 0x4 1,2 CV%s Compare Value Registers 0x18 32 read-write 0 0xFFFFFFFF CV Compare Value. 0 16 read-write SC2 Status and Control Register 2 0x20 32 read-write 0 0xFFFFFFFF REFSEL Voltage Reference Selection 0 2 read-write 00 Default voltage reference pin pair, that is, external pins VREFH and VREFL #00 01 Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU #01 11 Reserved - Selects default voltage reference (V REFH and V REFL ) pin pair. #11 DMAEN DMA Enable 2 1 read-write 0 DMA is disabled. #0 1 DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted. #1 ACREN Compare Function Range Enable 3 1 read-write 0 Range function disabled. Only CV1 is compared. #0 1 Range function enabled. Both CV1 and CV2 are compared. #1 ACFGT Compare Function Greater Than Enable 4 1 read-write 0 Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2. #0 1 Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2. #1 ACFE Compare Function Enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ADTRG Conversion Trigger Select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 ADACT Conversion Active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 SC3 Status and Control Register 3 0x24 32 read-write 0 0xFFFFFFFF AVGS Hardware Average Select 0 2 read-write 00 4 samples averaged. #00 01 8 samples averaged. #01 10 16 samples averaged. #10 11 32 samples averaged. #11 AVGE Hardware Average Enable 2 1 read-write 0 Hardware average function disabled. #0 1 Hardware average function enabled. #1 ADCO Continuous Conversion Enable 3 1 read-write 0 One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. #0 1 Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. #1 CALF Calibration Failed Flag 6 1 read-write 0 Calibration completed normally. #0 1 Calibration failed. ADC accuracy specifications are not guaranteed. #1 CAL Calibration 7 1 read-write OFS ADC Offset Correction Register 0x28 32 read-write 0x4 0xFFFFFFFF OFS Offset Error Correction Value 0 16 read-write PG ADC Plus-Side Gain Register 0x2C 32 read-write 0x8200 0xFFFFFFFF PG Plus-Side Gain 0 16 read-write MG ADC Minus-Side Gain Register 0x30 32 read-write 0x8200 0xFFFFFFFF MG Minus-Side Gain 0 16 read-write CLPD ADC Plus-Side General Calibration Value Register 0x34 32 read-write 0xA 0xFFFFFFFF CLPD Calibration Value 0 6 read-write CLPS ADC Plus-Side General Calibration Value Register 0x38 32 read-write 0x20 0xFFFFFFFF CLPS Calibration Value 0 6 read-write CLP4 ADC Plus-Side General Calibration Value Register 0x3C 32 read-write 0x200 0xFFFFFFFF CLP4 Calibration Value 0 10 read-write CLP3 ADC Plus-Side General Calibration Value Register 0x40 32 read-write 0x100 0xFFFFFFFF CLP3 Calibration Value 0 9 read-write CLP2 ADC Plus-Side General Calibration Value Register 0x44 32 read-write 0x80 0xFFFFFFFF CLP2 Calibration Value 0 8 read-write CLP1 ADC Plus-Side General Calibration Value Register 0x48 32 read-write 0x40 0xFFFFFFFF CLP1 Calibration Value 0 7 read-write CLP0 ADC Plus-Side General Calibration Value Register 0x4C 32 read-write 0x20 0xFFFFFFFF CLP0 Calibration Value 0 6 read-write CLMD ADC Minus-Side General Calibration Value Register 0x54 32 read-write 0xA 0xFFFFFFFF CLMD Calibration Value 0 6 read-write CLMS ADC Minus-Side General Calibration Value Register 0x58 32 read-write 0x20 0xFFFFFFFF CLMS Calibration Value 0 6 read-write CLM4 ADC Minus-Side General Calibration Value Register 0x5C 32 read-write 0x200 0xFFFFFFFF CLM4 Calibration Value 0 10 read-write CLM3 ADC Minus-Side General Calibration Value Register 0x60 32 read-write 0x100 0xFFFFFFFF CLM3 Calibration Value 0 9 read-write CLM2 ADC Minus-Side General Calibration Value Register 0x64 32 read-write 0x80 0xFFFFFFFF CLM2 Calibration Value 0 8 read-write CLM1 ADC Minus-Side General Calibration Value Register 0x68 32 read-write 0x40 0xFFFFFFFF CLM1 Calibration Value 0 7 read-write CLM0 ADC Minus-Side General Calibration Value Register 0x6C 32 read-write 0x20 0xFFFFFFFF CLM0 Calibration Value 0 6 read-write RTC Secure Real Time Clock RTC_ 0x4003D000 0 0x20 registers RTC 20 RTC_Seconds 21 TSR RTC Time Seconds Register 0 32 read-write 0 0xFFFFFFFF TSR Time Seconds Register 0 32 read-write TPR RTC Time Prescaler Register 0x4 32 read-write 0 0xFFFFFFFF TPR Time Prescaler Register 0 16 read-write TAR RTC Time Alarm Register 0x8 32 read-write 0 0xFFFFFFFF TAR Time Alarm Register 0 32 read-write TCR RTC Time Compensation Register 0xC 32 read-write 0 0xFFFFFFFF TCR Time Compensation Register 0 8 read-write 10000000 Time Prescaler Register overflows every 32896 clock cycles. #10000000 11111111 Time Prescaler Register overflows every 32769 clock cycles. #11111111 0 Time Prescaler Register overflows every 32768 clock cycles. #0 1 Time Prescaler Register overflows every 32767 clock cycles. #1 1111111 Time Prescaler Register overflows every 32641 clock cycles. #1111111 CIR Compensation Interval Register 8 8 read-write TCV Time Compensation Value 16 8 read-only CIC Compensation Interval Counter 24 8 read-only CR RTC Control Register 0x10 32 read-write 0 0xFFFFFFFF SWR Software Reset 0 1 read-write 0 No effect. #0 1 Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it. #1 WPE Wakeup Pin Enable 1 1 read-write 0 Wakeup pin is disabled. #0 1 Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on. #1 SUP Supervisor Access 2 1 read-write 0 Non-supervisor mode write accesses are not supported and generate a bus error. #0 1 Non-supervisor mode write accesses are supported. #1 UM Update Mode 3 1 read-write 0 Registers cannot be written when locked. #0 1 Registers can be written when locked under limited conditions. #1 WPS Wakeup Pin Select 4 1 read-write 0 Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on. #0 1 Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals. #1 OSCE Oscillator Enable 8 1 read-write 0 32.768 kHz oscillator is disabled. #0 1 32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize. #1 CLKO Clock Output 9 1 read-write 0 The 32 kHz clock is output to other peripherals. #0 1 The 32 kHz clock is not output to other peripherals. #1 SC16P Oscillator 16pF Load Configure 10 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC8P Oscillator 8pF Load Configure 11 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC4P Oscillator 4pF Load Configure 12 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC2P Oscillator 2pF Load Configure 13 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 OTE Oscillator Test Enable 14 1 read-write 0 Disable oscillator test mode. #0 1 Enable oscillator test mode. #1 SR RTC Status Register 0x14 32 read-write 0x1 0xFFFFFFFF TIF Time Invalid Flag 0 1 read-only 0 Time is valid. #0 1 Time is invalid and time counter is read as zero. #1 TOF Time Overflow Flag 1 1 read-only 0 Time overflow has not occurred. #0 1 Time overflow has occurred and time counter is read as zero. #1 TAF Time Alarm Flag 2 1 read-only 0 Time alarm has not occurred. #0 1 Time alarm has occurred. #1 TCE Time Counter Enable 4 1 read-write 0 Time counter is disabled. #0 1 Time counter is enabled. #1 LR RTC Lock Register 0x18 32 read-write 0xFF 0xFFFFFFFF TCL Time Compensation Lock 3 1 read-write 0 Time Compensation Register is locked and writes are ignored. #0 1 Time Compensation Register is not locked and writes complete as normal. #1 CRL Control Register Lock 4 1 read-write 0 Control Register is locked and writes are ignored. #0 1 Control Register is not locked and writes complete as normal. #1 SRL Status Register Lock 5 1 read-write 0 Status Register is locked and writes are ignored. #0 1 Status Register is not locked and writes complete as normal. #1 LRL Lock Register Lock 6 1 read-write 0 Lock Register is locked and writes are ignored. #0 1 Lock Register is not locked and writes complete as normal. #1 IER RTC Interrupt Enable Register 0x1C 32 read-write 0x7 0xFFFFFFFF TIIE Time Invalid Interrupt Enable 0 1 read-write 0 Time invalid flag does not generate an interrupt. #0 1 Time invalid flag does generate an interrupt. #1 TOIE Time Overflow Interrupt Enable 1 1 read-write 0 Time overflow flag does not generate an interrupt. #0 1 Time overflow flag does generate an interrupt. #1 TAIE Time Alarm Interrupt Enable 2 1 read-write 0 Time alarm flag does not generate an interrupt. #0 1 Time alarm flag does generate an interrupt. #1 TSIE Time Seconds Interrupt Enable 4 1 read-write 0 Seconds interrupt is disabled. #0 1 Seconds interrupt is enabled. #1 WPON Wakeup Pin On 7 1 read-write 0 No effect. #0 1 If the wakeup pin is enabled, then the wakeup pin will assert. #1 DAC0 12-Bit Digital-to-Analog Converter DAC0_ 0x4003F000 0 0x24 registers DAC0 25 2 0x2 0,1 DAT%sL DAC Data Low Register 0 8 read-write 0 0xFF DATA0 DATA0 0 8 read-write 2 0x2 0,1 DAT%sH DAC Data High Register 0x1 8 read-write 0 0xFF DATA1 DATA1 0 4 read-write SR DAC Status Register 0x20 8 read-write 0x2 0xFF DACBFRPBF DAC Buffer Read Pointer Bottom Position Flag 0 1 read-write 0 The DAC buffer read pointer is not equal to C2[DACBFUP]. #0 1 The DAC buffer read pointer is equal to C2[DACBFUP]. #1 DACBFRPTF DAC Buffer Read Pointer Top Position Flag 1 1 read-write 0 The DAC buffer read pointer is not zero. #0 1 The DAC buffer read pointer is zero. #1 C0 DAC Control Register 0x21 8 read-write 0 0xFF DACBBIEN DAC Buffer Read Pointer Bottom Flag Interrupt Enable 0 1 read-write 0 The DAC buffer read pointer bottom flag interrupt is disabled. #0 1 The DAC buffer read pointer bottom flag interrupt is enabled. #1 DACBTIEN DAC Buffer Read Pointer Top Flag Interrupt Enable 1 1 read-write 0 The DAC buffer read pointer top flag interrupt is disabled. #0 1 The DAC buffer read pointer top flag interrupt is enabled. #1 LPEN DAC Low Power Control 3 1 read-write 0 High-Power mode #0 1 Low-Power mode #1 DACSWTRG DAC Software Trigger 4 1 write-only 0 The DAC soft trigger is not valid. #0 1 The DAC soft trigger is valid. #1 DACTRGSEL DAC Trigger Select 5 1 read-write 0 The DAC hardware trigger is selected. #0 1 The DAC software trigger is selected. #1 DACRFS DAC Reference Select 6 1 read-write 0 The DAC selects DACREF_1 as the reference voltage. #0 1 The DAC selects DACREF_2 as the reference voltage. #1 DACEN DAC Enable 7 1 read-write 0 The DAC system is disabled. #0 1 The DAC system is enabled. #1 C1 DAC Control Register 1 0x22 8 read-write 0 0xFF DACBFEN DAC Buffer Enable 0 1 read-write 0 Buffer read pointer is disabled. The converted data is always the first word of the buffer. #0 1 Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. #1 DACBFMD DAC Buffer Work Mode Select 2 1 read-write 0 Normal mode #0 1 One-Time Scan mode #1 DMAEN DMA Enable Select 7 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time. #1 C2 DAC Control Register 2 0x23 8 read-write 0x1 0xFF DACBFUP DAC Buffer Upper Limit 0 1 read-write DACBFRP DAC Buffer Read Pointer 4 1 read-write LPTMR0 Low Power Timer LPTMR0_ 0x40040000 0 0x10 registers LPTMR0 28 CSR Low Power Timer Control Status Register 0 32 read-write 0 0xFFFFFFFF TEN Timer Enable 0 1 read-write 0 LPTMR is disabled and internal logic is reset. #0 1 LPTMR is enabled. #1 TMS Timer Mode Select 1 1 read-write 0 Time Counter mode. #0 1 Pulse Counter mode. #1 TFC Timer Free-Running Counter 2 1 read-write 0 CNR is reset whenever TCF is set. #0 1 CNR is reset on overflow. #1 TPP Timer Pin Polarity 3 1 read-write 0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. #0 1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. #1 TPS Timer Pin Select 4 2 read-write 00 Pulse counter input 0 is selected. #00 01 Pulse counter input 1 is selected. #01 10 Pulse counter input 2 is selected. #10 11 Pulse counter input 3 is selected. #11 TIE Timer Interrupt Enable 6 1 read-write 0 Timer interrupt disabled. #0 1 Timer interrupt enabled. #1 TCF Timer Compare Flag 7 1 read-write 0 The value of CNR is not equal to CMR and increments. #0 1 The value of CNR is equal to CMR and increments. #1 PSR Low Power Timer Prescale Register 0x4 32 read-write 0 0xFFFFFFFF PCS Prescaler Clock Select 0 2 read-write 00 Prescaler/glitch filter clock 0 selected. #00 01 Prescaler/glitch filter clock 1 selected. #01 10 Prescaler/glitch filter clock 2 selected. #10 11 Prescaler/glitch filter clock 3 selected. #11 PBYP Prescaler Bypass 2 1 read-write 0 Prescaler/glitch filter is enabled. #0 1 Prescaler/glitch filter is bypassed. #1 PRESCALE Prescale Value 3 4 read-write 0000 Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. #0000 0001 Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. #0001 0010 Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. #0010 0011 Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. #0011 0100 Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. #0100 0101 Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. #0101 0110 Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. #0110 0111 Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. #0111 1000 Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. #1000 1001 Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. #1001 1010 Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. #1010 1011 Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. #1011 1100 Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. #1100 1101 Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. #1101 1110 Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. #1110 1111 Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. #1111 CMR Low Power Timer Compare Register 0x8 32 read-write 0 0xFFFFFFFF COMPARE Compare Value 0 16 read-write CNR Low Power Timer Counter Register 0xC 32 read-write 0 0xFFFFFFFF COUNTER Counter Value 0 16 read-write TSI0 Touch sense input TSI0_ 0x40045000 0 0xC registers TSI0 11 GENCS TSI General Control and Status Register 0 32 read-write 0 0xFFFFFFFF CURSW CURSW 1 1 read-write 0 The current source pair are not swapped. #0 1 The current source pair are swapped. #1 EOSF End of Scan Flag 2 1 read-write 0 Scan not complete. #0 1 Scan complete. #1 SCNIP Scan In Progress Status 3 1 read-only 0 No scan in progress. #0 1 Scan in progress. #1 STM Scan Trigger Mode 4 1 read-write 0 Software trigger scan. #0 1 Hardware trigger scan. #1 STPE TSI STOP Enable 5 1 read-write 0 TSI is disabled when MCU goes into low power mode. #0 1 Allows TSI to continue running in all low power modes. #1 TSIIEN Touch Sensing Input Interrupt Enable 6 1 read-write 0 TSI interrupt is disabled. #0 1 TSI interrupt is enabled. #1 TSIEN Touch Sensing Input Module Enable 7 1 read-write 0 TSI module disabled. #0 1 TSI module enabled. #1 NSCN NSCN 8 5 read-write 00000 Once per electrode #00000 00001 Twice per electrode #00001 00010 3 times per electrode #00010 00011 4 times per electrode #00011 00100 5 times per electrode #00100 00101 6 times per electrode #00101 00110 7 times per electrode #00110 00111 8 times per electrode #00111 01000 9 times per electrode #01000 01001 10 times per electrode #01001 01010 11 times per electrode #01010 01011 12 times per electrode #01011 01100 13 times per electrode #01100 01101 14 times per electrode #01101 01110 15 times per electrode #01110 01111 16 times per electrode #01111 10000 17 times per electrode #10000 10001 18 times per electrode #10001 10010 19 times per electrode #10010 10011 20 times per electrode #10011 10100 21 times per electrode #10100 10101 22 times per electrode #10101 10110 23 times per electrode #10110 10111 24 times per electrode #10111 11000 25 times per electrode #11000 11001 26 times per electrode #11001 11010 27 times per electrode #11010 11011 28 times per electrode #11011 11100 29 times per electrode #11100 11101 30 times per electrode #11101 11110 31 times per electrode #11110 11111 32 times per electrode #11111 PS PS 13 3 read-write 000 Electrode Oscillator Frequency divided by 1 #000 001 Electrode Oscillator Frequency divided by 2 #001 010 Electrode Oscillator Frequency divided by 4 #010 011 Electrode Oscillator Frequency divided by 8 #011 100 Electrode Oscillator Frequency divided by 16 #100 101 Electrode Oscillator Frequency divided by 32 #101 110 Electrode Oscillator Frequency divided by 64 #110 111 Electrode Oscillator Frequency divided by 128 #111 EXTCHRG EXTCHRG 16 3 read-write 000 500 nA. #000 001 1 uA. #001 010 2 uA. #010 011 4 uA. #011 100 8 uA. #100 101 16 uA. #101 110 32 uA. #110 111 64 uA. #111 DVOLT DVOLT 19 2 read-write 00 DV = 1.026 V; VP = 1.328 V; Vm = 0.302 V. #00 01 DV = 0.592 V; VP = 1.111 V; Vm = 0.519 V. #01 10 DV = 0.342 V; VP = 0.986 V; Vm = 0.644 V. #10 11 DV = 0.197 V; VP = 0.914 V; Vm = 0.716 V. #11 REFCHRG REFCHRG 21 3 read-write 000 500 nA. #000 001 1 uA. #001 010 2 uA. #010 011 4 uA. #011 100 8 uA. #100 101 16 uA. #101 110 32 uA. #110 111 64 uA. #111 MODE TSI analog modes setup and status bits. 24 4 read-write 0000 Set TSI in capacitive sensing(non-noise detection) mode. #0000 0100 Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is disabled. #0100 1000 Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is enabled to work in higher frequencies operations. #1000 1100 Set TSI analog to work in automatic noise detection mode. #1100 ESOR End-of-scan or Out-of-Range Interrupt Selection 28 1 read-write 0 Out-of-range interrupt is allowed. #0 1 End-of-scan interrupt is allowed. #1 OUTRGF Out of Range Flag. 31 1 read-write DATA TSI DATA Register 0x4 32 read-write 0 0xFFFFFFFF TSICNT TSI Conversion Counter Value 0 16 read-only SWTS Software Trigger Start 22 1 write-only 0 No effect. #0 1 Start a scan to determine which channel is specified by TSI_DATA[TSICH]. #1 DMAEN DMA Transfer Enabled 23 1 read-write 0 Interrupt is selected when the interrupt enable bit is set and the corresponding TSI events assert. #0 1 DMA transfer request is selected when the interrupt enable bit is set and the corresponding TSI events assert. #1 TSICH TSICH 28 4 read-write 0000 Channel 0. #0000 0001 Channel 1. #0001 0010 Channel 2. #0010 0011 Channel 3. #0011 0100 Channel 4. #0100 0101 Channel 5. #0101 0110 Channel 6. #0110 0111 Channel 7. #0111 1000 Channel 8. #1000 1001 Channel 9. #1001 1010 Channel 10. #1010 1011 Channel 11. #1011 1100 Channel 12. #1100 1101 Channel 13. #1101 1110 Channel 14. #1110 1111 Channel 15. #1111 TSHD TSI Threshold Register 0x8 32 read-write 0 0xFFFFFFFF THRESL TSI Wakeup Channel Low-threshold 0 16 read-write THRESH TSI Wakeup Channel High-threshold 16 16 read-write SIM System Integration Module SIM_ 0x40047000 0 0x1108 registers SOPT1 System Options Register 1 0 32 read-write 0 0xFFFFFFFF OSC32KOUT 32K oscillator clock output 16 2 read-write 00 ERCLK32K is not output. #00 01 ERCLK32K is output on PTB3. #01 OSC32KSEL 32K Oscillator Clock Select 18 2 read-write 00 32kHz oscillator (OSC32KCLK) #00 10 RTC_CLKIN #10 11 LPO 1kHz #11 SIM_MISCTL This bit control the function of RF_ACTIVE on PTC1/PTC19 ALT7 20 1 read-write 0 Radio active status is output from RF_ACTIVE #0 1 MCU low power status is output from RF_ACTIVE. Output logic is high when MCU is in STOP, VLPS, LLSx or VLLSx modes and low when not. #1 SOPT2 System Options Register 2 0x1004 32 read-write 0 0xFFFFFFFF CLKOUTSEL CLKOUT select 5 3 read-write 000 OSCERCLK DIV2 #000 001 OSCERCLK DIV4 #001 010 Bus clock #010 011 LPO clock 1 kHz #011 100 MCGIRCLK #100 101 OSCERCLK DIV8 #101 110 OSCERCLK #110 TPMSRC TPM Clock Source Select 24 2 read-write 00 Clock disabled #00 01 MCGFLLCLK clock #01 10 OSCERCLK clock #10 11 MCGIRCLK clock #11 LPUART0SRC LPUART0 Clock Source Select 26 2 read-write 00 Clock disabled #00 01 MCGFLLCLK clock #01 10 OSCERCLK clock #10 11 MCGIRCLK clock #11 SOPT4 System Options Register 4 0x100C 32 read-write 0 0xFFFFFFFF TPM1CH0SRC TPM1 Channel 0 Input Capture Source Select 18 1 read-write 0 TPM1_CH0 signal #0 1 CMP0 output #1 TPM2CH0SRC TPM2 Channel 0 Input Capture Source Select 20 1 read-write 0 TPM2_CH0 signal #0 1 CMP0 output #1 TPM0CLKSEL TPM0 External Clock Pin Select 24 1 read-write 0 TPM0 external clock driven by TPM_CLKIN0 pin. #0 1 TPM0 external clock driven by TPM_CLKIN1 pin. #1 TPM1CLKSEL TPM1 External Clock Pin Select 25 1 read-write 0 TPM1 external clock driven by TPM_CLKIN0 pin. #0 1 TPM1 external clock driven by TPM_CLKIN1 pin. #1 TPM2CLKSEL TPM2 External Clock Pin Select 26 1 read-write 0 TPM2 external clock driven by TPM_CLKIN0 pin. #0 1 TPM2 external clock driven by TPM_CLKIN1 pin. #1 SOPT5 System Options Register 5 0x1010 32 read-write 0 0xFFFFFFFF LPUART0TXSRC LPUART0 Transmit Data Source Select 0 2 read-write 00 LPUART0_TX pin #00 01 LPUART0_TX pin modulated with TPM1 channel 0 output #01 10 LPUART0_TX pin modulated with TPM2 channel 0 output #10 LPUART0RXSRC LPUART0 Receive Data Source Select 2 1 read-write 0 LPUART_RX pin #0 1 CMP0 output #1 LPUART0ODE LPUART0 Open Drain Enable 16 1 read-write 0 Open drain is disabled on LPUART0. #0 1 Open drain is enabled on LPUART0. #1 SOPT7 System Options Register 7 0x1018 32 read-write 0 0xFFFFFFFF ADC0TRGSEL ADC0 Trigger Select 0 4 read-write 0000 External trigger pin input (EXTRG_IN) #0000 0001 CMP0 output #0001 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 1000 TPM0 overflow #1000 1001 TPM1 overflow #1001 1010 TPM2 overflow #1010 1100 RTC alarm #1100 1101 RTC seconds #1101 1110 LPTMR0 trigger #1110 1111 Radio TSM #1111 ADC0PRETRGSEL ADC0 Pretrigger Select 4 1 read-write 0 Pre-trigger ADHDWTSA is selected, thus ADC0 will use ADC0_SC1A configuration for the next ADC conversion and store the result in ADC0_RA register. #0 1 Pre-trigger ADHDWTSB is selected, thus ADC0 will use ADC0_SC1B configuration for the next ADC conversion and store the result in ADC0_RB register. #1 ADC0ALTTRGEN ADC0 Alternate Trigger Enable 7 1 read-write 0 ADC ADHWT trigger comes from TPM1 channel 0 and channel1. Prior to the assertion of TPM1 channel 0, a pre-trigger pulse will be sent to ADHWTSA to initiate an ADC acquisition using ADCx_SC1A configuration and store ADC conversion in ADCx_RA Register. Prior to the assertion of TPM1 channel 1 a pre-trigger pulse will be sent to ADHWTSB to initiate an ADC acquisition using ADCx_SC1Bconfiguration and store ADC conversion in ADCx_RB Register. #0 1 ADC ADHWT trigger comes from a peripheral event selected by ADC0TRGSEL bits.ADC0PRETRGSEL bit will select the optional ADHWTSA or ADHWTSB select lines for choosing the ADCx_SC1x config and ADCx_Rx result regsiter to store the ADC conversion. #1 SDID System Device Identification Register 0x1024 32 read-only 0x5F0000 0xFFFFFFFF PINID Pin count Identification 0 4 read-only 0010 32-pin #0010 0100 48-pin #0100 1011 CSP #1011 DIEID Device Die Number 7 5 read-only REVID Device Revision Number 12 4 read-only SRAMSIZE System SRAM Size 16 4 read-only SERIESID Kinetis Series ID 20 4 read-only 0101 KW family #0101 SUBFAMID Kinetis Sub-Family ID. 24 2 read-only 00 KWx0 Subfamily #00 01 KWx1 Subfamily #01 10 KWx2 Subfamily #10 11 KWx3 Subfamily #11 FAMID Kinetis family ID 28 4 read-only 0010 KW2x Family (802.15.4/ZigBee) #0010 0011 KW3x Family (BTLE) #0011 0100 KW4x Family (802.15.4/ZigBee, BTLE) #0100 SCGC4 System Clock Gating Control Register 4 0x1034 32 read-write 0xF0000030 0xFFFFFFFF CMT CMT Clock Gate Control 2 1 read-write 0 Clock disabled #0 1 Clock enabled #1 I2C0 I2C0 Clock Gate Control 6 1 read-write 0 Clock disabled #0 1 Clock enabled #1 I2C1 I2C1 Clock Gate Control 7 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CMP Comparator Clock Gate Control 19 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC5 System Clock Gating Control Register 5 0x1038 32 read-write 0x2000182 0xFFFFFFFF LPTMR Low Power Timer Access Control 0 1 read-write 0 Access disabled #0 1 Access enabled #1 TSI TSI Access Control 5 1 read-write 0 Access disabled #0 1 Access enabled #1 PORTA Port A Clock Gate Control 9 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTB Port B Clock Gate Control 10 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTC Port C Clock Gate Control 11 1 read-write 0 Clock disabled #0 1 Clock enabled #1 LPUART0 LPUART0 Clock Gate Control 20 1 read-write 0 Clock disabled #0 1 Clock enabled #1 LTC LTC Clock Gate Control 24 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RSIM RSIM Clock Gate Control 25 1 read-only DCDC DCDC Clock Gate Control 26 1 read-write 0 Clock disabled #0 1 Clock enabled #1 BTLL BTLL System Clock Gate Control 27 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PHYDIG PHY Digital Clock Gate Control 28 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ZigBee ZigBee Clock Gate Control 29 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC6 System Clock Gating Control Register 6 0x103C 32 read-write 0x1 0xFFFFFFFF FTF Flash Memory Clock Gate Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 DMAMUX DMA Mux Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TRNG TRNG Clock Gate Control 9 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SPI0 SPI0 Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SPI1 SPI1 Clock Gate Control 13 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PIT PIT Clock Gate Control 23 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TPM0 TPM0 Clock Gate Control 24 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TPM1 TPM1 Clock Gate Control 25 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TPM2 TPM2 Clock Gate Control 26 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ADC0 ADC0 Clock Gate Control 27 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RTC RTC Access Control 29 1 read-write 0 Access and interrupts disabled #0 1 Access and interrupts enabled #1 DAC0 DAC0 Clock Gate Control 31 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC7 System Clock Gating Control Register 7 0x1040 32 read-write 0x100 0xFFFFFFFF DMA DMA Clock Gate Control 8 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CLKDIV1 System Clock Divider Register 1 0x1044 32 read-write 0x10000 0xFFFFFFFF OUTDIV4 Clock 4 Output Divider value 16 3 read-write 000 Divide-by-1. #000 001 Divide-by-2. #001 010 Divide-by-3. #010 011 Divide-by-4. #011 100 Divide-by-5. #100 101 Divide-by-6. #101 110 Divide-by-7. #110 111 Divide-by-8. #111 OUTDIV1 Clock 1 Output Divider value 28 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 FCFG1 Flash Configuration Register 1 0x104C 32 read-write 0xF000000 0xFFFFFFFF FLASHDIS Flash Disable 0 1 read-write 0 Flash is enabled. #0 1 Flash is disabled. #1 FLASHDOZE Flash Doze 1 1 read-write 0 Flash remains enabled during Doze mode. #0 1 Flash is disabled for the duration of Doze mode. #1 PFSIZE Program Flash Size 24 4 read-only FCFG2 Flash Configuration Register 2 0x1050 32 read-only 0x7FFF0000 0xFFFFFFFF MAXADDR1 This field concatenated with leading zeros plus the value of the MAXADDR1 field indicates the first invalid address of the second program flash block (flash block 1) 16 7 read-only MAXADDR0 Max Address lock 24 7 read-only UIDMH Unique Identification Register Mid-High 0x1058 32 read-only 0 0xFFFFFFFF UID Unique Identification 0 16 read-only UIDML Unique Identification Register Mid Low 0x105C 32 read-only 0 0xFFFFFFFF UID Unique Identification 0 32 read-only UIDL Unique Identification Register Low 0x1060 32 read-only 0 0xFFFFFFFF UID Unique Identification 0 32 read-only COPC COP Control Register 0x1100 32 read-write 0xC 0xFFFFFFFF COPW COP Windowed Mode 0 1 read-write 0 Normal mode #0 1 Windowed mode #1 COPCLKS COP Clock Select 1 1 read-write 0 COP configured for short timeout #0 1 COP configured for long timeout #1 COPT COP Watchdog Timeout 2 2 read-write 00 COP disabled #00 01 COP timeout after 25 cycles for short timeout or 213 cycles for long timeout #01 10 COP timeout after 28 cycles for short timeout or 216 cycles for long timeout #10 11 COP timeout after 210 cycles for short timeout or 218 cycles for long timeout #11 COPSTPEN COP Stop Enable 4 1 read-write 0 COP is disabled and the counter is reset in Stop modes #0 1 COP is enabled in Stop modes #1 COPDBGEN COP Debug Enable 5 1 read-write 0 COP is disabled and the counter is reset in Debug mode #0 1 COP is enabled in Debug mode #1 COPCLKSEL COP Clock Select 6 2 read-write 00 LPO clock (1 kHz) #00 01 MCGIRCLK #01 10 OSCERCLK #10 11 Bus clock #11 SRVCOP Service COP 0x1104 32 write-only 0 0xFFFFFFFF SRVCOP Service COP Register 0 8 write-only PORTA Pin Control and Interrupts PORT PORTA_ 0x40049000 0 0xA4 registers PORTA 30 PCR0 Pin Control Register n 0 32 read-write 0x707 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR1 Pin Control Register n 0x4 32 read-write 0x706 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR2 Pin Control Register n 0x8 32 read-write 0x707 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR3 Pin Control Register n 0xC 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR4 Pin Control Register n 0x10 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR5 Pin Control Register n 0x14 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR6 Pin Control Register n 0x18 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR7 Pin Control Register n 0x1C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR8 Pin Control Register n 0x20 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR9 Pin Control Register n 0x24 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR10 Pin Control Register n 0x28 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR11 Pin Control Register n 0x2C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR12 Pin Control Register n 0x30 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR13 Pin Control Register n 0x34 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR14 Pin Control Register n 0x38 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR15 Pin Control Register n 0x3C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR16 Pin Control Register n 0x40 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR17 Pin Control Register n 0x44 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR18 Pin Control Register n 0x48 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR19 Pin Control Register n 0x4C 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR20 Pin Control Register n 0x50 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR21 Pin Control Register n 0x54 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR22 Pin Control Register n 0x58 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR23 Pin Control Register n 0x5C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR24 Pin Control Register n 0x60 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR25 Pin Control Register n 0x64 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR26 Pin Control Register n 0x68 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR27 Pin Control Register n 0x6C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR28 Pin Control Register n 0x70 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR29 Pin Control Register n 0x74 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR30 Pin Control Register n 0x78 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR31 Pin Control Register n 0x7C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PORTB Pin Control and Interrupts PORT PORTB_ 0x4004A000 0 0xA4 registers PORTB_PORTC 31 PCR0 Pin Control Register n 0 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR1 Pin Control Register n 0x4 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR2 Pin Control Register n 0x8 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR3 Pin Control Register n 0xC 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR4 Pin Control Register n 0x10 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR5 Pin Control Register n 0x14 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR6 Pin Control Register n 0x18 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR7 Pin Control Register n 0x1C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR8 Pin Control Register n 0x20 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR9 Pin Control Register n 0x24 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR10 Pin Control Register n 0x28 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR11 Pin Control Register n 0x2C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR12 Pin Control Register n 0x30 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR13 Pin Control Register n 0x34 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR14 Pin Control Register n 0x38 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR15 Pin Control Register n 0x3C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR16 Pin Control Register n 0x40 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR17 Pin Control Register n 0x44 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR18 Pin Control Register n 0x48 32 read-write 0x715 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR19 Pin Control Register n 0x4C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR20 Pin Control Register n 0x50 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR21 Pin Control Register n 0x54 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR22 Pin Control Register n 0x58 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR23 Pin Control Register n 0x5C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR24 Pin Control Register n 0x60 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR25 Pin Control Register n 0x64 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR26 Pin Control Register n 0x68 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR27 Pin Control Register n 0x6C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR28 Pin Control Register n 0x70 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR29 Pin Control Register n 0x74 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR30 Pin Control Register n 0x78 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR31 Pin Control Register n 0x7C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PORTC Pin Control and Interrupts PORT PORTC_ 0x4004B000 0 0xA4 registers PORTB_PORTC 31 PCR0 Pin Control Register n 0 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR1 Pin Control Register n 0x4 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR2 Pin Control Register n 0x8 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR3 Pin Control Register n 0xC 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR4 Pin Control Register n 0x10 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR5 Pin Control Register n 0x14 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR6 Pin Control Register n 0x18 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR7 Pin Control Register n 0x1C 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR8 Pin Control Register n 0x20 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR9 Pin Control Register n 0x24 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR10 Pin Control Register n 0x28 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR11 Pin Control Register n 0x2C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR12 Pin Control Register n 0x30 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR13 Pin Control Register n 0x34 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR14 Pin Control Register n 0x38 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR15 Pin Control Register n 0x3C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR16 Pin Control Register n 0x40 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR17 Pin Control Register n 0x44 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR18 Pin Control Register n 0x48 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR19 Pin Control Register n 0x4C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR20 Pin Control Register n 0x50 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR21 Pin Control Register n 0x54 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR22 Pin Control Register n 0x58 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR23 Pin Control Register n 0x5C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR24 Pin Control Register n 0x60 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR25 Pin Control Register n 0x64 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR26 Pin Control Register n 0x68 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR27 Pin Control Register n 0x6C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR28 Pin Control Register n 0x70 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR29 Pin Control Register n 0x74 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR30 Pin Control Register n 0x78 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR31 Pin Control Register n 0x7C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LPUART0 Universal Asynchronous Receiver/Transmitter LPUART0_ 0x40054000 0 0x18 registers LPUART0 12 BAUD LPUART Baud Rate Register 0 32 read-write 0xF000004 0xFFFFFFFF SBR Baud Rate Modulo Divisor. 0 13 read-write SBNS Stop Bit Number Select 13 1 read-write 0 One stop bit. #0 1 Two stop bits. #1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write 0 Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. #1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write 0 Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. #1 RESYNCDIS Resynchronization Disable 16 1 read-write 0 Resynchronization during received data word is supported #0 1 Resynchronization during received data word is disabled #1 BOTHEDGE Both Edge Sampling 17 1 read-write 0 Receiver samples input data using the rising edge of the baud rate clock. #0 1 Receiver samples input data using the rising and falling edge of the baud rate clock. #1 MATCFG Match Configuration 18 2 read-write 00 Address Match Wakeup #00 01 Idle Match Wakeup #01 10 Match On and Match Off #10 11 Enables RWU on Data Match and Match On/Off for transmitter CTS input #11 RDMAE Receiver Full DMA Enable 21 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 TDMAE Transmitter DMA Enable 23 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 OSR Oversampling Ratio 24 5 read-write M10 10-bit Mode select 29 1 read-write 0 Receiver and transmitter use 8-bit or 9-bit data characters. #0 1 Receiver and transmitter use 10-bit data characters. #1 MAEN2 Match Address Mode Enable 2 30 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA2]. #1 MAEN1 Match Address Mode Enable 1 31 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA1]. #1 STAT LPUART Status Register 0x4 32 read-write 0xC00000 0xFFFFFFFF MA2F Match 2 Flag 14 1 read-write 0 Received data is not equal to MA2 #0 1 Received data is equal to MA2 #1 MA1F Match 1 Flag 15 1 read-write 0 Received data is not equal to MA1 #0 1 Received data is equal to MA1 #1 PF Parity Error Flag 16 1 read-write 0 No parity error. #0 1 Parity error. #1 FE Framing Error Flag 17 1 read-write 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 NF Noise Flag 18 1 read-write 0 No noise detected. #0 1 Noise detected in the received character in LPUART_DATA. #1 OR Receiver Overrun Flag 19 1 read-write 0 No overrun. #0 1 Receive overrun (new LPUART data lost). #1 IDLE Idle Line Flag 20 1 read-write 0 No idle line detected. #0 1 Idle line was detected. #1 RDRF Receive Data Register Full Flag 21 1 read-only 0 Receive data buffer empty. #0 1 Receive data buffer full. #1 TC Transmission Complete Flag 22 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 23 1 read-only 0 Transmit data buffer full. #0 1 Transmit data buffer empty. #1 RAF Receiver Active Flag 24 1 read-only 0 LPUART receiver idle waiting for a start bit. #0 1 LPUART receiver active (LPUART_RX input not idle). #1 LBKDE LIN Break Detection Enable 25 1 read-write 0 Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1). #1 BRK13 Break Character Generation Length 26 1 read-write 0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1). #1 RWUID Receive Wake Up Idle Detect 27 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match. #1 RXINV Receive Data Inversion 28 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 MSBF MSB First 29 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. #1 RXEDGIF LPUART_RX Pin Active Edge Interrupt Flag 30 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 CTRL LPUART Control Register 0x8 32 read-write 0 0xFFFFFFFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Configures RWU for idle-line wakeup. #0 1 Configures RWU with address-mark wakeup. #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Receiver and transmitter use 8-bit data characters. #0 1 Receiver and transmitter use 9-bit data characters. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin. #0 1 Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input. #1 DOZEEN Doze Enable 6 1 read-write 0 LPUART is enabled in Doze mode. #0 1 LPUART is disabled in Doze mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - LPUART_RX and LPUART_TX use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). #1 IDLECFG Idle Configuration 8 3 read-write 000 1 idle character #000 001 2 idle characters #001 010 4 idle characters #010 011 8 idle characters #011 100 16 idle characters #100 101 32 idle characters #101 110 64 idle characters #110 111 128 idle characters #111 MA2IE Match 2 Interrupt Enable 14 1 read-write 0 MA2F interrupt disabled #0 1 MA2F interrupt enabled #1 MA1IE Match 1 Interrupt Enable 15 1 read-write 0 MA1F interrupt disabled #0 1 MA1F interrupt enabled #1 SBK Send Break 16 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 RWU Receiver Wakeup Control 17 1 read-write 0 Normal receiver operation. #0 1 LPUART receiver in standby waiting for wakeup condition. #1 RE Receiver Enable 18 1 read-write 0 Receiver disabled. #0 1 Receiver enabled. #1 TE Transmitter Enable 19 1 read-write 0 Transmitter disabled. #0 1 Transmitter enabled. #1 ILIE Idle Line Interrupt Enable 20 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 RIE Receiver Interrupt Enable 21 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TIE Transmit Interrupt Enable 23 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 PEIE Parity Error Interrupt Enable 24 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 FEIE Framing Error Interrupt Enable 25 1 read-write 0 FE interrupts disabled; use polling. #0 1 Hardware interrupt requested when FE is set. #1 NEIE Noise Error Interrupt Enable 26 1 read-write 0 NF interrupts disabled; use polling. #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 27 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 TXINV Transmit Data Inversion 28 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 TXDIR LPUART_TX Pin Direction in Single-Wire Mode 29 1 read-write 0 LPUART_TX pin is an input in single-wire mode. #0 1 LPUART_TX pin is an output in single-wire mode. #1 R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write DATA LPUART Data Register 0xC 32 read-write 0x1000 0xFFFFFFFF R0T0 Read receive data buffer 0 or write transmit data buffer 0. 0 1 read-write R1T1 Read receive data buffer 1 or write transmit data buffer 1. 1 1 read-write R2T2 Read receive data buffer 2 or write transmit data buffer 2. 2 1 read-write R3T3 Read receive data buffer 3 or write transmit data buffer 3. 3 1 read-write R4T4 Read receive data buffer 4 or write transmit data buffer 4. 4 1 read-write R5T5 Read receive data buffer 5 or write transmit data buffer 5. 5 1 read-write R6T6 Read receive data buffer 6 or write transmit data buffer 6. 6 1 read-write R7T7 Read receive data buffer 7 or write transmit data buffer 7. 7 1 read-write R8T8 Read receive data buffer 8 or write transmit data buffer 8. 8 1 read-write R9T9 Read receive data buffer 9 or write transmit data buffer 9. 9 1 read-write IDLINE Idle Line 11 1 read-only 0 Receiver was not idle before receiving this character. #0 1 Receiver was idle before receiving this character. #1 RXEMPT Receive Buffer Empty 12 1 read-only 0 Receive buffer contains valid data. #0 1 Receive buffer is empty, data returned on read is not valid. #1 FRETSC Frame Error / Transmit Special Character 13 1 read-write 0 The dataword was received without a frame error on read, transmit a normal character on write. #0 1 The dataword was received with a frame error, transmit an idle or break character on transmit. #1 PARITYE The current received dataword contained in DATA[R9:R0] was received with a parity error. 14 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 NOISY The current received dataword contained in DATA[R9:R0] was received with noise. 15 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 MATCH LPUART Match Address Register 0x10 32 read-write 0 0xFFFFFFFF MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x14 32 read-write 0 0xFFFFFFFF TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS assertion is configured by the RTSWATER field #1 TXCTSC Transmit CTS Configuration 4 1 read-write 0 CTS input is sampled at the start of each character. #0 1 CTS input is sampled when the transmitter is idle. #1 TXCTSSRC Transmit CTS Source 5 1 read-write 0 CTS input is the LPUART_CTS pin. #0 1 CTS input is the inverted Receiver Match result. #1 TNP Transmitter narrow pulse 16 2 read-write 00 1/OSR. #00 01 2/OSR. #01 10 3/OSR. #10 11 4/OSR. #11 IREN Infrared enable 18 1 read-write 0 IR disabled. #0 1 IR enabled. #1 LTC0 LTC 0x40058000 0 0x8FC registers LTC0 23 LTC_MD LTC Mode Register 0 32 read-write 0 0xFFFFFFFF ENC Encrypt/Decrypt. This bit selects encryption or decryption. 0 1 read-write 0 Decrypt. #0 1 Encrypt. #1 ICV_TEST ICV Checking / Test AES fault detection 1 1 read-write AS Algorithm State 2 2 read-write 00 Update #00 01 Initialize #01 10 Finalize #10 11 Initialize/Finalize #11 AAI Additional Algorithm information 4 9 read-write ALG Algorithm. This field specifies which algorithm is being selected. 16 8 read-write 00010000 AES #10000 LTC_KS LTC Key Size Register 0x8 32 read-write 0x10 0xFFFFFFFF KS Key Size. This is the size of a Key measured in bytes 0 5 read-write LTC_DS LTC Data Size Register 0x10 32 read-write 0 0xFFFFFFFF DS Data Size 0 12 read-write LTC_ICVS LTC ICV Size Register 0x18 32 read-write 0 0xFFFFFFFF ICVS ICV Size, in Bytes. 0 5 read-write LTC_COM LTC Command Register 0x30 32 read-write 0 0xFFFFFFFF ALL Reset All Internal Logic 0 1 write-only 0 Do Not Reset #0 1 Reset all CHAs in use by this CCB. #1 AES Reset AESA. Writing a 1 to this bit resets the AES Accelerator core engine. 1 1 write-only 0 Do Not Reset #0 1 Reset AES Accelerator #1 LTC_CTL LTC Control Register 0x34 32 read-write 0 0xFFFFFFFF IM Interrupt Mask. Once this bit is set, it can only be cleared by hard reset. 0 1 read-write 0 Interrupt not masked. #0 1 Interrupt masked #1 IFE Input FIFO DMA Enable. 8 1 read-write 0 DMA Request and Done signals disabled for the Input FIFO. #0 1 DMA Request and Done signals enabled for the Input FIFO. #1 IFR Input FIFO DMA Request Size 9 1 read-write 0 DMA request size is 1 entry. #0 1 DMA request size is 4 entries. #1 OFE Output FIFO DMA Enable. 12 1 read-write 0 DMA Request and Done signals disabled for the Output FIFO. #0 1 DMA Request and Done signals enabled for the Output FIFO. #1 OFR Output FIFO DMA Request Size 13 1 read-write 0 DMA request size is 1 entry. #0 1 DMA request size is 4 entries. #1 IFS Input FIFO Byte Swap. Byte swap all data that is written to the Input FIFO. 16 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 OFS Output FIFO Byte Swap. Byte swap all data that is read from the Onput FIFO. 17 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 KIS Key Register Input Byte Swap 20 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 KOS Key Register Output Byte Swap 21 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 CIS Context Register Input Byte Swap 22 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 COS Context Register Output Byte Swap 23 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 KAL Key Register Access Lock 31 1 read-write 0 Key Register is readable. #0 1 Key Register is not readable. #1 LTC_CW LTC Clear Written Register 0x40 32 read-write 0 0xFFFFFFFF CM Clear the Mode Register. Writing a one to this bit causes the Mode Register to be cleared. 0 1 write-only CDS Clear the Data Size Register 2 1 write-only CICV Clear the ICV Size Register. Writing a one to this bit causes the ICV Size Register to be cleared. 3 1 write-only CCR Clear the Context Register. Writing a one to this bit causes the Context Register to be cleared. 5 1 write-only CKR Clear the Key Register 6 1 write-only COF Clear Output FIFO. Writing a 1 to this bit causes the Output FIFO to be cleared. 30 1 write-only CIF Clear Input FIFO. Writing a 1 to this bit causes the Input Data FIFO. 31 1 write-only LTC_STA LTC Status Register 0x48 32 read-write 0 0xFFFFFFFF AB AESA Busy 1 1 read-only 0 AESA Idle #0 1 AESA Busy. #1 DI Done Interrupt 16 1 read-write EI Error Interrupt 20 1 read-only 0 Not Error. #0 1 Error Interrupt. #1 LTC_ESTA LTC Error Status Register 0x4C 32 read-only 0 0xFFFFFFFF ERRID1 Error ID 1 0 4 read-only 0001 Mode Error #0001 0010 Data Size Error #0010 0011 Key Size Error #0011 0110 Data Arrived out of Sequence Error #0110 1010 ICV Check Failed #1010 1011 Internal Hardware Failure #1011 1100 CCM AAD Size Error (either 1. AAD flag in B0 =1 and no AAD type provided, 2. AAD flag in B0 = 0 and AAD povided, or 3. AAD flag in B0 =1 and not enough AAD provided - expecting more based on AAD size.) #1100 1111 Invalid Crypto Engine Selected #1111 CL1 algorithms. The algorithms field indicates which algorithm is asserting an error. Others reserved 8 4 read-only 0000 LTC General Error #0000 0001 AES #0001 LTC_AADSZ LTC AAD Size Register 0x58 32 read-write 0 0xFFFFFFFF AADSZ AAD size in Bytes, mod 16. 0 4 read-write AL AAD Last. Only AAD data will be written into the Input FIFO. 31 1 read-write LTC_CTX_0 LTC Context Register 0x100 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC_CTX_1 LTC Context Register 0x104 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC_CTX_2 LTC Context Register 0x108 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC_CTX_3 LTC Context Register 0x10C 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC_CTX_4 LTC Context Register 0x110 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC_CTX_5 LTC Context Register 0x114 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC_CTX_6 LTC Context Register 0x118 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC_CTX_7 LTC Context Register 0x11C 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC_CTX_8 LTC Context Register 0x120 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC_CTX_9 LTC Context Register 0x124 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC_CTX_10 LTC Context Register 0x128 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC_CTX_11 LTC Context Register 0x12C 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC_CTX_12 LTC Context Register 0x130 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC_CTX_13 LTC Context Register 0x134 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC_CTX_14 LTC Context Register 0x138 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC_CTX_15 LTC Context Register 0x13C 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC_KEY_0 LTC Key Registers 0x200 32 read-write 0 0xFFFFFFFF KEY KEY 0 32 read-write LTC_KEY_1 LTC Key Registers 0x204 32 read-write 0 0xFFFFFFFF KEY KEY 0 32 read-write LTC_KEY_2 LTC Key Registers 0x208 32 read-write 0 0xFFFFFFFF KEY KEY 0 32 read-write LTC_KEY_3 LTC Key Registers 0x20C 32 read-write 0 0xFFFFFFFF KEY KEY 0 32 read-write LTC_VID2 LTC Version ID 2 Register 0x4F4 32 read-only 0 0xFFFFFFFF ECO_REV ECO revision number. 0 8 read-only ARCH_ERA Architectural ERA. 8 8 read-only LTC_FIFOSTA LTC FIFO Status Register 0x7C0 32 read-only 0 0xFFFFFFFF IFL Input FIFO Level. These bits indicate the current number of entries in the Input FIFO. 0 7 read-only IFF Input FIFO Full. The Input FIFO is full and should not be written to. 15 1 read-only OFL Output FIFO Level. These bits indicate the current number of entries in the Output FIFO. 16 7 read-only OFF Output FIFO Full. The Output FIFO is full and should not be written to. 31 1 read-only LTC_IFIFO LTC Input Data FIFO 0x7E0 32 write-only 0 0xFFFFFFFF IFIFO IFIFO 0 32 write-only LTC_OFIFO LTC Output Data FIFO 0x7F0 32 read-only 0 0xFFFFFFFF OFIFO Output FIFO 0 32 read-only LTC_VID1 LTC Version ID Register 0x8F0 32 read-only 0x340100 0xFFFFFFFF MIN_REV Minor revision number. 0 8 read-only MAJ_REV Major revision number. 8 8 read-only IP_ID no description available 16 16 read-only LTC_CHAVID LTC CHA Version ID Register 0x8F8 32 read-only 0x51 0xFFFF00FF AESREV AES Revision Number 0 4 read-only AESVID AES Version ID 4 4 read-only RSIM Radio System Integration Module RSIM_ 0x40059000 0 0x14 registers BTLL_RSIM 24 CONTROL RSIM Control 0 32 read-write 0xC00000 0xFFFFFFFF BLE_RF_OSC_REQ_EN BLE Ref Osc (Sysclk) Request Enable 0 1 read-write BLE_RF_OSC_REQ_STAT BLE Ref Osc (Sysclk) Request Status 1 1 read-only BLE_RF_OSC_REQ_INT_EN BLE Ref Osc (Sysclk) Request Interrupt Enable 4 1 read-write BLE_RF_OSC_REQ_INT BLE Ref Osc (Sysclk) Request Interrupt Flag 5 1 read-write RF_OSC_EN RF Ref Osc Enable [3:0] 8 4 read-write 0000 RF Ref Osc will be controlled by the SoC or the BLE link layer #0000 0001 RF Ref Osc on in Run/Wait #0001 0011 RF Ref Osc on in Stop #0011 0111 RF Ref Osc on in VLPR/VLPW #0111 1111 RF Ref Osc on in VLPS #1111 GASKET_BYPASS_OVRD_EN Gasket Bypass Override Enable 12 1 read-write GASKET_BYPASS_OVRD Gasket Bypass Override 13 1 read-write RF_OSC_BYPASS_EN RF Ref Osc Bypass Enable 14 1 read-write BLE_ACTIVE_PORT_1_SEL BLE Active port 1 select 16 1 read-write BLE_ACTIVE_PORT_2_SEL BLE Active port 2 select 17 1 read-write BLE_DEEP_SLEEP_EXIT BLE Deep Sleep Exit 20 1 read-write STOP_ACK_OVRD_EN Stop Acknowledge Override Enable 22 1 read-write STOP_ACK_OVRD Stop Acknowledge Override 23 1 read-write RF_OSC_READY RF Ref Osc Ready 24 1 read-only RF_OSC_READY_OVRD_EN RF Ref Osc Ready Override Enable 25 1 read-write RF_OSC_READY_OVRD RF Ref Osc Ready Override 26 1 read-write BLOCK_RADIO_RESETS Block Radio Resets 28 1 read-write BLOCK_RADIO_OUTPUTS Block Radio Outputs 29 1 read-write RADIO_RESET Software Reset for the Radio 31 1 read-write ACTIVE_DELAY RSIM BLE Active Delay 0x4 32 read-write 0 0xFFFFFFFF BLE_ACTIVE_FINE_DELAY The SoC Flash is presented with a BLE Active early warning signal to allow the Flash to complete any program or erase activities prior to a Radio communication event 0 6 read-write BLE_ACTIVE_COARSE_DELAY The SoC Flash is presented with a BLE Active early warning signal to allow the Flash to complete any program or erase activities prior to a Radio communication event 16 4 read-write MAC_MSB RSIM MAC MSB 0x8 32 read-only 0 0xFFFFFFFF MAC_ADDR_MSB MAC Address MSB 0 8 read-only MAC_LSB RSIM MAC LSB 0xC 32 read-only 0 0xFFFFFFFF MAC_ADDR_LSB MAC Address LSB 0 32 read-only ANA_TEST RSIM Analog Test 0x10 32 read-write 0x1000000 0xFFFFFFFF ATST_GATE_EN ATST Transmission Gate Enables 0 5 read-write RADIO_ID Radio Version ID number 24 4 read-only 0001 Apache 1.0 #0001 0010 Apache 2.0 #0010 0011 2.4 GHz Radio 2.0, Used by various SoC implementations #0011 DCDC DC to DC Converter DCDC_ 0x4005A000 0 0x20 registers LVD_LVW_DCDC 6 REG0 DCDC REGISTER 0 0 32 read-write 0x4180000 0xFFFFFFFF DCDC_DISABLE_AUTO_CLK_SWITCH Disable automatic clock switch from internal oscillator to external clock. 1 1 read-write DCDC_SEL_CLK Select external clock for DCDC when DCDC_DISABLE_AUTO_CLK_SWITCH is set. 2 1 read-write DCDC_PWD_OSC_INT Power down internal oscillator. Only set this bit when 32M crystal oscillator is available. 3 1 read-write DCDC_LP_DF_CMP_ENABLE Enable low power differential comparators, to sense lower supply in pulsed mode 9 1 read-write DCDC_VBAT_DIV_CTRL Controls VBAT voltage divider 10 2 read-write DCDC_LP_STATE_HYS_L Configure the hysteretic lower threshold value in low power mode 17 2 read-write 00 Target voltage value - 0 mV #00 01 Target voltage value - 25 mV #01 10 Target voltage value - 50 mV #10 11 Target voltage value - 75 mV #11 DCDC_LP_STATE_HYS_H Configure the hysteretic upper threshold value in low power mode 19 2 read-write 00 Target voltage value + 0 mV #00 01 Target voltage value + 25 mV #01 10 Target voltage value + 50 mV #10 11 Target voltage value + 75 mV #11 HYST_LP_COMP_ADJ Adjust hysteretic value in low power comparator. 21 1 read-write HYST_LP_CMP_DISABLE Disable hysteresis in low power comparator. 22 1 read-write OFFSET_RSNS_LP_ADJ Adjust hysteretic value in low power voltage sense. 23 1 read-write OFFSET_RSNS_LP_DISABLE Disable hysteresis in low power voltage sense. 24 1 read-write DCDC_LESS_I Reduce DCDC current. It will save approximately 20 uA in RUN. 25 1 read-write PWD_CMP_OFFSET Power down output range comparator 26 1 read-write DCDC_XTALOK_DISABLE Disable xtalok detection circuit. 27 1 read-write PSWITCH_STATUS Status register to indicate PSWITCH status 28 1 read-only VLPS_CONFIG_DCDC_HP Selects behavior of DCDC in device VLPS low power mode 29 1 read-write VLPR_VLPW_CONFIG_DCDC_HP Selects behavior of DCDC in device VLPR and VLPW low power modes 30 1 read-write DCDC_STS_DC_OK Status register to indicate DCDC lock 31 1 read-only REG1 DCDC REGISTER 1 0x4 32 read-write 0x17C21C 0xFFFFFFFF POSLIMIT_BUCK_IN Upper limit duty cycle limit in DC-DC converter 0 7 read-write POSLIMIT_BOOST_IN Upper limit duty cycle limit in DC-DC converter 7 7 read-write DCDC_LOOPCTRL_CM_HST_THRESH Enable hysteresis in switching converter common mode analog comparators 21 1 read-write DCDC_LOOPCTRL_DF_HST_THRESH Enable hysteresis in switching converter differential mode analog comparators 22 1 read-write DCDC_LOOPCTRL_EN_CM_HYST Enable hysteresis in switching converter common mode analog comparators 23 1 read-write DCDC_LOOPCTRL_EN_DF_HYST Enable hysteresis in switching converter differential mode analog comparators 24 1 read-write REG2 DCDC REGISTER 2 0x8 32 read-write 0x4009 0xFFFFFFFF DCDC_LOOPCTRL_DC_C Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter, it can be used to optimize efficiency and loop response 0 2 read-write DCDC_LOOPCTRL_DC_FF Two complement feed forward step in duty cycle in the switching DC-DC converter 6 3 read-write DCDC_LOOPCTRL_HYST_SIGN Invert the sign of the hysteresis in DC-DC analog comparators. This bit is set when in Pulsed mode. 13 1 read-write DCDC_LOOPCTRL_TOGGLE_DIF Set high to enable supply stepping to change, only after the differential control loop has toggled 14 1 read-write DCDC_BATTMONITOR_EN_BATADJ This bit enables the DC-DC to improve efficiency and minimize ripple using the information from the BATT_VAL field 15 1 read-write DCDC_BATTMONITOR_BATT_VAL Software should be configured to place the battery voltage in this register measured with an 8 mV LSB resolution through the ADC 16 10 read-write REG3 DCDC REGISTER 3 0xC 32 read-write 0xA9C6 0xFFFFFFFF DCDC_VDD1P8CTRL_TRG Target value of VDD1P8, 25 mV each step in two ranges, from 0x00 to 0x11 and 0x20 to 0x3F. 0 6 read-write 0 1.65 V #0 110 1.8 V #110 10001 2.075 V #10001 100000 2.8 V #100000 110100 3.3 V #110100 111111 3.575 V #111111 DCDC_VDD1P45CTRL_TRG_BUCK Target value of VDD1P45 in buck mode, 25 mV each step from 0x00 to 0x0F 6 5 read-write 1111 1.65 V #01111 111 1.45 V #00111 0 1.275 V #00000 DCDC_VDD1P45CTRL_TRG_BOOST Target value of VDD1P45 in boost mode, 25 mV each step from 0x00 to 0x0F 11 5 read-write 10101 1.8 V #10101 1111 1.65 V #01111 111 1.45 V #00111 0 1.275 V #00000 DCDC_VDD1P45CTRL_ADJTN Adjust value of duty cycle when switching between VDD1P45 and VDD1P8. The unit is 1/32 or 3.125%. 17 4 read-write DCDC_MINPWR_DC_HALFCLK_PULSED Set DCDC clock to half frequency for the Pulsed mode. 21 1 read-write DCDC_MINPWR_DOUBLE_FETS_PULSED Use double switch FET for the Pulsed mode. 22 1 read-write DCDC_MINPWR_HALF_FETS_PULSED Use half switch FET for the Pulsed mode. 23 1 read-write DCDC_MINPWR_DC_HALFCLK Set DCDC clock to half frequency for the continuous mode. 24 1 read-write DCDC_MINPWR_DOUBLE_FETS Use double switch FET for the continuous mode. 25 1 read-write DCDC_MINPWR_HALF_FETS Use half switch FET for the continuous mode. 26 1 read-write DCDC_VDD1P45CTRL_DISABLE_STEP Disable stepping for VDD1P45. Must set this bit before enter low power modes. 29 1 read-write DCDC_VDD1P8CTRL_DISABLE_STEP Disable stepping for VDD1P8. Must set this bit before enter low power modes. 30 1 read-write REG4 DCDC REGISTER 4 0x10 32 read-write 0 0xFFFFFFFF DCDC_SW_SHUTDOWN Shut down DCDC in buck mode. DCDC can be turned on by pulling PSWITCH to high momentarily (min 50 ms). 0 1 read-write UNLOCK 0x3E77 KEY-Key needed to unlock HW_POWER_RESET register 16 16 read-write REG6 DCDC REGISTER 6 0x18 32 read-write 0 0xFFFFFFFF PSWITCH_INT_RISE_EN Enable rising edge detect for interrupt. 0 1 read-write PSWITCH_INT_FALL_EN Enable falling edge detect for interrupt. 1 1 read-write PSWITCH_INT_CLEAR Write 1 to clear interrupt. Set to 0 after clear. 2 1 read-write PSWITCH_INT_MUTE Mask interrupt to SoC, edge detection result can be read from PSIWTCH_INT_STS. 3 1 read-write PSWITCH_INT_STS PSWITCH edge detection interrupt status 31 1 read-only REG7 DCDC REGISTER 7 0x1C 32 read-write 0 0xFFFFFFFF INTEGRATOR_VALUE Integrator value which can be loaded in pulsed mode 0 19 read-write INTEGRATOR_VALUE_SEL Select the integrator value from above register or saved value in hardware. 19 1 read-write PULSE_RUN_SPEEDUP Enable pulse run speedup 20 1 read-write BLE_RF_REGS Bluetooth Low Energy RF Registers BLE_RF_REGS_ 0x4005B000 0xD00 0xE registers BLE_PART_ID Bluetooth Low Energy Part ID 0xD00 16 read-only 0x1 0xFFFF BLE_PART_ID BLE Part ID 0 16 read-only DSM_STATUS DSM Status 0xD04 16 read-only 0 0xFFFC ORF_SYSCLK_REQ RF Oscillator Requested 0 1 read-only RIF_LL_ACTIVE Link Layer Active 1 1 read-only BLE_AFC Bluetooth Low Energy AFC 0xD08 16 read-write 0 0xFFFF BLE_AFC BLE AFC Result 0 14 read-only LATCH_AFC_ON_ACCESS_MATCH Latch AFC Estimation on Access Address Match 15 1 read-write 0 BLE_AFC[13:0] is updated whenever preamble is detected #0 1 BLE_AFC[13:0] is latched at access address match, and will not be updated until the next access address match. #1 BLE_BSM Bluetooth Low Energy BSM 0xD0C 16 read-write 0 0xFFFF BSM_EN_BLE BLE Bit Streaming Mode Enable 0 1 read-write 0 BLE Bit Streaming Mode disabled #0 1 BLE Bit Streaming Mode enabled #1 XCVR Apache 1.0 Transceiver XCVR_ 0x4005C000 0 0x480 registers RX_DIG_CTRL RX Digital Control 0 32 read-write 0 0xFFFFFFFF RX_ADC_NEGEDGE Receive ADC Negative Edge Selection 0 1 read-write 0 Register ADC data on positive edge of clock #0 1 Register ADC data on negative edge of clock #1 RX_CH_FILT_BYPASS Receive Channel Filter Bypass 1 1 read-write 0 Channel filter is enabled. #0 1 Disable and bypass channel filter. #1 RX_ADC_RAW_EN ADC Raw Mode selection 2 1 read-write 0 Normal operation. #0 1 The decimation filter's 12bit output consists of two unfiltered 5-bit ADC samples. This is for test purposes only to observe ADC output via XCVR DMA or DTEST. #1 RX_DEC_FILT_OSR Decimation Filter Oversampling 4 3 read-write 0 OSR 2 #000 1 OSR 4 #001 10 OSR 8 #010 11 OSR 9 #011 100 OSR 16 #100 101 OSR 18 #101 RX_INTERP_EN Interpolator Enable 8 1 read-write 0 Interpolator is disabled. #0 1 Interpolator is enabled. #1 RX_NORM_EN Normalizer Enable 9 1 read-write 0 Normalizer is disabled. #0 1 Normalizer is enabled. #1 RX_RSSI_EN RSSI Measurement Enable 10 1 read-write 0 RSSI measurement is disabled. #0 1 RSSI measurement is enabled. #1 RX_AGC_EN AGC Global Enable 11 1 read-write 0 AGC is disabled. #0 1 AGC is enabled. #1 RX_DCOC_EN DCOC Enable 12 1 read-write 0 DCOC is disabled. #0 1 DCOC is enabled. #1 RX_DCOC_CAL_EN DCOC Calibration Enable 13 1 read-write 0 DCOC calibration is disabled. #0 1 DCOC calibration is enabled. #1 RX_IQ_SWAP RX IQ Swap 14 1 read-write 0 IQ swap is disabled. #0 1 IQ swap is enabled. #1 AGC_CTRL_0 AGC Control 0 0x4 32 read-write 0 0xFFFFFFFF SLOW_AGC_EN Slow AGC Enable 0 1 read-write SLOW_AGC_SRC Slow AGC Source Selection 1 2 read-write 0 BTLE Preamble Detect #00 1 Zigbee Preamble Detect #01 10 Fast AGC expire timer #10 AGC_FREEZE_EN AGC Freeze Enable 3 1 read-write FREEZE_AGC_SRC Freeze AGC Source Selection 4 2 read-write 0 BTLE Preamble Detect #00 1 Zigbee Preamble Detect #01 10 BTLE access match (orf_access_match freeze) #10 11 Zigbee LQI done (1=freeze, 0=run AGC) #11 AGC_UP_EN AGC Up Enable 6 1 read-write AGC_UP_SRC AGC Up Source 7 1 read-write 0 PDET LO #0 1 RSSI #1 AGC_DOWN_BBF_STEP_SZ AGC_DOWN_BBF_STEP_SZ 8 4 read-write AGC_DOWN_TZA_STEP_SZ AGC_DOWN_TZA_STEP_SZ 12 4 read-write AGC_UP_RSSI_THRESH AGC UP RSSI Threshold 16 8 read-write AGC_DOWN_RSSI_THRESH AGC DOWN RSSI Threshold 24 8 read-write AGC_CTRL_1 AGC Control 1 0x8 32 read-write 0 0xFFFFFFFF BBF_ALT_CODE BBF_ALT_CODE 0 4 read-write LNM_ALT_CODE LNM_ALT_CODE 4 8 read-write LNM_USER_GAIN LNM_USER_GAIN 12 4 read-write BBF_USER_GAIN BBF_USER_GAIN 16 4 read-write USER_LNM_GAIN_EN User LNM Gain Enable 20 1 read-write USER_BBF_GAIN_EN User BBF Gain Enable 21 1 read-write PRESLOW_EN Pre-slow Enable 22 1 read-write 0 Pre-slow is disabled. #0 1 Pre-slow is enabled. #1 TZA_GAIN_SETTLE_TIME TZA_GAIN_SETTLE_TIME 24 8 read-write AGC_CTRL_2 AGC Control 2 0xC 32 read-write 0 0xFFFFFFFF BBF_PDET_RST BBF PDET Reset 0 1 read-write TZA_PDET_RST TZA PDET Reset 1 1 read-write BBF_GAIN_SETTLE_TIME BBF Gain Settle Time 4 8 read-write BBF_PDET_THRESH_LO BBF PDET Threshold Low 12 3 read-write 000 0.6V #000 001 0.675V #001 010 0.75V #010 011 0.825V #011 100 0.9V #100 101 0.975V #101 110 1.05V #110 111 1.125V #111 BBF_PDET_THRESH_HI BBF PDET Threshold High 15 3 read-write 000 0.6V #000 001 0.675V #001 010 0.75V #010 011 0.825V #011 100 0.9V #100 101 0.975V #101 110 1.05V #110 111 1.125V #111 TZA_PDET_THRESH_LO TZA PDET Threshold Low 18 3 read-write 000 0.6V #000 001 0.675V #001 010 0.75V #010 011 0.825V #011 100 0.9V #100 101 0.975V #101 110 1.05V #110 111 1.125V #111 TZA_PDET_THRESH_HI TZA PDET Threshold High 21 3 read-write 000 0.6V #000 001 0.675V #001 010 0.75V #010 011 0.825V #011 100 0.9V #100 101 0.975V #101 110 1.05V #110 111 1.125V #111 AGC_FAST_EXPIRE AGC Fast Expire 24 6 read-write AGC_CTRL_3 AGC Control 3 0x10 32 read-write 0 0xFFFFFFFF AGC_UNFREEZE_TIME AGC Unfreeze Time 0 13 read-write AGC_PDET_LO_DLY AGC Peak Detect Low Delay 13 3 read-write AGC_RSSI_DELT_H2S AGC_RSSI_DELT_H2S 16 7 read-write AGC_H2S_STEP_SZ AGC_H2S_STEP_SZ 23 5 read-write AGC_UP_STEP_SZ AGC Up Step Size 28 4 read-write AGC_STAT AGC Status 0x14 32 read-only 0 0xFFFFFFFF BBF_PDET_LO_STAT BBF Peak Detector Low Status 0 1 read-only BBF_PDET_HI_STAT BBF Peak Detector High Status 1 1 read-only TZA_PDET_LO_STAT TZA Peak Detector Low Status 2 1 read-only TZA_PDET_HI_STAT TZA Peak Detector High Status 3 1 read-only CURR_AGC_IDX Current AGC Gain Index 4 5 read-only AGC_FROZEN AGC Frozen Status 9 1 read-only 0 AGC is not frozen. #0 1 AGC is frozen. #1 RSSI_ADC_RAW ADC RAW RSSI Reading 16 8 read-only RSSI_CTRL_0 RSSI Control 0 0x18 32 read-write 0 0xFFFFFFFF RSSI_USE_VALS RSSI Values Selection 0 1 read-write RSSI_HOLD_SRC Hold RSSI Source Selection 1 2 read-write 0 BTLE Preamble Detect #00 1 Zigbee Preamble Detect #01 10 BTLE access match (orf_access_match freeze) #10 11 Zigbee LQI done (1=freeze, 0=run AGC) #11 RSSI_HOLD_EN RSSI Hold Enable 3 1 read-write RSSI_DEC_EN RSSI Decimation Enable 4 1 read-write RSSI_IIR_CW_WEIGHT RSSI IIR CW Weighting 5 2 read-write 0 Bypass #00 1 1/8 #01 10 1/16 #10 11 1/32 #11 RSSI_IIR_WEIGHT RSSI IIR Weighting 16 4 read-write 0 Bypass #0000 1 1/2 #0001 10 1/4 #0010 11 1/8 #0011 100 1/16 #0100 101 1/32 #0101 RSSI_ADJ RSSI Adjustment 24 8 read-write RSSI_CTRL_1 RSSI Control 1 0x1C 32 read-write 0 0xFFFFFFFF RSSI_ED_THRESH0 RSSI Energy Detect 0 Threshold 0 8 read-write RSSI_ED_THRESH1 RSSI Energy Detect 1 Threshold 8 8 read-write RSSI_ED_THRESH0_H RSSI Energy Detect 0 Hysteresis 16 4 read-write RSSI_ED_THRESH1_H RSSI Energy Detect 1 Hysteresis 20 4 read-write RSSI_OUT RSSI Reading 24 8 read-only DCOC_CTRL_0 DCOC Control 0 0x20 32 read-write 0 0xFFFFFFFF DCOC_MAN DCOC Manual Override 1 1 read-write DCOC_TRACK_EN DCOC Tracking Enable 3 1 read-write DCOC_CORRECT_EN DCOC Correction Enable 4 1 read-write DCOC_SIGN_SCALE_IDX DCOC Sign Scaling 5 2 read-write 00 1/4 #00 01 1/8 #01 10 1/16 #10 11 1/32 #11 DCOC_ALPHAC_SCALE_IDX DCOC Alpha-C Scaling 8 2 read-write 00 1/2 #00 01 1/4 #01 10 1/8 #10 11 1/16 #11 DCOC_ALPHA_RADIUS_IDX Alpha-R Scaling 12 3 read-write 000 1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 DCOC_CAL_DURATION DCOC Calibration Duration 15 5 read-write DCOC_CORR_DLY DCOC Correction Delay 20 5 read-write DCOC_CORR_HOLD_TIME DCOC Correction Hold Time 25 7 read-write DCOC_CTRL_1 DCOC Control 1 0x24 32 read-write 0 0xFFFFFFFF BBF_DCOC_STEP DCOC BBF Step Size 0 9 read-write TRACK_FROM_ZERO Track from Zero 24 1 read-write 0 Track from current I/Q sample. #0 1 Track from zero. #1 BBA_CORR_POL BBA Correction Polarity 25 1 read-write 0 Normal polarity. #0 1 Negative polarity. This should be set if the ADC output is inverted, or if the BBA DACs were implemented with negative polarity. #1 TZA_CORR_POL TZA Correction Polarity 26 1 read-write 0 Normal polarity. #0 1 Negative polarity. This should be set if the ADC output is inverted, or if the TZA DACs were implemented with negative polarity. #1 DCOC_CTRL_2 DCOC Control 2 0x28 32 read-write 0 0xFFFFFFFF BBF_DCOC_STEP_RECIP DCOC BBF Reciprocal of Step Size 0 13 read-write DCOC_CTRL_3 DCOC Control 3 0x2C 32 read-write 0 0xFFFFFFFF BBF_DCOC_INIT_I DCOC BBF Init I 0 6 read-write BBF_DCOC_INIT_Q DCOC BBF Init Q 8 6 read-write TZA_DCOC_INIT_I DCOC TZA Init I 16 8 read-write TZA_DCOC_INIT_Q DCOC TZA Init Q 24 8 read-write DCOC_CTRL_4 DCOC Control 4 0x30 32 read-write 0 0xFFFFFFFF DIG_DCOC_INIT_I DCOC DIG Init I 0 12 read-write DIG_DCOC_INIT_Q DCOC DIG Init Q 16 12 read-write DCOC_CAL_GAIN DCOC Calibration Gain 0x34 32 read-write 0 0xFFFFFFFF DCOC_BBF_CAL_GAIN1 DCOC BBF Calibration Gain 1 8 4 read-write DCOC_TZA_CAL_GAIN1 DCOC TZA Calibration Gain 1 12 4 read-write DCOC_BBF_CAL_GAIN2 DCOC BBF Calibration Gain 2 16 4 read-write DCOC_TZA_CAL_GAIN2 DCOC TZA Calibration Gain 2 20 4 read-write DCOC_BBF_CAL_GAIN3 DCOC BBF Calibration Gain 3 24 4 read-write DCOC_TZA_CAL_GAIN3 DCOC TZA Calibration Gain 3 28 4 read-write DCOC_STAT DCOC Status 0x38 32 read-only 0x80802020 0xFFFFFFFF BBF_DCOC_I DCOC BBF DAC I 0 6 read-only BBF_DCOC_Q DCOC BBF DAC Q 8 6 read-only TZA_DCOC_I DCOC TZA DAC I 16 8 read-only TZA_DCOC_Q DCOC TZA DAC Q 24 8 read-only DCOC_DC_EST DCOC DC Estimate 0x3C 32 read-only 0 0xFFFFFFFF DC_EST_I DCOC DC Estimate I 0 12 read-only DC_EST_Q DCOC DC Estimate Q 16 12 read-only DCOC_CAL_RCP DCOC Calibration Reciprocals 0x40 32 read-write 0 0xFFFFFFFF DCOC_TMP_CALC_RECIP DCOC Calculation Reciprocal 0 10 read-write ALPHA_CALC_RECIP Alpha Calculation Reciprocal 10 11 read-write IQMC_CTRL IQMC Control 0x4C 32 read-write 0x8000 0xFFFFFFFF IQMC_CAL_EN IQ Mismatch Cal Enable 0 1 read-write IQMC_NUM_ITER IQ Mismatch Cal Num Iter 8 8 read-write IQMC_CAL IQMC Calibration 0x50 32 read-write 0x400 0xFFFFFFFF IQMC_GAIN_ADJ IQ Mismatch Correction Gain Coeff 0 11 read-write IQMC_PHASE_ADJ IQ Mismatch Correction Phase Coeff 16 12 read-write TCA_AGC_VAL_3_0 TCA AGC Step Values 3..0 0x54 32 read-write 0x3C242C14 0xFFFFFFFF TCA_AGC_VAL_0 TCA_AGC step 0 0 8 read-write TCA_AGC_VAL_1 TCA_AGC step 1 8 8 read-write TCA_AGC_VAL_2 TCA_AGC step 2 16 8 read-write TCA_AGC_VAL_3 TCA_AGC step 3 24 8 read-write TCA_AGC_VAL_7_4 TCA AGC Step Values 7..4 0x58 32 read-write 0x9C846C54 0xFFFFFFFF TCA_AGC_VAL_4 TCA_AGC step 4 0 8 read-write TCA_AGC_VAL_5 TCA_AGC step 5 8 8 read-write TCA_AGC_VAL_6 TCA_AGC step 6 16 8 read-write TCA_AGC_VAL_7 TCA_AGC step 7 24 8 read-write TCA_AGC_VAL_8 TCA AGC Step Values 8 0x5C 32 read-write 0xB4 0xFFFFFFFF TCA_AGC_VAL_8 TCA_AGC step 8 0 8 read-write BBF_RES_TUNE_VAL_7_0 BBF Resistor Tune Values 7..0 0x60 32 read-write 0 0xFFFFFFFF BBF_RES_TUNE_VAL_0 BBF Resistor Tune Step 0 0 4 read-write BBF_RES_TUNE_VAL_1 BBF Resistor Tune Step 1 4 4 read-write BBF_RES_TUNE_VAL_2 BBF Resistor Tune Step 2 8 4 read-write BBF_RES_TUNE_VAL_3 BBF Resistor Tune Step 3 12 4 read-write BBF_RES_TUNE_VAL_4 BBF Resistor Tune Step 4 16 4 read-write BBF_RES_TUNE_VAL_5 BBF Resistor Tune Step 5 20 4 read-write BBF_RES_TUNE_VAL_6 BBF Resistor Tune Step 6 24 4 read-write BBF_RES_TUNE_VAL_7 BBF Resistor Tune Step 7 28 4 read-write BBF_RES_TUNE_VAL_10_8 BBF Resistor Tune Values 10..8 0x64 32 read-write 0 0xFFFFFFFF BBF_RES_TUNE_VAL_8 BBF Resistor Tune Step 8 0 4 read-write BBF_RES_TUNE_VAL_9 BBF Resistor Tune Step 9 4 4 read-write BBF_RES_TUNE_VAL_10 BBF Resistor Tune Step 10 8 4 read-write TCA_AGC_LIN_VAL_2_0 TCA AGC Linear Gain Values 2..0 0x68 32 read-write 0 0xFFFFFFFF TCA_AGC_LIN_VAL_0 LNM linear gain value for index 0, e.g. nominal value is 10^(-3/20). Stored with 2 fractional bits, e.g. round([10^(-3/20)]*2^2) = 3decimal 0 10 read-write TCA_AGC_LIN_VAL_1 TCA AGC Linear Gain Step 1 10 10 read-write TCA_AGC_LIN_VAL_2 TCA AGC Linear Gain Step 2 20 10 read-write TCA_AGC_LIN_VAL_5_3 TCA AGC Linear Gain Values 5..3 0x6C 32 read-write 0 0xFFFFFFFF TCA_AGC_LIN_VAL_3 TCA AGC Linear Gain Step 3 0 10 read-write TCA_AGC_LIN_VAL_4 TCA AGC Linear Gain Step 4 10 10 read-write TCA_AGC_LIN_VAL_5 TCA AGC Linear Gain Step 5 20 10 read-write TCA_AGC_LIN_VAL_8_6 TCA AGC Linear Gain Values 8..6 0x70 32 read-write 0 0xFFFFFFFF TCA_AGC_LIN_VAL_6 TCA AGC Linear Gain Step 6 0 10 read-write TCA_AGC_LIN_VAL_7 TCA AGC Linear Gain Step 7 10 10 read-write TCA_AGC_LIN_VAL_8 TCA AGC Linear Gain Step 8 20 10 read-write BBF_RES_TUNE_LIN_VAL_3_0 BBF Resistor Tune Values 3..0 0x74 32 read-write 0 0xFFFFFFFF BBF_RES_TUNE_LIN_VAL_0 BBF Resistor Tune Linear Gain Step 0 0 8 read-write BBF_RES_TUNE_LIN_VAL_1 BBF Resistor Tune Linear Gain Step 1 8 8 read-write BBF_RES_TUNE_LIN_VAL_2 BBF Resistor Tune Linear Gain Step 2 16 8 read-write BBF_RES_TUNE_LIN_VAL_3 BBF Resistor Tune Linear Gain Step 3 24 8 read-write BBF_RES_TUNE_LIN_VAL_7_4 BBF Resistor Tune Values 7..4 0x78 32 read-write 0 0xFFFFFFFF BBF_RES_TUNE_LIN_VAL_4 BBF Resistor Tune Linear Gain Step 4 0 8 read-write BBF_RES_TUNE_LIN_VAL_5 BBF Resistor Tune Linear Gain Step 5 8 8 read-write BBF_RES_TUNE_LIN_VAL_6 BBF Resistor Tune Linear Gain Step 6 16 8 read-write BBF_RES_TUNE_LIN_VAL_7 BBF Resistor Tune Linear Gain Step 7 24 8 read-write BBF_RES_TUNE_LIN_VAL_10_8 BBF Resistor Tune Values 10..8 0x7C 32 read-write 0 0xFFFFFFFF BBF_RES_TUNE_LIN_VAL_8 BBF Resistor Tune Linear Gain Step 8 0 8 read-write BBF_RES_TUNE_LIN_VAL_9 BBF Resistor Tune Linear Gain Step 9 8 8 read-write BBF_RES_TUNE_LIN_VAL_10 BBF Resistor Tune Linear Gain Step 10 16 8 read-write AGC_GAIN_TBL_03_00 AGC Gain Tables Step 03..00 0x80 32 read-write 0 0xFFFFFFFF BBF_GAIN_00 BBF Gain 00 0 4 read-write LNM_GAIN_00 LNM Gain 00 4 4 read-write BBF_GAIN_01 BBF Gain 01 8 4 read-write LNM_GAIN_01 LNM Gain 01 12 4 read-write BBF_GAIN_02 BBF Gain 02 16 4 read-write LNM_GAIN_02 LNM Gain 02 20 4 read-write BBF_GAIN_03 BBF Gain 03 24 4 read-write LNM_GAIN_03 LNM Gain 03 28 4 read-write AGC_GAIN_TBL_07_04 AGC Gain Tables Step 07..04 0x84 32 read-write 0 0xFFFFFFFF BBF_GAIN_04 BBF Gain 04 0 4 read-write LNM_GAIN_04 LNM Gain 04 4 4 read-write BBF_GAIN_05 BBF Gain 05 8 4 read-write LNM_GAIN_05 LNM Gain 05 12 4 read-write BBF_GAIN_06 BBF Gain 06 16 4 read-write LNM_GAIN_06 LNM Gain 06 20 4 read-write BBF_GAIN_07 BBF Gain 07 24 4 read-write LNM_GAIN_07 LNM Gain 07 28 4 read-write AGC_GAIN_TBL_11_08 AGC Gain Tables Step 11..08 0x88 32 read-write 0 0xFFFFFFFF BBF_GAIN_08 BBF Gain 08 0 4 read-write LNM_GAIN_08 LNM Gain 08 4 4 read-write BBF_GAIN_09 BBF Gain 09 8 4 read-write LNM_GAIN_09 LNM Gain 09 12 4 read-write BBF_GAIN_10 BBF Gain 10 16 4 read-write LNM_GAIN_10 LNM Gain 10 20 4 read-write BBF_GAIN_11 BBF Gain 11 24 4 read-write LNM_GAIN_11 LNM Gain 11 28 4 read-write AGC_GAIN_TBL_15_12 AGC Gain Tables Step 15..12 0x8C 32 read-write 0 0xFFFFFFFF BBF_GAIN_12 BBF Gain 12 0 4 read-write LNM_GAIN_12 LNM Gain 12 4 4 read-write BBF_GAIN_13 BBF Gain 13 8 4 read-write LNM_GAIN_13 LNM Gain 13 12 4 read-write BBF_GAIN_14 BBF Gain 14 16 4 read-write LNM_GAIN_14 LNM Gain 14 20 4 read-write BBF_GAIN_15 BBF Gain 15 24 4 read-write LNM_GAIN_15 LNM Gain 15 28 4 read-write AGC_GAIN_TBL_19_16 AGC Gain Tables Step 19..16 0x90 32 read-write 0 0xFFFFFFFF BBF_GAIN_16 BBF Gain 16 0 4 read-write LNM_GAIN_16 LNM Gain 16 4 4 read-write BBF_GAIN_17 BBF Gain 17 8 4 read-write LNM_GAIN_17 LNM Gain 17 12 4 read-write BBF_GAIN_18 BBF Gain 18 16 4 read-write LNM_GAIN_18 LNM Gain 18 20 4 read-write BBF_GAIN_19 BBF Gain 193 24 4 read-write LNM_GAIN_19 LNM Gain 19 28 4 read-write AGC_GAIN_TBL_23_20 AGC Gain Tables Step 23..20 0x94 32 read-write 0 0xFFFFFFFF BBF_GAIN_20 BBF Gain 20 0 4 read-write LNM_GAIN_20 LNM Gain 20 4 4 read-write BBF_GAIN_21 BBF Gain 21 8 4 read-write LNM_GAIN_21 LNM Gain 21 12 4 read-write BBF_GAIN_22 BBF Gain 22 16 4 read-write LNM_GAIN_22 LNM Gain 22 20 4 read-write BBF_GAIN_23 BBF Gain 23 24 4 read-write LNM_GAIN_23 LNM Gain 23 28 4 read-write AGC_GAIN_TBL_26_24 AGC Gain Tables Step 26..24 0x98 32 read-write 0 0xFFFFFFFF BBF_GAIN_24 BBF Gain 24 0 4 read-write LNM_GAIN_24 LNM Gain 24 4 4 read-write BBF_GAIN_25 BBF Gain 25 8 4 read-write LNM_GAIN_25 LNM Gain 25 12 4 read-write BBF_GAIN_26 BBF Gain 26 16 4 read-write LNM_GAIN_26 LNM Gain 26 20 4 read-write 27 0x4 00,01,02,03,04,05,06,07,08,09,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26 DCOC_OFFSET_%s DCOC Offset 0xA0 32 read-write 0 0xFFFFFFFF DCOC_BBF_OFFSET_I DCOC BBF I-channel offset 0 6 read-write DCOC_BBF_OFFSET_Q DCOC BBF Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write 11 0x4 00,01,02,03,04,05,06,07,08,09,10 DCOC_TZA_STEP_%s DCOC TZA DC step 0x110 32 read-write 0 0xFFFFFFFF DCOC_TZA_STEP_RCP DCOC_TZA_STEP_RCP 0 13 read-write DCOC_TZA_STEP_GAIN DCOC_TZA_STEP_GAIN 16 12 read-write DCOC_CAL_ALPHA DCOC Calibration Alpha 0x16C 32 read-only 0 0xFFFFFFFF DCOC_CAL_ALPHA_I DCOC Calibration I-channel ALPHA constant 0 16 read-only DCOC_CAL_ALPHA_Q DCOC_CAL_ALPHA_Q 16 16 read-only DCOC_CAL_BETA DCOC Calibration Beta 0x170 32 read-only 0 0xFFFFFFFF DCOC_CAL_BETA_I DCOC_CAL_BETA_I 0 16 read-only DCOC_CAL_BETA_Q DCOC_CAL_BETA_Q 16 16 read-only DCOC_CAL_GAMMA DCOC Calibration Gamma 0x174 32 read-only 0 0xFFFFFFFF DCOC_CAL_GAMMA_I DCOC_CAL_GAMMA_I 0 16 read-only DCOC_CAL_GAMMA_Q DCOC_CAL_GAMMA_Q 16 16 read-only DCOC_CAL_IIR DCOC Calibration IIR 0x178 32 read-write 0 0xFFFFFFFF DCOC_CAL_IIR1A_IDX DCOC Calibration IIR 1A Index 0 2 read-write 0 1/1 #00 1 1/4 #01 10 1/8 #10 11 1/16 #11 DCOC_CAL_IIR2A_IDX DCOC Calibration IIR 2A Index 2 2 read-write 0 1/1 #00 1 1/4 #01 10 1/8 #10 11 1/16 #11 DCOC_CAL_IIR3A_IDX DCOC Calibration IIR 3A Index 4 2 read-write 0 1/4 #00 1 1/8 #01 10 1/16 #10 11 1/32 #11 3 0x4 1,2,3 DCOC_CAL%s DCOC Calibration Result 0x180 32 read-only 0 0xFFFFFFFF DCOC_CAL_RES_I DCOC Calibration Result - I Channel 0 12 read-only DCOC_CAL_RES_Q DCOC Calibration Result - Q Channel 16 12 read-only 8 0x4 0,1,2,3,4,5,6,7 RX_CHF_COEF%s Receive Channel Filter Coefficient 0x1A0 32 read-write 0 0xFFFFFFFF RX_CH_FILT_HX RX Channel Filter Coefficient 0 8 read-write TX_DIG_CTRL TX Digital Control 0x200 32 read-write 0x140 0xFFFFFFFF DFT_MODE Radio DFT Modes 0 3 read-write 000 Normal Radio Operation. DFT not engaged. #000 001 Pattern Register Mode. TX DFT Modulation Pattern Register is shifted out as the transmission data stream. Note that the DFT_EN bit must be set. #001 010 LFSR Data Mode. TX LFSR is used as the transmission data stream. Note that the LFSR_EN bit must be set. #010 011 LFSR Symbol Mode. TX LFSR is used to create 802.15.4 symbols which are then converted to Chips and transmitted. Note that the LFSR_EN bit must be set. #011 100 Not implemented on Apache 1.0, future use will allow a package pin to be used as the source of the TX data stream. Note that the DFT_EN bit must be set. #100 101 Constant Frequency Mode. No data modulation is done, Radio transmits at the channel frequency selected. #101 110 LFSR Tone Mode. TX LFSR is used to select the DFT Tone register to transmit, LFSR_EN bit must be set. #110 111 Manual Tone Mode. TONE_SEL is used to select the DFT Tone register to transmit. #111 DFT_EN Radio DFT Mode Enable 3 1 read-write DFT_LFSR_LEN DFT LFSR Length 4 3 read-write 000 LFSR 9, tap mask 100010000 #000 001 LFSR 10, tap mask 1001000000 #001 010 LFSR 11, tap mask 11101000000 #010 011 LFSR 13, tap mask 1101100000000 #011 100 LFSR 15, tap mask 111010000000000 #100 101 LFSR 17, tap mask 11110000000000000 #101 LFSR_EN DFT LFSR Enable 7 1 read-write DFT_CLK_SEL DFT Clock Selection 8 3 read-write 000 62.5 kHz #000 001 125 kHz #001 010 250 kHz #010 011 500 kHz #011 100 1 MHz #100 101 2 MHz #101 110 4 MHz #110 111 Clock is off #111 TONE_SEL DFT Tone Selection 12 2 read-write 00 DFT Tone 0 #00 01 DFT Tone 1 #01 10 DFT Tone 2 #10 11 DFT Tone 3 #11 POL Oversample Clock Capture Polarity 16 1 read-write 0 Selects Even clock cycle #0 1 Selects Odd clock cycle, a one cycle delay #1 DP_SEL Data Padding Pattern Select 20 1 read-write 0 Selects DATA_PADDING_PATTERN_0 as the source for data padding #0 1 Selects DATA_PADDING_PATTERN_1 as the source for data padding #1 FREQ_WORD_ADJ GFSK Frequency Word Adjustment 22 10 read-write TX_DATA_PAD_PAT TX Data Padding Pattern 0x204 32 read-write 0x7FFF55AA 0xFFFFFFFF DATA_PADDING_PAT_0 Data Padding Pattern 0 0 8 read-write DATA_PADDING_PAT_1 Data Padding Pattern 1 8 8 read-write DFT_LFSR_OUT Transmit DFT LFSR Output 16 15 read-only LRM LFSR Reset Mask 31 1 read-write TX_GFSK_MOD_CTRL TX GFSK Modulation Control 0x208 32 read-write 0x3014000 0xFFFFFFFF GFSK_MULTIPLY_TABLE_MANUAL GFSK Multiply Lookup Table Override Value 0 16 read-write GFSK_MI GFSK Modulation Index 16 2 read-write 00 0.32 #00 01 0.50 #01 10 0.80 #10 11 1.00 #11 GFSK_MLD GFSK Multiply Lookup Table Disable 20 1 read-write GFSK_SYMBOL_RATE GFSK Symbol Rate 24 3 read-write 000 50 kHz #000 001 100 kHz #001 010 200 kHz #010 011 1 MHz #011 100 2 MHz #100 GFSK_FLD GFSK Filter Lookup Table Disable 28 1 read-write TX_GFSK_COEFF2 TX GFSK Filter Coefficients 2 0x20C 32 read-write 0xC0630401 0xFFFFFFFF GFSK_FILTER_COEFF_MANUAL2 GFSK Manual Filter Coefficients[63:32] 0 32 read-write TX_GFSK_COEFF1 TX GFSK Filter Coefficients 1 0x210 32 read-write 0xBB29960D 0xFFFFFFFF GFSK_FILTER_COEFF_MANUAL1 GFSK Manual Filter Coefficient [31:0] 0 32 read-write TX_FSK_MOD_SCALE TX FSK Modulation Scale 0x214 32 read-write 0x7FF1800 0xFFFFFFFF FSK_MODULATION_SCALE_0 FSK Modulation Scale for a data 0 0 13 read-write FSK_MODULATION_SCALE_1 FSK Modulation Scale for a data 1 16 13 read-write TX_DFT_MOD_PAT TX DFT Modulation Pattern 0x218 32 read-write 0 0xFFFFFFFF DFT_MOD_PATTERN DFT Modulation Pattern 0 32 read-write TX_DFT_TONE_0_1 TX DFT Tones 0 and 1 0x21C 32 read-write 0x10000FFF 0xFFFFFFFF DFT_TONE_1 DFT Tone 1 0 13 read-write DFT_TONE_0 DFT Tone 0 16 13 read-write TX_DFT_TONE_2_3 TX DFT Tones 2 and 3 0x220 32 read-write 0x1E0001FF 0xFFFFFFFF DFT_TONE_3 DFT Tone 3 0 13 read-write DFT_TONE_2 DFT Tone 2 16 13 read-write PLL_MOD_OVRD PLL Modulation Overrides 0x228 32 read-write 0 0xFFFFFFFF MODULATION_WORD_MANUAL Manual Modulation Word 0 13 read-write MOD_DIS Disable Modulation Word 15 1 read-write HPM_BANK_MANUAL Manual HPM bank 16 8 read-write HPM_BANK_DIS Disable HPM Bank 27 1 read-write HPM_LSB_MANUAL Manual HPM LSB 28 2 read-write HPM_LSB_DIS Disable HPM LSB 31 1 read-write PLL_CHAN_MAP PLL Channel Mapping 0x22C 32 read-write 0x200 0xFFFFFFFF CHANNEL_NUM Protocol specific Channel Number for PLL Frequency Mapping 0 7 read-write BOC BLE Channel Number Override 8 1 read-write 0 BLE channel number comes from the BLE Link Layer #0 1 BLE channel number comes from the CHANNEL_NUM register #1 BMR BLE MBAN Channel Remap 9 1 read-write 0 BLE channel 39 is mapped to BLE channel 39, 2.480 GHz #0 1 BLE channel 39 is mapped to MBAN channel 39, 2.399 GHz #1 ZOC Zigbee Channel Number Override 10 1 read-write 0 Zigbee channel number comes from the 802.15.4 Link Layer. #0 1 Zigbee channel number comes from the CHANNEL_NUM register #1 PLL_LOCK_DETECT PLL Lock Detect 0x230 32 read-write 0x202600 0xFFFFFFFF CT_FAIL Real time status of Coarse Tune Fail signal 0 1 read-only CTFF CTUNE Failure Flag, held until cleared 1 1 read-write CS_FAIL Real time status of Cycle Slip circuit 2 1 read-only CSFF Cycle Slip Failure Flag, held until cleared 3 1 read-write FT_FAIL Real time status of Frequency Target Failure 4 1 read-only FTFF Frequency Target Failure Flag 5 1 read-write TAFF TSM Abort Failure Flag 7 1 read-write CTUNE_LDF_LEV CTUNE Lock Detect Fail Level 8 4 read-write FTF_RX_THRSH RX Frequency Target Fail Threshold 12 6 read-write FTW_RX RX Frequency Target Window time select 19 1 read-write 0 4 us #0 1 8 us #1 FTF_TX_THRSH TX Frequency Target Fail Threshold 20 6 read-write FTW_TX TX Frequency Target Window time select 27 1 read-write 0 4 us #0 1 8 us #1 PLL_HP_MOD_CTRL PLL High Port Modulation Control 0x234 32 read-write 0x840000 0xFFFFFFFF HPM_SDM_MANUAL PLL HPM SDM MANUAL 0 10 read-write HPFF HPM SDM Invalid Flag 13 1 read-write HP_SDM_INV Invert HPM SDM 14 1 read-write HP_SDM_DIS Disable HPM SDM 15 1 read-write HPM_LFSR_LEN HPM LFSR Length 16 3 read-write 000 LFSR 9, tap mask 100010000 #000 001 LFSR 10, tap mask 1001000000 #001 010 LFSR 11, tap mask 11101000000 #010 011 LFSR 13, tap mask 1101100000000 #011 100 LFSR 15, tap mask 111010000000000 #100 101 LFSR 17, tap mask 11110000000000000 #101 HP_DTH_SCL HPM Dither Scale 20 1 read-write HPM_DTH_EN Dither Enable for HPM LFSR 23 1 read-write HPM_SCALE HPM Scale Factor 24 2 read-write 00 No Scaling #00 01 Multiply by 2 #01 10 Divide by 2 #10 HP_MOD_INV HPM Invert 31 1 read-write PLL_HPM_CAL_CTRL PLL HPM Calibration Control 0x238 32 read-write 0x400002A2 0xFFFFFFFF HPM_CAL_FACTOR High Port Modulation Calibration Factor 0 13 read-only HP_CAL_DIS If this bit is set, the lookup table value for the HPM Calibration Factor is overridden by the HPM_CAL_FACTOR_MANUAL register 15 1 read-write HPM_CAL_FACTOR_MANUAL HPM Manual Calibration Factor 16 13 read-write HP_CAL_ARY High Port Modulation Calibration Array Size 30 1 read-write 0 128 #0 1 256 #1 HP_CAL_TIME High Port Modulation Calibration Time 31 1 read-write 0 25 us #0 1 50 us #1 PLL_LD_HPM_CAL1 PLL Cycle Slip Lock Detect Configuration and HPM Calibration 1 0x23C 32 read-write 0x44300000 0xFFFFFFFF CNT_1 High Port Modulation Counter Value 1 0 17 read-only CS_WT Cycle Slip Wait Time 20 3 read-write 000 128 us #000 001 256 us #001 010 384 us #010 011 512 us #011 100 640 us #100 101 768 us #101 110 896 us #110 111 1024 us #111 CS_FW Cycle Slip Flag Window 24 3 read-write 000 8 us #000 001 16 us #001 010 24 us #010 011 32 us #011 100 64 us #100 101 96 us #101 110 128 us #110 111 256 us #111 CS_FCNT Cycle Slip Flag Count 28 4 read-write PLL_LD_HPM_CAL2 PLL Cycle Slip Lock Detect Configuration and HPM Calibration 2 0x240 32 read-write 0x2100000 0xFFFFFFFF CNT_2 High Port Modulation Counter Value 2 0 17 read-only CS_RC Cycle Slip Recycle 20 1 read-write CS_FT Cycle Slip Flag Timeout 24 5 read-write PLL_HPM_SDM_FRACTION PLL HPM SDM Fraction 0x244 32 read-write 0x1FF0000 0xFFFFFFFF HPM_NUM_SELECTED HPM_NUM_SELECTED 0 10 read-only HPM_DENOM High Port Modulation Denominator 16 10 read-write PLL_LP_MOD_CTRL PLL Low Port Modulation Control 0x248 32 read-write 0x8080000 0xFFFFFFFF PLL_LOOP_DIVIDER_MANUAL PLL Loop Divider Manual 0 6 read-write PLL_LD_DIS PLL Loop Divider Disable 11 1 read-write LPFF LPM SDM Invalid Flag 13 1 read-write LPM_SDM_INV Invert LPM SDM 14 1 read-write LPM_SDM_DIS Disable LPM SDM 15 1 read-write LPM_DTH_SCL LPM Dither Scale 16 4 read-write 0101 -128 to 96 #0101 0110 -256 to 192 #0110 0111 -512 to 384 #0111 1000 -1024 to 768 #1000 1001 -2048 to 1536 #1001 1010 -4096 to 3072 #1010 1011 -8192 to 6144 #1011 LPM_D_CTRL LPM Dither Control in Override Mode 22 1 read-write LPM_D_OVRD LPM Dither Override Mode Select 23 1 read-write LPM_SCALE LPM Scale Factor 24 4 read-write 0000 No Scaling #0000 0001 Multiply by 2 #0001 0010 Multiply by 4 #0010 0011 Multiply by 8 #0011 0100 Multiply by 16 #0100 0101 Multiply by 32 #0101 0110 Multiply by 64 #0110 0111 Multiply by 128 #0111 1000 Multiply by 256 #1000 1001 Multiply by 512 #1001 1010 Multiply by 1024 #1010 1011 Multiply by 2048 #1011 PLL_LP_SDM_CTRL1 PLL Low Port SDM Control 1 0x24C 32 read-write 0x260026 0xFFFFFFFF LPM_INTG_SELECTED Low Port Modulation Integer Value Selected 0 7 read-only LPM_INTG Low Port Modulation Integer Manual Value 16 7 read-write SDM_MAP_DIS SDM Mapping Disable 31 1 read-write PLL_LP_SDM_CTRL2 PLL Low Port SDM Control 2 0x250 32 read-write 0x2000000 0xFFFFFFFF LPM_NUM Low Port Modulation Numerator 0 28 read-write PLL_LP_SDM_CTRL3 PLL Low Port SDM Control 3 0x254 32 read-write 0x4000000 0xFFFFFFFF LPM_DENOM Low Port Modulation Denominator 0 28 read-write PLL_LP_SDM_NUM PLL Low Port SDM Numerator Applied 0x258 32 read-only 0xE200000 0xFFFFFFFF LPM_NUM_SELECTED Low Port Modulation Numerator Applied 0 28 read-only PLL_LP_SDM_DENOM PLL Low Port SDM Denominator Applied 0x25C 32 read-only 0x4000000 0xFFFFFFFF LPM_DENOM_SELECTED Low Port Modulation Denominator Selected 0 28 read-only PLL_DELAY_MATCH PLL Delay Matching 0x260 32 read-write 0x201 0xFFFFFFFF LP_SDM_DELAY LP_SDM_DELAY 0 4 read-write HPM_SDM_DELAY HPM_SDM_DELAY 8 4 read-write HPM_BANK_DELAY HPM Bank Delay 16 4 read-write PLL_CTUNE_CTRL PLL Coarse Tune Control 0x264 32 read-write 0 0xFFFFFFFF CTUNE_TARGET_MANUAL CTUNE Target Manual 0 12 read-write CTUNE_TD CTUNE Target Disable 15 1 read-write CTUNE_ADJUST CTUNE Count Adjustment 16 4 read-write CTUNE_MANUAL CTUNE Manual 24 7 read-write CTUNE_DIS CTUNE Disable 31 1 read-write PLL_CTUNE_CNT6 PLL Coarse Tune Count 6 0x268 32 read-only 0 0xFFFFFFFF CTUNE_COUNT_6 CTUNE Count 6 0 12 read-only PLL_CTUNE_CNT5_4 PLL Coarse Tune Counts 5 and 4 0x26C 32 read-only 0 0xFFFFFFFF CTUNE_COUNT_4 CTUNE Count 4 0 12 read-only CTUNE_COUNT_5 CTUNE Count 5 16 12 read-only PLL_CTUNE_CNT3_2 PLL Coarse Tune Counts 3 and 2 0x270 32 read-only 0 0xFFFFFFFF CTUNE_COUNT_2 CTUNE Count 2 0 12 read-only CTUNE_COUNT_3 CTUNE Count 3 16 12 read-only PLL_CTUNE_CNT1_0 PLL Coarse Tune Counts 1 and 0 0x274 32 read-only 0 0xFFFFFFFF CTUNE_COUNT_0 CTUNE Count 0 0 12 read-only CTUNE_COUNT_1 CTUNE Count 1 16 12 read-only PLL_CTUNE_RESULTS PLL Coarse Tune Results 0x278 32 read-only 0x9620040 0xFFFFFFFF CTUNE_SELECTED Coarse Tune Band to VCO 0 7 read-only CTUNE_BEST_DIFF Coarse Tune Absolute Best Difference 8 8 read-only CTUNE_FREQ_TARGET Coarse Tune Frequency Target 16 12 read-only CTRL Transceiver Control 0x280 32 read-write 0 0xFFFFFFFF PROTOCOL Radio Protocol Selection 0 3 read-write 000 BLE #000 001 BLE in MBAN #001 010 BLE overlap MBAN #010 100 Zigbee #100 101 802.15.4j #101 110 128 Channel FSK #110 111 128 Channel GFSK #111 TGT_PWR_SRC Target Power Source 4 2 read-write REF_CLK_FREQ Radio Reference Clock Frequency 6 2 read-write 00 32 MHz #00 STATUS Transceiver Status 0x284 32 read-only 0 0xFFF0CFFF TSM_COUNT TSM Count 0 8 read-only PLL_SEQ_STATE PLL Sequence State 8 4 read-only 0 PLL OFF #0000 10 CTUNE #0010 11 CTUNE_SETTLE #0011 110 HPMCAL1 #0110 1000 HPMCAL1_SETTLE #1000 1100 HPMCAL2_SETTLE #1100 1111 PLLREADY #1111 RX_MODE Receive Mode 12 1 read-only TX_MODE Transmit Mode 13 1 read-only BTLE_SYSCLK_REQ BTLE System Clock Request 16 1 read-only RIF_LL_ACTIVE Link Layer Active Indication 17 1 read-only XTAL_READY RF Osciallator Xtal Ready 18 1 read-only 0 Indicates that the RF Oscillator is disabled or has not completed its warmup. #0 1 Indicates that the RF Oscillator has completed its warmup count and is ready for use. #1 SOC_USING_RF_OSC_CLK SOC Using RF Clock Indication 19 1 read-only SOFT_RESET Soft Reset 0x288 32 read-only 0 0xFFFFFFFF OVERWRITE_VER Overwrite Version 0x290 32 read-write 0 0xFFFFFFFF OVERWRITE_VER Overwrite Version Number. 0 8 read-write DMA_CTRL DMA Control 0x294 32 read-write 0 0xFFFFFFFF DMA_I_EN DMA I Enable 0 1 read-write 0 Transceiver I channel DMA disabled. #0 1 Enable the transceiver DMA engine to store RX_DIG I channel outputs to system memory. #1 DMA_Q_EN DMA Q Enable 1 1 read-write 0 Transceiver Q channel DMA disabled. #0 1 Enable the transceiver DMA engine to store RX_DIG Q channel outputs to system memory. #1 DMA_DATA DMA Data 0x298 32 read-only 0 0xFFFFFFFF DMA_DATA_11_0 DMA_DATA_11_0 0 12 read-only DMA_DATA_27_16 DMA_DATA_27_16 16 12 read-only DTEST_CTRL Digital Test Control 0x29C 32 read-write 0 0xFFFFFFFF DTEST_PAGE DTEST Page Selector 0 6 read-write DTEST_EN DTEST Enable 7 1 read-write 0 Disables DTEST. The IC's DTEST pins assume their mission function. #0 1 Enables DTEST. The contents of the selected page (DTEST_PAGE) will appear on the IC's DTEST output pins. #1 GPIO0_OVLAY_PIN GPIO 0 Overlay Pin 8 4 read-write GPIO1_OVLAY_PIN GPIO 1 Overlay Pin 12 4 read-write TSM_GPIO_OVLAY_0 TSM GPIO 0 Overlay Pin 16 1 read-write 0 there is no overlay, and the DTEST Page Table dictates the node that appears on each DTEST pin. #0 1 the register GPIO0_OVLAY_PIN[3:0] selects the DTEST pin on which GPIO0_TRIG_EN will appear. #1 TSM_GPIO_OVLAY_1 TSM GPIO 1 Overlay Pin 17 1 read-write 0 there is no overlay, and the DTEST Page Table dictates the node that appears on each DTEST pin. #0 1 the register GPIO1_OVLAY_PIN[3:0] selects the DTEST pin on which GPIO1_TRIG_EN will appear. #1 DTEST_SHFT DTEST Shift Control 24 3 read-write RAW_MODE_I DTEST Raw Mode Enable for I Channel 28 1 read-write RAW_MODE_Q DTEST Raw Mode Enable for Q Channel 29 1 read-write PB_CTRL Packet Buffer Control Register 0x2A0 32 read-write 0 0xFFFFFFFF PB_PROTECT PB Protect 0 1 read-write 0 Incoming received packets overwrite Packet Buffer contents (default) #0 1 Incoming received packets are blocked from overwriting Packet Buffer contents #1 TSM_CTRL Transceiver Sequence Manager Control 0x2C0 32 read-write 0xFF000000 0xFFFFFFFF FORCE_TX_EN Force Transmit Enable 2 1 read-write 0 TSM Idle #0 1 TSM executes a TX sequence #1 FORCE_RX_EN Force Receive Enable 3 1 read-write 0 TSM Idle #0 1 TSM executes a RX sequence #1 PA_RAMP_SEL PA Ramp Selection 4 2 read-write DATA_PADDING_EN Data Padding Enable 6 1 read-write 0 Disable TX Data Padding #0 1 Enable TX Data Padding #1 TX_ABORT_DIS Transmit Abort Disable 16 1 read-write RX_ABORT_DIS Receive Abort Disable 17 1 read-write ABORT_ON_CTUNE Abort On Coarse Tune Lock Detect Failure 18 1 read-write 0 don't allow TSM abort on Coarse Tune Unlock Detect #0 1 allow TSM abort on Coarse Tune Unlock Detect #1 ABORT_ON_CYCLE_SLIP Abort On Cycle Slip Lock Detect Failure 19 1 read-write 0 don't allow TSM abort on Cycle Slip Unlock Detect #0 1 allow TSM abort on Cycle Slip Unlock Detect #1 ABORT_ON_FREQ_TARG Abort On Frequency Target Lock Detect Failure 20 1 read-write 0 don't allow TSM abort on Frequency Target Unlock Detect #0 1 allow TSM abort on Frequency Target Unlock Detect #1 BKPT TSM Breakpoint 24 8 read-write END_OF_SEQ End of Sequence Control 0x2C4 32 read-write 0x65646A67 0xFFFFFFFF END_OF_TX_WU End of TX Warmup 0 8 read-write END_OF_TX_WD End of TX Warmdown 8 8 read-write END_OF_RX_WU End of RX Warmup 16 8 read-write END_OF_RX_WD End of RX Warmdown 24 8 read-write TSM_OVRD0 TSM Override 0 0x2C8 32 read-write 0 0xFFFFFFFF PLL_REG_EN_OVRD_EN Override control for PLL_REG_EN 0 1 read-write 0 Normal operation. #0 1 Use the state of PLL_REG_EN_OVRD to override the signal "pll_reg_en". #1 PLL_REG_EN_OVRD Override value for PLL_REG_EN 1 1 read-write PLL_VCO_REG_EN_OVRD_EN Override control for PLL_VCO_REG_EN 2 1 read-write 0 Normal operation. #0 1 Use the state of PLL_VCO_REG_EN_OVRD to override the signal "pll_vco_reg_en". #1 PLL_VCO_REG_EN_OVRD Override value for PLL_VCO_REG_EN 3 1 read-write QGEN_REG_EN_OVRD_EN Override control for QGEN_REG_EN 4 1 read-write 0 Normal operation. #0 1 Use the state of QGEN_REG_EN_OVRD to override the signal "qgen_reg_en". #1 QGEN_REG_EN_OVRD Override value for QGEN_REG_EN 5 1 read-write TCA_TX_REG_EN_OVRD_EN Override control for TCA_TX_REG_EN 6 1 read-write 0 Normal operation. #0 1 Use the state of TCA_TX_REG_EN_OVRD to override the signal "tca_tx_reg_en". #1 TCA_TX_REG_EN_OVRD Override value for TCA_TX_REG_EN 7 1 read-write ADC_ANA_REG_EN_OVRD_EN Override control for ADC_ANA_REG_EN 8 1 read-write 0 Normal operation. #0 1 Use the state of ADC_ANA_REG_EN_OVRD to override the signal "adc_ana_reg_en". #1 ADC_ANA_REG_EN_OVRD Override value for ADC_ANA_REG_EN 9 1 read-write ADC_DIG_REG_EN_OVRD_EN Override control for ADC_DIG_REG_EN 10 1 read-write 0 Normal operation. #0 1 Use the state of ADC_DIG_REG_EN_OVRD to override the signal "adc_dig_reg_en". #1 ADC_DIG_REG_EN_OVRD Override value for ADC_DIG_REG_EN 11 1 read-write XTAL_PLL_REF_CLK_EN_OVRD_EN Override control for XTAL_PLL_REF_CLK_EN 12 1 read-write 0 Normal operation. #0 1 Use the state of XTAL_PLL_REF_CLK_EN_OVRD to override the signal "xtal_pll_ref_clk_en". #1 XTAL_PLL_REF_CLK_EN_OVRD Override value for XTAL_PLL_REF_CLK_EN 13 1 read-write XTAL_ADC_REF_CLK_EN_OVRD_EN Override control for XTAL_ADC_REF_CLK_EN 14 1 read-write 0 Normal operation. #0 1 Use the state of XTAL_ADC_REF_CLK_EN_OVRD to override the signal "xtal_adc_ref_clk_en". #1 XTAL_ADC_REF_CLK_EN_OVRD Override value for XTAL_ADC_REF_CLK_EN 15 1 read-write PLL_VCO_AUTOTUNE_EN_OVRD_EN Override control for PLL_VCO_AUTOTUNE_EN 16 1 read-write 0 Normal operation. #0 1 Use the state of PLL_VCO_AUTOTUNE_EN_OVRD to override the signal "pll_vco_autotune_en". #1 PLL_VCO_AUTOTUNE_EN_OVRD Override value for PLL_VCO_AUTOTUNE_EN 17 1 read-write PLL_CYCLE_SLIP_LD_EN_OVRD_EN Override control for PLL_CYCLE_SLIP_LD_EN 18 1 read-write 0 Normal operation. #0 1 Use the state of PLL_CYCLE_SLIP_LD_EN_OVRD to override the signal "pll_cycle_slip_ld_en". #1 PLL_CYCLE_SLIP_LD_EN_OVRD Override value for PLL_CYCLE_SLIP_LD_EN 19 1 read-write PLL_VCO_EN_OVRD_EN Override control for PLL_VCO_EN 20 1 read-write 0 Normal operation. #0 1 Use the state of PLL_VCO_EN_OVRD to override the signal "pll_vco_en". #1 PLL_VCO_EN_OVRD Override value for PLL_VCO_EN 21 1 read-write PLL_VCO_BUF_RX_EN_OVRD_EN Override control for PLL_VCO_BUF_RX_EN 22 1 read-write 0 Normal operation. #0 1 Use the state of PLL_VCO_BUF_RX_EN_OVRD to override the signal "pll_vco_buf_rx_en". #1 PLL_VCO_BUF_RX_EN_OVRD Override value for PLL_VCO_BUF_RX_EN 23 1 read-write PLL_VCO_BUF_TX_EN_OVRD_EN Override control for PLL_VCO_BUF_TX_EN 24 1 read-write 0 Normal operation. #0 1 Use the state of PLL_VCO_BUF_TX_EN_OVRD to override the signal "pll_vco_buf_tx_en". #1 PLL_VCO_BUF_TX_EN_OVRD Override value for PLL_VCO_BUF_TX_EN 25 1 read-write PLL_PA_BUF_EN_OVRD_EN Override control for PLL_PA_BUF_EN 26 1 read-write 0 Normal operation. #0 1 Use the state of PLL_PA_BUF_EN_OVRD to override the signal "pll_pa_buf_en". #1 PLL_PA_BUF_EN_OVRD Override value for PLL_PA_BUF_EN 27 1 read-write PLL_LDV_EN_OVRD_EN Override control for PLL_LDV_EN 28 1 read-write 0 Normal operation. #0 1 Use the state of PLL_LDV_EN_OVRD to override the signal "pll_ldv_en". #1 PLL_LDV_EN_OVRD Override value for PLL_LDV_EN 29 1 read-write PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN Override control for PLL_RX_LDV_RIPPLE_MUX_EN 30 1 read-write 0 Normal operation. #0 1 Use the state of PLL_RX_LDV_RIPPLE_MUX_EN_OVRD to override the signal "pll_rx_ldv_ripple_mux_en". #1 PLL_RX_LDV_RIPPLE_MUX_EN_OVRD Override value for PLL_RX_LDV_RIPPLE_MUX_EN 31 1 read-write TSM_OVRD1 TSM Override 1 0x2CC 32 read-write 0 0xFFFFFFFF PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN Override control for PLL_TX_LDV_RIPPLE_MUX_EN 0 1 read-write 0 Normal operation. #0 1 Use the state of PLL_TX_LDV_RIPPLE_MUX_EN_OVRD to override the signal "pll_tx_ldv_ripple_mux_en". #1 PLL_TX_LDV_RIPPLE_MUX_EN_OVRD Override value for PLL_TX_LDV_RIPPLE_MUX_EN 1 1 read-write PLL_FILTER_CHARGE_EN_OVRD_EN Override control for PLL_FILTER_CHARGE_EN 2 1 read-write 0 Normal operation. #0 1 Use the state of PLL_FILTER_CHARGE_EN_OVRD to override the signal "pll_filter_charge_en". #1 PLL_FILTER_CHARGE_EN_OVRD Override value for PLL_FILTER_CHARGE_EN 3 1 read-write PLL_PHDET_EN_OVRD_EN Override control for PLL_PHDET_EN 4 1 read-write 0 Normal operation. #0 1 Use the state of PLL_PHDET_EN_OVRD to override the signal "pll_phdet_en". #1 PLL_PHDET_EN_OVRD Override value for PLL_PHDET_EN 5 1 read-write QGEN25_EN_OVRD_EN Override control for QGEN25_EN 6 1 read-write 0 Normal operation. #0 1 Use the state of QGEN25_EN_OVRD to override the signal "qgen25_en". #1 QGEN25_EN_OVRD Override value for QGEN25_EN 7 1 read-write TX_EN_OVRD_EN Override control for TX_EN 8 1 read-write 0 Normal operation. #0 1 Use the state of TX_EN_OVRD to override the signal "tx_en". #1 TX_EN_OVRD Override value for TX_EN 9 1 read-write ADC_EN_OVRD_EN Override control for ADC_EN 10 1 read-write 0 Normal operation. #0 1 Use the state of ADC_EN_OVRD to override the signal "adc_en". #1 ADC_EN_OVRD Override value for ADC_EN 11 1 read-write ADC_BIAS_EN_OVRD_EN Override control for ADC_BIAS_EN 12 1 read-write 0 Normal operation. #0 1 Use the state of ADC_BIAS_EN_OVRD to override the signal "adc_bias_en". #1 ADC_BIAS_EN_OVRD Override value for ADC_BIAS_EN 13 1 read-write ADC_CLK_EN_OVRD_EN Override control for ADC_CLK_EN 14 1 read-write 0 Normal operation. #0 1 Use the state of ADC_CLK_EN_OVRD to override the signal "adc_clk_en". #1 ADC_CLK_EN_OVRD Override value for ADC_CLK_EN 15 1 read-write ADC_I_ADC_EN_OVRD_EN Override control for ADC_I_ADC_EN 16 1 read-write 0 Normal operation. #0 1 Use the state of ADC_I_ADC_EN_OVRD to override the signal "adc_i_adc_en". #1 ADC_I_ADC_EN_OVRD Override value for ADC_I_ADC_EN 17 1 read-write ADC_Q_ADC_EN_OVRD_EN Override control for ADC_Q_ADC_EN 18 1 read-write 0 Normal operation. #0 1 Use the state of ADC_Q_ADC_EN_OVRD to override the signal "adc_q_adc_en". #1 ADC_Q_ADC_EN_OVRD Override value for ADC_Q_ADC_EN 19 1 read-write ADC_DAC1_EN_OVRD_EN Override control for ADC_DAC1_EN 20 1 read-write 0 Normal operation. #0 1 Use the state of ADC_DAC1_EN_OVRD to override the signal "adc_dac1_en". #1 ADC_DAC1_EN_OVRD Override value for ADC_DAC1_EN 21 1 read-write ADC_DAC2_EN_OVRD_EN Override control for ADC_DAC2_EN 22 1 read-write 0 Normal operation. #0 1 Use the state of ADC_DAC2_EN_OVRD to override the signal "adc_dac2_en". #1 ADC_DAC2_EN_OVRD Override value for ADC_DAC2_EN 23 1 read-write ADC_RST_EN_OVRD_EN Override control for ADC_RST_EN 24 1 read-write 0 Normal operation. #0 1 Use the state of ADC_RST_EN_OVRD to override the signal "adc_rst_en". #1 ADC_RST_EN_OVRD Override value for ADC_RST_EN 25 1 read-write BBF_I_EN_OVRD_EN Override control for BBF_I_EN 26 1 read-write 0 Normal operation. #0 1 Use the state of BBF_I_EN_OVRD to override the signal "bbf_i_en". #1 BBF_I_EN_OVRD Override value for BBF_I_EN 27 1 read-write BBF_Q_EN_OVRD_EN Override control for BBF_Q_EN 28 1 read-write 0 Normal operation. #0 1 Use the state of BBF_Q_EN_OVRD to override the signal "bbf_q_en". #1 BBF_Q_EN_OVRD Override value for BBF_Q_EN 29 1 read-write BBF_PDET_EN_OVRD_EN Override control for BBF_PDET_EN 30 1 read-write 0 Normal operation. #0 1 Use the state of BBF_PDET_EN_OVRD to override the signal "bbf_pdet_en". #1 BBF_PDET_EN_OVRD Override value for BBF_PDET_EN 31 1 read-write TSM_OVRD2 TSM Override 2 0x2D0 32 read-write 0 0xFFFFFFFF BBF_DCOC_EN_OVRD_EN Override control for BBF_DCOC_EN 0 1 read-write 0 Normal operation. #0 1 Use the state of BBF_DCOC_EN_OVRD to override the signal "bbf_dcoc_en". #1 BBF_DCOC_EN_OVRD Override value for BBF_DCOC_EN 1 1 read-write TCA_EN_OVRD_EN Override control for TCA_EN 2 1 read-write 0 Normal operation. #0 1 Use the state of TCA_EN_OVRD to override the signal "tca_en". #1 TCA_EN_OVRD Override value for TCA_EN 3 1 read-write TZA_I_EN_OVRD_EN Override control for TZA_I_EN 4 1 read-write 0 Normal operation. #0 1 Use the state of TZA_I_EN_OVRD to override the signal "tza_i_en". #1 TZA_I_EN_OVRD Override value for TZA_I_EN 5 1 read-write TZA_Q_EN_OVRD_EN Override control for TZA_Q_EN 6 1 read-write 0 Normal operation. #0 1 Use the state of TZA_Q_EN_OVRD to override the signal "tza_q_en". #1 TZA_Q_EN_OVRD Override value for TZA_Q_EN 7 1 read-write TZA_PDET_EN_OVRD_EN Override control for TZA_PDET_EN 8 1 read-write 0 Normal operation. #0 1 Use the state of TZA_PDET_EN_OVRD to override the signal "tza_pdet_en". #1 TZA_PDET_EN_OVRD Override value for TZA_PDET_EN 9 1 read-write TZA_DCOC_EN_OVRD_EN Override control for TZA_DCOC_EN 10 1 read-write 0 Normal operation. #0 1 Use the state of TZA_DCOC_EN_OVRD to override the signal "tza_dcoc_en". #1 TZA_DCOC_EN_OVRD Override value for TZA_DCOC_EN 11 1 read-write PLL_DIG_EN_OVRD_EN Override control for PLL_DIG_EN 12 1 read-write 0 Normal operation. #0 1 Use the state of PLL_DIG_EN_OVRD to override the signal "pll_dig_en". #1 PLL_DIG_EN_OVRD Override value for PLL_DIG_EN 13 1 read-write TX_DIG_EN_OVRD_EN Override control for TX_DIG_EN 14 1 read-write 0 Normal operation. #0 1 Use the state of TX_DIG_EN_OVRD to override the signal "tx_dig_en". #1 TX_DIG_EN_OVRD Override value for TX_DIG_EN 15 1 read-write RX_DIG_EN_OVRD_EN Override control for RX_DIG_EN 16 1 read-write 0 Normal operation. #0 1 Use the state of RX_DIG_EN_OVRD to override the signal "rx_dig_en". #1 RX_DIG_EN_OVRD Override value for RX_DIG_EN 17 1 read-write RX_INIT_OVRD_EN Override control for RX_INIT 18 1 read-write 0 Normal operation. #0 1 Use the state of RX_INIT_OVRD to override the signal "rx_init". #1 RX_INIT_OVRD Override value for RX_INIT 19 1 read-write SIGMA_DELTA_EN_OVRD_EN Override control for SIGMA_DELTA_EN 20 1 read-write 0 Normal operation. #0 1 Use the state of SIGMA_DELTA_EN_OVRD to override the signal "sigma_delta_en". #1 SIGMA_DELTA_EN_OVRD Override value for SIGMA_DELTA_EN 21 1 read-write ZBDEM_RX_EN_OVRD_EN Override control for ZBDEM_RX_EN 22 1 read-write 0 Normal operation. #0 1 Use the state of ZBDEM_RX_EN_OVRD to override the signal "zbdem_rx_en". #1 ZBDEM_RX_EN_OVRD Override value for ZBDEM_RX_EN 23 1 read-write DCOC_EN_OVRD_EN Override control for DCOC_EN 24 1 read-write 0 Normal operation. #0 1 Use the state of DCOC_EN_OVRD to override the signal "dcoc_en". #1 DCOC_EN_OVRD Override value for DCOC_EN 25 1 read-write DCOC_INIT_OVRD_EN Override control for DCOC_INIT 26 1 read-write 0 Normal operation. #0 1 Use the state of DCOC_INIT_OVRD to override the signal "dcoc_init". #1 DCOC_INIT_OVRD Override value for DCOC_INIT 27 1 read-write FREQ_TARG_LD_EN_OVRD_EN Override control for FREQ_TARG_LD_EN 28 1 read-write 0 Normal operation. #0 1 Use the state of FREQ_TARG_LD_EN_OVRD to override the signal "freq_targ_ld_en". #1 FREQ_TARG_LD_EN_OVRD Override value for FREQ_TARG_LD_EN 29 1 read-write SAR_ADC_TRIG_EN_OVRD_EN Override control for SAR_ADC_TRIG_EN 30 1 read-write 0 Normal operation. #0 1 Use the state of SAR_ADC_TRIG_EN_OVRD to override the signal "sar_adc_trig_en". #1 SAR_ADC_TRIG_EN_OVRD Override value for SAR_ADC_TRIG_EN 31 1 read-write TSM_OVRD3 TSM Override 3 0x2D4 32 read-write 0 0xFFFFFFFF TSM_SPARE0_EN_OVRD_EN Override control for TSM_SPARE0_EN 0 1 read-write 0 Normal operation. #0 1 Use the state of TSM_SPARE0_EN_OVRD to override the signal "tsm_spare0_en". #1 TSM_SPARE0_EN_OVRD Override value for TSM_SPARE0_EN 1 1 read-write TSM_SPARE1_EN_OVRD_EN Override control for TSM_SPARE1_EN 2 1 read-write 0 Normal operation. #0 1 Use the state of TSM_SPARE1_EN_OVRD to override the signal "tsm_spare1_en". #1 TSM_SPARE1_EN_OVRD Override value for TSM_SPARE1_EN 3 1 read-write TSM_SPARE2_EN_OVRD_EN Override control for TSM_SPARE2_EN 4 1 read-write 0 Normal operation. #0 1 Use the state of TSM_SPARE2_EN_OVRD to override the signal "tsm_spare2_en". #1 TSM_SPARE2_EN_OVRD Override value for TSM_SPARE2_EN 5 1 read-write TSM_SPARE3_EN_OVRD_EN Override control for TSM_SPARE3_EN 6 1 read-write 0 Normal operation. #0 1 Use the state of TSM_SPARE3_EN_OVRD to override the signal "tsm_spare3_en". #1 TSM_SPARE3_EN_OVRD Override value for TSM_SPARE3_EN 7 1 read-write TX_MODE_OVRD_EN Override control for TX_MODE 8 1 read-write 0 Normal operation. #0 1 Use the state of TX_MODE_OVRD to override the signal "tx_mode". #1 TX_MODE_OVRD Override value for TX_MODE 9 1 read-write RX_MODE_OVRD_EN Override control for RX_MODE 10 1 read-write 0 Normal operation. #0 1 Use the state of RX_MODE_OVRD to override the signal "rx_mode". #1 RX_MODE_OVRD Override value for RX_MODE 11 1 read-write PA_POWER PA Power 0x2D8 32 read-write 0 0xFFFFFFFF PA_POWER PA Power 0 4 read-write PA_BIAS_TBL0 PA Bias Table 0 0x2DC 32 read-write 0 0xFFFFFFFF PA_BIAS0 PA_BIAS0 0 4 read-write PA_BIAS1 PA_BIAS1 8 4 read-write PA_BIAS2 PA_BIAS2 16 4 read-write PA_BIAS3 PA_BIAS3 24 4 read-write PA_BIAS_TBL1 PA Bias Table 1 0x2E0 32 read-write 0 0xFFFFFFFF PA_BIAS4 PA_BIAS4 0 4 read-write PA_BIAS5 PA_BIAS5 8 4 read-write PA_BIAS6 PA_BIAS6 16 4 read-write PA_BIAS7 PA_BIAS7 24 4 read-write RECYCLE_COUNT Recycle Count Register 0x2E4 32 read-write 0x826 0xFFFFFFFF RECYCLE_COUNT0 TSM RX Recycle Count 0 0 8 read-write RECYCLE_COUNT1 TSM RX Recycle Count 1 8 8 read-write TSM_TIMING00 TSM_TIMING00 0x2E8 32 read-write 0x65006A00 0xFFFFFFFF PLL_REG_EN_TX_HI Assertion time setting for PLL_REG_EN TX sequence. 0 8 read-write PLL_REG_EN_TX_LO Deassertion time setting for PLL_REG_EN signal or group TX sequence. 8 8 read-write PLL_REG_EN_RX_HI Assertion time setting for PLL_REG_EN signal or group RX sequence. 16 8 read-write PLL_REG_EN_RX_LO Deassertion time setting for PLL_REG_EN signal or group RX sequence. 24 8 read-write TSM_TIMING01 TSM_TIMING01 0x2EC 32 read-write 0x65006A00 0xFFFFFFFF PLL_VCO_REG_EN_TX_HI Assertion time setting for PLL_VCO_REG_EN TX sequence. 0 8 read-write PLL_VCO_REG_EN_TX_LO Deassertion time setting for PLL_VCO_REG_EN signal or group TX sequence. 8 8 read-write PLL_VCO_REG_EN_RX_HI Assertion time setting for PLL_VCO_REG_EN signal or group RX sequence. 16 8 read-write PLL_VCO_REG_EN_RX_LO Deassertion time setting for PLL_VCO_REG_EN signal or group RX sequence. 24 8 read-write TSM_TIMING02 TSM_TIMING02 0x2F0 32 read-write 0x65006A00 0xFFFFFFFF QGEN_REG_EN_TX_HI Assertion time setting for QGEN_REG_EN TX sequence. 0 8 read-write QGEN_REG_EN_TX_LO Deassertion time setting for QGEN_REG_EN signal or group TX sequence. 8 8 read-write QGEN_REG_EN_RX_HI Assertion time setting for QGEN_REG_EN signal or group RX sequence. 16 8 read-write QGEN_REG_EN_RX_LO Deassertion time setting for QGEN_REG_EN signal or group RX sequence. 24 8 read-write TSM_TIMING03 TSM_TIMING03 0x2F4 32 read-write 0x65006A00 0xFFFFFFFF TCA_TX_REG_EN_TX_HI Assertion time setting for TCA_TX_REG_EN TX sequence. 0 8 read-write TCA_TX_REG_EN_TX_LO Deassertion time setting for TCA_TX_REG_EN signal or group TX sequence. 8 8 read-write TCA_TX_REG_EN_RX_HI Assertion time setting for TCA_TX_REG_EN signal or group RX sequence. 16 8 read-write TCA_TX_REG_EN_RX_LO Deassertion time setting for TCA_TX_REG_EN signal or group RX sequence. 24 8 read-write TSM_TIMING04 TSM_TIMING04 0x2F8 32 read-write 0x6500FFFF 0xFFFFFFFF ADC_REG_EN_RX_HI Assertion time setting for ADC_REG_EN signal or group RX sequence. 16 8 read-write ADC_REG_EN_RX_LO Deassertion time setting for ADC_REG_EN signal or group RX sequence. 24 8 read-write TSM_TIMING05 TSM_TIMING05 0x2FC 32 read-write 0x650B6A3F 0xFFFFFFFF PLL_REF_CLK_EN_TX_HI Assertion time setting for PLL_REF_CLK_EN TX sequence. 0 8 read-write PLL_REF_CLK_EN_TX_LO Deassertion time setting for PLL_REF_CLK_EN signal or group TX sequence. 8 8 read-write PLL_REF_CLK_EN_RX_HI Assertion time setting for PLL_REF_CLK_EN signal or group RX sequence. 16 8 read-write PLL_REF_CLK_EN_RX_LO Deassertion time setting for PLL_REF_CLK_EN signal or group RX sequence. 24 8 read-write TSM_TIMING06 TSM_TIMING06 0x300 32 read-write 0x651AFFFF 0xFFFFFFFF ADC_CLK_EN_RX_HI Assertion time setting for ADC_CLK_EN signal or group RX sequence. 16 8 read-write ADC_CLK_EN_RX_LO Deassertion time setting for ADC_CLK_EN signal or group RX sequence. 24 8 read-write TSM_TIMING07 TSM_TIMING07 0x304 32 read-write 0x1A004E00 0xFFFFFFFF PLL_VCO_AUTOTUNE_EN_TX_HI Assertion time setting for PLL_VCO_AUTOTUNE_EN TX sequence. 0 8 read-write PLL_VCO_AUTOTUNE_EN_TX_LO Deassertion time setting for PLL_VCO_AUTOTUNE_EN signal or group TX sequence. 8 8 read-write PLL_VCO_AUTOTUNE_EN_RX_HI Assertion time setting for PLL_VCO_AUTOTUNE_EN signal or group RX sequence. 16 8 read-write PLL_VCO_AUTOTUNE_EN_RX_LO Deassertion time setting for PLL_VCO_AUTOTUNE_EN signal or group RX sequence. 24 8 read-write TSM_TIMING08 TSM_TIMING08 0x308 32 read-write 0x65336867 0xFFFFFFFF PLL_CYCLE_SLIP_LD_EN_TX_HI Assertion time setting for PLL_CYCLE_SLIP_LD_EN TX sequence. 0 8 read-write PLL_CYCLE_SLIP_LD_EN_TX_LO Deassertion time setting for PLL_CYCLE_SLIP_LD_EN signal or group TX sequence. 8 8 read-write PLL_CYCLE_SLIP_LD_EN_RX_HI Assertion time setting for PLL_CYCLE_SLIP_LD_EN signal or group RX sequence. 16 8 read-write PLL_CYCLE_SLIP_LD_EN_RX_LO Deassertion time setting for PLL_CYCLE_SLIP_LD_EN signal or group RX sequence. 24 8 read-write TSM_TIMING09 TSM_TIMING09 0x30C 32 read-write 0x65056A05 0xFFFFFFFF PLL_VCO_EN_TX_HI Assertion time setting for PLL_VCO_EN TX sequence. 0 8 read-write PLL_VCO_EN_TX_LO Deassertion time setting for PLL_VCO_EN signal or group TX sequence. 8 8 read-write PLL_VCO_EN_RX_HI Assertion time setting for PLL_VCO_EN signal or group RX sequence. 16 8 read-write PLL_VCO_EN_RX_LO Deassertion time setting for PLL_VCO_EN signal or group RX sequence. 24 8 read-write TSM_TIMING10 TSM_TIMING10 0x310 32 read-write 0x6509FFFF 0xFFFFFFFF PLL_VCO_BUF_RX_EN_RX_HI Assertion time setting for PLL_VCO_BUF_RX_EN signal or group RX sequence. 16 8 read-write PLL_VCO_BUF_RX_EN_RX_LO Deassertion time setting for PLL_VCO_BUF_RX_EN signal or group RX sequence. 24 8 read-write TSM_TIMING11 TSM_TIMING11 0x314 32 read-write 0xFFFF6A09 0xFFFFFFFF PLL_VCO_BUF_TX_EN_TX_HI Assertion time setting for PLL_VCO_BUF_TX_EN TX sequence. 0 8 read-write PLL_VCO_BUF_TX_EN_TX_LO Deassertion time setting for PLL_VCO_BUF_TX_EN signal or group TX sequence. 8 8 read-write TSM_TIMING12 TSM_TIMING12 0x318 32 read-write 0xFFFF6A64 0xFFFFFFFF PLL_PA_BUF_EN_TX_HI Assertion time setting for PLL_PA_BUF_EN TX sequence. 0 8 read-write PLL_PA_BUF_EN_TX_LO Deassertion time setting for PLL_PA_BUF_EN signal or group TX sequence. 8 8 read-write TSM_TIMING13 TSM_TIMING13 0x31C 32 read-write 0x651A6A4E 0xFFFFFFFF PLL_LDV_EN_TX_HI Assertion time setting for PLL_LDV_EN TX sequence. 0 8 read-write PLL_LDV_EN_TX_LO Deassertion time setting for PLL_LDV_EN signal or group TX sequence. 8 8 read-write PLL_LDV_EN_RX_HI Assertion time setting for PLL_LDV_EN signal or group RX sequence. 16 8 read-write PLL_LDV_EN_RX_LO Deassertion time setting for PLL_LDV_EN signal or group RX sequence. 24 8 read-write TSM_TIMING14 TSM_TIMING14 0x320 32 read-write 0x650AFFFF 0xFFFFFFFF PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI Assertion time setting for PLL_RX_LDV_RIPPLE_MUX_EN signal or group RX sequence. 16 8 read-write PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO Deassertion time setting for PLL_RX_LDV_RIPPLE_MUX_EN signal or group RX sequence. 24 8 read-write TSM_TIMING15 TSM_TIMING15 0x324 32 read-write 0xFFFF6A0A 0xFFFFFFFF PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI Assertion time setting for PLL_TX_LDV_RIPPLE_MUX_EN TX sequence. 0 8 read-write PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO Deassertion time setting for PLL_TX_LDV_RIPPLE_MUX_EN signal or group TX sequence. 8 8 read-write TSM_TIMING16 TSM_TIMING16 0x328 32 read-write 0x1A104E44 0xFFFFFFFF PLL_FILTER_CHARGE_EN_TX_HI Assertion time setting for PLL_FILTER_CHARGE_EN TX sequence. 0 8 read-write PLL_FILTER_CHARGE_EN_TX_LO Deassertion time setting for PLL_FILTER_CHARGE_EN signal or group TX sequence. 8 8 read-write PLL_FILTER_CHARGE_EN_RX_HI Assertion time setting for PLL_FILTER_CHARGE_EN signal or group RX sequence. 16 8 read-write PLL_FILTER_CHARGE_EN_RX_LO Deassertion time setting for PLL_FILTER_CHARGE_EN signal or group RX sequence. 24 8 read-write TSM_TIMING17 TSM_TIMING17 0x32C 32 read-write 0x65106A44 0xFFFFFFFF PLL_PHDET_EN_TX_HI Assertion time setting for PLL_PHDET_EN TX sequence. 0 8 read-write PLL_PHDET_EN_TX_LO Deassertion time setting for PLL_PHDET_EN signal or group TX sequence. 8 8 read-write PLL_PHDET_EN_RX_HI Assertion time setting for PLL_PHDET_EN signal or group RX sequence. 16 8 read-write PLL_PHDET_EN_RX_LO Deassertion time setting for PLL_PHDET_EN signal or group RX sequence. 24 8 read-write TSM_TIMING18 TSM_TIMING18 0x330 32 read-write 0x6505FFFF 0xFFFFFFFF QGEN25_EN_RX_HI Assertion time setting for QGEN25_EN signal or group RX sequence. 16 8 read-write QGEN25_EN_RX_LO Deassertion time setting for QGEN25_EN signal or group RX sequence. 24 8 read-write TSM_TIMING19 TSM_TIMING19 0x334 32 read-write 0xFFFF6864 0xFFFFFFFF TX_EN_TX_HI Assertion time setting for TX_EN TX sequence. 0 8 read-write TX_EN_TX_LO Deassertion time setting for TX_EN signal or group TX sequence. 8 8 read-write TSM_TIMING20 TSM_TIMING20 0x338 32 read-write 0x651AFFFF 0xFFFFFFFF ADC_EN_RX_HI Assertion time setting for ADC_EN signal or group RX sequence. 16 8 read-write ADC_EN_RX_LO Deassertion time setting for ADC_EN signal or group RX sequence. 24 8 read-write TSM_TIMING21 TSM_TIMING21 0x33C 32 read-write 0x651AFFFF 0xFFFFFFFF ADC_I_Q_EN_RX_HI Assertion time setting for ADC_I_Q_EN signal or group RX sequence. 16 8 read-write ADC_I_Q_EN_RX_LO Deassertion time setting for ADC_I_Q_EN signal or group RX sequence. 24 8 read-write TSM_TIMING22 TSM_TIMING22 0x340 32 read-write 0x651AFFFF 0xFFFFFFFF ADC_DAC_EN_RX_HI Assertion time setting for ADC_DAC_EN signal or group RX sequence. 16 8 read-write ADC_DAC_EN_RX_LO Deassertion time setting for ADC_DAC_EN signal or group RX sequence. 24 8 read-write TSM_TIMING23 TSM_TIMING23 0x344 32 read-write 0x651AFFFF 0xFFFFFFFF ADC_RST_EN_RX_HI Assertion time setting for ADC_RST_EN signal or group RX sequence. 16 8 read-write ADC_RST_EN_RX_LO Deassertion time setting for ADC_RST_EN signal or group RX sequence. 24 8 read-write TSM_TIMING24 TSM_TIMING24 0x348 32 read-write 0x6518FFFF 0xFFFFFFFF BBF_EN_RX_HI Assertion time setting for BBF_EN signal or group RX sequence. 16 8 read-write BBF_EN_RX_LO Deassertion time setting for BBF_EN signal or group RX sequence. 24 8 read-write TSM_TIMING25 TSM_TIMING25 0x34C 32 read-write 0x6518FFFF 0xFFFFFFFF TCA_EN_RX_HI Assertion time setting for TCA_EN signal or group RX sequence. 16 8 read-write TCA_EN_RX_LO Deassertion time setting for TCA_EN signal or group RX sequence. 24 8 read-write TSM_TIMING26 TSM_TIMING26 0x350 32 read-write 0x65096A09 0xFFFFFFFF PLL_DIG_EN_TX_HI Assertion time setting for PLL_DIG_EN TX sequence. 0 8 read-write PLL_DIG_EN_TX_LO Deassertion time setting for PLL_DIG_EN signal or group TX sequence. 8 8 read-write PLL_DIG_EN_RX_HI Assertion time setting for PLL_DIG_EN signal or group RX sequence. 16 8 read-write PLL_DIG_EN_RX_LO Deassertion time setting for PLL_DIG_EN signal or group RX sequence. 24 8 read-write TSM_TIMING27 TSM_TIMING27 0x354 32 read-write 0xFFFF6A67 0xFFFFFFFF TX_DIG_EN_TX_HI Assertion time setting for TX_DIG_EN TX sequence. 0 8 read-write TX_DIG_EN_TX_LO Deassertion time setting for TX_DIG_EN signal or group TX sequence. 8 8 read-write TSM_TIMING28 TSM_TIMING28 0x358 32 read-write 0x6562FFFF 0xFFFFFFFF RX_DIG_EN_RX_HI Assertion time setting for RX_DIG_EN signal or group RX sequence. 16 8 read-write RX_DIG_EN_RX_LO Deassertion time setting for RX_DIG_EN signal or group RX sequence. 24 8 read-write TSM_TIMING29 TSM_TIMING29 0x35C 32 read-write 0x6362FFFF 0xFFFFFFFF RX_INIT_RX_HI Assertion time setting for RX_INIT signal or group RX sequence. 16 8 read-write RX_INIT_RX_LO Deassertion time setting for RX_INIT signal or group RX sequence. 24 8 read-write TSM_TIMING30 TSM_TIMING30 0x360 32 read-write 0x65106A44 0xFFFFFFFF SIGMA_DELTA_EN_TX_HI Assertion time setting for SIGMA_DELTA_EN TX sequence. 0 8 read-write SIGMA_DELTA_EN_TX_LO Deassertion time setting for SIGMA_DELTA_EN signal or group TX sequence. 8 8 read-write SIGMA_DELTA_EN_RX_HI Assertion time setting for SIGMA_DELTA_EN signal or group RX sequence. 16 8 read-write SIGMA_DELTA_EN_RX_LO Deassertion time setting for SIGMA_DELTA_EN signal or group RX sequence. 24 8 read-write TSM_TIMING31 TSM_TIMING31 0x364 32 read-write 0x6562FFFF 0xFFFFFFFF ZBDEM_RX_EN_RX_HI Assertion time setting for ZBDEM_RX_EN signal or group RX sequence. 16 8 read-write ZBDEM_RX_EN_RX_LO Deassertion time setting for ZBDEM_RX_EN signal or group RX sequence. 24 8 read-write TSM_TIMING32 TSM_TIMING32 0x368 32 read-write 0x6526FFFF 0xFFFFFFFF DCOC_EN_RX_HI Assertion time setting for DCOC_EN signal or group RX sequence. 16 8 read-write DCOC_EN_RX_LO Deassertion time setting for DCOC_EN signal or group RX sequence. 24 8 read-write TSM_TIMING33 TSM_TIMING33 0x36C 32 read-write 0x2726FFFF 0xFFFFFFFF DCOC_INIT_RX_HI Assertion time setting for DCOC_INIT signal or group RX sequence. 16 8 read-write DCOC_INIT_RX_LO Deassertion time setting for DCOC_INIT signal or group RX sequence. 24 8 read-write TSM_TIMING34 TSM_TIMING34 0x370 32 read-write 0x65336865 0xFFFFFFFF FREQ_TARG_LD_EN_TX_HI Assertion time setting for FREQ_TARG_LD_EN TX sequence. 0 8 read-write FREQ_TARG_LD_EN_TX_LO Deassertion time setting for FREQ_TARG_LD_EN signal or group TX sequence. 8 8 read-write FREQ_TARG_LD_EN_RX_HI Assertion time setting for FREQ_TARG_LD_EN signal or group RX sequence. 16 8 read-write FREQ_TARG_LD_EN_RX_LO Deassertion time setting for FREQ_TARG_LD_EN signal or group RX sequence. 24 8 read-write TSM_TIMING35 TSM_TIMING35 0x374 32 read-write 0xFFFFFFFF 0xFFFFFFFF SAR_ADC_TRIG_EN_TX_HI Assertion time setting for SAR_ADC_TRIG_EN TX sequence. 0 8 read-write SAR_ADC_TRIG_EN_TX_LO Deassertion time setting for SAR_ADC_TRIG_EN signal or group TX sequence. 8 8 read-write SAR_ADC_TRIG_EN_RX_HI Assertion time setting for SAR_ADC_TRIG_EN signal or group RX sequence. 16 8 read-write SAR_ADC_TRIG_EN_RX_LO Deassertion time setting for SAR_ADC_TRIG_EN signal or group RX sequence. 24 8 read-write TSM_TIMING36 TSM_TIMING36 0x378 32 read-write 0xFFFFFFFF 0xFFFFFFFF TSM_SPARE0_EN_TX_HI Assertion time setting for TSM_SPARE0_EN TX sequence. 0 8 read-write TSM_SPARE0_EN_TX_LO Deassertion time setting for TSM_SPARE0_EN signal or group TX sequence. 8 8 read-write TSM_SPARE0_EN_RX_HI Assertion time setting for TSM_SPARE0_EN signal or group RX sequence. 16 8 read-write TSM_SPARE0_EN_RX_LO Deassertion time setting for TSM_SPARE0_EN signal or group RX sequence. 24 8 read-write TSM_TIMING37 TSM_TIMING37 0x37C 32 read-write 0xFFFFFFFF 0xFFFFFFFF TSM_SPARE1_EN_TX_HI Assertion time setting for TSM_SPARE1_EN TX sequence. 0 8 read-write TSM_SPARE1_EN_TX_LO Deassertion time setting for TSM_SPARE1_EN signal or group TX sequence. 8 8 read-write TSM_SPARE1_EN_RX_HI Assertion time setting for TSM_SPARE1_EN signal or group RX sequence. 16 8 read-write TSM_SPARE1_EN_RX_LO Deassertion time setting for TSM_SPARE1_EN signal or group RX sequence. 24 8 read-write TSM_TIMING38 TSM_TIMING38 0x380 32 read-write 0xFFFFFFFF 0xFFFFFFFF TSM_SPARE2_EN_TX_HI Assertion time setting for TSM_SPARE2_EN TX sequence. 0 8 read-write TSM_SPARE2_EN_TX_LO Deassertion time setting for TSM_SPARE2_EN signal or group TX sequence. 8 8 read-write TSM_SPARE2_EN_RX_HI Assertion time setting for TSM_SPARE2_EN signal or group RX sequence. 16 8 read-write TSM_SPARE2_EN_RX_LO Deassertion time setting for TSM_SPARE2_EN signal or group RX sequence. 24 8 read-write TSM_TIMING39 TSM_TIMING39 0x384 32 read-write 0xFFFFFFFF 0xFFFFFFFF TSM_SPARE3_EN_TX_HI Assertion time setting for TSM_SPARE3_EN TX sequence. 0 8 read-write TSM_SPARE3_EN_TX_LO Deassertion time setting for TSM_SPARE3_EN signal or group TX sequence. 8 8 read-write TSM_SPARE3_EN_RX_HI Assertion time setting for TSM_SPARE3_EN signal or group RX sequence. 16 8 read-write TSM_SPARE3_EN_RX_LO Deassertion time setting for TSM_SPARE3_EN signal or group RX sequence. 24 8 read-write TSM_TIMING40 TSM_TIMING40 0x388 32 read-write 0xFFFFFFFF 0xFFFFFFFF GPIO0_TRIG_EN_TX_HI Assertion time setting for GPIO0_TRIG_EN TX sequence. 0 8 read-write GPIO0_TRIG_EN_TX_LO Deassertion time setting for GPIO0_TRIG_EN signal or group TX sequence. 8 8 read-write GPIO0_TRIG_EN_RX_HI Assertion time setting for GPIO0_TRIG_EN signal or group RX sequence. 16 8 read-write GPIO0_TRIG_EN_RX_LO Deassertion time setting for GPIO0_TRIG_EN signal or group RX sequence. 24 8 read-write TSM_TIMING41 TSM_TIMING41 0x38C 32 read-write 0xFFFFFFFF 0xFFFFFFFF GPIO1_TRIG_EN_TX_HI Assertion time setting for GPIO1_TRIG_EN TX sequence. 0 8 read-write GPIO1_TRIG_EN_TX_LO Deassertion time setting for GPIO1_TRIG_EN signal or group TX sequence. 8 8 read-write GPIO1_TRIG_EN_RX_HI Assertion time setting for GPIO1_TRIG_EN signal or group RX sequence. 16 8 read-write GPIO1_TRIG_EN_RX_LO Deassertion time setting for GPIO1_TRIG_EN signal or group RX sequence. 24 8 read-write TSM_TIMING42 TSM_TIMING42 0x390 32 read-write 0xFFFFFFFF 0xFFFFFFFF GPIO2_TRIG_EN_TX_HI Assertion time setting for GPIO2_TRIG_EN TX sequence. 0 8 read-write GPIO2_TRIG_EN_TX_LO Deassertion time setting for GPIO2_TRIG_EN signal or group TX sequence. 8 8 read-write GPIO2_TRIG_EN_RX_HI Assertion time setting for GPIO2_TRIG_EN signal or group RX sequence. 16 8 read-write GPIO2_TRIG_EN_RX_LO Deassertion time setting for GPIO2_TRIG_EN signal or group RX sequence. 24 8 read-write TSM_TIMING43 TSM_TIMING43 0x394 32 read-write 0xFFFFFFFF 0xFFFFFFFF GPIO3_TRIG_EN_TX_HI Assertion time setting for GPIO3_TRIG_EN TX sequence. 0 8 read-write GPIO3_TRIG_EN_TX_LO Deassertion time setting for GPIO3_TRIG_EN signal or group TX sequence. 8 8 read-write GPIO3_TRIG_EN_RX_HI Assertion time setting for GPIO3_TRIG_EN signal or group RX sequence. 16 8 read-write GPIO3_TRIG_EN_RX_LO Deassertion time setting for GPIO3_TRIG_EN signal or group RX sequence. 24 8 read-write CORR_CTRL CORR_CTRL 0x3C0 32 read-write 0x482 0xFFFFFFFF CORR_VT CORR_VT 0 8 read-write CORR_NVAL CORR_NVAL 8 3 read-write MAX_CORR_EN MAX_CORR_EN 11 1 read-write RX_MAX_CORR RX_MAX_CORR 16 8 read-only RX_MAX_PREAMBLE RX_MAX_PREAMBLE 24 8 read-only PN_TYPE PN_TYPE 0x3C4 32 read-write 0x1 0xFFFFFFFF PN_TYPE PN_TYPE 0 1 read-write TX_INV TX_INV 1 1 read-write PN_CODE PN_CODE 0x3C8 32 read-write 0x744AC39B 0xFFFFFFFF PN_LSB PN_LSB 0 16 read-write PN_MSB PN_MSB 16 16 read-write SYNC_CTRL Sync Control 0x3CC 32 read-write 0x8 0xFFFFFFFF SYNC_PER Symbol Sync Tracking Period 0 3 read-write TRACK_ENABLE TRACK_ENABLE 3 1 read-write 0 symbol timing synchronization tracking disabled in Rx frontend #0 1 symbol timing synchronization tracking enabled in Rx frontend (default) #1 SNF_THR SNF_THR 0x3D0 32 read-write 0 0xFFFFFFFF SNF_THR SNIFF Mode Threshold 0 8 read-write FAD_THR FAD_THR 0x3D4 32 read-write 0x82 0xFFFFFFFF FAD_THR FAD_THR 0 8 read-write ZBDEM_AFC ZBDEM_AFC 0x3D8 32 read-write 0x1 0xFFFFFFFF AFC_EN AFC_EN 0 1 read-write DCD_EN DCD Mode Enable 1 1 read-write 0 NCD Mode (default) #0 1 DCD Mode #1 AFC_OUT AFC_OUT 8 5 read-only LPPS_CTRL LPPS Control Register 0x3DC 32 read-write 0 0xFFFFFFFF LPPS_ENABLE LPPS Mode Enable 0 1 read-write 0 LPPS mode disabled #0 1 LPPS mode enabled #1 LPPS_QGEN25_ALLOW LPPS_QGEN25_ALLOW 1 1 read-write 0 Disallow TSM output qgen25_en to be duty-cycled during LPPS #0 1 Allow TSM output qgen25_en to be duty-cycled during LPPS #1 LPPS_ADC_ALLOW LPPS_ADC_ALLOW 2 1 read-write 0 Disallow ADC-related TSM outputs {adc_en, adc_bias_en} to be duty-cycled during LPPS. #0 1 Allow ADC-related TSM outputs {adc_en, adc_bias_en} to be duty-cycled during LPPS. #1 LPPS_ADC_CLK_ALLOW LPPS_ADC_CLK_ALLOW 3 1 read-write 0 Disallow ADC-related TSM outputs {xtal_adc_ref_clk_en, adc_clk_en} to be duty-cycled during LPPS. #0 1 Allow ADC_CLK-related TSM outputs {xtal_adc_ref_clk_en, adc_clk_en} to be duty-cycled during LPPS. #1 LPPS_ADC_I_Q_ALLOW LPPS_ADC_I_Q_ALLOW 4 1 read-write 0 Disallow ADC_I/Q-related TSM outputs {adc_I_adc_en, adc_Q_adc_en} to be duty-cycled during LPPS. #0 1 Allow ADC_I/Q-related TSM outputs {adc_I_adc_en, adc_Q_adc_en} to be duty-cycled during LPPS. #1 LPPS_ADC_DAC_ALLOW LPPS_ADC_DAC_ALLOW 5 1 read-write 0 Disallow ADC_DAC-related TSM outputs {adc_dac1_en, adc_dac2_en} to be duty-cycled during LPPS. #0 1 Allow ADC_DAC-related TSM outputs {adc_dac1_en, adc_dac2_en} to be duty-cycled during LPPS. #1 LPPS_BBF_ALLOW LPPS_BBF_ALLOW 6 1 read-write 0 Disallow BBF-related TSM outputs {bbf_i_en, bbf_q_en, bbf_pdet_en, bbf_dcoc_en} to be duty-cycled during LPPS. #0 1 Allow BBF-related TSM outputs {bbf_i_en, bbf_q_en, bbf_pdet_en, bbf_dcoc_en} to be duty-cycled during LPPS. #1 LPPS_TCA_ALLOW LPPS_TCA_ALLOW 7 1 read-write 0 Disallow TCA-related TSM outputs {tca_en, tza_i_en, tza_q_en, tza_pdet_en, tza_dcoc_en} to be duty-cycled during LPPS. #0 1 Allow TCA-related TSM outputs {tca_en, tza_i_en, tza_q_en, tza_pdet_en, tza_dcoc_en} to be duty-cycled during LPPS. #1 ADC_CTRL ADC Control 0x400 32 read-write 0xFFFF0001 0xFFFFFFFF ADC_32MHZ_SEL ADC 32MHZ Clock Select 0 1 read-write ADC_2X_CLK_SEL ADC_2X_CLK_SEL 2 1 read-write ADC_DITHER_ON ADC Dither On 9 1 read-write ADC_TEST_ON ADC Test On 10 1 read-write ADC_COMP_ON ADC Comparator Enable 16 16 read-write ADC_TUNE ADC Tuning 0x404 32 read-write 0x880033 0xFFFFFFFF ADC_R1_TUNE ADC_R1_TUNE 0 3 read-write ADC_R2_TUNE ADC_R2_TUNE 4 3 read-write ADC_C1_TUNE ADC_C1_TUNE 16 4 read-write ADC_C2_TUNE ADC_C2_TUNE 20 4 read-write ADC_ADJ ADC Adjustment 0x408 32 read-write 0x43033033 0xFFFFFFFF ADC_IB_OPAMP1_ADJ ADC_IB_OPAMP1_ADJ 0 3 read-write ADC_IB_OPAMP2_ADJ ADC_IB_OPAMP2_ADJ 4 3 read-write ADC_IB_DAC1_ADJ ADC_IB_DAC1_ADJ 12 3 read-write ADC_IB_DAC2_ADJ ADC_IB_DAC2_ADJ 16 3 read-write ADC_IB_FLSH_ADJ ADC_IB_FLSH_ADJ 24 3 read-write ADC_FLSH_RES_ADJ ADC_FLSH_RES_ADJ 28 3 read-write ADC_REGS ADC Regulators 0x40C 32 read-write 0 0xFFFFFFFF ADC_ANA_REG_SUPPLY ADC_ANA_REG_SUPPLY 0 4 read-write 0 1.2V #0000 1 1.05V #0001 10 1.075V #0010 11 1.1V #0011 100 1.125V #0100 101 1.15V #0101 110 1.175V #0110 111 1.2V #0111 1000 1.225V #1000 1001 1.25V #1001 1100 1.325V #1100 1101 1.35V #1101 1110 1.375V #1110 1111 1.4V #1111 ADC_REG_DIG_SUPPLY ADC_REG_DIG_SUPPLY 4 4 read-write 0 1.2V #0000 1 1.05V #0001 10 1.075V #0010 11 1.1V #0011 100 1.125V #0100 101 1.15V #0101 110 1.175V #0110 111 1.2V #0111 1000 1.225V #1000 1001 1.25V #1001 1100 1.325V #1100 1101 1.35V #1101 1110 1.375V #1110 1111 1.4V #1111 ADC_ANA_REG_BYPASS_ON ADC_ANA_REG_BYPASS_ON 8 1 read-write ADC_DIG_REG_BYPASS_ON ADC_DIG_REG_BYPASS_ON 9 1 read-write ADC_VCMREF_BYPASS_ON ADC_VCMREF_BYPASS_ON 15 1 read-write ADC_INTERNAL_IREF_BYPASS_ON ADC_INTERNAL_IREF_BYPASS_ON 17 1 read-write ADC_TRIMS ADC Regulator Trims 0x410 32 read-write 0x444 0xFFFFFFFF ADC_IREF_OPAMPS_RES_TRIM ADC_IREF_OPAMPS_RES_TRIM 0 3 read-write ADC_IREF_FLSH_RES_TRIM ADC_IREF_FLSH_RES_TRIM 4 3 read-write ADC_VCM_TRIM ADC_VCM_TRIM 8 3 read-write ADC_TEST_CTRL ADC Test Control 0x414 32 read-write 0 0xFFFFFFFF ADC_ATST_SEL ADC Analog Test Selection 0 5 read-write 0 Inject 5uA refrence current on ATST0 ,Inject 0.6V reference voltage on ATST1 #00000 1 Monitor Flash refrence currents on ATST3 #00001 10 Monitor DAC refrence current on ATST0,Monitor mirrored reference current at ATST1,Monitor operational amplifiers reference current at ATST2, Monitor buffered 0.6V reference voltage used for opamp1 common mode at ATST3 #00010 11 Monitored buffered 0.6V reference voltrage used for opamp2 common mode at ATST0 monitor buffered 0.6V reference voltage used for opam3 comon mode at ATST2. However opamp3 does not exisit in this silicon but there is still a buffered reference available. #00011 ADC_DIG_REG_ATST_SEL ADC_DIG_REG_ATST_SEL 8 2 read-write ADC_ANA_REG_ATST_SEL ADC_ANA_REG_ATST_SEL 12 2 read-write DCOC_ALPHA_RADIUS_GS_IDX Alpha-R Scaling 24 3 read-write 000 1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 ADC_SPARE3 ADC_SPARE3 27 1 read-write BBF_CTRL Baseband Filter Control 0x420 32 read-write 0x173 0xFFFFFFFF BBF_CAP_TUNE BBF_CAP_TUNE 0 4 read-write BBF_RES_TUNE2 BBF_RES_TUNE2 4 4 read-write BBF_CUR_CNTL BBF_CUR_CNTL 8 1 read-write 0 Low current setting. #0 1 High current setting. #1 BBF_DCOC_ON BBF_DCOC_ON 9 1 read-write BBF_TMUX_ON BBF_TMUX_ON 11 1 read-write DCOC_ALPHAC_SCALE_GS_IDX DCOC Alpha-C Scaling 12 2 read-write 00 1/2 #00 01 1/4 #01 10 1/8 #10 11 1/16 #11 BBF_SPARE_3_2 BBF_SPARE_3_2 14 2 read-write RX_ANA_CTRL RX Analog Control 0x42C 32 read-write 0 0xFFFFFFFF RX_ATST_SEL RX_ATST_SEL 0 4 read-write IQMC_DC_GAIN_ADJ_EN IQMC_DC_GAIN_ADJ_EN 4 1 read-write LNM_SPARE_3_2_1 LNM_SPARE_3_2_1 5 3 read-write XTAL_CTRL Crystal Oscillator Control Register 1 0x434 32 read-write 0xACAC177 0x7FFFFFFF XTAL_TRIM XTAL Trim 0 8 read-write XTAL_GM XTAL_GM 8 5 read-write XTAL_BYPASS XTAL Bypass 13 1 read-write XTAL_READY_COUNT_SEL XTAL Ready Count Select 14 2 read-write 00 1024 clock cycles #00 01 2048 clock cycles #01 10 4096 clock cycles #10 11 8192 clock cycles #11 XTAL_COMP_BIAS_LO XTAL_COMP_BIAS (Low) 16 5 read-write XTAL_ALC_START_512U XTAL_ALC_START_512U 22 1 read-write 0 Start XTAL ALC at 256usec #0 1 Start XTAL ALC at 512usec #1 XTAL_ALC_ON XTAL_ALC_ON 23 1 read-write XTAL_COMP_BIAS_HI XTAL_COMP_BIAS (High) 24 5 read-write XTAL_READY XTAL Ready Indicator 31 1 read-only XTAL_CTRL2 Crystal Oscillator Control Register 2 0x438 32 read-write 0x1000 0xFFFFFFFF XTAL_REG_SUPPLY XTAL_REG_SUPPLY 0 4 read-write 0 1.2V #0000 1 1.05V #0001 10 1.075V #0010 11 1.1V #0011 100 1.125V #0100 101 1.15V #0101 110 1.175V #0110 111 1.2V #0111 1000 1.225V #1000 1001 1.25V #1001 1100 1.325V #1100 1101 1.35V #1101 1110 1.375V #1110 1111 1.4V #1111 XTAL_REG_BYPASS_ON XTAL_REG_BYPASS_ON 4 1 read-write XTAL_REG_ON_OVRD_ON XTAL_REG_ON_OVRD_ON 8 1 read-write XTAL_REG_ON_OVRD XTAL_REG_ON_OVRD 9 1 read-write XTAL_ON_OVRD_ON XTAL_ON_OVRD_ON 10 1 read-write XTAL_ON_OVRD XTAL_ON_OVRD 11 1 read-write XTAL_DIG_CLK_OUT_ON XTAL_DIG_CLK_OUT_ON 12 1 read-write XTAL_REG_ATST_SEL XTAL_REG_ATST_SEL 16 2 read-write XTAL_ATST_SEL XTAL_ATST_SEL 24 2 read-write XTAL_ATST_ON XTAL_ATST_ON 26 1 read-write XTAL_SPARE XTAL_SPARE 28 4 read-write BGAP_CTRL Bandgap Control 0x43C 32 read-write 0x87 0xFFFFFFFF BGAP_CURRENT_TRIM BGAP_CURRENT_TRIM 0 4 read-write BGAP_VOLTAGE_TRIM BGAP_VOLTAGE_TRIM 4 4 read-write BGAP_ATST_SEL BGAP_ATST_SEL 8 4 read-write BGAP_ATST_ON BGAP_ATST_ON 12 1 read-write PLL_CTRL PLL Control Register 0x444 32 read-write 0x23 0xFFFFFFFF PLL_VCO_BIAS PLL VCO Bias Control 0 3 read-write PLL_LFILT_CNTL PLL Loop Filter Control 4 3 read-write PLL_REG_SUPPLY PLL_REG_SUPPLY 8 4 read-write 0 1.2V #0000 1 1.05V #0001 10 1.075V #0010 11 1.1V #0011 100 1.125V #0100 101 1.15V #0101 110 1.175V #0110 111 1.2V #0111 1000 1.225V #1000 1001 1.25V #1001 1100 1.325V #1100 1101 1.35V #1101 1110 1.375V #1110 1111 1.4V #1111 PLL_REG_BYPASS_ON PLL_REG_BYPASS_ON 16 1 read-write PLL_VCO_LDO_BYPASS PLL_VCO_LDO_BYPASS 17 1 read-write HPM_BIAS HPM Array Bias 24 7 read-write PLL_VCO_SPARE7 PLL_VCO_SPARE7 31 1 read-write PLL_CTRL2 PLL Control Register 2 0x448 32 read-write 0x4 0xFFFFFFFF PLL_VCO_KV PLL_VCO_KV 0 3 read-write PLL_KMOD_SLOPE PLL_KMOD_SLOPE 3 1 read-write PLL_VCO_REG_SUPPLY PLL_VCO_REG_SUPPLY 4 2 read-write 0 1.15V #00 1 1.2V #01 10 1.25V #10 11 1.3V #11 PLL_TMUX_ON PLL_TMUX_ON 8 1 read-write PLL_TEST_CTRL PLL Test Control 0x44C 32 read-write 0 0xFFFFFFFF PLL_TMUX_SEL PLL_TMUX_SEL 0 2 read-write PLL_VCO_REG_ATST PLL_VCO_REG_ATST 4 2 read-write PLL_REG_ATST_SEL PLL_REG_ATST_SEL 8 2 read-write PLL_VCO_TEST_CLK_MODE PLL_VCO_TEST_CLK_MODE 12 1 read-write PLL_FORCE_VTUNE_EXTERNALLY PLL_FORCE_VTUNE_EXTERNALLY 13 1 read-write PLL_RIPPLE_COUNTER_TEST_MODE PLL_RIPPLE_COUNTER_TEST_MODE 14 1 read-write QGEN_CTRL QGEN Control 0x458 32 read-write 0 0xFFFFFFFF QGEN_REG_SUPPLY QGEN_REG_SUPPLY 0 4 read-write 0 1.2V #0000 1 1.05V #0001 10 1.075V #0010 11 1.1V #0011 100 1.125V #0100 101 1.15V #0101 110 1.175V #0110 111 1.2V #0111 1000 1.225V #1000 1001 1.25V #1001 1100 1.325V #1100 1101 1.35V #1101 1110 1.375V #1110 1111 1.4V #1111 QGEN_REG_ATST_SEL QGEN_REG_ATST_SEL 4 4 read-write QGEN_REG_BYPASS_ON QGEN_REG_BYPASS_ON 8 1 read-write TCA_CTRL TCA Control 0x464 32 read-write 0 0xFFFFFFFF TCA_BIAS_CURR TCA_BIAS_CURR 0 2 read-write TCA_LOW_PWR_ON TCA_LOW_PWR_ON 2 1 read-write TCA_TX_REG_BYPASS_ON TCA_TX_REG_BYPASS_ON 3 1 read-write TCA_TX_REG_SUPPLY TCA_TX_REG_SUPPLY 4 4 read-write 0 1.2V #0000 1 1.05V #0001 10 1.075V #0010 11 1.1V #0011 100 1.125V #0100 101 1.15V #0101 110 1.175V #0110 111 1.2V #0111 1000 1.225V #1000 1001 1.25V #1001 1100 1.325V #1100 1101 1.35V #1101 1110 1.375V #1110 1111 1.4V #1111 TCA_TX_REG_ATST_SEL TCA_TX_REG_ATST_SEL 8 2 read-write TZA_CTRL TZA Control 0x468 32 read-write 0x44 0xFFFFFFFF TZA_CAP_TUNE TZA_CAP_TUNE 0 4 read-write TZA_GAIN TZA_GAIN 4 1 read-write TZA_DCOC_ON TZA_DCOC_ON 5 1 read-write TZA_CUR_CNTL TZA_CUR_CNTL 6 2 read-write TZA_SPARE TZA_SPARE 20 4 read-write TX_ANA_CTRL TX Analog Control 0x474 32 read-write 0 0xFFFFFFFF HPM_CAL_ADJUST HPM Cal Count Adjust 0 4 read-write ANA_SPARE Analog Spare 0x47C 32 read-write 0 0xFFFFFFFF IQMC_DC_GAIN_ADJ IQ Mismatch Correction DC Gain Coeff 0 11 read-write DCOC_TRK_EST_GS_CNT DCOC Tracking Estimator Gearshift Count 11 3 read-write 0 Only use {dcoc_alpha_radius_idx, dcoc_alphac_scaling_idx, dcoc_sign_scaling_idx} #000 1 Switch from {dcoc_alpha_radius_idx, dcoc_alphac_scaling_idx, dcoc_sign_scaling_idx} to {dcoc_alpha_radius_gs_idx, dcoc_alphac_scaling_gs_idx, dcoc_sign_scaling_idx} after the 1 update correction. #001 10 Switch after 2 update corrections. #010 11 Switch after 3 update corrections. #011 100 Switch after 4 update corrections. #100 101 Switch after 5 update corrections. #101 110 Switch after 6 update corrections. #110 111 Switch after 7 update corrections. #111 HPM_LSB_INVERT High port LSB array inversion control 14 2 read-write ANA_DTEST ANA_DTEST 16 6 read-only ZLL Zigbee Link Layer ZLL_ 0x4005D000 0 0x180 registers IRQSTS INTERRUPT REQUEST STATUS 0 32 read-write 0xF00000 0xFFF00500 SEQIRQ Sequence-end Interrupt Status bit. A '1' indicates the completion of an autosequence. This interrupt will assert whenever the Sequence Manager transitions from non-idle to idle state, for any reason. This is write a '1' to clear bit. 0 1 read-write 0 A Sequencer Interrupt has not occurred #0 1 A Sequencer Interrupt has occurred #1 TXIRQ Transmitter Interrupt Status bit. A '1' indicates the completion of a transmit operation. This is write a '1' to clear bit. 1 1 read-write 0 A TX Interrupt has not occurred #0 1 A TX Interrupt has occurred #1 RXIRQ Receiver Interrupt Status bit. A '1' indicates the completion of a receive operation. This is write a '1' to clear bit. 2 1 read-write 0 A RX Interrupt has not occurred #0 1 A RX Interrupt has occurred #1 CCAIRQ Clear Channel Assessment Interrupt Status bit. A '1' indicates completion of CCA operation. This is write '1' to clear bit. 3 1 read-write 0 A CCA Interrupt has not occurred #0 1 A CCA Interrupt has occurred #1 RXWTRMRKIRQ Receiver Byte Count Water Mark Interrupt Status bit. A '1' indicates that the number of bytes specified in the RX_WTR_MARK register has been reached. This is write a '1' to clear bit. 4 1 read-write 0 A RX Watermark Interrupt has not occurred #0 1 A RX Watermark Interrupt has occurred #1 FILTERFAIL_IRQ Receiver Packet Filter Fail Interrupt Status bit. A '1' indicates that the most-recently received packet has been rejected due to elements within the packet. This is write a '1' to clear bit. In Dual PAN mode, FILTERFAIL_IRQ applies to either or both networks, as follows: A: If PAN0 and PAN1 occupy different channels and CURRENT_NETWORK=0, FILTERFAIL_IRQ applies to PAN0. B: If PAN0 and PAN1 occupy different channels and CURRENT_NETWORK=1, FILTERFAIL_IRQ applies to PAN1. C: If PAN0 and PAN1 occupy the same channel, FILTERFAIL_IRQ is the logical 'AND' of the individual PANs' Filter Fail status. 5 1 read-write 0 A Filter Fail Interrupt has not occurred #0 1 A Filter Fail Interrupt has occurred #1 PLL_UNLOCK_IRQ PLL Un-lock Interrupt Status bit. A '1' indicates an unlock event has occurred in the PLL. This is write a '1' to clear bit. 6 1 read-write 0 A PLL Unlock Interrupt has not occurred #0 1 A PLL Unlock Interrupt has occurred #1 RX_FRM_PEND Status of the frame pending bit of the frame control field for the most-recently received packet. Read-only. 7 1 read-only PB_ERR_IRQ Packet Buffer Underrun Error IRQ 9 1 read-write 0 A Packet Buffer Underrun Error Interrupt has not occurred #0 1 A Packet Buffer Underrun Error Interrupt has occurred #1 TMRSTATUS Composite TMR Status 11 1 read-only 0 no TMRxIRQ is asserted #0 1 At least one of the TMRxIRQ is asserted (TMR1IRQ, TMR2IRQ, TMR3IRQ, or TMR4IRQ) #1 PI Poll Indication 12 1 read-only 0 the received packet was not a data request #0 1 the received packet was a data request, regardless of whether a Source Address table match occurred, or whether Source Address Management is enabled or not #1 SRCADDR Source Address Match Status 13 1 read-only CCA CCA Status 14 1 read-only 0 IDLE #0 1 BUSY #1 CRCVALID CRC Valid Status 15 1 read-only 0 Rx FCS != calculated CRC (incorrect) #0 1 Rx FCS = calculated CRC (correct) #1 TMR1IRQ Timer 1 IRQ 16 1 read-write TMR2IRQ Timer 2 IRQ 17 1 read-write TMR3IRQ Timer 3 IRQ 18 1 read-write TMR4IRQ Timer 4 IRQ 19 1 read-write TMR1MSK Timer Comperator 1 Interrupt Mask bit 20 1 read-write 0 allows interrupt when comparator matches event timer count #0 1 Interrupt generation is disabled, but a TMR1IRQ flag can be set #1 TMR2MSK Timer Comperator 2 Interrupt Mask bit 21 1 read-write 0 allows interrupt when comparator matches event timer count #0 1 Interrupt generation is disabled, but a TMR2IRQ flag can be set #1 TMR3MSK Timer Comperator 3 Interrupt Mask bit 22 1 read-write 0 allows interrupt when comparator matches event timer count #0 1 Interrupt generation is disabled, but a TMR3IRQ flag can be set #1 TMR4MSK Timer Comperator 4 Interrupt Mask bit 23 1 read-write 0 allows interrupt when comparator matches event timer count #0 1 Interrupt generation is disabled, but a TMR4IRQ flag can be set #1 RX_FRAME_LENGTH Receive Frame Length 24 7 read-only PHY_CTRL PHY CONTROL 0x4 32 read-write 0x802FF00 0xFFFFFFFF XCVSEQ Zigbee Transceiver Sequence Selector 0 3 read-write 0 I (IDLE) #000 1 R (RECEIVE) #001 10 T (TRANSMIT) #010 11 C (CCA) #011 100 TR (TRANSMIT/RECEIVE) #100 101 CCCA (CONTINUOUS CCA) #101 AUTOACK Auto Acknowledge Enable 3 1 read-write 0 sequence manager will not follow a receive frame with a Tx Ack frame, under any conditions; the autosequence will terminate after the receive frame. #0 1 sequence manager will follow a receive frame with an automatic hardware-generated Tx Ack frame, assuming other necessary conditions are met. #1 RXACKRQD Receive Acknowledge Frame required 4 1 read-write 0 An ordinary receive frame (any type of frame) follows the transmit frame. #0 1 A receive Ack frame is expected to follow the transmit frame (non-Ack frames are rejected). #1 CCABFRTX CCA Before TX 5 1 read-write 0 no CCA required, transmit operation begins immediately. #0 1 at least one CCA measurement is required prior to the transmit operation (see also SLOTTED). #1 SLOTTED Slotted Mode 6 1 read-write TMRTRIGEN Timer2 Trigger Enable 7 1 read-write 0 programmed sequence initiates immediately upon write to XCVSEQ. #0 1 allow timer TC2 (or TC2') to initiate a preprogrammed sequence (see XCVSEQ register). #1 SEQMSK Sequencer Interrupt Mask 8 1 read-write 0 allows completion of an autosequence to generate a zigbee interrupt #0 1 Completion of an autosequence will set the SEQIRQ status bit, but a zigbee interrupt is not generated #1 TXMSK TX Interrupt Mask 9 1 read-write 0 allows completion of a TX operation to generate a zigbee interrupt #0 1 Completion of a TX operation will set the TXIRQ status bit, but a zigbee interrupt is not generated #1 RXMSK RX Interrupt Mask 10 1 read-write 0 allows completion of a RX operation to generate a zigbee interrupt #0 1 Completion of a RX operation will set the RXIRQ status bit, but a zigbee interrupt is not generated #1 CCAMSK CCA Interrupt Mask 11 1 read-write 0 allows completion of a CCA operation to generate a zigbee interrupt #0 1 Completion of a CCA operation will set the CCAIRQ status bit, but an zigbee interrupt #1 RX_WMRK_MSK RX Watermark Interrupt Mask 12 1 read-write 0 allows a Received Byte Count match to the RX_WTR_MARK threshold register to generate a zigbee interrupt #0 1 A Received Byte Count match to the RX_WTR_MARK threshold register will set the RXWTRMRKIRQ status bit, but a zigbee interrupt is not generated #1 FILTERFAIL_MSK FilterFail Interrupt Mask 13 1 read-write 0 allows Packet Processor Filtering Failure to generate a zigbee interrupt #0 1 A Packet Processor Filtering Failure will set the FILTERFAIL_IRQ status bit, but a zigbee interrupt is not generated #1 PLL_UNLOCK_MSK PLL Unlock Interrupt Mask 14 1 read-write 0 allows PLL unlock event to generate a zigbee interrupt #0 1 A PLL unlock event will set the PLL_UNLOCK_IRQ status bit, but a zigbee interrupt is not generated #1 CRC_MSK CRC Mask 15 1 read-write 0 sequence manager ignores CRCVALID and considers the receive operation complete after the last octet of the frame has been received. #0 1 sequence manager requires CRCVALID=1 at the end of the received frame in order for the receive operation to complete successfully; if CRCVALID=0, sequence manager will return to preamble-detect mode after the last octet of the frame has been received. #1 PB_ERR_MSK Packet Buffer Error Interrupt Mask 17 1 read-write 0 Enable Packet Buffer Error to assert a zigbee interrupt #0 1 Mask Packet Buffer Error from generating a zigbee interrupt #1 TMR1CMP_EN Timer 1 Compare Enable 20 1 read-write 0 Don't allow an Event Timer Match to T1CMP to set TMR1IRQ #0 1 Allow an Event Timer Match to T1CMP to set TMR1IRQ #1 TMR2CMP_EN Timer 2 Compare Enable 21 1 read-write 0 Don't allow an Event Timer Match to T2CMP or T2PRIMECMP to set TMR2IRQ #0 1 Allow an Event Timer Match to T2CMP or T2PRIMECMP to set TMR2IRQ #1 TMR3CMP_EN Timer 3 Compare Enable 22 1 read-write 0 Don't allow an Event Timer Match to T3CMP to set TMR3IRQ #0 1 Allow an Event Timer Match to T3CMP to set TMR3IRQ #1 TMR4CMP_EN Timer 4 Compare Enable 23 1 read-write 0 Don't allow an Event Timer Match to T4CMP to set TMR4IRQ #0 1 Allow an Event Timer Match to T4CMP to set TMR4IRQ #1 TC2PRIME_EN Timer 2 Prime Compare Enable 24 1 read-write 0 Don't allow a match of the lower 16 bits of Event Timer to T2PRIMECMP to set TMR2IRQ #0 1 Allow a match of the lower 16 bits of Event Timer to T2PRIMECMP to set TMR2IRQ #1 PROMISCUOUS Promiscuous Mode Enable 25 1 read-write 0 normal mode #0 1 all packet filtering except frame length checking (FrameLength>=5 and FrameLength<=127) is bypassed. #1 TMRLOAD Event Timer Load Enable 26 1 write-only CCATYPE Clear Channel Assessment Type 27 2 read-write 0 ENERGY DETECT #00 1 CCA MODE 1 #01 10 CCA MODE 2 #10 11 CCA MODE 3 #11 PANCORDNTR0 Device is a PAN Coordinator on PAN0 29 1 read-write TC3TMOUT TMR3 Timeout Enable 30 1 read-write 0 TMR3 is a software timer only #0 1 Enable TMR3 to abort Rx or CCCA operations. #1 TRCV_MSK Transceiver Global Interrupt Mask 31 1 read-write 0 Enable any unmasked interrupt source to assert zigbee interrupt #0 1 Mask all interrupt sources from asserting zigbee interrupt #1 EVENT_TMR EVENT TIMER 0x8 32 read-only 0 0xFFFFFFFF EVENT_TMR Event Timer 0 24 read-only TIMESTAMP TIMESTAMP 0xC 32 read-only 0 0xFFFFFFFF TIMESTAMP Timestamp 0 24 read-only T1CMP T1 COMPARE 0x10 32 read-write 0xFFFFFF 0xFFFFFFFF T1CMP TMR1 Compare Value 0 24 read-write T2CMP T2 COMPARE 0x14 32 read-write 0xFFFFFF 0xFFFFFFFF T2CMP TMR2 Compare Value 0 24 read-write T2PRIMECMP T2 PRIME COMPARE 0x18 32 read-write 0xFFFF 0xFFFFFFFF T2PRIMECMP TMR2 Prime Compare Value 0 16 read-write T3CMP T3 COMPARE 0x1C 32 read-write 0xFFFFFF 0xFFFFFFFF T3CMP TMR3 Compare Value 0 24 read-write T4CMP T4 COMPARE 0x20 32 read-write 0xFFFFFF 0xFFFFFFFF T4CMP TMR4 Compare Value 0 24 read-write PA_PWR PA POWER 0x24 32 read-write 0x8 0xFFFFFFFF PA_PWR PA Power 0 4 read-write CHANNEL_NUM0 CHANNEL NUMBER 0 0x28 32 read-write 0x12 0xFFFFFFFF CHANNEL_NUM0 Channel Number for PAN0 0 7 read-write LQI_AND_RSSI LQI AND RSSI 0x2C 32 read-only 0 0xFFFFFFFF LQI_VALUE LQI Value 0 8 read-only RSSI RSSI Value 8 8 read-only CCA1_ED_FNL RSSI Value 16 8 read-only MACSHORTADDRS0 MAC SHORT ADDRESS 0 0x30 32 read-write 0xFFFFFFFF 0xFFFFFFFF MACPANID0 MAC PAN ID for PAN0 0 16 read-write MACSHORTADDRS0 MAC SHORT ADDRESS for PAN0 16 16 read-write MACLONGADDRS0_LSB MAC LONG ADDRESS 0 LSB 0x34 32 read-write 0xFFFFFFFF 0xFFFFFFFF MACLONGADDRS0_LSB MAC LONG ADDRESS for PAN0 LSB 0 32 read-write MACLONGADDRS0_MSB MAC LONG ADDRESS 0 MSB 0x38 32 read-write 0xFFFFFFFF 0xFFFFFFFF MACLONGADDRS0_MSB MAC LONG ADDRESS for PAN0 MSB 0 32 read-write RX_FRAME_FILTER RECEIVE FRAME FILTER 0x3C 32 read-write 0xF 0xFFFFFFFF BEACON_FT Beacon Frame Type Enable 0 1 read-write 0 reject all Beacon frames #0 1 Beacon frame type enabled. #1 DATA_FT Data Frame Type Enable 1 1 read-write 0 reject all Data frames #0 1 Data frame type enabled. #1 ACK_FT Ack Frame Type Enable 2 1 read-write 0 reject all Acknowledge frames #0 1 Acknowledge frame type enabled. #1 CMD_FT MAC Command Frame Type Enable 3 1 read-write 0 reject all MAC Command frames #0 1 MAC Command frame type enabled. #1 NS_FT Not Specified Frame Type Enable 4 1 read-write 0 reject all reserved frame types #0 1 Not-specified (reserved) frame type enabled. No packet filtering is performed, except for frame length checking (FrameLength>=5 and FrameLength<=127). #1 ACTIVE_PROMISCUOUS Active Promiscuous 5 1 read-write 0 normal operation #0 1 Provide Data Indication on all received packets under the same rules which apply in PROMISCUOUS mode, however acknowledge those packets under rules which apply in non-PROMISCUOUS mode #1 FRM_VER Frame Version Selector 6 2 read-write CCA_LQI_CTRL CCA AND LQI CONTROL 0x40 32 read-write 0x866004B 0xFFFFFFFF CCA1_THRESH CCA Mode 1 Threshold 0 8 read-write LQI_OFFSET_COMP LQI Offset Compensation 16 8 read-write CCA3_AND_NOT_OR CCA Mode 3 AND not OR 27 1 read-write 0 CCA1 or CCA2 #0 1 CCA1 and CCA2 #1 CCA2_CTRL CCA2 CONTROL 0x44 32 read-write 0x8230 0xFFFFFFFF CCA2_NUM_CORR_PEAKS CCA Mode 2 Number of Correlation Peaks Detected 0 4 read-only CCA2_MIN_NUM_CORR_TH CCA Mode 2 Threshold Number of Correlation Peaks 4 3 read-write CCA2_CORR_THRESH CCA Mode 2 Correlation Threshold 8 8 read-write FAD_CTRL FAD CONTROL 0x48 32 read-write 0x804 0xFFFFFFFF FAD_EN FAD Enable 0 1 read-write ANTX Antenna Selection 1 1 read-write FAD_NOT_GPIO FAD/GPIO Selector 2 1 read-write ANTX_EN FAD Antenna Controls Enable 8 2 read-write 00 all disabled (held low) #00 01 only RX/TX_SWITCH enabled #01 10 only ANT_A/B enabled #10 11 all enabled #11 ANTX_HZ FAD PAD Tristate Control 10 1 read-write 0 ANT_A, ANT_B, RX_SWITCH and TX_SWITCH are actively driven outputs. #0 1 Antenna controls high impedance- Set ANT_A, ANT_B, RX_SWITCH and TX_SWITCH in high impedance. #1 ANTX_CTRLMODE Antenna Diversity Control Mode 11 1 read-write ANTX_POL Antenna Diversity PAD Polarity 12 4 read-write SNF_CTRL SNF CONTROL 0x4C 32 read-write 0 0xFFFFFFFF SNF_EN SNF Enable 0 1 read-write BSM_CTRL BSM CONTROL 0x50 32 read-write 0 0xFFFFFFFF BSM_EN BSM Enable 0 1 read-write 0 Zigbee Bit Streaming Mode Disabled #0 1 Zigbee Bit Streaming Mode Enabled #1 MACSHORTADDRS1 MAC SHORT ADDRESS 1 0x54 32 read-write 0xFFFFFFFF 0xFFFFFFFF MACPANID1 MAC PAN ID for PAN1 0 16 read-write MACSHORTADDRS1 MAC SHORT ADDRESS for PAN1 16 16 read-write MACLONGADDRS1_LSB MAC LONG ADDRESS 1 LSB 0x58 32 read-write 0xFFFFFFFF 0xFFFFFFFF MACLONGADDRS1_LSB MAC LONG ADDRESS for PAN1 LSB 0 32 read-write MACLONGADDRS1_MSB MAC LONG ADDRESS 1 MSB 0x5C 32 read-write 0xFFFFFFFF 0xFFFFFFFF MACLONGADDRS1_MSB MAC LONG ADDRESS for PAN1 MSB 0 32 read-write DUAL_PAN_CTRL DUAL PAN CONTROL 0x60 32 read-write 0 0xFF3FFFF7 ACTIVE_NETWORK Active Network Selector 0 1 read-write 0 Select PAN0 #0 1 Select PAN1 #1 DUAL_PAN_AUTO Activates automatic Dual PAN operating mode 1 1 read-write PANCORDNTR1 Device is a PAN Coordinator on PAN1 2 1 read-write CURRENT_NETWORK Indicates which PAN is currently selected by hardware 3 1 read-only 0 PAN0 is selected #0 1 PAN1 is selected #1 ZB_DP_CHAN_OVRD_EN Dual PAN Channel Override Enable 4 1 read-write ZB_DP_CHAN_OVRD_SEL Dual PAN Channel Override Selector 5 1 read-write DUAL_PAN_DWELL Dual PAN Channel Frequency Dwell Time 8 8 read-write DUAL_PAN_REMAIN Time Remaining before next PAN switch in auto Dual PAN mode 16 6 read-only RECD_ON_PAN0 Last Packet was Received on PAN0 22 1 read-only RECD_ON_PAN1 Last Packet was Received on PAN1 23 1 read-only CHANNEL_NUM1 CHANNEL NUMBER 1 0x64 32 read-write 0x7F 0xFFFFFFFF CHANNEL_NUM1 Channel Number for PAN1 0 7 read-write SAM_CTRL SAM CONTROL 0x68 32 read-write 0x80804000 0xFFFFFFFF SAP0_EN Enables SAP0 Partition of the SAM Table 0 1 read-write 0 Disables SAP0 Partition #0 1 Enables SAP0 Partition #1 SAA0_EN Enables SAA0 Partition of the SAM Table 1 1 read-write 0 Disables SAA0 Partition #0 1 Enables SAA0 Partition #1 SAP1_EN Enables SAP1 Partition of the SAM Table 2 1 read-write 0 Disables SAP1 Partition #0 1 Enables SAP1 Partition #1 SAA1_EN Enables SAA1 Partition of the SAM Table 3 1 read-write 0 Disables SAA1 Partition #0 1 Enables SAA1 Partition #1 SAA0_START First Index of SAA0 partition 8 8 read-write SAP1_START First Index of SAP1 partition 16 8 read-write SAA1_START First Index of SAA1 partition 24 8 read-write SAM_TABLE SOURCE ADDRESS MANAGEMENT TABLE 0x6C 32 read-write 0 0x4CFFFF7F SAM_INDEX Contains the SAM table index to be enabled or invalidated 0 7 read-write SAM_INDEX_WR Enables SAM Table Contents to be updated 7 1 write-only SAM_CHECKSUM Software-computed source address checksum, to be installed into a table index 8 16 read-write SAM_INDEX_INV Invalidate the SAM table index selected by SAM_INDEX 24 1 write-only SAM_INDEX_EN Enable the SAM table index selected by SAM_INDEX 25 1 write-only ACK_FRM_PND Software-override value for the state of the AutoTxAck FramePending field 26 1 read-write ACK_FRM_PND_CTRL Software-override control for the state of the AutoTxAck FramePending field 27 1 read-write 0 the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet is determined by hardware #0 1 the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet tracks ACK_FRM_PEND #1 FIND_FREE_IDX Find First Free Index 28 1 write-only INVALIDATE_ALL Invalidated Entire SAM Table 29 1 write-only SAM_BUSY SAM Table Update Status Bit 31 1 read-only SAM_MATCH SAM MATCH 0x70 32 read-only 0 0x7F7F7F7F SAP0_MATCH Index in the SAP0 Partition of the SAM Table corresponding to the first checksum match 0 7 read-only SAP0_ADDR_PRESENT A Checksum Match is Present in the SAP0 Partition of the SAM Table 7 1 read-only SAA0_MATCH Index in the SAA0 Partition of the SAM Table corresponding to the first checksum match 8 7 read-only SAA0_ADDR_ABSENT A Checksum Match is Absent in the SAA0 Partition of the SAM Table 15 1 read-only SAP1_MATCH Index in the SAP1 Partition of the SAM Table corresponding to the first checksum match 16 7 read-only SAP1_ADDR_PRESENT A Checksum Match is Present in the SAP1 Partition of the SAM Table 23 1 read-only SAA1_MATCH Index in the SAA1 Partition of the SAM Table corresponding to the first checksum match 24 7 read-only SAA1_ADDR_ABSENT A Checksum Match is Absent in the SAP1 Partition of the SAM Table 31 1 read-only SAM_FREE_IDX SAM FREE INDEX 0x74 32 read-only 0 0xFFFFFFFF SAP0_1ST_FREE_IDX First non-enabled (invalid) index in the SAP0 partition 0 8 read-only SAA0_1ST_FREE_IDX First non-enabled (invalid) index in the SAA0 partition 8 8 read-only SAP1_1ST_FREE_IDX First non-enabled (invalid) index in the SAP1 partition 16 8 read-only SAA1_1ST_FREE_IDX First non-enabled (invalid) index in the SAA1 partition 24 8 read-only SEQ_CTRL_STS SEQUENCE CONTROL AND STATUS 0x78 32 read-write 0x8 0xF8FF07FF CLR_NEW_SEQ_INHIBIT Overrides the automatic hardware locking of the programmed XCVSEQ while an autosequence is underway 2 1 read-write EVENT_TMR_DO_NOT_LATCH Overrides the automatic hardware latching of the Event Timer 3 1 read-write LATCH_PREAMBLE Stickiness Control for Preamble Detection 4 1 read-write 0 Don't make PREAMBLE_DET and SFD_DET bits of PHY_STS (SEQ_STATE) Register "sticky", i.e, these status bits reflect the realtime, dynamic state of preamble_detect and sfd_detect #0 1 Make PREAMBLE_DET and SFD_DET bits of PHY_STS (SEQ_STATE) Register "sticky", i.e.,occurrences of preamble and SFD detection are latched and held until the start of the next autosequence #1 NO_RX_RECYCLE Disable Automatic RX Sequence Recycling 5 1 read-write FORCE_CRC_ERROR Induce a CRC Error in Transmitted Packets 6 1 read-write 0 normal operation #0 1 Force the next transmitted packet to have a CRC error #1 CONTINUOUS_EN Enable Continuous TX or RX Mode 7 1 read-write 0 normal operation #0 1 Continuous TX or RX mode is enabled (depending on XCVSEQ setting). #1 XCVSEQ_ACTUAL Reflects the programmed sequence that has been recognized by the ZSM Sequence Manager 8 3 read-only SEQ_IDLE ZSM Sequence Idle Indicator 11 1 read-only NEW_SEQ_INHIBIT New Sequence Inhibit 12 1 read-only RX_TIMEOUT_PENDING Indicates a TMR3 RX Timeout is Pending 13 1 read-only RX_MODE RX Operation in Progress 14 1 read-only TMR2_SEQ_TRIG_ARMED indicates that TMR2 has been programmed and is armed to trigger a new autosequence 15 1 read-only SEQ_T_STATUS Status of the just-completed or ongoing Sequence T or Sequence TR 16 6 read-only SW_ABORTED Autosequence has terminated due to a Software abort. 24 1 read-only TC3_ABORTED Autosequence has terminated due to an TMR3 timeout 25 1 read-only PLL_ABORTED Autosequence has terminated due to an PLL unlock event 26 1 read-only ACKDELAY ACK DELAY 0x7C 32 read-write 0x7 0xFFFFFFFF ACKDELAY Provides a fine-tune adjustment of the time delay between Rx warmdown and the beginning of Tx warmup for an autoTxAck packet 0 6 read-write TXDELAY Provides a fine-tune adjustment of the time delay between post-CCA Rx warm-down and the beginning of Tx warm-up 8 6 read-write FILTERFAIL_CODE FILTER FAIL CODE 0x80 32 read-write 0 0xFFFFFFFF FILTERFAIL_CODE Filter Fail Code 0 10 read-only FILTERFAIL_PAN_SEL PAN Selector for Filter Fail Code 15 1 read-write 0 FILTERFAIL_CODE[9:0] will report the FILTERFAIL status of PAN0 #0 1 FILTERFAIL_CODE[9:0] will report the FILTERFAIL status of PAN1 #1 RX_WTR_MARK RECEIVE WATER MARK 0x84 32 read-write 0xFF 0xFFFFFFFF RX_WTR_MARK Receive byte count needed to trigger a RXWTRMRKIRQ interrupt 0 8 read-write SLOT_PRELOAD SLOT PRELOAD 0x8C 32 read-write 0x74 0xFFFFFFFF SLOT_PRELOAD Slotted Mode Preload 0 8 read-write SEQ_STATE ZIGBEE SEQUENCE STATE 0x90 32 read-only 0 0xFFFFC0FF SEQ_STATE ZSM Sequence State 0 5 read-only PREAMBLE_DET Preamble Detected 8 1 read-only SFD_DET SFD Detected 9 1 read-only FILTERFAIL_FLAG_SEL Consolidated Filter Fail Flag 10 1 read-only CRCVALID CRC Valid Indicator 11 1 read-only 0 Rx FCS != calculated CRC (incorrect) #0 1 Rx FCS = calculated CRC (correct) #1 PLL_ABORT Raw PLL Abort Signal 12 1 read-only PLL_ABORTED Autosequence has terminated due to an PLL unlock event 13 1 read-only RX_BYTE_COUNT Realtime Received Byte Count 16 8 read-only CCCA_BUSY_CNT Number of CCA Measurements resulting in Busy Channel 24 6 read-only TMR_PRESCALE TIMER PRESCALER 0x94 32 read-write 0x3 0xFFFFFFFF TMR_PRESCALE Timer Prescaler 0 3 read-write 010 500kHz (33.55 S) #010 011 250kHz (67.11 S) -- default #011 100 125kHz (134.22 S) #100 101 62.5kHz (268.44 S) #101 110 31.25kHz (536.87 S) #110 111 15.625kHz (1073.74 S) #111 LENIENCY_LSB LENIENCY LSB 0x98 32 read-write 0 0xFFFFFFFF LENIENCY_REGISTER Leniency Register, bits [31:0] 0 32 read-write LENIENCY_MSB LENIENCY MSB 0x9C 32 read-write 0 0xFFFFFFFF LENIENCY_REGISTER Leniency Register, bits [39:32] 0 8 read-write PART_ID PART ID 0xA0 32 read-only 0 0xFFFFFFFF PART_ID Zigbee Part ID 0 8 read-only 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PKT_BUFFER%s PACKET BUFFER 0x100 32 read-write 0 0xFFFFFFFF PKT_BUFFER Packet Buffer Entry 0 32 read-write CMT Carrier Modulator Transmitter CMT_ 0x40062000 0 0xC registers CMT 14 CGH1 CMT Carrier Generator High Data Register 1 0 8 read-write 0 0 PH Primary Carrier High Time Data Value 0 8 read-write CGL1 CMT Carrier Generator Low Data Register 1 0x1 8 read-write 0 0 PL Primary Carrier Low Time Data Value 0 8 read-write CGH2 CMT Carrier Generator High Data Register 2 0x2 8 read-write 0 0 SH Secondary Carrier High Time Data Value 0 8 read-write CGL2 CMT Carrier Generator Low Data Register 2 0x3 8 read-write 0 0 SL Secondary Carrier Low Time Data Value 0 8 read-write OC CMT Output Control Register 0x4 8 read-write 0 0xFF IROPEN IRO Pin Enable 5 1 read-write 0 The IRO signal is disabled. #0 1 The IRO signal is enabled as output. #1 CMTPOL CMT Output Polarity 6 1 read-write 0 The IRO signal is active-low. #0 1 The IRO signal is active-high. #1 IROL IRO Latch Control 7 1 read-write MSC CMT Modulator Status and Control Register 0x5 8 read-write 0 0xFF MCGEN Modulator and Carrier Generator Enable 0 1 read-write 0 Modulator and carrier generator disabled #0 1 Modulator and carrier generator enabled #1 EOCIE End of Cycle Interrupt Enable 1 1 read-write 0 CPU interrupt is disabled. #0 1 CPU interrupt is enabled. #1 FSK FSK Mode Select 2 1 read-write 0 The CMT operates in Time or Baseband mode. #0 1 The CMT operates in FSK mode. #1 BASE Baseband Enable 3 1 read-write 0 Baseband mode is disabled. #0 1 Baseband mode is enabled. #1 EXSPC Extended Space Enable 4 1 read-write 0 Extended space is disabled. #0 1 Extended space is enabled. #1 CMTDIV CMT Clock Divide Prescaler 5 2 read-write 00 IF * 1 #00 01 IF * 2 #01 10 IF * 4 #10 11 IF * 8 #11 EOCF End Of Cycle Status Flag 7 1 read-only 0 End of modulation cycle has not occured since the flag last cleared. #0 1 End of modulator cycle has occurred. #1 CMD1 CMT Modulator Data Register Mark High 0x6 8 read-write 0 0 MB MB[15:8] 0 8 read-write CMD2 CMT Modulator Data Register Mark Low 0x7 8 read-write 0 0 MB MB[7:0] 0 8 read-write CMD3 CMT Modulator Data Register Space High 0x8 8 read-write 0 0 SB SB[15:8] 0 8 read-write CMD4 CMT Modulator Data Register Space Low 0x9 8 read-write 0 0 SB SB[7:0] 0 8 read-write PPS CMT Primary Prescaler Register 0xA 8 read-write 0 0xFF PPSDIV Primary Prescaler Divider 0 4 read-write 0000 Bus clock * 1 #0000 0001 Bus clock * 2 #0001 0010 Bus clock * 3 #0010 0011 Bus clock * 4 #0011 0100 Bus clock * 5 #0100 0101 Bus clock * 6 #0101 0110 Bus clock * 7 #0110 0111 Bus clock * 8 #0111 1000 Bus clock * 9 #1000 1001 Bus clock * 10 #1001 1010 Bus clock * 11 #1010 1011 Bus clock * 12 #1011 1100 Bus clock * 13 #1100 1101 Bus clock * 14 #1101 1110 Bus clock * 15 #1110 1111 Bus clock * 16 #1111 DMA CMT Direct Memory Access Register 0xB 8 read-write 0 0xFF DMA DMA Enable 0 1 read-write 0 DMA transfer request and done are disabled. #0 1 DMA transfer request and done are enabled. #1 MCG Multipurpose Clock Generator module MCG_ 0x40064000 0 0xE registers MCG 27 C1 MCG Control 1 Register 0 8 read-write 0x4 0xFF IREFSTEN Internal Reference Stop Enable 0 1 read-write 0 Internal reference clock is disabled in Stop mode. #0 1 Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. #1 IRCLKEN Internal Reference Clock Enable 1 1 read-write 0 MCGIRCLK inactive. #0 1 MCGIRCLK active. #1 IREFS Internal Reference Select 2 1 read-write 0 External reference clock is selected. #0 1 The slow internal reference clock is selected. #1 FRDIV FLL External Reference Divider 3 3 read-write 000 If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. #000 001 If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. #001 010 If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. #010 011 If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. #011 100 If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. #100 101 If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. #101 110 If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . #110 111 If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 . #111 CLKS Clock Source Select 6 2 read-write 00 Encoding 0 - Output of FLL is selected. #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 11 Encoding 3 - Reserved. #11 C2 MCG Control 2 Register 0x1 8 read-write 0xC0 0xFF IRCS Internal Reference Clock Select 0 1 read-write 0 Slow internal reference clock selected. (32 kHz Internal Reference Clock (32 kHz IRC)). #0 1 Fast internal reference clock selected. (4 MHz Internal Reference Clock (4 MHz IRC)). #1 LP Low Power Select 1 1 read-write 0 FLL is not disabled in bypass modes. #0 1 FLL is disabled in bypass modes (lower power) #1 EREFS External Reference Select 2 1 read-write 0 External reference clock requested. #0 1 Oscillator requested. #1 HGO High Gain Oscillator Select 3 1 read-write 0 Configure crystal oscillator for low-power operation. #0 1 Configure crystal oscillator for high-gain operation. #1 RANGE Frequency Range Select 4 2 read-write 00 Encoding 0 - Low frequency range selected for the crystal oscillator . #00 01 Encoding 1 - High frequency range selected for the crystal oscillator . #01 1X Encoding 2 - Very high frequency range selected for the crystal oscillator . #1x FCFTRIM Fast Internal Reference Clock Fine Trim 6 1 read-write LOCRE0 Loss of Clock Reset Enable 7 1 read-write 0 Interrupt request is generated on a loss of OSC0 external reference clock. #0 1 Generate a reset request on a loss of OSC0 external reference clock. #1 C3 MCG Control 3 Register 0x2 8 read-write 0 0 SCTRIM Slow Internal Reference Clock Trim Setting 0 8 read-write C4 MCG Control 4 Register 0x3 8 read-write 0 0xE0 SCFTRIM Slow Internal Reference Clock Fine Trim 0 1 read-write FCTRIM Fast Internal Reference Clock Trim Setting 1 4 read-write DRST_DRS DCO Range Select 5 2 read-write 00 Encoding 0 - Low range (reset default). #00 01 Encoding 1 - Mid range. #01 10 Encoding 2 - Mid-high range. #10 11 Encoding 3 - High range. #11 DMX32 DCO Maximum Frequency with 32.768 kHz Reference 7 1 read-write 0 DCO has a default range of 25%. #0 1 DCO is fine-tuned for maximum frequency with 32.768 kHz reference. #1 C5 MCG Control 5 Register 0x4 8 read-only 0 0xFF C6 MCG Control 6 Register 0x5 8 read-write 0 0xFF CME0 Clock Monitor Enable 5 1 read-write 0 External clock monitor is disabled. #0 1 Generate an interrupt or a reset request (see MCG_C2[LOCRE0]) on loss of external clock. #1 S MCG Status Register 0x6 8 read-only 0x10 0xFF IRCST Internal Reference Clock Status 0 1 read-only 0 Source of internal reference clock is the slow clock (32 kHz IRC). #0 1 Source of internal reference clock is the fast clock (4 MHz IRC). #1 OSCINIT0 OSC Initialization 1 1 read-only CLKST Clock Mode Status 2 2 read-only 00 Encoding 0 - Output of the FLL is selected (reset default). #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 IREFST Internal Reference Status 4 1 read-only 0 Source of FLL reference clock is the external reference clock. #0 1 Source of FLL reference clock is the internal reference clock. #1 SC MCG Status and Control Register 0x8 8 read-write 0x2 0xFF LOCS0 OSC0 Loss of Clock Status 0 1 read-write 0 Loss of OSC0 has not occurred. #0 1 Loss of OSC0 has occurred. #1 FCRDIV Fast Clock Internal Reference Divider 1 3 read-write 000 Divide Factor is 1 #000 001 Divide Factor is 2. #001 010 Divide Factor is 4. #010 011 Divide Factor is 8. #011 100 Divide Factor is 16 #100 101 Divide Factor is 32 #101 110 Divide Factor is 64 #110 111 Divide Factor is 128. #111 FLTPRSRV FLL Filter Preserve Enable 4 1 read-write 0 FLL filter and FLL frequency will reset on changes to currect clock mode. #0 1 Fll filter and FLL frequency retain their previous values during new clock mode change. #1 ATMF Automatic Trim Machine Fail Flag 5 1 read-write 0 Automatic Trim Machine completed normally. #0 1 Automatic Trim Machine failed. #1 ATMS Automatic Trim Machine Select 6 1 read-write 0 32 kHz Internal Reference Clock selected. #0 1 4 MHz Internal Reference Clock selected. #1 ATME Automatic Trim Machine Enable 7 1 read-write 0 Auto Trim Machine disabled. #0 1 Auto Trim Machine enabled. #1 ATCVH MCG Auto Trim Compare Value High Register 0xA 8 read-write 0 0xFF ATCVH ATM Compare Value High 0 8 read-write ATCVL MCG Auto Trim Compare Value Low Register 0xB 8 read-write 0 0xFF ATCVL ATM Compare Value Low 0 8 read-write C7 MCG Control 7 Register 0xC 8 read-write 0 0xFF OSCSEL MCG OSC Clock Select 0 1 read-write 0 Selects Oscillator (OSCCLK). #0 1 Selects 32 kHz RTC Oscillator. #1 C8 MCG Control 8 Register 0xD 8 read-write 0x80 0xFF LOCS1 RTC Loss of Clock Status 0 1 read-write 0 Loss of RTC has not occur. #0 1 Loss of RTC has occur #1 CME1 Clock Monitor Enable1 5 1 read-write 0 External clock monitor is disabled for RTC clock. #0 1 External clock monitor is enabled for RTC clock. #1 LOCRE1 Loss of Clock Reset Enable 7 1 read-write 0 Interrupt request is generated on a loss of RTC external reference clock. #0 1 Generate a reset request on a loss of RTC external reference clock #1 I2C0 Inter-Integrated Circuit I2C I2C0_ 0x40066000 0 0xD registers I2C0 8 A1 I2C Address Register 1 0 8 read-write 0 0xFF AD Address 1 7 read-write F I2C Frequency Divider register 0x1 8 read-write 0 0xFF ICR ClockRate 0 6 read-write MULT Multiplier Factor 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 C1 I2C Control Register 1 0x2 8 read-write 0 0xFF DMAEN DMA Enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 WUEN Wakeup Enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 RSTA Repeat START 2 1 write-only TXAK Transmit Acknowledge Enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). #0 1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). #1 TX Transmit Mode Select 4 1 read-write 0 Receive #0 1 Transmit #1 MST Master Mode Select 5 1 read-write 0 Slave mode #0 1 Master mode #1 IICIE I2C Interrupt Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 IICEN I2C Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 S I2C Status register 0x3 8 read-write 0x80 0xFF RXAK Receive Acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 IICIF Interrupt Flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 SRW Slave Read/Write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 RAM Range Address Match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 ARBL Arbitration Lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus Busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed As A Slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 TCF Transfer Complete Flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 D I2C Data I/O register 0x4 8 read-write 0 0xFF DATA Data 0 8 read-write C2 I2C Control Register 2 0x5 8 read-write 0 0xFF AD Slave Address 0 3 read-write RMEN Range Address Matching Enable 3 1 read-write 0 Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave Baud Rate Control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 HDRS High Drive Select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 ADEXT Address Extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General Call Address Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 FLT I2C Programmable Input Glitch Filter Register 0x6 8 read-write 0 0xFF FLT I2C Programmable Filter Factor 0 4 read-write 0 No filter/bypass #0000 STARTF I2C Bus Start Detect Flag 4 1 read-write 0 No start happens on I2C bus #0 1 Start detected on I2C bus #1 SSIE I2C Bus Stop or Start Interrupt Enable 5 1 read-write 0 Stop or start detection interrupt is disabled #0 1 Stop or start detection interrupt is enabled #1 STOPF I2C Bus Stop Detect Flag 6 1 read-write 0 No stop happens on I2C bus #0 1 Stop detected on I2C bus #1 SHEN Stop Hold Enable 7 1 read-write 0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated. Clocks to peripherals are gated when the core stop occurs. #0 1 Stop holdoff is enabled. Stop mode entry is gated until the current transaction phase is complete, and the IP enters stop mode (clocks are gated) after the current phase's completion. That is to say: If the system stop request occurs between the address or data phase, the stop acknowledge is asserted after the current byte and IIC ack completion (after the acknowledge in the ninth cycle). #1 RA I2C Range Address register 0x7 8 read-write 0 0xFF RAD Range Slave Address 1 7 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write 0 0xFF SHTF2IE SHTF2 Interrupt Enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SHTF2 SCL High Timeout Flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF1 SCL High Timeout Flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SLTF SCL Low Timeout Flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout Counter Clock Select 4 1 read-write 0 Timeout counter counts at the frequency of the I2C module clock / 64 #0 1 Timeout counter counts at the frequency of the I2C module clock #1 SIICAEN Second I2C Address Enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 ALERTEN SMBus Alert Response Address Enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK Enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. Enable I2C_S2[DFEN] in the master receive mode. #1 A2 I2C Address Register 2 0x9 8 read-write 0xC2 0xFF SAD SMBus Address 1 7 read-write SLTH I2C SCL Low Timeout Register High 0xA 8 read-write 0 0xFF SSLT SSLT[15:8] 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write 0 0xFF SSLT SSLT[7:0] 0 8 read-write S2 I2C Status register 2 0xC 8 read-write 0x1 0xFF EMPTY Empty flag 0 1 read-only 0 Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer. #0 1 Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer. Write 1 to reset this flag (to the default value 1, which means that the Tx or Rx buffer is empty). #1 ERROR Error flag 1 1 read-write 0 The buffer is not full and all write/read operations have no errors. #0 1 There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the buffer is busy). #1 DFEN Double Buffer Enable 2 1 read-write 0 Disables the double buffer mode; clock stretch is enabled. #0 1 Enables the double buffer mode; clock stretch is disabled. In the slave mode, the I2C will not hold bus between data transfers. #1 I2C1 Inter-Integrated Circuit I2C I2C1_ 0x40067000 0 0xD registers I2C1 9 A1 I2C Address Register 1 0 8 read-write 0 0xFF AD Address 1 7 read-write F I2C Frequency Divider register 0x1 8 read-write 0 0xFF ICR ClockRate 0 6 read-write MULT Multiplier Factor 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 C1 I2C Control Register 1 0x2 8 read-write 0 0xFF DMAEN DMA Enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 WUEN Wakeup Enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 RSTA Repeat START 2 1 write-only TXAK Transmit Acknowledge Enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). #0 1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). #1 TX Transmit Mode Select 4 1 read-write 0 Receive #0 1 Transmit #1 MST Master Mode Select 5 1 read-write 0 Slave mode #0 1 Master mode #1 IICIE I2C Interrupt Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 IICEN I2C Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 S I2C Status register 0x3 8 read-write 0x80 0xFF RXAK Receive Acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 IICIF Interrupt Flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 SRW Slave Read/Write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 RAM Range Address Match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 ARBL Arbitration Lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus Busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed As A Slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 TCF Transfer Complete Flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 D I2C Data I/O register 0x4 8 read-write 0 0xFF DATA Data 0 8 read-write C2 I2C Control Register 2 0x5 8 read-write 0 0xFF AD Slave Address 0 3 read-write RMEN Range Address Matching Enable 3 1 read-write 0 Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave Baud Rate Control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 HDRS High Drive Select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 ADEXT Address Extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General Call Address Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 FLT I2C Programmable Input Glitch Filter Register 0x6 8 read-write 0 0xFF FLT I2C Programmable Filter Factor 0 4 read-write 0 No filter/bypass #0000 STARTF I2C Bus Start Detect Flag 4 1 read-write 0 No start happens on I2C bus #0 1 Start detected on I2C bus #1 SSIE I2C Bus Stop or Start Interrupt Enable 5 1 read-write 0 Stop or start detection interrupt is disabled #0 1 Stop or start detection interrupt is enabled #1 STOPF I2C Bus Stop Detect Flag 6 1 read-write 0 No stop happens on I2C bus #0 1 Stop detected on I2C bus #1 SHEN Stop Hold Enable 7 1 read-write 0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated. Clocks to peripherals are gated when the core stop occurs. #0 1 Stop holdoff is enabled. Stop mode entry is gated until the current transaction phase is complete, and the IP enters stop mode (clocks are gated) after the current phase's completion. That is to say: If the system stop request occurs between the address or data phase, the stop acknowledge is asserted after the current byte and IIC ack completion (after the acknowledge in the ninth cycle). #1 RA I2C Range Address register 0x7 8 read-write 0 0xFF RAD Range Slave Address 1 7 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write 0 0xFF SHTF2IE SHTF2 Interrupt Enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SHTF2 SCL High Timeout Flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF1 SCL High Timeout Flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SLTF SCL Low Timeout Flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout Counter Clock Select 4 1 read-write 0 Timeout counter counts at the frequency of the I2C module clock / 64 #0 1 Timeout counter counts at the frequency of the I2C module clock #1 SIICAEN Second I2C Address Enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 ALERTEN SMBus Alert Response Address Enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK Enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. Enable I2C_S2[DFEN] in the master receive mode. #1 A2 I2C Address Register 2 0x9 8 read-write 0xC2 0xFF SAD SMBus Address 1 7 read-write SLTH I2C SCL Low Timeout Register High 0xA 8 read-write 0 0xFF SSLT SSLT[15:8] 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write 0 0xFF SSLT SSLT[7:0] 0 8 read-write S2 I2C Status register 2 0xC 8 read-write 0x1 0xFF EMPTY Empty flag 0 1 read-only 0 Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer. #0 1 Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer. Write 1 to reset this flag (to the default value 1, which means that the Tx or Rx buffer is empty). #1 ERROR Error flag 1 1 read-write 0 The buffer is not full and all write/read operations have no errors. #0 1 There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the buffer is busy). #1 DFEN Double Buffer Enable 2 1 read-write 0 Disables the double buffer mode; clock stretch is enabled. #0 1 Enables the double buffer mode; clock stretch is disabled. In the slave mode, the I2C will not hold bus between data transfers. #1 CMP0 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP0_ 0x40073000 0 0x6 registers CMP0 16 CR0 CMP Control Register 0 0 8 read-write 0 0xFF HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 The hard block output has no hysteresis internally. #00 01 Level 1 The hard block output has 20 mv hysteresis internally. #01 10 Level 2 The hard block output has 40 mv hysteresis internally. #10 11 Level 3 The hard block output has 60 mv hysteresis internally. #11 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. SE = 0, COUT = COUTA. #000 001 One sample must agree. The comparator output is simply sampled. #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 CR1 CMP Control Register 1 0x1 8 read-write 0 0xFF EN Comparator Module Enable 0 1 read-write 0 Analog Comparator is disabled. #0 1 Analog Comparator is enabled. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 CMPO is not available on the associated CMPO output pin. For devices that use explicit muxing control to I/O pin functions (DSC and non-Flexis ColdFire devices): If the comparator does not own the pin, this field has no effect. #0 1 CMPO is available on the associated CMPO output pin. For devices that use explicit muxing control to I/O pin functions (DSC and non-Flexis ColdFire devices): The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. #1 COS Comparator Output Select 2 1 read-write 0 Set the filtered comparator output (CMPO) to equal COUT. #0 1 Set the unfiltered comparator output (CMPO) to equal COUTA. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 PMODE Power Mode Select 4 1 read-write 0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 TRIGM Trigger Mode Enable 5 1 read-write 0 Trigger mode is disabled. #0 1 Trigger mode is enabled. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode is not selected. #0 1 Windowing mode is selected. #1 SE Sample Enable 7 1 read-write 0 Sampling mode is not selected. #0 1 Sampling mode is selected. #1 FPR CMP Filter Period Register 0x2 8 read-write 0 0xFF FILT_PER Filter Sample Period 0 8 read-write SCR CMP Status and Control Register 0x3 8 read-write 0 0xFF COUT Analog Comparator Output 0 1 read-only CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling-edge on COUT has not been detected. #0 1 Falling-edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising-edge on COUT has not been detected. #0 1 Rising-edge on COUT has occurred. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 DMAEN DMA Enable Control 6 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. #1 DACCR DAC Control Register 0x4 8 read-write 0 0xFF VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference. #0 1 Vin2 is selected as resistor ladder network supply reference. #1 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 MUXCR MUX Control Register 0x5 8 read-write 0 0xFF MSEL Minus Input Mux Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input Mux Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSTM Pass Through Mode Enable 7 1 read-write 0 Pass Through Mode is disabled. #0 1 Pass Through Mode is enabled. #1 LLWU Low leakage wakeup unit LLWU_ 0x4007C000 0 0xA registers LLWU 7 PE1 LLWU Pin Enable 1 register 0 8 read-write 0 0xFF WUPE0 Wakeup Pin Enable For LLWU_P0 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE1 Wakeup Pin Enable For LLWU_P1 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE2 Wakeup Pin Enable For LLWU_P2 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE3 Wakeup Pin Enable For LLWU_P3 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE2 LLWU Pin Enable 2 register 0x1 8 read-write 0 0xFF WUPE4 Wakeup Pin Enable For LLWU_P4 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE5 Wakeup Pin Enable For LLWU_P5 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE6 Wakeup Pin Enable For LLWU_P6 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE7 Wakeup Pin Enable For LLWU_P7 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE3 LLWU Pin Enable 3 register 0x2 8 read-write 0 0xFF WUPE8 Wakeup Pin Enable For LLWU_P8 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE9 Wakeup Pin Enable For LLWU_P9 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE10 Wakeup Pin Enable For LLWU_P10 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE11 Wakeup Pin Enable For LLWU_P11 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE4 LLWU Pin Enable 4 register 0x3 8 read-write 0 0xFF WUPE12 Wakeup Pin Enable For LLWU_P12 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE13 Wakeup Pin Enable For LLWU_P13 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE14 Wakeup Pin Enable For LLWU_P14 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE15 Wakeup Pin Enable For LLWU_P15 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 ME LLWU Module Enable register 0x4 8 read-write 0 0xFF WUME0 Wakeup Module Enable For Module 0 0 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME1 Wakeup Module Enable for Module 1 1 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME2 Wakeup Module Enable For Module 2 2 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME3 Wakeup Module Enable For Module 3 3 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME4 Wakeup Module Enable For Module 4 4 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME5 Wakeup Module Enable For Module 5 5 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME6 Wakeup Module Enable For Module 6 6 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME7 Wakeup Module Enable For Module 7 7 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 F1 LLWU Flag 1 register 0x5 8 read-write 0 0xFF WUF0 Wakeup Flag For LLWU_P0 0 1 read-write 0 LLWU_P0 input was not a wakeup source #0 1 LLWU_P0 input was a wakeup source #1 WUF1 Wakeup Flag For LLWU_P1 1 1 read-write 0 LLWU_P1 input was not a wakeup source #0 1 LLWU_P1 input was a wakeup source #1 WUF2 Wakeup Flag For LLWU_P2 2 1 read-write 0 LLWU_P2 input was not a wakeup source #0 1 LLWU_P2 input was a wakeup source #1 WUF3 Wakeup Flag For LLWU_P3 3 1 read-write 0 LLWU_P3 input was not a wake-up source #0 1 LLWU_P3 input was a wake-up source #1 WUF4 Wakeup Flag For LLWU_P4 4 1 read-write 0 LLWU_P4 input was not a wakeup source #0 1 LLWU_P4 input was a wakeup source #1 WUF5 Wakeup Flag For LLWU_P5 5 1 read-write 0 LLWU_P5 input was not a wakeup source #0 1 LLWU_P5 input was a wakeup source #1 WUF6 Wakeup Flag For LLWU_P6 6 1 read-write 0 LLWU_P6 input was not a wakeup source #0 1 LLWU_P6 input was a wakeup source #1 WUF7 Wakeup Flag For LLWU_P7 7 1 read-write 0 LLWU_P7 input was not a wakeup source #0 1 LLWU_P7 input was a wakeup source #1 F2 LLWU Flag 2 register 0x6 8 read-write 0 0xFF WUF8 Wakeup Flag For LLWU_P8 0 1 read-write 0 LLWU_P8 input was not a wakeup source #0 1 LLWU_P8 input was a wakeup source #1 WUF9 Wakeup Flag For LLWU_P9 1 1 read-write 0 LLWU_P9 input was not a wakeup source #0 1 LLWU_P9 input was a wakeup source #1 WUF10 Wakeup Flag For LLWU_P10 2 1 read-write 0 LLWU_P10 input was not a wakeup source #0 1 LLWU_P10 input was a wakeup source #1 WUF11 Wakeup Flag For LLWU_P11 3 1 read-write 0 LLWU_P11 input was not a wakeup source #0 1 LLWU_P11 input was a wakeup source #1 WUF12 Wakeup Flag For LLWU_P12 4 1 read-write 0 LLWU_P12 input was not a wakeup source #0 1 LLWU_P12 input was a wakeup source #1 WUF13 Wakeup Flag For LLWU_P13 5 1 read-write 0 LLWU_P13 input was not a wakeup source #0 1 LLWU_P13 input was a wakeup source #1 WUF14 Wakeup Flag For LLWU_P14 6 1 read-write 0 LLWU_P14 input was not a wakeup source #0 1 LLWU_P14 input was a wakeup source #1 WUF15 Wakeup Flag For LLWU_P15 7 1 read-write 0 LLWU_P15 input was not a wakeup source #0 1 LLWU_P15 input was a wakeup source #1 F3 LLWU Flag 3 register 0x7 8 read-only 0 0xFF MWUF0 Wakeup flag For module 0 0 1 read-only 0 Module 0 input was not a wakeup source #0 1 Module 0 input was a wakeup source #1 MWUF1 Wakeup flag For module 1 1 1 read-only 0 Module 1 input was not a wakeup source #0 1 Module 1 input was a wakeup source #1 MWUF2 Wakeup flag For module 2 2 1 read-only 0 Module 2 input was not a wakeup source #0 1 Module 2 input was a wakeup source #1 MWUF3 Wakeup flag For module 3 3 1 read-only 0 Module 3 input was not a wakeup source #0 1 Module 3 input was a wakeup source #1 MWUF4 Wakeup flag For module 4 4 1 read-only 0 Module 4 input was not a wakeup source #0 1 Module 4 input was a wakeup source #1 MWUF5 Wakeup flag For module 5 5 1 read-only 0 Module 5 input was not a wakeup source #0 1 Module 5 input was a wakeup source #1 MWUF6 Wakeup flag For module 6 6 1 read-only 0 Module 6 input was not a wakeup source #0 1 Module 6 input was a wakeup source #1 MWUF7 Wakeup flag For module 7 7 1 read-only 0 Module 7 input was not a wakeup source #0 1 Module 7 input was a wakeup source #1 FILT1 LLWU Pin Filter 1 register 0x8 8 read-write 0 0xFF FILTSEL Filter Pin Select 0 4 read-write 0000 Select LLWU_P0 for filter #0000 1111 Select LLWU_P15 for filter #1111 FILTE Digital Filter On External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 1 was not a wakeup source #0 1 Pin Filter 1 was a wakeup source #1 FILT2 LLWU Pin Filter 2 register 0x9 8 read-write 0 0xFF FILTSEL Filter Pin Select 0 4 read-write 0000 Select LLWU_P0 for filter #0000 1111 Select LLWU_P15 for filter #1111 FILTE Digital Filter On External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 2 was not a wakeup source #0 1 Pin Filter 2 was a wakeup source #1 PMC Power Management Controller PMC_ 0x4007D000 0 0x3 registers LVD_LVW_DCDC 6 LVDSC1 Low Voltage Detect Status And Control 1 register 0 8 read-write 0x10 0xFF LVDV Low-Voltage Detect Voltage Select 0 2 read-write 00 Low trip point selected (V LVD = V LVDL ) #00 01 High trip point selected (V LVD = V LVDH ) #01 11 NON-CUSTOMER INFO: High trip point selected (VLVD = VLVDH). Change 11 from reserved on 5V devices to high trip point. #11 LVDRE Low-Voltage Detect Reset Enable 4 1 read-write 0 LVDF does not generate hardware resets #0 1 Force an MCU reset when LVDF = 1 #1 LVDIE Low-Voltage Detect Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVDF = 1 #1 LVDACK Low-Voltage Detect Acknowledge 6 1 write-only LVDF Low-Voltage Detect Flag 7 1 read-only 0 Low-voltage event not detected #0 1 Low-voltage event detected #1 LVDSC2 Low Voltage Detect Status And Control 2 register 0x1 8 read-write 0 0xFF LVWV Low-Voltage Warning Voltage Select 0 2 read-write 00 Low trip point selected (VLVW = VLVW1) #00 01 Mid 1 trip point selected (VLVW = VLVW2) #01 10 Mid 2 trip point selected (VLVW = VLVW3) #10 11 High trip point selected (VLVW = VLVW4) #11 LVWIE Low-Voltage Warning Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVWF = 1 #1 LVWACK Low-Voltage Warning Acknowledge 6 1 write-only LVWF Low-Voltage Warning Flag 7 1 read-only 0 Low-voltage warning event not detected #0 1 Low-voltage warning event detected #1 REGSC Regulator Status And Control register 0x2 8 read-write 0x4 0xFF BGBE Bandgap Buffer Enable 0 1 read-write 0 Bandgap buffer not enabled #0 1 Bandgap buffer enabled #1 REGONS Regulator In Run Regulation Status 2 1 read-only 0 Regulator is in stop regulation or in transition to/from it #0 1 Regulator is in run regulation #1 ACKISO Acknowledge Isolation 3 1 read-write 0 Peripherals and I/O pads are in normal run state. #0 1 Certain peripherals and I/O pads are in an isolated and latched state. #1 VLPO VLPx Option 6 1 read-write 0 Operating frequencies and MCG clocking modes are restricted during VLPx modes as listed in the Power Management chapter. #0 1 If BGEN is also set, operating frequencies and MCG clocking modes are unrestricted during VLPx modes. Note that flash access frequency is still restricted however. #1 SMC System Mode Controller SMC_ 0x4007E000 0 0x4 registers PMPROT Power Mode Protection register 0 8 read-write 0 0xFF AVLLS Allow Very-Low-Leakage Stop Mode 1 1 read-write 0 Any VLLSx mode is not allowed #0 1 Any VLLSx mode is allowed #1 ALLS Allow Low-Leakage Stop Mode 3 1 read-write 0 Any LLSx mode is not allowed #0 1 Any LLSx mode is allowed #1 AVLP Allow Very-Low-Power Modes 5 1 read-write 0 VLPR, VLPW, and VLPS are not allowed. #0 1 VLPR, VLPW, and VLPS are allowed. #1 PMCTRL Power Mode Control register 0x1 8 read-write 0 0xFF STOPM Stop Mode Control 0 3 read-write 000 Normal Stop (STOP) #000 010 Very-Low-Power Stop (VLPS) #010 011 Low-Leakage Stop (LLSx) #011 100 Very-Low-Leakage Stop (VLLSx) #100 110 Reseved #110 STOPA Stop Aborted 3 1 read-only 0 The previous stop mode entry was successful. #0 1 The previous stop mode entry was aborted. #1 RUNM Run Mode Control 5 2 read-write 00 Normal Run mode (RUN) #00 10 Very-Low-Power Run mode (VLPR) #10 STOPCTRL Stop Control Register 0x2 8 read-write 0x3 0xFF LLSM LLS or VLLS Mode Control 0 3 read-write 000 VLLS0 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx #000 001 VLLS1 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx #001 010 VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx #010 011 VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx #011 PORPO POR Power Option 5 1 read-write 0 POR detect circuit is enabled in VLLS0 #0 1 POR detect circuit is disabled in VLLS0 #1 PSTOPO Partial Stop Option 6 2 read-write 00 STOP - Normal Stop mode #00 01 PSTOP1 - Partial Stop with both system and bus clocks disabled #01 10 PSTOP2 - Partial Stop with system clock disabled and bus clock enabled #10 PMSTAT Power Mode Status register 0x3 8 read-only 0x1 0xFF PMSTAT Power Mode Status 0 8 read-only RCM Reset Control Module RCM_ 0x4007F000 0 0x6 registers SRS0 System Reset Status Register 0 0 8 read-only 0x82 0xFF WAKEUP Low Leakage Wakeup Reset 0 1 read-only 0 Reset not caused by LLWU module wakeup source #0 1 Reset caused by LLWU module wakeup source #1 LVD Low-Voltage Detect Reset 1 1 read-only 0 Reset not caused by LVD trip or POR #0 1 Reset caused by LVD trip or POR #1 LOC Loss-of-Clock Reset 2 1 read-only 0 Reset not caused by a loss of external clock. #0 1 Reset caused by a loss of external clock. #1 WDOG Watchdog 5 1 read-only 0 Reset not caused by watchdog timeout #0 1 Reset caused by watchdog timeout #1 PIN External Reset Pin 6 1 read-only 0 Reset not caused by external reset pin #0 1 Reset caused by external reset pin #1 POR Power-On Reset 7 1 read-only 0 Reset not caused by POR #0 1 Reset caused by POR #1 SRS1 System Reset Status Register 1 0x1 8 read-only 0 0xFF LOCKUP Core Lockup 1 1 read-only 0 Reset not caused by core LOCKUP event #0 1 Reset caused by core LOCKUP event #1 SW Software 2 1 read-only 0 Reset not caused by software setting of SYSRESETREQ bit #0 1 Reset caused by software setting of SYSRESETREQ bit #1 MDM_AP MDM-AP System Reset Request 3 1 read-only 0 Reset not caused by host debugger system setting of the System Reset Request bit #0 1 Reset caused by host debugger system setting of the System Reset Request bit #1 SACKERR Stop Mode Acknowledge Error Reset 5 1 read-only 0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode #0 1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode #1 RPFC Reset Pin Filter Control register 0x4 8 read-write 0 0xFF RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes 0 2 read-write 00 All filtering disabled #00 01 Bus clock filter enabled for normal operation #01 10 LPO clock filter enabled for normal operation #10 11 Reserved (all filtering disabled) #11 RSTFLTSS Reset Pin Filter Select in Stop Mode 2 1 read-write 0 All filtering disabled #0 1 LPO clock filter enabled #1 RPFW Reset Pin Filter Width register 0x5 8 read-write 0 0xFF RSTFLTSEL Reset Pin Filter Bus Clock Select 0 5 read-write 00000 Bus clock filter count is 1 #00000 00001 Bus clock filter count is 2 #00001 00010 Bus clock filter count is 3 #00010 00011 Bus clock filter count is 4 #00011 00100 Bus clock filter count is 5 #00100 00101 Bus clock filter count is 6 #00101 00110 Bus clock filter count is 7 #00110 00111 Bus clock filter count is 8 #00111 01000 Bus clock filter count is 9 #01000 01001 Bus clock filter count is 10 #01001 01010 Bus clock filter count is 11 #01010 01011 Bus clock filter count is 12 #01011 01100 Bus clock filter count is 13 #01100 01101 Bus clock filter count is 14 #01101 01110 Bus clock filter count is 15 #01110 01111 Bus clock filter count is 16 #01111 10000 Bus clock filter count is 17 #10000 10001 Bus clock filter count is 18 #10001 10010 Bus clock filter count is 19 #10010 10011 Bus clock filter count is 20 #10011 10100 Bus clock filter count is 21 #10100 10101 Bus clock filter count is 22 #10101 10110 Bus clock filter count is 23 #10110 10111 Bus clock filter count is 24 #10111 11000 Bus clock filter count is 25 #11000 11001 Bus clock filter count is 26 #11001 11010 Bus clock filter count is 27 #11010 11011 Bus clock filter count is 28 #11011 11100 Bus clock filter count is 29 #11100 11101 Bus clock filter count is 30 #11101 11110 Bus clock filter count is 31 #11110 11111 Bus clock filter count is 32 #11111 GPIOA General Purpose Input/Output GPIO GPIOA_ 0x400FF000 0 0x18 registers PORTA 30 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOB General Purpose Input/Output GPIO GPIOB_ 0x400FF040 0 0x18 registers PORTB_PORTC 31 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOC General Purpose Input/Output GPIO GPIOC_ 0x400FF080 0 0x18 registers PORTB_PORTC 31 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 MTB Micro Trace Buffer MTB_ 0xF0000000 0 0x1000 registers POSITION MTB Position Register 0 32 read-write 0 0x3 WRAP WRAP 2 1 read-write POINTER Trace Packet Address Pointer[28:0] 3 29 read-write MASTER MTB Master Register 0x4 32 read-write 0x80 0xFFFFFFE0 MASK Mask 0 5 read-write TSTARTEN Trace Start Input Enable 5 1 read-write TSTOPEN Trace Stop Input Enable 6 1 read-write SFRWPRIV Special Function Register Write Privilege 7 1 read-write RAMPRIV RAM Privilege 8 1 read-write HALTREQ Halt Request 9 1 read-write EN Main Trace Enable 31 1 read-write FLOW MTB Flow Register 0x8 32 read-write 0 0x4 AUTOSTOP AUTOSTOP 0 1 read-write AUTOHALT AUTOHALT 1 1 read-write WATERMARK WATERMARK[28:0] 3 29 read-write BASE MTB Base Register 0xC 32 read-only 0 0 BASEADDR BASEADDR 0 32 read-only MODECTRL Integration Mode Control Register 0xF00 32 read-only 0 0xFFFFFFFF MODECTRL MODECTRL 0 32 read-only TAGSET Claim TAG Set Register 0xFA0 32 read-only 0 0xFFFFFFFF TAGSET TAGSET 0 32 read-only TAGCLEAR Claim TAG Clear Register 0xFA4 32 read-only 0 0xFFFFFFFF TAGCLEAR TAGCLEAR 0 32 read-only LOCKACCESS Lock Access Register 0xFB0 32 read-only 0 0xFFFFFFFF LOCKACCESS Hardwired to 0x0000_0000 0 32 read-only LOCKSTAT Lock Status Register 0xFB4 32 read-only 0 0xFFFFFFFF LOCKSTAT LOCKSTAT 0 32 read-only AUTHSTAT Authentication Status Register 0xFB8 32 read-only 0 0xFFFFFFFF BIT0 Connected to DBGEN. 0 1 read-only BIT1 BIT1 1 1 read-only BIT2 BIT2 2 1 read-only BIT3 BIT3 3 1 read-only DEVICEARCH Device Architecture Register 0xFBC 32 read-only 0x47700A31 0xFFFFFFFF DEVICEARCH DEVICEARCH 0 32 read-only DEVICECFG Device Configuration Register 0xFC8 32 read-only 0 0xFFFFFFFF DEVICECFG DEVICECFG 0 32 read-only DEVICETYPID Device Type Identifier Register 0xFCC 32 read-only 0x31 0xFFFFFFFF DEVICETYPID DEVICETYPID 0 32 read-only 8 0x4 4,5,6,7,0,1,2,3 PERIPHID%s Peripheral ID Register 0xFD0 32 read-only 0 0 PERIPHID PERIPHID 0 32 read-only 4 0x4 0,1,2,3 COMPID%s Component ID Register 0xFF0 32 read-only 0 0 COMPID Component ID 0 32 read-only MTBDWT MTB data watchpoint and trace MTBDWT_ 0xF0001000 0 0x1000 registers CTRL MTB DWT Control Register 0 32 read-only 0x2F000000 0xFFFFFFFF DWTCFGCTRL DWT configuration controls 0 28 read-only NUMCMP Number of comparators 28 4 read-only 2 0x10 0,1 COMP%s MTB_DWT Comparator Register 0x20 32 read-write 0 0xFFFFFFFF COMP Reference value for comparison 0 32 read-write 2 0x10 0,1 MASK%s MTB_DWT Comparator Mask Register 0x24 32 read-write 0 0xFFFFFFFF MASK MASK 0 5 read-write FCT0 MTB_DWT Comparator Function Register 0 0x28 32 read-write 0 0xFFFFFFFF FUNCTION Function 0 4 read-write 0000 Disabled. #0000 0100 Instruction fetch. #0100 0101 Data operand read. #0101 0110 Data operand write. #0110 0111 Data operand (read + write). #0111 DATAVMATCH Data Value Match 8 1 read-write 0 Perform address comparison. #0 1 Perform data value comparison. #1 DATAVSIZE Data Value Size 10 2 read-write 00 Byte. #00 01 Halfword. #01 10 Word. #10 11 Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. #11 DATAVADDR0 Data Value Address 0 12 4 read-write MATCHED Comparator match 24 1 read-only 0 No match. #0 1 Match occurred. #1 FCT1 MTB_DWT Comparator Function Register 1 0x38 32 read-write 0 0xFFFFFFFF FUNCTION Function 0 4 read-write 0000 Disabled. #0000 0100 Instruction fetch. #0100 0101 Data operand read. #0101 0110 Data operand write. #0110 0111 Data operand (read + write). #0111 MATCHED Comparator match 24 1 read-only 0 No match. #0 1 Match occurred. #1 TBCTRL MTB_DWT Trace Buffer Control Register 0x200 32 read-write 0x20000000 0xFFFFFFFF ACOMP0 Action based on Comparator 0 match 0 1 read-write 0 Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED]. #0 1 Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED]. #1 ACOMP1 Action based on Comparator 1 match 1 1 read-write 0 Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED]. #0 1 Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED]. #1 NUMCOMP Number of Comparators 28 4 read-only DEVICECFG Device Configuration Register 0xFC8 32 read-only 0 0xFFFFFFFF DEVICECFG DEVICECFG 0 32 read-only DEVICETYPID Device Type Identifier Register 0xFCC 32 read-only 0x4 0xFFFFFFFF DEVICETYPID DEVICETYPID 0 32 read-only 8 0x4 4,5,6,7,0,1,2,3 PERIPHID%s Peripheral ID Register 0xFD0 32 read-only 0 0 PERIPHID PERIPHID 0 32 read-only 4 0x4 0,1,2,3 COMPID%s Component ID Register 0xFF0 32 read-only 0 0 COMPID Component ID 0 32 read-only ROM System ROM ROM_ 0xF0002000 0 0x1000 registers 3 0x4 0,1,2 ENTRY%s Entry 0 32 read-only 0 0 ENTRY ENTRY 0 32 read-only TABLEMARK End of Table Marker Register 0xC 32 read-only 0 0xFFFFFFFF MARK MARK 0 32 read-only SYSACCESS System Access Register 0xFCC 32 read-only 0x1 0xFFFFFFFF SYSACCESS SYSACCESS 0 32 read-only 8 0x4 4,5,6,7,0,1,2,3 PERIPHID%s Peripheral ID Register 0xFD0 32 read-only 0 0 PERIPHID PERIPHID 0 32 read-only 4 0x4 0,1,2,3 COMPID%s Component ID Register 0xFF0 32 read-only 0 0 COMPID Component ID 0 32 read-only MCM Core Platform Miscellaneous Control Module MCM_ 0xF0003000 0x8 0x3C registers PLASC Crossbar Switch (AXBS) Slave Configuration 0x8 16 read-only 0x7 0xFFFF ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0 8 read-only 0 A bus slave connection to AXBS input port n is absent. #0 1 A bus slave connection to AXBS input port n is present. #1 PLAMC Crossbar Switch (AXBS) Master Configuration 0xA 16 read-only 0x5 0xFFFF AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 8 read-only 0 A bus master connection to AXBS input port n is absent #0 1 A bus master connection to AXBS input port n is present #1 PLACR Platform Control Register 0xC 32 read-write 0x50 0xFFFFFFFF ARB Arbitration select 9 1 read-write 0 Fixed-priority arbitration for the crossbar masters #0 1 Round-robin arbitration for the crossbar masters #1 CFCC Clear Flash Controller Cache 10 1 write-only DFCDA Disable Flash Controller Data Caching 11 1 read-write 0 Enable flash controller data caching #0 1 Disable flash controller data caching. #1 DFCIC Disable Flash Controller Instruction Caching 12 1 read-write 0 Enable flash controller instruction caching. #0 1 Disable flash controller instruction caching. #1 DFCC Disable Flash Controller Cache 13 1 read-write 0 Enable flash controller cache. #0 1 Disable flash controller cache. #1 EFDS Enable Flash Data Speculation 14 1 read-write 0 Disable flash data speculation. #0 1 Enable flash data speculation. #1 DFCS Disable Flash Controller Speculation 15 1 read-write 0 Enable flash controller speculation. #0 1 Disable flash controller speculation. #1 ESFC Enable Stalling Flash Controller 16 1 read-write 0 Disable stalling flash controller when flash is busy. #0 1 Enable stalling flash controller when flash is busy. #1 CPO Compute Operation Control Register 0x40 32 read-write 0 0xFFFFFFFF CPOREQ Compute Operation Request 0 1 read-write 0 Request is cleared. #0 1 Request Compute Operation. #1 CPOACK Compute Operation Acknowledge 1 1 read-only 0 Compute operation entry has not completed or compute operation exit has completed. #0 1 Compute operation entry has completed or compute operation exit has not completed. #1 CPOWOI Compute Operation Wake-up on Interrupt 2 1 read-write 0 No effect. #0 1 When set, the CPOREQ is cleared on any interrupt or exception vector fetch. #1 FGPIOA General Purpose Input/Output FGPIO FGPIOA_ 0xF8000000 0 0x18 registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 FGPIOB General Purpose Input/Output FGPIO FGPIOB_ 0xF8000040 0 0x18 registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 FGPIOC General Purpose Input/Output FGPIO FGPIOC_ 0xF8000080 0 0x18 registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1