Freescale Semiconductor, Inc. Freescale Kinetis_W MKW21Z4 1.6 MKW21Z4 Freescale Microcontroller Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. 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CM0PLUS r0p0 little false false true 2 false 8 32 FTFA_FlashConfig Flash configuration field NV_ 0x400 0 0xE registers BACKKEY3 Backdoor Comparison Key 3. 0 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY2 Backdoor Comparison Key 2. 0x1 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY1 Backdoor Comparison Key 1. 0x2 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY0 Backdoor Comparison Key 0. 0x3 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY7 Backdoor Comparison Key 7. 0x4 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY6 Backdoor Comparison Key 6. 0x5 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY5 Backdoor Comparison Key 5. 0x6 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY4 Backdoor Comparison Key 4. 0x7 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only FPROT3 Non-volatile P-Flash Protection 1 - Low Register 0x8 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FPROT2 Non-volatile P-Flash Protection 1 - High Register 0x9 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FPROT1 Non-volatile P-Flash Protection 0 - Low Register 0xA 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FPROT0 Non-volatile P-Flash Protection 0 - High Register 0xB 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FSEC Non-volatile Flash Security Register 0xC 8 read-only 0xFF 0xFF SEC Flash Security 0 2 read-only 10 MCU security status is unsecure #10 11 MCU security status is secure #11 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 10 Freescale factory access denied #10 11 Freescale factory access granted #11 MEEN no description available 4 2 read-only 10 Mass erase is disabled #10 11 Mass erase is enabled #11 KEYEN Backdoor Key Security Enable 6 2 read-only 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 FOPT Non-volatile Flash Option Register 0xD 8 read-only 0xFF 0xFF LPBOOT0 no description available 0 1 read-only 00 Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. #0 01 Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. #1 NMI_DIS no description available 2 1 read-only 00 NMI interrupts are always blocked #0 01 NMI_b pin/interrupts reset default to enabled #1 RESET_PIN_CFG no description available 3 1 read-only 00 RESET pin is disabled following a POR and cannot be enabled as reset function #0 01 RESET_b pin is dedicated #1 LPBOOT1 no description available 4 1 read-only 00 Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. #0 01 Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. #1 FAST_INIT no description available 5 1 read-only 00 Slower initialization #0 01 Fast Initialization #1 DMA Enhanced direct memory access controller DMA_ 0x40008000 0 0x1080 registers DMA0 0 DMA1 1 DMA2 2 DMA3 3 CR Control Register 0 32 read-write 0 0xFFFFFFFF EDBG Enable Debug 1 1 read-write 0 When in debug mode, the DMA continues to operate. #0 1 When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. #1 ERCA Enable Round Robin Channel Arbitration 2 1 read-write 0 Fixed priority arbitration is used for channel selection . #0 1 Round robin arbitration is used for channel selection . #1 HOE Halt On Error 4 1 read-write 0 Normal operation #0 1 Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. #1 HALT Halt DMA Operations 5 1 read-write 0 Normal operation #0 1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. #1 CLM Continuous Link Mode 6 1 read-write 0 A minor loop channel link made to itself goes through channel arbitration before being activated again. #0 1 A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. #1 EMLM Enable Minor Loop Mapping 7 1 read-write 0 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. #0 1 Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. #1 ECX Error Cancel Transfer 16 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. #1 CX Cancel Transfer 17 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. #1 ACTIVE DMA Active Status 31 1 read-only 0 eDMA is idle. #0 1 eDMA is executing a channel. #1 ES Error Status Register 0x4 32 read-only 0 0xFFFFFFFF DBE Destination Bus Error 0 1 read-only 0 No destination bus error #0 1 The last recorded error was a bus error on a destination write #1 SBE Source Bus Error 1 1 read-only 0 No source bus error #0 1 The last recorded error was a bus error on a source read #1 SGE Scatter/Gather Configuration Error 2 1 read-only 0 No scatter/gather configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. #1 NCE NBYTES/CITER Configuration Error 3 1 read-only 0 No NBYTES/CITER configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] #1 DOE Destination Offset Error 4 1 read-only 0 No destination offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. #1 DAE Destination Address Error 5 1 read-only 0 No destination address configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. #1 SOE Source Offset Error 6 1 read-only 0 No source offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. #1 SAE Source Address Error 7 1 read-only 0 No source address configuration error. #0 1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. #1 ERRCHN Error Channel Number or Canceled Channel Number 8 2 read-only CPE Channel Priority Error 14 1 read-only 0 No channel priority error #0 1 The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique. #1 ECX Transfer Canceled 16 1 read-only 0 No canceled transfers #0 1 The last recorded entry was a canceled transfer by the error cancel transfer input #1 VLD Logical OR of all ERR status bits 31 1 read-only 0 No ERR bits are set. #0 1 At least one ERR bit is set indicating a valid error exists that has not been cleared. #1 ERQ Enable Request Register 0xC 32 read-write 0 0xFFFFFFFF ERQ0 Enable DMA Request 0 0 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ1 Enable DMA Request 1 1 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ2 Enable DMA Request 2 2 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ3 Enable DMA Request 3 3 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 EEI Enable Error Interrupt Register 0x14 32 read-write 0 0xFFFFFFFF EEI0 Enable Error Interrupt 0 0 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI1 Enable Error Interrupt 1 1 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI2 Enable Error Interrupt 2 2 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI3 Enable Error Interrupt 3 3 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 CEEI Clear Enable Error Interrupt Register 0x18 8 write-only 0 0xFF CEEI Clear Enable Error Interrupt 0 2 write-only CAEE Clear All Enable Error Interrupts 6 1 write-only 0 Clear only the EEI bit specified in the CEEI field #0 1 Clear all bits in EEI #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SEEI Set Enable Error Interrupt Register 0x19 8 write-only 0 0xFF SEEI Set Enable Error Interrupt 0 2 write-only SAEE Sets All Enable Error Interrupts 6 1 write-only 0 Set only the EEI bit specified in the SEEI field. #0 1 Sets all bits in EEI #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERQ Clear Enable Request Register 0x1A 8 write-only 0 0xFF CERQ Clear Enable Request 0 2 write-only CAER Clear All Enable Requests 6 1 write-only 0 Clear only the ERQ bit specified in the CERQ field #0 1 Clear all bits in ERQ #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SERQ Set Enable Request Register 0x1B 8 write-only 0 0xFF SERQ Set Enable Request 0 2 write-only SAER Set All Enable Requests 6 1 write-only 0 Set only the ERQ bit specified in the SERQ field #0 1 Set all bits in ERQ #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CDNE Clear DONE Status Bit Register 0x1C 8 write-only 0 0xFF CDNE Clear DONE Bit 0 2 write-only CADN Clears All DONE Bits 6 1 write-only 0 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field #0 1 Clears all bits in TCDn_CSR[DONE] #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SSRT Set START Bit Register 0x1D 8 write-only 0 0xFF SSRT Set START Bit 0 2 write-only SAST Set All START Bits (activates all channels) 6 1 write-only 0 Set only the TCDn_CSR[START] bit specified in the SSRT field #0 1 Set all bits in TCDn_CSR[START] #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERR Clear Error Register 0x1E 8 write-only 0 0xFF CERR Clear Error Indicator 0 2 write-only CAEI Clear All Error Indicators 6 1 write-only 0 Clear only the ERR bit specified in the CERR field #0 1 Clear all bits in ERR #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CINT Clear Interrupt Request Register 0x1F 8 write-only 0 0xFF CINT Clear Interrupt Request 0 2 write-only CAIR Clear All Interrupt Requests 6 1 write-only 0 Clear only the INT bit specified in the CINT field #0 1 Clear all bits in INT #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 INT Interrupt Request Register 0x24 32 read-write 0 0xFFFFFFFF INT0 Interrupt Request 0 0 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT1 Interrupt Request 1 1 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT2 Interrupt Request 2 2 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT3 Interrupt Request 3 3 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 ERR Error Register 0x2C 32 read-write 0 0xFFFFFFFF ERR0 Error In Channel 0 0 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR1 Error In Channel 1 1 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR2 Error In Channel 2 2 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR3 Error In Channel 3 3 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 HRS Hardware Request Status Register 0x34 32 read-only 0 0xFFFFFFFF HRS0 Hardware Request Status Channel 0 0 1 read-only 0 A hardware service request for channel 0 is not present #0 1 A hardware service request for channel 0 is present #1 HRS1 Hardware Request Status Channel 1 1 1 read-only 0 A hardware service request for channel 1 is not present #0 1 A hardware service request for channel 1 is present #1 HRS2 Hardware Request Status Channel 2 2 1 read-only 0 A hardware service request for channel 2 is not present #0 1 A hardware service request for channel 2 is present #1 HRS3 Hardware Request Status Channel 3 3 1 read-only 0 A hardware service request for channel 3 is not present #0 1 A hardware service request for channel 3 is present #1 EARS Enable Asynchronous Request in Stop Register 0x44 32 read-write 0 0xFFFFFFFF EDREQ_0 Enable asynchronous DMA request in stop mode for channel 0. 0 1 read-write 0 Disable asynchronous DMA request for channel 0. #0 1 Enable asynchronous DMA request for channel 0. #1 EDREQ_1 Enable asynchronous DMA request in stop mode for channel 1. 1 1 read-write 0 Disable asynchronous DMA request for channel 1 #0 1 Enable asynchronous DMA request for channel 1. #1 EDREQ_2 Enable asynchronous DMA request in stop mode for channel 2. 2 1 read-write 0 Disable asynchronous DMA request for channel 2. #0 1 Enable asynchronous DMA request for channel 2. #1 EDREQ_3 Enable asynchronous DMA request in stop mode for channel 3. 3 1 read-write 0 Disable asynchronous DMA request for channel 3. #0 1 Enable asynchronous DMA request for channel 3. #1 4 0x1 3,2,1,0 DCHPRI%s Channel n Priority Register 0x100 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 2 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 4 0x20 0,1,2,3 TCD%s_SADDR TCD Source Address 0x1000 32 read-write 0 0 SADDR Source Address 0 32 read-write 4 0x20 0,1,2,3 TCD%s_SOFF TCD Signed Source Address Offset 0x1004 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write 4 0x20 0,1,2,3 TCD%s_ATTR TCD Transfer Attributes 0x1006 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 101 32-byte #101 SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 4 0x20 0,1,2,3 TCD%s_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write 4 0x20 0,1,2,3 TCD%s_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 4 0x20 0,1,2,3 TCD%s_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 4 0x20 0,1,2,3 TCD%s_SLAST TCD Last Source Address Adjustment 0x100C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write 4 0x20 0,1,2,3 TCD%s_DADDR TCD Destination Address 0x1010 32 read-write 0 0 DADDR Destination Address 0 32 read-write 4 0x20 0,1,2,3 TCD%s_DOFF TCD Signed Destination Address Offset 0x1014 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write 4 0x20 0,1,2,3 TCD%s_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1016 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 4 0x20 0,1,2,3 TCD%s_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1016 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 2 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 4 0x20 0,1,2,3 TCD%s_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1018 32 read-write 0 0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write 4 0x20 0,1,2,3 TCD%s_CSR TCD Control and Status 0x101C 16 read-write 0 0 START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 2 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 4 0x20 0,1,2,3 TCD%s_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x101E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 4 0x20 0,1,2,3 TCD%s_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x101E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 2 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 FTFA Flash Memory Interface FTFA_ 0x40020000 0 0x2C registers FTFA 5 FSTAT Flash Status Register 0 8 read-write 0 0xFF MGSTAT0 Memory Controller Command Completion Status Flag 0 1 read-only FPVIOL Flash Protection Violation Flag 4 1 read-write 0 No protection violation detected #0 1 Protection violation detected #1 ACCERR Flash Access Error Flag 5 1 read-write 0 No access error detected #0 1 Access error detected #1 RDCOLERR Flash Read Collision Error Flag 6 1 read-write 0 No collision error detected #0 1 Collision error detected #1 CCIF Command Complete Interrupt Flag 7 1 read-write 0 Flash command in progress #0 1 Flash command has completed #1 FCNFG Flash Configuration Register 0x1 8 read-write 0 0xFF ERSSUSP Erase Suspend 4 1 read-write 0 No suspend requested #0 1 Suspend the current Erase Flash Sector command execution. #1 ERSAREQ Erase All Request 5 1 read-only 0 No request or request complete #0 1 Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state. #1 RDCOLLIE Read Collision Error Interrupt Enable 6 1 read-write 0 Read collision error interrupt disabled #0 1 Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]). #1 CCIE Command Complete Interrupt Enable 7 1 read-write 0 Command complete interrupt disabled #0 1 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. #1 FSEC Flash Security Register 0x2 8 read-only 0 0 SEC Flash Security 0 2 read-only 00 MCU security status is secure. #00 01 MCU security status is secure. #01 10 MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.) #10 11 MCU security status is secure. #11 FSLACC Factory Security Level Access Code 2 2 read-only 00 NXP factory access granted #00 01 NXP factory access denied #01 10 NXP factory access denied #10 11 NXP factory access granted #11 MEEN Mass Erase Enable 4 2 read-only 00 Mass erase is enabled #00 01 Mass erase is enabled #01 10 Mass erase is disabled #10 11 Mass erase is enabled #11 KEYEN Backdoor Key Security Enable 6 2 read-only 00 Backdoor key access disabled #00 01 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) #01 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 FOPT Flash Option Register 0x3 8 read-only 0 0 OPT Nonvolatile Option 0 8 read-only 12 0x1 3,2,1,0,7,6,5,4,B,A,9,8 FCCOB%s Flash Common Command Object Registers 0x4 8 read-write 0 0xFF CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write 4 0x1 3,2,1,0 FPROT%s Program Flash Protection Registers 0x10 8 read-write 0 0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 8 0x1 H3,H2,H1,H0,L3,L2,L1,L0 XACC%s Execute-only Access Registers 0x18 8 read-only 0 0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 8 0x1 H3,H2,H1,H0,L3,L2,L1,L0 SACC%s Supervisor-only Access Registers 0x20 8 read-only 0 0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 FACSS Flash Access Segment Size Register 0x28 8 read-only 0 0 SGSIZE Segment Size 0 8 read-only FACSN Flash Access Segment Number Register 0x2B 8 read-only 0 0 NUMSG Number of Segments Indicator 0 8 read-only 100000 Program flash memory is divided into 32 segments (64 Kbytes, 128 Kbytes) #100000 101000 Program flash memory is divided into 40 segments (160 Kbytes) #101000 1000000 Program flash memory is divided into 64 segments (256 Kbytes, 512 Kbytes) #1000000 DMAMUX0 DMA channel multiplexor DMAMUX0_ 0x40021000 0 0x4 registers 4 0x1 0,1,2,3 CHCFG%s Channel Configuration register 0 8 read-write 0 0xFF SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 LPUART0_Rx_Signal #10 3 LPUART0_Tx_Signal #11 16 SPI0_Rx_Signal #10000 17 SPI0_Tx_Signal #10001 18 SPI1_Rx_Signal #10010 19 SPI1_Tx_Signal #10011 20 LTC0_Input_FIFO_Signal #10100 21 LTC0_Output_FIFO_Signal #10101 22 I2C0_Signal #10110 23 I2C1_Signal #10111 24 TPM0_Channel0_Signal #11000 25 TPM0_Channel1_Signal #11001 26 TPM0_Channel2_Signal #11010 27 TPM0_Channel3_Signal #11011 32 TPM1_Channel0_Signal #100000 33 TPM1_Channel1_Signal #100001 34 TPM2_Channel0_Signal #100010 35 TPM2_Channel1_Signal #100011 40 ADC0_Signal #101000 42 CMP0_Signal #101010 45 DAC0_Signal #101101 47 CMT_Signal #101111 49 PortA_Signal #110001 50 PortB_Signal #110010 51 PortC_Signal #110011 54 TPM0_Overflow_Signal #110110 55 TPM1_Overflow_Signal #110111 56 TPM2_Overflow_Signal #111000 57 TSI0_Signal #111001 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 TRNG0 TRNG0 0x40029000 0 0xF8 registers TRNG0 13 MCTL Miscellaneous Control Register 0 32 read-write 0x12001 0xFFFFFFFF SAMP_MODE Sample Mode 0 2 read-write 00 use Von Neumann data into both Entropy shifter and Statistical Checker #00 01 use raw data into both Entropy shifter and Statistical Checker #01 10 use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker #10 11 undefined/reserved. #11 OSC_DIV Oscillator Divide 2 2 read-write 00 use ring oscillator with no divide #00 01 use ring oscillator divided-by-2 #01 10 use ring oscillator divided-by-4 #10 11 use ring oscillator divided-by-8 #11 UNUSED This bit is unused but write-able. Must be left as zero. 4 1 read-write TRNG_ACC TRNG Access Mode 5 1 read-write RST_DEF Reset Defaults 6 1 write-only FOR_SCLK Force System Clock 7 1 read-write FCT_FAIL Read only: Frequency Count Fail 8 1 read-only FCT_VAL Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT. 9 1 read-only ENT_VAL Read only: Entropy Valid 10 1 read-only TST_OUT Read only: Test point inside ring oscillator. 11 1 read-only ERR Read: Error status 12 1 read-write TSTOP_OK TRNG_OK_TO_STOP 13 1 read-only PRGM Programming Mode Select 16 1 read-write SCMISC Statistical Check Miscellaneous Register 0x4 32 read-write 0x10022 0xFFFFFFFF LRUN_MAX LONG RUN MAX LIMIT 0 8 read-write RTY_CT RETRY COUNT 16 4 read-write PKRRNG Poker Range Register 0x8 32 read-write 0x9A3 0xFFFFFFFF PKR_RNG Poker Range 0 16 read-write PKRMAX Poker Maximum Limit Register TRNG0 0xC 32 read-write 0x6920 0xFFFFFFFF PKR_MAX Poker Maximum Limit. 0 24 read-write PKRSQ Poker Square Calculation Result Register TRNG0 0xC 32 read-only 0 0xFFFFFFFF PKR_SQ Poker Square Calculation Result. 0 24 read-only SDCTL Seed Control Register 0x10 32 read-write 0xC8009C4 0xFFFFFFFF SAMP_SIZE Sample Size 0 16 read-write ENT_DLY Entropy Delay 16 16 read-write SBLIM Sparse Bit Limit Register TRNG0 0x14 32 read-write 0x3F 0xFFFFFFFF SB_LIM Sparse Bit Limit 0 10 read-write TOTSAM Total Samples Register TRNG0 0x14 32 read-only 0 0xFFFFFFFF TOT_SAM Total Samples 0 20 read-only FRQMIN Frequency Count Minimum Limit Register 0x18 32 read-write 0x640 0xFFFFFFFF FRQ_MIN Frequency Count Minimum Limit 0 22 read-write FRQCNT Frequency Count Register TRNG0 0x1C 32 read-only 0 0xFFFFFFFF FRQ_CT Frequency Count 0 22 read-only FRQMAX Frequency Count Maximum Limit Register TRNG0 0x1C 32 read-write 0x6400 0xFFFFFFFF FRQ_MAX Frequency Counter Maximum Limit 0 22 read-write SCMC Statistical Check Monobit Count Register TRNG0 0x20 32 read-only 0 0xFFFFFFFF MONO_CT Monobit Count 0 16 read-only SCML Statistical Check Monobit Limit Register TRNG0 0x20 32 read-write 0x10C0568 0xFFFFFFFF MONO_MAX Monobit Maximum Limit 0 16 read-write MONO_RNG Monobit Range 16 16 read-write SCR1C Statistical Check Run Length 1 Count Register TRNG0 0x24 32 read-only 0 0xFFFFFFFF R1_0_CT Runs of Zero, Length 1 Count 0 15 read-only R1_1_CT Runs of One, Length 1 Count 16 15 read-only SCR1L Statistical Check Run Length 1 Limit Register TRNG0 0x24 32 read-write 0xB20195 0xFFFFFFFF RUN1_MAX Run Length 1 Maximum Limit 0 15 read-write RUN1_RNG Run Length 1 Range 16 15 read-write SCR2C Statistical Check Run Length 2 Count Register TRNG0 0x28 32 read-only 0 0xFFFFFFFF R2_0_CT Runs of Zero, Length 2 Count 0 14 read-only R2_1_CT Runs of One, Length 2 Count 16 14 read-only SCR2L Statistical Check Run Length 2 Limit Register TRNG0 0x28 32 read-write 0x7A00DC 0xFFFFFFFF RUN2_MAX Run Length 2 Maximum Limit 0 14 read-write RUN2_RNG Run Length 2 Range 16 14 read-write SCR3C Statistical Check Run Length 3 Count Register TRNG0 0x2C 32 read-only 0 0xFFFFFFFF R3_0_CT Runs of Zeroes, Length 3 Count 0 13 read-only R3_1_CT Runs of Ones, Length 3 Count 16 13 read-only SCR3L Statistical Check Run Length 3 Limit Register TRNG0 0x2C 32 read-write 0x58007D 0xFFFFFFFF RUN3_MAX Run Length 3 Maximum Limit 0 13 read-write RUN3_RNG Run Length 3 Range 16 13 read-write SCR4C Statistical Check Run Length 4 Count Register TRNG0 0x30 32 read-only 0 0xFFFFFFFF R4_0_CT Runs of Zero, Length 4 Count 0 12 read-only R4_1_CT Runs of One, Length 4 Count 16 12 read-only SCR4L Statistical Check Run Length 4 Limit Register TRNG0 0x30 32 read-write 0x40004B 0xFFFFFFFF RUN4_MAX Run Length 4 Maximum Limit 0 12 read-write RUN4_RNG Run Length 4 Range 16 12 read-write SCR5C Statistical Check Run Length 5 Count Register TRNG0 0x34 32 read-only 0 0xFFFFFFFF R5_0_CT Runs of Zero, Length 5 Count 0 11 read-only R5_1_CT Runs of One, Length 5 Count 16 11 read-only SCR5L Statistical Check Run Length 5 Limit Register TRNG0 0x34 32 read-write 0x2E002F 0xFFFFFFFF RUN5_MAX Run Length 5 Maximum Limit 0 11 read-write RUN5_RNG Run Length 5 Range 16 11 read-write SCR6PC Statistical Check Run Length 6+ Count Register TRNG0 0x38 32 read-only 0 0xFFFFFFFF R6P_0_CT Runs of Zero, Length 6+ Count 0 11 read-only R6P_1_CT Runs of One, Length 6+ Count 16 11 read-only SCR6PL Statistical Check Run Length 6+ Limit Register TRNG0 0x38 32 read-write 0x2E002F 0xFFFFFFFF RUN6P_MAX Run Length 6+ Maximum Limit 0 11 read-write RUN6P_RNG Run Length 6+ Range 16 11 read-write STATUS Status Register 0x3C 32 read-only 0 0xFFFFFFFF TF1BR0 Test Fail, 1-Bit Run, Sampling 0s. If TF1BR0=1, the 1-Bit Run, Sampling 0s Test has failed. 0 1 read-only TF1BR1 Test Fail, 1-Bit Run, Sampling 1s. If TF1BR1=1, the 1-Bit Run, Sampling 1s Test has failed. 1 1 read-only TF2BR0 Test Fail, 2-Bit Run, Sampling 0s. If TF2BR0=1, the 2-Bit Run, Sampling 0s Test has failed. 2 1 read-only TF2BR1 Test Fail, 2-Bit Run, Sampling 1s. If TF2BR1=1, the 2-Bit Run, Sampling 1s Test has failed. 3 1 read-only TF3BR0 Test Fail, 3-Bit Run, Sampling 0s. If TF3BR0=1, the 3-Bit Run, Sampling 0s Test has failed. 4 1 read-only TF3BR1 Test Fail, 3-Bit Run, Sampling 1s. If TF3BR1=1, the 3-Bit Run, Sampling 1s Test has failed. 5 1 read-only TF4BR0 Test Fail, 4-Bit Run, Sampling 0s. If TF4BR0=1, the 4-Bit Run, Sampling 0s Test has failed. 6 1 read-only TF4BR1 Test Fail, 4-Bit Run, Sampling 1s. If TF4BR1=1, the 4-Bit Run, Sampling 1s Test has failed. 7 1 read-only TF5BR0 Test Fail, 5-Bit Run, Sampling 0s. If TF5BR0=1, the 5-Bit Run, Sampling 0s Test has failed. 8 1 read-only TF5BR1 Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed. 9 1 read-only TF6PBR0 Test Fail, 6 Plus Bit Run, Sampling 0s 10 1 read-only TF6PBR1 Test Fail, 6 Plus Bit Run, Sampling 1s 11 1 read-only TFSB Test Fail, Sparse Bit. If TFSB=1, the Sparse Bit Test has failed. 12 1 read-only TFLR Test Fail, Long Run. If TFLR=1, the Long Run Test has failed. 13 1 read-only TFP Test Fail, Poker. If TFP=1, the Poker Test has failed. 14 1 read-only TFMB Test Fail, Mono Bit. If TFMB=1, the Mono Bit Test has failed. 15 1 read-only RETRY_CT RETRY COUNT 16 4 read-only ENT0 Entropy Read Register 0x40 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only ENT1 Entropy Read Register 0x44 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only ENT2 Entropy Read Register 0x48 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only ENT3 Entropy Read Register 0x4C 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only ENT4 Entropy Read Register 0x50 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only ENT5 Entropy Read Register 0x54 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only ENT6 Entropy Read Register 0x58 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only ENT7 Entropy Read Register 0x5C 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only ENT8 Entropy Read Register 0x60 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only ENT9 Entropy Read Register 0x64 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only ENT10 Entropy Read Register 0x68 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only ENT11 Entropy Read Register 0x6C 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only ENT12 Entropy Read Register 0x70 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only ENT13 Entropy Read Register 0x74 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only ENT14 Entropy Read Register 0x78 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only ENT15 Entropy Read Register 0x7C 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only PKRCNT10 Statistical Check Poker Count 1 and 0 Register 0x80 32 read-only 0 0xFFFFFFFF PKR_0_CT Poker 0h Count 0 16 read-only PKR_1_CT Poker 1h Count 16 16 read-only PKRCNT32 Statistical Check Poker Count 3 and 2 Register 0x84 32 read-only 0 0xFFFFFFFF PKR_2_CT Poker 2h Count 0 16 read-only PKR_3_CT Poker 3h Count 16 16 read-only PKRCNT54 Statistical Check Poker Count 5 and 4 Register 0x88 32 read-only 0 0xFFFFFFFF PKR_4_CT Poker 4h Count 0 16 read-only PKR_5_CT Poker 5h Count 16 16 read-only PKRCNT76 Statistical Check Poker Count 7 and 6 Register 0x8C 32 read-only 0 0xFFFFFFFF PKR_6_CT Poker 6h Count 0 16 read-only PKR_7_CT Poker 7h Count 16 16 read-only PKRCNT98 Statistical Check Poker Count 9 and 8 Register 0x90 32 read-only 0 0xFFFFFFFF PKR_8_CT Poker 8h Count 0 16 read-only PKR_9_CT Poker 9h Count 16 16 read-only PKRCNTBA Statistical Check Poker Count B and A Register 0x94 32 read-only 0 0xFFFFFFFF PKR_A_CT Poker Ah Count 0 16 read-only PKR_B_CT Poker Bh Count 16 16 read-only PKRCNTDC Statistical Check Poker Count D and C Register 0x98 32 read-only 0 0xFFFFFFFF PKR_C_CT Poker Ch Count 0 16 read-only PKR_D_CT Poker Dh Count 16 16 read-only PKRCNTFE Statistical Check Poker Count F and E Register 0x9C 32 read-only 0 0xFFFFFFFF PKR_E_CT Poker Eh Count 0 16 read-only PKR_F_CT Poker Fh Count 16 16 read-only SEC_CFG Security Configuration Register 0xB0 32 read-write 0 0xFFFFFFFF SH0 Reserved. DRNG specific, not applicable to this version. 0 1 read-write 0 See DRNG version. #0 1 See DRNG version. #1 NO_PRGM If set, the TRNG registers cannot be programmed 1 1 read-write 0 Programability of registers controlled only by the Miscellaneous Control Register's access mode bit. #0 1 Overides Miscellaneous Control Register access mode and prevents TRNG register programming. #1 SK_VAL Reserved. DRNG-specific, not applicable to this version. 2 1 read-write 0 See DRNG version. #0 1 See DRNG version. #1 INT_CTRL Interrupt Control Register 0xB4 32 read-write 0xFFFFFFFF 0xFFFFFFFF HW_ERR Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. 0 1 read-write 0 Corresponding bit of INT_STATUS cleared. #0 1 Corresponding bit of INT_STATUS active. #1 ENT_VAL Same behavior as bit 0 above. 1 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 FRQ_CT_FAIL Same behavior as bit 0 above. 2 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 UNUSED Reserved but writeable. 3 29 read-write INT_MASK Mask Register 0xB8 32 read-write 0 0xFFFFFFFF HW_ERR Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. 0 1 read-write 0 Corresponding interrupt of INT_STATUS is masked. #0 1 Corresponding bit of INT_STATUS is active. #1 ENT_VAL Same behavior as bit 0 above. 1 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 FRQ_CT_FAIL Same behavior as bit 0 above. 2 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 INT_STATUS Interrupt Status Register 0xBC 32 read-write 0 0xFFFFFFFF HW_ERR Read: Error status 0 1 read-only 0 no error #0 1 error detected. #1 ENT_VAL Read only: Entropy Valid 1 1 read-only 0 Busy generation entropy. Any value read is invalid. #0 1 TRNG can be stopped and entropy is valid if read. #1 FRQ_CT_FAIL Read only: Frequency Count Fail 2 1 read-write 0 No hardware nor self test frequency errors. #0 1 The frequency counter has detected a failure. #1 VID1 Version ID Register (MS) 0xF0 32 read-only 0x300100 0xFFFFFFFF MIN_REV Shows the Freescale IP's Minor revision of the TRNG. 0 8 read-only 0x00 Minor revision number for TRNG. #0 MAJ_REV Shows the Freescale IP's Major revision of the TRNG. 8 8 read-only 0x01 Major revision number for TRNG. #1 IP_ID Shows the Freescale IP ID. 16 16 read-only 0x0030 ID for TRNG. #110000 VID2 Version ID Register (LS) 0xF4 32 read-only 0x300100 0xFFFFFFFF CONFIG_OPT Shows the Freescale IP's Configuaration options for the TRNG. 0 8 read-only 0x00 TRNG_CONFIG_OPT for TRNG. #0 ECO_REV Shows the Freescale IP's ECO revision of the TRNG. 8 8 read-only 0x00 TRNG_ECO_REV for TRNG. #0 INTG_OPT Shows the Freescale integration options for the TRNG. 16 8 read-only 0x00 INTG_OPT for TRNG. #0 ERA Shows the Freescale compile options for the TRNG. 24 8 read-only 0x00 COMPILE_OPT for TRNG. #0 SPI0 Serial Peripheral Interface SPI SPI0_ 0x4002C000 0 0x8C registers SPI0 10 MCR Module Configuration Register 0 32 read-write 0x4001 0xFFFFFFFF HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 SMPL_PT Sample Point 8 2 read-write 00 0 protocol clock cycles between SCK edge and SIN sample #00 01 1 protocol clock cycle between SCK edge and SIN sample #01 10 2 protocol clock cycles between SCK edge and SIN sample #10 CLR_RXF CLR_RXF 10 1 write-only 0 Do not clear the RX FIFO counter. #0 1 Clear the RX FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the TX FIFO counter. #0 1 Clear the TX FIFO counter. #1 DIS_RXF Disable Receive FIFO 12 1 read-write 0 RX FIFO is enabled. #0 1 RX FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 TX FIFO is enabled. #0 1 TX FIFO is disabled. #1 MDIS Module Disable 14 1 read-write 0 Enables the module clocks. #0 1 Allows external logic to disable the module clocks. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on the module. #0 1 Doze mode disables the module. #1 PCSIS Peripheral Chip Select x Inactive State 16 4 read-write 0 The inactive state of PCSx is low. #0000 1 The inactive state of PCSx is high. #0001 ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 MTFE Modified Transfer Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in Debug mode. #0 1 Halt serial transfers in Debug mode. #1 DCONF SPI Configuration. 28 2 read-only 00 SPI #00 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 Enables Slave mode #0 1 Enables Master mode #1 TCR Transfer Count Register 0x8 32 read-write 0 0xFFFFFFFF SPI_TCNT SPI Transfer Counter 16 16 read-write 2 0x4 0,1 CTAR%s Clock and Transfer Attributes Register (In Master Mode) SPI0 0xC 32 read-write 0x78000000 0xFFFFFFFF BR Baud Rate Scaler 0 4 read-write DT Delay After Transfer Scaler 4 4 read-write ASC After SCK Delay Scaler 8 4 read-write CSSCK PCS to SCK Delay Scaler 12 4 read-write PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 CTAR_SLAVE Clock and Transfer Attributes Register (In Slave Mode) SPI0 0xC 32 read-write 0x78000000 0xFFFFFFFF CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write SR Status Register 0x2C 32 read-write 0x2000000 0xFFFFFFFF POPNXTPTR Pop Next Pointer 0 4 read-only RXCTR RX FIFO Counter 4 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXCTR TX FIFO Counter 12 4 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 RX FIFO is empty. #0 1 RX FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 TX FIFO is full. #0 1 TX FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No TX FIFO underflow. #0 1 TX FIFO underflow has occurred. #1 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 TXRXS TX and RX Status 30 1 read-only 0 Transmit and receive operations are disabled (The module is in Stopped state). #0 1 Transmit and receive operations are enabled (The module is in Running state). #1 TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 RSER DMA/Interrupt Request Select and Enable Register 0x30 32 read-write 0 0xFFFFFFFF RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled. #0 1 RFDF interrupt or DMA requests are enabled. #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 EOQF_RE Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 PUSHR PUSH TX FIFO Register In Master Mode SPI0 0x34 32 read-write 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-write PCS Select which PCS signals are to be asserted for the transfer 16 4 read-write 0 Negate the PCS[x] signal #0000 1 Assert the PCS[x] signal. #0001 CTCNT Clear Transfer Counter 26 1 read-write 0 Do not clear the TCR[TCNT] field. #0 1 Clear the TCR[TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 CTAS Clock and Transfer Attributes Select 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 PUSHR_SLAVE PUSH TX FIFO Register In Slave Mode SPI0 0x34 32 read-write 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-write POPR POP RX FIFO Register 0x38 32 read-only 0 0xFFFFFFFF RXDATA Received Data 0 32 read-only 4 0x4 0,1,2,3 TXFR%s Transmit FIFO Registers 0x3C 32 read-only 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-only TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only 4 0x4 0,1,2,3 RXFR%s Receive FIFO Registers 0x7C 32 read-only 0 0xFFFFFFFF RXDATA Receive Data 0 32 read-only SPI1 Serial Peripheral Interface SPI SPI1_ 0x4002D000 0 0x8C registers SPI1 29 MCR Module Configuration Register 0 32 read-write 0x4001 0xFFFFFFFF HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 SMPL_PT Sample Point 8 2 read-write 00 0 protocol clock cycles between SCK edge and SIN sample #00 01 1 protocol clock cycle between SCK edge and SIN sample #01 10 2 protocol clock cycles between SCK edge and SIN sample #10 CLR_RXF CLR_RXF 10 1 write-only 0 Do not clear the RX FIFO counter. #0 1 Clear the RX FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the TX FIFO counter. #0 1 Clear the TX FIFO counter. #1 DIS_RXF Disable Receive FIFO 12 1 read-write 0 RX FIFO is enabled. #0 1 RX FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 TX FIFO is enabled. #0 1 TX FIFO is disabled. #1 MDIS Module Disable 14 1 read-write 0 Enables the module clocks. #0 1 Allows external logic to disable the module clocks. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on the module. #0 1 Doze mode disables the module. #1 PCSIS Peripheral Chip Select x Inactive State 16 4 read-write 0 The inactive state of PCSx is low. #0000 1 The inactive state of PCSx is high. #0001 ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 MTFE Modified Transfer Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in Debug mode. #0 1 Halt serial transfers in Debug mode. #1 DCONF SPI Configuration. 28 2 read-only 00 SPI #00 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 Enables Slave mode #0 1 Enables Master mode #1 TCR Transfer Count Register 0x8 32 read-write 0 0xFFFFFFFF SPI_TCNT SPI Transfer Counter 16 16 read-write 2 0x4 0,1 CTAR%s Clock and Transfer Attributes Register (In Master Mode) SPI1 0xC 32 read-write 0x78000000 0xFFFFFFFF BR Baud Rate Scaler 0 4 read-write DT Delay After Transfer Scaler 4 4 read-write ASC After SCK Delay Scaler 8 4 read-write CSSCK PCS to SCK Delay Scaler 12 4 read-write PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 CTAR_SLAVE Clock and Transfer Attributes Register (In Slave Mode) SPI1 0xC 32 read-write 0x78000000 0xFFFFFFFF CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write SR Status Register 0x2C 32 read-write 0x2000000 0xFFFFFFFF POPNXTPTR Pop Next Pointer 0 4 read-only RXCTR RX FIFO Counter 4 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXCTR TX FIFO Counter 12 4 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 RX FIFO is empty. #0 1 RX FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 TX FIFO is full. #0 1 TX FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No TX FIFO underflow. #0 1 TX FIFO underflow has occurred. #1 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 TXRXS TX and RX Status 30 1 read-only 0 Transmit and receive operations are disabled (The module is in Stopped state). #0 1 Transmit and receive operations are enabled (The module is in Running state). #1 TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 RSER DMA/Interrupt Request Select and Enable Register 0x30 32 read-write 0 0xFFFFFFFF RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled. #0 1 RFDF interrupt or DMA requests are enabled. #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 EOQF_RE Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 PUSHR PUSH TX FIFO Register In Master Mode SPI1 0x34 32 read-write 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-write PCS Select which PCS signals are to be asserted for the transfer 16 4 read-write 0 Negate the PCS[x] signal #0000 1 Assert the PCS[x] signal. #0001 CTCNT Clear Transfer Counter 26 1 read-write 0 Do not clear the TCR[TCNT] field. #0 1 Clear the TCR[TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 CTAS Clock and Transfer Attributes Select 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 PUSHR_SLAVE PUSH TX FIFO Register In Slave Mode SPI1 0x34 32 read-write 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-write POPR POP RX FIFO Register 0x38 32 read-only 0 0xFFFFFFFF RXDATA Received Data 0 32 read-only 4 0x4 0,1,2,3 TXFR%s Transmit FIFO Registers 0x3C 32 read-only 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-only TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only 4 0x4 0,1,2,3 RXFR%s Receive FIFO Registers 0x7C 32 read-only 0 0xFFFFFFFF RXDATA Receive Data 0 32 read-only PIT Periodic Interrupt Timer PIT_ 0x40037000 0 0x120 registers PIT 22 MCR PIT Module Control Register 0 32 read-write 0x6 0xFFFFFFFF FRZ Freeze 0 1 read-write 0 Timers continue to run in Debug mode. #0 1 Timers are stopped in Debug mode. #1 MDIS Module Disable - (PIT section) 1 1 read-write 0 Clock for standard PIT timers is enabled. #0 1 Clock for standard PIT timers is disabled. #1 LTMR64H PIT Upper Lifetime Timer Register 0xE0 32 read-only 0 0xFFFFFFFF LTH Life Timer value 0 32 read-only LTMR64L PIT Lower Lifetime Timer Register 0xE4 32 read-only 0 0xFFFFFFFF LTL Life Timer value 0 32 read-only 2 0x10 0,1 LDVAL%s Timer Load Value Register 0x100 32 read-write 0 0xFFFFFFFF TSV Timer Start Value 0 32 read-write 2 0x10 0,1 CVAL%s Current Timer Value Register 0x104 32 read-only 0 0xFFFFFFFF TVL Current Timer Value 0 32 read-only 2 0x10 0,1 TCTRL%s Timer Control Register 0x108 32 read-write 0 0xFFFFFFFF TEN Timer Enable 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is enabled. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 CHN Chain Mode 2 1 read-write 0 Timer is not chained. #0 1 Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. #1 2 0x10 0,1 TFLG%s Timer Flag Register 0x10C 32 read-write 0 0xFFFFFFFF TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 TPM0 Timer/PWM Module TPM TPM0_ 0x40038000 0 0x88 registers TPM0 17 SC Status and Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CMOD Clock Mode Selection 3 2 read-write 00 TPM counter is disabled #00 01 TPM counter increments on every TPM counter clock #01 10 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock #10 CPWMS Center-Aligned PWM Select 5 1 read-write 0 TPM counter operates in up counting mode. #0 1 TPM counter operates in up-down counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling or DMA request. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 DMA DMA Enable 8 1 read-write 0 Disables DMA transfers. #0 1 Enables DMA transfers. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter value 0 16 read-write MOD Modulo 0x8 32 read-write 0xFFFF 0xFFFFFFFF MOD Modulo value 0 16 read-write 4 0x8 0,1,2,3 C%sSC Channel (n) Status and Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 4 0x8 0,1,2,3 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write STATUS Capture and Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 TOF Timer Overflow Flag 8 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 COMBINE Combine Channel Register 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels 0 and 1 0 1 read-write 0 Channels 0 and 1 are independent. #0 1 Channels 0 and 1 are combined. #1 COMSWAP0 Combine Channel 0 and 1 Swap 1 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 COMBINE1 Combine Channels 2 and 3 8 1 read-write 0 Channels 2 and 3 are independent. #0 1 Channels 2 and 3 are combined. #1 COMSWAP1 Combine Channels 2 and 3 Swap 9 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 POL Channel Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FILTER Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Filter Value 0 4 read-write CH1FVAL Channel 1 Filter Value 4 4 read-write CH2FVAL Channel 2 Filter Value 8 4 read-write CH3FVAL Channel 3 Filter Value 12 4 read-write QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Enables the quadrature decoder mode 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 TOFDIR Indicates if the TOF bit was set on the top or the bottom of counting. 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). #1 QUADIR Counter Direction in Quadrature Decode Mode 2 1 read-only 0 Counter direction is decreasing (counter decrement). #0 1 Counter direction is increasing (counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase encoding mode. #0 1 Count and direction encoding mode. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF DOZEEN Doze Enable 5 1 read-write 0 Internal TPM counter continues in Doze mode. #0 1 Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. #1 DBGMODE Debug Mode 6 2 read-write 00 TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. #00 11 TPM counter continues in debug mode. #11 GTBSYNC Global Time Base Synchronization 8 1 read-write 0 Global timebase synchronization disabled. #0 1 Global timebase synchronization enabled. #1 GTBEEN Global time base enable 9 1 read-write 0 All channels use the internally generated TPM counter as their timebase #0 1 All channels use an externally generated global timebase as their timebase #1 CSOT Counter Start on Trigger 16 1 read-write 0 TPM counter starts to increment immediately, once it is enabled. #0 1 TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. #1 CSOO Counter Stop On Overflow 17 1 read-write 0 TPM counter continues incrementing or decrementing after overflow #0 1 TPM counter stops incrementing or decrementing after overflow. #1 CROT Counter Reload On Trigger 18 1 read-write 0 Counter is not reloaded due to a rising edge on the selected input trigger #0 1 Counter is reloaded when a rising edge is detected on the selected input trigger #1 CPOT Counter Pause On Trigger 19 1 read-write TRGPOL Trigger Polarity 22 1 read-write 0 Trigger is active high. #0 1 Trigger is active low. #1 TRGSRC Trigger Source 23 1 read-write 0 Trigger source selected by TRGSEL is external. #0 1 Trigger source selected by TRGSEL is internal (channel pin input capture). #1 TRGSEL Trigger Select 24 4 read-write 0001 Channel 0 pin input capture #0001 0010 Channel 1 pin input capture #0010 0011 Channel 0 or Channel 1 pin input capture #0011 0100 Channel 2 pin input capture #0100 0101 Channel 0 or Channel 2 pin input capture #0101 0110 Channel 1 or Channel 2 pin input capture #0110 0111 Channel 0 or Channel 1 or Channel 2 pin input capture #0111 1000 Channel 3 pin input capture #1000 1001 Channel 0 or Channel 3 pin input capture #1001 1010 Channel 1 or Channel 3 pin input capture #1010 1011 Channel 0 or Channel 1 or Channel 3 pin input capture #1011 1100 Channel 2 or Channel 3 pin input capture #1100 1101 Channel 0 or Channel 2 or Channel 3 pin input capture #1101 1110 Channel 1 or Channel 2 or Channel 3 pin input capture #1110 1111 Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture #1111 TPM1 Timer/PWM Module TPM TPM1_ 0x40039000 0 0x88 registers TPM1 18 SC Status and Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CMOD Clock Mode Selection 3 2 read-write 00 TPM counter is disabled #00 01 TPM counter increments on every TPM counter clock #01 10 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock #10 CPWMS Center-Aligned PWM Select 5 1 read-write 0 TPM counter operates in up counting mode. #0 1 TPM counter operates in up-down counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling or DMA request. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 DMA DMA Enable 8 1 read-write 0 Disables DMA transfers. #0 1 Enables DMA transfers. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter value 0 16 read-write MOD Modulo 0x8 32 read-write 0xFFFF 0xFFFFFFFF MOD Modulo value 0 16 read-write 2 0x8 0,1 C%sSC Channel (n) Status and Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 2 0x8 0,1 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write STATUS Capture and Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 TOF Timer Overflow Flag 8 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 COMBINE Combine Channel Register 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels 0 and 1 0 1 read-write 0 Channels 0 and 1 are independent. #0 1 Channels 0 and 1 are combined. #1 COMSWAP0 Combine Channel 0 and 1 Swap 1 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 COMBINE1 Combine Channels 2 and 3 8 1 read-write 0 Channels 2 and 3 are independent. #0 1 Channels 2 and 3 are combined. #1 COMSWAP1 Combine Channels 2 and 3 Swap 9 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 POL Channel Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FILTER Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Filter Value 0 4 read-write CH1FVAL Channel 1 Filter Value 4 4 read-write CH2FVAL Channel 2 Filter Value 8 4 read-write CH3FVAL Channel 3 Filter Value 12 4 read-write QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Enables the quadrature decoder mode 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 TOFDIR Indicates if the TOF bit was set on the top or the bottom of counting. 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). #1 QUADIR Counter Direction in Quadrature Decode Mode 2 1 read-only 0 Counter direction is decreasing (counter decrement). #0 1 Counter direction is increasing (counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase encoding mode. #0 1 Count and direction encoding mode. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF DOZEEN Doze Enable 5 1 read-write 0 Internal TPM counter continues in Doze mode. #0 1 Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. #1 DBGMODE Debug Mode 6 2 read-write 00 TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. #00 11 TPM counter continues in debug mode. #11 GTBSYNC Global Time Base Synchronization 8 1 read-write 0 Global timebase synchronization disabled. #0 1 Global timebase synchronization enabled. #1 GTBEEN Global time base enable 9 1 read-write 0 All channels use the internally generated TPM counter as their timebase #0 1 All channels use an externally generated global timebase as their timebase #1 CSOT Counter Start on Trigger 16 1 read-write 0 TPM counter starts to increment immediately, once it is enabled. #0 1 TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. #1 CSOO Counter Stop On Overflow 17 1 read-write 0 TPM counter continues incrementing or decrementing after overflow #0 1 TPM counter stops incrementing or decrementing after overflow. #1 CROT Counter Reload On Trigger 18 1 read-write 0 Counter is not reloaded due to a rising edge on the selected input trigger #0 1 Counter is reloaded when a rising edge is detected on the selected input trigger #1 CPOT Counter Pause On Trigger 19 1 read-write TRGPOL Trigger Polarity 22 1 read-write 0 Trigger is active high. #0 1 Trigger is active low. #1 TRGSRC Trigger Source 23 1 read-write 0 Trigger source selected by TRGSEL is external. #0 1 Trigger source selected by TRGSEL is internal (channel pin input capture). #1 TRGSEL Trigger Select 24 4 read-write 0001 Channel 0 pin input capture #0001 0010 Channel 1 pin input capture #0010 0011 Channel 0 or Channel 1 pin input capture #0011 0100 Channel 2 pin input capture #0100 0101 Channel 0 or Channel 2 pin input capture #0101 0110 Channel 1 or Channel 2 pin input capture #0110 0111 Channel 0 or Channel 1 or Channel 2 pin input capture #0111 1000 Channel 3 pin input capture #1000 1001 Channel 0 or Channel 3 pin input capture #1001 1010 Channel 1 or Channel 3 pin input capture #1010 1011 Channel 0 or Channel 1 or Channel 3 pin input capture #1011 1100 Channel 2 or Channel 3 pin input capture #1100 1101 Channel 0 or Channel 2 or Channel 3 pin input capture #1101 1110 Channel 1 or Channel 2 or Channel 3 pin input capture #1110 1111 Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture #1111 TPM2 Timer/PWM Module TPM TPM2_ 0x4003A000 0 0x88 registers TPM2 19 SC Status and Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CMOD Clock Mode Selection 3 2 read-write 00 TPM counter is disabled #00 01 TPM counter increments on every TPM counter clock #01 10 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock #10 CPWMS Center-Aligned PWM Select 5 1 read-write 0 TPM counter operates in up counting mode. #0 1 TPM counter operates in up-down counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling or DMA request. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 DMA DMA Enable 8 1 read-write 0 Disables DMA transfers. #0 1 Enables DMA transfers. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter value 0 16 read-write MOD Modulo 0x8 32 read-write 0xFFFF 0xFFFFFFFF MOD Modulo value 0 16 read-write 2 0x8 0,1 C%sSC Channel (n) Status and Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 2 0x8 0,1 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write STATUS Capture and Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 TOF Timer Overflow Flag 8 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 COMBINE Combine Channel Register 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels 0 and 1 0 1 read-write 0 Channels 0 and 1 are independent. #0 1 Channels 0 and 1 are combined. #1 COMSWAP0 Combine Channel 0 and 1 Swap 1 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 COMBINE1 Combine Channels 2 and 3 8 1 read-write 0 Channels 2 and 3 are independent. #0 1 Channels 2 and 3 are combined. #1 COMSWAP1 Combine Channels 2 and 3 Swap 9 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 POL Channel Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FILTER Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Filter Value 0 4 read-write CH1FVAL Channel 1 Filter Value 4 4 read-write CH2FVAL Channel 2 Filter Value 8 4 read-write CH3FVAL Channel 3 Filter Value 12 4 read-write QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Enables the quadrature decoder mode 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 TOFDIR Indicates if the TOF bit was set on the top or the bottom of counting. 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). #1 QUADIR Counter Direction in Quadrature Decode Mode 2 1 read-only 0 Counter direction is decreasing (counter decrement). #0 1 Counter direction is increasing (counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase encoding mode. #0 1 Count and direction encoding mode. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF DOZEEN Doze Enable 5 1 read-write 0 Internal TPM counter continues in Doze mode. #0 1 Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. #1 DBGMODE Debug Mode 6 2 read-write 00 TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. #00 11 TPM counter continues in debug mode. #11 GTBSYNC Global Time Base Synchronization 8 1 read-write 0 Global timebase synchronization disabled. #0 1 Global timebase synchronization enabled. #1 GTBEEN Global time base enable 9 1 read-write 0 All channels use the internally generated TPM counter as their timebase #0 1 All channels use an externally generated global timebase as their timebase #1 CSOT Counter Start on Trigger 16 1 read-write 0 TPM counter starts to increment immediately, once it is enabled. #0 1 TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. #1 CSOO Counter Stop On Overflow 17 1 read-write 0 TPM counter continues incrementing or decrementing after overflow #0 1 TPM counter stops incrementing or decrementing after overflow. #1 CROT Counter Reload On Trigger 18 1 read-write 0 Counter is not reloaded due to a rising edge on the selected input trigger #0 1 Counter is reloaded when a rising edge is detected on the selected input trigger #1 CPOT Counter Pause On Trigger 19 1 read-write TRGPOL Trigger Polarity 22 1 read-write 0 Trigger is active high. #0 1 Trigger is active low. #1 TRGSRC Trigger Source 23 1 read-write 0 Trigger source selected by TRGSEL is external. #0 1 Trigger source selected by TRGSEL is internal (channel pin input capture). #1 TRGSEL Trigger Select 24 4 read-write 0001 Channel 0 pin input capture #0001 0010 Channel 1 pin input capture #0010 0011 Channel 0 or Channel 1 pin input capture #0011 0100 Channel 2 pin input capture #0100 0101 Channel 0 or Channel 2 pin input capture #0101 0110 Channel 1 or Channel 2 pin input capture #0110 0111 Channel 0 or Channel 1 or Channel 2 pin input capture #0111 1000 Channel 3 pin input capture #1000 1001 Channel 0 or Channel 3 pin input capture #1001 1010 Channel 1 or Channel 3 pin input capture #1010 1011 Channel 0 or Channel 1 or Channel 3 pin input capture #1011 1100 Channel 2 or Channel 3 pin input capture #1100 1101 Channel 0 or Channel 2 or Channel 3 pin input capture #1101 1110 Channel 1 or Channel 2 or Channel 3 pin input capture #1110 1111 Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture #1111 ADC0 Analog-to-Digital Converter ADC0_ 0x4003B000 0 0x70 registers ADC0 15 2 0x4 A,B SC1%s ADC Status and Control Registers 1 0 32 read-write 0x1F 0xFFFFFFFF ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11010 When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11101 When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. #11101 11110 When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. #11110 11111 Module is disabled. #11111 DIFF Differential Mode Enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 AIEN Interrupt Enable 6 1 read-write 0 Conversion complete interrupt is disabled. #0 1 Conversion complete interrupt is enabled. #1 COCO Conversion Complete Flag 7 1 read-only 0 Conversion is not completed. #0 1 Conversion is completed. #1 CFG1 ADC Configuration Register 1 0x8 32 read-write 0 0xFFFFFFFF ADICLK Input Clock Select 0 2 read-write 00 Bus clock #00 01 Bus clock divided by 2(BUSCLK/2) #01 10 Alternate clock (ALTCLK) #10 11 Asynchronous clock (ADACK) #11 MODE Conversion mode selection 2 2 read-write 00 When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. #00 01 When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output. #01 10 When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output #10 11 When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output #11 ADLSMP Sample Time Configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 ADIV Clock Divide Select 5 2 read-write 00 The divide ratio is 1 and the clock rate is input clock. #00 01 The divide ratio is 2 and the clock rate is (input clock)/2. #01 10 The divide ratio is 4 and the clock rate is (input clock)/4. #10 11 The divide ratio is 8 and the clock rate is (input clock)/8. #11 ADLPC Low-Power Configuration 7 1 read-write 0 Normal power configuration. #0 1 Low-power configuration. The power is reduced at the expense of maximum clock speed. #1 CFG2 ADC Configuration Register 2 0xC 32 read-write 0 0xFFFFFFFF ADLSTS Long Sample Time Select 0 2 read-write 00 Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. #00 01 12 extra ADCK cycles; 16 ADCK cycles total sample time. #01 10 6 extra ADCK cycles; 10 ADCK cycles total sample time. #10 11 2 extra ADCK cycles; 6 ADCK cycles total sample time. #11 ADHSC High-Speed Configuration 2 1 read-write 0 Normal conversion sequence selected. #0 1 High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. #1 ADACKEN Asynchronous Clock Output Enable 3 1 read-write 0 Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. #0 1 Asynchronous clock and clock output is enabled regardless of the state of the ADC. #1 MUXSEL ADC Mux Select 4 1 read-write 0 ADxxa channels are selected. #0 1 ADxxb channels are selected. #1 2 0x4 A,B R%s ADC Data Result Register 0x10 32 read-only 0 0xFFFFFFFF D Data result 0 16 read-only 2 0x4 1,2 CV%s Compare Value Registers 0x18 32 read-write 0 0xFFFFFFFF CV Compare Value. 0 16 read-write SC2 Status and Control Register 2 0x20 32 read-write 0 0xFFFFFFFF REFSEL Voltage Reference Selection 0 2 read-write 00 Default voltage reference pin pair, that is, external pins VREFH and VREFL #00 01 Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU #01 DMAEN DMA Enable 2 1 read-write 0 DMA is disabled. #0 1 DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted. #1 ACREN Compare Function Range Enable 3 1 read-write 0 Range function disabled. Only CV1 is compared. #0 1 Range function enabled. Both CV1 and CV2 are compared. #1 ACFGT Compare Function Greater Than Enable 4 1 read-write 0 Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2. #0 1 Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2. #1 ACFE Compare Function Enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ADTRG Conversion Trigger Select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 ADACT Conversion Active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 SC3 Status and Control Register 3 0x24 32 read-write 0 0xFFFFFFFF AVGS Hardware Average Select 0 2 read-write 00 4 samples averaged. #00 01 8 samples averaged. #01 10 16 samples averaged. #10 11 32 samples averaged. #11 AVGE Hardware Average Enable 2 1 read-write 0 Hardware average function disabled. #0 1 Hardware average function enabled. #1 ADCO Continuous Conversion Enable 3 1 read-write 0 One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. #0 1 Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. #1 CALF Calibration Failed Flag 6 1 read-write 0 Calibration completed normally. #0 1 Calibration failed. ADC accuracy specifications are not guaranteed. #1 CAL Calibration 7 1 read-write OFS ADC Offset Correction Register 0x28 32 read-write 0x4 0xFFFFFFFF OFS Offset Error Correction Value 0 16 read-write PG ADC Plus-Side Gain Register 0x2C 32 read-write 0x8200 0xFFFFFFFF PG Plus-Side Gain 0 16 read-write MG ADC Minus-Side Gain Register 0x30 32 read-write 0x8200 0xFFFFFFFF MG Minus-Side Gain 0 16 read-write CLPD ADC Plus-Side General Calibration Value Register 0x34 32 read-write 0xA 0xFFFFFFFF CLPD Calibration Value 0 6 read-write CLPS ADC Plus-Side General Calibration Value Register 0x38 32 read-write 0x20 0xFFFFFFFF CLPS Calibration Value 0 6 read-write CLP4 ADC Plus-Side General Calibration Value Register 0x3C 32 read-write 0x200 0xFFFFFFFF CLP4 Calibration Value 0 10 read-write CLP3 ADC Plus-Side General Calibration Value Register 0x40 32 read-write 0x100 0xFFFFFFFF CLP3 Calibration Value 0 9 read-write CLP2 ADC Plus-Side General Calibration Value Register 0x44 32 read-write 0x80 0xFFFFFFFF CLP2 Calibration Value 0 8 read-write CLP1 ADC Plus-Side General Calibration Value Register 0x48 32 read-write 0x40 0xFFFFFFFF CLP1 Calibration Value 0 7 read-write CLP0 ADC Plus-Side General Calibration Value Register 0x4C 32 read-write 0x20 0xFFFFFFFF CLP0 Calibration Value 0 6 read-write CLMD ADC Minus-Side General Calibration Value Register 0x54 32 read-write 0xA 0xFFFFFFFF CLMD Calibration Value 0 6 read-write CLMS ADC Minus-Side General Calibration Value Register 0x58 32 read-write 0x20 0xFFFFFFFF CLMS Calibration Value 0 6 read-write CLM4 ADC Minus-Side General Calibration Value Register 0x5C 32 read-write 0x200 0xFFFFFFFF CLM4 Calibration Value 0 10 read-write CLM3 ADC Minus-Side General Calibration Value Register 0x60 32 read-write 0x100 0xFFFFFFFF CLM3 Calibration Value 0 9 read-write CLM2 ADC Minus-Side General Calibration Value Register 0x64 32 read-write 0x80 0xFFFFFFFF CLM2 Calibration Value 0 8 read-write CLM1 ADC Minus-Side General Calibration Value Register 0x68 32 read-write 0x40 0xFFFFFFFF CLM1 Calibration Value 0 7 read-write CLM0 ADC Minus-Side General Calibration Value Register 0x6C 32 read-write 0x20 0xFFFFFFFF CLM0 Calibration Value 0 6 read-write RTC Secure Real Time Clock RTC_ 0x4003D000 0 0x20 registers RTC 20 RTC_Seconds 21 TSR RTC Time Seconds Register 0 32 read-write 0 0xFFFFFFFF TSR Time Seconds Register 0 32 read-write TPR RTC Time Prescaler Register 0x4 32 read-write 0 0xFFFFFFFF TPR Time Prescaler Register 0 16 read-write TAR RTC Time Alarm Register 0x8 32 read-write 0 0xFFFFFFFF TAR Time Alarm Register 0 32 read-write TCR RTC Time Compensation Register 0xC 32 read-write 0 0xFFFFFFFF TCR Time Compensation Register 0 8 read-write 10000000 Time Prescaler Register overflows every 32896 clock cycles. #10000000 11111111 Time Prescaler Register overflows every 32769 clock cycles. #11111111 0 Time Prescaler Register overflows every 32768 clock cycles. #0 1 Time Prescaler Register overflows every 32767 clock cycles. #1 1111111 Time Prescaler Register overflows every 32641 clock cycles. #1111111 CIR Compensation Interval Register 8 8 read-write TCV Time Compensation Value 16 8 read-only CIC Compensation Interval Counter 24 8 read-only CR RTC Control Register 0x10 32 read-write 0 0xFFFFFFFF SWR Software Reset 0 1 read-write 0 No effect. #0 1 Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it. #1 WPE Wakeup Pin Enable 1 1 read-write 0 Wakeup pin is disabled. #0 1 Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on. #1 SUP Supervisor Access 2 1 read-write 0 Non-supervisor mode write accesses are not supported and generate a bus error. #0 1 Non-supervisor mode write accesses are supported. #1 UM Update Mode 3 1 read-write 0 Registers cannot be written when locked. #0 1 Registers can be written when locked under limited conditions. #1 WPS Wakeup Pin Select 4 1 read-write 0 Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on. #0 1 Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals. #1 OSCE Oscillator Enable 8 1 read-write 0 32.768 kHz oscillator is disabled. #0 1 32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize. #1 CLKO Clock Output 9 1 read-write 0 The 32 kHz clock is output to other peripherals. #0 1 The 32 kHz clock is not output to other peripherals. #1 SC16P Oscillator 16pF Load Configure 10 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC8P Oscillator 8pF Load Configure 11 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC4P Oscillator 4pF Load Configure 12 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC2P Oscillator 2pF Load Configure 13 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SR RTC Status Register 0x14 32 read-write 0x1 0xFFFFFFFF TIF Time Invalid Flag 0 1 read-only 0 Time is valid. #0 1 Time is invalid and time counter is read as zero. #1 TOF Time Overflow Flag 1 1 read-only 0 Time overflow has not occurred. #0 1 Time overflow has occurred and time counter is read as zero. #1 TAF Time Alarm Flag 2 1 read-only 0 Time alarm has not occurred. #0 1 Time alarm has occurred. #1 TCE Time Counter Enable 4 1 read-write 0 Time counter is disabled. #0 1 Time counter is enabled. #1 LR RTC Lock Register 0x18 32 read-write 0xFF 0xFFFFFFFF TCL Time Compensation Lock 3 1 read-write 0 Time Compensation Register is locked and writes are ignored. #0 1 Time Compensation Register is not locked and writes complete as normal. #1 CRL Control Register Lock 4 1 read-write 0 Control Register is locked and writes are ignored. #0 1 Control Register is not locked and writes complete as normal. #1 SRL Status Register Lock 5 1 read-write 0 Status Register is locked and writes are ignored. #0 1 Status Register is not locked and writes complete as normal. #1 LRL Lock Register Lock 6 1 read-write 0 Lock Register is locked and writes are ignored. #0 1 Lock Register is not locked and writes complete as normal. #1 IER RTC Interrupt Enable Register 0x1C 32 read-write 0x7 0xFFFFFFFF TIIE Time Invalid Interrupt Enable 0 1 read-write 0 Time invalid flag does not generate an interrupt. #0 1 Time invalid flag does generate an interrupt. #1 TOIE Time Overflow Interrupt Enable 1 1 read-write 0 Time overflow flag does not generate an interrupt. #0 1 Time overflow flag does generate an interrupt. #1 TAIE Time Alarm Interrupt Enable 2 1 read-write 0 Time alarm flag does not generate an interrupt. #0 1 Time alarm flag does generate an interrupt. #1 TSIE Time Seconds Interrupt Enable 4 1 read-write 0 Seconds interrupt is disabled. #0 1 Seconds interrupt is enabled. #1 WPON Wakeup Pin On 7 1 read-write 0 No effect. #0 1 If the wakeup pin is enabled, then the wakeup pin will assert. #1 DAC0 12-Bit Digital-to-Analog Converter DAC0_ 0x4003F000 0 0x24 registers DAC0 25 2 0x2 0,1 DAT%sL DAC Data Low Register 0 8 read-write 0 0xFF DATA0 DATA0 0 8 read-write 2 0x2 0,1 DAT%sH DAC Data High Register 0x1 8 read-write 0 0xFF DATA1 DATA1 0 4 read-write SR DAC Status Register 0x20 8 read-write 0x6 0xFF DACBFRPBF DAC Buffer Read Pointer Bottom Position Flag 0 1 read-write 0 The DAC buffer read pointer is not equal to C2[DACBFUP]. #0 1 The DAC buffer read pointer is equal to C2[DACBFUP]. #1 DACBFRPTF DAC Buffer Read Pointer Top Position Flag 1 1 read-write 0 The DAC buffer read pointer is not zero. #0 1 The DAC buffer read pointer is zero. #1 DACBFWMF DAC Buffer Watermark Flag 2 1 read-write 0 The DAC buffer read pointer has not reached the watermark level. #0 1 The DAC buffer read pointer has reached the watermark level. #1 C0 DAC Control Register 0x21 8 read-write 0 0xFF DACBBIEN DAC Buffer Read Pointer Bottom Flag Interrupt Enable 0 1 read-write 0 The DAC buffer read pointer bottom flag interrupt is disabled. #0 1 The DAC buffer read pointer bottom flag interrupt is enabled. #1 DACBTIEN DAC Buffer Read Pointer Top Flag Interrupt Enable 1 1 read-write 0 The DAC buffer read pointer top flag interrupt is disabled. #0 1 The DAC buffer read pointer top flag interrupt is enabled. #1 DACBWIEN DAC Buffer Watermark Interrupt Enable 2 1 read-write 0 The DAC buffer watermark interrupt is disabled. #0 1 The DAC buffer watermark interrupt is enabled. #1 LPEN DAC Low Power Control 3 1 read-write 0 High-Power mode #0 1 Low-Power mode #1 DACSWTRG DAC Software Trigger 4 1 write-only 0 The DAC soft trigger is not valid. #0 1 The DAC soft trigger is valid. #1 DACTRGSEL DAC Trigger Select 5 1 read-write 0 The DAC hardware trigger is selected. #0 1 The DAC software trigger is selected. #1 DACRFS DAC Reference Select 6 1 read-write 0 The DAC selects DACREF_1 as the reference voltage. #0 1 The DAC selects DACREF_2 as the reference voltage. #1 DACEN DAC Enable 7 1 read-write 0 The DAC system is disabled. #0 1 The DAC system is enabled. #1 C1 DAC Control Register 1 0x22 8 read-write 0 0xFF DACBFEN DAC Buffer Enable 0 1 read-write 0 Buffer read pointer is disabled. The converted data is always the first word of the buffer. #0 1 Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. #1 DACBFMD DAC Buffer Work Mode Select 2 1 read-write 0 Normal mode #0 1 One-Time Scan mode #1 DACBFWM DAC Buffer Watermark Select 3 2 read-write 00 1 word #00 01 2 words #01 DMAEN DMA Enable Select 7 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time. #1 C2 DAC Control Register 2 0x23 8 read-write 0x1 0xFF DACBFUP DAC Buffer Upper Limit 0 1 read-write DACBFRP DAC Buffer Read Pointer 4 1 read-write LPTMR0 Low Power Timer LPTMR0_ 0x40040000 0 0x10 registers LPTMR0 28 CSR Low Power Timer Control Status Register 0 32 read-write 0 0xFFFFFFFF TEN Timer Enable 0 1 read-write 0 LPTMR is disabled and internal logic is reset. #0 1 LPTMR is enabled. #1 TMS Timer Mode Select 1 1 read-write 0 Time Counter mode. #0 1 Pulse Counter mode. #1 TFC Timer Free-Running Counter 2 1 read-write 0 CNR is reset whenever TCF is set. #0 1 CNR is reset on overflow. #1 TPP Timer Pin Polarity 3 1 read-write 0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. #0 1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. #1 TPS Timer Pin Select 4 2 read-write 00 Pulse counter input 0 is selected. #00 01 Pulse counter input 1 is selected. #01 10 Pulse counter input 2 is selected. #10 11 Pulse counter input 3 is selected. #11 TIE Timer Interrupt Enable 6 1 read-write 0 Timer interrupt disabled. #0 1 Timer interrupt enabled. #1 TCF Timer Compare Flag 7 1 read-write 0 The value of CNR is not equal to CMR and increments. #0 1 The value of CNR is equal to CMR and increments. #1 PSR Low Power Timer Prescale Register 0x4 32 read-write 0 0xFFFFFFFF PCS Prescaler Clock Select 0 2 read-write 00 Prescaler/glitch filter clock 0 selected. #00 01 Prescaler/glitch filter clock 1 selected. #01 10 Prescaler/glitch filter clock 2 selected. #10 11 Prescaler/glitch filter clock 3 selected. #11 PBYP Prescaler Bypass 2 1 read-write 0 Prescaler/glitch filter is enabled. #0 1 Prescaler/glitch filter is bypassed. #1 PRESCALE Prescale Value 3 4 read-write 0000 Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. #0000 0001 Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. #0001 0010 Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. #0010 0011 Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. #0011 0100 Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. #0100 0101 Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. #0101 0110 Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. #0110 0111 Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. #0111 1000 Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. #1000 1001 Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. #1001 1010 Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. #1010 1011 Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. #1011 1100 Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. #1100 1101 Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. #1101 1110 Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. #1110 1111 Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. #1111 CMR Low Power Timer Compare Register 0x8 32 read-write 0 0xFFFFFFFF COMPARE Compare Value 0 16 read-write CNR Low Power Timer Counter Register 0xC 32 read-write 0 0xFFFFFFFF COUNTER Counter Value 0 16 read-write RFSYS System register file RFSYS_ 0x40041000 0 0x20 registers 8 0x4 0,1,2,3,4,5,6,7 REG%s Register file register 0 32 read-write 0 0xFFFFFFFF LL Low lower byte 0 8 read-write LH Low higher byte 8 8 read-write HL High lower byte 16 8 read-write HH High higher byte 24 8 read-write TSI0 Touch sense input TSI0_ 0x40045000 0 0xC registers TSI0 11 GENCS TSI General Control and Status Register 0 32 read-write 0 0xFFFFFFFF CURSW CURSW 1 1 read-write 0 The current source pair are not swapped. #0 1 The current source pair are swapped. #1 EOSF End of Scan Flag 2 1 read-write 0 Scan not complete. #0 1 Scan complete. #1 SCNIP Scan In Progress Status 3 1 read-only 0 No scan in progress. #0 1 Scan in progress. #1 STM Scan Trigger Mode 4 1 read-write 0 Software trigger scan. #0 1 Hardware trigger scan. #1 STPE TSI STOP Enable 5 1 read-write 0 TSI is disabled when MCU goes into low power mode. #0 1 Allows TSI to continue running in all low power modes. #1 TSIIEN Touch Sensing Input Interrupt Enable 6 1 read-write 0 TSI interrupt is disabled. #0 1 TSI interrupt is enabled. #1 TSIEN Touch Sensing Input Module Enable 7 1 read-write 0 TSI module disabled. #0 1 TSI module enabled. #1 NSCN NSCN 8 5 read-write 00000 Once per electrode #00000 00001 Twice per electrode #00001 00010 3 times per electrode #00010 00011 4 times per electrode #00011 00100 5 times per electrode #00100 00101 6 times per electrode #00101 00110 7 times per electrode #00110 00111 8 times per electrode #00111 01000 9 times per electrode #01000 01001 10 times per electrode #01001 01010 11 times per electrode #01010 01011 12 times per electrode #01011 01100 13 times per electrode #01100 01101 14 times per electrode #01101 01110 15 times per electrode #01110 01111 16 times per electrode #01111 10000 17 times per electrode #10000 10001 18 times per electrode #10001 10010 19 times per electrode #10010 10011 20 times per electrode #10011 10100 21 times per electrode #10100 10101 22 times per electrode #10101 10110 23 times per electrode #10110 10111 24 times per electrode #10111 11000 25 times per electrode #11000 11001 26 times per electrode #11001 11010 27 times per electrode #11010 11011 28 times per electrode #11011 11100 29 times per electrode #11100 11101 30 times per electrode #11101 11110 31 times per electrode #11110 11111 32 times per electrode #11111 PS PS 13 3 read-write 000 Electrode Oscillator Frequency divided by 1 #000 001 Electrode Oscillator Frequency divided by 2 #001 010 Electrode Oscillator Frequency divided by 4 #010 011 Electrode Oscillator Frequency divided by 8 #011 100 Electrode Oscillator Frequency divided by 16 #100 101 Electrode Oscillator Frequency divided by 32 #101 110 Electrode Oscillator Frequency divided by 64 #110 111 Electrode Oscillator Frequency divided by 128 #111 EXTCHRG EXTCHRG 16 3 read-write 000 500 nA. #000 001 1 uA. #001 010 2 uA. #010 011 4 uA. #011 100 8 uA. #100 101 16 uA. #101 110 32 uA. #110 111 64 uA. #111 DVOLT DVOLT 19 2 read-write 00 DV = 1.026 V; VP = 1.328 V; Vm = 0.302 V. #00 01 DV = 0.592 V; VP = 1.111 V; Vm = 0.519 V. #01 10 DV = 0.342 V; VP = 0.986 V; Vm = 0.644 V. #10 11 DV = 0.197 V; VP = 0.914 V; Vm = 0.716 V. #11 REFCHRG REFCHRG 21 3 read-write 000 500 nA. #000 001 1 uA. #001 010 2 uA. #010 011 4 uA. #011 100 8 uA. #100 101 16 uA. #101 110 32 uA. #110 111 64 uA. #111 MODE TSI analog modes setup and status bits. 24 4 read-write 0000 Set TSI in capacitive sensing(non-noise detection) mode. #0000 0100 Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is disabled. #0100 1000 Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is enabled to work in higher frequencies operations. #1000 1100 Set TSI analog to work in automatic noise detection mode. #1100 ESOR End-of-scan or Out-of-Range Interrupt Selection 28 1 read-write 0 Out-of-range interrupt is allowed. #0 1 End-of-scan interrupt is allowed. #1 OUTRGF Out of Range Flag. 31 1 read-write DATA TSI DATA Register 0x4 32 read-write 0 0xFFFFFFFF TSICNT TSI Conversion Counter Value 0 16 read-only SWTS Software Trigger Start 22 1 write-only 0 No effect. #0 1 Start a scan to determine which channel is specified by TSI_DATA[TSICH]. #1 DMAEN DMA Transfer Enabled 23 1 read-write 0 Interrupt is selected when the interrupt enable bit is set and the corresponding TSI events assert. #0 1 DMA transfer request is selected when the interrupt enable bit is set and the corresponding TSI events assert. #1 TSICH TSICH 28 4 read-write 0000 Channel 0. #0000 0001 Channel 1. #0001 0010 Channel 2. #0010 0011 Channel 3. #0011 0100 Channel 4. #0100 0101 Channel 5. #0101 0110 Channel 6. #0110 0111 Channel 7. #0111 1000 Channel 8. #1000 1001 Channel 9. #1001 1010 Channel 10. #1010 1011 Channel 11. #1011 1100 Channel 12. #1100 1101 Channel 13. #1101 1110 Channel 14. #1110 1111 Channel 15. #1111 TSHD TSI Threshold Register 0x8 32 read-write 0 0xFFFFFFFF THRESL TSI Wakeup Channel Low-threshold 0 16 read-write THRESH TSI Wakeup Channel High-threshold 16 16 read-write SIM System Integration Module SIM_ 0x40047000 0 0x1108 registers SOPT1 System Options Register 1 0 32 read-write 0x9000 0xFFFFFFFF OSC32KOUT 32K oscillator clock output 16 2 read-write 00 ERCLK32K is not output. #00 01 ERCLK32K is output on PTB3. #01 OSC32KSEL 32K Oscillator Clock Select 18 2 read-write 00 32kHz oscillator (OSC32KCLK) #00 10 RTC_CLKIN #10 11 LPO 1kHz #11 SOPT2 System Options Register 2 0x1004 32 read-write 0 0xFFFFFFFF CLKOUTSEL CLKOUT select 5 3 read-write 000 OSCERCLK DIV2 #000 001 OSCERCLK DIV4 #001 010 Bus clock #010 011 LPO clock 1 kHz #011 100 MCGIRCLK #100 101 OSCERCLK DIV8 #101 110 OSCERCLK #110 TPMSRC TPM Clock Source Select 24 2 read-write 00 Clock disabled #00 01 MCGFLLCLK clock #01 10 OSCERCLK clock #10 11 MCGIRCLK clock #11 LPUART0SRC LPUART0 Clock Source Select 26 2 read-write 00 Clock disabled #00 01 MCGFLLCLK clock #01 10 OSCERCLK clock #10 11 MCGIRCLK clock #11 SOPT4 System Options Register 4 0x100C 32 read-write 0 0xFFFFFFFF TPM1CH0SRC TPM1 Channel 0 Input Capture Source Select 18 1 read-write 0 TPM1_CH0 signal #0 1 CMP0 output #1 TPM2CH0SRC TPM2 Channel 0 Input Capture Source Select 20 1 read-write 0 TPM2_CH0 signal #0 1 CMP0 output #1 TPM0CLKSEL TPM0 External Clock Pin Select 24 1 read-write 0 TPM0 external clock driven by TPM_CLKIN0 pin. #0 1 TPM0 external clock driven by TPM_CLKIN1 pin. #1 TPM1CLKSEL TPM1 External Clock Pin Select 25 1 read-write 0 TPM1 external clock driven by TPM_CLKIN0 pin. #0 1 TPM1 external clock driven by TPM_CLKIN1 pin. #1 TPM2CLKSEL TPM2 External Clock Pin Select 26 1 read-write 0 TPM2 external clock driven by TPM_CLKIN0 pin. #0 1 TPM2 external clock driven by TPM_CLKIN1 pin. #1 SOPT5 System Options Register 5 0x1010 32 read-write 0 0xFFFFFFFF LPUART0TXSRC LPUART0 Transmit Data Source Select 0 2 read-write 00 LPUART0_TX pin #00 01 LPUART0_TX pin modulated with TPM1 channel 0 output #01 10 LPUART0_TX pin modulated with TPM2 channel 0 output #10 LPUART0RXSRC LPUART0 Receive Data Source Select 2 1 read-write 0 LPUART_RX pin #0 1 CMP0 output #1 LPUART0ODE LPUART0 Open Drain Enable 16 1 read-write 0 Open drain is disabled on LPUART0. #0 1 Open drain is enabled on LPUART0. #1 SOPT7 System Options Register 7 0x1018 32 read-write 0 0xFFFFFFFF ADC0TRGSEL ADC0 Trigger Select 0 4 read-write 0000 External trigger pin input (EXTRG_IN) #0000 0001 CMP0 output #0001 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 1000 TPM0 overflow #1000 1001 TPM1 overflow #1001 1010 TPM2 overflow #1010 1100 RTC alarm #1100 1101 RTC seconds #1101 1110 LPTMR0 trigger #1110 1111 Radio TSM #1111 ADC0PRETRGSEL ADC0 Pretrigger Select 4 1 read-write 0 Pre-trigger ADHDWTSA is selected, thus ADC0 will use ADC0_SC1A configuration for the next ADC conversion and store the result in ADC0_RA register. #0 1 Pre-trigger ADHDWTSB is selected, thus ADC0 will use ADC0_SC1B configuration for the next ADC conversion and store the result in ADC0_RB register. #1 ADC0ALTTRGEN ADC0 Alternate Trigger Enable 7 1 read-write 0 ADC ADHWT trigger comes from TPM1 channel 0 and channel1. Prior to the assertion of TPM1 channel 0, a pre-trigger pulse will be sent to ADHWTSA to initiate an ADC acquisition using ADCx_SC1A configuration and store ADC conversion in ADCx_RA Register. Prior to the assertion of TPM1 channel 1 a pre-trigger pulse will be sent to ADHWTSB to initiate an ADC acquisition using ADCx_SC1Bconfiguration and store ADC conversion in ADCx_RB Register. #0 1 ADC ADHWT trigger comes from a peripheral event selected by ADC0TRGSEL bits.ADC0PRETRGSEL bit will select the optional ADHWTSA or ADHWTSB select lines for choosing the ADCx_SC1x config and ADCx_Rx result regsiter to store the ADC conversion. #1 SDID System Device Identification Register 0x1024 32 read-only 0x5F0000 0xFFFFFFFF PINID Pin count Identification 0 4 read-only 0010 32-pin #0010 0100 48-pin #0100 1011 CSP #1011 DIEID Device Die Number 7 5 read-only REVID Device Revision Number 12 4 read-only SRAMSIZE System SRAM Size 16 4 read-only 1001 128 KB #1001 0111 64 KB #0111 SERIESID Kinetis Series ID 20 4 read-only 0101 KW family #0101 SUBFAMID Kinetis Sub-Family ID. 24 2 read-only 00 KWx0 Subfamily #00 01 KWx1 Subfamily #01 10 KWx2 Subfamily #10 11 KWx3 Subfamily #11 FAMID Kinetis family ID 28 4 read-only 0010 KW2x Family (802.15.4/ZigBee) #0010 0011 KW3x Family (BTLE) #0011 0100 KW4x Family (802.15.4/ZigBee, BTLE, GFSK , ANT) #0100 SCGC4 System Clock Gating Control Register 4 0x1034 32 read-write 0xF0000030 0xFFFFFFFF CMT CMT Clock Gate Control 2 1 read-write 0 Clock disabled #0 1 Clock enabled #1 I2C0 I2C0 Clock Gate Control 6 1 read-write 0 Clock disabled #0 1 Clock enabled #1 I2C1 I2C1 Clock Gate Control 7 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CMP Comparator Clock Gate Control 19 1 read-write 0 Clock disabled #0 1 Clock enabled #1 VREF VREF Clock Gate Control 20 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC5 System Clock Gating Control Register 5 0x1038 32 read-write 0x2000182 0xFFFFFFFF LPTMR Low Power Timer Access Control 0 1 read-write 0 Access disabled #0 1 Access enabled #1 TSI TSI Access Control 5 1 read-write 0 Access disabled #0 1 Access enabled #1 PORTA Port A Clock Gate Control 9 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTB Port B Clock Gate Control 10 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTC Port C Clock Gate Control 11 1 read-write 0 Clock disabled #0 1 Clock enabled #1 LPUART0 LPUART0 Clock Gate Control 20 1 read-write 0 Clock disabled #0 1 Clock enabled #1 LTC LTC Clock Gate Control 24 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RSIM RSIM Clock Gate Control 25 1 read-only DCDC DCDC Clock Gate Control 26 1 read-write 0 Clock disabled #0 1 Clock enabled #1 BTLL BTLL System Clock Gate Control 27 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PHYDIG PHY Digital Clock Gate Control 28 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ZigBee ZigBee Clock Gate Control 29 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ANT ANT Clock Gate Control 30 1 read-write 0 ANT CGC bit disabled. #0 1 ANT CGC bit can be enabled. #1 GEN_FSK Generic FSK enabled 31 1 read-write 0 GFSK CGC bit disabled. #0 1 GFSK CGC bit enabled. #1 SCGC6 System Clock Gating Control Register 6 0x103C 32 read-write 0x1 0xFFFFFFFF FTF Flash Memory Clock Gate Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 DMAMUX DMA Mux Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TRNG TRNG Clock Gate Control 9 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SPI0 SPI0 Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SPI1 SPI1 Clock Gate Control 13 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PIT PIT Clock Gate Control 23 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TPM0 TPM0 Clock Gate Control 24 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TPM1 TPM1 Clock Gate Control 25 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TPM2 TPM2 Clock Gate Control 26 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ADC0 ADC0 Clock Gate Control 27 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RTC RTC Access Control 29 1 read-write 0 Access and interrupts disabled #0 1 Access and interrupts enabled #1 DAC0 DAC0 Clock Gate Control 31 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC7 System Clock Gating Control Register 7 0x1040 32 read-write 0x100 0xFFFFFFFF DMA DMA Clock Gate Control 8 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CLKDIV1 System Clock Divider Register 1 0x1044 32 read-write 0x10000 0xFFFFFFFF OUTDIV4 Clock 4 Output Divider value 16 3 read-write 000 Divide-by-1. #000 001 Divide-by-2. #001 010 Divide-by-3. #010 011 Divide-by-4. #011 100 Divide-by-5. #100 101 Divide-by-6. #101 110 Divide-by-7. #110 111 Divide-by-8. #111 OUTDIV1 Clock 1 Output Divider value 28 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 FCFG1 Flash Configuration Register 1 0x104C 32 read-write 0xF000000 0xFFFFFFFF FLASHDIS Flash Disable 0 1 read-write 0 Flash is enabled. #0 1 Flash is disabled. #1 FLASHDOZE Flash Doze 1 1 read-write 0 Flash remains enabled during Doze mode. #0 1 Flash is disabled for the duration of Doze mode. #1 PFSIZE Program Flash Size 24 4 read-only 1001 256 KB of program flash memory #1001 1011 512 KB of program flash memory #1011 1111 512 KB of program flash memory #1111 FCFG2 Flash Configuration Register 2 0x1050 32 read-only 0x7FFF0000 0xFFFFFFFF MAXADDR1 This field concatenated with leading zeros plus the value of the MAXADDR1 field indicates the first invalid address of the second program flash block (flash block 1) 16 7 read-only MAXADDR0 Max Address lock 24 7 read-only UIDMH Unique Identification Register Mid-High 0x1058 32 read-only 0 0xFFFFFFFF UID Unique Identification 0 16 read-only UIDML Unique Identification Register Mid Low 0x105C 32 read-only 0 0xFFFFFFFF UID Unique Identification 0 32 read-only UIDL Unique Identification Register Low 0x1060 32 read-only 0 0xFFFFFFFF UID Unique Identification 0 32 read-only COPC COP Control Register 0x1100 32 read-write 0xC 0xFFFFFFFF COPW COP Windowed Mode 0 1 read-write 0 Normal mode #0 1 Windowed mode #1 COPCLKS COP Clock Select 1 1 read-write 0 COP configured for short timeout #0 1 COP configured for long timeout #1 COPT COP Watchdog Timeout 2 2 read-write 00 COP disabled #00 01 COP timeout after 25 cycles for short timeout or 213 cycles for long timeout #01 10 COP timeout after 28 cycles for short timeout or 216 cycles for long timeout #10 11 COP timeout after 210 cycles for short timeout or 218 cycles for long timeout #11 COPSTPEN COP Stop Enable 4 1 read-write 0 COP is disabled and the counter is reset in Stop modes #0 1 COP is enabled in Stop modes #1 COPDBGEN COP Debug Enable 5 1 read-write 0 COP is disabled and the counter is reset in Debug mode #0 1 COP is enabled in Debug mode #1 COPCLKSEL COP Clock Select 6 2 read-write 00 LPO clock (1 kHz) #00 01 MCGIRCLK #01 10 OSCERCLK #10 11 Bus clock #11 SRVCOP Service COP 0x1104 32 write-only 0 0xFFFFFFFF SRVCOP Service COP Register 0 8 write-only PORTA Pin Control and Interrupts PORT PORTA_ 0x40049000 0 0xA4 registers PORTA 30 PCR0 Pin Control Register n 0 32 read-write 0x707 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR1 Pin Control Register n 0x4 32 read-write 0x706 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR2 Pin Control Register n 0x8 32 read-write 0x707 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR3 Pin Control Register n 0xC 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR4 Pin Control Register n 0x10 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR5 Pin Control Register n 0x14 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR6 Pin Control Register n 0x18 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR7 Pin Control Register n 0x1C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR8 Pin Control Register n 0x20 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR9 Pin Control Register n 0x24 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR10 Pin Control Register n 0x28 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR11 Pin Control Register n 0x2C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR12 Pin Control Register n 0x30 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR13 Pin Control Register n 0x34 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR14 Pin Control Register n 0x38 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR15 Pin Control Register n 0x3C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR16 Pin Control Register n 0x40 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR17 Pin Control Register n 0x44 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR18 Pin Control Register n 0x48 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR19 Pin Control Register n 0x4C 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR20 Pin Control Register n 0x50 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR21 Pin Control Register n 0x54 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR22 Pin Control Register n 0x58 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR23 Pin Control Register n 0x5C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR24 Pin Control Register n 0x60 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR25 Pin Control Register n 0x64 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR26 Pin Control Register n 0x68 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR27 Pin Control Register n 0x6C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR28 Pin Control Register n 0x70 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR29 Pin Control Register n 0x74 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR30 Pin Control Register n 0x78 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR31 Pin Control Register n 0x7C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PORTB Pin Control and Interrupts PORT PORTB_ 0x4004A000 0 0xA4 registers PORTB_PORTC 31 PCR0 Pin Control Register n 0 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR1 Pin Control Register n 0x4 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR2 Pin Control Register n 0x8 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR3 Pin Control Register n 0xC 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR4 Pin Control Register n 0x10 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR5 Pin Control Register n 0x14 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR6 Pin Control Register n 0x18 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR7 Pin Control Register n 0x1C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR8 Pin Control Register n 0x20 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR9 Pin Control Register n 0x24 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR10 Pin Control Register n 0x28 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR11 Pin Control Register n 0x2C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR12 Pin Control Register n 0x30 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR13 Pin Control Register n 0x34 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR14 Pin Control Register n 0x38 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR15 Pin Control Register n 0x3C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR16 Pin Control Register n 0x40 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR17 Pin Control Register n 0x44 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR18 Pin Control Register n 0x48 32 read-write 0x715 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR19 Pin Control Register n 0x4C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR20 Pin Control Register n 0x50 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR21 Pin Control Register n 0x54 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR22 Pin Control Register n 0x58 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR23 Pin Control Register n 0x5C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR24 Pin Control Register n 0x60 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR25 Pin Control Register n 0x64 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR26 Pin Control Register n 0x68 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR27 Pin Control Register n 0x6C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR28 Pin Control Register n 0x70 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR29 Pin Control Register n 0x74 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR30 Pin Control Register n 0x78 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR31 Pin Control Register n 0x7C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PORTC Pin Control and Interrupts PORT PORTC_ 0x4004B000 0 0xA4 registers PORTB_PORTC 31 PCR0 Pin Control Register n 0 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR1 Pin Control Register n 0x4 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR2 Pin Control Register n 0x8 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR3 Pin Control Register n 0xC 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR4 Pin Control Register n 0x10 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR5 Pin Control Register n 0x14 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR6 Pin Control Register n 0x18 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR7 Pin Control Register n 0x1C 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR8 Pin Control Register n 0x20 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR9 Pin Control Register n 0x24 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR10 Pin Control Register n 0x28 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR11 Pin Control Register n 0x2C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR12 Pin Control Register n 0x30 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR13 Pin Control Register n 0x34 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR14 Pin Control Register n 0x38 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR15 Pin Control Register n 0x3C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR16 Pin Control Register n 0x40 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR17 Pin Control Register n 0x44 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR18 Pin Control Register n 0x48 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR19 Pin Control Register n 0x4C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR20 Pin Control Register n 0x50 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR21 Pin Control Register n 0x54 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR22 Pin Control Register n 0x58 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR23 Pin Control Register n 0x5C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR24 Pin Control Register n 0x60 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR25 Pin Control Register n 0x64 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR26 Pin Control Register n 0x68 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR27 Pin Control Register n 0x6C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR28 Pin Control Register n 0x70 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR29 Pin Control Register n 0x74 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR30 Pin Control Register n 0x78 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR31 Pin Control Register n 0x7C 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LPUART0 Universal Asynchronous Receiver/Transmitter LPUART0_ 0x40054000 0 0x18 registers LPUART0 12 BAUD LPUART Baud Rate Register 0 32 read-write 0xF000004 0xFFFFFFFF SBR Baud Rate Modulo Divisor. 0 13 read-write SBNS Stop Bit Number Select 13 1 read-write 0 One stop bit. #0 1 Two stop bits. #1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write 0 Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. #1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write 0 Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. #1 RESYNCDIS Resynchronization Disable 16 1 read-write 0 Resynchronization during received data word is supported #0 1 Resynchronization during received data word is disabled #1 BOTHEDGE Both Edge Sampling 17 1 read-write 0 Receiver samples input data using the rising edge of the baud rate clock. #0 1 Receiver samples input data using the rising and falling edge of the baud rate clock. #1 MATCFG Match Configuration 18 2 read-write 00 Address Match Wakeup #00 01 Idle Match Wakeup #01 10 Match On and Match Off #10 11 Enables RWU on Data Match and Match On/Off for transmitter CTS input #11 RDMAE Receiver Full DMA Enable 21 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 TDMAE Transmitter DMA Enable 23 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 OSR Oversampling Ratio 24 5 read-write M10 10-bit Mode select 29 1 read-write 0 Receiver and transmitter use 8-bit or 9-bit data characters. #0 1 Receiver and transmitter use 10-bit data characters. #1 MAEN2 Match Address Mode Enable 2 30 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA2]. #1 MAEN1 Match Address Mode Enable 1 31 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA1]. #1 STAT LPUART Status Register 0x4 32 read-write 0xC00000 0xFFFFFFFF MA2F Match 2 Flag 14 1 read-write 0 Received data is not equal to MA2 #0 1 Received data is equal to MA2 #1 MA1F Match 1 Flag 15 1 read-write 0 Received data is not equal to MA1 #0 1 Received data is equal to MA1 #1 PF Parity Error Flag 16 1 read-write 0 No parity error. #0 1 Parity error. #1 FE Framing Error Flag 17 1 read-write 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 NF Noise Flag 18 1 read-write 0 No noise detected. #0 1 Noise detected in the received character in LPUART_DATA. #1 OR Receiver Overrun Flag 19 1 read-write 0 No overrun. #0 1 Receive overrun (new LPUART data lost). #1 IDLE Idle Line Flag 20 1 read-write 0 No idle line detected. #0 1 Idle line was detected. #1 RDRF Receive Data Register Full Flag 21 1 read-only 0 Receive data buffer empty. #0 1 Receive data buffer full. #1 TC Transmission Complete Flag 22 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 23 1 read-only 0 Transmit data buffer full. #0 1 Transmit data buffer empty. #1 RAF Receiver Active Flag 24 1 read-only 0 LPUART receiver idle waiting for a start bit. #0 1 LPUART receiver active (LPUART_RX input not idle). #1 LBKDE LIN Break Detection Enable 25 1 read-write 0 Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1). #1 BRK13 Break Character Generation Length 26 1 read-write 0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1). #1 RWUID Receive Wake Up Idle Detect 27 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match. #1 RXINV Receive Data Inversion 28 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 MSBF MSB First 29 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. #1 RXEDGIF LPUART_RX Pin Active Edge Interrupt Flag 30 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 CTRL LPUART Control Register 0x8 32 read-write 0 0xFFFFFFFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Configures RWU for idle-line wakeup. #0 1 Configures RWU with address-mark wakeup. #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Receiver and transmitter use 8-bit data characters. #0 1 Receiver and transmitter use 9-bit data characters. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin. #0 1 Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input. #1 DOZEEN Doze Enable 6 1 read-write 0 LPUART is enabled in Doze mode. #0 1 LPUART is disabled in Doze mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - LPUART_RX and LPUART_TX use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). #1 IDLECFG Idle Configuration 8 3 read-write 000 1 idle character #000 001 2 idle characters #001 010 4 idle characters #010 011 8 idle characters #011 100 16 idle characters #100 101 32 idle characters #101 110 64 idle characters #110 111 128 idle characters #111 MA2IE Match 2 Interrupt Enable 14 1 read-write 0 MA2F interrupt disabled #0 1 MA2F interrupt enabled #1 MA1IE Match 1 Interrupt Enable 15 1 read-write 0 MA1F interrupt disabled #0 1 MA1F interrupt enabled #1 SBK Send Break 16 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 RWU Receiver Wakeup Control 17 1 read-write 0 Normal receiver operation. #0 1 LPUART receiver in standby waiting for wakeup condition. #1 RE Receiver Enable 18 1 read-write 0 Receiver disabled. #0 1 Receiver enabled. #1 TE Transmitter Enable 19 1 read-write 0 Transmitter disabled. #0 1 Transmitter enabled. #1 ILIE Idle Line Interrupt Enable 20 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 RIE Receiver Interrupt Enable 21 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TIE Transmit Interrupt Enable 23 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 PEIE Parity Error Interrupt Enable 24 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 FEIE Framing Error Interrupt Enable 25 1 read-write 0 FE interrupts disabled; use polling. #0 1 Hardware interrupt requested when FE is set. #1 NEIE Noise Error Interrupt Enable 26 1 read-write 0 NF interrupts disabled; use polling. #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 27 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 TXINV Transmit Data Inversion 28 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 TXDIR LPUART_TX Pin Direction in Single-Wire Mode 29 1 read-write 0 LPUART_TX pin is an input in single-wire mode. #0 1 LPUART_TX pin is an output in single-wire mode. #1 R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write DATA LPUART Data Register 0xC 32 read-write 0x1000 0xFFFFFFFF R0T0 Read receive data buffer 0 or write transmit data buffer 0. 0 1 read-write R1T1 Read receive data buffer 1 or write transmit data buffer 1. 1 1 read-write R2T2 Read receive data buffer 2 or write transmit data buffer 2. 2 1 read-write R3T3 Read receive data buffer 3 or write transmit data buffer 3. 3 1 read-write R4T4 Read receive data buffer 4 or write transmit data buffer 4. 4 1 read-write R5T5 Read receive data buffer 5 or write transmit data buffer 5. 5 1 read-write R6T6 Read receive data buffer 6 or write transmit data buffer 6. 6 1 read-write R7T7 Read receive data buffer 7 or write transmit data buffer 7. 7 1 read-write R8T8 Read receive data buffer 8 or write transmit data buffer 8. 8 1 read-write R9T9 Read receive data buffer 9 or write transmit data buffer 9. 9 1 read-write IDLINE Idle Line 11 1 read-only 0 Receiver was not idle before receiving this character. #0 1 Receiver was idle before receiving this character. #1 RXEMPT Receive Buffer Empty 12 1 read-only 0 Receive buffer contains valid data. #0 1 Receive buffer is empty, data returned on read is not valid. #1 FRETSC Frame Error / Transmit Special Character 13 1 read-write 0 The dataword was received without a frame error on read, transmit a normal character on write. #0 1 The dataword was received with a frame error, transmit an idle or break character on transmit. #1 PARITYE The current received dataword contained in DATA[R9:R0] was received with a parity error. 14 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 NOISY The current received dataword contained in DATA[R9:R0] was received with noise. 15 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 MATCH LPUART Match Address Register 0x10 32 read-write 0 0xFFFFFFFF MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x14 32 read-write 0 0xFFFFFFFF TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS assertion is configured by the RTSWATER field #1 TXCTSC Transmit CTS Configuration 4 1 read-write 0 CTS input is sampled at the start of each character. #0 1 CTS input is sampled when the transmitter is idle. #1 TXCTSSRC Transmit CTS Source 5 1 read-write 0 CTS input is the LPUART_CTS pin. #0 1 CTS input is the inverted Receiver Match result. #1 TNP Transmitter narrow pulse 16 2 read-write 00 1/OSR. #00 01 2/OSR. #01 10 3/OSR. #10 11 4/OSR. #11 IREN Infrared enable 18 1 read-write 0 IR disabled. #0 1 IR enabled. #1 LTC0 LTC 0x40058000 0 0x7F4 registers LTC0 23 MD Mode Register 0 32 read-write 0 0xFFFFFFFF ENC Encrypt/Decrypt. 0 1 read-write 0 Decrypt. #0 1 Encrypt. #1 ICV_TEST ICV Checking / Test AES fault detection. 1 1 read-write AS Algorithm State 2 2 read-write 00 Update #00 01 Initialize #01 10 Finalize #10 11 Initialize/Finalize #11 AAI Additional Algorithm information 4 9 read-write ALG Algorithm 16 8 read-write 00010000 AES #10000 KS Key Size Register 0x8 32 read-write 0x10 0xFFFFFFFF KS Key Size 0 5 write-only DS Data Size Register 0x10 32 read-write 0 0xFFFFFFFF DS Data Size 0 12 read-write ICVS ICV Size Register 0x18 32 read-write 0 0xFFFFFFFF ICVS ICV Size, in Bytes 0 5 read-write COM Command Register 0x30 32 read-write 0 0xFFFFFFFF ALL Reset All Internal Logic 0 1 write-only 0 Do Not Reset #0 1 Reset all CHAs in use by this CCB. #1 AES Reset AESA 1 1 write-only 0 Do Not Reset #0 1 Reset AES Accelerator #1 CTL Control Register 0x34 32 read-write 0 0xFFFFFFFF IM Interrupt Mask 0 1 read-write 0 Interrupt not masked. #0 1 Interrupt masked #1 IFE Input FIFO DMA Enable 8 1 read-write 0 DMA Request and Done signals disabled for the Input FIFO. #0 1 DMA Request and Done signals enabled for the Input FIFO. #1 IFR Input FIFO DMA Request Size 9 1 read-write 0 DMA request size is 1 entry. #0 1 DMA request size is 4 entries. #1 OFE Output FIFO DMA Enable 12 1 read-write 0 DMA Request and Done signals disabled for the Output FIFO. #0 1 DMA Request and Done signals enabled for the Output FIFO. #1 OFR Output FIFO DMA Request Size 13 1 read-write 0 DMA request size is 1 entry. #0 1 DMA request size is 4 entries. #1 IFS Input FIFO Byte Swap 16 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 OFS Output FIFO Byte Swap 17 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 KIS Key Register Input Byte Swap 20 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 KOS Key Register Output Byte Swap 21 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 CIS Context Register Input Byte Swap 22 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 COS Context Register Output Byte Swap 23 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 KAL Key Register Access Lock 31 1 read-write 0 Key Register is readable. #0 1 Key Register is not readable. #1 CW Clear Written Register 0x40 32 read-write 0 0xFFFFFFFF CM Clear the Mode Register 0 1 write-only CDS Clear the Data Size Register 2 1 write-only CICV Clear the ICV Size Register 3 1 write-only CCR Clear the Context Register 5 1 write-only CKR Clear the Key Register 6 1 write-only COF Clear Output FIFO 30 1 write-only CIF Clear Input FIFO 31 1 write-only STA Status Register 0x48 32 read-write 0 0xFFFFFFFF AB AESA Busy 1 1 read-only 0 AESA Idle #0 1 AESA Busy. #1 DI Done Interrupt 16 1 read-write EI Error Interrupt 20 1 read-only 0 Not Error. #0 1 Error Interrupt. #1 ESTA Error Status Register 0x4C 32 read-only 0 0xFFFFFFFF ERRID1 Error ID 1 0 4 read-only 0001 Mode Error #0001 0010 Data Size Error #0010 0011 Key Size Error #0011 0110 Data Arrived out of Sequence Error #0110 1010 ICV Check Failed #1010 1011 Internal Hardware Failure #1011 1100 CCM AAD Size Error (either 1. AAD flag in B0 =1 and no AAD type provided, 2. AAD flag in B0 = 0 and AAD povided, or 3. AAD flag in B0 =1 and not enough AAD provided - expecting more based on AAD size.) #1100 1111 Invalid Crypto Engine Selected #1111 CL1 algorithms 8 4 read-only 0000 General Error #0000 0001 AES #0001 AADSZ AAD Size Register 0x58 32 read-write 0 0xFFFFFFFF AADSZ AAD size in Bytes, mod 16 0 4 read-write AL AAD Last 31 1 read-write CTX_0 Context Register 0x100 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write CTX_1 Context Register 0x104 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write CTX_2 Context Register 0x108 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write CTX_3 Context Register 0x10C 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write CTX_4 Context Register 0x110 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write CTX_5 Context Register 0x114 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write CTX_6 Context Register 0x118 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write CTX_7 Context Register 0x11C 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write CTX_8 Context Register 0x120 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write CTX_9 Context Register 0x124 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write CTX_10 Context Register 0x128 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write CTX_11 Context Register 0x12C 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write CTX_12 Context Register 0x130 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write CTX_13 Context Register 0x134 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write KEY_0 Key Registers 0x200 32 read-write 0 0xFFFFFFFF KEY KEY 0 32 read-write KEY_1 Key Registers 0x204 32 read-write 0 0xFFFFFFFF KEY KEY 0 32 read-write KEY_2 Key Registers 0x208 32 read-write 0 0xFFFFFFFF KEY KEY 0 32 read-write KEY_3 Key Registers 0x20C 32 read-write 0 0xFFFFFFFF KEY KEY 0 32 read-write VID1 Version ID Register 0x4F0 32 read-only 0x340100 0xFFFFFFFF MIN_REV Minor revision number. 0 8 read-only MAJ_REV Major revision number. 8 8 read-only IP_ID ID(0x0034). 16 16 read-only VID2 Version ID 2 Register 0x4F4 32 read-only 0x101 0xFFFFFFFF ECO_REV ECO revision number. 0 8 read-only ARCH_ERA Architectural ERA. 8 8 read-only CHAVID CHA Version ID Register 0x4F8 32 read-only 0x50 0xFFFFFFFF AESREV AES Revision Number 0 4 read-only AESVID AES Version ID 4 4 read-only FIFOSTA FIFO Status Register 0x7C0 32 read-only 0 0xFFFFFFFF IFL Input FIFO Level 0 7 read-only IFF Input FIFO Full 15 1 read-only OFL Output FIFO Level 16 7 read-only OFF Output FIFO Full 31 1 read-only IFIFO Input Data FIFO 0x7E0 32 write-only 0 0xFFFFFFFF IFIFO IFIFO 0 32 write-only OFIFO Output Data FIFO 0x7F0 32 read-only 0 0xFFFFFFFF OFIFO Output FIFO 0 32 read-only RSIM_REGS RSIM 0x40059000 0 0x130 registers CONTROL Radio System Control 0 32 read-write 0xC00002 0xFFFFFFFF BLE_RF_OSC_REQ_EN BLE Ref Osc (Sysclk) Request Enable 0 1 read-write BLE_RF_OSC_REQ_STAT BLE Ref Osc (Sysclk) Request Status 1 1 read-only BLE_RF_OSC_REQ_INT_EN BLE Ref Osc (Sysclk) Request Interrupt Enable 4 1 read-write BLE_RF_OSC_REQ_INT BLE Ref Osc (Sysclk) Request Interrupt Flag 5 1 read-write RF_OSC_EN RF Ref Osc Enable Select 8 4 read-write 0000 RF Ref Osc will be controlled by the SoC, external pin, or a link layer #0000 0001 RF Ref Osc on in Run/Wait #0001 0011 RF Ref Osc on in Stop #0011 0111 RF Ref Osc on in VLPR/VLPW #0111 1111 RF Ref Osc on in VLPS #1111 RADIO_GASKET_BYPASS_OVRD_EN Radio Gasket Bypass Override Enable 12 1 read-write RADIO_GASKET_BYPASS_OVRD Radio Gasket Bypass Override 13 1 read-write IPP_OBE_3V_BLE_ACTIVE_1 IPP_OBE_3V_BLE_ACTIVE_1 16 1 read-write IPP_OBE_3V_BLE_ACTIVE_2 IPP_OBE_3V_BLE_ACTIVE_2 17 1 read-write RADIO_RAM_ACCESS_OVRD_EN Radio RAM Access Override Enable 18 1 read-write RADIO_RAM_ACCESS_OVRD Radio RAM Access Override 19 1 read-write RSIM_DSM_EXIT BLE Force Deep Sleep Mode Exit 20 1 read-write RSIM_STOP_ACK_OVRD_EN Stop Acknowledge Override Enable 22 1 read-write RSIM_STOP_ACK_OVRD Stop Acknowledge Override 23 1 read-write RF_OSC_READY RF Ref Osc Ready 24 1 read-only RF_OSC_READY_OVRD_EN RF Ref Osc Ready Override Enable 25 1 read-write RF_OSC_READY_OVRD RF Ref Osc Ready Override 26 1 read-write BLOCK_SOC_RESETS Block SoC Resets of the Radio 28 1 read-write BLOCK_RADIO_OUTPUTS Block Radio Outputs 29 1 read-write ALLOW_DFT_RESETS Allow the DFT Reset Pin to Reset the Radio 30 1 read-write RADIO_RESET_BIT Software Reset for the Radio 31 1 read-write ACTIVE_DELAY Radio Active Early Warning 0x4 32 read-write 0 0xFFFFFFFF BLE_FINE_DELAY BLE Active Fine Delay 0 6 read-write BLE_COARSE_DELAY BLE Active Coarse Delay 16 4 read-write MAC_MSB Radio MAC Address 0x8 32 read-only 0 0xFFFFFFFF MAC_ADDR_MSB Radio MAC Address MSB 0 8 read-only MAC_LSB Radio MAC Address 0xC 32 read-only 0 0xFFFFFFFF MAC_ADDR_LSB Radio MAC Address LSB 0 32 read-only MISC Radio Miscellaneous 0x10 32 read-write 0x3000000 0xFFFFFFFF ANALOG_TEST_EN RSIM Analog Test Mux Enables 0 5 read-write RADIO_VERSION Radio Version ID number 24 8 read-write DSM_TIMER Deep Sleep Timer 0x100 32 read-only 0 0xFFFFFFFF DSM_TIMER Deep Sleep Mode Timer 0 24 read-only DSM_CONTROL Deep Sleep Timer Control 0x104 32 read-write 0 0xFFFFFFFF DSM_ANT_READY ANT Ready for Deep Sleep Mode 0 1 read-only ANT_DEEP_SLEEP_STATUS ANT Link Layer Deep Sleep Mode Status 1 1 read-only DSM_ANT_FINISHED ANT Deep Sleep Time Finished 2 1 read-only ANT_SYSCLK_REQUEST_EN Enable ANT Link Layer to Request RF OSC 3 1 read-write ANT_SLEEP_REQUEST ANT Link Layer Deep Sleep Requested 4 1 read-only ANT_SYSCLK_REQ ANT Link Layer RF OSC Request Status 5 1 read-only ANT_SYSCLK_INTERRUPT_EN ANT Link Layer RF OSC Request Interrupt Enable 6 1 read-write ANT_SYSCLK_REQ_INT Interrupt Flag from an ANT Link Layer RF OSC Request 7 1 read-write DSM_GEN_READY Generic FSK Ready for Deep Sleep Mode 8 1 read-only GEN_DEEP_SLEEP_STATUS Generic FSK Link Layer Deep Sleep Mode Status 9 1 read-only DSM_GEN_FINISHED Generic FSK Deep Sleep Time Finished 10 1 read-only GEN_SYSCLK_REQUEST_EN Enable Generic FSK Link Layer to Request RF OSC 11 1 read-write GEN_SLEEP_REQUEST Generic FSK Link Layer Deep Sleep Requested 12 1 read-only GEN_SYSCLK_REQ Generic FSK Link Layer RF OSC Request Status 13 1 read-only GEN_SYSCLK_INTERRUPT_EN Generic FSK Link Layer RF OSC Request Interrupt Enable 14 1 read-write GEN_SYSCLK_REQ_INT Interrupt Flag from an Generic FSK Link Layer RF OSC Request 15 1 read-only DSM_ZIG_READY 802.15.4 Ready for Deep Sleep Mode 16 1 read-only ZIG_DEEP_SLEEP_STATUS 802.15.4 Link Layer Deep Sleep Mode Status 17 1 read-only DSM_ZIG_FINISHED 802.15.4 Deep Sleep Time Finished 18 1 read-only ZIG_SYSCLK_REQUEST_EN Enable 802.15.4 Link Layer to Request RF OSC 19 1 read-write ZIG_SLEEP_REQUEST 802.15.4 Link Layer Deep Sleep Requested 20 1 read-only ZIG_SYSCLK_REQ 802.15.4 Link Layer RF OSC Request Status 21 1 read-only ZIG_SYSCLK_INTERRUPT_EN 802.15.4 Link Layer RF OSC Request Interrupt Enable 22 1 read-write ZIG_SYSCLK_REQ_INT Interrupt Flag from an 802.15.4 Link Layer RF OSC Request 23 1 read-only DSM_TIMER_CLR Deep Sleep Mode Timer Clear 27 1 read-write DSM_TIMER_EN Deep Sleep Mode Timer Enable 31 1 read-write DSM_OSC_OFFSET Deep Sleep Wakeup Time Offset 0x108 32 read-write 0 0xFFFFFFFF DSM_OSC_STABILIZE_TIME Deep Sleep Wakeup RF OSC Stabilize Time 0 10 read-write ANT_SLEEP ANT Link Layer Sleep Time 0x10C 32 read-write 0 0xFFFFFFFF ANT_SLEEP_TIME ANT Link Layer Sleep Time 0 24 read-write ANT_WAKE ANT Link Layer Wake Time 0x110 32 read-write 0 0xFFFFFFFF ANT_WAKE_TIME ANT Link Layer Wake Time 0 24 read-write ZIG_SLEEP 802.15.4 Link Layer Sleep Time 0x114 32 read-write 0 0xFFFFFFFF ZIG_SLEEP_TIME 802.15.4 Link Layer Sleep Time 0 24 read-write ZIG_WAKE 802.15.4 Link Layer Wake Time 0x118 32 read-write 0 0xFFFFFFFF ZIG_WAKE_TIME 802.15.4 Link Layer Wake Time 0 24 read-write GEN_SLEEP Generic FSK Link Layer Sleep Time 0x11C 32 read-write 0 0xFFFFFFFF GEN_SLEEP_TIME Generic FSK Link Layer Sleep Time 0 24 read-write GEN_WAKE Generic FSK Link Layer Wake Time 0x120 32 read-write 0 0xFFFFFFFF GEN_WAKE_TIME Generic FSK Link Layer Wake Time 0 24 read-write RF_OSC_CTRL Radio Oscillator Control 0x124 32 read-write 0x203806 0xFFFFFFFF BB_XTAL_ALC_COUNT_SEL rmap_bb_xtal_alc_count_sel_hv[1:0] 0 2 read-write BB_XTAL_ALC_ON rmap_bb_xtal_alc_on_hv 2 1 read-write RF_OSC_BYPASS_EN RF Ref Osc Bypass Enable 3 1 read-write BB_XTAL_COMP_BIAS rmap_bb_xtal_comp_bias_hv[4:0] 4 5 read-write BB_XTAL_DC_COUP_MODE_EN rmap_bb_xtal_dc_coup_mode_en_hv 9 1 read-write BB_XTAL_DIAGSEL rmap_bb_xtal_diagsel_hv 10 1 read-write BB_XTAL_DIG_CLK_ON rmap_bb_xtal_dig_clk_on_hv 11 1 read-write BB_XTAL_GM rmap_bb_xtal_gm_hv[4:0] 12 5 read-write BB_XTAL_ON_OVRD rmap_bb_xtal_on_ovrd_hv 17 1 read-write BB_XTAL_ON_OVRD_ON rmap_bb_xtal_on_ovrd_on_hv 18 1 read-write BB_XTAL_READY_COUNT_SEL rmap_bb_xtal_ready_count_sel_hv[1:0] 20 2 read-write RADIO_EXT_OSC_RF_EN_SEL Radio External Request for RF OSC Select 27 1 read-write RADIO_EXT_OSC_OVRD Radio External Request for RF OSC Override 28 1 read-write RADIO_EXT_OSC_OVRD_EN Radio External Request for RF OSC Override Enable 29 1 read-write RADIO_RF_ABORT_OVRD Radio RF Abort Override 30 1 read-write RADIO_RF_ABORT_OVRD_EN Radio RF Abort Override Enable 31 1 read-write ANA_TEST Radio Analog Test Registers 0x128 32 read-write 0 0xFFFFFFFF BB_LDO_LS_BYP rmap_bb_ldo_ls_byp_hv 0 1 read-write BB_LDO_LS_DIAGSEL rmap_bb_ldo_ls_diagsel_hv 1 1 read-write BB_LDO_XO_BYP_ON rmap_bb_ldo_xo_byp_on_hv 2 1 read-write BB_LDO_XO_DIAGSEL rmap_bb_ldo_xo_diagsel_hv 3 1 read-write BB_XTAL_TEST rmap_bb_xtal_test_en_hv 4 1 read-write BG_DIAGBUF rmap_bg_diagbuf_hv 5 1 read-write BG_DIAGSEL rmap_bg_diagsel_hv 6 1 read-write BG_STARTUPFORCE rmap_bg_startupforce_hv 7 1 read-write DIAG_1234_ON rmap_diag_1234_on_hv 8 1 read-write DIAG2SOCADC_DEC rmap_diag2socadc_dec_hv[1:0] 9 2 read-write DIAG2SOCADC_DEC_ON rmap_diag2socadc_dec_on_hv 11 1 read-write DIAGCODE rmap_diagcode_hv[2:0] 12 3 read-write ANA_TRIM Radio Analog Trim Registers 0x12C 32 read-write 0x784B0000 0xFFFFFFFF BB_LDO_LS_SPARE rmap_bb_ldo_ls_spare_hv[1:0] 0 2 read-write BB_LDO_LS_TRIM rmap_bb_ldo_ls_trim_hv[2:0] 3 3 read-write BB_LDO_XO_SPARE rmap_bb_ldo_xo_spare_hv[1:0] 6 2 read-write BB_LDO_XO_TRIM rmap_bb_ldo_xo_trim_hv[2:0] 8 3 read-write BB_XTAL_SPARE rmap_bb_xtal_spare_hv[4:0] 11 5 read-write BB_XTAL_TRIM rmap_bb_xtal_trim_hv[7:0] 16 8 read-write BG_1V_TRIM rmap_bg_1v_trim_hv[3:0] 24 4 read-write BG_IBIAS_5U_TRIM rmap_bg_ibias_5u_trim_hv[3:0] 28 4 read-write DCDC DC to DC Converter DCDC_ 0x4005A000 0 0x20 registers LVD_LVW_DCDC 6 REG0 DCDC REGISTER 0 0 32 read-write 0x4180000 0xFFFFFFFF DCDC_DISABLE_AUTO_CLK_SWITCH Disable automatic clock switch from internal oscillator to external clock. 1 1 read-write DCDC_SEL_CLK Select external clock for DCDC when DCDC_DISABLE_AUTO_CLK_SWITCH is set. 2 1 read-write DCDC_PWD_OSC_INT Power down internal oscillator. Only set this bit when 32M crystal oscillator is available. 3 1 read-write DCDC_LP_DF_CMP_ENABLE Enable low power differential comparators, to sense lower supply in pulsed mode 9 1 read-write DCDC_VBAT_DIV_CTRL Controls VBAT voltage divider 10 2 read-write DCDC_LP_STATE_HYS_L Configure the hysteretic lower threshold value in low power mode 17 2 read-write 00 Target voltage value - 0 mV #00 01 Target voltage value - 25 mV #01 10 Target voltage value - 50 mV #10 11 Target voltage value - 75 mV #11 DCDC_LP_STATE_HYS_H Configure the hysteretic upper threshold value in low power mode 19 2 read-write 00 Target voltage value + 0 mV #00 01 Target voltage value + 25 mV #01 10 Target voltage value + 50 mV #10 11 Target voltage value + 75 mV #11 HYST_LP_COMP_ADJ Adjust hysteretic value in low power comparator. 21 1 read-write HYST_LP_CMP_DISABLE Disable hysteresis in low power comparator. 22 1 read-write OFFSET_RSNS_LP_ADJ Adjust hysteretic value in low power voltage sense. 23 1 read-write OFFSET_RSNS_LP_DISABLE Disable hysteresis in low power voltage sense. 24 1 read-write DCDC_LESS_I Reduce DCDC current. It will save approximately 20 uA in RUN. 25 1 read-write PWD_CMP_OFFSET Power down output range comparator 26 1 read-write DCDC_XTALOK_DISABLE Disable xtalok detection circuit. 27 1 read-write PSWITCH_STATUS Status register to indicate PSWITCH status 28 1 read-only VLPS_CONFIG_DCDC_HP Selects behavior of DCDC in device VLPS low power mode 29 1 read-write VLPR_VLPW_CONFIG_DCDC_HP Selects behavior of DCDC in device VLPR and VLPW low power modes 30 1 read-write DCDC_STS_DC_OK Status register to indicate DCDC lock 31 1 read-only REG1 DCDC REGISTER 1 0x4 32 read-write 0x17C21C 0xFFFFFFFF POSLIMIT_BUCK_IN Upper limit duty cycle limit in DC-DC converter 0 7 read-write POSLIMIT_BOOST_IN Upper limit duty cycle limit in DC-DC converter 7 7 read-write DCDC_LOOPCTRL_CM_HST_THRESH Enable hysteresis in switching converter common mode analog comparators 21 1 read-write DCDC_LOOPCTRL_DF_HST_THRESH Enable hysteresis in switching converter differential mode analog comparators 22 1 read-write DCDC_LOOPCTRL_EN_CM_HYST Enable hysteresis in switching converter common mode analog comparators 23 1 read-write DCDC_LOOPCTRL_EN_DF_HYST Enable hysteresis in switching converter differential mode analog comparators 24 1 read-write REG2 DCDC REGISTER 2 0x8 32 read-write 0x4009 0xFFFFFFFF DCDC_LOOPCTRL_HYST_SIGN Invert the sign of the hysteresis in DC-DC analog comparators. This bit is set when in Pulsed mode. 13 1 read-write DCDC_BATTMONITOR_EN_BATADJ This bit enables the DC-DC to improve efficiency and minimize ripple using the information from the BATT_VAL field 15 1 read-write DCDC_BATTMONITOR_BATT_VAL Software should be configured to place the battery voltage in this register measured with an 8 mV LSB resolution through the ADC 16 10 read-write REG3 DCDC REGISTER 3 0xC 32 read-write 0xAA46 0xFFFFFFFF DCDC_VDD1P8CTRL_TRG Target value of VDD1P8, 25 mV each step in two ranges, from 0x00 to 0x11 and 0x20 to 0x3F. 0 6 read-write 0 1.65 V #0 110 1.8 V #110 10001 2.075 V #10001 100000 2.8 V #100000 110100 3.3 V #110100 111111 3.575 V #111111 DCDC_VDD1P5CTRL_TRG_BUCK Target value of VDD1P5 in buck mode, 25 mV each step from 0x00 to 0x0F 6 5 read-write 1111 1.65 V #01111 1001 1.5 V #01001 0 1.275 V #00000 DCDC_VDD1P5CTRL_TRG_BOOST Target value of VDD1P5 in boost mode, 25 mV each step from 0x00 to 0x0F 11 5 read-write 10101 1.8 V #10101 1111 1.65 V #01111 1001 1.5 V #01001 0 1.275 V #00000 DCDC_VDD1P5CTRL_ADJTN Adjust value of duty cycle when switching between VDD1P5 and VDD1P8. The unit is 1/32 or 3.125%. 17 4 read-write DCDC_MINPWR_DC_HALFCLK_PULSED Set DCDC clock to half frequency for the Pulsed mode. 21 1 read-write DCDC_MINPWR_DOUBLE_FETS_PULSED Use double switch FET for the Pulsed mode. 22 1 read-write DCDC_MINPWR_HALF_FETS_PULSED Use half switch FET for the Pulsed mode. 23 1 read-write DCDC_MINPWR_DC_HALFCLK Set DCDC clock to half frequency for the continuous mode. 24 1 read-write DCDC_MINPWR_DOUBLE_FETS Use double switch FET for the continuous mode. 25 1 read-write DCDC_MINPWR_HALF_FETS Use half switch FET for the continuous mode. 26 1 read-write DCDC_VDD1P5CTRL_DISABLE_STEP Disable stepping for VDD1P5. Must set this bit before enter low power modes. 29 1 read-write DCDC_VDD1P8CTRL_DISABLE_STEP Disable stepping for VDD1P8. Must set this bit before enter low power modes. 30 1 read-write REG4 DCDC REGISTER 4 0x10 32 read-write 0 0xFFFFFFFF DCDC_SW_SHUTDOWN Shut down DCDC in buck mode. DCDC can be turned on by pulling PSWITCH to high momentarily (min 50 ms).DCDC_SW_SHUTDOWN should not be used in boost mode because when user write this bit, MCU won't be POR and enters an abnormal state. 0 1 read-write UNLOCK 0x3E77 KEY-Key needed to unlock HW_POWER_RESET register 16 16 read-write REG6 DCDC REGISTER 6 0x18 32 read-write 0 0xFFFFFFFF PSWITCH_INT_RISE_EN Enable rising edge detect for interrupt. 0 1 read-write PSWITCH_INT_FALL_EN Enable falling edge detect for interrupt. 1 1 read-write PSWITCH_INT_CLEAR Write 1 to clear interrupt. Set to 0 after clear. 2 1 read-write PSWITCH_INT_MUTE Mask interrupt to SoC, edge detection result can be read from PSIWTCH_INT_STS. 3 1 read-write PSWITCH_INT_STS PSWITCH edge detection interrupt status 31 1 read-only REG7 DCDC REGISTER 7 0x1C 32 read-write 0 0xFFFFFFFF INTEGRATOR_VALUE Integrator value which can be loaded in pulsed mode 0 19 read-write INTEGRATOR_VALUE_SEL Select the integrator value from above register or saved value in hardware. 19 1 read-write PULSE_RUN_SPEEDUP Enable pulse run speedup 20 1 read-write RX_DIG XCVR_RX_DIG 0x4005C000 0 0x200 registers RX_DIG_CTRL RX Digital Control 0 32 read-write 0 0xFFFFFFFF RX_ADC_NEGEDGE Receive ADC Negative Edge Selection 0 1 read-write 0 Register ADC data on positive edge of clock #0 1 Register ADC data on negative edge of clock #1 RX_CH_FILT_BYPASS Receive Channel Filter Bypass 1 1 read-write 0 Channel filter is enabled. #0 1 Disable and bypass channel filter. #1 RX_ADC_RAW_EN ADC Raw Mode selection 2 1 read-write 0 Normal operation. #0 1 The decimation filter's 12bit output consists of ADC samples in the 8 LSBs. This is for test purposes only to observe ADC output via XCVR DMA or DTEST. #1 RX_ADC_POL Receive ADC Polarity 3 1 read-write 0 ADC output of 1'b0 maps to -1, 1'b1 maps to +1 (default) #0 1 ADC output of 1'b0 maps to +1, 1'b1 maps to -1 #1 RX_DEC_FILT_OSR Decimation Filter Oversampling 4 3 read-write 0 OSR 4 #000 1 OSR 8 #001 2 OSR 16 #010 4 OSR 32 #100 3 OSR 6 #011 5 OSR 12 #101 6 OSR 24 #110 RX_FSK_ZB_SEL FSK / 802.15.4 demodulator select 8 1 read-write 0 FSK demodulator. #0 1 802.15.4 demodulator. #1 RX_NORM_EN Normalizer Enable 9 1 read-write 0 Normalizer is disabled. #0 1 Normalizer is enabled. #1 RX_RSSI_EN RSSI Measurement Enable 10 1 read-write 0 RSSI measurement is disabled. #0 1 RSSI measurement is enabled. #1 RX_AGC_EN AGC Global Enable 11 1 read-write 0 AGC is disabled. #0 1 AGC is enabled. #1 RX_DCOC_EN DCOC Enable 12 1 read-write 0 DCOC is disabled. #0 1 DCOC is enabled. #1 RX_DCOC_CAL_EN DCOC Calibration Enable 13 1 read-write 0 DCOC calibration is disabled. #0 1 DCOC calibration is enabled. #1 RX_IQ_SWAP RX IQ Swap 14 1 read-write 0 IQ swap is disabled. #0 1 IQ swap is enabled. #1 RX_DC_RESID_EN DC Residual Enable 15 1 read-write 0 DC Residual block is disabled. #0 1 DC Residual block is enabled. #1 RX_SRC_EN RX Sample Rate Converter Enable 16 1 read-write 0 SRC is disabled. #0 1 SRC is enabled. #1 RX_SRC_RATE RX Sample Rate Converter Rate Selections 17 1 read-write 0 SRC is configured for a First Order Hold rate of 8/13. #0 1 SRC is configured for a Zero Order Hold rate of 12/13. #1 RX_DMA_DTEST_EN RX DMA and DTEST enable 18 1 read-write RX_DEC_FILT_GAIN Decimation Filter Fractional Gain 20 5 read-write RX_DEC_FILT_HZD_CORR_DIS Decimator filter hazard correction disable 25 1 read-write RX_DEC_FILT_HAZARD Decimator output, hazard condition detected 28 1 read-only 0 A hazard condition has not been detected #0 1 A hazard condition has been detected #1 RX_RSSI_FILT_HAZARD Decimator output for RSSI, hazard condition detected 29 1 read-only 0 A hazard condition has not been detected #0 1 A hazard condition has been detected #1 RX_DEC_FILT_SAT_I Decimator output, saturation detected for I channel 30 1 read-only 0 A saturation condition has not occurred. #0 1 A saturation condition has occurred. #1 RX_DEC_FILT_SAT_Q Decimator output, saturation detected for Q channel 31 1 read-only 0 A saturation condition has not occurred. #0 1 A saturation condition has occurred. #1 AGC_CTRL_0 AGC Control 0 0x4 32 read-write 0 0xFFFFFFFF SLOW_AGC_EN Slow AGC Enable 0 1 read-write SLOW_AGC_SRC Slow AGC Source Selection 1 2 read-write 0 Access Address match (for active protocol) #00 1 Preamble Detect (for active protocol) #01 2 Fast AGC expire timer #10 AGC_FREEZE_EN AGC Freeze Enable 3 1 read-write AGC_FREEZE_PRE_OR_AA AGC Freeze Source Selection 4 1 read-write 0 Access Address match (for active protocol) #0 1 Preamble Detect (for active protocol) #1 AGC_UP_EN AGC Up Enable 6 1 read-write AGC_UP_SRC AGC Up Source 7 1 read-write 0 PDET LO #0 1 RSSI #1 AGC_DOWN_BBA_STEP_SZ AGC_DOWN_BBA_STEP_SZ 8 4 read-write AGC_DOWN_LNA_STEP_SZ AGC_DOWN_LNA_STEP_SZ 12 4 read-write AGC_UP_RSSI_THRESH AGC UP RSSI Threshold 16 8 read-write AGC_DOWN_RSSI_THRESH AGC DOWN RSSI Threshold 24 8 read-write AGC_CTRL_1 AGC Control 1 0x8 32 read-write 0 0xFFFFFFFF BBA_ALT_CODE BBA_ALT_CODE 0 4 read-write LNA_ALT_CODE LNA_ALT_CODE 4 8 read-write LNA_USER_GAIN LNA_USER_GAIN 12 4 read-write BBA_USER_GAIN BBA_USER_GAIN 16 4 read-write USER_LNA_GAIN_EN User LNA Gain Enable 20 1 read-write USER_BBA_GAIN_EN User BBA Gain Enable 21 1 read-write PRESLOW_EN Pre-slow Enable 22 1 read-write 0 Pre-slow is disabled. #0 1 Pre-slow is enabled. #1 LNA_GAIN_SETTLE_TIME LNA_GAIN_SETTLE_TIME 24 8 read-write AGC_CTRL_2 AGC Control 2 0xC 32 read-write 0xA69000 0xFFFFFFFF BBA_PDET_RST BBA PDET Reset 0 1 read-write TZA_PDET_RST TZA PDET Reset 1 1 read-write MAN_PDET_RST MAN PDET Reset 2 1 read-write 0 The peak detector reset signals are controlled automatically by the AGC. #0 1 The BBA_PDET_RST and TZA_PDET_RST are used to manually control the peak detector reset signals. #1 BBA_GAIN_SETTLE_TIME BBA Gain Settle Time 4 8 read-write BBA_PDET_SEL_LO BBA PDET Threshold Low 12 3 read-write 000 0.600V #000 001 0.615V #001 010 0.630V #010 011 0.645V #011 100 0.660V #100 101 0.675V #101 110 0.690V #110 111 0.705V #111 BBA_PDET_SEL_HI BBA PDET Threshold High 15 3 read-write 000 0.600V #000 001 0.795V #001 010 0.900V #010 011 0.945V #011 100 1.005V #100 101 1.050V #101 110 1.095V #110 111 1.155V #111 TZA_PDET_SEL_LO TZA PDET Threshold Low 18 3 read-write 000 0.600V #000 001 0.615V #001 010 0.630V #010 011 0.645V #011 100 0.660V #100 101 0.675V #101 110 0.690V #110 111 0.705V #111 TZA_PDET_SEL_HI TZA PDET Threshold High 21 3 read-write 000 0.60V #000 001 0.63V #001 010 0.66V #010 011 0.69V #011 100 0.72V #100 101 0.75V #101 110 0.78V #110 111 0.81V #111 AGC_FAST_EXPIRE AGC Fast Expire 24 6 read-write LNA_LG_ON_OVR LNA_LG_ON override 30 1 read-write LNA_HG_ON_OVR LNA_HG_ON override 31 1 read-write AGC_CTRL_3 AGC Control 3 0x10 32 read-write 0 0xFFFFFFFF AGC_UNFREEZE_TIME AGC Unfreeze Time 0 13 read-write AGC_PDET_LO_DLY AGC Peak Detect Low Delay 13 3 read-write AGC_RSSI_DELT_H2S AGC_RSSI_DELT_H2S 16 7 read-write AGC_H2S_STEP_SZ AGC_H2S_STEP_SZ 23 5 read-write AGC_UP_STEP_SZ AGC Up Step Size 28 4 read-write AGC_STAT AGC Status 0x14 32 read-only 0 0xFFFFFFFF BBA_PDET_LO_STAT BBA Peak Detector Low Status 0 1 read-only BBA_PDET_HI_STAT BBA Peak Detector High Status 1 1 read-only TZA_PDET_LO_STAT TZA Peak Detector Low Status 2 1 read-only TZA_PDET_HI_STAT TZA Peak Detector High Status 3 1 read-only CURR_AGC_IDX Current AGC Gain Index 4 5 read-only AGC_FROZEN AGC Frozen Status 9 1 read-only 0 AGC is not frozen. #0 1 AGC is frozen. #1 RSSI_ADC_RAW ADC RAW RSSI Reading 16 8 read-only RSSI_CTRL_0 RSSI Control 0 0x18 32 read-write 0x300000 0xFFFFFFFF RSSI_USE_VALS RSSI Values Selection 0 1 read-write RSSI_HOLD_SRC RSSI Hold Source Selection 1 2 read-write 00 Access Address match #00 01 Preamble Detect #01 11 802.15.4 LQI done (1=freeze, 0=run AGC) #11 RSSI_HOLD_EN RSSI Hold Enable 3 1 read-write RSSI_IIR_CW_WEIGHT RSSI IIR CW Weighting 5 2 read-write 0 Bypass #00 1 1/8 #01 2 1/16 #10 3 1/32 #11 RSSI_N_WINDOW_AVG RSSI N Window Average 8 2 read-write 0 No averaging #00 1 Averaging window length is 2 samples #01 2 Averaging window length is 4 samples #10 3 Averaging window length is 8 samples #11 RSSI_HOLD_DELAY RSSI Hold Delay 10 6 read-write RSSI_IIR_WEIGHT RSSI IIR Weighting 16 4 read-write 0 Bypass #0000 1 1/2 #0001 2 1/4 #0010 3 1/8 #0011 4 1/16 #0100 5 1/32 #0101 RSSI_VLD_SETTLE RSSI Valid Settle 20 3 read-write RSSI_ADJ RSSI Adjustment 24 8 read-write RSSI_CTRL_1 RSSI Control 1 0x1C 32 read-only 0 0xFFFFFFFF RSSI_OUT RSSI Reading 24 8 read-only RSSI_DFT RSSI DFT 0x20 32 read-only 0 0xFFFFFFFF DFT_MAG RSSI MAG 0 13 read-only DFT_NOISE RSSI MAG 16 13 read-only DCOC_CTRL_0 DCOC Control 0 0x24 32 read-write 0 0xFFFFFFFF DCOC_MIDPWR_TRK_DIS DCOC Mid Power Tracking Disable 0 1 read-write 0 Tracking corrections are enabled as determined by DCOC_CORRECT_SRC and DCOC_TRK_MIN_AGC_IDX. #0 1 Tracking corrections are disabled when either the TZA or BBA lo peak detector asserts. #1 DCOC_MAN DCOC Manual Override 1 1 read-write DCOC_TRK_EST_OVR Override for the DCOC tracking estimator 2 1 read-write 0 The tracking estimator is enabled only as needed by the corrector #0 1 The tracking estimator remains enabled whenever the DCOC is active #1 DCOC_CORRECT_SRC DCOC Corrector Source 3 1 read-write 0 If correction is enabled, the DCOC will use only the DCOC calibration table to correct the DC offset. #0 1 If correction is enabled, the DCOC will use the DCOC calibration table and then the tracking estimator to correct the DC offset. #1 DCOC_CORRECT_EN DCOC Correction Enable 4 1 read-write 0 Correction disabled. The DCOC will not correct the DC offset. #0 1 Correction enabled. The DCOC will use the TZA and BBA DACs, and apply digital corrections (if DCOC_CORRECT_SRC=1) to correct the DC offset. #1 TRACK_FROM_ZERO Track from Zero 5 1 read-write 0 Track from current I/Q sample. #0 1 Track from zero. #1 BBA_CORR_POL BBA Correction Polarity 6 1 read-write 0 Normal polarity. #0 1 Negative polarity. This should be set if the ADC output is inverted, or if the BBA DACs were implemented with negative polarity. #1 TZA_CORR_POL TZA Correction Polarity 7 1 read-write 0 Normal polarity. #0 1 Negative polarity. This should be set if the ADC output is inverted, or if the TZA DACs were implemented with negative polarity. #1 DCOC_CAL_DURATION DCOC Calibration Duration 8 5 read-write DCOC_CORR_DLY DCOC Correction Delay 16 5 read-write DCOC_CORR_HOLD_TIME DCOC Correction Hold Time 24 7 read-write 127 The DC correction is not frozen. #1111111 DCOC_CTRL_1 DCOC Control 1 0x28 32 read-write 0 0xFFFFFFFF DCOC_SIGN_SCALE_IDX DCOC Sign Scaling 0 2 read-write 00 1/8 #00 01 1/16 #01 10 1/32 #10 11 1/64 #11 DCOC_ALPHAC_SCALE_IDX DCOC Alpha-C Scaling 2 3 read-write 000 1/2 #000 001 1/4 #001 010 1/8 #010 011 1/16 #011 100 1/32 #100 101 1/64 #101 DCOC_ALPHA_RADIUS_IDX Alpha-R Scaling 5 3 read-write 000 1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 DCOC_TRK_EST_GS_CNT DCOC Tracking Estimator Gearshift Count 12 3 read-write DCOC_SIGN_SCALE_GS_IDX DCOC Sign Scaling for Gearshift 16 2 read-write 00 1/8 #00 01 1/16 #01 10 1/32 #10 11 1/64 #11 DCOC_ALPHAC_SCALE_GS_IDX DCOC Alpha-C Scaling for Gearshift 18 3 read-write 000 1/2 #000 001 1/4 #001 010 1/8 #010 011 1/16 #011 100 1/32 #100 101 1/64 #101 DCOC_ALPHA_RADIUS_GS_IDX Alpha-R Scaling for Gearshift 21 3 read-write 000 1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 DCOC_TRK_MIN_AGC_IDX DCOC Tracking Minimum AGC Table Index 24 5 read-write DCOC_DAC_INIT DCOC DAC Initialization 0x2C 32 read-write 0x80802020 0xFFFFFFFF BBA_DCOC_INIT_I DCOC BBA Init I 0 6 read-write BBA_DCOC_INIT_Q DCOC BBA Init Q 8 6 read-write TZA_DCOC_INIT_I DCOC TZA Init I 16 8 read-write TZA_DCOC_INIT_Q DCOC TZA Init Q 24 8 read-write DCOC_DIG_MAN DCOC Digital Correction Manual Override 0x30 32 read-write 0 0xFFFFFFFF DIG_DCOC_INIT_I DCOC DIG Init I 0 12 read-write DIG_DCOC_INIT_Q DCOC DIG Init Q 16 12 read-write DCOC_CAL_GAIN DCOC Calibration Gain 0x34 32 read-write 0 0xFFFFFFFF DCOC_BBA_CAL_GAIN1 DCOC BBA Calibration Gain 1 8 4 read-write DCOC_LNA_CAL_GAIN1 DCOC LNA Calibration Gain 1 12 4 read-write DCOC_BBA_CAL_GAIN2 DCOC BBA Calibration Gain 2 16 4 read-write DCOC_LNA_CAL_GAIN2 DCOC LNA Calibration Gain 2 20 4 read-write DCOC_BBA_CAL_GAIN3 DCOC BBA Calibration Gain 3 24 4 read-write DCOC_LNA_CAL_GAIN3 DCOC LNA Calibration Gain 3 28 4 read-write DCOC_STAT DCOC Status 0x38 32 read-only 0x80802020 0xFFFFFFFF BBA_DCOC_I DCOC BBA DAC I 0 6 read-only BBA_DCOC_Q DCOC BBA DAC Q 8 6 read-only TZA_DCOC_I DCOC TZA DAC I 16 8 read-only TZA_DCOC_Q DCOC TZA DAC Q 24 8 read-only DCOC_DC_EST DCOC DC Estimate 0x3C 32 read-only 0 0xFFFFFFFF DC_EST_I DCOC DC Estimate I 0 12 read-only DC_EST_Q DCOC DC Estimate Q 16 12 read-only DCOC_CAL_RCP DCOC Calibration Reciprocals 0x40 32 read-write 0 0xFFFFFFFF DCOC_TMP_CALC_RECIP DCOC Calculation Reciprocal 0 11 read-write ALPHA_CALC_RECIP Alpha Calculation Reciprocal 16 11 read-write IQMC_CTRL IQMC Control 0x48 32 read-write 0x4008000 0xFFFFFFFF IQMC_CAL_EN IQ Mismatch Cal Enable 0 1 read-write IQMC_NUM_ITER IQ Mismatch Cal Num Iter 8 8 read-write IQMC_DC_GAIN_ADJ IQ Mismatch Correction DC Gain Coeff 16 11 read-write IQMC_CAL IQMC Calibration 0x4C 32 read-write 0x400 0xFFFFFFFF IQMC_GAIN_ADJ IQ Mismatch Correction Gain Coeff 0 11 read-write IQMC_PHASE_ADJ IQ Mismatch Correction Phase Coeff 16 12 read-write LNA_GAIN_VAL_3_0 LNA_GAIN Step Values 3..0 0x50 32 read-write 0x3809321D 0xFFFFFFFF LNA_GAIN_VAL_0 LNA_GAIN step 0 0 8 read-write LNA_GAIN_VAL_1 LNA_GAIN step 1 8 8 read-write LNA_GAIN_VAL_2 LNA_GAIN step 2 16 8 read-write LNA_GAIN_VAL_3 LNA_GAIN step 3 24 8 read-write LNA_GAIN_VAL_7_4 LNA_GAIN Step Values 7..4 0x54 32 read-write 0x8B745D4F 0xFFFFFFFF LNA_GAIN_VAL_4 LNA_GAIN step 4 0 8 read-write LNA_GAIN_VAL_5 LNA_GAIN step 5 8 8 read-write LNA_GAIN_VAL_6 LNA_GAIN step 6 16 8 read-write LNA_GAIN_VAL_7 LNA_GAIN step 7 24 8 read-write LNA_GAIN_VAL_8 LNA_GAIN Step Values 8 0x58 32 read-write 0xB6A1 0xFFFFFFFF LNA_GAIN_VAL_8 LNA_GAIN step 8 0 8 read-write LNA_GAIN_VAL_9 LNA_GAIN step 9 8 8 read-write BBA_RES_TUNE_VAL_7_0 BBA Resistor Tune Values 7..0 0x5C 32 read-write 0 0xFFFFFFFF BBA_RES_TUNE_VAL_0 BBA Resistor Tune Step 0 0 4 read-write BBA_RES_TUNE_VAL_1 BBA Resistor Tune Step 1 4 4 read-write BBA_RES_TUNE_VAL_2 BBA Resistor Tune Step 2 8 4 read-write BBA_RES_TUNE_VAL_3 BBA Resistor Tune Step 3 12 4 read-write BBA_RES_TUNE_VAL_4 BBA Resistor Tune Step 4 16 4 read-write BBA_RES_TUNE_VAL_5 BBA Resistor Tune Step 5 20 4 read-write BBA_RES_TUNE_VAL_6 BBA Resistor Tune Step 6 24 4 read-write BBA_RES_TUNE_VAL_7 BBA Resistor Tune Step 7 28 4 read-write BBA_RES_TUNE_VAL_10_8 BBA Resistor Tune Values 10..8 0x60 32 read-write 0 0xFFFFFFFF BBA_RES_TUNE_VAL_8 BBA Resistor Tune Step 8 0 4 read-write BBA_RES_TUNE_VAL_9 BBA Resistor Tune Step 9 4 4 read-write BBA_RES_TUNE_VAL_10 BBA Resistor Tune Step 10 8 4 read-write LNA_GAIN_LIN_VAL_2_0 LNA Linear Gain Values 2..0 0x64 32 read-write 0 0xFFFFFFFF LNA_GAIN_LIN_VAL_0 LNA Linear Gain Step 0 0 10 read-write LNA_GAIN_LIN_VAL_1 LNA Linear Gain Step 1 10 10 read-write LNA_GAIN_LIN_VAL_2 LNA Linear Gain Step 2 20 10 read-write LNA_GAIN_LIN_VAL_5_3 LNA Linear Gain Values 5..3 0x68 32 read-write 0 0xFFFFFFFF LNA_GAIN_LIN_VAL_3 LNA Linear Gain Step 3 0 10 read-write LNA_GAIN_LIN_VAL_4 LNA Linear Gain Step 4 10 10 read-write LNA_GAIN_LIN_VAL_5 LNA Linear Gain Step 5 20 10 read-write LNA_GAIN_LIN_VAL_8_6 LNA Linear Gain Values 8..6 0x6C 32 read-write 0 0xFFFFFFFF LNA_GAIN_LIN_VAL_6 LNA Linear Gain Step 6 0 10 read-write LNA_GAIN_LIN_VAL_7 LNA Linear Gain Step 7 10 10 read-write LNA_GAIN_LIN_VAL_8 LNA Linear Gain Step 8 20 10 read-write LNA_GAIN_LIN_VAL_9 LNA Linear Gain Values 9 0x70 32 read-write 0 0xFFFFFFFF LNA_GAIN_LIN_VAL_9 LNA Linear Gain Step 9 0 10 read-write BBA_RES_TUNE_LIN_VAL_3_0 BBA Resistor Tune Values 3..0 0x74 32 read-write 0 0xFFFFFFFF BBA_RES_TUNE_LIN_VAL_0 BBA Resistor Tune Linear Gain Step 0 0 8 read-write BBA_RES_TUNE_LIN_VAL_1 BBA Resistor Tune Linear Gain Step 1 8 8 read-write BBA_RES_TUNE_LIN_VAL_2 BBA Resistor Tune Linear Gain Step 2 16 8 read-write BBA_RES_TUNE_LIN_VAL_3 BBA Resistor Tune Linear Gain Step 3 24 8 read-write BBA_RES_TUNE_LIN_VAL_7_4 BBA Resistor Tune Values 7..4 0x78 32 read-write 0 0xFFFFFFFF BBA_RES_TUNE_LIN_VAL_4 BBA Resistor Tune Linear Gain Step 4 0 8 read-write BBA_RES_TUNE_LIN_VAL_5 BBA Resistor Tune Linear Gain Step 5 8 8 read-write BBA_RES_TUNE_LIN_VAL_6 BBA Resistor Tune Linear Gain Step 6 16 8 read-write BBA_RES_TUNE_LIN_VAL_7 BBA Resistor Tune Linear Gain Step 7 24 8 read-write BBA_RES_TUNE_LIN_VAL_10_8 BBA Resistor Tune Values 10..8 0x7C 32 read-write 0 0xFFFFFFFF BBA_RES_TUNE_LIN_VAL_8 BBA Resistor Tune Linear Gain Step 8 0 10 read-write BBA_RES_TUNE_LIN_VAL_9 BBA Resistor Tune Linear Gain Step 9 10 10 read-write BBA_RES_TUNE_LIN_VAL_10 BBA Resistor Tune Linear Gain Step 10 20 10 read-write AGC_GAIN_TBL_03_00 AGC Gain Tables Step 03..00 0x80 32 read-write 0 0xFFFFFFFF BBA_GAIN_00 BBA Gain 00 0 4 read-write LNA_GAIN_00 LNA Gain 00 4 4 read-write BBA_GAIN_01 BBA Gain 01 8 4 read-write LNA_GAIN_01 LNA Gain 01 12 4 read-write BBA_GAIN_02 BBA Gain 02 16 4 read-write LNA_GAIN_02 LNA Gain 02 20 4 read-write BBA_GAIN_03 BBA Gain 03 24 4 read-write LNA_GAIN_03 LNA Gain 03 28 4 read-write AGC_GAIN_TBL_07_04 AGC Gain Tables Step 07..04 0x84 32 read-write 0 0xFFFFFFFF BBA_GAIN_04 BBA Gain 04 0 4 read-write LNA_GAIN_04 LNA Gain 04 4 4 read-write BBA_GAIN_05 BBA Gain 05 8 4 read-write LNA_GAIN_05 LNA Gain 05 12 4 read-write BBA_GAIN_06 BBA Gain 06 16 4 read-write LNA_GAIN_06 LNA Gain 06 20 4 read-write BBA_GAIN_07 BBA Gain 07 24 4 read-write LNA_GAIN_07 LNA Gain 07 28 4 read-write AGC_GAIN_TBL_11_08 AGC Gain Tables Step 11..08 0x88 32 read-write 0 0xFFFFFFFF BBA_GAIN_08 BBA Gain 08 0 4 read-write LNA_GAIN_08 LNA Gain 08 4 4 read-write BBA_GAIN_09 BBA Gain 09 8 4 read-write LNA_GAIN_09 LNA Gain 09 12 4 read-write BBA_GAIN_10 BBA Gain 10 16 4 read-write LNA_GAIN_10 LNA Gain 10 20 4 read-write BBA_GAIN_11 BBA Gain 11 24 4 read-write LNA_GAIN_11 LNA Gain 11 28 4 read-write AGC_GAIN_TBL_15_12 AGC Gain Tables Step 15..12 0x8C 32 read-write 0 0xFFFFFFFF BBA_GAIN_12 BBA Gain 12 0 4 read-write LNA_GAIN_12 LNA Gain 12 4 4 read-write BBA_GAIN_13 BBA Gain 13 8 4 read-write LNA_GAIN_13 LNA Gain 13 12 4 read-write BBA_GAIN_14 BBA Gain 14 16 4 read-write LNA_GAIN_14 LNA Gain 14 20 4 read-write BBA_GAIN_15 BBA Gain 15 24 4 read-write LNA_GAIN_15 LNA Gain 15 28 4 read-write AGC_GAIN_TBL_19_16 AGC Gain Tables Step 19..16 0x90 32 read-write 0 0xFFFFFFFF BBA_GAIN_16 BBA Gain 16 0 4 read-write LNA_GAIN_16 LNA Gain 16 4 4 read-write BBA_GAIN_17 BBA Gain 17 8 4 read-write LNA_GAIN_17 LNA Gain 17 12 4 read-write BBA_GAIN_18 BBA Gain 18 16 4 read-write LNA_GAIN_18 LNA Gain 18 20 4 read-write BBA_GAIN_19 BBA Gain 193 24 4 read-write LNA_GAIN_19 LNA Gain 19 28 4 read-write AGC_GAIN_TBL_23_20 AGC Gain Tables Step 23..20 0x94 32 read-write 0 0xFFFFFFFF BBA_GAIN_20 BBA Gain 20 0 4 read-write LNA_GAIN_20 LNA Gain 20 4 4 read-write BBA_GAIN_21 BBA Gain 21 8 4 read-write LNA_GAIN_21 LNA Gain 21 12 4 read-write BBA_GAIN_22 BBA Gain 22 16 4 read-write LNA_GAIN_22 LNA Gain 22 20 4 read-write BBA_GAIN_23 BBA Gain 23 24 4 read-write LNA_GAIN_23 LNA Gain 23 28 4 read-write AGC_GAIN_TBL_26_24 AGC Gain Tables Step 26..24 0x98 32 read-write 0 0xFFFFFFFF BBA_GAIN_24 BBA Gain 24 0 4 read-write LNA_GAIN_24 LNA Gain 24 4 4 read-write BBA_GAIN_25 BBA Gain 25 8 4 read-write LNA_GAIN_25 LNA Gain 25 12 4 read-write BBA_GAIN_26 BBA Gain 26 16 4 read-write LNA_GAIN_26 LNA Gain 26 20 4 read-write DCOC_OFFSET_0 DCOC Offset 0xA0 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_1 DCOC Offset 0xA4 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_2 DCOC Offset 0xA8 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_3 DCOC Offset 0xAC 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_4 DCOC Offset 0xB0 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_5 DCOC Offset 0xB4 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_6 DCOC Offset 0xB8 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_7 DCOC Offset 0xBC 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_8 DCOC Offset 0xC0 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_9 DCOC Offset 0xC4 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_10 DCOC Offset 0xC8 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_11 DCOC Offset 0xCC 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_12 DCOC Offset 0xD0 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_13 DCOC Offset 0xD4 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_14 DCOC Offset 0xD8 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_15 DCOC Offset 0xDC 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_16 DCOC Offset 0xE0 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_17 DCOC Offset 0xE4 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_18 DCOC Offset 0xE8 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_19 DCOC Offset 0xEC 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_20 DCOC Offset 0xF0 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_21 DCOC Offset 0xF4 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_22 DCOC Offset 0xF8 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_23 DCOC Offset 0xFC 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_24 DCOC Offset 0x100 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_25 DCOC Offset 0x104 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_26 DCOC Offset 0x108 32 read-write 0 0xFFFFFFFF DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_BBA_STEP DCOC BBA DAC Step 0x10C 32 read-write 0 0xFFFFFFFF BBA_DCOC_STEP_RECIP DCOC BBA Reciprocal of Step Size 0 13 read-write BBA_DCOC_STEP DCOC BBA Step Size 16 9 read-write DCOC_TZA_STEP_0 DCOC TZA DAC Step 0 0x110 32 read-write 0 0xFFFFFFFF DCOC_TZA_STEP_RCP_0 DCOC_TZA_STEP_RCP_0 0 13 read-write DCOC_TZA_STEP_GAIN_0 DCOC_TZA_STEP_GAIN_0 16 12 read-write DCOC_TZA_STEP_1 DCOC TZA DAC Step 1 0x114 32 read-write 0 0xFFFFFFFF DCOC_TZA_STEP_RCP_1 DCOC_TZA_STEP_RCP_1 0 13 read-write DCOC_TZA_STEP_GAIN_1 DCOC_TZA_STEP_GAIN_1 16 12 read-write DCOC_TZA_STEP_2 DCOC TZA DAC Step 2 0x118 32 read-write 0 0xFFFFFFFF DCOC_TZA_STEP_RCP_2 DCOC_TZA_STEP_RCP_2 0 13 read-write DCOC_TZA_STEP_GAIN_2 DCOC_TZA_STEP_GAIN_2 16 12 read-write DCOC_TZA_STEP_3 DCOC TZA DAC Step 3 0x11C 32 read-write 0 0xFFFFFFFF DCOC_TZA_STEP_RCP_3 DCOC_TZA_STEP_RCP_3 0 13 read-write DCOC_TZA_STEP_GAIN_3 DCOC_TZA_STEP_GAIN_3 16 12 read-write DCOC_TZA_STEP_4 DCOC TZA DAC Step 4 0x120 32 read-write 0 0xFFFFFFFF DCOC_TZA_STEP_RCP_4 DCOC_TZA_STEP_RCP_4 0 13 read-write DCOC_TZA_STEP_GAIN_4 DCOC_TZA_STEP_GAIN_4 16 12 read-write DCOC_TZA_STEP_5 DCOC TZA DAC Step 5 0x124 32 read-write 0 0xFFFFFFFF DCOC_TZA_STEP_RCP_5 DCOC_TZA_STEP_RCP_5 0 13 read-write DCOC_TZA_STEP_GAIN_5 DCOC_TZA_STEP_GAIN_5 16 12 read-write DCOC_TZA_STEP_6 DCOC TZA DAC Step 6 0x128 32 read-write 0 0xFFFFFFFF DCOC_TZA_STEP_RCP_6 DCOC_TZA_STEP_RCP_6 0 13 read-write DCOC_TZA_STEP_GAIN_6 DCOC_TZA_STEP_GAIN_6 16 12 read-write DCOC_TZA_STEP_7 DCOC TZA DAC Step 7 0x12C 32 read-write 0 0xFFFFFFFF DCOC_TZA_STEP_RCP_7 DCOC_TZA_STEP_RCP_7 0 13 read-write DCOC_TZA_STEP_GAIN_7 DCOC_TZA_STEP_GAIN_7 16 13 read-write DCOC_TZA_STEP_8 DCOC TZA DAC Step 5 0x130 32 read-write 0 0xFFFFFFFF DCOC_TZA_STEP_RCP_8 DCOC_TZA_STEP_RCP_8 0 13 read-write DCOC_TZA_STEP_GAIN_8 DCOC_TZA_STEP_GAIN_8 16 13 read-write DCOC_TZA_STEP_9 DCOC TZA DAC Step 9 0x134 32 read-write 0 0xFFFFFFFF DCOC_TZA_STEP_RCP_9 DCOC_TZA_STEP_RCP_9 0 13 read-write DCOC_TZA_STEP_GAIN_9 DCOC_TZA_STEP_GAIN_9 16 14 read-write DCOC_TZA_STEP_10 DCOC TZA DAC Step 10 0x138 32 read-write 0 0xFFFFFFFF DCOC_TZA_STEP_RCP_10 DCOC_TZA_STEP_RCP_10 0 13 read-write DCOC_TZA_STEP_GAIN_10 DCOC_TZA_STEP_GAIN_10 16 14 read-write DCOC_CAL_ALPHA DCOC Calibration Alpha 0x168 32 read-only 0 0xFFFFFFFF DCOC_CAL_ALPHA_I DCOC Calibration I-channel ALPHA constant 0 11 read-only DCOC_CAL_ALPHA_Q DCOC_CAL_ALPHA_Q 16 11 read-only DCOC_CAL_BETA_Q DCOC Calibration Beta Q 0x16C 32 read-only 0 0xFFFFFFFF DCOC_CAL_BETA_Q DCOC_CAL_BETA_Q 0 17 read-only DCOC_CAL_BETA_I DCOC Calibration Beta I 0x170 32 read-only 0 0xFFFFFFFF DCOC_CAL_BETA_I DCOC_CAL_BETA_I 0 17 read-only DCOC_CAL_GAMMA DCOC Calibration Gamma 0x174 32 read-only 0 0xFFFFFFFF DCOC_CAL_GAMMA_I DCOC_CAL_GAMMA_I 0 16 read-only DCOC_CAL_GAMMA_Q DCOC_CAL_GAMMA_Q 16 16 read-only DCOC_CAL_IIR DCOC Calibration IIR 0x178 32 read-write 0 0xFFFFFFFF DCOC_CAL_IIR1A_IDX DCOC Calibration IIR 1A Index 0 2 read-write 0 1/1 #00 1 1/4 #01 2 1/8 #10 3 1/16 #11 DCOC_CAL_IIR2A_IDX DCOC Calibration IIR 2A Index 2 2 read-write 0 1/1 #00 1 1/4 #01 2 1/8 #10 3 1/16 #11 DCOC_CAL_IIR3A_IDX DCOC Calibration IIR 3A Index 4 2 read-write 0 1/4 #00 1 1/8 #01 2 1/16 #10 3 1/32 #11 DCOC_CAL1 DCOC Calibration Result 0x180 32 read-only 0 0xFFFFFFFF DCOC_CAL_RES_I DCOC Calibration Result - I Channel 0 12 read-only DCOC_CAL_RES_Q DCOC Calibration Result - Q Channel 16 12 read-only DCOC_CAL2 DCOC Calibration Result 0x184 32 read-only 0 0xFFFFFFFF DCOC_CAL_RES_I DCOC Calibration Result - I Channel 0 12 read-only DCOC_CAL_RES_Q DCOC Calibration Result - Q Channel 16 12 read-only DCOC_CAL3 DCOC Calibration Result 0x188 32 read-only 0 0xFFFFFFFF DCOC_CAL_RES_I DCOC Calibration Result - I Channel 0 12 read-only DCOC_CAL_RES_Q DCOC Calibration Result - Q Channel 16 12 read-only CCA_ED_LQI_CTRL_0 RX_DIG CCA ED LQI Control Register 0 0x190 32 read-write 0 0xFFFFFFFF LQI_CORR_THRESH LQI Correlation Threshold 0 8 read-write CORR_CNTR_THRESH Correlation Count Threshold 8 8 read-write LQI_CNTR LQI Counter 16 8 read-write SNR_ADJ SNR calculation adjustment 24 6 read-write CCA_ED_LQI_CTRL_1 RX_DIG CCA ED LQI Control Register 1 0x194 32 read-write 0 0xFFFFFFFF RSSI_NOISE_AVG_DELAY RSSI Noise Averaging Delay 0 6 read-write RSSI_NOISE_AVG_FACTOR RSSI Noise Averaging Factor 6 3 read-write 0 1 #000 1 64 #001 2 70 #010 3 128 #011 4 139 #100 5 256 #101 6 277 #110 7 512 #111 LQI_RSSI_WEIGHT LQI RSSI Weight 9 3 read-write 0 2.0 #000 1 2.125 #001 2 2.25 #010 3 2.375 #011 4 2.5 #100 5 2.625 #101 6 2.75 #110 7 2.875 #111 LQI_RSSI_SENS LQI RSSI Sensitivity 12 4 read-write SNR_LQI_DIS SNR LQI Disable 16 1 read-write 0 Normal operation. #0 1 The RX_DIG CCA/ED/LQI block ignores the AA match input which starts an LQI measurement. #1 SEL_SNR_MODE Select SNR Mode 17 1 read-write 0 SNR estimate #0 1 Mapped correlation magnitude #1 MEAS_TRANS_TO_IDLE Measurement Transition to IDLE 18 1 read-write 0 Module transitions to RSSI state #0 1 Module transitions to IDLE state #1 CCA1_ED_EN_DIS CCA1_ED_EN Disable 19 1 read-write 0 Normal operation #0 1 CCA1_ED_EN input is disabled #1 MAN_MEAS_COMPLETE Manual measurement complete 20 1 read-write 0 Normal operation #0 1 Manually asserts the measurement complete signal for the RX_DIG CCA/ED/LQI blocks. Intended to be used only for debug. #1 MAN_AA_MATCH Manual AA Match 21 1 read-write 0 Normal operation #0 1 Manually asserts the AA match signal for the RX_DIG CCA/ED/LQI and AGC blocks. Intended to be used only for debug. #1 SNR_LQI_WEIGHT SNR LQI Weight 24 4 read-write 0 0.0 #0000 1 1.0 #0001 2 1.125 #0010 3 1.25 #0011 4 1.375 #0100 5 1.5 #0101 6 1.625 #0110 7 1.75 #0111 8 1.875 #1000 9 2.0 #1001 10 2.125 #1010 11 2.25 #1011 12 2.375 #1100 13 2.5 #1101 14 2.625 #1110 15 2.75 #1111 LQI_BIAS LQI Bias. 28 4 read-write CCA_ED_LQI_STAT_0 RX_DIG CCA ED LQI Status Register 0 0x198 32 read-only 0 0xFFFFFFFF LQI_OUT LQI output 0 8 read-only ED_OUT ED output 8 8 read-only SNR_OUT SNR output 16 8 read-only CCA1_STATE CCA1 State 24 1 read-only MEAS_COMPLETE Measurement Complete 25 1 read-only RX_CHF_COEF_0 Receive Channel Filter Coefficient 0 0x1A0 32 read-write 0 0xFFFFFFFF RX_CH_FILT_H0 RX Channel Filter Coefficient 0 0 6 read-write RX_CHF_COEF_1 Receive Channel Filter Coefficient 1 0x1A4 32 read-write 0 0xFFFFFFFF RX_CH_FILT_H1 RX Channel Filter Coefficient 1 0 6 read-write RX_CHF_COEF_2 Receive Channel Filter Coefficient 2 0x1A8 32 read-write 0 0xFFFFFFFF RX_CH_FILT_H2 RX Channel Filter Coefficient 2 0 7 read-write RX_CHF_COEF_3 Receive Channel Filter Coefficient 3 0x1AC 32 read-write 0 0xFFFFFFFF RX_CH_FILT_H3 RX Channel Filter Coefficient 3 0 7 read-write RX_CHF_COEF_4 Receive Channel Filter Coefficient 4 0x1B0 32 read-write 0 0xFFFFFFFF RX_CH_FILT_H4 RX Channel Filter Coefficient 4 0 7 read-write RX_CHF_COEF_5 Receive Channel Filter Coefficient 5 0x1B4 32 read-write 0 0xFFFFFFFF RX_CH_FILT_H5 RX Channel Filter Coefficient 5 0 7 read-write RX_CHF_COEF_6 Receive Channel Filter Coefficient 6 0x1B8 32 read-write 0 0xFFFFFFFF RX_CH_FILT_H6 RX Channel Filter Coefficient 6 0 8 read-write RX_CHF_COEF_7 Receive Channel Filter Coefficient 7 0x1BC 32 read-write 0 0xFFFFFFFF RX_CH_FILT_H7 RX Channel Filter Coefficient 7 0 8 read-write RX_CHF_COEF_8 Receive Channel Filter Coefficient 8 0x1C0 32 read-write 0 0xFFFFFFFF RX_CH_FILT_H8 RX Channel Filter Coefficient 8 0 9 read-write RX_CHF_COEF_9 Receive Channel Filter Coefficient 9 0x1C4 32 read-write 0 0xFFFFFFFF RX_CH_FILT_H9 RX Channel Filter Coefficient 9 0 9 read-write RX_CHF_COEF_10 Receive Channel Filter Coefficient 10 0x1C8 32 read-write 0 0xFFFFFFFF RX_CH_FILT_H10 RX Channel Filter Coefficient 10 0 10 read-write RX_CHF_COEF_11 Receive Channel Filter Coefficient 11 0x1CC 32 read-write 0 0xFFFFFFFF RX_CH_FILT_H11 RX Channel Filter Coefficient 11 0 10 read-write AGC_MAN_AGC_IDX AGC Manual AGC Index 0x1D0 32 read-write 0 0xFFFFFFFF AGC_MAN_IDX AGC Manual Index 16 5 read-write AGC_MAN_IDX_EN AGC Manual Index Enable 24 1 read-write AGC_DCOC_START_PT AGC DCOC Start Point 25 1 read-write DC_RESID_CTRL DC Residual Control 0x1D4 32 read-write 0 0xFFFFFFFF DC_RESID_NWIN DC Residual NWIN 0 7 read-write DC_RESID_ITER_FREEZE DC Residual Iteration Freeze 8 4 read-write DC_RESID_ALPHA DC Residual Alpha 12 3 read-write DC_RESID_DLY DC Residual Delay 16 3 read-write DC_RESID_EXT_DC_EN DC Residual External DC Enable 20 1 read-write DC_RESID_MIN_AGC_IDX DC Residual Minimum AGC Table Index 24 5 write-only DC_RESID_EST DC Residual Estimate 0x1D8 32 read-only 0 0xFFFFFFFF DC_RESID_OFFSET_I DC Residual Offset I 0 13 read-only DC_RESID_OFFSET_Q DC Residual Offset Q 16 13 read-only RX_RCCAL_CTRL0 RX RC Calibration Control0 0x1DC 32 read-write 0 0xFFFFFFFF BBA_RCCAL_OFFSET BBA RC Calibration value offset 0 4 read-write BBA_RCCAL_MANUAL BBA RC Calibration manual value 4 5 read-write BBA_RCCAL_DIS BBA RC Calibration Disable 9 1 read-write 0 BBA RC Calibration is enabled #0 1 BBA RC Calibration is disabled #1 RCCAL_SMP_DLY RC Calibration Sample Delay 12 2 read-write 00 The comp_out signal is sampled 0 clk cycle after sample signal is deasserted #00 01 The comp_out signal is sampled 1 clk cycle after sample signal is deasserted #01 10 The comp_out signal is sampled 2 clk cycle after sample signal is deasserted #10 11 The comp_out signal is sampled 3 clk cycle after sample signal is deasserted #11 RCCAL_COMP_INV RC Calibration comp_out Invert 15 1 read-write 0 The comp_out signal polarity is NOT inverted #0 1 The comp_out signal polarity is inverted #1 TZA_RCCAL_OFFSET TZA RC Calibration value offset 16 4 read-write TZA_RCCAL_MANUAL TZA RC Calibration manual value 20 5 read-write TZA_RCCAL_DIS TZA RC Calibration Disable 25 1 read-write 0 TZA RC Calibration is enabled #0 1 TZA RC Calibration is disabled #1 RX_RCCAL_CTRL1 RX RC Calibration Control1 0x1E0 32 read-write 0 0xFFFFFFFF ADC_RCCAL_OFFSET ADC RC Calibration value offset 0 4 read-write ADC_RCCAL_MANUAL ADC RC Calibration manual value 4 5 read-write ADC_RCCAL_DIS ADC RC Calibration Disable 9 1 read-write 0 ADC RC Calibration is enabled #0 1 ADC RC Calibration is disabled #1 BBA2_RCCAL_OFFSET BBA2 RC Calibration value offset 16 4 read-write BBA2_RCCAL_MANUAL BBA2 RC Calibration manual value 20 5 read-write BBA2_RCCAL_DIS BBA2 RC Calibration Disable 25 1 read-write 0 BBA2 RC Calibration is enabled #0 1 BBA2 RC Calibration is disabled #1 RX_RCCAL_STAT RX RC Calibration Status 0x1E4 32 read-only 0x2104210 0xFFFFFFFF RCCAL_CODE RC Calibration code 0 5 read-only ADC_RCCAL ADC RC Calibration 5 5 read-only BBA2_RCCAL BBA2 RC Calibration 10 5 read-only BBA_RCCAL BBA RC Calibration 16 5 read-only TZA_RCCAL TZA RC Calibration 21 5 read-only AUXPLL_FCAL_CTRL Aux PLL Frequency Calibration Control 0x1E8 32 read-write 0x400000 0xFFFFFFFF DAC_CAL_ADJUST_MANUAL Aux PLL Frequency DAC Calibration Adjust Manual value 0 7 read-write AUXPLL_DAC_CAL_ADJUST_DIS Aux PLL Frequency Calibration Disable 7 1 read-write 0 Calibration is enabled #0 1 Calibration is disabled #1 FCAL_RUN_CNT Aux PLL Frequency Calibration Run Count 8 1 read-write 0 Run count is 256 clock cycles #0 1 Run count is 512 clock cycles #1 FCAL_COMP_INV Aux PLL Frequency Calibration Comparison Invert 9 1 read-write 0 (Default) The comparison associated with the count is not inverted. #0 1 The comparison associated with the count is inverted #1 FCAL_SMP_DLY Aux PLL Frequency Calibration Sample Delay 10 2 read-write 00 The count signal is sampled 1 clk cycle after fcal_run signal is deasserted #00 01 The count signal is sampled 2 clk cycle after fcal_run signal is deasserted #01 10 The count signal is sampled 3 clk cycle after fcal_run signal is deasserted #10 11 The count signal is sampled 4 clk cycle after fcal_run signal is deasserted #11 DAC_CAL_ADJUST Aux PLL DAC Calibration Adjust value 16 7 read-only AUXPLL_FCAL_CNT6 Aux PLL Frequency Calibration Count 6 0x1EC 32 read-only 0 0xFFFFFFFF FCAL_COUNT_6 Aux PLL Frequency Calibration Count 6 0 10 read-only FCAL_BESTDIFF Aux PLL Frequency Calibration Best Difference 16 10 read-only AUXPLL_FCAL_CNT5_4 Aux PLL Frequency Calibration Count 5 and 4 0x1F0 32 read-only 0 0xFFFFFFFF FCAL_COUNT_4 Aux PLL Frequency Calibration Count 4 0 10 read-only FCAL_COUNT_5 Aux PLL Frequency Calibration Count 5 16 10 read-only AUXPLL_FCAL_CNT3_2 Aux PLL Frequency Calibration Count 3 and 2 0x1F4 32 read-only 0 0xFFFFFFFF FCAL_COUNT_2 Aux PLL Frequency Calibration Count 2 0 10 read-only FCAL_COUNT_3 Aux PLL Frequency Calibration Count 3 16 10 read-only AUXPLL_FCAL_CNT1_0 Aux PLL Frequency Calibration Count 1 and 0 0x1F8 32 read-only 0 0xFFFFFFFF FCAL_COUNT_0 Frequency Calibration Count 0 0 10 read-only FCAL_COUNT_1 Frequency Calibration Count 1 16 10 read-only RXDIG_DFT RXDIG DFT 0x1FC 32 read-write 0 0xFFFFFFFF DFT_TONE_FREQ DFT Tone Generator Frequency 0 3 read-write 0 1/64 of the ref osc frequency (500kHz for 32MHz ref osc) #000 1 1/128 of the ref osc frequency (250kHz for 32MHz ref osc) #001 2 1/256 of the ref osc frequency (125kHz for 32MHz ref osc) #010 3 1/512 of the ref osc frequency (62.5kHz for 32MHz ref osc) #011 4 1/1024 of the ref osc frequency (31.25kHz for 32MHz ref osc) #100 DFT_TONE_SCALE DFT Tone Generator Scale 3 1 read-write 0 The DFT tone generator uses 3/4 of the DC offset correction DAC range. #0 1 The DFT tone generator uses 1/2 of the DC offset correction DAC range. #1 DFT_TONE_TZA_EN DFT Tone Generator TZA Enable 4 1 read-write 0 The DCOC controls the TZA DC offset correction DACs #0 1 A tone is generated using the TZA DC offset correction DACs. #1 DFT_TONE_BBA_EN DFT Tone Generator BBA Enable 5 1 read-write 0 The DCOC controls the BBA DC offset correction DACs #0 1 A tone is generated using the BBA DC offset correction DACs. #1 TX_DIG_REGS XCVR_TX_DIG 0x4005C200 0 0x24 registers CTRL TX Digital Control 0 32 read-write 0x140 0xFFFFFFFF RADIO_DFT_MODE Radio DFT Modes 0 4 read-write 0000 Normal Radio Operation, DFT not engaged. #0000 0001 Carrier Frequency Only #0001 0010 Pattern Register GFSK #0010 0011 LFSR GFSK #0011 0100 Pattern Register FSK #0100 0101 LFSR FSK #0101 0110 Pattern Register O-QPSK #0110 0111 LFSR O-QPSK #0111 1000 LFSR 802.15.4 Symbols #1000 1001 PLL Modulation from RAM #1001 1010 PLL Coarse Tune BIST #1010 1011 PLL Frequency Synthesizer BIST #1011 1100 High Port DAC BIST #1100 1101 VCO Frequency Meter #1101 LFSR_LENGTH LFSR Length 4 3 read-write 000 LFSR 9, tap mask 100010000 #000 001 LFSR 10, tap mask 1001000000 #001 010 LFSR 11, tap mask 11101000000 #010 011 LFSR 13, tap mask 1101100000000 #011 100 LFSR 15, tap mask 111010000000000 #100 101 LFSR 17, tap mask 11110000000000000 #101 LFSR_EN LFSR Enable 7 1 read-write DFT_CLK_SEL DFT Clock Selection 8 3 read-write 000 62.5 kHz #000 001 125 kHz #001 010 250 kHz #010 011 500 kHz #011 100 1 MHz #100 101 2 MHz #101 110 4 MHz #110 111 RF OSC Clock #111 TX_DFT_EN DFT Modulation Enable 11 1 read-write SOC_TEST_SEL Radio Clock Selector for SoC RF Clock Tests 12 2 read-write 00 No Clock Selected #00 01 PLL Sigma Delta Clock, divided by 2 #01 10 Auxiliary PLL Clock, divided by 2 #10 11 RF Ref Osc clock, divided by 2 #11 TX_CAPTURE_POL Polarity of the Input Data for the Transmitter 16 1 read-write FREQ_WORD_ADJ Frequency Word Adjustment 22 10 read-write DATA_PADDING TX Data Padding 0x4 32 read-write 0x7FFF55AA 0xFFFFFFFF DATA_PADDING_PAT_0 Data Padding Pattern 0 0 8 read-write DATA_PADDING_PAT_1 Data Padding Pattern 1 8 8 read-write DFT_LFSR_OUT LFSR Output 16 15 read-only LRM LFSR Reset Mask 31 1 read-write GFSK_CTRL TX GFSK Modulator Control 0x8 32 read-write 0x3014000 0xFFFFFFFF GFSK_MULTIPLY_TABLE_MANUAL Manual GFSK Multiply Lookup Table Value 0 16 read-write GFSK_MI GFSK Modulation Index 16 2 read-write 00 0.32 #00 01 0.50 #01 10 0.70 #10 11 1.00 #11 GFSK_MLD Disable GFSK Multiply Lookup Table 20 1 read-write GFSK_FLD Disable GFSK Filter Lookup Table 21 1 read-write GFSK_MOD_INDEX_SCALING GFSK Modulation Index Scaling Factor 24 3 read-write 000 1 #000 001 1 + 1/32 #001 010 1 + 1/16 #010 011 1 + 1/8 #011 100 1 - 1/32 #100 101 1 - 1/16 #101 110 1 - 1/8 #110 TX_IMAGE_FILTER_OVRD_EN TX Image Filter Override Enable 28 1 read-write TX_IMAGE_FILTER_0_OVRD TX Image Filter 0 Override Control 29 1 read-write TX_IMAGE_FILTER_1_OVRD TX Image Filter 1 Override Control 30 1 read-write TX_IMAGE_FILTER_2_OVRD TX Image Filter 2 Override Control 31 1 read-write GFSK_COEFF2 TX GFSK Filter Coefficients 2 0xC 32 read-write 0xC0630401 0xFFFFFFFF GFSK_FILTER_COEFF_MANUAL2 GFSK Manual Filter Coefficients[63:32] 0 32 read-write GFSK_COEFF1 TX GFSK Filter Coefficients 1 0x10 32 read-write 0xBB29960D 0xFFFFFFFF GFSK_FILTER_COEFF_MANUAL1 GFSK Manual Filter Coefficient [31:0] 0 32 read-write FSK_SCALE TX FSK Modulation Levels 0x14 32 read-write 0x8001800 0xFFFFFFFF FSK_MODULATION_SCALE_0 FSK Modulation Scale for a data 0 0 13 read-write FSK_MODULATION_SCALE_1 FSK Modulation Scale for a data 1 16 13 read-write DFT_PATTERN TX DFT Modulation Pattern 0x18 32 read-write 0 0xFFFFFFFF DFT_MOD_PATTERN DFT Modulation Pattern 0 32 read-write RF_DFT_BIST_1 TX DFT Control 1 0x1C 32 read-write 0 0xFFFFFFFF CTUNE_BIST_GO Start the Coarse Tune BIST 0 1 read-write CTUNE_BIST_FINISHED Coarse Tune BIST has finished Tuning all Channels 1 1 read-only CTUNE_BIST_RESULT Coarse Tune BIST Result 2 1 read-only CTUNE_BIST_THRSHLD Maximum Difference Threshold for Coarse Tune BIST 4 4 read-write CTUNE_MAX_DIFF Maximum Frequency Count Difference found by the Coarse Tune BIST 8 8 read-only CTUNE_MAX_DIFF_CH Maximum Frequency Count Difference Radio Channel 16 7 read-only PA_AM_MOD_FREQ RF Power Amplifier Amplitude Modulation Frequency 24 3 read-write 000 4 MHz #000 001 2 MHz #001 010 1 MHz #010 011 500 kHz #011 100 250 kHz #100 101 125 kHz #101 110 62.5 kHz #110 PA_AM_MOD_ENTRIES RF Power Amplifier Amplitude Modulation Table Entries 28 3 read-write 001 2 entries #001 010 3 entries #010 011 4 entries #011 100 5 entries #100 101 6 entries #101 110 7 entries #110 111 8 entries #111 PA_AM_MOD_EN RF Power Amplifier Amplitude Modulation Enable 31 1 read-write RF_DFT_BIST_2 TX DFT Control 2 0x20 32 read-write 0 0xFFFFFFFF SYN_BIST_GO Start the PLL Frequency Synthesizer BIST 0 1 read-write SYN_BIST_FINISHED PLL Frequency Synthesizer BIST has finished trying to lock to Radio Channels 1 1 read-only SYN_BIST_RESULT PLL Frequency Synthesizer BIST Result 2 1 read-only SYN_BIST_ALL_CHANNELS PLL Frequency Synthesizer BIST All Channels 3 1 read-write FREQ_COUNT_THRESHOLD Frequency Meter Count Difference Threshold 4 8 read-write HPM_INL_BIST_GO Start the High Port Modulator DAC INL BIST 12 1 read-write HPM_INL_BIST_FINISHED High Port Modulator DAC INL BIST has finished measuring the INL of the HPM DAC 13 1 read-only HPM_INL_BIST_RESULT High Port Modulator DAC INL BIST Result 14 1 read-only HPM_DNL_BIST_GO Start the High Port Modulator DAC DNL BIST 16 1 read-write HPM_DNL_BIST_FINISHED High Port Modulator DAC DNL BIST has finished measuring the DNL of the HPM DAC 17 1 read-only HPM_DNL_BIST_RESULT High Port Modulator DAC DNL BIST Result 18 1 read-only DFT_MAX_RAM_SIZE Maximum RAM Address to use as Modulation 20 9 read-write PLL_DIG_REGS XCVR_PLL_DIG 0x4005C224 0 0x58 registers HPM_BUMP PLL HPM Analog Bump Control 0 32 read-write 0x1010 0xFFFFFFFF HPM_VCM_TX rfctrl_tx_dac_bump_vcm[2:0] during Transmission 0 3 read-write 000 432 mV #000 001 328 mV #001 010 456 mV #010 011 473 mV #011 100 488 mV #100 101 408 mV #101 110 392 mV #110 111 376 mV #111 HPM_VCM_CAL rfctrl_tx_dac_bump_vcm[2:0] during Calibration 4 3 read-write 000 432 mV #000 001 328 mV #001 010 456 mV #010 011 473 mV #011 100 488 mV #100 101 408 mV #101 110 392 mV #110 111 376 mV #111 HPM_FDB_RES_TX rfctrl_tx_dac_bump_fdb_res[1:0] during Transmission 8 2 read-write 00 29 kohms #00 01 58 kohms(gain of 2) #01 10 13 kohms #10 11 23.7 kohms #11 HPM_FDB_RES_CAL rfctrl_tx_dac_bump_fdb_res[1:0] during Calibration 12 2 read-write 00 29 kohms #00 01 58 kohms(gain of 2) #01 10 13 kohms #10 11 23.7 kohms #11 MOD_CTRL PLL Modulation Control 0x4 32 read-write 0 0xFFFFFFFF MODULATION_WORD_MANUAL Manual Modulation Word 0 13 read-write MOD_DISABLE Disable Modulation Word 15 1 read-write HPM_MOD_MANUAL Manual HPM Modulation 16 8 read-write HPM_MOD_DISABLE Disable HPM Modulation 27 1 read-write HPM_SDM_OUT_MANUAL Manual HPM SDM out 28 2 read-write HPM_SDM_OUT_DISABLE Disable HPM SDM out 31 1 read-write CHAN_MAP PLL Channel Mapping 0x8 32 read-write 0x200 0xFFFFFFFF CHANNEL_NUM Protocol specific Channel Number for PLL Frequency Mapping 0 7 read-write BOC BLE Channel Number Override 8 1 read-write 0 BLE channel number comes from the BLE Link Layer #0 1 BLE channel number comes from the CHANNEL_NUM register (BLE protocols 0 and 2) #1 BMR BLE MBAN Channel Remap 9 1 read-write 0 BLE channel 39 is mapped to BLE channel 39, 2.480 GHz #0 1 BLE channel 39 is mapped to MBAN channel 39, 2.399 GHz #1 ZOC 802.15.4 Channel Number Override 10 1 read-write 0 802.15.4 channel number comes from the 802.15.4 Link Layer. #0 1 802.15.4 channel number comes from the CHANNEL_NUM register (802.15.4 protocols 4 and 5) #1 LOCK_DETECT PLL Lock Detect Control 0xC 32 read-write 0x606800 0xFFFFFFFF CT_FAIL Real time status of Coarse Tune Fail signal 0 1 read-only CTFF CTUNE Failure Flag, held until cleared 1 1 read-write CS_FAIL Real time status of Cycle Slip circuit 2 1 read-only CSFF Cycle Slip Failure Flag, held until cleared 3 1 read-write FT_FAIL Real time status of Frequency Target Failure 4 1 read-only FTFF Frequency Target Failure Flag 5 1 read-write TAFF TSM Abort Failure Flag 7 1 read-write CTUNE_LDF_LEV CTUNE Lock Detect Fail Level 8 4 read-write FTF_RX_THRSH RX Frequency Target Fail Threshold 12 6 read-write FTW_RX RX Frequency Target Window time select 19 1 read-write 0 4 us #0 1 8 us #1 FTF_TX_THRSH TX Frequency Target Fail Threshold 20 6 read-write FTW_TX TX Frequency Target Window time select 27 1 read-write 0 4 us #0 1 8 us #1 FREQ_COUNT_GO Start the Frequency Meter 28 1 read-write FREQ_COUNT_FINISHED Frequency Meter has finished the Count Time 29 1 read-only FREQ_COUNT_TIME Frequency Meter Count Time 30 2 read-write 00 10 us #00 01 25 us #01 10 50 us #10 11 100 us #11 HPM_CTRL PLL High Port Modulator Control 0x10 32 read-write 0x90840000 0xFFFFFFFF HPM_SDM_IN_MANUAL Manual High Port SDM Fractional value 0 10 read-write HPFF HPM SDM Invalid Flag 13 1 read-write HPM_SDM_OUT_INVERT Invert HPM SDM Output 14 1 read-write HPM_SDM_IN_DISABLE Disable HPM SDM Input 15 1 read-write HPM_LFSR_SIZE HPM LFSR Length 16 3 read-write 000 LFSR 9, tap mask 100010000 #000 001 LFSR 10, tap mask 1001000000 #001 010 LFSR 11, tap mask 11101000000 #010 011 LFSR 13, tap mask 1101100000000 #011 100 LFSR 15, tap mask 111010000000000 #100 101 LFSR 17, tap mask 11110000000000000 #101 HPM_DTH_SCL HPM Dither Scale 20 1 read-write HPM_DTH_EN Dither Enable for HPM LFSR 23 1 read-write HPM_INTEGER_SCALE High Port Modulation Integer Scale 24 2 read-write 00 No Scaling #00 01 Multiply by 2 #01 10 Divide by 2 #10 HPM_INTEGER_INVERT Invert High Port Modulation Integer 27 1 read-write HPM_CAL_INVERT Invert High Port Modulator Calibration 28 1 read-write HPM_MOD_IN_INVERT Invert High Port Modulation 31 1 read-write HPMCAL_CTRL PLL High Port Calibration Control 0x14 32 read-write 0x40000221 0xFFFFFFFF HPM_CAL_FACTOR High Port Modulation Calibration Factor 0 13 read-only HPM_CAL_NOT_BUMPED HPM_CAL_NOT_BUMPED 13 1 read-write HPM_CAL_COUNT_SCALE HPM_CAL_COUNT_SCALE 14 1 read-write HP_CAL_DISABLE Disable HPM Manual Calibration 15 1 read-write HPM_CAL_FACTOR_MANUAL Manual HPM Calibration Factor 16 13 read-write HPM_CAL_ARRAY_SIZE High Port Modulation Calibration Array Size 30 1 read-write 0 128 #0 1 256 #1 HPM_CAL_TIME High Port Modulation Calibration Time 31 1 read-write 0 25 us #0 1 50 us #1 HPM_CAL1 PLL High Port Calibration Result 1 0x18 32 read-write 0x44300000 0xFFFFFFFF HPM_COUNT_1 High Port Modulation Counter Value 1 0 19 read-only CS_WT Cycle Slip Wait Time 20 3 read-write 000 128 us #000 001 256 us #001 010 384 us #010 011 512 us #011 100 640 us #100 101 768 us #101 110 896 us #110 111 1024 us #111 CS_FW Cycle Slip Flag Window 24 3 read-write 000 8 us #000 001 16 us #001 010 24 us #010 011 32 us #011 100 64 us #100 101 96 us #101 110 128 us #110 111 256 us #111 CS_FCNT Cycle Slip Flag Count 28 4 read-write HPM_CAL2 PLL High Port Calibration Result 2 0x1C 32 read-write 0x2100000 0xFFFFFFFF HPM_COUNT_2 High Port Modulation Counter Value 2 0 19 read-only CS_RC Cycle Slip Recycle 20 1 read-write CS_FT Cycle Slip Flag Timeout 24 5 read-write HPM_SDM_RES PLL High Port Sigma Delta Results 0x20 32 read-write 0x1000000 0xFFFFFFFF HPM_NUM_SELECTED High Port Modulator SDM Numerator 0 10 read-only HPM_DENOM High Port Modulator SDM Denominator 16 10 read-write HPM_COUNT_ADJUST HPM_COUNT_ADJUST 28 4 read-write LPM_CTRL PLL Low Port Modulator Control 0x24 32 read-write 0x8080000 0xFFFFFFFF PLL_LD_MANUAL Manual PLL Loop Divider value 0 6 read-write PLL_LD_DISABLE Disable PLL Loop Divider 11 1 read-write LPFF LPM SDM Invalid Flag 13 1 read-write LPM_SDM_INV Invert LPM SDM 14 1 read-write LPM_DISABLE Disable LPM SDM 15 1 read-write LPM_DTH_SCL LPM Dither Scale 16 4 read-write 0101 -128 to 96 #0101 0110 -256 to 192 #0110 0111 -512 to 384 #0111 1000 -1024 to 768 #1000 1001 -2048 to 1536 #1001 1010 -4096 to 3072 #1010 1011 -8192 to 6144 #1011 LPM_D_CTRL LPM Dither Control in Override Mode 22 1 read-write LPM_D_OVRD LPM Dither Override Mode Select 23 1 read-write LPM_SCALE LPM Scale Factor 24 4 read-write 0000 No Scaling #0000 0001 Multiply by 2 #0001 0010 Multiply by 4 #0010 0011 Multiply by 8 #0011 0100 Multiply by 16 #0100 0101 Multiply by 32 #0101 0110 Multiply by 64 #0110 0111 Multiply by 128 #0111 1000 Multiply by 256 #1000 1001 Multiply by 512 #1001 1010 Multiply by 1024 #1010 1011 Multiply by 2048 #1011 LPM_SDM_USE_NEG Use the Negedge of the Sigma Delta clock 31 1 read-write LPM_SDM_CTRL1 PLL Low Port Sigma Delta Control 1 0x28 32 read-write 0x260026 0xFFFFFFFF LPM_INTG_SELECTED Low Port Modulation Integer Value Selected 0 7 read-only HPM_ARRAY_BIAS Bias value for High Port DAC Array Midpoint 8 7 read-write LPM_INTG Manual Low Port Modulation Integer Value 16 7 read-write SDM_MAP_DISABLE Disable SDM Mapping 31 1 read-write LPM_SDM_CTRL2 PLL Low Port Sigma Delta Control 2 0x2C 32 read-write 0x2000000 0xFFFFFFFF LPM_NUM Low Port Modulation Numerator 0 28 read-write LPM_SDM_CTRL3 PLL Low Port Sigma Delta Control 3 0x30 32 read-write 0x4000000 0xFFFFFFFF LPM_DENOM Low Port Modulation Denominator 0 28 read-write LPM_SDM_RES1 PLL Low Port Sigma Delta Result 1 0x34 32 read-only 0xE200000 0xFFFFFFFF LPM_NUM_SELECTED Low Port Modulation Numerator Applied 0 28 read-only LPM_SDM_RES2 PLL Low Port Sigma Delta Result 2 0x38 32 read-only 0x4000000 0xFFFFFFFF LPM_DENOM_SELECTED Low Port Modulation Denominator Selected 0 28 read-only DELAY_MATCH PLL Delay Matching 0x3C 32 read-write 0x204 0xFFFFFFFF LPM_SDM_DELAY Low Port SDM Delay Matching 0 4 read-write HPM_SDM_DELAY High Port SDM Delay Matching 8 4 read-write HPM_INTEGER_DELAY High Port Integer Delay Matching 16 4 read-write CTUNE_CTRL PLL Coarse Tune Control 0x40 32 read-write 0 0xFFFFFFFF CTUNE_TARGET_MANUAL Manual Coarse Tune Target 0 12 read-write CTUNE_TARGET_DISABLE Disable Coarse Tune Target 15 1 read-write CTUNE_ADJUST Coarse Tune Count Adjustment 16 4 read-write CTUNE_MANUAL Manual Coarse Tune Setting 24 7 read-write CTUNE_DISABLE Coarse Tune Disable 31 1 read-write CTUNE_CNT6 PLL Coarse Tune Count 6 0x44 32 read-only 0 0xFFFFFFFF CTUNE_COUNT_6 CTUNE Count 6 0 13 read-only CTUNE_CNT5_4 PLL Coarse Tune Counts 5 and 4 0x48 32 read-only 0 0xFFFFFFFF CTUNE_COUNT_4 CTUNE Count 4 0 13 read-only CTUNE_COUNT_5 CTUNE Count 5 16 13 read-only CTUNE_CNT3_2 PLL Coarse Tune Counts 3 and 2 0x4C 32 read-only 0 0xFFFFFFFF CTUNE_COUNT_2 CTUNE Count 2 0 13 read-only CTUNE_COUNT_3 CTUNE Count 3 16 13 read-only CTUNE_CNT1_0 PLL Coarse Tune Counts 1 and 0 0x50 32 read-only 0 0xFFFFFFFF CTUNE_COUNT_0 CTUNE Count 0 0 13 read-only CTUNE_COUNT_1 CTUNE Count 1 16 13 read-only CTUNE_RES PLL Coarse Tune Results 0x54 32 read-only 0x9620040 0xFFFFFFFF CTUNE_SELECTED Coarse Tune Setting to VCO 0 7 read-only CTUNE_BEST_DIFF Coarse Tune Absolute Best Difference 8 8 read-only CTUNE_FREQ_SELECTED Coarse Tune Frequency Selected 16 12 read-only XCVR_CTRL_REGS XCVR_MISC 0x4005C280 0 0x3C registers XCVR_CTRL TRANSCEIVER CONTROL 0 32 read-write 0x101000 0xFFFFFFFF PROTOCOL Radio Protocol Selection 0 4 read-write 0000 BLE #0000 0001 BLE in MBAN #0001 0010 BLE overlap MBAN #0010 0011 ANT #0011 0100 Zigbee #0100 0101 802.15.4j #0101 0110 128 Channel FSK #0110 0111 128 Channel GFSK #0111 1000 Generic FSK #1000 1001 MSK #1001 TGT_PWR_SRC Target Power Source 4 3 read-write REF_CLK_FREQ Radio Reference Clock Frequency 8 2 read-write 00 32 MHz #00 01 26 MHz #01 SOC_RF_OSC_CLK_GATE_EN SOC_RF_OSC_CLK_GATE_EN 11 1 read-write DEMOD_SEL Demodulator Selector 12 2 read-write 00 No demodulator selected #00 01 Use Freescale Constant Envelope demodulator #01 10 Use Legacy 802.15.4 demodulator #10 RADIO0_IRQ_SEL RADIO0_IRQ_SEL 16 3 read-write 000 Assign Radio #0 Interrupt to BLE #000 001 Assign Radio #0 Interrupt to 802.15.4 #001 010 Assign Radio #0 Interrupt to ANT #010 011 Assign Radio #0 Interrupt to GENERIC_FSK #011 100 Radio #0 Interrupt unassigned #100 101 Radio #0 Interrupt unassigned #101 110 Radio #0 Interrupt unassigned #110 111 Radio #0 Interrupt unassigned #111 RADIO1_IRQ_SEL RADIO1_IRQ_SEL 20 3 read-write 000 Assign Radio #1 Interrupt to BLE #000 001 Assign Radio #1 Interrupt to 802.15.4 #001 010 Assign Radio #1 Interrupt to ANT #010 011 Assign Radio #1 Interrupt to GENERIC_FSK #011 100 Radio #1 Interrupt unassigned #100 101 Radio #1 Interrupt unassigned #101 110 Radio #1 Interrupt unassigned #110 111 Radio #1 Interrupt unassigned #111 XCVR_STATUS TRANSCEIVER STATUS 0x4 32 read-write 0 0xFFF0C000 TSM_COUNT TSM_COUNT 0 8 read-only PLL_SEQ_STATE PLL Sequence State 8 4 read-only 0 PLL OFF #0000 2 CTUNE #0010 3 CTUNE_SETTLE #0011 6 HPMCAL1 #0110 8 HPMCAL1_SETTLE #1000 10 HPMCAL2 #1010 12 HPMCAL2_SETTLE #1100 15 PLLREADY #1111 RX_MODE Receive Mode 12 1 read-only TX_MODE Transmit Mode 13 1 read-only BTLE_SYSCLK_REQ BTLE System Clock Request 16 1 read-only RIF_LL_ACTIVE Link Layer Active Indication 17 1 read-only XTAL_READY RF Osciallator Xtal Ready 18 1 read-only 0 Indicates that the RF Oscillator is disabled or has not completed its warmup. #0 1 Indicates that the RF Oscillator has completed its warmup count and is ready for use. #1 SOC_USING_RF_OSC_CLK SOC Using RF Clock Indication 19 1 read-only TSM_IRQ0 TSM Interrupt #0 24 1 read-write 0 TSM Interrupt #0 is not asserted. #0 1 TSM Interrupt #0 is asserted. Write '1' to this bit to clear it. #1 TSM_IRQ1 TSM Interrupt #1 25 1 read-write 0 TSM Interrupt #1 is not asserted. #0 1 TSM Interrupt #1 is asserted. Write '1' to this bit to clear it. #1 BLE_ARB_CTRL BLE ARBITRATION CONTROL 0x8 32 read-write 0 0xFFFFFFFF BLE_RELINQUISH BLE Relinquish Control 0 1 read-write XCVR_BUSY Transceiver Busy Status Bit 1 1 read-only 0 RF Channel in available (TSM is idle) #0 1 RF Channel in use (TSM is busy) #1 OVERWRITE_VER OVERWRITE VERSION 0x10 32 read-write 0 0xFFFFFFFF OVERWRITE_VER Overwrite Version Number. 0 8 read-write DMA_CTRL TRANSCEIVER DMA CONTROL 0x14 32 read-write 0x300 0xFFFFFFFF DMA_PAGE Transceiver DMA Page Selector 0 4 read-write 0000 DMA Idle #0000 0001 RX_DIG I and Q #0001 0010 RX_DIG I Only #0010 0011 RX_DIG Q Only #0011 0100 RAW ADC I and Q #0100 0101 RAW ADC I Only #0101 0110 RAW ADC Q only #0110 0111 DC Estimator I and Q #0111 1000 DC Estimator I Only #1000 1001 DC Estimator Q only #1001 1010 RX_DIG Phase Output #1010 1011 Demodulator Hard Decision #1011 1100 Demodulator Soft Decision #1100 1101 Demodulator Data Output #1101 1110 Demodulator CFO Phase Output #1110 SINGLE_REQ_MODE DMA Single Request Mode 4 1 read-write 0 Disable Single Request Mode. The transceiver will assert ipd_req_radio_rx whenever it has a new sample ready for transfer. #0 1 Enable Single Request Mode. A single initial request by the transceiver will transfer the entire DMA block of data #1 BYPASS_DMA_SYNC Bypass External DMA Synchronization 5 1 read-write 0 Don't Bypass External Synchronization. Use this setting if SINGLE_REQ_MODE=1. #0 1 Bypass External Synchronization. This setting is mandatory if SINGLE_REQ_MODE=0. #1 DMA_TRIGGERRED DMA TRIGGERRED 6 1 read-only DMA_TIMED_OUT DMA Transfer Timed Out 7 1 read-write 0 A DMA timeout has not occurred #0 1 A DMA timeout has occurred in Single Request Mode since the last time this bit was cleared #1 DMA_TIMEOUT DMA Timeout 8 4 read-write DMA_DATA TRANSCEIVER DMA DATA 0x18 32 read-only 0 0xFFFFFFFF DMA_DATA DMA Data Register 0 32 read-only DTEST_CTRL DIGITAL TEST MUX CONTROL 0x1C 32 read-write 0 0xFFFFFFFF DTEST_PAGE DTEST Page Selector 0 6 read-write DTEST_EN DTEST Enable 7 1 read-write 0 Disables DTEST. The DTEST pins assume their mission function. #0 1 Enables DTEST. The contents of the selected page (DTEST_PAGE) will appear on the DTEST output pins. #1 GPIO0_OVLAY_PIN GPIO 0 Overlay Pin 8 4 read-write GPIO1_OVLAY_PIN GPIO 1 Overlay Pin 12 4 read-write TSM_GPIO_OVLAY TSM GPIO Overlay Pin Control 16 2 read-write 00 there is no overlay, and the DTEST Page Table dictates the node that appears on each DTEST pin. #00 01 the register GPIO0_OVLAY_PIN[3:0] selects the DTEST pin on which GPIO0_TRIG_EN will appear. #01 DTEST_SHFT DTEST Shift Control 24 3 read-write RAW_MODE_I DTEST Raw Mode Enable for I Channel 28 1 read-write RAW_MODE_Q DTEST Raw Mode Enable for Q Channel 29 1 read-write PACKET_RAM_CTRL PACKET RAM CONTROL 0x20 32 read-write 0 0xFFFFFFFF DBG_PAGE Packet RAM Debug Page Selector 0 4 read-write 0000 Packet RAM Debug Mode Idle #0000 0001 RX_DIG I and Q #0001 0100 RAW ADC I and Q #0100 0111 DC Estimator I and Q #0111 1010 RX_DIG Phase Output #1010 1011 Demodulator Hard Decision #1011 1100 Demodulator Soft Decision #1100 1101 Demodulator Data Output #1101 1110 Demodulator CFO Phase Output #1110 PB_PROTECT Packet Buffer Protect 4 1 read-write 0 Incoming received packets overwrite Packet Buffer RX contents (default) #0 1 Incoming received packets are blocked from overwriting Packet Buffer RX contents #1 XCVR_RAM_ALLOW Allow Packet RAM Transceiver Access 5 1 read-write 0 Protocol Engines, and associated IPS busses, have exclusive access to Packet RAM (mission mode) #0 1 Transceiver-space access to Packet RAM, including Packet RAM debug mode, are allowed #1 ALL_PROTOCOLS_ALLOW Allow IPS bus access to Packet RAM for any protocol at any time. 6 1 read-write 0 IPS bus access to Packet RAM is restricted to the protocol engine currently selected by XCVR_CTRL[PROTOCOL]. #0 1 All IPS bus access to Packet RAM permitted, regardless of XCVR_CTRL[PROTOCOL] setting #1 DBG_TRIGGERRED DBG_TRIGGERRED 7 1 read-only DBG_RAM_FULL DBG_RAM_FULL[1:0] 8 2 read-only 00 Neither Packet RAM0 nor RAM1 is full #00 x1 Packet RAM0 has been filled to capacity. #x1 1x Packet RAM1 has been filled to capacity. #1x RAM0_CLK_ON_OVRD_EN Override control for RAM0 Clock Gate Enable 10 1 read-write 0 Normal operation. #0 1 Use the state of RAM0_CLK_ON_OVRD to override the RAM0 Clock Gate Enable. #1 RAM0_CLK_ON_OVRD Override value for RAM0 Clock Gate Enable 11 1 read-write RAM1_CLK_ON_OVRD_EN Override control for RAM1 Clock Gate Enable 12 1 read-write 0 Normal operation. #0 1 Use the state of RAM1_CLK_ON_OVRD to override the RAM1 Clock Gate Enable. #1 RAM1_CLK_ON_OVRD Override value for RAM1 Clock Gate Enable 13 1 read-write RAM0_CE_ON_OVRD_EN Override control for RAM0 CE (Chip Enable) 14 1 read-write 0 Normal operation. #0 1 Use the state of RAM0_CE_ON_OVRD to override the RAM0 CE. #1 RAM0_CE_ON_OVRD Override value for RAM0 CE (Chip Enable) 15 1 read-write RAM1_CE_ON_OVRD_EN Override control for RAM1 CE (Chip Enable) 16 1 read-write 0 Normal operation. #0 1 Use the state of RAM1_CE_ON_OVRD to override the RAM1 CE. #1 RAM1_CE_ON_OVRD Override value for RAM1 CE (Chip Enable) 17 1 read-write FAD_CTRL FAD CONTROL 0x24 32 read-write 0xF080 0xFFFFFFFF FAD_EN Fast Antenna Diversity Enable 0 1 read-write 0 Fast Antenna Diversity disabled #0 1 Fast Antenna Diversity enabled for 802.15.4 #1 ANTX Antenna Selection State 1 1 read-write ANTX_EN FAD Antenna Controls Enable 4 2 read-write 00 all disabled (held low) #00 01 only RX/TX_SWITCH enabled #01 10 only ANT_A/B enabled #10 11 all enabled #11 ANTX_HZ FAD PAD Tristate Control 6 1 read-write 0 ANT_A, ANT_B, RX_SWITCH and TX_SWITCH are actively driven outputs. #0 1 Antenna controls high impedance- Set ANT_A, ANT_B, RX_SWITCH and TX_SWITCH in high impedance. #1 ANTX_CTRLMODE Antenna Diversity Control Mode 7 1 read-write ANTX_POL FAD Antenna Controls Polarity 8 4 read-write FAD_NOT_GPIO FAD versus GPIO Mode Selector 12 4 read-write LPPS_CTRL LOW POWER PREAMBLE SEARCH CONTROL 0x28 32 read-write 0x64260000 0xFFFFFFFF LPPS_ENABLE LPPS_ENABLE 0 1 read-write LPPS_TZA_ALLOW LPPS_TZA_ALLOW 1 1 read-write LPPS_BBA_ALLOW LPPS_BBA_ALLOW 2 1 read-write LPPS_ADC_ALLOW LPPS_ADC_ALLOW 3 1 read-write LPPS_DCOC_ALLOW LPPS_DCOC_ALLOW 4 1 read-write LPPS_PDET_ALLOW LPPS_PDET_ALLOW 5 1 read-write LPPS_SY_LO_ALLOW LPPS_SY_LO_ALLOW 6 1 read-write LPPS_SY_LO_BUF_ALLOW LPPS_SY_LO_BUF_ALLOW 7 1 read-write LPPS_RX_DIG_ALLOW LPPS_RX_DIG_ALLOW 8 1 read-write LPPS_DCOC_DIG_ALLOW LPPS_DCOC_DIG_ALLOW 9 1 read-write LPPS_START_RX LPPS Fast TSM RX Warmup "Jump-from" Point 16 8 read-write LPPS_DEST_RX LPPS Fast TSM RX Warmup "Jump-to" Point 24 8 read-write RF_NOT_ALLOWED_CTRL WIFI COEXISTENCE CONTROL 0x2C 32 read-write 0 0xFFFFFFFF RF_NOT_ALLOWED_NO_TX RF_NOT_ALLOWED_NO_TX 0 1 read-write 0 Assertion on RF_NOT_ALLOWED has no effect on TX #0 1 Assertion on RF_NOT_ALLOWED can abort TX #1 RF_NOT_ALLOWED_NO_RX RF_NOT_ALLOWED_NO_RX 1 1 read-write 0 Assertion on RF_NOT_ALLOWED has no effect on RX #0 1 Assertion on RF_NOT_ALLOWED can abort RX #1 RF_NOT_ALLOWED_ASSERTED RF_NOT_ALLOWED_ASSERTED 2 1 read-write 0 Assertion on RF_NOT_ALLOWED has not occurred #0 1 Assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared #1 RF_NOT_ALLOWED_TX_ABORT RF_NOT_ALLOWED_TX_ABORT 3 1 read-write 0 A TX abort due to assertion on RF_NOT_ALLOWED has not occurred #0 1 A TX abort due to assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared #1 RF_NOT_ALLOWED_RX_ABORT RF_NOT_ALLOWED_RX_ABORT 4 1 read-write 0 A RX abort due to assertion on RF_NOT_ALLOWED has not occurred #0 1 A RX abort due to assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared #1 RF_NOT_ALLOWED RF_NOT_ALLOWED 5 1 read-only CRCW_CFG CRC/WHITENER CONTROL 0x30 32 read-write 0x1 0xFFFFFFFF CRCW_EN CRC calculation enable 0 1 read-write CRC_ZERO CRC zero 1 1 read-only CRC_EARLY_FAIL CRC error correction fail 2 1 read-only CRC_RES_OUT_VLD CRC result output valid 3 1 read-only CRC_EC_OFFSET CRC error correction offset 16 11 read-only CRC_EC_DONE CRC error correction done 28 1 read-only CRC_EC_FAIL CRC error correction fail 29 1 read-only CRC_EC_MASK CRC ERROR CORRECTION MASK 0x34 32 read-only 0 0xFFFFFFFF CRC_EC_MASK CRC error correction mask 0 32 read-only CRC_RES_OUT CRC RESULT 0x38 32 read-only 0 0xFFFFFFFF CRC_RES_OUT CRC result output 0 32 read-only XCVR_TSM_REGS XCVR_TSM 0x4005C2C0 0 0x11C registers CTRL TRANSCEIVER SEQUENCE MANAGER CONTROL 0 32 read-write 0xFF004000 0xFFFFFFFF FORCE_TX_EN Force Transmit Enable 2 1 read-write 0 TSM Idle #0 1 TSM executes a TX sequence #1 FORCE_RX_EN Force Receive Enable 3 1 read-write 0 TSM Idle #0 1 TSM executes a RX sequence #1 PA_RAMP_SEL PA Ramp Selection 4 2 read-write DATA_PADDING_EN Data Padding Enable 6 2 read-write 00 Disable TX Data Padding #00 01 Enable TX Data Padding #01 TSM_IRQ0_EN TSM_IRQ0 Enable/Disable bit 8 1 read-write 0 TSM_IRQ0 is disabled #0 1 TSM_IRQ0 is enabled #1 TSM_IRQ1_EN TSM_IRQ1 Enable/Disable bit 9 1 read-write 0 TSM_IRQ1 is disabled #0 1 TSM_IRQ1 is enabled #1 RAMP_DN_DELAY PA Ramp Down Delay 12 4 read-write TX_ABORT_DIS Transmit Abort Disable 16 1 read-write RX_ABORT_DIS Receive Abort Disable 17 1 read-write ABORT_ON_CTUNE Abort On Coarse Tune Lock Detect Failure 18 1 read-write 0 don't allow TSM abort on Coarse Tune Unlock Detect #0 1 allow TSM abort on Coarse Tune Unlock Detect #1 ABORT_ON_CYCLE_SLIP Abort On Cycle Slip Lock Detect Failure 19 1 read-write 0 don't allow TSM abort on Cycle Slip Unlock Detect #0 1 allow TSM abort on Cycle Slip Unlock Detect #1 ABORT_ON_FREQ_TARG Abort On Frequency Target Lock Detect Failure 20 1 read-write 0 don't allow TSM abort on Frequency Target Unlock Detect #0 1 allow TSM abort on Frequency Target Unlock Detect #1 BKPT TSM Breakpoint 24 8 read-write END_OF_SEQ TSM END OF SEQUENCE 0x4 32 read-write 0x67666A63 0xFFFFFFFF END_OF_TX_WU End of TX Warmup 0 8 read-write END_OF_TX_WD End of TX Warmdown 8 8 read-write END_OF_RX_WU End of RX Warmup 16 8 read-write END_OF_RX_WD End of RX Warmdown 24 8 read-write OVRD0 TSM OVERRIDE REGISTER 0 0x8 32 read-write 0 0xFFFFFFFF BB_LDO_HF_EN_OVRD_EN Override control for BB_LDO_HF_EN 0 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_HF_EN_OVRD to override the signal "bb_ldo_hf_en". #1 BB_LDO_HF_EN_OVRD Override value for BB_LDO_HF_EN 1 1 read-write BB_LDO_ADCDAC_EN_OVRD_EN Override control for BB_LDO_ADCDAC_EN 2 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_ADCDAC_EN_OVRD to override the signal "bb_ldo_adcdac_en". #1 BB_LDO_ADCDAC_EN_OVRD Override value for BB_LDO_ADCDAC_EN 3 1 read-write BB_LDO_BBA_EN_OVRD_EN Override control for BB_LDO_BBA_EN 4 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_BBA_EN_OVRD to override the signal "bb_ldo_bba_en". #1 BB_LDO_BBA_EN_OVRD Override value for BB_LDO_BBA_EN 5 1 read-write BB_LDO_PD_EN_OVRD_EN Override control for BB_LDO_PD_EN 6 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_PD_EN_OVRD to override the signal "bb_ldo_pd_en". #1 BB_LDO_PD_EN_OVRD Override value for BB_LDO_PD_EN 7 1 read-write BB_LDO_FDBK_EN_OVRD_EN Override control for BB_LDO_FDBK_EN 8 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_FDBK_EN_OVRD to override the signal "bb_ldo_fdbk_en". #1 BB_LDO_FDBK_EN_OVRD Override value for BB_LDO_FDBK_EN 9 1 read-write BB_LDO_VCOLO_EN_OVRD_EN Override control for BB_LDO_VCOLO_EN 10 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_VCOLO_EN_OVRD to override the signal "bb_ldo_vcolo_en". #1 BB_LDO_VCOLO_EN_OVRD Override value for BB_LDO_VCOLO_EN 11 1 read-write BB_LDO_VTREF_EN_OVRD_EN Override control for BB_LDO_VTREF_EN 12 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_VTREF_EN_OVRD to override the signal "bb_ldo_vtref_en". #1 BB_LDO_VTREF_EN_OVRD Override value for BB_LDO_VTREF_EN 13 1 read-write BB_LDO_FDBK_BLEED_EN_OVRD_EN Override control for BB_LDO_FDBK_BLEED_EN 14 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_FDBK_BLEED_EN_OVRD to override the signal "bb_ldo_fdbk_bleed_en". #1 BB_LDO_FDBK_BLEED_EN_OVRD Override value for BB_LDO_FDBK_BLEED_EN 15 1 read-write BB_LDO_VCOLO_BLEED_EN_OVRD_EN Override control for BB_LDO_VCOLO_BLEED_EN 16 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_VCOLO_BLEED_EN_OVRD to override the signal "bb_ldo_vcolo_bleed_en". #1 BB_LDO_VCOLO_BLEED_EN_OVRD Override value for BB_LDO_VCOLO_BLEED_EN 17 1 read-write BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN Override control for BB_LDO_VCOLO_FASTCHARGE_EN 18 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_VCOLO_FASTCHARGE_EN_OVRD to override the signal "bb_ldo_vcolo_fastcharge_en". #1 BB_LDO_VCOLO_FASTCHARGE_EN_OVRD Override value for BB_LDO_VCOLO_FASTCHARGE_EN 19 1 read-write BB_XTAL_PLL_REF_CLK_EN_OVRD_EN Override control for BB_XTAL_PLL_REF_CLK_EN 20 1 read-write 0 Normal operation. #0 1 Use the state of BB_XTAL_PLL_REF_CLK_EN_OVRD to override the signal "bb_xtal_pll_ref_clk_en". #1 BB_XTAL_PLL_REF_CLK_EN_OVRD Override value for BB_XTAL_PLL_REF_CLK_EN 21 1 read-write BB_XTAL_DAC_REF_CLK_EN_OVRD_EN Override control for BB_XTAL_DAC_REF_CLK_EN 22 1 read-write 0 Normal operation. #0 1 Use the state of BB_XTAL_DAC_REF_CLK_EN_OVRD to override the signal "bb_xtal_dac_ref_clk_en". #1 BB_XTAL_DAC_REF_CLK_EN_OVRD Override value for BB_XTAL_DAC_REF_CLK_EN 23 1 read-write BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN Override control for BB_XTAL_AUXPLL_REF_CLK_EN 24 1 read-write 0 Normal operation. #0 1 Use the state of BB_XTAL_AUXPLL_REF_CLK_EN_OVRD to override the signal "bb_xtal_auxpll_ref_clk_en". #1 BB_XTAL_AUXPLL_REF_CLK_EN_OVRD Override value for BB_XTAL_AUXPLL_REF_CLK_EN 25 1 read-write SY_VCO_AUTOTUNE_EN_OVRD_EN Override control for SY_VCO_AUTOTUNE_EN 26 1 read-write 0 Normal operation. #0 1 Use the state of SY_VCO_AUTOTUNE_EN_OVRD to override the signal "sy_vco_autotune_en". #1 SY_VCO_AUTOTUNE_EN_OVRD Override value for SY_VCO_AUTOTUNE_EN 27 1 read-write SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN Override control for SY_PD_CYCLE_SLIP_LD_EN 28 1 read-write 0 Normal operation. #0 1 Use the state of SY_PD_CYCLE_SLIP_LD_EN_OVRD to override the signal "sy_pd_cycle_slip_ld_en". #1 SY_PD_CYCLE_SLIP_LD_EN_OVRD Override value for SY_PD_CYCLE_SLIP_LD_EN 29 1 read-write SY_VCO_EN_OVRD_EN Override control for SY_VCO_EN 30 1 read-write 0 Normal operation. #0 1 Use the state of SY_VCO_EN_OVRD to override the signal "sy_vco_en". #1 SY_VCO_EN_OVRD Override value for SY_VCO_EN 31 1 read-write OVRD1 TSM OVERRIDE REGISTER 1 0xC 32 read-write 0 0xFFFFFFFF SY_LO_RX_BUF_EN_OVRD_EN Override control for SY_LO_RX_BUF_EN 0 1 read-write 0 Normal operation. #0 1 Use the state of SY_LO_RX_BUF_EN_OVRD to override the signal "sy_lo_rx_buf_en". #1 SY_LO_RX_BUF_EN_OVRD Override value for SY_LO_RX_BUF_EN 1 1 read-write SY_LO_TX_BUF_EN_OVRD_EN Override control for SY_LO_TX_BUF_EN 2 1 read-write 0 Normal operation. #0 1 Use the state of SY_LO_TX_BUF_EN_OVRD to override the signal "sy_lo_tx_buf_en". #1 SY_LO_TX_BUF_EN_OVRD Override value for SY_LO_TX_BUF_EN 3 1 read-write SY_DIVN_EN_OVRD_EN Override control for SY_DIVN_EN 4 1 read-write 0 Normal operation. #0 1 Use the state of SY_DIVN_EN_OVRD to override the signal "sy_divn_en". #1 SY_DIVN_EN_OVRD Override value for SY_DIVN_EN 5 1 read-write SY_PD_FILTER_CHARGE_EN_OVRD_EN Override control for SY_PD_FILTER_CHARGE_EN 6 1 read-write 0 Normal operation. #0 1 Use the state of SY_PD_FILTER_CHARGE_EN_OVRD to override the signal "sy_pd_filter_charge_en". #1 SY_PD_FILTER_CHARGE_EN_OVRD Override value for SY_PD_FILTER_CHARGE_EN 7 1 read-write SY_PD_EN_OVRD_EN Override control for SY_PD_EN 8 1 read-write 0 Normal operation. #0 1 Use the state of SY_PD_EN_OVRD to override the signal "sy_pd_en". #1 SY_PD_EN_OVRD Override value for SY_PD_EN 9 1 read-write SY_LO_DIVN_EN_OVRD_EN Override control for SY_LO_DIVN_EN 10 1 read-write 0 Normal operation. #0 1 Use the state of SY_LO_DIVN_EN_OVRD to override the signal "sy_lo_divn_en". #1 SY_LO_DIVN_EN_OVRD Override value for SY_LO_DIVN_EN 11 1 read-write SY_LO_RX_EN_OVRD_EN Override control for SY_LO_RX_EN 12 1 read-write 0 Normal operation. #0 1 Use the state of SY_LO_RX_EN_OVRD to override the signal "sy_lo_rx_en". #1 SY_LO_RX_EN_OVRD Override value for SY_LO_RX_EN 13 1 read-write SY_LO_TX_EN_OVRD_EN Override control for SY_LO_TX_EN 14 1 read-write 0 Normal operation. #0 1 Use the state of SY_LO_TX_EN_OVRD to override the signal "sy_lo_tx_en". #1 SY_LO_TX_EN_OVRD Override value for SY_LO_TX_EN 15 1 read-write SY_DIVN_CAL_EN_OVRD_EN Override control for SY_DIVN_CAL_EN 16 1 read-write 0 Normal operation. #0 1 Use the state of SY_DIVN_CAL_EN_OVRD to override the signal "sy_divn_cal_en". #1 SY_DIVN_CAL_EN_OVRD Override value for SY_DIVN_CAL_EN 17 1 read-write RX_MIXER_EN_OVRD_EN Override control for RX_MIXER_EN 18 1 read-write 0 Normal operation. #0 1 Use the state of RX_MIXER_EN_OVRD to override the signal "rx_mixer_en". #1 RX_MIXER_EN_OVRD Override value for RX_MIXER_EN 19 1 read-write TX_PA_EN_OVRD_EN Override control for TX_PA_EN 20 1 read-write 0 Normal operation. #0 1 Use the state of TX_PA_EN_OVRD to override the signal "tx_pa_en". #1 TX_PA_EN_OVRD Override value for TX_PA_EN 21 1 read-write RX_ADC_I_EN_OVRD_EN Override control for RX_ADC_I_EN 22 1 read-write 0 Normal operation. #0 1 Use the state of RX_ADC_I_EN_OVRD to override the signal "rx_adc_i_en". #1 RX_ADC_I_EN_OVRD Override value for RX_ADC_I_EN 23 1 read-write RX_ADC_Q_EN_OVRD_EN Override control for RX_ADC_Q_EN 24 1 read-write 0 Normal operation. #0 1 Use the state of RX_ADC_Q_EN_OVRD to override the signal "rx_adc_q_en". #1 RX_ADC_Q_EN_OVRD Override value for RX_ADC_Q_EN 25 1 read-write RX_ADC_RESET_EN_OVRD_EN Override control for RX_ADC_RESET_EN 26 1 read-write 0 Normal operation. #0 1 Use the state of RX_ADC_RESET_EN_OVRD to override the signal "rx_adc_reset_en". #1 RX_ADC_RESET_EN_OVRD Override value for RX_ADC_RESET_EN 27 1 read-write RX_BBA_I_EN_OVRD_EN Override control for RX_BBA_I_EN 28 1 read-write 0 Normal operation. #0 1 Use the state of RX_BBA_I_EN_OVRD to override the signal "rx_bba_i_en". #1 RX_BBA_I_EN_OVRD Override value for RX_BBA_I_EN 29 1 read-write RX_BBA_Q_EN_OVRD_EN Override control for RX_BBA_Q_EN 30 1 read-write 0 Normal operation. #0 1 Use the state of RX_BBA_Q_EN_OVRD to override the signal "rx_bba_q_en". #1 RX_BBA_Q_EN_OVRD Override value for RX_BBA_Q_EN 31 1 read-write OVRD2 TSM OVERRIDE REGISTER 2 0x10 32 read-write 0 0xFFFFFFFF RX_BBA_PDET_EN_OVRD_EN Override control for RX_BBA_PDET_EN 0 1 read-write 0 Normal operation. #0 1 Use the state of RX_BBA_PDET_EN_OVRD to override the signal "rx_bba_pdet_en". #1 RX_BBA_PDET_EN_OVRD Override value for RX_BBA_PDET_EN 1 1 read-write RX_BBA_DCOC_EN_OVRD_EN Override control for RX_BBA_DCOC_EN 2 1 read-write 0 Normal operation. #0 1 Use the state of RX_BBA_DCOC_EN_OVRD to override the signal "rx_bba_dcoc_en". #1 RX_BBA_DCOC_EN_OVRD Override value for RX_BBA_DCOC_EN 3 1 read-write RX_LNA_EN_OVRD_EN Override control for RX_LNA_EN 4 1 read-write 0 Normal operation. #0 1 Use the state of RX_LNA_EN_OVRD to override the signal "rx_lna_en". #1 RX_LNA_EN_OVRD Override value for RX_LNA_EN 5 1 read-write RX_TZA_I_EN_OVRD_EN Override control for RX_TZA_I_EN 6 1 read-write 0 Normal operation. #0 1 Use the state of RX_TZA_I_EN_OVRD to override the signal "rx_tza_i_en". #1 RX_TZA_I_EN_OVRD Override value for RX_TZA_I_EN 7 1 read-write RX_TZA_Q_EN_OVRD_EN Override control for RX_TZA_Q_EN 8 1 read-write 0 Normal operation. #0 1 Use the state of RX_TZA_Q_EN_OVRD to override the signal "rx_tza_q_en". #1 RX_TZA_Q_EN_OVRD Override value for RX_TZA_Q_EN 9 1 read-write RX_TZA_PDET_EN_OVRD_EN Override control for RX_TZA_PDET_EN 10 1 read-write 0 Normal operation. #0 1 Use the state of RX_TZA_PDET_EN_OVRD to override the signal "rx_tza_pdet_en". #1 RX_TZA_PDET_EN_OVRD Override value for RX_TZA_PDET_EN 11 1 read-write RX_TZA_DCOC_EN_OVRD_EN Override control for RX_TZA_DCOC_EN 12 1 read-write 0 Normal operation. #0 1 Use the state of RX_TZA_DCOC_EN_OVRD to override the signal "rx_tza_dcoc_en". #1 RX_TZA_DCOC_EN_OVRD Override control for RX_TZA_DCOC_EN 13 1 read-write 0 Normal operation. #0 1 Use the state of RX_TZA_DCOC_EN_OVRD to override the signal "rx_tza_dcoc_en". #1 PLL_DIG_EN_OVRD_EN Override control for PLL_DIG_EN 14 1 read-write 0 Normal operation. #0 1 Use the state of PLL_DIG_EN_OVRD to override the signal "pll_dig_en". #1 PLL_DIG_EN_OVRD Override value for PLL_DIG_EN 15 1 read-write TX_DIG_EN_OVRD_EN Override control for TX_DIG_EN 16 1 read-write 0 Normal operation. #0 1 Use the state of TX_DIG_EN_OVRD to override the signal "tx_dig_en". #1 TX_DIG_EN_OVRD Override value for TX_DIG_EN 17 1 read-write RX_DIG_EN_OVRD_EN Override control for RX_DIG_EN 18 1 read-write 0 Normal operation. #0 1 Use the state of RX_DIG_EN_OVRD to override the signal "rx_dig_en". #1 RX_DIG_EN_OVRD Override value for RX_DIG_EN 19 1 read-write RX_INIT_OVRD_EN Override control for RX_INIT 20 1 read-write 0 Normal operation. #0 1 Use the state of RX_INIT_OVRD to override the signal "rx_init". #1 RX_INIT_OVRD Override value for RX_INIT 21 1 read-write SIGMA_DELTA_EN_OVRD_EN Override control for SIGMA_DELTA_EN 22 1 read-write 0 Normal operation. #0 1 Use the state of SIGMA_DELTA_EN_OVRD to override the signal "sigma_delta_en". #1 SIGMA_DELTA_EN_OVRD Override value for SIGMA_DELTA_EN 23 1 read-write RX_PHY_EN_OVRD_EN Override control for RX_PHY_EN 24 1 read-write 0 Normal operation. #0 1 Use the state of RX_PHY_EN_OVRD to override the signal "rx_phy_en". #1 RX_PHY_EN_OVRD Override value for RX_PHY_EN 25 1 read-write DCOC_EN_OVRD_EN Override control for DCOC_EN 26 1 read-write 0 Normal operation. #0 1 Use the state of DCOC_EN_OVRD to override the signal "dcoc_en". #1 DCOC_EN_OVRD Override value for DCOC_EN 27 1 read-write DCOC_INIT_OVRD_EN Override control for DCOC_INIT 28 1 read-write 0 Normal operation. #0 1 Use the state of DCOC_INIT_OVRD to override the signal "dcoc_init". #1 DCOC_INIT_OVRD Override value for DCOC_INIT 29 1 read-write FREQ_TARG_LD_EN_OVRD_EN Override control for FREQ_TARG_LD_EN 30 1 read-write 0 Normal operation. #0 1 Use the state of FREQ_TARG_LD_EN_OVRD to override the signal "freq_targ_ld_en". #1 FREQ_TARG_LD_EN_OVRD Override value for FREQ_TARG_LD_EN 31 1 read-write OVRD3 TSM OVERRIDE REGISTER 3 0x14 32 read-write 0 0xFFFFFFFF TSM_SPARE0_EN_OVRD_EN Override control for TSM_SPARE0_EN 0 1 read-write 0 Normal operation. #0 1 Use the state of TSM_SPARE0_EN_OVRD to override the signal "tsm_spare0_en". #1 TSM_SPARE0_EN_OVRD Override value for TSM_SPARE0_EN 1 1 read-write TSM_SPARE1_EN_OVRD_EN Override control for TSM_SPARE1_EN 2 1 read-write 0 Normal operation. #0 1 Use the state of TSM_SPARE1_EN_OVRD to override the signal "tsm_spare1_en". #1 TSM_SPARE1_EN_OVRD Override value for TSM_SPARE1_EN 3 1 read-write TSM_SPARE2_EN_OVRD_EN Override control for TSM_SPARE2_EN 4 1 read-write 0 Normal operation. #0 1 Use the state of TSM_SPARE2_EN_OVRD to override the signal "tsm_spare2_en". #1 TSM_SPARE2_EN_OVRD Override value for TSM_SPARE2_EN 5 1 read-write TSM_SPARE3_EN_OVRD_EN Override control for TSM_SPARE3_EN 6 1 read-write 0 Normal operation. #0 1 Use the state of TSM_SPARE3_EN_OVRD to override the signal "tsm_spare3_en". #1 TSM_SPARE3_EN_OVRD Override value for TSM_SPARE3_EN 7 1 read-write RXTX_AUXPLL_BIAS_EN_OVRD_EN Override control for RXTX_AUXPLL_BIAS_EN 8 1 read-write 0 Normal operation. #0 1 Use the state of RXTX_AUXPLL_BIAS_EN_OVRD to override the signal "rxtx_auxpll_bias_en". #1 RXTX_AUXPLL_BIAS_EN_OVRD Override value for RXTX_AUXPLL_BIAS_EN 9 1 read-write RXTX_AUXPLL_VCO_EN_OVRD_EN Override control for RXTX_AUXPLL_VCO_EN 10 1 read-write 0 Normal operation. #0 1 Use the state of RXTX_AUXPLL_VCO_EN_OVRD to override the signal "rxtx_auxpll_vco_en". #1 RXTX_AUXPLL_VCO_EN_OVRD Override value for RXTX_AUXPLL_VCO_EN 11 1 read-write RXTX_AUXPLL_FCAL_EN_OVRD_EN Override control for RXTX_AUXPLL_FCAL_EN 12 1 read-write 0 Normal operation. #0 1 Use the state of RXTX_AUXPLL_FCAL_EN_OVRD to override the signal "rxtx_auxpll_fcal_en". #1 RXTX_AUXPLL_FCAL_EN_OVRD Override value for RXTX_AUXPLL_FCAL_EN 13 1 read-write RXTX_AUXPLL_LF_EN_OVRD_EN Override control for RXTX_AUXPLL_LF_EN 14 1 read-write 0 Normal operation. #0 1 Use the state of RXTX_AUXPLL_LF_EN_OVRD to override the signal "rxtx_auxpll_lf_en". #1 RXTX_AUXPLL_LF_EN_OVRD Override value for RXTX_AUXPLL_LF_EN 15 1 read-write RXTX_AUXPLL_PD_EN_OVRD_EN Override control for RXTX_AUXPLL_PD_EN 16 1 read-write 0 Normal operation. #0 1 Use the state of RXTX_AUXPLL_PD_EN_OVRD to override the signal "rxtx_auxpll_pd_en". #1 RXTX_AUXPLL_PD_EN_OVRD Override value for RXTX_AUXPLL_PD_EN 17 1 read-write RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN Override control for RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN 18 1 read-write 0 Normal operation. #0 1 Use the state of RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD to override the signal "rxtx_auxpll_pd_lf_filter_charge_en". #1 RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD Override value for RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN 19 1 read-write RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN Override control for RXTX_AUXPLL_ADC_BUF_EN 20 1 read-write 0 Normal operation. #0 1 Use the state of RXTX_AUXPLL_ADC_BUF_EN_OVRD to override the signal "rxtx_auxpll_adc_buf_en". #1 RXTX_AUXPLL_ADC_BUF_EN_OVRD Override value for RXTX_AUXPLL_ADC_BUF_EN 21 1 read-write RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN Override control for RXTX_AUXPLL_DIG_BUF_EN 22 1 read-write 0 Normal operation. #0 1 Use the state of RXTX_AUXPLL_DIG_BUF_EN_OVRD to override the signal "rxtx_auxpll_dig_buf_en". #1 RXTX_AUXPLL_DIG_BUF_EN_OVRD Override value for RXTX_AUXPLL_DIG_BUF_EN 23 1 read-write RXTX_RCCAL_EN_OVRD_EN Override control for RXTX_RCCAL_EN 24 1 read-write 0 Normal operation. #0 1 Use the state of RXTX_RCCAL_EN_OVRD to override the signal "rxtx_rccal_en". #1 RXTX_RCCAL_EN_OVRD Override value for RXTX_RCCAL_EN 25 1 read-write TX_HPM_DAC_EN_OVRD_EN Override control for TX_HPM_DAC_EN 26 1 read-write 0 Normal operation. #0 1 Use the state of TX_HPM_DAC_EN_OVRD to override the signal "tx_hpm_dac_en". #1 TX_HPM_DAC_EN_OVRD Override value for TX_HPM_DAC_EN 27 1 read-write TX_MODE_OVRD_EN Override control for TX_MODE 28 1 read-write 0 Normal operation. #0 1 Use the state of TX_MODE_OVRD to override the signal "tx_mode". #1 TX_MODE_OVRD Override value for TX_MODE 29 1 read-write RX_MODE_OVRD_EN Override control for RX_MODE 30 1 read-write 0 Normal operation. #0 1 Use the state of RX_MODE_OVRD to override the signal "rx_mode". #1 RX_MODE_OVRD Override value for RX_MODE 31 1 read-write PA_POWER PA POWER 0x18 32 read-write 0 0xFFFFFFFF PA_POWER PA POWER 0 6 read-write PA_RAMP_TBL0 PA RAMP TABLE 0 0x1C 32 read-write 0x10080402 0xFFFFFFFF PA_RAMP0 PA_RAMP0 0 6 read-write PA_RAMP1 PA_RAMP1 8 6 read-write PA_RAMP2 PA_RAMP2 16 6 read-write PA_RAMP3 PA_RAMP3 24 6 read-write PA_RAMP_TBL1 PA RAMP TABLE 1 0x20 32 read-write 0x3A342A1C 0xFFFFFFFF PA_RAMP4 PA_RAMP4 0 6 read-write PA_RAMP5 PA_RAMP5 8 6 read-write PA_RAMP6 PA_RAMP6 16 6 read-write PA_RAMP7 PA_RAMP7 24 6 read-write RECYCLE_COUNT TSM RECYCLE COUNT 0x24 32 read-write 0x1A0464 0xFFFFFFFF RECYCLE_COUNT0 TSM RX Recycle Count 0 0 8 read-write RECYCLE_COUNT1 TSM RX Recycle Count 1 8 8 read-write RECYCLE_COUNT2 TSM RX Recycle Count 2 16 8 read-write FAST_CTRL1 TSM FAST WARMUP CONTROL REGISTER 1 0x28 32 read-write 0xFF00 0xFFFFFFFF FAST_TX_WU_EN Fast TSM TX Warmup Enable 0 1 read-write 0 Fast TSM TX Warmups are disabled #0 1 Fast TSM TX Warmups are enabled, if the RF channel has not changed since the last TX warmup, and for BLE mode, the RF channel is not an advertising channel. #1 FAST_RX_WU_EN Fast TSM RX Warmup Enable 1 1 read-write 0 Fast TSM RX Warmups are disabled #0 1 Fast TSM RX Warmups are enabled, if the RF channel has not changed since the last RX warmup, and for BLE mode, the RF channel is not an advertising channel. #1 FAST_RX2TX_EN Fast TSM RX-to-TX Transition Enable 2 1 read-write FAST_WU_CLEAR Fast TSM Warmup Clear State 3 1 read-write FAST_RX2TX_START TSM "Jump-to" point for a Fast TSM RX-to-TX Transition. 8 8 read-write FAST_CTRL2 TSM FAST WARMUP CONTROL REGISTER 2 0x2C 32 read-write 0xFFFFFFFF 0xFFFFFFFF FAST_START_TX Fast TSM TX "Jump-from" Point 0 8 read-write FAST_DEST_TX Fast TSM TX "Jump-to" Point 8 8 read-write FAST_START_RX Fast TSM RX "Jump-from" Point 16 8 read-write FAST_DEST_RX Fast TSM RX "Jump-to" Point 24 8 read-write TIMING00 TSM_TIMING00 0x30 32 read-write 0x67006A00 0xFFFFFFFF BB_LDO_HF_EN_TX_HI Assertion time setting for BB_LDO_HF_EN (TX) 0 8 read-write BB_LDO_HF_EN_TX_LO De-assertion time setting for BB_LDO_HF_EN (TX) 8 8 read-write BB_LDO_HF_EN_RX_HI Assertion time setting for BB_LDO_HF_EN (RX) 16 8 read-write BB_LDO_HF_EN_RX_LO De-assertion time setting for BB_LDO_HF_EN (RX) 24 8 read-write TIMING01 TSM_TIMING01 0x34 32 read-write 0x67006A00 0xFFFFFFFF BB_LDO_ADCDAC_EN_TX_HI Assertion time setting for BB_LDO_ADCDAC_EN (TX) 0 8 read-write BB_LDO_ADCDAC_EN_TX_LO De-assertion time setting for BB_LDO_ADCDAC_EN (TX) 8 8 read-write BB_LDO_ADCDAC_EN_RX_HI Assertion time setting for BB_LDO_ADCDAC_EN (RX) 16 8 read-write BB_LDO_ADCDAC_EN_RX_LO De-assertion time setting for BB_LDO_ADCDAC_EN (RX) 24 8 read-write TIMING02 TSM_TIMING02 0x38 32 read-write 0x6700FFFF 0xFFFFFFFF BB_LDO_BBA_EN_RX_HI Assertion time setting for BB_LDO_BBA_EN (RX) 16 8 read-write BB_LDO_BBA_EN_RX_LO De-assertion time setting for BB_LDO_BBA_EN (RX) 24 8 read-write TIMING03 TSM_TIMING03 0x3C 32 read-write 0x67006A00 0xFFFFFFFF BB_LDO_PD_EN_TX_HI Assertion time setting for BB_LDO_PD_EN (TX) 0 8 read-write BB_LDO_PD_EN_TX_LO De-assertion time setting for BB_LDO_PD_EN (TX) 8 8 read-write BB_LDO_PD_EN_RX_HI Assertion time setting for BB_LDO_PD_EN (RX) 16 8 read-write BB_LDO_PD_EN_RX_LO De-assertion time setting for BB_LDO_PD_EN (RX) 24 8 read-write TIMING04 TSM_TIMING04 0x40 32 read-write 0x67006A00 0xFFFFFFFF BB_LDO_FDBK_EN_TX_HI Assertion time setting for BB_LDO_FDBK_EN (TX) 0 8 read-write BB_LDO_FDBK_EN_TX_LO De-assertion time setting for BB_LDO_FDBK_EN (TX) 8 8 read-write BB_LDO_FDBK_EN_RX_HI Assertion time setting for BB_LDO_FDBK_EN (RX) 16 8 read-write BB_LDO_FDBK_EN_RX_LO De-assertion time setting for BB_LDO_FDBK_EN (RX) 24 8 read-write TIMING05 TSM_TIMING05 0x44 32 read-write 0x67006A00 0xFFFFFFFF BB_LDO_VCOLO_EN_TX_HI Assertion time setting for BB_LDO_VCOLO_EN (TX) 0 8 read-write BB_LDO_VCOLO_EN_TX_LO De-assertion time setting for BB_LDO_VCOLO_EN (TX) 8 8 read-write BB_LDO_VCOLO_EN_RX_HI Assertion time setting for BB_LDO_VCOLO_EN (RX) 16 8 read-write BB_LDO_VCOLO_EN_RX_LO De-assertion time setting for BB_LDO_VCOLO_EN (RX) 24 8 read-write TIMING06 TSM_TIMING06 0x48 32 read-write 0x67006A00 0xFFFFFFFF BB_LDO_VTREF_EN_TX_HI Assertion time setting for BB_LDO_VTREF_EN (TX) 0 8 read-write BB_LDO_VTREF_EN_TX_LO De-assertion time setting for BB_LDO_VTREF_EN (TX) 8 8 read-write BB_LDO_VTREF_EN_RX_HI Assertion time setting for BB_LDO_VTREF_EN (RX) 16 8 read-write BB_LDO_VTREF_EN_RX_LO De-assertion time setting for BB_LDO_VTREF_EN (RX) 24 8 read-write TIMING07 TSM_TIMING07 0x4C 32 read-write 0x5000500 0xFFFFFFFF BB_LDO_FDBK_BLEED_EN_TX_HI Assertion time setting for BB_LDO_FDBK_BLEED_EN (TX) 0 8 read-write BB_LDO_FDBK_BLEED_EN_TX_LO De-assertion time setting for BB_LDO_FDBK_BLEED_EN (TX) 8 8 read-write BB_LDO_FDBK_BLEED_EN_RX_HI Assertion time setting for BB_LDO_FDBK_BLEED_EN (RX) 16 8 read-write BB_LDO_FDBK_BLEED_EN_RX_LO De-assertion time setting for BB_LDO_FDBK_BLEED_EN (RX) 24 8 read-write TIMING08 TSM_TIMING08 0x50 32 read-write 0x3000300 0xFFFFFFFF BB_LDO_VCOLO_BLEED_EN_TX_HI Assertion time setting for BB_LDO_VCOLO_BLEED_EN (TX) 0 8 read-write BB_LDO_VCOLO_BLEED_EN_TX_LO De-assertion time setting for BB_LDO_VCOLO_BLEED_EN (TX) 8 8 read-write BB_LDO_VCOLO_BLEED_EN_RX_HI Assertion time setting for BB_LDO_VCOLO_BLEED_EN (RX) 16 8 read-write BB_LDO_VCOLO_BLEED_EN_RX_LO De-assertion time setting for BB_LDO_VCOLO_BLEED_EN (RX) 24 8 read-write TIMING09 TSM_TIMING09 0x54 32 read-write 0x3000300 0xFFFFFFFF BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI Assertion time setting for BB_LDO_VCOLO_FASTCHARGE_EN (TX) 0 8 read-write BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO De-assertion time setting for BB_LDO_VCOLO_FASTCHARGE_EN (TX) 8 8 read-write BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI Assertion time setting for BB_LDO_VCOLO_FASTCHARGE_EN (RX) 16 8 read-write BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO De-assertion time setting for BB_LDO_VCOLO_FASTCHARGE_EN (RX) 24 8 read-write TIMING10 TSM_TIMING10 0x58 32 read-write 0x67036A03 0xFFFFFFFF BB_XTAL_PLL_REF_CLK_EN_TX_HI Assertion time setting for BB_XTAL_PLL_REF_CLK_EN (TX) 0 8 read-write BB_XTAL_PLL_REF_CLK_EN_TX_LO De-assertion time setting for BB_XTAL_PLL_REF_CLK_EN (TX) 8 8 read-write BB_XTAL_PLL_REF_CLK_EN_RX_HI Assertion time setting for BB_XTAL_PLL_REF_CLK_EN (RX) 16 8 read-write BB_XTAL_PLL_REF_CLK_EN_RX_LO De-assertion time setting for BB_XTAL_PLL_REF_CLK_EN (RX) 24 8 read-write TIMING11 TSM_TIMING11 0x5C 32 read-write 0xFFFF6A03 0xFFFFFFFF BB_XTAL_DAC_REF_CLK_EN_TX_HI Assertion time setting for BB_XTAL_DAC_REF_CLK_EN (TX) 0 8 read-write BB_XTAL_DAC_REF_CLK_EN_TX_LO De-assertion time setting for BB_XTAL_DAC_REF_CLK_EN (TX) 8 8 read-write TIMING12 TSM_TIMING12 0x60 32 read-write 0x6703FFFF 0xFFFFFFFF RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI Assertion time setting for RXTX_AUXPLL_VCO_REF_CLK_EN (RX) 16 8 read-write RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO De-assertion time setting for RXTX_AUXPLL_VCO_REF_CLK_EN (RX) 24 8 read-write TIMING13 TSM_TIMING13 0x64 32 read-write 0x16004A00 0xFFFFFFFF SY_VCO_AUTOTUNE_EN_TX_HI Assertion time setting for SY_VCO_AUTOTUNE_EN (TX) 0 8 read-write SY_VCO_AUTOTUNE_EN_TX_LO De-assertion time setting for SY_VCO_AUTOTUNE_EN (TX) 8 8 read-write SY_VCO_AUTOTUNE_EN_RX_HI Assertion time setting for SY_VCO_AUTOTUNE_EN (RX) 16 8 read-write SY_VCO_AUTOTUNE_EN_RX_LO De-assertion time setting for SY_VCO_AUTOTUNE_EN (RX) 24 8 read-write TIMING14 TSM_TIMING14 0x68 32 read-write 0x672F645F 0xFFFFFFFF SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI Assertion time setting for SY_PD_CYCLE_SLIP_LD_FT_EN (TX) 0 8 read-write SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO De-assertion time setting for SY_PD_CYCLE_SLIP_LD_FT_EN (TX) 8 8 read-write SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI Assertion time setting for SY_PD_CYCLE_SLIP_LD_FT_EN (RX) 16 8 read-write SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO De-assertion time setting for SY_PD_CYCLE_SLIP_LD_FT_EN (RX) 24 8 read-write TIMING15 TSM_TIMING15 0x6C 32 read-write 0x67036A03 0xFFFFFFFF SY_VCO_EN_TX_HI Assertion time setting for SY_VCO_EN (TX) 0 8 read-write SY_VCO_EN_TX_LO De-assertion time setting for SY_VCO_EN (TX) 8 8 read-write SY_VCO_EN_RX_HI Assertion time setting for SY_VCO_EN (RX) 16 8 read-write SY_VCO_EN_RX_LO De-assertion time setting for SY_VCO_EN (RX) 24 8 read-write TIMING16 TSM_TIMING16 0x70 32 read-write 0x671AFFFF 0xFFFFFFFF SY_LO_RX_BUF_EN_RX_HI Assertion time setting for SY_LO_RX_BUF_EN (RX) 16 8 read-write SY_LO_RX_BUF_EN_RX_LO De-assertion time setting for SY_LO_RX_BUF_EN (RX) 24 8 read-write TIMING17 TSM_TIMING17 0x74 32 read-write 0xFFFF6A5A 0xFFFFFFFF SY_LO_TX_BUF_EN_TX_HI Assertion time setting for SY_LO_TX_BUF_EN (TX) 0 8 read-write SY_LO_TX_BUF_EN_TX_LO De-assertion time setting for SY_LO_TX_BUF_EN (TX) 8 8 read-write TIMING18 TSM_TIMING18 0x78 32 read-write 0x67056A05 0xFFFFFFFF SY_DIVN_EN_TX_HI Assertion time setting for SY_DIVN_EN (TX) 0 8 read-write SY_DIVN_EN_TX_LO De-assertion time setting for SY_DIVN_EN (TX) 8 8 read-write SY_DIVN_EN_RX_HI Assertion time setting for SY_DIVN_EN (RX) 16 8 read-write SY_DIVN_EN_RX_LO De-assertion time setting for SY_DIVN_EN (RX) 24 8 read-write TIMING19 TSM_TIMING19 0x7C 32 read-write 0x16054A05 0xFFFFFFFF SY_PD_FILTER_CHARGE_EN_TX_HI Assertion time setting for SY_PD_FILTER_CHARGE_EN (TX) 0 8 read-write SY_PD_FILTER_CHARGE_EN_TX_LO De-assertion time setting for SY_PD_FILTER_CHARGE_EN (TX) 8 8 read-write SY_PD_FILTER_CHARGE_EN_RX_HI Assertion time setting for SY_PD_FILTER_CHARGE_EN (RX) 16 8 read-write SY_PD_FILTER_CHARGE_EN_RX_LO De-assertion time setting for SY_PD_FILTER_CHARGE_EN (RX) 24 8 read-write TIMING20 TSM_TIMING20 0x80 32 read-write 0x67056A05 0xFFFFFFFF SY_PD_EN_TX_HI Assertion time setting for SY_PD_EN (TX) 0 8 read-write SY_PD_EN_TX_LO De-assertion time setting for SY_PD_EN (TX) 8 8 read-write SY_PD_EN_RX_HI Assertion time setting for SY_PD_EN (RX) 16 8 read-write SY_PD_EN_RX_LO De-assertion time setting for SY_PD_EN (RX) 24 8 read-write TIMING21 TSM_TIMING21 0x84 32 read-write 0x67046A04 0xFFFFFFFF SY_LO_DIVN_EN_TX_HI Assertion time setting for SY_LO_DIVN_EN (TX) 0 8 read-write SY_LO_DIVN_EN_TX_LO De-assertion time setting for SY_LO_DIVN_EN (TX) 8 8 read-write SY_LO_DIVN_EN_RX_HI Assertion time setting for SY_LO_DIVN_EN (RX) 16 8 read-write SY_LO_DIVN_EN_RX_LO De-assertion time setting for SY_LO_DIVN_EN (RX) 24 8 read-write TIMING22 TSM_TIMING22 0x88 32 read-write 0x6704FFFF 0xFFFFFFFF SY_LO_RX_EN_RX_HI Assertion time setting for SY_LO_RX_EN (RX) 16 8 read-write SY_LO_RX_EN_RX_LO De-assertion time setting for SY_LO_RX_EN (RX) 24 8 read-write TIMING23 TSM_TIMING23 0x8C 32 read-write 0xFFFF6A04 0xFFFFFFFF SY_LO_TX_EN_TX_HI Assertion time setting for SY_LO_TX_EN (TX) 0 8 read-write SY_LO_TX_EN_TX_LO De-assertion time setting for SY_LO_TX_EN (TX) 8 8 read-write TIMING24 TSM_TIMING24 0x90 32 read-write 0x16004A00 0xFFFFFFFF SY_DIVN_CAL_EN_TX_HI Assertion time setting for SY_DIVN_CAL_EN (TX) 0 8 read-write SY_DIVN_CAL_EN_TX_LO De-assertion time setting for SY_DIVN_CAL_EN (TX) 8 8 read-write SY_DIVN_CAL_EN_RX_HI Assertion time setting for SY_DIVN_CAL_EN (RX) 16 8 read-write SY_DIVN_CAL_EN_RX_LO De-assertion time setting for SY_DIVN_CAL_EN (RX) 24 8 read-write TIMING25 TSM_TIMING25 0x94 32 read-write 0x671BFFFF 0xFFFFFFFF RX_LNA_MIXER_EN_RX_HI Assertion time setting for RX_LNA_MIXER_EN (RX) 16 8 read-write RX_LNA_MIXER_EN_RX_LO De-assertion time setting for RX_LNA_MIXER_EN (RX) 24 8 read-write TIMING26 TSM_TIMING26 0x98 32 read-write 0xFFFF6A5A 0xFFFFFFFF TX_PA_EN_TX_HI Assertion time setting for TX_PA_EN (TX) 0 8 read-write TX_PA_EN_TX_LO De-assertion time setting for TX_PA_EN (TX) 8 8 read-write TIMING27 TSM_TIMING27 0x9C 32 read-write 0x671EFFFF 0xFFFFFFFF RX_ADC_I_Q_EN_RX_HI Assertion time setting for RX_ADC_I_Q_EN (RX) 16 8 read-write RX_ADC_I_Q_EN_RX_LO De-assertion time setting for RX_ADC_I_Q_EN (RX) 24 8 read-write TIMING28 TSM_TIMING28 0xA0 32 read-write 0x1F1EFFFF 0xFFFFFFFF RX_ADC_RESET_EN_RX_HI Assertion time setting for RX_ADC_RESET_EN (RX) 16 8 read-write RX_ADC_RESET_EN_RX_LO De-assertion time setting for RX_ADC_RESET_EN (RX) 24 8 read-write TIMING29 TSM_TIMING29 0xA4 32 read-write 0x671CFFFF 0xFFFFFFFF RX_BBA_I_Q_EN_RX_HI Assertion time setting for RX_BBA_I_Q_EN (RX) 16 8 read-write RX_BBA_I_Q_EN_RX_LO De-assertion time setting for RX_BBA_I_Q_EN (RX) 24 8 read-write TIMING30 TSM_TIMING30 0xA8 32 read-write 0x671EFFFF 0xFFFFFFFF RX_BBA_PDET_EN_RX_HI Assertion time setting for RX_BBA_PDET_EN (RX) 16 8 read-write RX_BBA_PDET_EN_RX_LO De-assertion time setting for RX_BBA_PDET_EN (RX) 24 8 read-write TIMING31 TSM_TIMING31 0xAC 32 read-write 0x671DFFFF 0xFFFFFFFF RX_BBA_TZA_DCOC_EN_RX_HI Assertion time setting for RX_BBA_TZA_DCOC_EN (RX) 16 8 read-write RX_BBA_TZA_DCOC_EN_RX_LO De-assertion time setting for RX_BBA_TZA_DCOC_EN (RX) 24 8 read-write TIMING32 TSM_TIMING32 0xB0 32 read-write 0x671BFFFF 0xFFFFFFFF RX_TZA_I_Q_EN_RX_HI Assertion time setting for RX_TZA_I_Q_EN (RX) 16 8 read-write RX_TZA_I_Q_EN_RX_LO De-assertion time setting for RX_TZA_I_Q_EN (RX) 24 8 read-write TIMING33 TSM_TIMING33 0xB4 32 read-write 0x671EFFFF 0xFFFFFFFF RX_TZA_PDET_EN_RX_HI Assertion time setting for RX_TZA_PDET_EN (RX) 16 8 read-write RX_TZA_PDET_EN_RX_LO De-assertion time setting for RX_TZA_PDET_EN (RX) 24 8 read-write TIMING34 TSM_TIMING34 0xB8 32 read-write 0x67056A05 0xFFFFFFFF PLL_DIG_EN_TX_HI Assertion time setting for PLL_DIG_EN (TX) 0 8 read-write PLL_DIG_EN_TX_LO De-assertion time setting for PLL_DIG_EN (TX) 8 8 read-write PLL_DIG_EN_RX_HI Assertion time setting for PLL_DIG_EN (RX) 16 8 read-write PLL_DIG_EN_RX_LO De-assertion time setting for PLL_DIG_EN (RX) 24 8 read-write TIMING35 TSM_TIMING35 0xBC 32 read-write 0xFFFF6A5D 0xFFFFFFFF TX_DIG_EN_TX_HI Assertion time setting for TX_DIG_EN (TX) 0 8 read-write TX_DIG_EN_TX_LO De-assertion time setting for TX_DIG_EN (TX) 8 8 read-write TIMING36 TSM_TIMING36 0xC0 32 read-write 0x6764FFFF 0xFFFFFFFF RX_DIG_EN_RX_HI Assertion time setting for RX_DIG_EN (RX) 16 8 read-write RX_DIG_EN_RX_LO De-assertion time setting for RX_DIG_EN (RX) 24 8 read-write TIMING37 TSM_TIMING37 0xC4 32 read-write 0x6564FFFF 0xFFFFFFFF RX_INIT_RX_HI Assertion time setting for RX_INIT (RX) 16 8 read-write RX_INIT_RX_LO De-assertion time setting for RX_INIT (RX) 24 8 read-write TIMING38 TSM_TIMING38 0xC8 32 read-write 0x670C6A40 0xFFFFFFFF SIGMA_DELTA_EN_TX_HI Assertion time setting for SIGMA_DELTA_EN (TX) 0 8 read-write SIGMA_DELTA_EN_TX_LO De-assertion time setting for SIGMA_DELTA_EN (TX) 8 8 read-write SIGMA_DELTA_EN_RX_HI Assertion time setting for SIGMA_DELTA_EN (RX) 16 8 read-write SIGMA_DELTA_EN_RX_LO De-assertion time setting for SIGMA_DELTA_EN (RX) 24 8 read-write TIMING39 TSM_TIMING39 0xCC 32 read-write 0x6764FFFF 0xFFFFFFFF RX_PHY_EN_RX_HI Assertion time setting for RX_PHY_EN (RX) 16 8 read-write RX_PHY_EN_RX_LO De-assertion time setting for RX_PHY_EN (RX) 24 8 read-write TIMING40 TSM_TIMING40 0xD0 32 read-write 0x6724FFFF 0xFFFFFFFF DCOC_EN_RX_HI Assertion time setting for DCOC_EN (RX) 16 8 read-write DCOC_EN_RX_LO De-assertion time setting for DCOC_EN (RX) 24 8 read-write TIMING41 TSM_TIMING41 0xD4 32 read-write 0x2524FFFF 0xFFFFFFFF DCOC_INIT_RX_HI Assertion time setting for DCOC_INIT (RX) 16 8 read-write DCOC_INIT_RX_LO De-assertion time setting for DCOC_INIT (RX) 24 8 read-write TIMING42 TSM_TIMING42 0xD8 32 read-write 0xFFFFFFFF 0xFFFFFFFF SAR_ADC_TRIG_EN_TX_HI Assertion time setting for SAR_ADC_TRIG_EN (TX) 0 8 read-write SAR_ADC_TRIG_EN_TX_LO De-assertion time setting for SAR_ADC_TRIG_EN (TX) 8 8 read-write SAR_ADC_TRIG_EN_RX_HI Assertion time setting for SAR_ADC_TRIG_EN (RX) 16 8 read-write SAR_ADC_TRIG_EN_RX_LO De-assertion time setting for SAR_ADC_TRIG_EN (RX) 24 8 read-write TIMING43 TSM_TIMING43 0xDC 32 read-write 0xFFFFFFFF 0xFFFFFFFF TSM_SPARE0_EN_TX_HI Assertion time setting for TSM_SPARE0_EN (TX) 0 8 read-write TSM_SPARE0_EN_TX_LO De-assertion time setting for TSM_SPARE0_EN (TX) 8 8 read-write TSM_SPARE0_EN_RX_HI Assertion time setting for TSM_SPARE0_EN (RX) 16 8 read-write TSM_SPARE0_EN_RX_LO De-assertion time setting for TSM_SPARE0_EN (RX) 24 8 read-write TIMING44 TSM_TIMING44 0xE0 32 read-write 0xFFFFFFFF 0xFFFFFFFF TSM_SPARE1_EN_TX_HI Assertion time setting for TSM_SPARE1_EN (TX) 0 8 read-write TSM_SPARE1_EN_TX_LO De-assertion time setting for TSM_SPARE1_EN (TX) 8 8 read-write TSM_SPARE1_EN_RX_HI Assertion time setting for TSM_SPARE1_EN (RX) 16 8 read-write TSM_SPARE1_EN_RX_LO De-assertion time setting for TSM_SPARE1_EN (RX) 24 8 read-write TIMING45 TSM_TIMING45 0xE4 32 read-write 0xFFFFFFFF 0xFFFFFFFF TSM_SPARE2_EN_TX_HI Assertion time setting for TSM_SPARE2_EN (TX) 0 8 read-write TSM_SPARE2_EN_TX_LO De-assertion time setting for TSM_SPARE2_EN (TX) 8 8 read-write TSM_SPARE2_EN_RX_HI Assertion time setting for TSM_SPARE2_EN (RX) 16 8 read-write TSM_SPARE2_EN_RX_LO De-assertion time setting for TSM_SPARE2_EN (RX) 24 8 read-write TIMING46 TSM_TIMING46 0xE8 32 read-write 0xFFFFFFFF 0xFFFFFFFF TSM_SPARE3_EN_TX_HI Assertion time setting for TSM_SPARE3_EN (TX) 0 8 read-write TSM_SPARE3_EN_TX_LO De-assertion time setting for TSM_SPARE3_EN (TX) 8 8 read-write TSM_SPARE3_EN_RX_HI Assertion time setting for TSM_SPARE3_EN (RX) 16 8 read-write TSM_SPARE3_EN_RX_LO De-assertion time setting for TSM_SPARE3_EN (RX) 24 8 read-write TIMING47 TSM_TIMING47 0xEC 32 read-write 0xFFFFFFFF 0xFFFFFFFF GPIO0_TRIG_EN_TX_HI Assertion time setting for GPIO0_TRIG_EN (TX) 0 8 read-write GPIO0_TRIG_EN_TX_LO De-assertion time setting for GPIO0_TRIG_EN (TX) 8 8 read-write GPIO0_TRIG_EN_RX_HI Assertion time setting for GPIO0_TRIG_EN (RX) 16 8 read-write GPIO0_TRIG_EN_RX_LO De-assertion time setting for GPIO0_TRIG_EN (RX) 24 8 read-write TIMING48 TSM_TIMING48 0xF0 32 read-write 0xFFFFFFFF 0xFFFFFFFF GPIO1_TRIG_EN_TX_HI Assertion time setting for GPIO1_TRIG_EN (TX) 0 8 read-write GPIO1_TRIG_EN_TX_LO De-assertion time setting for GPIO1_TRIG_EN (TX) 8 8 read-write GPIO1_TRIG_EN_RX_HI Assertion time setting for GPIO1_TRIG_EN (RX) 16 8 read-write GPIO1_TRIG_EN_RX_LO De-assertion time setting for GPIO1_TRIG_EN (RX) 24 8 read-write TIMING49 TSM_TIMING49 0xF4 32 read-write 0xFFFFFFFF 0xFFFFFFFF GPIO2_TRIG_EN_TX_HI Assertion time setting for GPIO2_TRIG_EN (TX) 0 8 read-write GPIO2_TRIG_EN_TX_LO De-assertion time setting for GPIO2_TRIG_EN (TX) 8 8 read-write GPIO2_TRIG_EN_RX_HI Assertion time setting for GPIO2_TRIG_EN (RX) 16 8 read-write GPIO2_TRIG_EN_RX_LO De-assertion time setting for GPIO2_TRIG_EN (RX) 24 8 read-write TIMING50 TSM_TIMING50 0xF8 32 read-write 0xFFFFFFFF 0xFFFFFFFF GPIO3_TRIG_EN_TX_HI Assertion time setting for GPIO3_TRIG_EN (TX) 0 8 read-write GPIO3_TRIG_EN_TX_LO De-assertion time setting for GPIO3_TRIG_EN (TX) 8 8 read-write GPIO3_TRIG_EN_RX_HI Assertion time setting for GPIO3_TRIG_EN (RX) 16 8 read-write GPIO3_TRIG_EN_RX_LO De-assertion time setting for GPIO3_TRIG_EN (RX) 24 8 read-write TIMING51 TSM_TIMING51 0xFC 32 read-write 0x6703FFFF 0xFFFFFFFF RXTX_AUXPLL_BIAS_EN_RX_HI Assertion time setting for RXTX_AUXPLL_BIAS_EN (RX) 16 8 read-write RXTX_AUXPLL_BIAS_EN_RX_LO De-assertion time setting for RXTX_AUXPLL_BIAS_EN (RX) 24 8 read-write TIMING52 TSM_TIMING52 0x100 32 read-write 0x1504FFFF 0xFFFFFFFF RXTX_AUXPLL_FCAL_EN_RX_HI Assertion time setting for RXTX_AUXPLL_FCAL_EN (RX) 16 8 read-write RXTX_AUXPLL_FCAL_EN_RX_LO De-assertion time setting for RXTX_AUXPLL_FCAL_EN (RX) 24 8 read-write TIMING53 TSM_TIMING53 0x104 32 read-write 0x6704FFFF 0xFFFFFFFF RXTX_AUXPLL_LF_PD_EN_RX_HI Assertion time setting for RXTX_AUXPLL_LF_PD_EN (RX) 16 8 read-write RXTX_AUXPLL_LF_PD_EN_RX_LO De-assertion time setting for RXTX_AUXPLL_LF_PD_EN (RX) 24 8 read-write TIMING54 TSM_TIMING54 0x108 32 read-write 0x1504FFFF 0xFFFFFFFF RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI Assertion time setting for RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN (RX) 16 8 read-write RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO De-assertion time setting for RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN (RX) 24 8 read-write TIMING55 TSM_TIMING55 0x10C 32 read-write 0x671EFFFF 0xFFFFFFFF RXTX_AUXPLL_ADC_BUF_EN_RX_HI Assertion time setting for RXTX_AUXPLL_ADC_BUF_EN (RX) 16 8 read-write RXTX_AUXPLL_ADC_BUF_EN_RX_LO De-assertion time setting for RXTX_AUXPLL_ADC_BUF_EN (RX) 24 8 read-write TIMING56 TSM_TIMING56 0x110 32 read-write 0x671EFFFF 0xFFFFFFFF RXTX_AUXPLL_DIG_BUF_EN_RX_HI Assertion time setting for RXTX_AUXPLL_DIG_BUF_EN (RX) 16 8 read-write RXTX_AUXPLL_DIG_BUF_EN_RX_LO De-assertion time setting for RXTX_AUXPLL_DIG_BUF_EN (RX) 24 8 read-write TIMING57 TSM_TIMING57 0x114 32 read-write 0x1A03FFFF 0xFFFFFFFF RXTX_RCCAL_EN_RX_HI Assertion time setting for RXTX_RCCAL_EN (RX) 16 8 read-write RXTX_RCCAL_EN_RX_LO De-assertion time setting for RXTX_RCCAL_EN (RX) 24 8 read-write TIMING58 TSM_TIMING58 0x118 32 read-write 0xFFFF6A03 0xFFFFFFFF TX_HPM_DAC_EN_TX_HI Assertion time setting for TX_HPM_DAC_EN (TX) 0 8 read-write TX_HPM_DAC_EN_TX_LO De-assertion time setting for TX_HPM_DAC_EN (TX) 8 8 read-write XCVR_PHY_REGS XCVR_PHY 0x4005C400 0 0x34 registers PHY_PRE_REF0 PREAMBLE REFERENCE WAVEFORM 0 0 32 read-write 0xFDDDEB39 0xFFFFFFFF FSK_PREAMBLE_REF0 Base preamble reference waveform containing sixteen 5-bit phase values 0 32 read-write PRE_REF1 PREAMBLE REFERENCE WAVEFORM 1 0x4 32 read-write 0xBEFBFFFF 0xFFFFFFFF FSK_PREAMBLE_REF1 Base preamble reference waveform containing sixteen 5-bit phase values 0 32 read-write PRE_REF2 PREAMBLE REFERENCE WAVEFORM 2 0x8 32 read-write 0xCE75 0xFFFFFFFF FSK_PREAMBLE_REF2 Base preamble reference waveform containing sixteen 5-bit phase values 0 16 read-write CFG1 PHY CONFIGURATION REGISTER 1 0x20 32 read-write 0x1070CD16 0xFFFFFFFF AA_PLAYBACK Access Address Playback 1 1 read-write AA_OUTPUT_SEL Access Address Output Select 2 1 read-write 0 demodulated #0 1 matched #1 FSK_BIT_INVERT FSK Bit Invert 3 1 read-write RFU00 Reserved for future use. 4 1 read-write BSM_EN_BLE BLE Bit Streaming Mode Enable bit 5 1 read-write 0 BSM for BLE disabled #0 1 BSM for BLE enabled #1 DEMOD_CLK_MODE Demodulator Clock Mode 6 2 read-write 0 Normal #00 1 Demodulate all samples #01 CTS_THRESH CTS (Coarse Timing Search) Correlation Threshold 8 8 read-write FSK_FTS_TIMEOUT FSK FTS Timeout 20 3 read-write 0 4 symbols #000 1 5 symbols #001 2 6 symbols #010 3 7 symbols #011 4 8 symbols #100 5 9 symbols #101 6 10 symbols #110 7 11 symbols #111 RFU01 Reserved for future use. 24 1 read-write RFU02 Reserved for future use. 25 1 read-write BLE_NTW_ADR_THR BLE Network Address Match Bit Error Threshold 28 3 read-write CFG2 PHY CONFIGURATION REGISTER 2 0x24 32 read-write 0x1000A48 0xFFFFFFFF PHY_FIFO_PRECHG PHY FIFO Precharge Level 0 4 read-write RFU03 Reserved for future use. 4 1 read-write RFU04 Reserved for future use. 5 1 read-write RFU05 Reserved for future use. 6 1 read-write RFU06 Reserved for future use. 7 1 read-write X2_DEMOD_GAIN X2_DEMOD_GAIN 8 4 read-write RFU07 Reserved for future use. 16 1 read-write RFU08 Reserved for future use. 17 1 read-write RFU09 Reserved for future use. 18 1 read-write RFU10 Reserved for future use. 19 1 read-write RFU11 Reserved for future use. 20 1 read-write RFU12 Reserved for future use. 21 1 read-write RFU13 Reserved for future use. 22 1 read-write RFU14 Reserved for future use. 23 1 read-write RFU15 Reserved for future use. 24 1 read-write RFU16 Reserved for future use. 25 1 read-write PHY_CLK_ON Force PHY Clock On (testmode) 31 1 read-write 0 PHY clock is enabled by TSM output: rx_phy_en #0 1 PHY clock is forced on at all times #1 EL_CFG PHY EARLY/LATE CONFIGURATION REGISTER 0x28 32 read-write 0 0xFFFFFFFF EL_ENABLE EL_ENABLE 0 1 read-write 0 Disable Early/Late #0 1 Enable Early/Late #1 EL_ZB_ENABLE EL_ZB_ENABLE 1 1 read-write 0 Disable Early/Late #0 1 Enable Early/Late #1 EL_ZB_WIN_SIZE EL_ZB_WIN_SIZE 2 1 read-write 0 2 symbols #0 1 3 symbols #1 EL_WIN_SIZE EL_WIN_SIZE 8 4 read-write EL_INTERVAL EL_INTERVAL 16 6 read-write NTW_ADR_BSM PHY NETWORK ADDRESS FOR BSM 0x2C 32 read-write 0 0xFFFFFFFF NTW_ADR_BSM NTW_ADR_BSM 0 32 read-write STATUS PHY STATUS REGISTER 0x30 32 read-only 0 0xFFFFFFFF PREAMBLE_FOUND Preamble Found 0 1 read-only AA_SFD_MATCHED Access Address or SFD Found 1 1 read-only AA_MATCHED Access Address Matched 4 4 read-only 0000 No Network Address has matched #0000 0001 Network Address 0 has matched #0001 0010 Network Address 1 has matched #0010 0100 Network Address 2 has matched #0100 1000 Network Address 3 has matched #1000 HAMMING_DISTANCE HAMMING DISTANCE 8 3 read-only DATA_FIFO_DEPTH DATA FIFO DEPTH 12 4 read-only CFO_ESTIMATE Carrier Frequency Offset Estimate 16 8 read-only XCVR_ZBDEMOD_REGS XCVR_ZBDEMOD 0x4005C480 0 0x1C registers CORR_CTRL 802.15.4 DEMOD CORRELLATOR CONTROL 0 32 read-write 0x482 0xFFFF CORR_VT CORR_VT 0 8 read-write CORR_NVAL CORR_NVAL 8 3 read-write MAX_CORR_EN MAX_CORR_EN 11 1 read-write ZBDEM_CLK_ON Force 802.15.4 Demodulator Clock On 15 1 read-write 0 Normal Operation #0 1 Force 802.15.4 Demodulator Clock On (debug purposes only) #1 RX_MAX_CORR RX_MAX_CORR 16 8 read-only RX_MAX_PREAMBLE RX_MAX_PREAMBLE 24 8 read-only PN_TYPE 802.15.4 DEMOD PN TYPE 0x4 32 read-write 0x1 0xFFFFFFFF PN_TYPE PN_TYPE 0 1 read-write TX_INV TX_INV 1 1 read-write PN_CODE 802.15.4 DEMOD PN CODE 0x8 32 read-write 0x744AC39B 0xFFFFFFFF PN_LSB PN_LSB 0 16 read-write PN_MSB PN_MSB 16 16 read-write SYNC_CTRL 802.15.4 DEMOD SYMBOL SYNC CONTROL 0xC 32 read-write 0x8 0xFFFFFFFF SYNC_PER Symbol Sync Tracking Period 0 3 read-write TRACK_ENABLE TRACK_ENABLE 3 1 read-write 0 symbol timing synchronization tracking disabled in Rx frontend #0 1 symbol timing synchronization tracking enabled in Rx frontend (default) #1 CCA_LQI_SRC 802.15.4 CCA/LQI SOURCE 0x10 32 read-write 0x4 0xFFFFFFFF CCA1_FROM_RX_DIG Selects the Source of CCA1 (Clear Channel Assessment Mode 1) Information Provided to the 802.15.4 Link Layer 0 1 read-write 0 Use the CCA1 information computed internally in the 802.15.4 Demod #0 1 Use the CCA1 information computed by the RX Digital #1 LQI_FROM_RX_DIG Selects the Source of LQI (Link Quality Indicator) Information Provided to the 802.15.4 Link Layer 1 1 read-write 0 Use the LQI information computed internally in the 802.15.4 Demod #0 1 Use the LQI information computed by the RX Digital #1 LQI_START_AT_SFD Select Start Point for LQI Computation 2 1 read-write 0 Start LQI computation at Preamble Detection (similar to previous Freescale 802.15.4 products) #0 1 Start LQI computation at SFD (Start of Frame Delimiter) Detection #1 FAD_THR FAD CORRELATOR THRESHOLD 0x14 32 read-write 0x82 0xFFFFFFFF FAD_THR FAD_THR 0 8 read-write ZBDEM_AFC 802.15.4 AFC STATUS 0x18 32 read-write 0x1 0xFFFFE0FF AFC_EN AFC_EN 0 1 read-write 0 AFC is disabled #0 1 AFC is enabled #1 DCD_EN DCD_EN 1 1 read-write 0 NCD Mode (default) #0 1 DCD Mode #1 AFC_OUT AFC_OUT 8 5 read-only XCVR_ANALOG_REGS XCVR_ANALOG 0x4005C500 0 0x38 registers BB_LDO_1 RF Analog Baseband LDO Control 1 0 32 read-write 0 0xFFFFFFFF BB_LDO_ADCDAC_BYP rmap_bb_ldo_adcdac_byp 0 1 read-write 0 Bypass disabled. #0 1 Bypass enabled #1 BB_LDO_ADCDAC_DIAGSEL rmap_bb_ldo_adcdac_diagsel 1 1 read-write 0 Diag disable #0 1 Diag enable #1 BB_LDO_ADCDAC_SPARE rmap_bb_ldo_adcdac_spare[1:0] 2 2 read-write BB_LDO_ADCDAC_TRIM rmap_bb_ldo_adcdac_trim[2:0] 4 3 read-write 000 1.20 V ( Default ) #000 001 1.25 V #001 010 1.28 V #010 011 1.33 V #011 100 1.40 V #100 101 1.44 V #101 110 1.50 V #110 111 1.66 V #111 BB_LDO_BBA_BYP rmap_bb_ldo_bba_byp 8 1 read-write 0 Bypass disabled. #0 1 Bypass enabled #1 BB_LDO_BBA_DIAGSEL rmap_bb_ldo_bba_diagsel 9 1 read-write 0 Diag disable #0 1 Diag enable #1 BB_LDO_BBA_SPARE rmap_bb_ldo_bba_spare[1:0] 10 2 read-write BB_LDO_BBA_TRIM rmap_bb_ldo_bba_trim[2:0] 12 3 read-write 0 1.20 V ( Default ) #000 1 1.25 V #001 2 1.28 V #010 3 1.33 V #011 4 1.40 V #100 5 1.44 V #101 6 1.50 V #110 7 1.66 V #111 BB_LDO_FDBK_BYP rmap_bb_ldo_fdbk_byp 16 1 read-write 0 Bypass disabled. #0 1 Bypass enabled #1 BB_LDO_FDBK_DIAGSEL rmap_bb_ldo_fdbk_diagsel 17 1 read-write 0 Diag disable #0 1 Diag enable #1 BB_LDO_FDBK_SPARE rmap_bb_ldo_fdbk_spare[1:0] 18 2 read-write BB_LDO_FDBK_TRIM rmap_bb_ldo_fdbk_trim[2:0] 20 3 read-write 0 1.2/1.176 V ( Default ) #000 1 1.138/1.115 V #001 2 1.085/1.066 V #010 3 1.04/1.025 V #011 4 1.28/1.25 V #100 5 1.4/1.35 V #101 6 1.55/1.4 V #110 7 1.78/1.4 V #111 BB_LDO_HF_BYP rmap_bb_ldo_hf_byp 24 1 read-write 0 Bypass disabled. #0 1 Bypass enabled #1 BB_LDO_HF_DIAGSEL rmap_bb_ldo_hf_diagsel 25 1 read-write 0 Diag disable #0 1 Diag enable #1 BB_LDO_HF_SPARE rmap_bb_ldo_hf_spare[1:0] 26 2 read-write BB_LDO_HF_TRIM rmap_bb_ldo_hf_trim[2:0] 28 3 read-write 0 1.20 V ( Default ) #000 1 1.25 V #001 2 1.28 V #010 3 1.33 V #011 4 1.40 V #100 5 1.44 V #101 6 1.50 V #110 7 1.66 V #111 BB_LDO_2 RF Analog Baseband LDO Control 2 0x4 32 read-write 0 0xFFFFFFFF BB_LDO_PD_BYP rmap_bb_ldo_pd_byp 0 1 read-write 0 Bypass disabled. #0 1 Bypass enabled #1 BB_LDO_PD_DIAGSEL rmap_bb_ldo_pd_diagsel 1 1 read-write 0 Diag disable #0 1 Diag enable #1 BB_LDO_PD_SPARE rmap_bb_ldo_pd_spare[1:0] 2 2 read-write BB_LDO_PD_TRIM rmap_bb_ldo_pd_trim[2:0] 4 3 read-write 0 1.20 V ( Default ) #000 1 1.25 V #001 2 1.28 V #010 3 1.33 V #011 4 1.40 V #100 5 1.44 V #101 6 1.50 V #110 7 1.66 V #111 BB_LDO_VCO_SPARE rmap_bb_ldo_vco_spare[1:0] 8 2 read-write BB_LDO_VCOLO_BYP rmap_bb_ldo_vcolo_byp 10 1 read-write 0 Bypass disabled. #0 1 Bypass enabled #1 BB_LDO_VCOLO_DIAGSEL rmap_bb_ldo_vcolo_diagsel 11 1 read-write 0 Diag disable #0 1 Diag enable #1 BB_LDO_VCOLO_TRIM rmap_bb_ldo_vcolo_trim[2:0] 12 3 read-write 0 1.138/1.117 V ( Default ) #000 1 1.076/1.058 V #001 2 1.027/1.012 V #010 3 0.98/0.97 V #011 4 1.22/1.19 V #100 5 1.33/1.3 V #101 6 1.5/1.4 V #110 7 1.82/1.4 V #111 BB_LDO_VTREF_DIAGSEL rmap_bb_ldo_vtref_diagsel 16 1 read-write 0 Diag disable #0 1 Diag enable #1 BB_LDO_VTREF_TC rmap_bb_ldo_vtref_tc[1:0] 17 2 read-write 0 1.117/1.176 V #00 1 1.134/1.188 V #01 2 1.10/1.162 V #10 3 1.09/1.152 V #11 RX_ADC RF Analog ADC Control 0x8 32 read-write 0x140 0xFFFFFFFF RX_ADC_BUMP rmap_rx_adc_bump[7:0] 0 8 read-write RX_ADC_FS_SEL rmap_rx_adc_fs_sel[1:0] 8 2 read-write 0 52MHz (2x26MHz) #00 1 64MHz (2x32MHz) #01 2 +13% of 64MHz #10 3 - 11% of 64MHz #11 RX_ADC_I_DIAGSEL rmap_rx_adc_i_diagsel 10 1 read-write RX_ADC_Q_DIAGSEL rmap_rx_adc_q_diagsel 11 1 read-write RX_ADC_SPARE rmap_rx_adc_spare[3:0] 12 4 read-write RX_BBA RF Analog BBA Control 0xC 32 read-write 0x3000003 0xFFFFFFFF RX_BBA_BW_SEL rmap_rx_bba_bw_sel[2:0] 0 3 read-write 000 1000K #000 001 900K #001 010 800K #010 011 700K Default #011 100 600K #100 101 500K #101 RX_BBA_CUR_BUMP rmap_rx_bba_cur_bump 3 1 read-write RX_BBA_DIAGSEL1 rmap_rx_bba_diagsel1 4 1 read-write 0 Diag disable #0 1 Diag enable #1 RX_BBA_DIAGSEL2 rmap_rx_bba_diagsel2 5 1 read-write 0 Diag disable #0 1 Diag enable #1 RX_BBA_DIAGSEL3 rmap_rx_bba_diagsel3 6 1 read-write 0 Diag disable #0 1 Diag enable #1 RX_BBA_DIAGSEL4 rmap_rx_bba_diagsel4 7 1 read-write 0 Diag disable #0 1 Diag enable #1 RX_BBA_SPARE rmap_rx_bba_spare[5:0] 16 6 read-write 00 600mV (Default) #0 01 675mV #1 10 450mV #10 11 525mV #11 RX_BBA2_BW_SEL rmap_bba2_bw_sel[2:0] 24 3 read-write 000 1000K #000 001 900K #001 010 800K #010 011 700K Default #011 100 600K #100 101 500K #101 RX_BBA2_SPARE rmap_rx_bba2_spare[2:0] 28 3 read-write RX_LNA RF Analog LNA Control 0x10 32 read-write 0 0xFFFFFFFF RX_LNA_BUMP rmap_rx_lna_bump[3:0] 0 4 read-write 0 Default #0000 1 -25% #0001 2 +50% #0010 3 +25% #0011 4 CM 480mV #0100 8 CM 600mV #1000 12 CM 660mV #1100 RX_LNA_HG_DIAGSEL rmap_rx_lna_hg_diagsel 4 1 read-write RX_LNA_HIZ_ENABLE rmap_rx_lna_hiZ_enable 5 1 read-write RX_LNA_LG_DIAGSEL rmap_rx_lna_lg_diagsel 6 1 read-write RX_LNA_SPARE rmap_rx_lna_spare[1:0] 8 2 read-write RX_MIXER_BUMP rmap_rx_mixer_bump[3:0] 16 4 read-write 0 825mV (Default) #0000 1 750mV #0001 2 900mV #0010 3 975mV #0011 RX_MIXER_SPARE rmap_rx_mixer_spare 20 1 read-write RX_TZA RF Analog TZA Control 0x14 32 read-write 0x3 0xFFFFFFFF RX_TZA_BW_SEL rmap_rx_tza_bw_sel[2:0] 0 3 read-write 000 1000K #000 001 900K #001 010 800K #010 011 700K Default #011 100 600K #100 101 500K #101 RX_TZA_CUR_BUMP rmap_rx_tza_cur_bump 3 1 read-write RX_TZA_GAIN_BUMP rmap_rx_tza_gain_bump 4 1 read-write RX_TZA_SPARE rmap_rx_tza_spare[5:0] 16 6 read-write 00 600mV (Default) #0 01 675mV #1 10 450mV #10 11 525mV #11 RX_TZA1_DIAGSEL rmap_rx_tza1_diagsel 24 1 read-write 0 Diag disable #0 1 Diag enable #1 RX_TZA2_DIAGSEL rmap_rx_tza2_diagsel 25 1 read-write 0 Diag disable #0 1 Diag enable #1 RX_TZA3_DIAGSEL rmap_rx_tza3_diagsel 26 1 read-write 0 Diag disable #0 1 Diag enable #1 RX_TZA4_DIAGSEL rmap_rx_tza4_diagsel 27 1 read-write 0 Diag disable #0 1 Diag enable #1 RX_AUXPLL RF Analog Aux PLL Control 0x18 32 read-write 0x9002 0xFFFFFFFF BIAS_TRIM rmap_rxtx_auxpll_bias_trim[2:0] 0 3 read-write DIAGSEL1 rmap_rxtx_auxpll_diagsel1 3 1 read-write DIAGSEL2 rmap_rxtx_auxpll_diagsel2 4 1 read-write LF_CNTL rmap_rxtx_auxpll_lf_cntl[2:0] 5 3 read-write SPARE rmap_rxtx_auxpll_spare[3:0] 8 4 read-write VCO_DAC_REF_ADJUST rmap_rxtx_auxpll_vco_dac_ref_adjust[3:0] 12 4 read-write VTUNE_TESTMODE rmap_rxtx_auxpll_vtune_testmode 16 1 read-write RXTX_BAL_BIAST rmap_rxtx_bal_biast[1:0] 20 2 read-write 0 0.6 #00 1 0.4 #01 2 0.9 #10 3 1.2 #11 RXTX_BAL_SPARE rmap_rxtx_bal_spare[2:0] 24 3 read-write RXTX_RCCAL_DIAGSEL rmap_rxtx_rccal_diagsel 28 1 read-write SY_CTRL_1 RF Analog Synthesizer Control 1 0x1C 32 read-write 0x150 0xFFFFFFFF SY_DIVN_SPARE rmap_sy_divn_spare 0 1 read-write SY_FCAL_SPARE rmap_sy_fcal_spare 1 1 read-write SY_LO_BUMP_RTLO_FDBK rmap_sy_lo_bump_rtlo_fdbk[1:0] 4 2 read-write 0 1.045 V #00 1 1.084 V #01 2 1.097 V #10 3 1.10 V #11 SY_LO_BUMP_RTLO_RX rmap_sy_lo_bump_rtlo_rx[1:0] 6 2 read-write 0 1.051/1.037 V #00 1 1.082/1.075 V #01 2 1.092/1.088 V #10 3 1.098/1.094 V #11 SY_LO_BUMP_RTLO_TX rmap_sy_lo_bump_rtlo_tx[1:0] 8 2 read-write 0 1.071/1.065 V #00 1 1.092/1.090 V #01 2 1.099/1.098 V #10 3 1.10/1.1 V #11 SY_LO_DIAGSEL rmap_sy_lo_diagsel 10 1 read-write 0 Diag disable #0 1 Diag enable #1 SY_LO_SPARE rmap_sy_lo_spare[2:0] 12 3 read-write SY_LPF_FILT_CTRL rmap_sy_lpf_filt_ctrl[2:0] 16 3 read-write SY_LPF_SPARE rmap_sy_lpf_spare 19 1 read-write SY_PD_DIAGSEL rmap_sy_pd_diagsel 20 1 read-write SY_PD_PCH_TUNE rmap_sy_pd_pch_tune[1:0] 21 2 read-write SY_PD_PCH_SEL rmap_sy_pd_pch_sel 23 1 read-write 0 inverter based precharge #0 1 resistor divider based precharge #1 SY_PD_SPARE rmap_sy_pd_spare[1:0] 24 2 read-write 0 Default ; #00 1 PD output is pulled down. #01 SY_PD_VTUNE_OVERRIDE_TEST_MODE rmap_sy_pd_vtune_override_test_mode 28 1 read-write SY_CTRL_2 RF Analog Synthesizer Control 2 0x20 32 read-write 0x14 0xFFFFFFFF SY_VCO_BIAS rmap_sy_vco_bias[2:0] 0 3 read-write 0 0.97V #000 1 1.033V #001 2 1.06V #010 3 1.07V #011 4 1.08V #100 5 1.085V #101 6 1.090V #110 7 1.095V #111 SY_VCO_DIAGSEL rmap_sy_vco_diagsel 3 1 read-write 1 Diag enable #1 0 Diag disable #0 SY_VCO_KV rmap_sy_vco_kv[2:0] 4 3 read-write 0 50MHz/V #000 1 60MHz/V #001 2 70MHz/V #010 3 80MHz/V #011 4 80MHz/V #100 5 80MHz/V #101 6 80MHz/V #110 7 80MHz/V #111 SY_VCO_KVM rmap_sy_vco_kvm[2:0] 8 3 read-write 0 10MHz/V #000 1 20MHz/V #001 2 30MHz/V #010 3 40MHz/V #011 4 40MHz/V #100 5 40MHz/V #101 6 40MHz/V #110 7 40MHz/V #111 SY_VCO_PK_DET_ON rmap_sy_vco_pk_det_on 12 1 read-write 1 Enable #1 0 Disable #0 SY_VCO_SPARE rmap_sy_vco_spare[2:0] 14 3 read-write TX_DAC_PA RF Analog TX HPM DAC and PA Control 0x24 32 read-write 0x20000 0xFFFFFFFF TX_DAC_BUMP_CAP rmap_tx_dac_bump_cap[1:0] 0 2 read-write 0 1pF(default) #00 1 1.5pF #01 2 1.5pF #10 3 2pF #11 TX_DAC_BUMP_IDAC rmap_tx_dac_bump_idac[1:0] 3 2 read-write 0 250nA(default) #00 1 207nA #01 2 312nA #10 3 415nA #11 TX_DAC_BUMP_RLOAD rmap_tx_dac_bump_rload[1:0] 6 2 read-write 0 3.12 kohms(default) #00 1 2.34 kohms #01 2 3.9 kohms #10 3 4.6 kohms #11 TX_DAC_DIAGSEL rmap_tx_dac_diagsel 9 1 read-write 0 Disable Diag #0 1 Enable Diag #1 TX_DAC_INVERT_CLK rmap_tx_dac_invert_clk 10 1 read-write TX_DAC_OPAMP_DIAGSEL rmap_tx_dac_opamp_diagsel 11 1 read-write 0 Disable Diag #0 1 Enable Diag #1 TX_DAC_SPARE rmap_tx_dac_spare[2:0] 13 3 read-write TX_PA_BUMP_VBIAS rmap_tx_pa_bump_vbias[2:0] 17 3 read-write 0 0.557 #000 1 0.651 #001 2 0.741 #010 3 0.822 #011 4 0.590 #100 5 0.683 #101 6 0.771 #110 7 0.850 #111 TX_PA_DIAGSEL rmap_tx_pa_diagsel 21 1 read-write TX_PA_SPARE rmap_tx_pa_spare[2:0] 23 3 read-write BALUN_TX RF Analog Balun TX Mode Control 0x28 32 read-write 0x724B6D 0xFFFFFFFF RXTX_BAL_TX_CODE Balun Tuning Cap Settings in Transmit Mode 0 24 read-write BALUN_RX RF Analog Balun RX Mode Control 0x2C 32 read-write 0x49372D 0xFFFFFFFF RXTX_BAL_RX_CODE Balun Tuning Cap Settings in Receive Mode 0 24 read-write DFT_OBSV_1 RF Analog DFT Observation Register 1 0x30 32 read-only 0 0xFFFFFFFF DFT_FREQ_COUNTER VCO Frequency Counter Value 0 19 read-only CTUNE_MAX_DIFF Maximum Frequency Count Difference found by the Coarse Tune BIST 20 8 read-only DFT_OBSV_2 RF Analog DFT Observation Register 2 0x34 32 read-write 0 0xFFFFFFFF SYN_BIST_MAX_DIFF PLL Frequency Synthesizer BIST Worst Frequency Count 0 17 read-only SYN_BIST_MAX_DIFF_CH PLL Frequency Synthesizer BIST Worst Channel 24 7 read-only SYN_BIST_IGNORE_FAILS PLL Frequency Synthesizer BIST Ignore Fails 31 1 read-write XCVR_PKT_RAM XCVR_PKT_RAM 0x4005C700 0 0x880 registers PACKET_RAM_0_0 Shared Packet RAM for multiple Link Layer usage. 0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_1 Shared Packet RAM for multiple Link Layer usage. 0x2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_2 Shared Packet RAM for multiple Link Layer usage. 0x4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_3 Shared Packet RAM for multiple Link Layer usage. 0x6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_4 Shared Packet RAM for multiple Link Layer usage. 0x8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_5 Shared Packet RAM for multiple Link Layer usage. 0xA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_6 Shared Packet RAM for multiple Link Layer usage. 0xC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_7 Shared Packet RAM for multiple Link Layer usage. 0xE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_8 Shared Packet RAM for multiple Link Layer usage. 0x10 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_9 Shared Packet RAM for multiple Link Layer usage. 0x12 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_10 Shared Packet RAM for multiple Link Layer usage. 0x14 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_11 Shared Packet RAM for multiple Link Layer usage. 0x16 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_12 Shared Packet RAM for multiple Link Layer usage. 0x18 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_13 Shared Packet RAM for multiple Link Layer usage. 0x1A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_14 Shared Packet RAM for multiple Link Layer usage. 0x1C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_15 Shared Packet RAM for multiple Link Layer usage. 0x1E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_16 Shared Packet RAM for multiple Link Layer usage. 0x20 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_17 Shared Packet RAM for multiple Link Layer usage. 0x22 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_18 Shared Packet RAM for multiple Link Layer usage. 0x24 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_19 Shared Packet RAM for multiple Link Layer usage. 0x26 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_20 Shared Packet RAM for multiple Link Layer usage. 0x28 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_21 Shared Packet RAM for multiple Link Layer usage. 0x2A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_22 Shared Packet RAM for multiple Link Layer usage. 0x2C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_23 Shared Packet RAM for multiple Link Layer usage. 0x2E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_24 Shared Packet RAM for multiple Link Layer usage. 0x30 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_25 Shared Packet RAM for multiple Link Layer usage. 0x32 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_26 Shared Packet RAM for multiple Link Layer usage. 0x34 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_27 Shared Packet RAM for multiple Link Layer usage. 0x36 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_28 Shared Packet RAM for multiple Link Layer usage. 0x38 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_29 Shared Packet RAM for multiple Link Layer usage. 0x3A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_30 Shared Packet RAM for multiple Link Layer usage. 0x3C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_31 Shared Packet RAM for multiple Link Layer usage. 0x3E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_32 Shared Packet RAM for multiple Link Layer usage. 0x40 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_33 Shared Packet RAM for multiple Link Layer usage. 0x42 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_34 Shared Packet RAM for multiple Link Layer usage. 0x44 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_35 Shared Packet RAM for multiple Link Layer usage. 0x46 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_36 Shared Packet RAM for multiple Link Layer usage. 0x48 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_37 Shared Packet RAM for multiple Link Layer usage. 0x4A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_38 Shared Packet RAM for multiple Link Layer usage. 0x4C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_39 Shared Packet RAM for multiple Link Layer usage. 0x4E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_40 Shared Packet RAM for multiple Link Layer usage. 0x50 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_41 Shared Packet RAM for multiple Link Layer usage. 0x52 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_42 Shared Packet RAM for multiple Link Layer usage. 0x54 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_43 Shared Packet RAM for multiple Link Layer usage. 0x56 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_44 Shared Packet RAM for multiple Link Layer usage. 0x58 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_45 Shared Packet RAM for multiple Link Layer usage. 0x5A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_46 Shared Packet RAM for multiple Link Layer usage. 0x5C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_47 Shared Packet RAM for multiple Link Layer usage. 0x5E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_48 Shared Packet RAM for multiple Link Layer usage. 0x60 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_49 Shared Packet RAM for multiple Link Layer usage. 0x62 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_50 Shared Packet RAM for multiple Link Layer usage. 0x64 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_51 Shared Packet RAM for multiple Link Layer usage. 0x66 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_52 Shared Packet RAM for multiple Link Layer usage. 0x68 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_53 Shared Packet RAM for multiple Link Layer usage. 0x6A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_54 Shared Packet RAM for multiple Link Layer usage. 0x6C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_55 Shared Packet RAM for multiple Link Layer usage. 0x6E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_56 Shared Packet RAM for multiple Link Layer usage. 0x70 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_57 Shared Packet RAM for multiple Link Layer usage. 0x72 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_58 Shared Packet RAM for multiple Link Layer usage. 0x74 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_59 Shared Packet RAM for multiple Link Layer usage. 0x76 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_60 Shared Packet RAM for multiple Link Layer usage. 0x78 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_61 Shared Packet RAM for multiple Link Layer usage. 0x7A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_62 Shared Packet RAM for multiple Link Layer usage. 0x7C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_63 Shared Packet RAM for multiple Link Layer usage. 0x7E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_64 Shared Packet RAM for multiple Link Layer usage. 0x80 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_65 Shared Packet RAM for multiple Link Layer usage. 0x82 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_66 Shared Packet RAM for multiple Link Layer usage. 0x84 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_67 Shared Packet RAM for multiple Link Layer usage. 0x86 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_68 Shared Packet RAM for multiple Link Layer usage. 0x88 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_69 Shared Packet RAM for multiple Link Layer usage. 0x8A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_70 Shared Packet RAM for multiple Link Layer usage. 0x8C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_71 Shared Packet RAM for multiple Link Layer usage. 0x8E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_72 Shared Packet RAM for multiple Link Layer usage. 0x90 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_73 Shared Packet RAM for multiple Link Layer usage. 0x92 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_74 Shared Packet RAM for multiple Link Layer usage. 0x94 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_75 Shared Packet RAM for multiple Link Layer usage. 0x96 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_76 Shared Packet RAM for multiple Link Layer usage. 0x98 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_77 Shared Packet RAM for multiple Link Layer usage. 0x9A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_78 Shared Packet RAM for multiple Link Layer usage. 0x9C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_79 Shared Packet RAM for multiple Link Layer usage. 0x9E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_80 Shared Packet RAM for multiple Link Layer usage. 0xA0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_81 Shared Packet RAM for multiple Link Layer usage. 0xA2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_82 Shared Packet RAM for multiple Link Layer usage. 0xA4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_83 Shared Packet RAM for multiple Link Layer usage. 0xA6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_84 Shared Packet RAM for multiple Link Layer usage. 0xA8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_85 Shared Packet RAM for multiple Link Layer usage. 0xAA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_86 Shared Packet RAM for multiple Link Layer usage. 0xAC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_87 Shared Packet RAM for multiple Link Layer usage. 0xAE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_88 Shared Packet RAM for multiple Link Layer usage. 0xB0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_89 Shared Packet RAM for multiple Link Layer usage. 0xB2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_90 Shared Packet RAM for multiple Link Layer usage. 0xB4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_91 Shared Packet RAM for multiple Link Layer usage. 0xB6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_92 Shared Packet RAM for multiple Link Layer usage. 0xB8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_93 Shared Packet RAM for multiple Link Layer usage. 0xBA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_94 Shared Packet RAM for multiple Link Layer usage. 0xBC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_95 Shared Packet RAM for multiple Link Layer usage. 0xBE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_96 Shared Packet RAM for multiple Link Layer usage. 0xC0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_97 Shared Packet RAM for multiple Link Layer usage. 0xC2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_98 Shared Packet RAM for multiple Link Layer usage. 0xC4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_99 Shared Packet RAM for multiple Link Layer usage. 0xC6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_100 Shared Packet RAM for multiple Link Layer usage. 0xC8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_101 Shared Packet RAM for multiple Link Layer usage. 0xCA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_102 Shared Packet RAM for multiple Link Layer usage. 0xCC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_103 Shared Packet RAM for multiple Link Layer usage. 0xCE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_104 Shared Packet RAM for multiple Link Layer usage. 0xD0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_105 Shared Packet RAM for multiple Link Layer usage. 0xD2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_106 Shared Packet RAM for multiple Link Layer usage. 0xD4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_107 Shared Packet RAM for multiple Link Layer usage. 0xD6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_108 Shared Packet RAM for multiple Link Layer usage. 0xD8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_109 Shared Packet RAM for multiple Link Layer usage. 0xDA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_110 Shared Packet RAM for multiple Link Layer usage. 0xDC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_111 Shared Packet RAM for multiple Link Layer usage. 0xDE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_112 Shared Packet RAM for multiple Link Layer usage. 0xE0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_113 Shared Packet RAM for multiple Link Layer usage. 0xE2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_114 Shared Packet RAM for multiple Link Layer usage. 0xE4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_115 Shared Packet RAM for multiple Link Layer usage. 0xE6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_116 Shared Packet RAM for multiple Link Layer usage. 0xE8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_117 Shared Packet RAM for multiple Link Layer usage. 0xEA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_118 Shared Packet RAM for multiple Link Layer usage. 0xEC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_119 Shared Packet RAM for multiple Link Layer usage. 0xEE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_120 Shared Packet RAM for multiple Link Layer usage. 0xF0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_121 Shared Packet RAM for multiple Link Layer usage. 0xF2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_122 Shared Packet RAM for multiple Link Layer usage. 0xF4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_123 Shared Packet RAM for multiple Link Layer usage. 0xF6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_124 Shared Packet RAM for multiple Link Layer usage. 0xF8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_125 Shared Packet RAM for multiple Link Layer usage. 0xFA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_126 Shared Packet RAM for multiple Link Layer usage. 0xFC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_127 Shared Packet RAM for multiple Link Layer usage. 0xFE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_128 Shared Packet RAM for multiple Link Layer usage. 0x100 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_129 Shared Packet RAM for multiple Link Layer usage. 0x102 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_130 Shared Packet RAM for multiple Link Layer usage. 0x104 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_131 Shared Packet RAM for multiple Link Layer usage. 0x106 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_132 Shared Packet RAM for multiple Link Layer usage. 0x108 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_133 Shared Packet RAM for multiple Link Layer usage. 0x10A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_134 Shared Packet RAM for multiple Link Layer usage. 0x10C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_135 Shared Packet RAM for multiple Link Layer usage. 0x10E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_136 Shared Packet RAM for multiple Link Layer usage. 0x110 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_137 Shared Packet RAM for multiple Link Layer usage. 0x112 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_138 Shared Packet RAM for multiple Link Layer usage. 0x114 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_139 Shared Packet RAM for multiple Link Layer usage. 0x116 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_140 Shared Packet RAM for multiple Link Layer usage. 0x118 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_141 Shared Packet RAM for multiple Link Layer usage. 0x11A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_142 Shared Packet RAM for multiple Link Layer usage. 0x11C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_143 Shared Packet RAM for multiple Link Layer usage. 0x11E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_144 Shared Packet RAM for multiple Link Layer usage. 0x120 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_145 Shared Packet RAM for multiple Link Layer usage. 0x122 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_146 Shared Packet RAM for multiple Link Layer usage. 0x124 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_147 Shared Packet RAM for multiple Link Layer usage. 0x126 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_148 Shared Packet RAM for multiple Link Layer usage. 0x128 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_149 Shared Packet RAM for multiple Link Layer usage. 0x12A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write 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read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_157 Shared Packet RAM for multiple Link Layer usage. 0x13A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_158 Shared Packet RAM for multiple Link Layer usage. 0x13C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_159 Shared Packet RAM for multiple Link Layer usage. 0x13E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_160 Shared Packet RAM for multiple Link Layer usage. 0x140 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_161 Shared Packet RAM for multiple Link Layer usage. 0x142 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_162 Shared Packet RAM for multiple Link Layer usage. 0x144 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_163 Shared Packet RAM for multiple Link Layer usage. 0x146 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for multiple Link Layer usage. 0x154 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_171 Shared Packet RAM for multiple Link Layer usage. 0x156 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_172 Shared Packet RAM for multiple Link Layer usage. 0x158 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_173 Shared Packet RAM for multiple Link Layer usage. 0x15A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_174 Shared Packet RAM for multiple Link Layer usage. 0x15C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_175 Shared Packet RAM for multiple Link Layer usage. 0x15E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_176 Shared Packet RAM for multiple Link Layer usage. 0x160 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write 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for multiple Link Layer usage. 0x1F6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_252 Shared Packet RAM for multiple Link Layer usage. 0x1F8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_253 Shared Packet RAM for multiple Link Layer usage. 0x1FA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_254 Shared Packet RAM for multiple Link Layer usage. 0x1FC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_255 Shared Packet RAM for multiple Link Layer usage. 0x1FE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_256 Shared Packet RAM for multiple Link Layer usage. 0x200 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_257 Shared Packet RAM for multiple Link Layer usage. 0x202 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write 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16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_272 Shared Packet RAM for multiple Link Layer usage. 0x220 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_273 Shared Packet RAM for multiple Link Layer usage. 0x222 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_274 Shared Packet RAM for multiple Link Layer usage. 0x224 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_275 Shared Packet RAM for multiple Link Layer usage. 0x226 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_276 Shared Packet RAM for multiple Link Layer usage. 0x228 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_277 Shared Packet RAM for multiple Link Layer usage. 0x22A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_278 Shared Packet RAM for multiple Link Layer usage. 0x22C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_279 Shared Packet RAM for multiple Link Layer usage. 0x22E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_280 Shared Packet RAM for multiple Link Layer usage. 0x230 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_281 Shared Packet RAM for multiple Link Layer usage. 0x232 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_282 Shared Packet RAM for multiple Link Layer usage. 0x234 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_283 Shared Packet RAM for multiple Link Layer usage. 0x236 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_284 Shared Packet RAM for multiple Link Layer usage. 0x238 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_285 Shared Packet RAM for multiple Link Layer usage. 0x23A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_286 Shared Packet RAM for multiple Link Layer usage. 0x23C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_287 Shared Packet RAM for multiple Link Layer usage. 0x23E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_288 Shared Packet RAM for multiple Link Layer usage. 0x240 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_289 Shared Packet RAM for multiple Link Layer usage. 0x242 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_290 Shared Packet RAM for multiple Link Layer usage. 0x244 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_291 Shared Packet RAM for multiple Link Layer usage. 0x246 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_292 Shared Packet RAM for multiple Link Layer usage. 0x248 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_293 Shared Packet RAM for multiple Link Layer usage. 0x24A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_294 Shared Packet RAM for multiple Link Layer usage. 0x24C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_295 Shared Packet RAM for multiple Link Layer usage. 0x24E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_296 Shared Packet RAM for multiple Link Layer usage. 0x250 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_297 Shared Packet RAM for multiple Link Layer usage. 0x252 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_298 Shared Packet RAM for multiple Link Layer usage. 0x254 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_299 Shared Packet RAM for multiple Link Layer usage. 0x256 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_300 Shared Packet RAM for multiple Link Layer usage. 0x258 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_301 Shared Packet RAM for multiple Link Layer usage. 0x25A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_302 Shared Packet RAM for multiple Link Layer usage. 0x25C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_303 Shared Packet RAM for multiple Link Layer usage. 0x25E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_304 Shared Packet RAM for multiple Link Layer usage. 0x260 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_305 Shared Packet RAM for multiple Link Layer usage. 0x262 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_306 Shared Packet RAM for multiple Link Layer usage. 0x264 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_307 Shared Packet RAM for multiple Link Layer usage. 0x266 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_308 Shared Packet RAM for multiple Link Layer usage. 0x268 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_309 Shared Packet RAM for multiple Link Layer usage. 0x26A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_310 Shared Packet RAM for multiple Link Layer usage. 0x26C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_311 Shared Packet RAM for multiple Link Layer usage. 0x26E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_312 Shared Packet RAM for multiple Link Layer usage. 0x270 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_313 Shared Packet RAM for multiple Link Layer usage. 0x272 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_314 Shared Packet RAM for multiple Link Layer usage. 0x274 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_315 Shared Packet RAM for multiple Link Layer usage. 0x276 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_316 Shared Packet RAM for multiple Link Layer usage. 0x278 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_317 Shared Packet RAM for multiple Link Layer usage. 0x27A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_318 Shared Packet RAM for multiple Link Layer usage. 0x27C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_319 Shared Packet RAM for multiple Link Layer usage. 0x27E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_320 Shared Packet RAM for multiple Link Layer usage. 0x280 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_321 Shared Packet RAM for multiple Link Layer usage. 0x282 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_322 Shared Packet RAM for multiple Link Layer usage. 0x284 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_323 Shared Packet RAM for multiple Link Layer usage. 0x286 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_324 Shared Packet RAM for multiple Link Layer usage. 0x288 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_325 Shared Packet RAM for multiple Link Layer usage. 0x28A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_326 Shared Packet RAM for multiple Link Layer usage. 0x28C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_327 Shared Packet RAM for multiple Link Layer usage. 0x28E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_328 Shared Packet RAM for multiple Link Layer usage. 0x290 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_329 Shared Packet RAM for multiple Link Layer usage. 0x292 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_330 Shared Packet RAM for multiple Link Layer usage. 0x294 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_331 Shared Packet RAM for multiple Link Layer usage. 0x296 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_332 Shared Packet RAM for multiple Link Layer usage. 0x298 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_333 Shared Packet RAM for multiple Link Layer usage. 0x29A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_334 Shared Packet RAM for multiple Link Layer usage. 0x29C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_335 Shared Packet RAM for multiple Link Layer usage. 0x29E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_336 Shared Packet RAM for multiple Link Layer usage. 0x2A0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_337 Shared Packet RAM for multiple Link Layer usage. 0x2A2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_338 Shared Packet RAM for multiple Link Layer usage. 0x2A4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_339 Shared Packet RAM for multiple Link Layer usage. 0x2A6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_340 Shared Packet RAM for multiple Link Layer usage. 0x2A8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_341 Shared Packet RAM for multiple Link Layer usage. 0x2AA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_342 Shared Packet RAM for multiple Link Layer usage. 0x2AC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_343 Shared Packet RAM for multiple Link Layer usage. 0x2AE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_344 Shared Packet RAM for multiple Link Layer usage. 0x2B0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_345 Shared Packet RAM for multiple Link Layer usage. 0x2B2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_346 Shared Packet RAM for multiple Link Layer usage. 0x2B4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_347 Shared Packet RAM for multiple Link Layer usage. 0x2B6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_348 Shared Packet RAM for multiple Link Layer usage. 0x2B8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_349 Shared Packet RAM for multiple Link Layer usage. 0x2BA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_350 Shared Packet RAM for multiple Link Layer usage. 0x2BC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_351 Shared Packet RAM for multiple Link Layer usage. 0x2BE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_352 Shared Packet RAM for multiple Link Layer usage. 0x2C0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_353 Shared Packet RAM for multiple Link Layer usage. 0x2C2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_354 Shared Packet RAM for multiple Link Layer usage. 0x2C4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_355 Shared Packet RAM for multiple Link Layer usage. 0x2C6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_356 Shared Packet RAM for multiple Link Layer usage. 0x2C8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_357 Shared Packet RAM for multiple Link Layer usage. 0x2CA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_358 Shared Packet RAM for multiple Link Layer usage. 0x2CC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_359 Shared Packet RAM for multiple Link Layer usage. 0x2CE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_360 Shared Packet RAM for multiple Link Layer usage. 0x2D0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_361 Shared Packet RAM for multiple Link Layer usage. 0x2D2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_362 Shared Packet RAM for multiple Link Layer usage. 0x2D4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_363 Shared Packet RAM for multiple Link Layer usage. 0x2D6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_364 Shared Packet RAM for multiple Link Layer usage. 0x2D8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_365 Shared Packet RAM for multiple Link Layer usage. 0x2DA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_366 Shared Packet RAM for multiple Link Layer usage. 0x2DC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_367 Shared Packet RAM for multiple Link Layer usage. 0x2DE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_368 Shared Packet RAM for multiple Link Layer usage. 0x2E0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_369 Shared Packet RAM for multiple Link Layer usage. 0x2E2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_370 Shared Packet RAM for multiple Link Layer usage. 0x2E4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_371 Shared Packet RAM for multiple Link Layer usage. 0x2E6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_372 Shared Packet RAM for multiple Link Layer usage. 0x2E8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_373 Shared Packet RAM for multiple Link Layer usage. 0x2EA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_374 Shared Packet RAM for multiple Link Layer usage. 0x2EC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_375 Shared Packet RAM for multiple Link Layer usage. 0x2EE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_376 Shared Packet RAM for multiple Link Layer usage. 0x2F0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_377 Shared Packet RAM for multiple Link Layer usage. 0x2F2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_378 Shared Packet RAM for multiple Link Layer usage. 0x2F4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_379 Shared Packet RAM for multiple Link Layer usage. 0x2F6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_380 Shared Packet RAM for multiple Link Layer usage. 0x2F8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_381 Shared Packet RAM for multiple Link Layer usage. 0x2FA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_382 Shared Packet RAM for multiple Link Layer usage. 0x2FC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_383 Shared Packet RAM for multiple Link Layer usage. 0x2FE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_384 Shared Packet RAM for multiple Link Layer usage. 0x300 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_385 Shared Packet RAM for multiple Link Layer usage. 0x302 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_386 Shared Packet RAM for multiple Link Layer usage. 0x304 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_387 Shared Packet RAM for multiple Link Layer usage. 0x306 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_388 Shared Packet RAM for multiple Link Layer usage. 0x308 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_389 Shared Packet RAM for multiple Link Layer usage. 0x30A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_390 Shared Packet RAM for multiple Link Layer usage. 0x30C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_391 Shared Packet RAM for multiple Link Layer usage. 0x30E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_392 Shared Packet RAM for multiple Link Layer usage. 0x310 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_393 Shared Packet RAM for multiple Link Layer usage. 0x312 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_394 Shared Packet RAM for multiple Link Layer usage. 0x314 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_395 Shared Packet RAM for multiple Link Layer usage. 0x316 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_396 Shared Packet RAM for multiple Link Layer usage. 0x318 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_397 Shared Packet RAM for multiple Link Layer usage. 0x31A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_398 Shared Packet RAM for multiple Link Layer usage. 0x31C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_399 Shared Packet RAM for multiple Link Layer usage. 0x31E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_400 Shared Packet RAM for multiple Link Layer usage. 0x320 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_401 Shared Packet RAM for multiple Link Layer usage. 0x322 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_402 Shared Packet RAM for multiple Link Layer usage. 0x324 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_403 Shared Packet RAM for multiple Link Layer usage. 0x326 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_404 Shared Packet RAM for multiple Link Layer usage. 0x328 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_405 Shared Packet RAM for multiple Link Layer usage. 0x32A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_406 Shared Packet RAM for multiple Link Layer usage. 0x32C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_407 Shared Packet RAM for multiple Link Layer usage. 0x32E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_408 Shared Packet RAM for multiple Link Layer usage. 0x330 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_409 Shared Packet RAM for multiple Link Layer usage. 0x332 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_410 Shared Packet RAM for multiple Link Layer usage. 0x334 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_411 Shared Packet RAM for multiple Link Layer usage. 0x336 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_412 Shared Packet RAM for multiple Link Layer usage. 0x338 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_413 Shared Packet RAM for multiple Link Layer usage. 0x33A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_414 Shared Packet RAM for multiple Link Layer usage. 0x33C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_415 Shared Packet RAM for multiple Link Layer usage. 0x33E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_416 Shared Packet RAM for multiple Link Layer usage. 0x340 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_417 Shared Packet RAM for multiple Link Layer usage. 0x342 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_418 Shared Packet RAM for multiple Link Layer usage. 0x344 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_419 Shared Packet RAM for multiple Link Layer usage. 0x346 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_420 Shared Packet RAM for multiple Link Layer usage. 0x348 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_421 Shared Packet RAM for multiple Link Layer usage. 0x34A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_422 Shared Packet RAM for multiple Link Layer usage. 0x34C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_423 Shared Packet RAM for multiple Link Layer usage. 0x34E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_424 Shared Packet RAM for multiple Link Layer usage. 0x350 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_425 Shared Packet RAM for multiple Link Layer usage. 0x352 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_426 Shared Packet RAM for multiple Link Layer usage. 0x354 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_427 Shared Packet RAM for multiple Link Layer usage. 0x356 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_428 Shared Packet RAM for multiple Link Layer usage. 0x358 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_429 Shared Packet RAM for multiple Link Layer usage. 0x35A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_430 Shared Packet RAM for multiple Link Layer usage. 0x35C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_431 Shared Packet RAM for multiple Link Layer usage. 0x35E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_432 Shared Packet RAM for multiple Link Layer usage. 0x360 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_433 Shared Packet RAM for multiple Link Layer usage. 0x362 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_434 Shared Packet RAM for multiple Link Layer usage. 0x364 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_435 Shared Packet RAM for multiple Link Layer usage. 0x366 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_436 Shared Packet RAM for multiple Link Layer usage. 0x368 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_437 Shared Packet RAM for multiple Link Layer usage. 0x36A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_438 Shared Packet RAM for multiple Link Layer usage. 0x36C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_439 Shared Packet RAM for multiple Link Layer usage. 0x36E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_440 Shared Packet RAM for multiple Link Layer usage. 0x370 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_441 Shared Packet RAM for multiple Link Layer usage. 0x372 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_442 Shared Packet RAM for multiple Link Layer usage. 0x374 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_443 Shared Packet RAM for multiple Link Layer usage. 0x376 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_444 Shared Packet RAM for multiple Link Layer usage. 0x378 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_445 Shared Packet RAM for multiple Link Layer usage. 0x37A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_446 Shared Packet RAM for multiple Link Layer usage. 0x37C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_447 Shared Packet RAM for multiple Link Layer usage. 0x37E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_448 Shared Packet RAM for multiple Link Layer usage. 0x380 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_449 Shared Packet RAM for multiple Link Layer usage. 0x382 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_450 Shared Packet RAM for multiple Link Layer usage. 0x384 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_451 Shared Packet RAM for multiple Link Layer usage. 0x386 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_452 Shared Packet RAM for multiple Link Layer usage. 0x388 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_453 Shared Packet RAM for multiple Link Layer usage. 0x38A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_454 Shared Packet RAM for multiple Link Layer usage. 0x38C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_455 Shared Packet RAM for multiple Link Layer usage. 0x38E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_456 Shared Packet RAM for multiple Link Layer usage. 0x390 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_457 Shared Packet RAM for multiple Link Layer usage. 0x392 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_458 Shared Packet RAM for multiple Link Layer usage. 0x394 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_459 Shared Packet RAM for multiple Link Layer usage. 0x396 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_460 Shared Packet RAM for multiple Link Layer usage. 0x398 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_461 Shared Packet RAM for multiple Link Layer usage. 0x39A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_462 Shared Packet RAM for multiple Link Layer usage. 0x39C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_463 Shared Packet RAM for multiple Link Layer usage. 0x39E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_464 Shared Packet RAM for multiple Link Layer usage. 0x3A0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_465 Shared Packet RAM for multiple Link Layer usage. 0x3A2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_466 Shared Packet RAM for multiple Link Layer usage. 0x3A4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_467 Shared Packet RAM for multiple Link Layer usage. 0x3A6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_468 Shared Packet RAM for multiple Link Layer usage. 0x3A8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_469 Shared Packet RAM for multiple Link Layer usage. 0x3AA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_470 Shared Packet RAM for multiple Link Layer usage. 0x3AC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_471 Shared Packet RAM for multiple Link Layer usage. 0x3AE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_472 Shared Packet RAM for multiple Link Layer usage. 0x3B0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_473 Shared Packet RAM for multiple Link Layer usage. 0x3B2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_474 Shared Packet RAM for multiple Link Layer usage. 0x3B4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_475 Shared Packet RAM for multiple Link Layer usage. 0x3B6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_476 Shared Packet RAM for multiple Link Layer usage. 0x3B8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_477 Shared Packet RAM for multiple Link Layer usage. 0x3BA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_478 Shared Packet RAM for multiple Link Layer usage. 0x3BC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_479 Shared Packet RAM for multiple Link Layer usage. 0x3BE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_480 Shared Packet RAM for multiple Link Layer usage. 0x3C0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_481 Shared Packet RAM for multiple Link Layer usage. 0x3C2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_482 Shared Packet RAM for multiple Link Layer usage. 0x3C4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_483 Shared Packet RAM for multiple Link Layer usage. 0x3C6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_484 Shared Packet RAM for multiple Link Layer usage. 0x3C8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_485 Shared Packet RAM for multiple Link Layer usage. 0x3CA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_486 Shared Packet RAM for multiple Link Layer usage. 0x3CC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_487 Shared Packet RAM for multiple Link Layer usage. 0x3CE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_488 Shared Packet RAM for multiple Link Layer usage. 0x3D0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_489 Shared Packet RAM for multiple Link Layer usage. 0x3D2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_490 Shared Packet RAM for multiple Link Layer usage. 0x3D4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_491 Shared Packet RAM for multiple Link Layer usage. 0x3D6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_492 Shared Packet RAM for multiple Link Layer usage. 0x3D8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_493 Shared Packet RAM for multiple Link Layer usage. 0x3DA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_494 Shared Packet RAM for multiple Link Layer usage. 0x3DC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_495 Shared Packet RAM for multiple Link Layer usage. 0x3DE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_496 Shared Packet RAM for multiple Link Layer usage. 0x3E0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_497 Shared Packet RAM for multiple Link Layer usage. 0x3E2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_498 Shared Packet RAM for multiple Link Layer usage. 0x3E4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_499 Shared Packet RAM for multiple Link Layer usage. 0x3E6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_500 Shared Packet RAM for multiple Link Layer usage. 0x3E8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_501 Shared Packet RAM for multiple Link Layer usage. 0x3EA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_502 Shared Packet RAM for multiple Link Layer usage. 0x3EC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_503 Shared Packet RAM for multiple Link Layer usage. 0x3EE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_504 Shared Packet RAM for multiple Link Layer usage. 0x3F0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_505 Shared Packet RAM for multiple Link Layer usage. 0x3F2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_506 Shared Packet RAM for multiple Link Layer usage. 0x3F4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_507 Shared Packet RAM for multiple Link Layer usage. 0x3F6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_508 Shared Packet RAM for multiple Link Layer usage. 0x3F8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_509 Shared Packet RAM for multiple Link Layer usage. 0x3FA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_510 Shared Packet RAM for multiple Link Layer usage. 0x3FC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_511 Shared Packet RAM for multiple Link Layer usage. 0x3FE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_512 Shared Packet RAM for multiple Link Layer usage. 0x400 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_513 Shared Packet RAM for multiple Link Layer usage. 0x402 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_514 Shared Packet RAM for multiple Link Layer usage. 0x404 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_515 Shared Packet RAM for multiple Link Layer usage. 0x406 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_516 Shared Packet RAM for multiple Link Layer usage. 0x408 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_517 Shared Packet RAM for multiple Link Layer usage. 0x40A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_518 Shared Packet RAM for multiple Link Layer usage. 0x40C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_519 Shared Packet RAM for multiple Link Layer usage. 0x40E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_520 Shared Packet RAM for multiple Link Layer usage. 0x410 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_521 Shared Packet RAM for multiple Link Layer usage. 0x412 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_522 Shared Packet RAM for multiple Link Layer usage. 0x414 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_523 Shared Packet RAM for multiple Link Layer usage. 0x416 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_524 Shared Packet RAM for multiple Link Layer usage. 0x418 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_525 Shared Packet RAM for multiple Link Layer usage. 0x41A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_526 Shared Packet RAM for multiple Link Layer usage. 0x41C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_527 Shared Packet RAM for multiple Link Layer usage. 0x41E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_528 Shared Packet RAM for multiple Link Layer usage. 0x420 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_529 Shared Packet RAM for multiple Link Layer usage. 0x422 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_530 Shared Packet RAM for multiple Link Layer usage. 0x424 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_531 Shared Packet RAM for multiple Link Layer usage. 0x426 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_532 Shared Packet RAM for multiple Link Layer usage. 0x428 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_533 Shared Packet RAM for multiple Link Layer usage. 0x42A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_534 Shared Packet RAM for multiple Link Layer usage. 0x42C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_535 Shared Packet RAM for multiple Link Layer usage. 0x42E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_536 Shared Packet RAM for multiple Link Layer usage. 0x430 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_537 Shared Packet RAM for multiple Link Layer usage. 0x432 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_538 Shared Packet RAM for multiple Link Layer usage. 0x434 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_539 Shared Packet RAM for multiple Link Layer usage. 0x436 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_540 Shared Packet RAM for multiple Link Layer usage. 0x438 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_541 Shared Packet RAM for multiple Link Layer usage. 0x43A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_542 Shared Packet RAM for multiple Link Layer usage. 0x43C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_0_543 Shared Packet RAM for multiple Link Layer usage. 0x43E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_0 Shared Packet RAM for multiple Link Layer usage. 0x440 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_1 Shared Packet RAM for multiple Link Layer usage. 0x442 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_2 Shared Packet RAM for multiple Link Layer usage. 0x444 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_3 Shared Packet RAM for multiple Link Layer usage. 0x446 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_4 Shared Packet RAM for multiple Link Layer usage. 0x448 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_5 Shared Packet RAM for multiple Link Layer usage. 0x44A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_6 Shared Packet RAM for multiple Link Layer usage. 0x44C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_7 Shared Packet RAM for multiple Link Layer usage. 0x44E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_8 Shared Packet RAM for multiple Link Layer usage. 0x450 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_9 Shared Packet RAM for multiple Link Layer usage. 0x452 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_10 Shared Packet RAM for multiple Link Layer usage. 0x454 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_11 Shared Packet RAM for multiple Link Layer usage. 0x456 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_12 Shared Packet RAM for multiple Link Layer usage. 0x458 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_13 Shared Packet RAM for multiple Link Layer usage. 0x45A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_14 Shared Packet RAM for multiple Link Layer usage. 0x45C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_15 Shared Packet RAM for multiple Link Layer usage. 0x45E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_16 Shared Packet RAM for multiple Link Layer usage. 0x460 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_17 Shared Packet RAM for multiple Link Layer usage. 0x462 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_18 Shared Packet RAM for multiple Link Layer usage. 0x464 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_19 Shared Packet RAM for multiple Link Layer usage. 0x466 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_20 Shared Packet RAM for multiple Link Layer usage. 0x468 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_21 Shared Packet RAM for multiple Link Layer usage. 0x46A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_22 Shared Packet RAM for multiple Link Layer usage. 0x46C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_23 Shared Packet RAM for multiple Link Layer usage. 0x46E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_24 Shared Packet RAM for multiple Link Layer usage. 0x470 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_25 Shared Packet RAM for multiple Link Layer usage. 0x472 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_26 Shared Packet RAM for multiple Link Layer usage. 0x474 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_27 Shared Packet RAM for multiple Link Layer usage. 0x476 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_28 Shared Packet RAM for multiple Link Layer usage. 0x478 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_29 Shared Packet RAM for multiple Link Layer usage. 0x47A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_30 Shared Packet RAM for multiple Link Layer usage. 0x47C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_31 Shared Packet RAM for multiple Link Layer usage. 0x47E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_32 Shared Packet RAM for multiple Link Layer usage. 0x480 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_33 Shared Packet RAM for multiple Link Layer usage. 0x482 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_34 Shared Packet RAM for multiple Link Layer usage. 0x484 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_35 Shared Packet RAM for multiple Link Layer usage. 0x486 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_36 Shared Packet RAM for multiple Link Layer usage. 0x488 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_37 Shared Packet RAM for multiple Link Layer usage. 0x48A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_38 Shared Packet RAM for multiple Link Layer usage. 0x48C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_39 Shared Packet RAM for multiple Link Layer usage. 0x48E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_40 Shared Packet RAM for multiple Link Layer usage. 0x490 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_41 Shared Packet RAM for multiple Link Layer usage. 0x492 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_42 Shared Packet RAM for multiple Link Layer usage. 0x494 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_43 Shared Packet RAM for multiple Link Layer usage. 0x496 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_44 Shared Packet RAM for multiple Link Layer usage. 0x498 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_45 Shared Packet RAM for multiple Link Layer usage. 0x49A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_46 Shared Packet RAM for multiple Link Layer usage. 0x49C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_47 Shared Packet RAM for multiple Link Layer usage. 0x49E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_48 Shared Packet RAM for multiple Link Layer usage. 0x4A0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_49 Shared Packet RAM for multiple Link Layer usage. 0x4A2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_50 Shared Packet RAM for multiple Link Layer usage. 0x4A4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_51 Shared Packet RAM for multiple Link Layer usage. 0x4A6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_52 Shared Packet RAM for multiple Link Layer usage. 0x4A8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_53 Shared Packet RAM for multiple Link Layer usage. 0x4AA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_54 Shared Packet RAM for multiple Link Layer usage. 0x4AC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_55 Shared Packet RAM for multiple Link Layer usage. 0x4AE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_56 Shared Packet RAM for multiple Link Layer usage. 0x4B0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_57 Shared Packet RAM for multiple Link Layer usage. 0x4B2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_58 Shared Packet RAM for multiple Link Layer usage. 0x4B4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_59 Shared Packet RAM for multiple Link Layer usage. 0x4B6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_60 Shared Packet RAM for multiple Link Layer usage. 0x4B8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_61 Shared Packet RAM for multiple Link Layer usage. 0x4BA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_62 Shared Packet RAM for multiple Link Layer usage. 0x4BC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_63 Shared Packet RAM for multiple Link Layer usage. 0x4BE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_64 Shared Packet RAM for multiple Link Layer usage. 0x4C0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_65 Shared Packet RAM for multiple Link Layer usage. 0x4C2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_66 Shared Packet RAM for multiple Link Layer usage. 0x4C4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_67 Shared Packet RAM for multiple Link Layer usage. 0x4C6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_68 Shared Packet RAM for multiple Link Layer usage. 0x4C8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_69 Shared Packet RAM for multiple Link Layer usage. 0x4CA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_70 Shared Packet RAM for multiple Link Layer usage. 0x4CC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_71 Shared Packet RAM for multiple Link Layer usage. 0x4CE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_72 Shared Packet RAM for multiple Link Layer usage. 0x4D0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_73 Shared Packet RAM for multiple Link Layer usage. 0x4D2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_74 Shared Packet RAM for multiple Link Layer usage. 0x4D4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_75 Shared Packet RAM for multiple Link Layer usage. 0x4D6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_76 Shared Packet RAM for multiple Link Layer usage. 0x4D8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_77 Shared Packet RAM for multiple Link Layer usage. 0x4DA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_78 Shared Packet RAM for multiple Link Layer usage. 0x4DC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_79 Shared Packet RAM for multiple Link Layer usage. 0x4DE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_80 Shared Packet RAM for multiple Link Layer usage. 0x4E0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_81 Shared Packet RAM for multiple Link Layer usage. 0x4E2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_82 Shared Packet RAM for multiple Link Layer usage. 0x4E4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_83 Shared Packet RAM for multiple Link Layer usage. 0x4E6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_84 Shared Packet RAM for multiple Link Layer usage. 0x4E8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_85 Shared Packet RAM for multiple Link Layer usage. 0x4EA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_86 Shared Packet RAM for multiple Link Layer usage. 0x4EC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_87 Shared Packet RAM for multiple Link Layer usage. 0x4EE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_88 Shared Packet RAM for multiple Link Layer usage. 0x4F0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_89 Shared Packet RAM for multiple Link Layer usage. 0x4F2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_90 Shared Packet RAM for multiple Link Layer usage. 0x4F4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_91 Shared Packet RAM for multiple Link Layer usage. 0x4F6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_92 Shared Packet RAM for multiple Link Layer usage. 0x4F8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_93 Shared Packet RAM for multiple Link Layer usage. 0x4FA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_94 Shared Packet RAM for multiple Link Layer usage. 0x4FC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_95 Shared Packet RAM for multiple Link Layer usage. 0x4FE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_96 Shared Packet RAM for multiple Link Layer usage. 0x500 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_97 Shared Packet RAM for multiple Link Layer usage. 0x502 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_98 Shared Packet RAM for multiple Link Layer usage. 0x504 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_99 Shared Packet RAM for multiple Link Layer usage. 0x506 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_100 Shared Packet RAM for multiple Link Layer usage. 0x508 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_101 Shared Packet RAM for multiple Link Layer usage. 0x50A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_102 Shared Packet RAM for multiple Link Layer usage. 0x50C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_103 Shared Packet RAM for multiple Link Layer usage. 0x50E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_104 Shared Packet RAM for multiple Link Layer usage. 0x510 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_105 Shared Packet RAM for multiple Link Layer usage. 0x512 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_106 Shared Packet RAM for multiple Link Layer usage. 0x514 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_107 Shared Packet RAM for multiple Link Layer usage. 0x516 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_108 Shared Packet RAM for multiple Link Layer usage. 0x518 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_109 Shared Packet RAM for multiple Link Layer usage. 0x51A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_110 Shared Packet RAM for multiple Link Layer usage. 0x51C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_111 Shared Packet RAM for multiple Link Layer usage. 0x51E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_112 Shared Packet RAM for multiple Link Layer usage. 0x520 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_113 Shared Packet RAM for multiple Link Layer usage. 0x522 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_114 Shared Packet RAM for multiple Link Layer usage. 0x524 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_115 Shared Packet RAM for multiple Link Layer usage. 0x526 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_116 Shared Packet RAM for multiple Link Layer usage. 0x528 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_117 Shared Packet RAM for multiple Link Layer usage. 0x52A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_118 Shared Packet RAM for multiple Link Layer usage. 0x52C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_119 Shared Packet RAM for multiple Link Layer usage. 0x52E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_120 Shared Packet RAM for multiple Link Layer usage. 0x530 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_121 Shared Packet RAM for multiple Link Layer usage. 0x532 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_122 Shared Packet RAM for multiple Link Layer usage. 0x534 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_123 Shared Packet RAM for multiple Link Layer usage. 0x536 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_124 Shared Packet RAM for multiple Link Layer usage. 0x538 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_125 Shared Packet RAM for multiple Link Layer usage. 0x53A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_126 Shared Packet RAM for multiple Link Layer usage. 0x53C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_127 Shared Packet RAM for multiple Link Layer usage. 0x53E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_128 Shared Packet RAM for multiple Link Layer usage. 0x540 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_129 Shared Packet RAM for multiple Link Layer usage. 0x542 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_130 Shared Packet RAM for multiple Link Layer usage. 0x544 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_131 Shared Packet RAM for multiple Link Layer usage. 0x546 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_132 Shared Packet RAM for multiple Link Layer usage. 0x548 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_133 Shared Packet RAM for multiple Link Layer usage. 0x54A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_134 Shared Packet RAM for multiple Link Layer usage. 0x54C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_135 Shared Packet RAM for multiple Link Layer usage. 0x54E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_136 Shared Packet RAM for multiple Link Layer usage. 0x550 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_137 Shared Packet RAM for multiple Link Layer usage. 0x552 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_138 Shared Packet RAM for multiple Link Layer usage. 0x554 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_139 Shared Packet RAM for multiple Link Layer usage. 0x556 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_140 Shared Packet RAM for multiple Link Layer usage. 0x558 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_141 Shared Packet RAM for multiple Link Layer usage. 0x55A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_142 Shared Packet RAM for multiple Link Layer usage. 0x55C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_143 Shared Packet RAM for multiple Link Layer usage. 0x55E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_144 Shared Packet RAM for multiple Link Layer usage. 0x560 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_145 Shared Packet RAM for multiple Link Layer usage. 0x562 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_146 Shared Packet RAM for multiple Link Layer usage. 0x564 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_147 Shared Packet RAM for multiple Link Layer usage. 0x566 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_148 Shared Packet RAM for multiple Link Layer usage. 0x568 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_149 Shared Packet RAM for multiple Link Layer usage. 0x56A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_150 Shared Packet RAM for multiple Link Layer usage. 0x56C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_151 Shared Packet RAM for multiple Link Layer usage. 0x56E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_152 Shared Packet RAM for multiple Link Layer usage. 0x570 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_153 Shared Packet RAM for multiple Link Layer usage. 0x572 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_154 Shared Packet RAM for multiple Link Layer usage. 0x574 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_155 Shared Packet RAM for multiple Link Layer usage. 0x576 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_156 Shared Packet RAM for multiple Link Layer usage. 0x578 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_157 Shared Packet RAM for multiple Link Layer usage. 0x57A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_158 Shared Packet RAM for multiple Link Layer usage. 0x57C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_159 Shared Packet RAM for multiple Link Layer usage. 0x57E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_160 Shared Packet RAM for multiple Link Layer usage. 0x580 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_161 Shared Packet RAM for multiple Link Layer usage. 0x582 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_162 Shared Packet RAM for multiple Link Layer usage. 0x584 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_163 Shared Packet RAM for multiple Link Layer usage. 0x586 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_164 Shared Packet RAM for multiple Link Layer usage. 0x588 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_165 Shared Packet RAM for multiple Link Layer usage. 0x58A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_166 Shared Packet RAM for multiple Link Layer usage. 0x58C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_167 Shared Packet RAM for multiple Link Layer usage. 0x58E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_168 Shared Packet RAM for multiple Link Layer usage. 0x590 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_169 Shared Packet RAM for multiple Link Layer usage. 0x592 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_170 Shared Packet RAM for multiple Link Layer usage. 0x594 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_171 Shared Packet RAM for multiple Link Layer usage. 0x596 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_172 Shared Packet RAM for multiple Link Layer usage. 0x598 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_173 Shared Packet RAM for multiple Link Layer usage. 0x59A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_174 Shared Packet RAM for multiple Link Layer usage. 0x59C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_175 Shared Packet RAM for multiple Link Layer usage. 0x59E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_176 Shared Packet RAM for multiple Link Layer usage. 0x5A0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_177 Shared Packet RAM for multiple Link Layer usage. 0x5A2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_178 Shared Packet RAM for multiple Link Layer usage. 0x5A4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_179 Shared Packet RAM for multiple Link Layer usage. 0x5A6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_180 Shared Packet RAM for multiple Link Layer usage. 0x5A8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_181 Shared Packet RAM for multiple Link Layer usage. 0x5AA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_182 Shared Packet RAM for multiple Link Layer usage. 0x5AC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_183 Shared Packet RAM for multiple Link Layer usage. 0x5AE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_184 Shared Packet RAM for multiple Link Layer usage. 0x5B0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_185 Shared Packet RAM for multiple Link Layer usage. 0x5B2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_186 Shared Packet RAM for multiple Link Layer usage. 0x5B4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_187 Shared Packet RAM for multiple Link Layer usage. 0x5B6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_188 Shared Packet RAM for multiple Link Layer usage. 0x5B8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_189 Shared Packet RAM for multiple Link Layer usage. 0x5BA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_190 Shared Packet RAM for multiple Link Layer usage. 0x5BC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_191 Shared Packet RAM for multiple Link Layer usage. 0x5BE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_192 Shared Packet RAM for multiple Link Layer usage. 0x5C0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_193 Shared Packet RAM for multiple Link Layer usage. 0x5C2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_194 Shared Packet RAM for multiple Link Layer usage. 0x5C4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_195 Shared Packet RAM for multiple Link Layer usage. 0x5C6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_196 Shared Packet RAM for multiple Link Layer usage. 0x5C8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_197 Shared Packet RAM for multiple Link Layer usage. 0x5CA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_198 Shared Packet RAM for multiple Link Layer usage. 0x5CC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_199 Shared Packet RAM for multiple Link Layer usage. 0x5CE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_200 Shared Packet RAM for multiple Link Layer usage. 0x5D0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_201 Shared Packet RAM for multiple Link Layer usage. 0x5D2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_202 Shared Packet RAM for multiple Link Layer usage. 0x5D4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_203 Shared Packet RAM for multiple Link Layer usage. 0x5D6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_204 Shared Packet RAM for multiple Link Layer usage. 0x5D8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_205 Shared Packet RAM for multiple Link Layer usage. 0x5DA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_206 Shared Packet RAM for multiple Link Layer usage. 0x5DC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_207 Shared Packet RAM for multiple Link Layer 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Packet RAM for multiple Link Layer usage. 0x5EC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_215 Shared Packet RAM for multiple Link Layer usage. 0x5EE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_216 Shared Packet RAM for multiple Link Layer usage. 0x5F0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_217 Shared Packet RAM for multiple Link Layer usage. 0x5F2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_218 Shared Packet RAM for multiple Link Layer usage. 0x5F4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_219 Shared Packet RAM for multiple Link Layer usage. 0x5F6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_220 Shared Packet RAM for multiple Link Layer usage. 0x5F8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 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usage. 0x722 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_370 Shared Packet RAM for multiple Link Layer usage. 0x724 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_371 Shared Packet RAM for multiple Link Layer usage. 0x726 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_372 Shared Packet RAM for multiple Link Layer usage. 0x728 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_373 Shared Packet RAM for multiple Link Layer usage. 0x72A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_374 Shared Packet RAM for multiple Link Layer usage. 0x72C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_375 Shared Packet RAM for multiple Link Layer usage. 0x72E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_376 Shared Packet RAM for multiple Link Layer usage. 0x730 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_377 Shared Packet RAM for multiple Link Layer usage. 0x732 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_378 Shared Packet RAM for multiple Link Layer usage. 0x734 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_379 Shared Packet RAM for multiple Link Layer usage. 0x736 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_380 Shared Packet RAM for multiple Link Layer usage. 0x738 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_381 Shared Packet RAM for multiple Link Layer usage. 0x73A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_382 Shared Packet RAM for multiple Link Layer usage. 0x73C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_383 Shared Packet RAM for multiple Link Layer usage. 0x73E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_384 Shared Packet RAM for multiple Link Layer usage. 0x740 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_385 Shared Packet RAM for multiple Link Layer usage. 0x742 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_386 Shared Packet RAM for multiple Link Layer usage. 0x744 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_387 Shared Packet RAM for multiple Link Layer usage. 0x746 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_388 Shared Packet RAM for multiple Link Layer usage. 0x748 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_389 Shared Packet RAM for multiple Link Layer usage. 0x74A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_390 Shared Packet RAM for multiple Link Layer usage. 0x74C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_391 Shared Packet RAM for multiple Link Layer usage. 0x74E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_392 Shared Packet RAM for multiple Link Layer usage. 0x750 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_393 Shared Packet RAM for multiple Link Layer usage. 0x752 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_394 Shared Packet RAM for multiple Link Layer usage. 0x754 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_395 Shared Packet RAM for multiple Link Layer usage. 0x756 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_396 Shared Packet RAM for multiple Link Layer usage. 0x758 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_397 Shared Packet RAM for multiple Link Layer usage. 0x75A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_398 Shared Packet RAM for multiple Link Layer usage. 0x75C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_399 Shared Packet RAM for multiple Link Layer usage. 0x75E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_400 Shared Packet RAM for multiple Link Layer usage. 0x760 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_401 Shared Packet RAM for multiple Link Layer usage. 0x762 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_402 Shared Packet RAM for multiple Link Layer usage. 0x764 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_403 Shared Packet RAM for multiple Link Layer usage. 0x766 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_404 Shared Packet RAM for multiple Link Layer usage. 0x768 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_405 Shared Packet RAM for multiple Link Layer usage. 0x76A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_406 Shared Packet RAM for multiple Link Layer usage. 0x76C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_407 Shared Packet RAM for multiple Link Layer usage. 0x76E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_408 Shared Packet RAM for multiple Link Layer usage. 0x770 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_409 Shared Packet RAM for multiple Link Layer usage. 0x772 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_410 Shared Packet RAM for multiple Link Layer usage. 0x774 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_411 Shared Packet RAM for multiple Link Layer usage. 0x776 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_412 Shared Packet RAM for multiple Link Layer usage. 0x778 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_413 Shared Packet RAM for multiple Link Layer usage. 0x77A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_414 Shared Packet RAM for multiple Link Layer usage. 0x77C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_415 Shared Packet RAM for multiple Link Layer usage. 0x77E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_416 Shared Packet RAM for multiple Link Layer usage. 0x780 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_417 Shared Packet RAM for multiple Link Layer usage. 0x782 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_418 Shared Packet RAM for multiple Link Layer usage. 0x784 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_419 Shared Packet RAM for multiple Link Layer usage. 0x786 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_420 Shared Packet RAM for multiple Link Layer usage. 0x788 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_421 Shared Packet RAM for multiple Link Layer usage. 0x78A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_422 Shared Packet RAM for multiple Link Layer usage. 0x78C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_423 Shared Packet RAM for multiple Link Layer usage. 0x78E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_424 Shared Packet RAM for multiple Link Layer usage. 0x790 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_425 Shared Packet RAM for multiple Link Layer usage. 0x792 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_426 Shared Packet RAM for multiple Link Layer usage. 0x794 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_427 Shared Packet RAM for multiple Link Layer usage. 0x796 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_428 Shared Packet RAM for multiple Link Layer usage. 0x798 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_429 Shared Packet RAM for multiple Link Layer usage. 0x79A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_430 Shared Packet RAM for multiple Link Layer usage. 0x79C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_431 Shared Packet RAM for multiple Link Layer usage. 0x79E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_432 Shared Packet RAM for multiple Link Layer usage. 0x7A0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_433 Shared Packet RAM for multiple Link Layer usage. 0x7A2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_434 Shared Packet RAM for multiple Link Layer usage. 0x7A4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_435 Shared Packet RAM for multiple Link Layer usage. 0x7A6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_436 Shared Packet RAM for multiple Link Layer usage. 0x7A8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_437 Shared Packet RAM for multiple Link Layer usage. 0x7AA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_438 Shared Packet RAM for multiple Link Layer usage. 0x7AC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_439 Shared Packet RAM for multiple Link Layer usage. 0x7AE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_440 Shared Packet RAM for multiple Link Layer usage. 0x7B0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_441 Shared Packet RAM for multiple Link Layer usage. 0x7B2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_442 Shared Packet RAM for multiple Link Layer usage. 0x7B4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_443 Shared Packet RAM for multiple Link Layer usage. 0x7B6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_444 Shared Packet RAM for multiple Link Layer usage. 0x7B8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_445 Shared Packet RAM for multiple Link Layer usage. 0x7BA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_446 Shared Packet RAM for multiple Link Layer usage. 0x7BC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_447 Shared Packet RAM for multiple Link Layer usage. 0x7BE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_448 Shared Packet RAM for multiple Link Layer usage. 0x7C0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_449 Shared Packet RAM for multiple Link Layer usage. 0x7C2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_450 Shared Packet RAM for multiple Link Layer usage. 0x7C4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_451 Shared Packet RAM for multiple Link Layer usage. 0x7C6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_452 Shared Packet RAM for multiple Link Layer usage. 0x7C8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_453 Shared Packet RAM for multiple Link Layer usage. 0x7CA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_454 Shared Packet RAM for multiple Link Layer usage. 0x7CC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_455 Shared Packet RAM for multiple Link Layer usage. 0x7CE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_456 Shared Packet RAM for multiple Link Layer usage. 0x7D0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_457 Shared Packet RAM for multiple Link Layer usage. 0x7D2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_458 Shared Packet RAM for multiple Link Layer usage. 0x7D4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_459 Shared Packet RAM for multiple Link Layer usage. 0x7D6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_460 Shared Packet RAM for multiple Link Layer usage. 0x7D8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_461 Shared Packet RAM for multiple Link Layer usage. 0x7DA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_462 Shared Packet RAM for multiple Link Layer usage. 0x7DC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_463 Shared Packet RAM for multiple Link Layer usage. 0x7DE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_464 Shared Packet RAM for multiple Link Layer usage. 0x7E0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_465 Shared Packet RAM for multiple Link Layer usage. 0x7E2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_466 Shared Packet RAM for multiple Link Layer usage. 0x7E4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_467 Shared Packet RAM for multiple Link Layer usage. 0x7E6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_468 Shared Packet RAM for multiple Link Layer usage. 0x7E8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_469 Shared Packet RAM for multiple Link Layer usage. 0x7EA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_470 Shared Packet RAM for multiple Link Layer usage. 0x7EC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_471 Shared Packet RAM for multiple Link Layer usage. 0x7EE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_472 Shared Packet RAM for multiple Link Layer usage. 0x7F0 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_473 Shared Packet RAM for multiple Link Layer usage. 0x7F2 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_474 Shared Packet RAM for multiple Link Layer usage. 0x7F4 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_475 Shared Packet RAM for multiple Link Layer usage. 0x7F6 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_476 Shared Packet RAM for multiple Link Layer usage. 0x7F8 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_477 Shared Packet RAM for multiple Link Layer usage. 0x7FA 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_478 Shared Packet RAM for multiple Link Layer usage. 0x7FC 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_479 Shared Packet RAM for multiple Link Layer usage. 0x7FE 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_480 Shared Packet RAM for multiple Link Layer usage. 0x800 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_481 Shared Packet RAM for multiple Link Layer usage. 0x802 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_482 Shared Packet RAM for multiple Link Layer usage. 0x804 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_483 Shared Packet RAM for multiple Link Layer usage. 0x806 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_484 Shared Packet RAM for multiple Link Layer usage. 0x808 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_485 Shared Packet RAM for multiple Link Layer usage. 0x80A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_486 Shared Packet RAM for multiple Link Layer usage. 0x80C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_487 Shared Packet RAM for multiple Link Layer usage. 0x80E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_488 Shared Packet RAM for multiple Link Layer usage. 0x810 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_489 Shared Packet RAM for multiple Link Layer usage. 0x812 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_490 Shared Packet RAM for multiple Link Layer usage. 0x814 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_491 Shared Packet RAM for multiple Link Layer usage. 0x816 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_492 Shared Packet RAM for multiple Link Layer usage. 0x818 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_493 Shared Packet RAM for multiple Link Layer usage. 0x81A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_494 Shared Packet RAM for multiple Link Layer usage. 0x81C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_495 Shared Packet RAM for multiple Link Layer usage. 0x81E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_496 Shared Packet RAM for multiple Link Layer usage. 0x820 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_497 Shared Packet RAM for multiple Link Layer usage. 0x822 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_498 Shared Packet RAM for multiple Link Layer usage. 0x824 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_499 Shared Packet RAM for multiple Link Layer usage. 0x826 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_500 Shared Packet RAM for multiple Link Layer usage. 0x828 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_501 Shared Packet RAM for multiple Link Layer usage. 0x82A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_502 Shared Packet RAM for multiple Link Layer usage. 0x82C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_503 Shared Packet RAM for multiple Link Layer usage. 0x82E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_504 Shared Packet RAM for multiple Link Layer usage. 0x830 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_505 Shared Packet RAM for multiple Link Layer usage. 0x832 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_506 Shared Packet RAM for multiple Link Layer usage. 0x834 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_507 Shared Packet RAM for multiple Link Layer usage. 0x836 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_508 Shared Packet RAM for multiple Link Layer usage. 0x838 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_509 Shared Packet RAM for multiple Link Layer usage. 0x83A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_510 Shared Packet RAM for multiple Link Layer usage. 0x83C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_511 Shared Packet RAM for multiple Link Layer usage. 0x83E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_512 Shared Packet RAM for multiple Link Layer usage. 0x840 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_513 Shared Packet RAM for multiple Link Layer usage. 0x842 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_514 Shared Packet RAM for multiple Link Layer usage. 0x844 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_515 Shared Packet RAM for multiple Link Layer usage. 0x846 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_516 Shared Packet RAM for multiple Link Layer usage. 0x848 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_517 Shared Packet RAM for multiple Link Layer usage. 0x84A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_518 Shared Packet RAM for multiple Link Layer usage. 0x84C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_519 Shared Packet RAM for multiple Link Layer usage. 0x84E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_520 Shared Packet RAM for multiple Link Layer usage. 0x850 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_521 Shared Packet RAM for multiple Link Layer usage. 0x852 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_522 Shared Packet RAM for multiple Link Layer usage. 0x854 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_523 Shared Packet RAM for multiple Link Layer usage. 0x856 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_524 Shared Packet RAM for multiple Link Layer usage. 0x858 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_525 Shared Packet RAM for multiple Link Layer usage. 0x85A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_526 Shared Packet RAM for multiple Link Layer usage. 0x85C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_527 Shared Packet RAM for multiple Link Layer usage. 0x85E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_528 Shared Packet RAM for multiple Link Layer usage. 0x860 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_529 Shared Packet RAM for multiple Link Layer usage. 0x862 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_530 Shared Packet RAM for multiple Link Layer usage. 0x864 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_531 Shared Packet RAM for multiple Link Layer usage. 0x866 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_532 Shared Packet RAM for multiple Link Layer usage. 0x868 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_533 Shared Packet RAM for multiple Link Layer usage. 0x86A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_534 Shared Packet RAM for multiple Link Layer usage. 0x86C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_535 Shared Packet RAM for multiple Link Layer usage. 0x86E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_536 Shared Packet RAM for multiple Link Layer usage. 0x870 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_537 Shared Packet RAM for multiple Link Layer usage. 0x872 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_538 Shared Packet RAM for multiple Link Layer usage. 0x874 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_539 Shared Packet RAM for multiple Link Layer usage. 0x876 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_540 Shared Packet RAM for multiple Link Layer usage. 0x878 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_541 Shared Packet RAM for multiple Link Layer usage. 0x87A 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_542 Shared Packet RAM for multiple Link Layer usage. 0x87C 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1_543 Shared Packet RAM for multiple Link Layer usage. 0x87E 16 read-write 0 0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write ZLL_REGS ZLL 0x4005D000 0 0x200 registers IRQSTS INTERRUPT REQUEST STATUS 0 32 read-write 0xF00000 0x80F00200 SEQIRQ Sequencer IRQ 0 1 read-write 0 A Sequencer Interrupt has not occurred #0 1 A Sequencer Interrupt has occurred #1 TXIRQ TX IRQ 1 1 read-write 0 A TX Interrupt has not occurred #0 1 A TX Interrupt has occurred #1 RXIRQ RX IRQ 2 1 read-write 0 A RX Interrupt has not occurred #0 1 A RX Interrupt has occurred #1 CCAIRQ CCA IRQ 3 1 read-write 0 A CCA Interrupt has not occurred #0 1 A CCA Interrupt has occurred #1 RXWTRMRKIRQ Receive Watermark IRQ 4 1 read-write 0 A Receive Watermark Interrupt has not occurred #0 1 A Receive Watermark Interrupt has occurred #1 FILTERFAIL_IRQ Filter Fail IRQ 5 1 read-write 0 A Filter Fail Interrupt has not occurred #0 1 A Filter Fail Interrupt has occurred #1 PLL_UNLOCK_IRQ PLL Unlock IRQ 6 1 read-write 0 A PLL Unlock Interrupt has not occurred #0 1 A PLL Unlock Interrupt has occurred #1 RX_FRM_PEND RX Frame Pending 7 1 read-only WAKE_IRQ WAKE Interrupt Request 8 1 read-write 0 A Wake Interrupt has not occurred #0 1 A Wake Interrupt has occurred #1 TSM_IRQ TSM IRQ 10 1 read-only 0 A TSM Interrupt has not occurred #0 1 A TSM Interrupt has occurred #1 ENH_PKT_STATUS Enhanced Packet Status 11 1 read-only 0 The last packet received was neither 4e- nor 2015-compliant #0 1 The last packet received was 4e- or 2015-compliant (RX_FRAME_FILTER register should be queried for additional status bits) #1 PI Poll Indication 12 1 read-only 0 the received packet was not a data request #0 1 the received packet was a data request, regardless of whether a Source Address table match occurred, or whether Source Address Management is enabled or not #1 SRCADDR Source Address Match Status 13 1 read-only CCA CCA Status 14 1 read-only 0 IDLE #0 1 BUSY #1 CRCVALID CRC Valid Status 15 1 read-only 0 Rx FCS != calculated CRC (incorrect) #0 1 Rx FCS = calculated CRC (correct) #1 TMR1IRQ Timer 1 IRQ 16 1 read-write TMR2IRQ Timer 2 IRQ 17 1 read-write TMR3IRQ Timer 3 IRQ 18 1 read-write TMR4IRQ Timer 4 IRQ 19 1 read-write TMR1MSK Timer Comperator 1 Interrupt Mask bit 20 1 read-write 0 allows interrupt when comparator matches event timer count #0 1 Interrupt generation is disabled, but a TMR1IRQ flag can be set #1 TMR2MSK Timer Comperator 2 Interrupt Mask bit 21 1 read-write 0 allows interrupt when comparator matches event timer count #0 1 Interrupt generation is disabled, but a TMR2IRQ flag can be set #1 TMR3MSK Timer Comperator 3 Interrupt Mask bit 22 1 read-write 0 allows interrupt when comparator matches event timer count #0 1 Interrupt generation is disabled, but a TMR3IRQ flag can be set #1 TMR4MSK Timer Comperator 4 Interrupt Mask bit 23 1 read-write 0 allows interrupt when comparator matches event timer count #0 1 Interrupt generation is disabled, but a TMR4IRQ flag can be set #1 RX_FRAME_LENGTH Receive Frame Length 24 7 read-only PHY_CTRL PHY CONTROL 0x4 32 read-write 0x805FF00 0xFFFFFFFF XCVSEQ Zigbee Transceiver Sequence Selector 0 3 read-write 0 I (IDLE) #000 1 R (RECEIVE) #001 2 T (TRANSMIT) #010 3 C (CCA) #011 4 TR (TRANSMIT/RECEIVE) #100 5 CCCA (CONTINUOUS CCA) #101 AUTOACK Auto Acknowledge Enable 3 1 read-write 0 sequence manager will not follow a receive frame with a Tx Ack frame, under any conditions; the autosequence will terminate after the receive frame. #0 1 sequence manager will follow a receive frame with an automatic hardware-generated Tx Ack frame, assuming other necessary conditions are met. #1 RXACKRQD Receive Acknowledge Frame required 4 1 read-write 0 An ordinary receive frame (any type of frame) follows the transmit frame. #0 1 A receive Ack frame is expected to follow the transmit frame (non-Ack frames are rejected). #1 CCABFRTX CCA Before TX 5 1 read-write 0 no CCA required, transmit operation begins immediately. #0 1 at least one CCA measurement is required prior to the transmit operation (see also SLOTTED). #1 SLOTTED Slotted Mode 6 1 read-write TMRTRIGEN Timer2 Trigger Enable 7 1 read-write 0 programmed sequence initiates immediately upon write to XCVSEQ. #0 1 allow timer TC2 (or TC2') to initiate a preprogrammed sequence (see XCVSEQ register). #1 SEQMSK Sequencer Interrupt Mask 8 1 read-write 0 allows completion of an autosequence to generate a zigbee interrupt #0 1 Completion of an autosequence will set the SEQIRQ status bit, but a zigbee interrupt is not generated #1 TXMSK TX Interrupt Mask 9 1 read-write 0 allows completion of a TX operation to generate a zigbee interrupt #0 1 Completion of a TX operation will set the TXIRQ status bit, but a zigbee interrupt is not generated #1 RXMSK RX Interrupt Mask 10 1 read-write 0 allows completion of a RX operation to generate a zigbee interrupt #0 1 Completion of a RX operation will set the RXIRQ status bit, but a zigbee interrupt is not generated #1 CCAMSK CCA Interrupt Mask 11 1 read-write 0 allows completion of a CCA operation to generate a zigbee interrupt #0 1 Completion of a CCA operation will set the CCA status bit, but a zigbee interrupt is not generated #1 RX_WMRK_MSK RX Watermark Interrupt Mask 12 1 read-write 0 allows a Received Byte Count match to the RX_WTR_MARK threshold register to generate a zigbee interrupt #0 1 A Received Byte Count match to the RX_WTR_MARK threshold register will set the RXWTRMRKIRQ status bit, but a zigbee interrupt is not generated #1 FILTERFAIL_MSK FilterFail Interrupt Mask 13 1 read-write 0 allows Packet Processor Filtering Failure to generate a zigbee interrupt #0 1 A Packet Processor Filtering Failure will set the FILTERFAIL_IRQ status bit, but a zigbee interrupt is not generated #1 PLL_UNLOCK_MSK PLL Unlock Interrupt Mask 14 1 read-write 0 allows PLL unlock event to generate a zigbee interrupt #0 1 A PLL unlock event will set the PLL_UNLOCK_IRQ status bit, but a zigbee interrupt is not generated #1 CRC_MSK CRC Mask 15 1 read-write 0 sequence manager ignores CRCVALID and considers the receive operation complete after the last octet of the frame has been received. #0 1 sequence manager requires CRCVALID=1 at the end of the received frame in order for the receive operation to complete successfully; if CRCVALID=0, sequence manager will return to preamble-detect mode after the last octet of the frame has been received. #1 WAKE_MSK no description available 16 1 read-write 0 Allows a wakeup from DSM to generate a zigbee interrupt #0 1 Wakeup from DSM will set the WAKE_IRQ status bit, but a zigbee interrupt is not generated #1 TSM_MSK no description available 18 1 read-write 0 allows assertion of a TSM interrupt to generate a zigbee interrupt #0 1 Assertion of a TSM interrupt will set the TSM_IRQ status bit, but a zigbee interrupt is not generated #1 TMR1CMP_EN Timer 1 Compare Enable 20 1 read-write 0 Don't allow an Event Timer Match to T1CMP to set TMR1IRQ #0 1 Allow an Event Timer Match to T1CMP to set TMR1IRQ #1 TMR2CMP_EN Timer 2 Compare Enable 21 1 read-write 0 Don't allow an Event Timer Match to T2CMP or T2PRIMECMP to set TMR2IRQ #0 1 Allow an Event Timer Match to T2CMP or T2PRIMECMP to set TMR2IRQ #1 TMR3CMP_EN Timer 3 Compare Enable 22 1 read-write 0 Don't allow an Event Timer Match to T3CMP to set TMR3IRQ #0 1 Allow an Event Timer Match to T3CMP to set TMR3IRQ #1 TMR4CMP_EN Timer 4 Compare Enable 23 1 read-write 0 Don't allow an Event Timer Match to T4CMP to set TMR4IRQ #0 1 Allow an Event Timer Match to T4CMP to set TMR4IRQ #1 TC2PRIME_EN Timer 2 Prime Compare Enable 24 1 read-write 0 Don't allow a match of the lower 16 bits of Event Timer to T2PRIMECMP to set TMR2IRQ #0 1 Allow a match of the lower 16 bits of Event Timer to T2PRIMECMP to set TMR2IRQ #1 PROMISCUOUS Promiscuous Mode Enable 25 1 read-write 0 normal mode #0 1 all packet filtering except frame length checking (FrameLength>=5 and FrameLength<=127) is bypassed. #1 CCATYPE Clear Channel Assessment Type 27 2 read-write 0 ENERGY DETECT #00 1 CCA MODE 1 #01 2 CCA MODE 2 #10 3 CCA MODE 3 #11 PANCORDNTR0 Device is a PAN Coordinator on PAN0 29 1 read-write TC3TMOUT TMR3 Timeout Enable 30 1 read-write 0 TMR3 is a software timer only #0 1 Enable TMR3 to abort Rx or CCCA operations. #1 TRCV_MSK Transceiver Global Interrupt Mask 31 1 read-write 0 Enable any unmasked interrupt source to assert zigbee interrupt #0 1 Mask all interrupt sources from asserting zigbee interrupt #1 EVENT_TMR EVENT TIMER 0x8 32 read-write 0 0xF EVENT_TMR_LD Event Timer Load Enable 0 1 write-only EVENT_TMR_ADD Event Timer Add Enable 1 1 write-only EVENT_TMR_FRAC Event Timer Fractional Component 4 4 read-write EVENT_TMR Event Timer Integer Component 8 24 read-write TIMESTAMP TIMESTAMP 0xC 32 read-only 0 0xFF000000 TIMESTAMP Timestamp 0 24 read-only T1CMP T1 COMPARE 0x10 32 read-write 0xFFFFFF 0xFFFFFFFF T1CMP TMR1 Compare Value 0 24 read-write T2CMP T2 COMPARE 0x14 32 read-write 0xFFFFFF 0xFFFFFFFF T2CMP TMR2 Compare Value 0 24 read-write T2PRIMECMP T2 PRIME COMPARE 0x18 32 read-write 0xFFFF 0xFFFFFFFF T2PRIMECMP TMR2 Prime Compare Value 0 16 read-write T3CMP T3 COMPARE 0x1C 32 read-write 0xFFFFFF 0xFFFFFFFF T3CMP TMR3 Compare Value 0 24 read-write T4CMP T4 COMPARE 0x20 32 read-write 0xFFFFFF 0xFFFFFFFF T4CMP TMR4 Compare Value 0 24 read-write PA_PWR PA POWER 0x24 32 read-write 0 0xFFFFFFFF PA_PWR PA Power 0 6 read-write CHANNEL_NUM0 CHANNEL NUMBER 0 0x28 32 read-write 0x12 0xFFFFFFFF CHANNEL_NUM0 Channel Number for PAN0 0 7 read-write LQI_AND_RSSI LQI AND RSSI 0x2C 32 read-only 0 0xFF000000 LQI_VALUE LQI Value 0 8 read-only RSSI RSSI Value 8 8 read-only CCA1_ED_FNL Final Result for CCA Mode 1 and Energy Detect 16 8 read-only MACSHORTADDRS0 MAC SHORT ADDRESS 0 0x30 32 read-write 0xFFFFFFFF 0xFFFFFFFF MACPANID0 MAC PAN ID for PAN0 0 16 read-write MACSHORTADDRS0 MAC SHORT ADDRESS FOR PAN0 16 16 read-write MACLONGADDRS0_LSB MAC LONG ADDRESS 0 LSB 0x34 32 read-write 0xFFFFFFFF 0xFFFFFFFF MACLONGADDRS0_LSB MAC LONG ADDRESS for PAN0 LSB 0 32 read-write MACLONGADDRS0_MSB MAC LONG ADDRESS 0 MSB 0x38 32 read-write 0xFFFFFFFF 0xFFFFFFFF MACLONGADDRS0_MSB MAC LONG ADDRESS for PAN0 MSB 0 32 read-write RX_FRAME_FILTER RECEIVE FRAME FILTER 0x3C 32 read-write 0x30F 0xFF40FFFF BEACON_FT Beacon Frame Type Enable 0 1 read-write 0 reject all Beacon frames #0 1 Beacon frame type enabled. #1 DATA_FT Data Frame Type Enable 1 1 read-write 0 reject all Beacon frames #0 1 Data frame type enabled. #1 ACK_FT Ack Frame Type Enable 2 1 read-write 0 reject all Acknowledge frames #0 1 Acknowledge frame type enabled. #1 CMD_FT MAC Command Frame Type Enable 3 1 read-write 0 reject all MAC Command frames #0 1 MAC Command frame type enabled. #1 LLDN_FT LLDN Frame Type Enable 4 1 read-write 0 reject all LLDN frames #0 1 LLDN frame type enabled (Frame Type 4). #1 MULTIPURPOSE_FT Multipurpose Frame Type Enable 5 1 read-write 0 reject all Multipurpose frames #0 1 Multipurpose frame type enabled (Frame Type 5). #1 NS_FT "Not Specified" Frame Type Enable 6 1 read-write 0 reject all "Not Specified" frames #0 1 Not-specified (reserved) frame type enabled. Applies to Frame Type 6. No packet filtering is performed, except for frame length checking (FrameLength>=5 and FrameLength<=127). No AUTOACK is transmitted for this Frame Type #1 EXTENDED_FT Extended Frame Type Enable 7 1 read-write 0 reject all Extended frames #0 1 Extended frame type enabled (Frame Type 7). #1 FRM_VER_FILTER Frame Version selector. 8 4 read-write ACTIVE_PROMISCUOUS Active Promiscuous 14 1 read-write 0 normal operation #0 1 Provide Data Indication on all received packets under the same rules which apply in PROMISCUOUS mode, however acknowledge those packets under rules which apply in non-PROMISCUOUS mode #1 EXTENDED_FCS_CHK Verify FCS on Frame Type Extended 15 1 read-write 0 Packet Processor will not check FCS for Frame Type EXTENDED (default) #0 1 Packet Processor will check FCS at end-of-packet based on packet length derived from PHR, for Frame Type EXTENDED #1 FV2_BEACON_RECD Frame Version 2 Beacon Packet Received 16 1 read-only 0 The last packet received was not Frame Type Beacon with Frame Version 2 #0 1 The last packet received was Frame Type Beacon with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets #1 FV2_DATA_RECD Frame Version 2 Data Packet Received 17 1 read-only 0 The last packet received was not Frame Type Data with Frame Version 2 #0 1 The last packet received was Frame Type Data with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets #1 FV2_ACK_RECD Frame Version 2 Acknowledge Packet Received 18 1 read-only 0 The last packet received was not Frame Type Ack with Frame Version 2 #0 1 The last packet received was Frame Type Ack with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets #1 FV2_CMD_RECD Frame Version 2 MAC Command Packet Received 19 1 read-only 0 The last packet received was not Frame Type MAC Command with Frame Version 2 #0 1 The last packet received was Frame Type MAC Command with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets #1 LLDN_RECD LLDN Packet Received 20 1 read-only 0 The last packet received was not Frame Type LLDN #0 1 The last packet received was Frame Type LLDN, and LLDN_FT=1 to allow such packets. #1 MULTIPURPOSE_RECD Multipurpose Packet Received 21 1 read-only 0 last packet received was not Frame Type MULTIPURPOSE #0 1 The last packet received was Frame Type MULTIPURPOSE, and MULTIPURPOSE_FT=1 to allow such packets. #1 EXTENDED_RECD Extended Packet Received 23 1 read-only 0 The last packet received was not Frame Type EXTENDED #0 1 The last packet received was Frame Type EXTENDED, and EXTENDED_FT=1 to allow such packets. #1 CCA_LQI_CTRL CCA AND LQI CONTROL 0x40 32 read-write 0x866004B 0xFFFFFFFF CCA1_THRESH CCA Mode 1 Threshold 0 8 read-write LQI_OFFSET_COMP LQI Offset Compensation 16 8 read-write CCA3_AND_NOT_OR CCA Mode 3 AND not OR 27 1 read-write 0 CCA1 or CCA2 #0 1 CCA1 and CCA2 #1 CCA2_CTRL CCA2 CONTROL 0x44 32 read-write 0x8230 0xFFFFFFF0 CCA2_NUM_CORR_PEAKS CCA Mode 2 Number of Correlation Peaks Detected 0 4 read-only CCA2_MIN_NUM_CORR_TH CCA Mode 2 Threshold Number of Correlation Peaks 4 3 read-write CCA2_CORR_THRESH CCA Mode 2 Correlation Threshold 8 8 read-write DSM_CTRL DSM CONTROL 0x4C 32 read-write 0 0xFFFFFFFF ZIGBEE_SLEEP_EN Zigbee sleep enable 0 1 read-write BSM_CTRL BSM CONTROL 0x50 32 read-write 0 0xFFFFFFFF BSM_EN BSM Enable 0 1 read-write 0 Zigbee Bit Streaming Mode Disabled #0 1 Zigbee Bit Streaming Mode Enabled #1 MACSHORTADDRS1 MAC SHORT ADDRESS FOR PAN1 0x54 32 read-write 0xFFFFFFFF 0xFFFFFFFF MACPANID1 MAC PAN ID for PAN1 0 16 read-write MACSHORTADDRS1 MAC SHORT ADDRESS for PAN1 16 16 read-write MACLONGADDRS1_LSB MAC LONG ADDRESS 1 LSB 0x58 32 read-write 0xFFFFFFFF 0xFFFFFFFF MACLONGADDRS1_LSB MAC LONG ADDRESS for PAN1 LSB 0 32 read-write MACLONGADDRS1_MSB MAC LONG ADDRESS 1 MSB 0x5C 32 read-write 0xFFFFFFFF 0xFFFFFFFF MACLONGADDRS1_MSB MAC LONG ADDRESS for PAN1 MSB 0 32 read-write DUAL_PAN_CTRL DUAL PAN CONTROL 0x60 32 read-write 0 0xFF00FFF7 ACTIVE_NETWORK Active Network Selector 0 1 read-write 0 Select PAN0 #0 1 Select PAN1 #1 DUAL_PAN_AUTO Activates automatic Dual PAN operating mode 1 1 read-write PANCORDNTR1 Device is a PAN Coordinator on PAN1 2 1 read-write CURRENT_NETWORK Indicates which PAN is currently selected by hardware 3 1 read-only 0 PAN0 is selected #0 1 PAN1 is selected #1 ZB_DP_CHAN_OVRD_EN Dual PAN Channel Override Enable 4 1 read-write ZB_DP_CHAN_OVRD_SEL Dual PAN Channel Override Selector 5 1 read-write DUAL_PAN_DWELL Dual PAN Channel Frequency Dwell Time 8 8 read-write DUAL_PAN_REMAIN Time Remaining before next PAN switch in auto Dual PAN mode 16 6 read-only RECD_ON_PAN0 Last Packet was Received on PAN0 22 1 read-only RECD_ON_PAN1 Last Packet was Received on PAN1 23 1 read-only CHANNEL_NUM1 CHANNEL NUMBER 1 0x64 32 read-write 0x7F 0xFFFFFFFF CHANNEL_NUM1 Channel Number for PAN1 0 7 read-write SAM_CTRL SAM CONTROL 0x68 32 read-write 0x80804000 0xFFFFFFFF SAP0_EN Enables SAP0 Partition of the SAM Table 0 1 read-write 0 Disables SAP0 Partition #0 1 Enables SAP0 Partition #1 SAA0_EN Enables SAA0 Partition of the SAM Table 1 1 read-write 0 Disables SAA0 Partition #0 1 Enables SAA0 Partition #1 SAP1_EN Enables SAP1 Partition of the SAM Table 2 1 read-write 0 Disables SAP1 Partition #0 1 Enables SAP1 Partition #1 SAA1_EN Enables SAA1 Partition of the SAM Table 3 1 read-write 0 Disables SAA1 Partition #0 1 Enables SAA1 Partition #1 SAA0_START First Index of SAA0 partition 8 8 read-write SAP1_START First Index of SAP1 partition 16 8 read-write SAA1_START First Index of SAA1 partition 24 8 read-write SAM_TABLE SOURCE ADDRESS MANAGEMENT TABLE 0x6C 32 read-write 0 0x4C00007F SAM_INDEX Contains the SAM table index to be enabled or invalidated 0 7 read-write SAM_INDEX_WR Enables SAM Table Contents to be updated 7 1 write-only SAM_CHECKSUM Software-computed source address checksum, to be installed into a table index 8 16 read-write SAM_INDEX_INV Invalidate the SAM table index selected by SAM_INDEX 24 1 write-only SAM_INDEX_EN Enable the SAM table index selected by SAM_INDEX 25 1 write-only ACK_FRM_PND State of AutoTxAck FramePending field when SAM Accelleration is Disabled 26 1 read-write ACK_FRM_PND_CTRL Manual Control for AutoTxAck FramePending field 27 1 read-write 0 the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet is determined by hardware #0 1 the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet tracks ACK_FRM_PEND #1 FIND_FREE_IDX Find First Free Index 28 1 write-only INVALIDATE_ALL Invalidate Entire SAM Table 29 1 write-only SAM_BUSY SAM Table Update Status Bit 31 1 read-only SAM_MATCH SOURCE ADDRESS MANAGEMENT MATCH 0x70 32 read-only 0 0 SAP0_MATCH Index in the SAP0 Partition of the SAM Table corresponding to the first checksum match 0 7 read-only SAP0_ADDR_PRESENT A Checksum Match is Present in the SAP0 Partition of the SAM Table 7 1 read-only SAA0_MATCH Index in the SAA0 Partition of the SAM Table corresponding to the first checksum match 8 7 read-only SAA0_ADDR_ABSENT A Checksum Match is Absent in the SAA0 Partition of the SAM Table 15 1 read-only SAP1_MATCH Index in the SAP1 Partition of the SAM Table corresponding to the first checksum match 16 7 read-only SAP1_ADDR_PRESENT A Checksum Match is Present in the SAP1 Partition of the SAM Table 23 1 read-only SAA1_MATCH Index in the SAA1 Partition of the SAM Table corresponding to the first checksum match 24 7 read-only SAA1_ADDR_ABSENT A Checksum Match is Absent in the SAP1 Partition of the SAM Table 31 1 read-only SAM_FREE_IDX SAM FREE INDEX 0x74 32 read-only 0 0 SAP0_1ST_FREE_IDX First non-enabled (invalid) index in the SAP0 partition 0 8 read-only SAA0_1ST_FREE_IDX First non-enabled (invalid) index in the SAA0 partition 8 8 read-only SAP1_1ST_FREE_IDX First non-enabled (invalid) index in the SAP1 partition 16 8 read-only SAA1_1ST_FREE_IDX First non-enabled (invalid) index in the SAA1 partition 24 8 read-only SEQ_CTRL_STS SEQUENCE CONTROL AND STATUS 0x78 32 read-write 0x8 0xF8C000FF CLR_NEW_SEQ_INHIBIT Overrides the automatic hardware locking of the programmed XCVSEQ while an autosequence is underway 2 1 read-write EVENT_TMR_DO_NOT_LATCH Overrides the automatic hardware latching of the Event Timer 3 1 read-write LATCH_PREAMBLE Stickiness Control for Preamble Detection 4 1 read-write 0 Don't make PREAMBLE_DET and SFD_DET bits of PHY_STS (SEQ_STATE) Register "sticky", i.e, these status bits reflect the realtime, dynamic state of preamble_detect and sfd_detect #0 1 Make PREAMBLE_DET and SFD_DET bits of PHY_STS (SEQ_STATE) Register "sticky", i.e.,occurrences of preamble and SFD detection are latched and held until the start of the next autosequence #1 NO_RX_RECYCLE Disable Automatic RX Sequence Recycling 5 1 read-write FORCE_CRC_ERROR Induce a CRC Error in Transmitted Packets 6 1 read-write 0 normal operation #0 1 Force the next transmitted packet to have a CRC error #1 CONTINUOUS_EN Enable Continuous TX or RX Mode 7 1 read-write 0 normal operation #0 1 Continuous TX or RX mode is enabled (depending on XCVSEQ setting). #1 XCVSEQ_ACTUAL Indicates the programmed sequence that has been recognized by the ZSM Sequence Manager 8 3 read-only SEQ_IDLE ZSM Sequence Idle Indicator 11 1 read-only NEW_SEQ_INHIBIT New Sequence Inhibit 12 1 read-only RX_TIMEOUT_PENDING Indicates a TMR3 RX Timeout is Pending 13 1 read-only RX_MODE RX Operation in Progress 14 1 read-only TMR2_SEQ_TRIG_ARMED indicates that TMR2 has been programmed and is armed to trigger a new autosequence 15 1 read-only SEQ_T_STATUS Status of the just-completed or ongoing Sequence T or Sequence TR 16 6 read-only SW_ABORTED Autosequence has terminated due to a Software abort. 24 1 read-only TC3_ABORTED autosequence has terminated due to an TMR3 timeout 25 1 read-only PLL_ABORTED Autosequence has terminated due to an PLL unlock event 26 1 read-only ACKDELAY ACK DELAY 0x7C 32 read-write 0x7 0xFFFFFFFF ACKDELAY ACK Delay 0 6 read-write TXDELAY TX Delay 8 6 read-write FILTERFAIL_CODE FILTER FAIL CODE 0x80 32 read-write 0 0xFFFFFC00 FILTERFAIL_CODE Filter Fail Code 0 10 read-only FILTERFAIL_PAN_SEL PAN Selector for Filter Fail Code 15 1 read-write 0 FILTERFAIL_CODE[9:0] will report the FILTERFAIL status of PAN0 #0 1 FILTERFAIL_CODE[9:0] will report the FILTERFAIL status of PAN1 #1 RX_WTR_MARK RECEIVE WATER MARK 0x84 32 read-write 0xFF 0xFFFFFFFF RX_WTR_MARK RECEIVE WATER MARK 0 8 read-write SLOT_PRELOAD SLOT PRELOAD 0x8C 32 read-write 0x74 0xFFFFFFFF SLOT_PRELOAD Slotted Mode Preload 0 8 read-write SEQ_STATE 802.15.4 SEQUENCE STATE 0x90 32 read-only 0 0xC000C0E0 SEQ_STATE ZSM Sequence State 0 5 read-only PREAMBLE_DET Preamble Detected 8 1 read-only SFD_DET SFD Detected 9 1 read-only FILTERFAIL_FLAG_SEL Consolidated Filter Fail Flag 10 1 read-only CRCVALID CRC Valid Indicator 11 1 read-only 0 Rx FCS != calculated CRC (incorrect) #0 1 Rx FCS = calculated CRC (correct) #1 PLL_ABORT Raw PLL Abort Signal 12 1 read-only PLL_ABORTED Autosequence has terminated due to an PLL unlock event 13 1 read-only RX_BYTE_COUNT Realtime Received Byte Count 16 8 read-only CCCA_BUSY_CNT Number of CCA Measurements resulting in Busy Channel 24 6 read-only TMR_PRESCALE TIMER PRESCALER 0x94 32 read-write 0x5 0xFFFFFFFF TMR_PRESCALE Timer Prescaler 0 3 read-write 010 500kHz (33.55 S) #010 011 250kHz (67.11 S) #011 100 125kHz (134.22 S) #100 101 62.5kHz (268.44 S) -- default #101 110 31.25kHz (536.87 S) #110 111 15.625kHz (1073.74 S) #111 LENIENCY_LSB LENIENCY LSB 0x98 32 read-write 0 0xFFFFFFFF LENIENCY_LSB Leniency LSB Register 0 32 read-write LENIENCY_MSB LENIENCY MSB 0x9C 32 read-write 0 0xFFFFFFFF LENIENCY_MSB Leniency MSB Register 0 8 read-write PART_ID PART ID 0xA0 32 read-only 0x2 0xFFFFFFFF PART_ID 802.15.4 Part ID 0 8 read-only PKT_BUFFER_TX0 Packet Buffer TX 0x100 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX1 Packet Buffer TX 0x102 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX2 Packet Buffer TX 0x104 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX3 Packet Buffer TX 0x106 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX4 Packet Buffer TX 0x108 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX5 Packet Buffer TX 0x10A 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX6 Packet Buffer TX 0x10C 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX7 Packet Buffer TX 0x10E 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX8 Packet Buffer TX 0x110 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX9 Packet Buffer TX 0x112 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX10 Packet Buffer TX 0x114 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX11 Packet Buffer TX 0x116 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX12 Packet Buffer TX 0x118 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX13 Packet Buffer TX 0x11A 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX14 Packet Buffer TX 0x11C 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX15 Packet Buffer TX 0x11E 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX16 Packet Buffer TX 0x120 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX17 Packet Buffer TX 0x122 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX18 Packet Buffer TX 0x124 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX19 Packet Buffer TX 0x126 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX20 Packet Buffer TX 0x128 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX21 Packet Buffer TX 0x12A 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX22 Packet Buffer TX 0x12C 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX23 Packet Buffer TX 0x12E 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX24 Packet Buffer TX 0x130 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX25 Packet Buffer TX 0x132 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX26 Packet Buffer TX 0x134 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX27 Packet Buffer TX 0x136 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX28 Packet Buffer TX 0x138 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX29 Packet Buffer TX 0x13A 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX30 Packet Buffer TX 0x13C 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX31 Packet Buffer TX 0x13E 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX32 Packet Buffer TX 0x140 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX33 Packet Buffer TX 0x142 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX34 Packet Buffer TX 0x144 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX35 Packet Buffer TX 0x146 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX36 Packet Buffer TX 0x148 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX37 Packet Buffer TX 0x14A 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX38 Packet Buffer TX 0x14C 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX39 Packet Buffer TX 0x14E 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX40 Packet Buffer TX 0x150 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX41 Packet Buffer TX 0x152 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX42 Packet Buffer TX 0x154 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX43 Packet Buffer TX 0x156 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX44 Packet Buffer TX 0x158 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX45 Packet Buffer TX 0x15A 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX46 Packet Buffer TX 0x15C 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX47 Packet Buffer TX 0x15E 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX48 Packet Buffer TX 0x160 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX49 Packet Buffer TX 0x162 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX50 Packet Buffer TX 0x164 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX51 Packet Buffer TX 0x166 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX52 Packet Buffer TX 0x168 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX53 Packet Buffer TX 0x16A 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX54 Packet Buffer TX 0x16C 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX55 Packet Buffer TX 0x16E 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX56 Packet Buffer TX 0x170 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX57 Packet Buffer TX 0x172 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX58 Packet Buffer TX 0x174 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX59 Packet Buffer TX 0x176 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX60 Packet Buffer TX 0x178 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX61 Packet Buffer TX 0x17A 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX62 Packet Buffer TX 0x17C 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_TX63 Packet Buffer TX 0x17E 16 read-write 0 0 PKT_BUFFER_TX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX0 Packet Buffer RX 0x180 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX1 Packet Buffer RX 0x182 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX2 Packet Buffer RX 0x184 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX3 Packet Buffer RX 0x186 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX4 Packet Buffer RX 0x188 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX5 Packet Buffer RX 0x18A 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX6 Packet Buffer RX 0x18C 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX7 Packet Buffer RX 0x18E 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX8 Packet Buffer RX 0x190 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX9 Packet Buffer RX 0x192 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX10 Packet Buffer RX 0x194 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX11 Packet Buffer RX 0x196 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX12 Packet Buffer RX 0x198 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX13 Packet Buffer RX 0x19A 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX14 Packet Buffer RX 0x19C 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX15 Packet Buffer RX 0x19E 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX16 Packet Buffer RX 0x1A0 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX17 Packet Buffer RX 0x1A2 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX18 Packet Buffer RX 0x1A4 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX19 Packet Buffer RX 0x1A6 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX20 Packet Buffer RX 0x1A8 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX21 Packet Buffer RX 0x1AA 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX22 Packet Buffer RX 0x1AC 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX23 Packet Buffer RX 0x1AE 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX24 Packet Buffer RX 0x1B0 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX25 Packet Buffer RX 0x1B2 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX26 Packet Buffer RX 0x1B4 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX27 Packet Buffer RX 0x1B6 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX28 Packet Buffer RX 0x1B8 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX29 Packet Buffer RX 0x1BA 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX30 Packet Buffer RX 0x1BC 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX31 Packet Buffer RX 0x1BE 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX32 Packet Buffer RX 0x1C0 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX33 Packet Buffer RX 0x1C2 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX34 Packet Buffer RX 0x1C4 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX35 Packet Buffer RX 0x1C6 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX36 Packet Buffer RX 0x1C8 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX37 Packet Buffer RX 0x1CA 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX38 Packet Buffer RX 0x1CC 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX39 Packet Buffer RX 0x1CE 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX40 Packet Buffer RX 0x1D0 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX41 Packet Buffer RX 0x1D2 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX42 Packet Buffer RX 0x1D4 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX43 Packet Buffer RX 0x1D6 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX44 Packet Buffer RX 0x1D8 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX45 Packet Buffer RX 0x1DA 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX46 Packet Buffer RX 0x1DC 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX47 Packet Buffer RX 0x1DE 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX48 Packet Buffer RX 0x1E0 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX49 Packet Buffer RX 0x1E2 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX50 Packet Buffer RX 0x1E4 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX51 Packet Buffer RX 0x1E6 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX52 Packet Buffer RX 0x1E8 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX53 Packet Buffer RX 0x1EA 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX54 Packet Buffer RX 0x1EC 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX55 Packet Buffer RX 0x1EE 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX56 Packet Buffer RX 0x1F0 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX57 Packet Buffer RX 0x1F2 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX58 Packet Buffer RX 0x1F4 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX59 Packet Buffer RX 0x1F6 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX60 Packet Buffer RX 0x1F8 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX61 Packet Buffer RX 0x1FA 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX62 Packet Buffer RX 0x1FC 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write PKT_BUFFER_RX63 Packet Buffer RX 0x1FE 16 read-write 0 0 PKT_BUFFER_RX Packet Buffer Entry 0 16 read-write ANT_REGS ANT 0x4005E000 0 0x180 registers IRQ_CTRL IRQ CONTROL 0 32 read-write 0 0x7FFFFC00 SEQ_END_IRQ Sequence End Interrupt 0 1 read-write 0 Sequence End Interrupt is not asserted. #0 1 Sequence End Interrupt is asserted. #1 TX_IRQ TX Interrupt 1 1 read-write 0 TX Interrupt is not asserted. #0 1 TX Interrupt is asserted. #1 RX_IRQ RX Interrupt 2 1 read-write 0 RX Interrupt is not asserted. #0 1 RX Interrupt is asserted. #1 NTW_ADR_IRQ Network Address Match Interrupt 3 1 read-write 0 Network Address Match Interrupt is not asserted. #0 1 Network Address Match Interrupt is asserted. #1 T1_IRQ Timer1 (T1) Compare Interrupt 4 1 read-write 0 Timer1 (T1) Compare Interrupt is not asserted. #0 1 Timer1 (T1) Compare Interrupt is asserted. #1 T2_IRQ Timer2 (T2) Compare Interrupt 5 1 read-write 0 Timer2 (T2) Compare Interrupt is not asserted. #0 1 Timer2 (T2) Compare Interrupt is asserted. #1 PLL_UNLOCK_IRQ PLL Unlock Interrupt 6 1 read-write 0 PLL Unlock Interrupt is not asserted. #0 1 PLL Unlock Interrupt is asserted. #1 WAKE_IRQ Wake Interrrupt 7 1 read-write 0 Wake Interrupt is not asserted. #0 1 Wake Interrupt is asserted. #1 RX_WATERMARK_IRQ RX Watermark Interrupt 8 1 read-write 0 RX Watermark Interrupt is not asserted. #0 1 RX Watermark Interrupt is asserted. #1 TSM_IRQ TSM Interrupt 9 1 read-only 0 TSM0_IRQ and TSM1_IRQ are both clear. #0 1 Indicates TSM0_IRQ or TSM1_IRQ is set in XCVR_STATUS. #1 SEQ_END_IRQ_EN SEQ_END_IRQ Enable 16 1 read-write 0 Sequence End Interrupt is not enabled. #0 1 Sequence End Interrupt is enabled. #1 TX_IRQ_EN TX_IRQ Enable 17 1 read-write 0 TX Interrupt is not enabled. #0 1 TX Interrupt is enabled. #1 RX_IRQ_EN RX_IRQ Enable 18 1 read-write 0 RX Interrupt is not enabled. #0 1 RX Interrupt is enabled. #1 NTW_ADR_IRQ_EN NTW_ADR_IRQ Enable 19 1 read-write 0 Network Address Match Interrupt is not enabled. #0 1 Network Address Match Interrupt is enabled. #1 T1_IRQ_EN T1_IRQ Enable 20 1 read-write 0 Timer1 (T1) Compare Interrupt is not enabled. #0 1 Timer1 (T1) Compare Interrupt is enabled. #1 T2_IRQ_EN T2_IRQ Enable 21 1 read-write 0 Timer1 (T2) Compare Interrupt is not enabled. #0 1 Timer1 (T2) Compare Interrupt is enabled. #1 PLL_UNLOCK_IRQ_EN PLL_UNLOCK_IRQ Enable 22 1 read-write 0 PLL Unlock Interrupt is not enabled. #0 1 PLL Unlock Interrupt is enabled. #1 WAKE_IRQ_EN WAKE_IRQ Enable 23 1 read-write 0 Wake Interrupt is not enabled. #0 1 Wake Interrupt is enabled. #1 RX_WATERMARK_IRQ_EN RX_WATERMARK_IRQ Enable 24 1 read-write 0 RX Watermark Interrupt is not enabled. #0 1 RX Watermark Interrupt is enabled. #1 TSM_IRQ_EN TSM_IRQ Enable 25 1 read-write 0 TSM Interrupt is not enabled. #0 1 TSM Interrupt is enabled. #1 ANT_IRQ_EN ANT_IRQ Master Enable 26 1 read-write 0 All ANT Interrupts are disabled. #0 1 All ANT Interrupts can be enabled. #1 CRC_IGNORE CRC Ignore 27 1 read-write 0 RX_IRQ will not be asserted for a received packet which fails CRC verification. #0 1 RX_IRQ will be asserted even for a received packet which fails CRC verification. #1 CRC_VALID CRC Valid 31 1 read-only 0 CRC of RX packet is not valid. #0 1 CRC of RX packet is valid. #1 EVENT_TMR EVENT TIMER 0x4 32 read-write 0 0xFF000000 EVENT_TMR Event Timer 0 24 read-write EVENT_TMR_LD Event Timer Load 24 1 write-only EVENT_TMR_ADD Event Timer Add 25 1 write-only T1_CMP T1 COMPARE 0x8 32 read-write 0xFFFFFF 0xFFFFFFFF T1_CMP Timer1 (T1) Compare Value 0 24 read-write T1_CMP_EN Timer1 (T1) Compare Enable 24 1 read-write T2_CMP T2 COMPARE 0xC 32 read-write 0xFFFFFF 0xFFFFFFFF T2_CMP Timer2 (T2) Compare Value 0 24 read-write T2_CMP_EN Timer2 (T2) Compare Enable 24 1 read-write TIMESTAMP TIMESTAMP 0x10 32 read-only 0 0xFF000000 TIMESTAMP Received Packet Timestamp 0 24 read-only XCVR_CTRL TRANSCEIVER CONTROL 0x14 32 read-write 0x121200 0x78FFFFFF SEQCMD Sequence Commands 0 4 read-write 0x0 No Action #0000 0x1 TX Start Now #0001 0x2 TX Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) #0010 0x3 TX Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) #0011 0x4 TX Cancel -- Cancels pending TX events but do not abort a TX-in-progress #0100 0x5 RX Start Now #0101 0x6 RX Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) #0110 0x7 RX Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) #0111 0x8 RX Stop @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) #1000 0x9 RX Stop @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) #1001 0xA RX Cancel -- Cancels pending RX events but do not abort a RX-in-progress #1010 0xB Abort All - Cancels all pending events and abort any sequence-in-progress #1011 TX_PKT_LENGTH Transmit Packet Length 8 6 read-write RX_PKT_LENGTH Receive Packet Length 16 6 read-write CMDDEC_CS Command Decode 24 3 read-only XCVR_BUSY Transceiver Busy 31 1 read-only 0 IDLE #0 1 BUSY #1 XCVR_STS TRANSCEIVER STATUS 0x18 32 read-only 0 0xFF006000 TX_START_T1_PEND TX T1 Start Pending Status 0 1 read-only TX_START_T2_PEND TX T2 Start Pending Status 1 1 read-only TX_IN_WARMUP TX Warmup Status 2 1 read-only TX_IN_PROGRESS TX in Progress Status 3 1 read-only TX_IN_WARMDN TX Warmdown Status 4 1 read-only RX_START_T1_PEND RX T1 Start Pending Status 5 1 read-only RX_START_T2_PEND RX T2 Start Pending Status 6 1 read-only RX_STOP_T1_PEND RX T1 Stop Pending Status 7 1 read-only RX_STOP_T2_PEND RX T2 Start Pending Status 8 1 read-only RX_IN_WARMUP RX Warmup Status 9 1 read-only RX_IN_SEARCH RX Search Status 10 1 read-only RX_IN_PROGRESS RX in Progress Status 11 1 read-only RX_IN_WARMDN RX Warmdown Status 12 1 read-only CRC_VALID CRC Valid Indicator 15 1 read-only 0 CRC is not valid for RX packet. #0 1 CRC is valid for RX packet. #1 RSSI Received Signal Stength Indicator 16 8 read-only XCVR_CFG TRANSCEIVER CONFIGURATION 0x1C 32 read-write 0 0xFF0000FF TX_WHITEN_DIS TX Whitening Disable 0 1 read-write RX_DEWHITEN_DIS RX De-Whitening Disable 1 1 read-write SW_CRC_EN Software CRC Enable 2 1 read-write PREAMBLE_SZ Preamble Size 4 2 read-write TX_WARMUP Transmit Warmup Time 8 8 read-only RX_WARMUP Receive Warmup Time 16 8 read-only CHANNEL_NUM CHANNEL NUMBER 0x20 32 read-write 0 0xFFFFFFFF CHANNEL_NUM Channel Number 0 7 read-write TX_POWER TRANSMIT POWER 0x24 32 read-write 0 0xFFFFFFFF TX_POWER Transmit Power 0 6 read-write NTW_ADR_CTRL NETWORK ADDRESS CONTROL 0x28 32 read-write 0x5500 0xFFFFFF0F NTW_ADR_EN Network Address Match Enable 0 4 read-write NTW_ADR_MCH Network Address Match Status 4 4 read-only NTW_ADR0_SZ Network Address Match Size 8 2 read-write 0 1 octet #00 1 2 octets #01 2 3 octets #10 3 4 octets #11 NTW_ADR1_SZ Network Address Match Size 10 2 read-write 0 1 octet #00 1 2 octets #01 2 3 octets #10 3 4 octets #11 NTW_ADR2_SZ Network Address Match Size 12 2 read-write 0 1 octet #00 1 2 octets #01 2 3 octets #10 3 4 octets #11 NTW_ADR3_SZ Network Address Match Size 14 2 read-write 0 1 octet #00 1 2 octets #01 2 3 octets #10 3 4 octets #11 NTW_ADR_THR0 Network Address Match Bit Error Threshold 0 16 3 read-write NTW_ADR_THR1 Network Address Match Bit Error Threshold 1 20 3 read-write NTW_ADR_THR2 Network Address Match Bit Error Threshold 2 24 3 read-write NTW_ADR_THR3 Network Address Match Bit Error Threshold 3 28 3 read-write NTW_ADR_0 NETWORK ADDRESS 0 0x2C 32 read-write 0x55555555 0xFFFFFFFF NTW_ADR_0 Network Address 0 0 32 read-write NTW_ADR_1 NETWORK ADDRESS 1 0x30 32 read-write 0x55555555 0xFFFFFFFF NTW_ADR_1 Network Address 1 0 32 read-write NTW_ADR_2 NETWORK ADDRESS 2 0x34 32 read-write 0x55555555 0xFFFFFFFF NTW_ADR_2 Network Address 2 0 32 read-write NTW_ADR_3 NETWORK ADDRESS 3 0x38 32 read-write 0x55555555 0xFFFFFFFF NTW_ADR_3 Network Address 2 0 32 read-write RX_WATERMARK RX WATERMARK 0x3C 32 read-write 0x7F 0xFF80FFFF RX_WATERMARK RX Watermark 0 7 read-write BYTE_COUNTER Byte Counter 16 7 read-only 1xxxxxx When less than 0, Preamble byte(s), TX only #1xxxxxx 0 First Byte of Network Address #0 1 Second Byte of Network Address #1 DSM_CTRL DSM CONTROL 0x40 32 read-write 0 0xFFFFFFFE ANT_SLEEP_EN ANT DSM Sleep Enable 0 1 write-only PART_ID PART ID 0x44 32 read-only 0 0xFFFFFFFF PART_ID Part ID 0 8 read-only PACKET_BUFFER_0 PACKET BUFFER 0x100 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1 PACKET BUFFER 0x102 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_2 PACKET BUFFER 0x104 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_3 PACKET BUFFER 0x106 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_4 PACKET BUFFER 0x108 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_5 PACKET BUFFER 0x10A 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_6 PACKET BUFFER 0x10C 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_7 PACKET BUFFER 0x10E 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_8 PACKET BUFFER 0x110 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_9 PACKET BUFFER 0x112 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_10 PACKET BUFFER 0x114 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_11 PACKET BUFFER 0x116 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_12 PACKET BUFFER 0x118 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_13 PACKET BUFFER 0x11A 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_14 PACKET BUFFER 0x11C 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_15 PACKET BUFFER 0x11E 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_16 PACKET BUFFER 0x120 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_17 PACKET BUFFER 0x122 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_18 PACKET BUFFER 0x124 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_19 PACKET BUFFER 0x126 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_20 PACKET BUFFER 0x128 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_21 PACKET BUFFER 0x12A 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_22 PACKET BUFFER 0x12C 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_23 PACKET BUFFER 0x12E 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_24 PACKET BUFFER 0x130 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_25 PACKET BUFFER 0x132 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_26 PACKET BUFFER 0x134 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_27 PACKET BUFFER 0x136 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_28 PACKET BUFFER 0x138 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_29 PACKET BUFFER 0x13A 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_30 PACKET BUFFER 0x13C 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_31 PACKET BUFFER 0x13E 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_32 PACKET BUFFER 0x140 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_33 PACKET BUFFER 0x142 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_34 PACKET BUFFER 0x144 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_35 PACKET BUFFER 0x146 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_36 PACKET BUFFER 0x148 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_37 PACKET BUFFER 0x14A 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_38 PACKET BUFFER 0x14C 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_39 PACKET BUFFER 0x14E 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_40 PACKET BUFFER 0x150 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_41 PACKET BUFFER 0x152 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_42 PACKET BUFFER 0x154 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_43 PACKET BUFFER 0x156 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_44 PACKET BUFFER 0x158 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_45 PACKET BUFFER 0x15A 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_46 PACKET BUFFER 0x15C 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_47 PACKET BUFFER 0x15E 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_48 PACKET BUFFER 0x160 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_49 PACKET BUFFER 0x162 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_50 PACKET BUFFER 0x164 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_51 PACKET BUFFER 0x166 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_52 PACKET BUFFER 0x168 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_53 PACKET BUFFER 0x16A 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_54 PACKET BUFFER 0x16C 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_55 PACKET BUFFER 0x16E 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_56 PACKET BUFFER 0x170 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_57 PACKET BUFFER 0x172 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_58 PACKET BUFFER 0x174 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_59 PACKET BUFFER 0x176 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_60 PACKET BUFFER 0x178 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_61 PACKET BUFFER 0x17A 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_62 PACKET BUFFER 0x17C 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_63 PACKET BUFFER 0x17E 16 read-write 0 0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write GENFSK_REGS GENERIC_FSK 0x4005F000 0 0x90 registers IRQ_CTRL IRQ CONTROL 0 32 read-write 0 0x7FFFFC00 SEQ_END_IRQ Sequence End Interrupt 0 1 read-write 0 Sequence End Interrupt is not asserted. #0 1 Sequence End Interrupt is asserted. #1 TX_IRQ TX Interrupt 1 1 read-write 0 TX Interrupt is not asserted. #0 1 TX Interrupt is asserted. #1 RX_IRQ RX Interrupt 2 1 read-write 0 RX Interrupt is not asserted. #0 1 RX Interrupt is asserted. #1 NTW_ADR_IRQ Network Address Match Interrupt 3 1 read-write 0 Network Address Match Interrupt is not asserted. #0 1 Network Address Match Interrupt is asserted. #1 T1_IRQ Timer1 (T1) Compare Interrupt 4 1 read-write 0 Timer1 (T1) Compare Interrupt is not asserted. #0 1 Timer1 (T1) Compare Interrupt is asserted. #1 T2_IRQ Timer2 (T2) Compare Interrupt 5 1 read-write 0 Timer2 (T2) Compare Interrupt is not asserted. #0 1 Timer2 (T2) Compare Interrupt is asserted. #1 PLL_UNLOCK_IRQ PLL Unlock Interrupt 6 1 read-write 0 PLL Unlock Interrupt is not asserted. #0 1 PLL Unlock Interrupt is asserted. #1 WAKE_IRQ Wake Interrrupt 7 1 read-write 0 Wake Interrupt is not asserted. #0 1 Wake Interrupt is asserted. #1 RX_WATERMARK_IRQ RX Watermark Interrupt 8 1 read-write 0 RX Watermark Interrupt is not asserted. #0 1 RX Watermark Interrupt is asserted. #1 TSM_IRQ TSM Interrupt 9 1 read-only 0 TSM0_IRQ and TSM1_IRQ are both clear. #0 1 Indicates TSM0_IRQ or TSM1_IRQ is set in XCVR_STATUS. #1 SEQ_END_IRQ_EN SEQ_END_IRQ Enable 16 1 read-write 0 Sequence End Interrupt is not enabled. #0 1 Sequence End Interrupt is enabled. #1 TX_IRQ_EN TX_IRQ Enable 17 1 read-write 0 TX Interrupt is not enabled. #0 1 TX Interrupt is enabled. #1 RX_IRQ_EN RX_IRQ Enable 18 1 read-write 0 RX Interrupt is not enabled. #0 1 RX Interrupt is enabled. #1 NTW_ADR_IRQ_EN NTW_ADR_IRQ Enable 19 1 read-write 0 Network Address Match Interrupt is not enabled. #0 1 Network Address Match Interrupt is enabled. #1 T1_IRQ_EN T1_IRQ Enable 20 1 read-write 0 Timer1 (T1) Compare Interrupt is not enabled. #0 1 Timer1 (T1) Compare Interrupt is enabled. #1 T2_IRQ_EN T2_IRQ Enable 21 1 read-write 0 Timer1 (T2) Compare Interrupt is not enabled. #0 1 Timer1 (T2) Compare Interrupt is enabled. #1 PLL_UNLOCK_IRQ_EN PLL_UNLOCK_IRQ Enable 22 1 read-write 0 PLL Unlock Interrupt is not enabled. #0 1 PLL Unlock Interrupt is enabled. #1 WAKE_IRQ_EN WAKE_IRQ Enable 23 1 read-write 0 Wake Interrupt is not enabled. #0 1 Wake Interrupt is enabled. #1 RX_WATERMARK_IRQ_EN RX_WATERMARK_IRQ Enable 24 1 read-write 0 RX Watermark Interrupt is not enabled. #0 1 RX Watermark Interrupt is enabled. #1 TSM_IRQ_EN TSM_IRQ Enable 25 1 read-write 0 TSM Interrupt is not enabled. #0 1 TSM Interrupt is enabled. #1 GENERIC_FSK_IRQ_EN GENERIC_FSK_IRQ Master Enable 26 1 read-write 0 All GENERIC_FSK Interrupts are disabled. #0 1 All GENERIC_FSK Interrupts can be enabled. #1 CRC_IGNORE CRC Ignore 27 1 read-write 0 RX_IRQ will not be asserted for a received packet which fails CRC verification. #0 1 RX_IRQ will be asserted even for a received packet which fails CRC verification. #1 CRC_VALID CRC Valid 31 1 read-only 0 CRC of RX packet is not valid. #0 1 CRC of RX packet is valid. #1 EVENT_TMR EVENT TIMER 0x4 32 read-write 0 0xFF000000 EVENT_TMR Event Timer 0 24 read-write EVENT_TMR_LD Event Timer Load 24 1 write-only EVENT_TMR_ADD Event Timer Add 25 1 write-only T1_CMP T1 COMPARE 0x8 32 read-write 0xFFFFFF 0xFFFFFFFF T1_CMP Timer1 (T1) Compare Value 0 24 read-write T1_CMP_EN Timer1 (T1) Compare Enable 24 1 read-write T2_CMP T2 COMPARE 0xC 32 read-write 0xFFFFFF 0xFFFFFFFF T2_CMP Timer2 (T2) Compare Value 0 24 read-write T2_CMP_EN Timer2 (T2) Compare Enable 24 1 read-write TIMESTAMP TIMESTAMP 0x10 32 read-only 0 0xFF000000 TIMESTAMP Received Packet Timestamp 0 24 read-only XCVR_CTRL TRANSCEIVER CONTROL 0x14 32 read-write 0 0x78FFFFFF SEQCMD Sequence Commands 0 4 read-write 0x0 No Action #0000 0x1 TX Start Now #0001 0x2 TX Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) #0010 0x3 TX Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) #0011 0x4 TX Cancel -- Cancels pending TX events but do not abort a TX-in-progress #0100 0x5 RX Start Now #0101 0x6 RX Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) #0110 0x7 RX Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) #0111 0x8 RX Stop @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) #1000 0x9 RX Stop @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) #1001 0xA RX Cancel -- Cancels pending RX events but do not abort a RX-in-progress #1010 0xB Abort All - Cancels all pending events and abort any sequence-in-progress #1011 CMDDEC_CS Command Decode 24 3 read-only XCVR_BUSY Transceiver Busy 31 1 read-only 0 IDLE #0 1 BUSY #1 XCVR_STS TRANSCEIVER STATUS 0x18 32 read-only 0 0x2000 TX_START_T1_PEND TX T1 Start Pending Status 0 1 read-only TX_START_T2_PEND TX T2 Start Pending Status 1 1 read-only TX_IN_WARMUP TX Warmup Status 2 1 read-only TX_IN_PROGRESS TX in Progress Status 3 1 read-only TX_IN_WARMDN TX Warmdown Status 4 1 read-only RX_START_T1_PEND RX T1 Start Pending Status 5 1 read-only RX_START_T2_PEND RX T2 Start Pending Status 6 1 read-only RX_STOP_T1_PEND RX T1 Stop Pending Status 7 1 read-only RX_STOP_T2_PEND RX T2 Start Pending Status 8 1 read-only RX_IN_WARMUP RX Warmup Status 9 1 read-only RX_IN_SEARCH RX Search Status 10 1 read-only RX_IN_PROGRESS RX in Progress Status 11 1 read-only RX_IN_WARMDN RX Warmdown Status 12 1 read-only LQI_VALID LQI Valid Indicator 14 1 read-only 0 LQI is not yet valid for RX packet. #0 1 LQI is valid for RX packet. #1 CRC_VALID CRC Valid Indicator 15 1 read-only 0 CRC is not valid for RX packet. #0 1 CRC is valid for RX packet. #1 RSSI Received Signal Stength Indicator, in dBm 16 8 read-only LQI Link Quality Indicator 24 8 read-only XCVR_CFG TRANSCEIVER CONFIGURATION 0x1C 32 read-write 0 0xFF0000FF TX_WHITEN_DIS TX Whitening Disable 0 1 read-write RX_DEWHITEN_DIS RX De-Whitening Disable 1 1 read-write SW_CRC_EN Software CRC Enable 2 1 read-write PREAMBLE_SZ Preamble Size 4 3 read-write TX_WARMUP Transmit Warmup Time 8 8 read-only RX_WARMUP Receive Warmup Time 16 8 read-only CHANNEL_NUM CHANNEL NUMBER 0x20 32 read-write 0 0xFFFFFFFF CHANNEL_NUM Channel Number 0 7 read-write TX_POWER TRANSMIT POWER 0x24 32 read-write 0 0xFFFFFFFF TX_POWER Transmit Power 0 6 read-write NTW_ADR_CTRL NETWORK ADDRESS CONTROL 0x28 32 read-write 0x5500 0xFFFFFF0F NTW_ADR_EN Network Address Enable 0 4 read-write 0001 Enable Network Address 0 for correlation #0001 0010 Enable Network Address 1 for correlation #0010 0100 Enable Network Address 2 for correlation #0100 1000 Enable Network Address 3 for correlation #1000 NTW_ADR_MCH Network Address Match 4 4 read-only 0001 Network Address 0 has matched #0001 0010 Network Address 1 has matched #0010 0100 Network Address 2 has matched #0100 1000 Network Address 3 has matched #1000 NTW_ADR0_SZ Network Address 0 Size 8 2 read-write 0 Network Address 0 requires a 8-bit correlation #00 1 Network Address 0 requires a 16-bit correlation #01 2 Network Address 0 requires a 24-bit correlation #10 3 Network Address 0 requires a 32-bit correlation #11 NTW_ADR1_SZ Network Address 1 Size 10 2 read-write 0 Network Address 1 requires a 8-bit correlation #00 1 Network Address 1 requires a 16-bit correlation #01 2 Network Address 1 requires a 24-bit correlation #10 3 Network Address 1 requires a 32-bit correlation #11 NTW_ADR2_SZ Network Address 2 Size 12 2 read-write 0 Network Address 2 requires a 8-bit correlation #00 1 Network Address 2 requires a 16-bit correlation #01 2 Network Address 2 requires a 24-bit correlation #10 3 Network Address 2 requires a 32-bit correlation #11 NTW_ADR3_SZ Network Address 3 Size 14 2 read-write 0 Network Address 3 requires a 8-bit correlation #00 1 Network Address 3 requires a 16-bit correlation #01 2 Network Address 3 requires a 24-bit correlation #10 3 Network Address 3 requires a 32-bit correlation #11 NTW_ADR_THR0 Network Address 0 Threshold 16 3 read-write NTW_ADR_THR1 Network Address 1 Threshold 20 3 read-write NTW_ADR_THR2 Network Address 2 Threshold 24 3 read-write NTW_ADR_THR3 Network Address 3 Threshold 28 3 read-write NTW_ADR_0 NETWORK ADDRESS 0 0x2C 32 read-write 0x55555555 0xFFFFFFFF NTW_ADR_0 Network Address 0 0 32 read-write NTW_ADR_1 NETWORK ADDRESS 1 0x30 32 read-write 0x55555555 0xFFFFFFFF NTW_ADR_1 Network Address 1 0 32 read-write NTW_ADR_2 NETWORK ADDRESS 2 0x34 32 read-write 0x55555555 0xFFFFFFFF NTW_ADR_2 Network Address 2 0 32 read-write NTW_ADR_3 NETWORK ADDRESS 3 0x38 32 read-write 0x55555555 0xFFFFFFFF NTW_ADR_3 Network Address 2 0 32 read-write RX_WATERMARK RECEIVE WATERMARK 0x3C 32 read-write 0xFFF 0xE000FFFF RX_WATERMARK Receive Watermark 0 13 read-write BYTE_COUNTER Byte Counter 16 13 read-only DSM_CTRL DSM CONTROL 0x40 32 read-write 0 0xFFFFFFFE GENERIC_FSK_SLEEP_EN GENERIC_FSK DSM Sleep Enable 0 1 write-only PART_ID PART ID 0x44 32 read-only 0 0xFFFFFFFF PART_ID Part ID 0 8 read-only PACKET_CFG PACKET CONFIGURATION 0x60 32 read-write 0x40 0x7F7F7FFF LENGTH_SZ LENGTH Size 0 5 read-write LENGTH_BIT_ORD LENGTH Bit Order 5 1 read-write 0 LS Bit First #0 1 MS Bit First #1 SYNC_ADDR_SZ Sync Address Size 6 2 read-write LENGTH_ADJ Length Adjustment 8 6 read-write LENGTH_FAIL Maximum Length Violated Status Bit 15 1 read-only H0_SZ H0 Size 16 5 read-write H0_FAIL H0 Violated Status Bit 23 1 read-only H1_SZ H1 Size 24 5 read-write H1_FAIL H1 Violated Status Bit 31 1 read-only H0_CFG H0 CONFIGURATION 0x64 32 read-write 0 0xFFFFFFFF H0_MATCH H0 Match Register 0 16 read-write H0_MASK H0 Mask Register 16 16 read-write H1_CFG H1 CONFIGURATION 0x68 32 read-write 0 0xFFFFFFFF H1_MATCH H1 Match Register 0 16 read-write H1_MASK H1 Mask Register 16 16 read-write CRC_CFG CRC CONFIGURATION 0x6C 32 read-write 0x2 0xFFFFFFFF CRC_SZ CRC Size (in octets) 0 3 read-write CRC_START_BYTE Configure CRC Start Point 8 4 read-write CRC_REF_IN CRC Reflect In 16 1 read-write 0 do not manipulate input data stream #0 1 reflect each byte in the input stream bitwise #1 CRC_REF_OUT CRC Reflect Out 17 1 read-write 0 do not manipulate CRC result #0 1 CRC result is to be reflected bitwise (operated on entire word) #1 CRC_BYTE_ORD CRC Byte Order 18 1 read-write 0 LS Byte First #0 1 MS Byte First #1 CRC_INIT CRC INITIALIZATION 0x70 32 read-write 0 0xFFFFFFFF CRC_SEED CRC Seed Value 0 32 read-write CRC_POLY CRC POLYNOMIAL 0x74 32 read-write 0x10210000 0xFFFFFFFF CRC_POLY CRC Polynomial. 0 32 read-write CRC_XOR_OUT CRC XOR OUT 0x78 32 read-write 0 0xFFFFFFFF CRC_XOR_OUT CRC XOR OUT Register 0 32 read-write WHITEN_CFG WHITENER CONFIGURATION 0x7C 32 read-write 0x1FF0918 0xFFFFFFFF WHITEN_START Configure Whitener Start Point 0 2 read-write 0 no whitening #00 1 start whitening at start-of-H0 #01 2 start whitening at start-of-H1 but only if LENGTH > WHITEN_SZ_THR #10 3 start whitening at start-of-payload but only if LENGTH > WHITEN_SZ_THR #11 WHITEN_END Configure end-of-whitening 2 1 read-write 0 end whiten at end-of-payload #0 1 end whiten at end-of-crc #1 WHITEN_B4_CRC Congifure for Whitening-before-CRC 3 1 read-write 0 CRC before whiten/de-whiten #0 1 Whiten/de-whiten before CRC #1 WHITEN_POLY_TYPE Whiten Polynomial Type 4 1 read-write WHITEN_REF_IN Whiten Reflect Input 5 1 read-write WHITEN_PAYLOAD_REINIT Configure for Whitener re-initialization 6 1 read-write 0 Don't re-initialize Whitener LFSR at start-of-payload #0 1 Re-initialize Whitener LFSR at start-of-payload #1 WHITEN_SIZE Length of Whitener LFSR 8 4 read-write MANCHESTER_EN Configure for Manchester Encoding/Decoding 12 1 read-write 0 Disable Manchester encoding (TX) and decoding (RX) #0 1 Enable Manchester encoding (TX) and decoding (RX) #1 MANCHESTER_INV Configure for Inverted Manchester Encoding 13 1 read-write 0 Manchester coding as per 802.3 #0 1 Manchester coding as per 802.3 but with the encoding signal inverted #1 MANCHESTER_START Configure Manchester Encoding Start Point 14 1 read-write 0 Start Manchester coding at start-of-payload #0 1 Start Manchester coding at start-of-header #1 WHITEN_INIT Initialization Value for Whitening/De-whitening 16 9 read-write WHITEN_POLY WHITENER POLYNOMIAL 0x80 32 read-write 0x21 0xFFFFFFFF WHITEN_POLY Whitener Polynomial 0 9 read-write WHITEN_SZ_THR WHITENER SIZE THRESHOLD 0x84 32 read-write 0x800 0xFFFFFFFF WHITEN_SZ_THR Whitener Size Threshold 0 12 read-write LENGTH_MAX Maximum Length for Received Packets 16 7 read-write REC_BAD_PKT Receive Bad Packets 23 1 read-write 0 packets which fail H0, H1, or LENGTH_MAX result in an automatic recycle after the header is received and parsed #0 1 packets which fail H0, H1, or LENGTH_MAX are received in their entirety #1 BITRATE BIT RATE 0x88 32 read-write 0 0xFFFFFFFF BITRATE Bit Rate 0 2 read-write 0 1Mbit/sec #00 1 500Kbit/sec #01 2 250Kbit/sec (not supported if WHITEN_CFG[MANCHESTER_EN]=1 #10 PB_PARTITION PACKET BUFFER PARTITION POINT 0x8C 32 read-write 0x220 0xFFFFFFFF PB_PARTITION Packet Buffer Partition Point 0 11 read-write CMT Carrier Modulator Transmitter CMT_ 0x40062000 0 0xC registers CMT 14 CGH1 CMT Carrier Generator High Data Register 1 0 8 read-write 0 0 PH Primary Carrier High Time Data Value 0 8 read-write CGL1 CMT Carrier Generator Low Data Register 1 0x1 8 read-write 0 0 PL Primary Carrier Low Time Data Value 0 8 read-write CGH2 CMT Carrier Generator High Data Register 2 0x2 8 read-write 0 0 SH Secondary Carrier High Time Data Value 0 8 read-write CGL2 CMT Carrier Generator Low Data Register 2 0x3 8 read-write 0 0 SL Secondary Carrier Low Time Data Value 0 8 read-write OC CMT Output Control Register 0x4 8 read-write 0 0xFF IROPEN IRO Pin Enable 5 1 read-write 0 The IRO signal is disabled. #0 1 The IRO signal is enabled as output. #1 CMTPOL CMT Output Polarity 6 1 read-write 0 The IRO signal is active-low. #0 1 The IRO signal is active-high. #1 IROL IRO Latch Control 7 1 read-write MSC CMT Modulator Status and Control Register 0x5 8 read-write 0 0xFF MCGEN Modulator and Carrier Generator Enable 0 1 read-write 0 Modulator and carrier generator disabled #0 1 Modulator and carrier generator enabled #1 EOCIE End of Cycle Interrupt Enable 1 1 read-write 0 CPU interrupt is disabled. #0 1 CPU interrupt is enabled. #1 FSK FSK Mode Select 2 1 read-write 0 The CMT operates in Time or Baseband mode. #0 1 The CMT operates in FSK mode. #1 BASE Baseband Enable 3 1 read-write 0 Baseband mode is disabled. #0 1 Baseband mode is enabled. #1 EXSPC Extended Space Enable 4 1 read-write 0 Extended space is disabled. #0 1 Extended space is enabled. #1 CMTDIV CMT Clock Divide Prescaler 5 2 read-write 00 IF * 1 #00 01 IF * 2 #01 10 IF * 4 #10 11 IF * 8 #11 EOCF End Of Cycle Status Flag 7 1 read-only 0 End of modulation cycle has not occured since the flag last cleared. #0 1 End of modulator cycle has occurred. #1 CMD1 CMT Modulator Data Register Mark High 0x6 8 read-write 0 0 MB MB[15:8] 0 8 read-write CMD2 CMT Modulator Data Register Mark Low 0x7 8 read-write 0 0 MB MB[7:0] 0 8 read-write CMD3 CMT Modulator Data Register Space High 0x8 8 read-write 0 0 SB SB[15:8] 0 8 read-write CMD4 CMT Modulator Data Register Space Low 0x9 8 read-write 0 0 SB SB[7:0] 0 8 read-write PPS CMT Primary Prescaler Register 0xA 8 read-write 0 0xFF PPSDIV Primary Prescaler Divider 0 4 read-write 0000 Bus clock * 1 #0000 0001 Bus clock * 2 #0001 0010 Bus clock * 3 #0010 0011 Bus clock * 4 #0011 0100 Bus clock * 5 #0100 0101 Bus clock * 6 #0101 0110 Bus clock * 7 #0110 0111 Bus clock * 8 #0111 1000 Bus clock * 9 #1000 1001 Bus clock * 10 #1001 1010 Bus clock * 11 #1010 1011 Bus clock * 12 #1011 1100 Bus clock * 13 #1100 1101 Bus clock * 14 #1101 1110 Bus clock * 15 #1110 1111 Bus clock * 16 #1111 DMA CMT Direct Memory Access Register 0xB 8 read-write 0 0xFF DMA DMA Enable 0 1 read-write 0 DMA transfer request and done are disabled. #0 1 DMA transfer request and done are enabled. #1 MCG Multipurpose Clock Generator module MCG_ 0x40064000 0 0xE registers MCG 27 C1 MCG Control 1 Register 0 8 read-write 0x4 0xFF IREFSTEN Internal Reference Stop Enable 0 1 read-write 0 Internal reference clock is disabled in Stop mode. #0 1 Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. #1 IRCLKEN Internal Reference Clock Enable 1 1 read-write 0 MCGIRCLK inactive. #0 1 MCGIRCLK active. #1 IREFS Internal Reference Select 2 1 read-write 0 External reference clock is selected. #0 1 The slow internal reference clock is selected. #1 FRDIV FLL External Reference Divider 3 3 read-write 000 If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. #000 001 If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. #001 010 If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. #010 011 If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. #011 100 If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. #100 101 If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. #101 110 If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . #110 111 If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 . #111 CLKS Clock Source Select 6 2 read-write 00 Encoding 0 - Output of FLL is selected. #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 11 Encoding 3 - Reserved. #11 C2 MCG Control 2 Register 0x1 8 read-write 0xC0 0xFF IRCS Internal Reference Clock Select 0 1 read-write 0 Slow internal reference clock selected. #0 1 Fast internal reference clock selected. #1 LP Low Power Select 1 1 read-write 0 FLL is not disabled in bypass modes. #0 1 FLL is disabled in bypass modes (lower power) #1 EREFS External Reference Select 2 1 read-write 0 External reference clock requested. #0 1 Oscillator requested. #1 HGO High Gain Oscillator Select 3 1 read-write 0 Configure crystal oscillator for low-power operation. #0 1 Configure crystal oscillator for high-gain operation. #1 RANGE Frequency Range Select 4 2 read-write 00 Encoding 0 - Low frequency range selected for the crystal oscillator . #00 01 Encoding 1 - High frequency range selected for the crystal oscillator . #01 1X Encoding 2 - Very high frequency range selected for the crystal oscillator . #1x FCFTRIM Fast Internal Reference Clock Fine Trim 6 1 read-write LOCRE0 Loss of Clock Reset Enable 7 1 read-write 0 Interrupt request is generated on a loss of OSC0 external reference clock. #0 1 Generate a reset request on a loss of OSC0 external reference clock. #1 C3 MCG Control 3 Register 0x2 8 read-write 0 0 SCTRIM Slow Internal Reference Clock Trim Setting 0 8 read-write C4 MCG Control 4 Register 0x3 8 read-write 0 0xE0 SCFTRIM Slow Internal Reference Clock Fine Trim 0 1 read-write FCTRIM Fast Internal Reference Clock Trim Setting 1 4 read-write DRST_DRS DCO Range Select 5 2 read-write 00 Encoding 0 - Low range (reset default). #00 01 Encoding 1 - Mid range. #01 10 Encoding 2 - Mid-high range. #10 11 Encoding 3 - High range. #11 DMX32 DCO Maximum Frequency with 32.768 kHz Reference 7 1 read-write 0 DCO has a default range of 25%. #0 1 DCO is fine-tuned for maximum frequency with 32.768 kHz reference. #1 C5 MCG Control 5 Register 0x4 8 read-only 0 0xFF C6 MCG Control 6 Register 0x5 8 read-write 0 0xFF CME0 Clock Monitor Enable 5 1 read-write 0 External clock monitor is disabled. #0 1 Generate an interrupt or a reset request (see MCG_C2[LOCRE0]) on loss of external clock. #1 S MCG Status Register 0x6 8 read-only 0x10 0xFF IRCST Internal Reference Clock Status 0 1 read-only 0 Source of internal reference clock is the slow clock (32 kHz IRC). #0 1 Source of internal reference clock is the fast clock (4 MHz IRC). #1 OSCINIT0 OSC Initialization 1 1 read-only CLKST Clock Mode Status 2 2 read-only 00 Encoding 0 - Output of the FLL is selected (reset default). #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 IREFST Internal Reference Status 4 1 read-only 0 Source of FLL reference clock is the external reference clock. #0 1 Source of FLL reference clock is the internal reference clock. #1 SC MCG Status and Control Register 0x8 8 read-write 0x2 0xFF LOCS0 OSC0 Loss of Clock Status 0 1 read-write 0 Loss of OSC0 has not occurred. #0 1 Loss of OSC0 has occurred. #1 FCRDIV Fast Clock Internal Reference Divider 1 3 read-write 000 Divide Factor is 1 #000 001 Divide Factor is 2. #001 010 Divide Factor is 4. #010 011 Divide Factor is 8. #011 100 Divide Factor is 16 #100 101 Divide Factor is 32 #101 110 Divide Factor is 64 #110 111 Divide Factor is 128. #111 FLTPRSRV FLL Filter Preserve Enable 4 1 read-write 0 FLL filter and FLL frequency will reset on changes to currect clock mode. #0 1 Fll filter and FLL frequency retain their previous values during new clock mode change. #1 ATMF Automatic Trim Machine Fail Flag 5 1 read-write 0 Automatic Trim Machine completed normally. #0 1 Automatic Trim Machine failed. #1 ATMS Automatic Trim Machine Select 6 1 read-write 0 32 kHz Internal Reference Clock selected. #0 1 4 MHz Internal Reference Clock selected. #1 ATME Automatic Trim Machine Enable 7 1 read-write 0 Auto Trim Machine disabled. #0 1 Auto Trim Machine enabled. #1 ATCVH MCG Auto Trim Compare Value High Register 0xA 8 read-write 0 0xFF ATCVH ATM Compare Value High 0 8 read-write ATCVL MCG Auto Trim Compare Value Low Register 0xB 8 read-write 0 0xFF ATCVL ATM Compare Value Low 0 8 read-write C7 MCG Control 7 Register 0xC 8 read-write 0 0xFF OSCSEL MCG OSC Clock Select 0 1 read-write 0 Selects Oscillator (OSCCLK). #0 1 Selects 32 kHz RTC Oscillator. #1 C8 MCG Control 8 Register 0xD 8 read-write 0x80 0xFF LOCS1 RTC Loss of Clock Status 0 1 read-write 0 Loss of RTC has not occur. #0 1 Loss of RTC has occur #1 CME1 Clock Monitor Enable1 5 1 read-write 0 External clock monitor is disabled for RTC clock. #0 1 External clock monitor is enabled for RTC clock. #1 LOCRE1 Loss of Clock Reset Enable 7 1 read-write 0 Interrupt request is generated on a loss of RTC external reference clock. #0 1 Generate a reset request on a loss of RTC external reference clock #1 I2C0 Inter-Integrated Circuit I2C I2C0_ 0x40066000 0 0xD registers I2C0 8 A1 I2C Address Register 1 0 8 read-write 0 0xFF AD Address 1 7 read-write F I2C Frequency Divider register 0x1 8 read-write 0 0xFF ICR ClockRate 0 6 read-write MULT Multiplier Factor 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 C1 I2C Control Register 1 0x2 8 read-write 0 0xFF DMAEN DMA Enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 WUEN Wakeup Enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 RSTA Repeat START 2 1 write-only TXAK Transmit Acknowledge Enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). #0 1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). #1 TX Transmit Mode Select 4 1 read-write 0 Receive #0 1 Transmit #1 MST Master Mode Select 5 1 read-write 0 Slave mode #0 1 Master mode #1 IICIE I2C Interrupt Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 IICEN I2C Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 S I2C Status register 0x3 8 read-write 0x80 0xFF RXAK Receive Acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 IICIF Interrupt Flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 SRW Slave Read/Write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 RAM Range Address Match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 ARBL Arbitration Lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus Busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed As A Slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 TCF Transfer Complete Flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 D I2C Data I/O register 0x4 8 read-write 0 0xFF DATA Data 0 8 read-write C2 I2C Control Register 2 0x5 8 read-write 0 0xFF AD Slave Address 0 3 read-write RMEN Range Address Matching Enable 3 1 read-write 0 Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave Baud Rate Control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 HDRS High Drive Select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 ADEXT Address Extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General Call Address Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 FLT I2C Programmable Input Glitch Filter Register 0x6 8 read-write 0 0xFF FLT I2C Programmable Filter Factor 0 4 read-write 0 No filter/bypass #0000 STARTF I2C Bus Start Detect Flag 4 1 read-write 0 No start happens on I2C bus #0 1 Start detected on I2C bus #1 SSIE I2C Bus Stop or Start Interrupt Enable 5 1 read-write 0 Stop or start detection interrupt is disabled #0 1 Stop or start detection interrupt is enabled #1 STOPF I2C Bus Stop Detect Flag 6 1 read-write 0 No stop happens on I2C bus #0 1 Stop detected on I2C bus #1 SHEN Stop Hold Enable 7 1 read-write 0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated. #0 1 Stop holdoff is enabled. #1 RA I2C Range Address register 0x7 8 read-write 0 0xFF RAD Range Slave Address 1 7 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write 0 0xFF SHTF2IE SHTF2 Interrupt Enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SHTF2 SCL High Timeout Flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF1 SCL High Timeout Flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SLTF SCL Low Timeout Flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout Counter Clock Select 4 1 read-write 0 Timeout counter counts at the frequency of the I2C module clock / 64 #0 1 Timeout counter counts at the frequency of the I2C module clock #1 SIICAEN Second I2C Address Enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 ALERTEN SMBus Alert Response Address Enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK Enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. Enable I2C_S2[DFEN] in the master receive mode. #1 A2 I2C Address Register 2 0x9 8 read-write 0xC2 0xFF SAD SMBus Address 1 7 read-write SLTH I2C SCL Low Timeout Register High 0xA 8 read-write 0 0xFF SSLT SSLT[15:8] 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write 0 0xFF SSLT SSLT[7:0] 0 8 read-write S2 I2C Status register 2 0xC 8 read-write 0x1 0xFF EMPTY Empty flag 0 1 read-only 0 Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer. #0 1 Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer. #1 ERROR Error flag 1 1 read-write 0 The buffer is not full and all write/read operations have no errors. #0 1 There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the buffer is busy). #1 DFEN Double Buffer Enable 2 1 read-write 0 Disables the double buffer mode; clock stretch is enabled. #0 1 Enables the double buffer mode; clock stretch is disabled. In the slave mode, the I2C will not hold bus between data transfers. #1 I2C1 Inter-Integrated Circuit I2C I2C1_ 0x40067000 0 0xD registers I2C1 9 A1 I2C Address Register 1 0 8 read-write 0 0xFF AD Address 1 7 read-write F I2C Frequency Divider register 0x1 8 read-write 0 0xFF ICR ClockRate 0 6 read-write MULT Multiplier Factor 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 C1 I2C Control Register 1 0x2 8 read-write 0 0xFF DMAEN DMA Enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 WUEN Wakeup Enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 RSTA Repeat START 2 1 write-only TXAK Transmit Acknowledge Enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). #0 1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). #1 TX Transmit Mode Select 4 1 read-write 0 Receive #0 1 Transmit #1 MST Master Mode Select 5 1 read-write 0 Slave mode #0 1 Master mode #1 IICIE I2C Interrupt Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 IICEN I2C Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 S I2C Status register 0x3 8 read-write 0x80 0xFF RXAK Receive Acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 IICIF Interrupt Flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 SRW Slave Read/Write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 RAM Range Address Match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 ARBL Arbitration Lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus Busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed As A Slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 TCF Transfer Complete Flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 D I2C Data I/O register 0x4 8 read-write 0 0xFF DATA Data 0 8 read-write C2 I2C Control Register 2 0x5 8 read-write 0 0xFF AD Slave Address 0 3 read-write RMEN Range Address Matching Enable 3 1 read-write 0 Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave Baud Rate Control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 HDRS High Drive Select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 ADEXT Address Extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General Call Address Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 FLT I2C Programmable Input Glitch Filter Register 0x6 8 read-write 0 0xFF FLT I2C Programmable Filter Factor 0 4 read-write 0 No filter/bypass #0000 STARTF I2C Bus Start Detect Flag 4 1 read-write 0 No start happens on I2C bus #0 1 Start detected on I2C bus #1 SSIE I2C Bus Stop or Start Interrupt Enable 5 1 read-write 0 Stop or start detection interrupt is disabled #0 1 Stop or start detection interrupt is enabled #1 STOPF I2C Bus Stop Detect Flag 6 1 read-write 0 No stop happens on I2C bus #0 1 Stop detected on I2C bus #1 SHEN Stop Hold Enable 7 1 read-write 0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated. #0 1 Stop holdoff is enabled. #1 RA I2C Range Address register 0x7 8 read-write 0 0xFF RAD Range Slave Address 1 7 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write 0 0xFF SHTF2IE SHTF2 Interrupt Enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SHTF2 SCL High Timeout Flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF1 SCL High Timeout Flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SLTF SCL Low Timeout Flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout Counter Clock Select 4 1 read-write 0 Timeout counter counts at the frequency of the I2C module clock / 64 #0 1 Timeout counter counts at the frequency of the I2C module clock #1 SIICAEN Second I2C Address Enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 ALERTEN SMBus Alert Response Address Enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK Enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. Enable I2C_S2[DFEN] in the master receive mode. #1 A2 I2C Address Register 2 0x9 8 read-write 0xC2 0xFF SAD SMBus Address 1 7 read-write SLTH I2C SCL Low Timeout Register High 0xA 8 read-write 0 0xFF SSLT SSLT[15:8] 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write 0 0xFF SSLT SSLT[7:0] 0 8 read-write S2 I2C Status register 2 0xC 8 read-write 0x1 0xFF EMPTY Empty flag 0 1 read-only 0 Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer. #0 1 Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer. #1 ERROR Error flag 1 1 read-write 0 The buffer is not full and all write/read operations have no errors. #0 1 There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the buffer is busy). #1 DFEN Double Buffer Enable 2 1 read-write 0 Disables the double buffer mode; clock stretch is enabled. #0 1 Enables the double buffer mode; clock stretch is disabled. In the slave mode, the I2C will not hold bus between data transfers. #1 CMP0 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP0_ 0x40073000 0 0x6 registers CMP0 16 CR0 CMP Control Register 0 0 8 read-write 0 0xFF HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. SE = 0, COUT = COUTA. #000 001 One sample must agree. The comparator output is simply sampled. #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 CR1 CMP Control Register 1 0x1 8 read-write 0 0xFF EN Comparator Module Enable 0 1 read-write 0 Analog Comparator is disabled. #0 1 Analog Comparator is enabled. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. #0 1 CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. #1 COS Comparator Output Select 2 1 read-write 0 Set the filtered comparator output (CMPO) to equal COUT. #0 1 Set the unfiltered comparator output (CMPO) to equal COUTA. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 PMODE Power Mode Select 4 1 read-write 0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 TRIGM Trigger Mode Enable 5 1 read-write 0 Trigger mode is disabled. #0 1 Trigger mode is enabled. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode is not selected. #0 1 Windowing mode is selected. #1 SE Sample Enable 7 1 read-write 0 Sampling mode is not selected. #0 1 Sampling mode is selected. #1 FPR CMP Filter Period Register 0x2 8 read-write 0 0xFF FILT_PER Filter Sample Period 0 8 read-write SCR CMP Status and Control Register 0x3 8 read-write 0 0xFF COUT Analog Comparator Output 0 1 read-only CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling-edge on COUT has not been detected. #0 1 Falling-edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising-edge on COUT has not been detected. #0 1 Rising-edge on COUT has occurred. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 DMAEN DMA Enable Control 6 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. #1 DACCR DAC Control Register 0x4 8 read-write 0 0xFF VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference. #0 1 Vin2 is selected as resistor ladder network supply reference. #1 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 MUXCR MUX Control Register 0x5 8 read-write 0 0xFF MSEL Minus Input Mux Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input Mux Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSTM Pass Through Mode Enable 7 1 read-write 0 Pass Through Mode is disabled. #0 1 Pass Through Mode is enabled. #1 VREF Voltage Reference VREF_ 0x40074000 0 0x2 registers TRM VREF Trim Register 0 8 read-write 0 0x40 TRIM Trim bits 0 6 read-write 000000 Min #0 111111 Max #111111 CHOPEN Chop oscillator enable. When set, internal chopping operation is enabled and the internal analog offset will be minimized. 6 1 read-write 0 Chop oscillator is disabled. #0 1 Chop oscillator is enabled. #1 SC VREF Status and Control Register 0x1 8 read-write 0 0xFF MODE_LV Buffer Mode selection 0 2 read-write 00 Bandgap on only, for stabilization and startup #00 01 High power buffer mode enabled #01 10 Low-power buffer mode enabled #10 VREFST Internal Voltage Reference stable 2 1 read-only 0 The module is disabled or not stable. #0 1 The module is stable. #1 ICOMPEN Second order curvature compensation enable 5 1 read-write 0 Disabled #0 1 Enabled #1 REGEN Regulator enable 6 1 read-write 0 Internal 1.75 V regulator is disabled. #0 1 Internal 1.75 V regulator is enabled. #1 VREFEN Internal Voltage Reference enable 7 1 read-write 0 The module is disabled. #0 1 The module is enabled. #1 LLWU Low leakage wakeup unit LLWU_ 0x4007C000 0 0xA registers LLWU 7 PE1 LLWU Pin Enable 1 register 0 8 read-write 0 0xFF WUPE0 Wakeup Pin Enable For LLWU_P0 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE1 Wakeup Pin Enable For LLWU_P1 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE2 Wakeup Pin Enable For LLWU_P2 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE3 Wakeup Pin Enable For LLWU_P3 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE2 LLWU Pin Enable 2 register 0x1 8 read-write 0 0xFF WUPE4 Wakeup Pin Enable For LLWU_P4 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE5 Wakeup Pin Enable For LLWU_P5 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE6 Wakeup Pin Enable For LLWU_P6 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE7 Wakeup Pin Enable For LLWU_P7 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE3 LLWU Pin Enable 3 register 0x2 8 read-write 0 0xFF WUPE8 Wakeup Pin Enable For LLWU_P8 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE9 Wakeup Pin Enable For LLWU_P9 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE10 Wakeup Pin Enable For LLWU_P10 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE11 Wakeup Pin Enable For LLWU_P11 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE4 LLWU Pin Enable 4 register 0x3 8 read-write 0 0xFF WUPE12 Wakeup Pin Enable For LLWU_P12 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE13 Wakeup Pin Enable For LLWU_P13 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE14 Wakeup Pin Enable For LLWU_P14 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE15 Wakeup Pin Enable For LLWU_P15 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 ME LLWU Module Enable register 0x4 8 read-write 0 0xFF WUME0 Wakeup Module Enable For Module 0 0 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME1 Wakeup Module Enable for Module 1 1 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME2 Wakeup Module Enable For Module 2 2 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME3 Wakeup Module Enable For Module 3 3 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME4 Wakeup Module Enable For Module 4 4 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME5 Wakeup Module Enable For Module 5 5 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME6 Wakeup Module Enable For Module 6 6 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME7 Wakeup Module Enable For Module 7 7 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 F1 LLWU Flag 1 register 0x5 8 read-write 0 0xFF WUF0 Wakeup Flag For LLWU_P0 0 1 read-write 0 LLWU_P0 input was not a wakeup source #0 1 LLWU_P0 input was a wakeup source #1 WUF1 Wakeup Flag For LLWU_P1 1 1 read-write 0 LLWU_P1 input was not a wakeup source #0 1 LLWU_P1 input was a wakeup source #1 WUF2 Wakeup Flag For LLWU_P2 2 1 read-write 0 LLWU_P2 input was not a wakeup source #0 1 LLWU_P2 input was a wakeup source #1 WUF3 Wakeup Flag For LLWU_P3 3 1 read-write 0 LLWU_P3 input was not a wake-up source #0 1 LLWU_P3 input was a wake-up source #1 WUF4 Wakeup Flag For LLWU_P4 4 1 read-write 0 LLWU_P4 input was not a wakeup source #0 1 LLWU_P4 input was a wakeup source #1 WUF5 Wakeup Flag For LLWU_P5 5 1 read-write 0 LLWU_P5 input was not a wakeup source #0 1 LLWU_P5 input was a wakeup source #1 WUF6 Wakeup Flag For LLWU_P6 6 1 read-write 0 LLWU_P6 input was not a wakeup source #0 1 LLWU_P6 input was a wakeup source #1 WUF7 Wakeup Flag For LLWU_P7 7 1 read-write 0 LLWU_P7 input was not a wakeup source #0 1 LLWU_P7 input was a wakeup source #1 F2 LLWU Flag 2 register 0x6 8 read-write 0 0xFF WUF8 Wakeup Flag For LLWU_P8 0 1 read-write 0 LLWU_P8 input was not a wakeup source #0 1 LLWU_P8 input was a wakeup source #1 WUF9 Wakeup Flag For LLWU_P9 1 1 read-write 0 LLWU_P9 input was not a wakeup source #0 1 LLWU_P9 input was a wakeup source #1 WUF10 Wakeup Flag For LLWU_P10 2 1 read-write 0 LLWU_P10 input was not a wakeup source #0 1 LLWU_P10 input was a wakeup source #1 WUF11 Wakeup Flag For LLWU_P11 3 1 read-write 0 LLWU_P11 input was not a wakeup source #0 1 LLWU_P11 input was a wakeup source #1 WUF12 Wakeup Flag For LLWU_P12 4 1 read-write 0 LLWU_P12 input was not a wakeup source #0 1 LLWU_P12 input was a wakeup source #1 WUF13 Wakeup Flag For LLWU_P13 5 1 read-write 0 LLWU_P13 input was not a wakeup source #0 1 LLWU_P13 input was a wakeup source #1 WUF14 Wakeup Flag For LLWU_P14 6 1 read-write 0 LLWU_P14 input was not a wakeup source #0 1 LLWU_P14 input was a wakeup source #1 WUF15 Wakeup Flag For LLWU_P15 7 1 read-write 0 LLWU_P15 input was not a wakeup source #0 1 LLWU_P15 input was a wakeup source #1 F3 LLWU Flag 3 register 0x7 8 read-only 0 0xFF MWUF0 Wakeup flag For module 0 0 1 read-only 0 Module 0 input was not a wakeup source #0 1 Module 0 input was a wakeup source #1 MWUF1 Wakeup flag For module 1 1 1 read-only 0 Module 1 input was not a wakeup source #0 1 Module 1 input was a wakeup source #1 MWUF2 Wakeup flag For module 2 2 1 read-only 0 Module 2 input was not a wakeup source #0 1 Module 2 input was a wakeup source #1 MWUF3 Wakeup flag For module 3 3 1 read-only 0 Module 3 input was not a wakeup source #0 1 Module 3 input was a wakeup source #1 MWUF4 Wakeup flag For module 4 4 1 read-only 0 Module 4 input was not a wakeup source #0 1 Module 4 input was a wakeup source #1 MWUF5 Wakeup flag For module 5 5 1 read-only 0 Module 5 input was not a wakeup source #0 1 Module 5 input was a wakeup source #1 MWUF6 Wakeup flag For module 6 6 1 read-only 0 Module 6 input was not a wakeup source #0 1 Module 6 input was a wakeup source #1 MWUF7 Wakeup flag For module 7 7 1 read-only 0 Module 7 input was not a wakeup source #0 1 Module 7 input was a wakeup source #1 FILT1 LLWU Pin Filter 1 register 0x8 8 read-write 0 0xFF FILTSEL Filter Pin Select 0 4 read-write 0000 Select LLWU_P0 for filter #0000 1111 Select LLWU_P15 for filter #1111 FILTE Digital Filter On External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 1 was not a wakeup source #0 1 Pin Filter 1 was a wakeup source #1 FILT2 LLWU Pin Filter 2 register 0x9 8 read-write 0 0xFF FILTSEL Filter Pin Select 0 4 read-write 0000 Select LLWU_P0 for filter #0000 1111 Select LLWU_P15 for filter #1111 FILTE Digital Filter On External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 2 was not a wakeup source #0 1 Pin Filter 2 was a wakeup source #1 PMC Power Management Controller PMC_ 0x4007D000 0 0x3 registers LVD_LVW_DCDC 6 LVDSC1 Low Voltage Detect Status And Control 1 register 0 8 read-write 0x10 0xFF LVDV Low-Voltage Detect Voltage Select 0 2 read-write 00 Low trip point selected (V LVD = V LVDL ) #00 01 High trip point selected (V LVD = V LVDH ) #01 LVDRE Low-Voltage Detect Reset Enable 4 1 read-write 0 LVDF does not generate hardware resets #0 1 Force an MCU reset when LVDF = 1 #1 LVDIE Low-Voltage Detect Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVDF = 1 #1 LVDACK Low-Voltage Detect Acknowledge 6 1 write-only LVDF Low-Voltage Detect Flag 7 1 read-only 0 Low-voltage event not detected #0 1 Low-voltage event detected #1 LVDSC2 Low Voltage Detect Status And Control 2 register 0x1 8 read-write 0 0xFF LVWV Low-Voltage Warning Voltage Select 0 2 read-write 00 Low trip point selected (VLVW = VLVW1) #00 01 Mid 1 trip point selected (VLVW = VLVW2) #01 10 Mid 2 trip point selected (VLVW = VLVW3) #10 11 High trip point selected (VLVW = VLVW4) #11 LVWIE Low-Voltage Warning Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVWF = 1 #1 LVWACK Low-Voltage Warning Acknowledge 6 1 write-only LVWF Low-Voltage Warning Flag 7 1 read-only 0 Low-voltage warning event not detected #0 1 Low-voltage warning event detected #1 REGSC Regulator Status And Control register 0x2 8 read-write 0x4 0xFF BGBE Bandgap Buffer Enable 0 1 read-write 0 Bandgap buffer not enabled #0 1 Bandgap buffer enabled #1 REGONS Regulator In Run Regulation Status 2 1 read-only 0 Regulator is in stop regulation or in transition to/from it #0 1 Regulator is in run regulation #1 ACKISO Acknowledge Isolation 3 1 read-write 0 Peripherals and I/O pads are in normal run state. #0 1 Certain peripherals and I/O pads are in an isolated and latched state. #1 VLPO VLPx Option 6 1 read-write 0 Operating frequencies and MCG clocking modes are restricted during VLPx modes as listed in the Power Management chapter. #0 1 If BGEN is also set, operating frequencies and MCG clocking modes are unrestricted during VLPx modes. Note that flash access frequency is still restricted however. #1 SMC System Mode Controller SMC_ 0x4007E000 0 0x4 registers PMPROT Power Mode Protection register 0 8 read-write 0 0xFF AVLLS Allow Very-Low-Leakage Stop Mode 1 1 read-write 0 Any VLLSx mode is not allowed #0 1 Any VLLSx mode is allowed #1 ALLS Allow Low-Leakage Stop Mode 3 1 read-write 0 Any LLSx mode is not allowed #0 1 Any LLSx mode is allowed #1 AVLP Allow Very-Low-Power Modes 5 1 read-write 0 VLPR, VLPW, and VLPS are not allowed. #0 1 VLPR, VLPW, and VLPS are allowed. #1 PMCTRL Power Mode Control register 0x1 8 read-write 0 0xFF STOPM Stop Mode Control 0 3 read-write 000 Normal Stop (STOP) #000 010 Very-Low-Power Stop (VLPS) #010 011 Low-Leakage Stop (LLSx) #011 100 Very-Low-Leakage Stop (VLLSx) #100 110 Reseved #110 STOPA Stop Aborted 3 1 read-only 0 The previous stop mode entry was successful. #0 1 The previous stop mode entry was aborted. #1 RUNM Run Mode Control 5 2 read-write 00 Normal Run mode (RUN) #00 10 Very-Low-Power Run mode (VLPR) #10 STOPCTRL Stop Control Register 0x2 8 read-write 0x3 0xFF LLSM LLS or VLLS Mode Control 0 3 read-write 000 VLLS0 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx #000 001 VLLS1 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx #001 010 VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx #010 011 VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx #011 RAM2PO RAM2 Power Option 4 1 read-write 0 RAM2 not powered in LLS2/VLLS2 #0 1 RAM2 powered in LLS2/VLLS2 #1 PORPO POR Power Option 5 1 read-write 0 POR detect circuit is enabled in VLLS0 #0 1 POR detect circuit is disabled in VLLS0 #1 PSTOPO Partial Stop Option 6 2 read-write 00 STOP - Normal Stop mode #00 01 PSTOP1 - Partial Stop with both system and bus clocks disabled #01 10 PSTOP2 - Partial Stop with system clock disabled and bus clock enabled #10 PMSTAT Power Mode Status register 0x3 8 read-only 0x1 0xFF PMSTAT Power Mode Status 0 8 read-only RCM Reset Control Module RCM_ 0x4007F000 0 0x6 registers SRS0 System Reset Status Register 0 0 8 read-only 0x82 0xFF WAKEUP Low Leakage Wakeup Reset 0 1 read-only 0 Reset not caused by LLWU module wakeup source #0 1 Reset caused by LLWU module wakeup source #1 LVD Low-Voltage Detect Reset 1 1 read-only 0 Reset not caused by LVD trip or POR #0 1 Reset caused by LVD trip or POR #1 LOC Loss-of-Clock Reset 2 1 read-only 0 Reset not caused by a loss of external clock. #0 1 Reset caused by a loss of external clock. #1 WDOG Watchdog 5 1 read-only 0 Reset not caused by watchdog timeout #0 1 Reset caused by watchdog timeout #1 PIN External Reset Pin 6 1 read-only 0 Reset not caused by external reset pin #0 1 Reset caused by external reset pin #1 POR Power-On Reset 7 1 read-only 0 Reset not caused by POR #0 1 Reset caused by POR #1 SRS1 System Reset Status Register 1 0x1 8 read-only 0 0xFF LOCKUP Core Lockup 1 1 read-only 0 Reset not caused by core LOCKUP event #0 1 Reset caused by core LOCKUP event #1 SW Software 2 1 read-only 0 Reset not caused by software setting of SYSRESETREQ bit #0 1 Reset caused by software setting of SYSRESETREQ bit #1 MDM_AP MDM-AP System Reset Request 3 1 read-only 0 Reset not caused by host debugger system setting of the System Reset Request bit #0 1 Reset caused by host debugger system setting of the System Reset Request bit #1 SACKERR Stop Mode Acknowledge Error Reset 5 1 read-only 0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode #0 1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode #1 RPFC Reset Pin Filter Control register 0x4 8 read-write 0 0xFF RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes 0 2 read-write 00 All filtering disabled #00 01 Bus clock filter enabled for normal operation #01 10 LPO clock filter enabled for normal operation #10 RSTFLTSS Reset Pin Filter Select in Stop Mode 2 1 read-write 0 All filtering disabled #0 1 LPO clock filter enabled #1 RPFW Reset Pin Filter Width register 0x5 8 read-write 0 0xFF RSTFLTSEL Reset Pin Filter Bus Clock Select 0 5 read-write 00000 Bus clock filter count is 1 #00000 00001 Bus clock filter count is 2 #00001 00010 Bus clock filter count is 3 #00010 00011 Bus clock filter count is 4 #00011 00100 Bus clock filter count is 5 #00100 00101 Bus clock filter count is 6 #00101 00110 Bus clock filter count is 7 #00110 00111 Bus clock filter count is 8 #00111 01000 Bus clock filter count is 9 #01000 01001 Bus clock filter count is 10 #01001 01010 Bus clock filter count is 11 #01010 01011 Bus clock filter count is 12 #01011 01100 Bus clock filter count is 13 #01100 01101 Bus clock filter count is 14 #01101 01110 Bus clock filter count is 15 #01110 01111 Bus clock filter count is 16 #01111 10000 Bus clock filter count is 17 #10000 10001 Bus clock filter count is 18 #10001 10010 Bus clock filter count is 19 #10010 10011 Bus clock filter count is 20 #10011 10100 Bus clock filter count is 21 #10100 10101 Bus clock filter count is 22 #10101 10110 Bus clock filter count is 23 #10110 10111 Bus clock filter count is 24 #10111 11000 Bus clock filter count is 25 #11000 11001 Bus clock filter count is 26 #11001 11010 Bus clock filter count is 27 #11010 11011 Bus clock filter count is 28 #11011 11100 Bus clock filter count is 29 #11100 11101 Bus clock filter count is 30 #11101 11110 Bus clock filter count is 31 #11110 11111 Bus clock filter count is 32 #11111 GPIOA General Purpose Input/Output GPIO GPIOA_ 0x400FF000 0 0x18 registers PORTA 30 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOB General Purpose Input/Output GPIO GPIOB_ 0x400FF040 0 0x18 registers PORTB_PORTC 31 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOC General Purpose Input/Output GPIO GPIOC_ 0x400FF080 0 0x18 registers PORTB_PORTC 31 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 MTB Micro Trace Buffer MTB_ 0xF0000000 0 0x1000 registers POSITION MTB Position Register 0 32 read-write 0 0x3 WRAP WRAP 2 1 read-write POINTER Trace Packet Address Pointer[28:0] 3 29 read-write MASTER MTB Master Register 0x4 32 read-write 0x80 0xFFFFFFE0 MASK Mask 0 5 read-write TSTARTEN Trace Start Input Enable 5 1 read-write TSTOPEN Trace Stop Input Enable 6 1 read-write SFRWPRIV Special Function Register Write Privilege 7 1 read-write RAMPRIV RAM Privilege 8 1 read-write HALTREQ Halt Request 9 1 read-write EN Main Trace Enable 31 1 read-write FLOW MTB Flow Register 0x8 32 read-write 0 0x4 AUTOSTOP AUTOSTOP 0 1 read-write AUTOHALT AUTOHALT 1 1 read-write WATERMARK WATERMARK[28:0] 3 29 read-write BASE MTB Base Register 0xC 32 read-only 0 0 BASEADDR BASEADDR 0 32 read-only MODECTRL Integration Mode Control Register 0xF00 32 read-only 0 0xFFFFFFFF MODECTRL MODECTRL 0 32 read-only TAGSET Claim TAG Set Register 0xFA0 32 read-only 0 0xFFFFFFFF TAGSET TAGSET 0 32 read-only TAGCLEAR Claim TAG Clear Register 0xFA4 32 read-only 0 0xFFFFFFFF TAGCLEAR TAGCLEAR 0 32 read-only LOCKACCESS Lock Access Register 0xFB0 32 read-only 0 0xFFFFFFFF LOCKACCESS Hardwired to 0x0000_0000 0 32 read-only LOCKSTAT Lock Status Register 0xFB4 32 read-only 0 0xFFFFFFFF LOCKSTAT LOCKSTAT 0 32 read-only AUTHSTAT Authentication Status Register 0xFB8 32 read-only 0 0xFFFFFFFF BIT0 Connected to DBGEN. 0 1 read-only BIT1 BIT1 1 1 read-only BIT2 BIT2 2 1 read-only BIT3 BIT3 3 1 read-only DEVICEARCH Device Architecture Register 0xFBC 32 read-only 0x47700A31 0xFFFFFFFF DEVICEARCH DEVICEARCH 0 32 read-only DEVICECFG Device Configuration Register 0xFC8 32 read-only 0 0xFFFFFFFF DEVICECFG DEVICECFG 0 32 read-only DEVICETYPID Device Type Identifier Register 0xFCC 32 read-only 0x31 0xFFFFFFFF DEVICETYPID DEVICETYPID 0 32 read-only 8 0x4 4,5,6,7,0,1,2,3 PERIPHID%s Peripheral ID Register 0xFD0 32 read-only 0 0 PERIPHID PERIPHID 0 32 read-only 4 0x4 0,1,2,3 COMPID%s Component ID Register 0xFF0 32 read-only 0 0 COMPID Component ID 0 32 read-only MTBDWT MTB data watchpoint and trace MTBDWT_ 0xF0001000 0 0x1000 registers CTRL MTB DWT Control Register 0 32 read-only 0x2F000000 0xFFFFFFFF DWTCFGCTRL DWT configuration controls 0 28 read-only NUMCMP Number of comparators 28 4 read-only 2 0x10 0,1 COMP%s MTB_DWT Comparator Register 0x20 32 read-write 0 0xFFFFFFFF COMP Reference value for comparison 0 32 read-write 2 0x10 0,1 MASK%s MTB_DWT Comparator Mask Register 0x24 32 read-write 0 0xFFFFFFFF MASK MASK 0 5 read-write FCT0 MTB_DWT Comparator Function Register 0 0x28 32 read-write 0 0xFFFFFFFF FUNCTION Function 0 4 read-write 0000 Disabled. #0000 0100 Instruction fetch. #0100 0101 Data operand read. #0101 0110 Data operand write. #0110 0111 Data operand (read + write). #0111 DATAVMATCH Data Value Match 8 1 read-write 0 Perform address comparison. #0 1 Perform data value comparison. #1 DATAVSIZE Data Value Size 10 2 read-write 00 Byte. #00 01 Halfword. #01 10 Word. #10 11 Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. #11 DATAVADDR0 Data Value Address 0 12 4 read-write MATCHED Comparator match 24 1 read-only 0 No match. #0 1 Match occurred. #1 FCT1 MTB_DWT Comparator Function Register 1 0x38 32 read-write 0 0xFFFFFFFF FUNCTION Function 0 4 read-write 0000 Disabled. #0000 0100 Instruction fetch. #0100 0101 Data operand read. #0101 0110 Data operand write. #0110 0111 Data operand (read + write). #0111 MATCHED Comparator match 24 1 read-only 0 No match. #0 1 Match occurred. #1 TBCTRL MTB_DWT Trace Buffer Control Register 0x200 32 read-write 0x20000000 0xFFFFFFFF ACOMP0 Action based on Comparator 0 match 0 1 read-write 0 Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED]. #0 1 Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED]. #1 ACOMP1 Action based on Comparator 1 match 1 1 read-write 0 Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED]. #0 1 Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED]. #1 NUMCOMP Number of Comparators 28 4 read-only DEVICECFG Device Configuration Register 0xFC8 32 read-only 0 0xFFFFFFFF DEVICECFG DEVICECFG 0 32 read-only DEVICETYPID Device Type Identifier Register 0xFCC 32 read-only 0x4 0xFFFFFFFF DEVICETYPID DEVICETYPID 0 32 read-only 8 0x4 4,5,6,7,0,1,2,3 PERIPHID%s Peripheral ID Register 0xFD0 32 read-only 0 0 PERIPHID PERIPHID 0 32 read-only 4 0x4 0,1,2,3 COMPID%s Component ID Register 0xFF0 32 read-only 0 0 COMPID Component ID 0 32 read-only ROM System ROM ROM_ 0xF0002000 0 0x1000 registers 3 0x4 0,1,2 ENTRY%s Entry 0 32 read-only 0 0 ENTRY ENTRY 0 32 read-only TABLEMARK End of Table Marker Register 0xC 32 read-only 0 0xFFFFFFFF MARK MARK 0 32 read-only SYSACCESS System Access Register 0xFCC 32 read-only 0x1 0xFFFFFFFF SYSACCESS SYSACCESS 0 32 read-only 8 0x4 4,5,6,7,0,1,2,3 PERIPHID%s Peripheral ID Register 0xFD0 32 read-only 0 0 PERIPHID PERIPHID 0 32 read-only 4 0x4 0,1,2,3 COMPID%s Component ID Register 0xFF0 32 read-only 0 0 COMPID Component ID 0 32 read-only MCM Core Platform Miscellaneous Control Module MCM_ 0xF0003000 0x8 0x3C registers PLASC Crossbar Switch (AXBS) Slave Configuration 0x8 16 read-only 0x7 0xFFFF ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0 8 read-only 0 A bus slave connection to AXBS input port n is absent. #0 1 A bus slave connection to AXBS input port n is present. #1 PLAMC Crossbar Switch (AXBS) Master Configuration 0xA 16 read-only 0x5 0xFFFF AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 8 read-only 0 A bus master connection to AXBS input port n is absent #0 1 A bus master connection to AXBS input port n is present #1 PLACR Platform Control Register 0xC 32 read-write 0x50 0xFFFFFFFF ARB Arbitration select 9 1 read-write 0 Fixed-priority arbitration for the crossbar masters #0 1 Round-robin arbitration for the crossbar masters #1 CFCC Clear Flash Controller Cache 10 1 write-only DFCDA Disable Flash Controller Data Caching 11 1 read-write 0 Enable flash controller data caching #0 1 Disable flash controller data caching. #1 DFCIC Disable Flash Controller Instruction Caching 12 1 read-write 0 Enable flash controller instruction caching. #0 1 Disable flash controller instruction caching. #1 DFCC Disable Flash Controller Cache 13 1 read-write 0 Enable flash controller cache. #0 1 Disable flash controller cache. #1 EFDS Enable Flash Data Speculation 14 1 read-write 0 Disable flash data speculation. #0 1 Enable flash data speculation. #1 DFCS Disable Flash Controller Speculation 15 1 read-write 0 Enable flash controller speculation. #0 1 Disable flash controller speculation. #1 ESFC Enable Stalling Flash Controller 16 1 read-write 0 Disable stalling flash controller when flash is busy. #0 1 Enable stalling flash controller when flash is busy. #1 CPO Compute Operation Control Register 0x40 32 read-write 0 0xFFFFFFFF CPOREQ Compute Operation Request 0 1 read-write 0 Request is cleared. #0 1 Request Compute Operation. #1 CPOACK Compute Operation Acknowledge 1 1 read-only 0 Compute operation entry has not completed or compute operation exit has completed. #0 1 Compute operation entry has completed or compute operation exit has not completed. #1 CPOWOI Compute Operation Wake-up on Interrupt 2 1 read-write 0 No effect. #0 1 When set, the CPOREQ is cleared on any interrupt or exception vector fetch. #1 FGPIOA General Purpose Input/Output FGPIO FGPIOA_ 0xF8000000 0 0x18 registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 FGPIOB General Purpose Input/Output FGPIO FGPIOB_ 0xF8000040 0 0x18 registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 FGPIOC General Purpose Input/Output FGPIO FGPIOC_ 0xF8000080 0 0x18 registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1