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Freescale Kinetis_V MKV44F16 1.6 MKV44F16 Freescale Microcontroller Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. 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CM4 r0p1 little false true false true 4 false 8 32 FTFL_FlashConfig Flash configuration field NV_ 0x400 0 0x10 registers BACKKEY3 Backdoor Comparison Key 3. 0 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY2 Backdoor Comparison Key 2. 0x1 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY1 Backdoor Comparison Key 1. 0x2 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY0 Backdoor Comparison Key 0. 0x3 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY7 Backdoor Comparison Key 7. 0x4 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY6 Backdoor Comparison Key 6. 0x5 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY5 Backdoor Comparison Key 5. 0x6 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY4 Backdoor Comparison Key 4. 0x7 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only FPROT3 Non-volatile P-Flash Protection 1 - Low Register 0x8 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FPROT2 Non-volatile P-Flash Protection 1 - High Register 0x9 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FPROT1 Non-volatile P-Flash Protection 0 - Low Register 0xA 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FPROT0 Non-volatile P-Flash Protection 0 - High Register 0xB 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FSEC Non-volatile Flash Security Register 0xC 8 read-only 0xFF 0xFF SEC Flash Security 0 2 read-only 10 MCU security status is unsecure #10 11 MCU security status is secure #11 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 10 Freescale factory access denied #10 11 Freescale factory access granted #11 MEEN no description available 4 2 read-only 10 Mass erase is disabled #10 11 Mass erase is enabled #11 KEYEN Backdoor Key Security Enable 6 2 read-only 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 FOPT Non-volatile Flash Option Register 0xD 8 read-only 0xFF 0xFF LPBOOT no description available 0 1 read-only 00 Low-power boot #0 01 Normal boot #1 NMI_DIS no description available 2 1 read-only 00 NMI interrupts are always blocked #0 01 NMI_b pin/interrupts reset default to enabled #1 FAST_INIT no description available 5 1 read-only 00 Slower initialization #0 01 Fast Initialization #1 FEPROT Non-volatile EERAM Protection Register 0xE 8 read-only 0xFF 0xFF EPROT no description available 0 8 read-only FDPROT Non-volatile D-Flash Protection Register 0xF 8 read-only 0xFF 0xFF DPROT D-Flash Region Protect 0 8 read-only AIPS AIPS-Lite Bridge AIPS_ 0x40000000 0 0x70 registers MPRA Master Privilege Register A 0 32 read-write 0x77700000 0xFFFFFFFF MPL2 Master 2 Privilege Level 20 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTW2 Master 2 Trusted For Writes 21 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTR2 Master 2 Trusted For Read 22 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MPL1 Master 1 Privilege Level 24 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTW1 Master 1 Trusted for Writes 25 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTR1 Master 1 Trusted for Read 26 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MPL0 Master 0 Privilege Level 28 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTW0 Master 0 Trusted For Writes 29 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTR0 Master 0 Trusted For Read 30 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 PACRA Peripheral Access Control Register 0x20 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRB Peripheral Access Control Register 0x24 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRC Peripheral Access Control Register 0x28 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRD Peripheral Access Control Register 0x2C 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRE Peripheral Access Control Register 0x40 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRF Peripheral Access Control Register 0x44 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRG Peripheral Access Control Register 0x48 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRH Peripheral Access Control Register 0x4C 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRI Peripheral Access Control Register 0x50 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRJ Peripheral Access Control Register 0x54 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRK Peripheral Access Control Register 0x58 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRL Peripheral Access Control Register 0x5C 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRM Peripheral Access Control Register 0x60 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRN Peripheral Access Control Register 0x64 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRO Peripheral Access Control Register 0x68 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRP Peripheral Access Control Register 0x6C 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 DMA Enhanced direct memory access controller DMA_ 0x40008000 0 0x1200 registers DMA0 0 DMA1 1 DMA2 2 DMA3 3 DMA4 4 DMA5 5 DMA6 6 DMA7 7 DMA8 8 DMA9 9 DMA10 10 DMA11 11 DMA12 12 DMA13 13 DMA14 14 DMA15 15 DMA_Error 16 CR Control Register 0 32 read-write 0 0xFFFFFFFF EDBG Enable Debug 1 1 read-write 0 When in debug mode, the DMA continues to operate. #0 1 When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. #1 ERCA Enable Round Robin Channel Arbitration 2 1 read-write 0 Fixed priority arbitration is used for channel selection . #0 1 Round robin arbitration is used for channel selection . #1 HOE Halt On Error 4 1 read-write 0 Normal operation #0 1 Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. #1 HALT Halt DMA Operations 5 1 read-write 0 Normal operation #0 1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. #1 CLM Continuous Link Mode 6 1 read-write 0 A minor loop channel link made to itself goes through channel arbitration before being activated again. #0 1 A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. #1 EMLM Enable Minor Loop Mapping 7 1 read-write 0 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. #0 1 Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. #1 ECX Error Cancel Transfer 16 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. #1 CX Cancel Transfer 17 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. #1 ES Error Status Register 0x4 32 read-only 0 0xFFFFFFFF DBE Destination Bus Error 0 1 read-only 0 No destination bus error #0 1 The last recorded error was a bus error on a destination write #1 SBE Source Bus Error 1 1 read-only 0 No source bus error #0 1 The last recorded error was a bus error on a source read #1 SGE Scatter/Gather Configuration Error 2 1 read-only 0 No scatter/gather configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. #1 NCE NBYTES/CITER Configuration Error 3 1 read-only 0 No NBYTES/CITER configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] #1 DOE Destination Offset Error 4 1 read-only 0 No destination offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. #1 DAE Destination Address Error 5 1 read-only 0 No destination address configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. #1 SOE Source Offset Error 6 1 read-only 0 No source offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. #1 SAE Source Address Error 7 1 read-only 0 No source address configuration error. #0 1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. #1 ERRCHN Error Channel Number or Canceled Channel Number 8 4 read-only CPE Channel Priority Error 14 1 read-only 0 No channel priority error #0 1 The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique. #1 ECX Transfer Canceled 16 1 read-only 0 No canceled transfers #0 1 The last recorded entry was a canceled transfer by the error cancel transfer input #1 VLD Logical OR of all ERR status bits 31 1 read-only 0 No ERR bits are set. #0 1 At least one ERR bit is set indicating a valid error exists that has not been cleared. #1 ERQ Enable Request Register 0xC 32 read-write 0 0xFFFFFFFF ERQ0 Enable DMA Request 0 0 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ1 Enable DMA Request 1 1 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ2 Enable DMA Request 2 2 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ3 Enable DMA Request 3 3 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ4 Enable DMA Request 4 4 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ5 Enable DMA Request 5 5 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ6 Enable DMA Request 6 6 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ7 Enable DMA Request 7 7 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ8 Enable DMA Request 8 8 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ9 Enable DMA Request 9 9 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ10 Enable DMA Request 10 10 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ11 Enable DMA Request 11 11 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ12 Enable DMA Request 12 12 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ13 Enable DMA Request 13 13 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ14 Enable DMA Request 14 14 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ15 Enable DMA Request 15 15 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 EEI Enable Error Interrupt Register 0x14 32 read-write 0 0xFFFFFFFF EEI0 Enable Error Interrupt 0 0 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI1 Enable Error Interrupt 1 1 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI2 Enable Error Interrupt 2 2 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI3 Enable Error Interrupt 3 3 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI4 Enable Error Interrupt 4 4 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI5 Enable Error Interrupt 5 5 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI6 Enable Error Interrupt 6 6 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI7 Enable Error Interrupt 7 7 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI8 Enable Error Interrupt 8 8 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI9 Enable Error Interrupt 9 9 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI10 Enable Error Interrupt 10 10 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI11 Enable Error Interrupt 11 11 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI12 Enable Error Interrupt 12 12 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI13 Enable Error Interrupt 13 13 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI14 Enable Error Interrupt 14 14 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI15 Enable Error Interrupt 15 15 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 CEEI Clear Enable Error Interrupt Register 0x18 8 write-only 0 0xFF CEEI Clear Enable Error Interrupt 0 4 write-only CAEE Clear All Enable Error Interrupts 6 1 write-only 0 Clear only the EEI bit specified in the CEEI field #0 1 Clear all bits in EEI #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SEEI Set Enable Error Interrupt Register 0x19 8 write-only 0 0xFF SEEI Set Enable Error Interrupt 0 4 write-only SAEE Sets All Enable Error Interrupts 6 1 write-only 0 Set only the EEI bit specified in the SEEI field. #0 1 Sets all bits in EEI #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERQ Clear Enable Request Register 0x1A 8 write-only 0 0xFF CERQ Clear Enable Request 0 4 write-only CAER Clear All Enable Requests 6 1 write-only 0 Clear only the ERQ bit specified in the CERQ field #0 1 Clear all bits in ERQ #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SERQ Set Enable Request Register 0x1B 8 write-only 0 0xFF SERQ Set Enable Request 0 4 write-only SAER Set All Enable Requests 6 1 write-only 0 Set only the ERQ bit specified in the SERQ field #0 1 Set all bits in ERQ #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CDNE Clear DONE Status Bit Register 0x1C 8 write-only 0 0xFF CDNE Clear DONE Bit 0 4 write-only CADN Clears All DONE Bits 6 1 write-only 0 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field #0 1 Clears all bits in TCDn_CSR[DONE] #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SSRT Set START Bit Register 0x1D 8 write-only 0 0xFF SSRT Set START Bit 0 4 write-only SAST Set All START Bits (activates all channels) 6 1 write-only 0 Set only the TCDn_CSR[START] bit specified in the SSRT field #0 1 Set all bits in TCDn_CSR[START] #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERR Clear Error Register 0x1E 8 write-only 0 0xFF CERR Clear Error Indicator 0 4 write-only CAEI Clear All Error Indicators 6 1 write-only 0 Clear only the ERR bit specified in the CERR field #0 1 Clear all bits in ERR #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CINT Clear Interrupt Request Register 0x1F 8 write-only 0 0xFF CINT Clear Interrupt Request 0 4 write-only CAIR Clear All Interrupt Requests 6 1 write-only 0 Clear only the INT bit specified in the CINT field #0 1 Clear all bits in INT #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 INT Interrupt Request Register 0x24 32 read-write 0 0xFFFFFFFF INT0 Interrupt Request 0 0 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT1 Interrupt Request 1 1 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT2 Interrupt Request 2 2 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT3 Interrupt Request 3 3 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT4 Interrupt Request 4 4 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT5 Interrupt Request 5 5 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT6 Interrupt Request 6 6 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT7 Interrupt Request 7 7 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT8 Interrupt Request 8 8 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT9 Interrupt Request 9 9 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT10 Interrupt Request 10 10 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT11 Interrupt Request 11 11 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT12 Interrupt Request 12 12 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT13 Interrupt Request 13 13 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT14 Interrupt Request 14 14 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT15 Interrupt Request 15 15 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 ERR Error Register 0x2C 32 read-write 0 0xFFFFFFFF ERR0 Error In Channel 0 0 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR1 Error In Channel 1 1 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR2 Error In Channel 2 2 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR3 Error In Channel 3 3 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR4 Error In Channel 4 4 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR5 Error In Channel 5 5 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR6 Error In Channel 6 6 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR7 Error In Channel 7 7 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR8 Error In Channel 8 8 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR9 Error In Channel 9 9 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR10 Error In Channel 10 10 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR11 Error In Channel 11 11 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR12 Error In Channel 12 12 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR13 Error In Channel 13 13 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR14 Error In Channel 14 14 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR15 Error In Channel 15 15 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 HRS Hardware Request Status Register 0x34 32 read-only 0 0xFFFFFFFF HRS0 Hardware Request Status Channel 0 0 1 read-only 0 A hardware service request for channel 0 is not present #0 1 A hardware service request for channel 0 is present #1 HRS1 Hardware Request Status Channel 1 1 1 read-only 0 A hardware service request for channel 1 is not present #0 1 A hardware service request for channel 1 is present #1 HRS2 Hardware Request Status Channel 2 2 1 read-only 0 A hardware service request for channel 2 is not present #0 1 A hardware service request for channel 2 is present #1 HRS3 Hardware Request Status Channel 3 3 1 read-only 0 A hardware service request for channel 3 is not present #0 1 A hardware service request for channel 3 is present #1 HRS4 Hardware Request Status Channel 4 4 1 read-only 0 A hardware service request for channel 4 is not present #0 1 A hardware service request for channel 4 is present #1 HRS5 Hardware Request Status Channel 5 5 1 read-only 0 A hardware service request for channel 5 is not present #0 1 A hardware service request for channel 5 is present #1 HRS6 Hardware Request Status Channel 6 6 1 read-only 0 A hardware service request for channel 6 is not present #0 1 A hardware service request for channel 6 is present #1 HRS7 Hardware Request Status Channel 7 7 1 read-only 0 A hardware service request for channel 7 is not present #0 1 A hardware service request for channel 7 is present #1 HRS8 Hardware Request Status Channel 8 8 1 read-only 0 A hardware service request for channel 8 is not present #0 1 A hardware service request for channel 8 is present #1 HRS9 Hardware Request Status Channel 9 9 1 read-only 0 A hardware service request for channel 9 is not present #0 1 A hardware service request for channel 9 is present #1 HRS10 Hardware Request Status Channel 10 10 1 read-only 0 A hardware service request for channel 10 is not present #0 1 A hardware service request for channel 10 is present #1 HRS11 Hardware Request Status Channel 11 11 1 read-only 0 A hardware service request for channel 11 is not present #0 1 A hardware service request for channel 11 is present #1 HRS12 Hardware Request Status Channel 12 12 1 read-only 0 A hardware service request for channel 12 is not present #0 1 A hardware service request for channel 12 is present #1 HRS13 Hardware Request Status Channel 13 13 1 read-only 0 A hardware service request for channel 13 is not present #0 1 A hardware service request for channel 13 is present #1 HRS14 Hardware Request Status Channel 14 14 1 read-only 0 A hardware service request for channel 14 is not present #0 1 A hardware service request for channel 14 is present #1 HRS15 Hardware Request Status Channel 15 15 1 read-only 0 A hardware service request for channel 15 is not present #0 1 A hardware service request for channel 15 is present #1 EARS Enable Asynchronous Request in Stop Register 0x44 32 read-write 0 0xFFFFFFFF EDREQ_0 Enable asynchronous DMA request in stop mode for channel 0. 0 1 read-write 0 Disable asynchronous DMA request for channel 0. #0 1 Enable asynchronous DMA request for channel 0. #1 EDREQ_1 Enable asynchronous DMA request in stop mode for channel 1. 1 1 read-write 0 Disable asynchronous DMA request for channel 1 #0 1 Enable asynchronous DMA request for channel 1. #1 EDREQ_2 Enable asynchronous DMA request in stop mode for channel 2. 2 1 read-write 0 Disable asynchronous DMA request for channel 2. #0 1 Enable asynchronous DMA request for channel 2. #1 EDREQ_3 Enable asynchronous DMA request in stop mode for channel 3. 3 1 read-write 0 Disable asynchronous DMA request for channel 3. #0 1 Enable asynchronous DMA request for channel 3. #1 EDREQ_4 Enable asynchronous DMA request in stop mode for channel 4 4 1 read-write 0 Disable asynchronous DMA request for channel 4. #0 1 Enable asynchronous DMA request for channel 4. #1 EDREQ_5 Enable asynchronous DMA request in stop mode for channel 5 5 1 read-write 0 Disable asynchronous DMA request for channel 5. #0 1 Enable asynchronous DMA request for channel 5. #1 EDREQ_6 Enable asynchronous DMA request in stop mode for channel 6 6 1 read-write 0 Disable asynchronous DMA request for channel 6. #0 1 Enable asynchronous DMA request for channel 6. #1 EDREQ_7 Enable asynchronous DMA request in stop mode for channel 7 7 1 read-write 0 Disable asynchronous DMA request for channel 7. #0 1 Enable asynchronous DMA request for channel 7. #1 EDREQ_8 Enable asynchronous DMA request in stop mode for channel 8 8 1 read-write 0 Disable asynchronous DMA request for channel 8. #0 1 Enable asynchronous DMA request for channel 8. #1 EDREQ_9 Enable asynchronous DMA request in stop mode for channel 9 9 1 read-write 0 Disable asynchronous DMA request for channel 9. #0 1 Enable asynchronous DMA request for channel 9. #1 EDREQ_10 Enable asynchronous DMA request in stop mode for channel 10 10 1 read-write 0 Disable asynchronous DMA request for channel 10. #0 1 Enable asynchronous DMA request for channel 10. #1 EDREQ_11 Enable asynchronous DMA request in stop mode for channel 11 11 1 read-write 0 Disable asynchronous DMA request for channel 11. #0 1 Enable asynchronous DMA request for channel 11. #1 EDREQ_12 Enable asynchronous DMA request in stop mode for channel 12 12 1 read-write 0 Disable asynchronous DMA request for channel 12. #0 1 Enable asynchronous DMA request for channel 12. #1 EDREQ_13 Enable asynchronous DMA request in stop mode for channel 13 13 1 read-write 0 Disable asynchronous DMA request for channel 13. #0 1 Enable asynchronous DMA request for channel 13. #1 EDREQ_14 Enable asynchronous DMA request in stop mode for channel 14 14 1 read-write 0 Disable asynchronous DMA request for channel 14. #0 1 Enable asynchronous DMA request for channel 14. #1 EDREQ_15 Enable asynchronous DMA request in stop mode for channel 15 15 1 read-write 0 Disable asynchronous DMA request for channel 15. #0 1 Enable asynchronous DMA request for channel 15. #1 16 0x1 3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12 DCHPRI%s Channel n Priority Register 0x100 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 16 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 TCD%s_SADDR TCD Source Address 0x1000 32 read-write 0 0 SADDR Source Address 0 32 read-write 16 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 TCD%s_SOFF TCD Signed Source Address Offset 0x1004 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write 16 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 TCD%s_ATTR TCD Transfer Attributes 0x1006 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 16 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 TCD%s_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write 16 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 TCD%s_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 16 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 TCD%s_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 16 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 TCD%s_SLAST TCD Last Source Address Adjustment 0x100C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write 16 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 TCD%s_DADDR TCD Destination Address 0x1010 32 read-write 0 0 DADDR Destination Address 0 32 read-write 16 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 TCD%s_DOFF TCD Signed Destination Address Offset 0x1014 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write 16 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 TCD%s_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1016 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 16 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 TCD%s_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1016 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 16 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 TCD%s_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1018 32 read-write 0 0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write 16 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 TCD%s_CSR TCD Control and Status 0x101C 16 read-write 0 0 START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 ACTIVE Channel Active 6 1 read-write DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 16 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 TCD%s_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x101E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 16 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 TCD%s_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x101E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 FMC Flash Memory Controller FMC_ 0x4001F000 0 0x280 registers PFAPR Flash Access Protection Register 0 32 read-write 0xF8003F 0xFFFFFFFF M0AP Master 0 Access Protection 0 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M1AP Master 1 Access Protection 2 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M2AP Master 2 Access Protection 4 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M0PFD Master 0 Prefetch Disable 16 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M1PFD Master 1 Prefetch Disable 17 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M2PFD Master 2 Prefetch Disable 18 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 PFB0CR Flash Bank 0 Control Register 0x4 32 read-write 0x3004001F 0xFFFFFFFF B0SEBE Bank 0 Single Entry Buffer Enable 0 1 read-write 0 Single entry buffer is disabled. #0 1 Single entry buffer is enabled. #1 B0IPE Bank 0 Instruction Prefetch Enable 1 1 read-write 0 Do not prefetch in response to instruction fetches. #0 1 Enable prefetches in response to instruction fetches. #1 B0DPE Bank 0 Data Prefetch Enable 2 1 read-write 0 Do not prefetch in response to data references. #0 1 Enable prefetches in response to data references. #1 B0ICE Bank 0 Instruction Cache Enable 3 1 read-write 0 Do not cache instruction fetches. #0 1 Cache instruction fetches. #1 B0DCE Bank 0 Data Cache Enable 4 1 read-write 0 Do not cache data references. #0 1 Cache data references. #1 CRC Cache Replacement Control 5 3 read-write 000 LRU replacement algorithm per set across all four ways #000 010 Independent LRU with ways [0-1] for ifetches, [2-3] for data #010 011 Independent LRU with ways [0-2] for ifetches, [3] for data #011 B0MW Bank 0 Memory Width 17 2 read-only 00 32 bits #00 01 64 bits #01 10 128 bits #10 S_B_INV Invalidate Prefetch Speculation Buffer 19 1 write-only 0 Speculation buffer and single entry buffer are not affected. #0 1 Invalidate (clear) speculation buffer and single entry buffer. #1 CINV_WAY Cache Invalidate Way x 20 4 write-only 0 No cache way invalidation for the corresponding cache #0000 1 Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected #0001 CLCK_WAY Cache Lock Way x 24 4 read-write 0 Cache way is unlocked and may be displaced #0000 1 Cache way is locked and its contents are not displaced #0001 B0RWSC Bank 0 Read Wait State Control 28 4 read-only 2 0x4 0,1 TAGVDW0S%s Cache Tag Storage 0x100 32 read-write 0 0xFFFFFFFF valid 1-bit valid for cache entry 0 1 read-write cache_tag the tag for cache entry 5 15 read-write 2 0x4 0,1 TAGVDW1S%s Cache Tag Storage 0x108 32 read-write 0 0xFFFFFFFF valid 1-bit valid for cache entry 0 1 read-write cache_tag the tag for cache entry 5 15 read-write 2 0x4 0,1 TAGVDW2S%s Cache Tag Storage 0x110 32 read-write 0 0xFFFFFFFF valid 1-bit valid for cache entry 0 1 read-write cache_tag the tag for cache entry 5 15 read-write 2 0x4 0,1 TAGVDW3S%s Cache Tag Storage 0x118 32 read-write 0 0xFFFFFFFF valid 1-bit valid for cache entry 0 1 read-write cache_tag the tag for cache entry 5 15 read-write 2 0x10 0,1 DATAW0S%sUM Cache Data Storage (uppermost word) 0x200 32 read-write 0 0xFFFFFFFF data Bits [127:96] of data entry 0 32 read-write 2 0x10 0,1 DATAW0S%sMU Cache Data Storage (mid-upper word) 0x204 32 read-write 0 0xFFFFFFFF data Bits [95:64] of data entry 0 32 read-write 2 0x10 0,1 DATAW0S%sML Cache Data Storage (mid-lower word) 0x208 32 read-write 0 0xFFFFFFFF data Bits [63:32] of data entry 0 32 read-write 2 0x10 0,1 DATAW0S%sLM Cache Data Storage (lowermost word) 0x20C 32 read-write 0 0xFFFFFFFF data Bits [31:0] of data entry 0 32 read-write 2 0x10 0,1 DATAW1S%sUM Cache Data Storage (uppermost word) 0x220 32 read-write 0 0xFFFFFFFF data Bits [127:96] of data entry 0 32 read-write 2 0x10 0,1 DATAW1S%sMU Cache Data Storage (mid-upper word) 0x224 32 read-write 0 0xFFFFFFFF data Bits [95:64] of data entry 0 32 read-write 2 0x10 0,1 DATAW1S%sML Cache Data Storage (mid-lower word) 0x228 32 read-write 0 0xFFFFFFFF data Bits [63:32] of data entry 0 32 read-write 2 0x10 0,1 DATAW1S%sLM Cache Data Storage (lowermost word) 0x22C 32 read-write 0 0xFFFFFFFF data Bits [31:0] of data entry 0 32 read-write 2 0x10 0,1 DATAW2S%sUM Cache Data Storage (uppermost word) 0x240 32 read-write 0 0xFFFFFFFF data Bits [127:96] of data entry 0 32 read-write 2 0x10 0,1 DATAW2S%sMU Cache Data Storage (mid-upper word) 0x244 32 read-write 0 0xFFFFFFFF data Bits [95:64] of data entry 0 32 read-write 2 0x10 0,1 DATAW2S%sML Cache Data Storage (mid-lower word) 0x248 32 read-write 0 0xFFFFFFFF data Bits [63:32] of data entry 0 32 read-write 2 0x10 0,1 DATAW2S%sLM Cache Data Storage (lowermost word) 0x24C 32 read-write 0 0xFFFFFFFF data Bits [31:0] of data entry 0 32 read-write 2 0x10 0,1 DATAW3S%sUM Cache Data Storage (uppermost word) 0x260 32 read-write 0 0xFFFFFFFF data Bits [127:96] of data entry 0 32 read-write 2 0x10 0,1 DATAW3S%sMU Cache Data Storage (mid-upper word) 0x264 32 read-write 0 0xFFFFFFFF data Bits [95:64] of data entry 0 32 read-write 2 0x10 0,1 DATAW3S%sML Cache Data Storage (mid-lower word) 0x268 32 read-write 0 0xFFFFFFFF data Bits [63:32] of data entry 0 32 read-write 2 0x10 0,1 DATAW3S%sLM Cache Data Storage (lowermost word) 0x26C 32 read-write 0 0xFFFFFFFF data Bits [31:0] of data entry 0 32 read-write FTFA Flash Memory Interface FTFA_ 0x40020000 0 0x2C registers FTFA 18 FTFA_Collision 19 FSTAT Flash Status Register 0 8 read-write 0 0xFF MGSTAT0 Memory Controller Command Completion Status Flag 0 1 read-only FPVIOL Flash Protection Violation Flag 4 1 read-write 0 No protection violation detected #0 1 Protection violation detected #1 ACCERR Flash Access Error Flag 5 1 read-write 0 No access error detected #0 1 Access error detected #1 RDCOLERR Flash Read Collision Error Flag 6 1 read-write 0 No collision error detected #0 1 Collision error detected #1 CCIF Command Complete Interrupt Flag 7 1 read-write 0 Flash command in progress #0 1 Flash command has completed #1 FCNFG Flash Configuration Register 0x1 8 read-write 0 0xFF ERSSUSP Erase Suspend 4 1 read-write 0 No suspend requested #0 1 Suspend the current Erase Flash Sector command execution. #1 ERSAREQ Erase All Request 5 1 read-only 0 No request or request complete #0 1 Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state. #1 RDCOLLIE Read Collision Error Interrupt Enable 6 1 read-write 0 Read collision error interrupt disabled #0 1 Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]). #1 CCIE Command Complete Interrupt Enable 7 1 read-write 0 Command complete interrupt disabled #0 1 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. #1 FSEC Flash Security Register 0x2 8 read-only 0 0 SEC Flash Security 0 2 read-only 00 MCU security status is secure. #00 01 MCU security status is secure. #01 10 MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.) #10 11 MCU security status is secure. #11 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 00 Freescale factory access granted #00 01 Freescale factory access denied #01 10 Freescale factory access denied #10 11 Freescale factory access granted #11 MEEN Mass Erase Enable 4 2 read-only 00 Mass erase is enabled #00 01 Mass erase is enabled #01 10 Mass erase is disabled #10 11 Mass erase is enabled #11 KEYEN Backdoor Key Security Enable 6 2 read-only 00 Backdoor key access disabled #00 01 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) #01 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 FOPT Flash Option Register 0x3 8 read-only 0 0 OPT Nonvolatile Option 0 8 read-only 12 0x1 3,2,1,0,7,6,5,4,B,A,9,8 FCCOB%s Flash Common Command Object Registers 0x4 8 read-write 0 0xFF CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write 4 0x1 3,2,1,0 FPROT%s Program Flash Protection Registers 0x10 8 read-write 0 0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 8 0x1 H3,H2,H1,H0,L3,L2,L1,L0 XACC%s Execute-only Access Registers 0x18 8 read-only 0 0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 8 0x1 H3,H2,H1,H0,L3,L2,L1,L0 SACC%s Supervisor-only Access Registers 0x20 8 read-only 0 0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 FACSS Flash Access Segment Size Register 0x28 8 read-only 0 0 SGSIZE Segment Size 0 8 read-only FACSN Flash Access Segment Number Register 0x2B 8 read-only 0 0 NUMSG Number of Segments Indicator 0 8 read-only 100000 Program flash memory is divided into 32 segments (64 Kbytes, 128 Kbytes) #100000 101000 Program flash memory is divided into 40 segments (160 Kbytes) #101000 1000000 Program flash memory is divided into 64 segments (256 Kbytes, 512 Kbytes) #1000000 DMAMUX DMA channel multiplexor DMAMUX_ 0x40021000 0 0x10 registers 16 0x1 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 CHCFG%s Channel Configuration register 0 8 read-write 0 0xFF SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 CAN0 Flex Controller Area Network module CAN CAN0_ 0x40024000 0 0x8C0 registers CAN0_ORed_Message_buffer 75 CAN0_Bus_Off 76 CAN0_Error 77 CAN0_Tx_Warning 78 CAN0_Rx_Warning 79 CAN0_Wake_Up 80 MCR Module Configuration Register 0 32 read-write 0xD890000F 0xFFFFFFFF MAXMB Number Of The Last Message Buffer 0 7 read-write IDAM ID Acceptance Mode 8 2 read-write 00 Format A: One full ID (standard and extended) per ID Filter Table element. #00 01 Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. #01 10 Format C: Four partial 8-bit Standard IDs per ID Filter Table element. #10 11 Format D: All frames rejected. #11 AEN Abort Enable 12 1 read-write 0 Abort disabled. #0 1 Abort enabled. #1 LPRIOEN Local Priority Enable 13 1 read-write 0 Local Priority disabled. #0 1 Local Priority enabled. #1 DMA DMA Enable 15 1 read-write 0 DMA feature for RX FIFO disabled. #0 1 DMA feature for RX FIFO enabled. #1 IRMQ Individual Rx Masking And Queue Enable 16 1 read-write 0 Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. #0 1 Individual Rx masking and queue feature are enabled. #1 SRXDIS Self Reception Disable 17 1 read-write 0 Self reception enabled. #0 1 Self reception disabled. #1 DOZE Doze Mode Enable 18 1 read-write 0 FlexCAN is not enabled to enter low-power mode when Doze mode is requested. #0 1 FlexCAN is enabled to enter low-power mode when Doze mode is requested. #1 WAKSRC Wake Up Source 19 1 read-write 0 FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. #0 1 FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. #1 LPMACK Low-Power Mode Acknowledge 20 1 read-only 0 FlexCAN is not in a low-power mode. #0 1 FlexCAN is in a low-power mode. #1 WRNEN Warning Interrupt Enable 21 1 read-write 0 TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. #0 1 TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. #1 SLFWAK Self Wake Up 22 1 read-write 0 FlexCAN Self Wake Up feature is disabled. #0 1 FlexCAN Self Wake Up feature is enabled. #1 SUPV Supervisor Mode 23 1 read-write 0 FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. #0 1 FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location. #1 FRZACK Freeze Mode Acknowledge 24 1 read-only 0 FlexCAN not in Freeze mode, prescaler running. #0 1 FlexCAN in Freeze mode, prescaler stopped. #1 SOFTRST Soft Reset 25 1 read-write 0 No reset request. #0 1 Resets the registers affected by soft reset. #1 WAKMSK Wake Up Interrupt Mask 26 1 read-write 0 Wake Up Interrupt is disabled. #0 1 Wake Up Interrupt is enabled. #1 NOTRDY FlexCAN Not Ready 27 1 read-only 0 FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. #0 1 FlexCAN module is either in Disable mode, Doze mode , Stop mode or Freeze mode. #1 HALT Halt FlexCAN 28 1 read-write 0 No Freeze mode request. #0 1 Enters Freeze mode if the FRZ bit is asserted. #1 RFEN Rx FIFO Enable 29 1 read-write 0 Rx FIFO not enabled. #0 1 Rx FIFO enabled. #1 FRZ Freeze Enable 30 1 read-write 0 Not enabled to enter Freeze mode. #0 1 Enabled to enter Freeze mode. #1 MDIS Module Disable 31 1 read-write 0 Enable the FlexCAN module. #0 1 Disable the FlexCAN module. #1 CTRL1 Control 1 register 0x4 32 read-write 0 0xFFFFFFFF PROPSEG Propagation Segment 0 3 read-write LOM Listen-Only Mode 3 1 read-write 0 Listen-Only mode is deactivated. #0 1 FlexCAN module operates in Listen-Only mode. #1 LBUF Lowest Buffer Transmitted First 4 1 read-write 0 Buffer with highest priority is transmitted first. #0 1 Lowest number buffer is transmitted first. #1 TSYN Timer Sync 5 1 read-write 0 Timer Sync feature disabled #0 1 Timer Sync feature enabled #1 BOFFREC Bus Off Recovery 6 1 read-write 0 Automatic recovering from Bus Off state enabled. #0 1 Automatic recovering from Bus Off state disabled. #1 SMP CAN Bit Sampling 7 1 read-write 0 Just one sample is used to determine the bit value. #0 1 Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used. #1 RWRNMSK Rx Warning Interrupt Mask 10 1 read-write 0 Rx Warning Interrupt disabled. #0 1 Rx Warning Interrupt enabled. #1 TWRNMSK Tx Warning Interrupt Mask 11 1 read-write 0 Tx Warning Interrupt disabled. #0 1 Tx Warning Interrupt enabled. #1 LPB Loop Back Mode 12 1 read-write 0 Loop Back disabled. #0 1 Loop Back enabled. #1 CLKSRC CAN Engine Clock Source 13 1 read-write 0 The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. #0 1 The CAN engine clock source is the peripheral clock. #1 ERRMSK Error Interrupt Mask 14 1 read-write 0 Error interrupt disabled. #0 1 Error interrupt enabled. #1 BOFFMSK Bus Off Interrupt Mask 15 1 read-write 0 Bus Off interrupt disabled. #0 1 Bus Off interrupt enabled. #1 PSEG2 Phase Segment 2 16 3 read-write PSEG1 Phase Segment 1 19 3 read-write RJW Resync Jump Width 22 2 read-write PRESDIV Prescaler Division Factor 24 8 read-write TIMER Free Running Timer 0x8 32 read-write 0 0xFFFFFFFF TIMER Timer Value 0 16 read-write RXMGMASK Rx Mailboxes Global Mask Register 0x10 32 read-write 0 0 MG Rx Mailboxes Global Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RX14MASK Rx 14 Mask register 0x14 32 read-write 0 0 RX14M Rx Buffer 14 Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RX15MASK Rx 15 Mask register 0x18 32 read-write 0 0 RX15M Rx Buffer 15 Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 ECR Error Counter 0x1C 32 read-write 0 0xFFFFFFFF TXERRCNT Transmit Error Counter 0 8 read-write RXERRCNT Receive Error Counter 8 8 read-write ESR1 Error and Status 1 register 0x20 32 read-write 0 0xFFFFFFFF WAKINT Wake-Up Interrupt 0 1 read-write 0 No such occurrence. #0 1 Indicates a recessive to dominant transition was received on the CAN bus. #1 ERRINT Error Interrupt 1 1 read-write 0 No such occurrence. #0 1 Indicates setting of any Error Bit in the Error and Status Register. #1 BOFFINT Bus Off Interrupt 2 1 read-write 0 No such occurrence. #0 1 FlexCAN module entered Bus Off state. #1 RX FlexCAN In Reception 3 1 read-only 0 FlexCAN is not receiving a message. #0 1 FlexCAN is receiving a message. #1 FLTCONF Fault Confinement State 4 2 read-only 00 Error Active #00 01 Error Passive #01 1x Bus Off #1x TX FlexCAN In Transmission 6 1 read-only 0 FlexCAN is not transmitting a message. #0 1 FlexCAN is transmitting a message. #1 IDLE This bit indicates when CAN bus is in IDLE state 7 1 read-only 0 No such occurrence. #0 1 CAN bus is now IDLE. #1 RXWRN Rx Error Warning 8 1 read-only 0 No such occurrence. #0 1 RXERRCNT is greater than or equal to 96. #1 TXWRN TX Error Warning 9 1 read-only 0 No such occurrence. #0 1 TXERRCNT is greater than or equal to 96. #1 STFERR Stuffing Error 10 1 read-only 0 No such occurrence. #0 1 A Stuffing Error occurred since last read of this register. #1 FRMERR Form Error 11 1 read-only 0 No such occurrence. #0 1 A Form Error occurred since last read of this register. #1 CRCERR Cyclic Redundancy Check Error 12 1 read-only 0 No such occurrence. #0 1 A CRC error occurred since last read of this register. #1 ACKERR Acknowledge Error 13 1 read-only 0 No such occurrence. #0 1 An ACK error occurred since last read of this register. #1 BIT0ERR Bit0 Error 14 1 read-only 0 No such occurrence. #0 1 At least one bit sent as dominant is received as recessive. #1 BIT1ERR Bit1 Error 15 1 read-only 0 No such occurrence. #0 1 At least one bit sent as recessive is received as dominant. #1 RWRNINT Rx Warning Interrupt Flag 16 1 read-write 0 No such occurrence. #0 1 The Rx error counter transitioned from less than 96 to greater than or equal to 96. #1 TWRNINT Tx Warning Interrupt Flag 17 1 read-write 0 No such occurrence. #0 1 The Tx error counter transitioned from less than 96 to greater than or equal to 96. #1 SYNCH CAN Synchronization Status 18 1 read-only 0 FlexCAN is not synchronized to the CAN bus. #0 1 FlexCAN is synchronized to the CAN bus. #1 BOFFDONEINT Bus Off Done Interrupt 19 1 read-write 0 No such occurrence. #0 1 FlexCAN module has completed Bus Off process. #1 ERROVR Error Overrun bit 21 1 read-write 0 Overrun has not occurred. #0 1 Overrun has occured. #1 IMASK1 Interrupt Masks 1 register 0x28 32 read-write 0 0xFFFFFFFF BUF31TO0M Buffer MB i Mask 0 32 read-write 0 The corresponding buffer Interrupt is disabled. #0 1 The corresponding buffer Interrupt is enabled. #1 IFLAG1 Interrupt Flags 1 register 0x30 32 read-write 0 0xFFFFFFFF BUF0I Buffer MB0 Interrupt Or Clear FIFO bit 0 1 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. #0 1 The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. #1 BUF4TO1I Buffer MB i Interrupt Or "reserved" 1 4 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. #0000 1 The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. #0001 BUF5I Buffer MB5 Interrupt Or "Frames available in Rx FIFO" 5 1 read-write 0 No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 #0 1 MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled. #1 BUF6I Buffer MB6 Interrupt Or "Rx FIFO Warning" 6 1 read-write 0 No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 #0 1 MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1 #1 BUF7I Buffer MB7 Interrupt Or "Rx FIFO Overflow" 7 1 read-write 0 No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 #0 1 MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1 #1 BUF31TO8I Buffer MBi Interrupt 8 24 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception. #0 1 The corresponding buffer has successfully completed transmission or reception. #1 CTRL2 Control 2 register 0x34 32 read-write 0xB00000 0xFFFFFFFF EACEN Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 16 1 read-write 0 Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. #0 1 Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. #1 RRS Remote Request Storing 17 1 read-write 0 Remote Response Frame is generated. #0 1 Remote Request Frame is stored. #1 MRP Mailboxes Reception Priority 18 1 read-write 0 Matching starts from Rx FIFO and continues on Mailboxes. #0 1 Matching starts from Mailboxes and continues on Rx FIFO. #1 TASD Tx Arbitration Start Delay 19 5 read-write RFFN Number Of Rx FIFO Filters 24 4 read-write BOFFDONEMSK Bus Off Done Interrupt Mask 30 1 read-write 0 Bus Off Done interrupt disabled. #0 1 Bus Off Done interrupt enabled. #1 ESR2 Error and Status 2 register 0x38 32 read-only 0 0xFFFFFFFF IMB Inactive Mailbox 13 1 read-only 0 If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. #0 1 If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. #1 VPS Valid Priority Status 14 1 read-only 0 Contents of IMB and LPTM are invalid. #0 1 Contents of IMB and LPTM are valid. #1 LPTM Lowest Priority Tx Mailbox 16 7 read-only CRCR CRC Register 0x44 32 read-only 0 0xFFFFFFFF TXCRC Transmitted CRC value 0 15 read-only MBCRC CRC Mailbox 16 7 read-only RXFGMASK Rx FIFO Global Mask register 0x48 32 read-write 0 0 FGM Rx FIFO Global Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXFIR Rx FIFO Information Register 0x4C 32 read-only 0 0 IDHIT Identifier Acceptance Filter Hit Indicator 0 9 read-only CBT CAN Bit Timing Register 0x50 32 read-write 0 0xFFFFFFFF EPSEG2 Extended Phase Segment 2 0 5 read-write EPSEG1 Extended Phase Segment 1 5 5 read-write EPROPSEG Extended Propagation Segment 10 6 read-write ERJW Extended Resync Jump Width 16 4 read-write EPRESDIV Extended Prescaler Division Factor 21 10 read-write BTF Bit Timing Format Enable 31 1 read-write 0 Extended bit time definitions disabled. #0 1 Extended bit time definitions enabled. #1 CS0 Message Buffer 0 CS Register 0x80 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID0 Message Buffer 0 ID Register 0x84 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD00 Message Buffer 0 WORD0 Register 0x88 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD10 Message Buffer 0 WORD1 Register 0x8C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS1 Message Buffer 1 CS Register 0x90 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID1 Message Buffer 1 ID Register 0x94 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD01 Message Buffer 1 WORD0 Register 0x98 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD11 Message Buffer 1 WORD1 Register 0x9C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS2 Message Buffer 2 CS Register 0xA0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID2 Message Buffer 2 ID Register 0xA4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD02 Message Buffer 2 WORD0 Register 0xA8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD12 Message Buffer 2 WORD1 Register 0xAC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS3 Message Buffer 3 CS Register 0xB0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID3 Message Buffer 3 ID Register 0xB4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD03 Message Buffer 3 WORD0 Register 0xB8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD13 Message Buffer 3 WORD1 Register 0xBC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS4 Message Buffer 4 CS Register 0xC0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID4 Message Buffer 4 ID Register 0xC4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD04 Message Buffer 4 WORD0 Register 0xC8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD14 Message Buffer 4 WORD1 Register 0xCC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS5 Message Buffer 5 CS Register 0xD0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID5 Message Buffer 5 ID Register 0xD4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD05 Message Buffer 5 WORD0 Register 0xD8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD15 Message Buffer 5 WORD1 Register 0xDC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS6 Message Buffer 6 CS Register 0xE0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID6 Message Buffer 6 ID Register 0xE4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD06 Message Buffer 6 WORD0 Register 0xE8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD16 Message Buffer 6 WORD1 Register 0xEC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS7 Message Buffer 7 CS Register 0xF0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID7 Message Buffer 7 ID Register 0xF4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD07 Message Buffer 7 WORD0 Register 0xF8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD17 Message Buffer 7 WORD1 Register 0xFC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS8 Message Buffer 8 CS Register 0x100 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID8 Message Buffer 8 ID Register 0x104 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD08 Message Buffer 8 WORD0 Register 0x108 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD18 Message Buffer 8 WORD1 Register 0x10C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS9 Message Buffer 9 CS Register 0x110 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID9 Message Buffer 9 ID Register 0x114 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD09 Message Buffer 9 WORD0 Register 0x118 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD19 Message Buffer 9 WORD1 Register 0x11C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS10 Message Buffer 10 CS Register 0x120 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID10 Message Buffer 10 ID Register 0x124 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD010 Message Buffer 10 WORD0 Register 0x128 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD110 Message Buffer 10 WORD1 Register 0x12C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS11 Message Buffer 11 CS Register 0x130 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID11 Message Buffer 11 ID Register 0x134 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD011 Message Buffer 11 WORD0 Register 0x138 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD111 Message Buffer 11 WORD1 Register 0x13C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS12 Message Buffer 12 CS Register 0x140 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID12 Message Buffer 12 ID Register 0x144 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD012 Message Buffer 12 WORD0 Register 0x148 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD112 Message Buffer 12 WORD1 Register 0x14C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS13 Message Buffer 13 CS Register 0x150 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID13 Message Buffer 13 ID Register 0x154 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD013 Message Buffer 13 WORD0 Register 0x158 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD113 Message Buffer 13 WORD1 Register 0x15C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS14 Message Buffer 14 CS Register 0x160 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID14 Message Buffer 14 ID Register 0x164 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD014 Message Buffer 14 WORD0 Register 0x168 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD114 Message Buffer 14 WORD1 Register 0x16C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS15 Message Buffer 15 CS Register 0x170 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID15 Message Buffer 15 ID Register 0x174 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD015 Message Buffer 15 WORD0 Register 0x178 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD115 Message Buffer 15 WORD1 Register 0x17C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write 16 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 RXIMR%s Rx Individual Mask Registers 0x880 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 CAN1 Flex Controller Area Network module CAN CAN1_ 0x40025000 0 0x8C0 registers CAN1_ORed_Message_buffer 94 CAN1_Bus_Off 95 CAN1_Error 96 CAN1_Tx_Warning 97 CAN1_Rx_Warning 98 CAN1_Wake_Up 99 MCR Module Configuration Register 0 32 read-write 0xD890000F 0xFFFFFFFF MAXMB Number Of The Last Message Buffer 0 7 read-write IDAM ID Acceptance Mode 8 2 read-write 00 Format A: One full ID (standard and extended) per ID Filter Table element. #00 01 Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. #01 10 Format C: Four partial 8-bit Standard IDs per ID Filter Table element. #10 11 Format D: All frames rejected. #11 AEN Abort Enable 12 1 read-write 0 Abort disabled. #0 1 Abort enabled. #1 LPRIOEN Local Priority Enable 13 1 read-write 0 Local Priority disabled. #0 1 Local Priority enabled. #1 DMA DMA Enable 15 1 read-write 0 DMA feature for RX FIFO disabled. #0 1 DMA feature for RX FIFO enabled. #1 IRMQ Individual Rx Masking And Queue Enable 16 1 read-write 0 Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. #0 1 Individual Rx masking and queue feature are enabled. #1 SRXDIS Self Reception Disable 17 1 read-write 0 Self reception enabled. #0 1 Self reception disabled. #1 DOZE Doze Mode Enable 18 1 read-write 0 FlexCAN is not enabled to enter low-power mode when Doze mode is requested. #0 1 FlexCAN is enabled to enter low-power mode when Doze mode is requested. #1 WAKSRC Wake Up Source 19 1 read-write 0 FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. #0 1 FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. #1 LPMACK Low-Power Mode Acknowledge 20 1 read-only 0 FlexCAN is not in a low-power mode. #0 1 FlexCAN is in a low-power mode. #1 WRNEN Warning Interrupt Enable 21 1 read-write 0 TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. #0 1 TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. #1 SLFWAK Self Wake Up 22 1 read-write 0 FlexCAN Self Wake Up feature is disabled. #0 1 FlexCAN Self Wake Up feature is enabled. #1 SUPV Supervisor Mode 23 1 read-write 0 FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. #0 1 FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location. #1 FRZACK Freeze Mode Acknowledge 24 1 read-only 0 FlexCAN not in Freeze mode, prescaler running. #0 1 FlexCAN in Freeze mode, prescaler stopped. #1 SOFTRST Soft Reset 25 1 read-write 0 No reset request. #0 1 Resets the registers affected by soft reset. #1 WAKMSK Wake Up Interrupt Mask 26 1 read-write 0 Wake Up Interrupt is disabled. #0 1 Wake Up Interrupt is enabled. #1 NOTRDY FlexCAN Not Ready 27 1 read-only 0 FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. #0 1 FlexCAN module is either in Disable mode, Doze mode , Stop mode or Freeze mode. #1 HALT Halt FlexCAN 28 1 read-write 0 No Freeze mode request. #0 1 Enters Freeze mode if the FRZ bit is asserted. #1 RFEN Rx FIFO Enable 29 1 read-write 0 Rx FIFO not enabled. #0 1 Rx FIFO enabled. #1 FRZ Freeze Enable 30 1 read-write 0 Not enabled to enter Freeze mode. #0 1 Enabled to enter Freeze mode. #1 MDIS Module Disable 31 1 read-write 0 Enable the FlexCAN module. #0 1 Disable the FlexCAN module. #1 CTRL1 Control 1 register 0x4 32 read-write 0 0xFFFFFFFF PROPSEG Propagation Segment 0 3 read-write LOM Listen-Only Mode 3 1 read-write 0 Listen-Only mode is deactivated. #0 1 FlexCAN module operates in Listen-Only mode. #1 LBUF Lowest Buffer Transmitted First 4 1 read-write 0 Buffer with highest priority is transmitted first. #0 1 Lowest number buffer is transmitted first. #1 TSYN Timer Sync 5 1 read-write 0 Timer Sync feature disabled #0 1 Timer Sync feature enabled #1 BOFFREC Bus Off Recovery 6 1 read-write 0 Automatic recovering from Bus Off state enabled. #0 1 Automatic recovering from Bus Off state disabled. #1 SMP CAN Bit Sampling 7 1 read-write 0 Just one sample is used to determine the bit value. #0 1 Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used. #1 RWRNMSK Rx Warning Interrupt Mask 10 1 read-write 0 Rx Warning Interrupt disabled. #0 1 Rx Warning Interrupt enabled. #1 TWRNMSK Tx Warning Interrupt Mask 11 1 read-write 0 Tx Warning Interrupt disabled. #0 1 Tx Warning Interrupt enabled. #1 LPB Loop Back Mode 12 1 read-write 0 Loop Back disabled. #0 1 Loop Back enabled. #1 CLKSRC CAN Engine Clock Source 13 1 read-write 0 The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. #0 1 The CAN engine clock source is the peripheral clock. #1 ERRMSK Error Interrupt Mask 14 1 read-write 0 Error interrupt disabled. #0 1 Error interrupt enabled. #1 BOFFMSK Bus Off Interrupt Mask 15 1 read-write 0 Bus Off interrupt disabled. #0 1 Bus Off interrupt enabled. #1 PSEG2 Phase Segment 2 16 3 read-write PSEG1 Phase Segment 1 19 3 read-write RJW Resync Jump Width 22 2 read-write PRESDIV Prescaler Division Factor 24 8 read-write TIMER Free Running Timer 0x8 32 read-write 0 0xFFFFFFFF TIMER Timer Value 0 16 read-write RXMGMASK Rx Mailboxes Global Mask Register 0x10 32 read-write 0 0 MG Rx Mailboxes Global Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RX14MASK Rx 14 Mask register 0x14 32 read-write 0 0 RX14M Rx Buffer 14 Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RX15MASK Rx 15 Mask register 0x18 32 read-write 0 0 RX15M Rx Buffer 15 Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 ECR Error Counter 0x1C 32 read-write 0 0xFFFFFFFF TXERRCNT Transmit Error Counter 0 8 read-write RXERRCNT Receive Error Counter 8 8 read-write ESR1 Error and Status 1 register 0x20 32 read-write 0 0xFFFFFFFF WAKINT Wake-Up Interrupt 0 1 read-write 0 No such occurrence. #0 1 Indicates a recessive to dominant transition was received on the CAN bus. #1 ERRINT Error Interrupt 1 1 read-write 0 No such occurrence. #0 1 Indicates setting of any Error Bit in the Error and Status Register. #1 BOFFINT Bus Off Interrupt 2 1 read-write 0 No such occurrence. #0 1 FlexCAN module entered Bus Off state. #1 RX FlexCAN In Reception 3 1 read-only 0 FlexCAN is not receiving a message. #0 1 FlexCAN is receiving a message. #1 FLTCONF Fault Confinement State 4 2 read-only 00 Error Active #00 01 Error Passive #01 1x Bus Off #1x TX FlexCAN In Transmission 6 1 read-only 0 FlexCAN is not transmitting a message. #0 1 FlexCAN is transmitting a message. #1 IDLE This bit indicates when CAN bus is in IDLE state 7 1 read-only 0 No such occurrence. #0 1 CAN bus is now IDLE. #1 RXWRN Rx Error Warning 8 1 read-only 0 No such occurrence. #0 1 RXERRCNT is greater than or equal to 96. #1 TXWRN TX Error Warning 9 1 read-only 0 No such occurrence. #0 1 TXERRCNT is greater than or equal to 96. #1 STFERR Stuffing Error 10 1 read-only 0 No such occurrence. #0 1 A Stuffing Error occurred since last read of this register. #1 FRMERR Form Error 11 1 read-only 0 No such occurrence. #0 1 A Form Error occurred since last read of this register. #1 CRCERR Cyclic Redundancy Check Error 12 1 read-only 0 No such occurrence. #0 1 A CRC error occurred since last read of this register. #1 ACKERR Acknowledge Error 13 1 read-only 0 No such occurrence. #0 1 An ACK error occurred since last read of this register. #1 BIT0ERR Bit0 Error 14 1 read-only 0 No such occurrence. #0 1 At least one bit sent as dominant is received as recessive. #1 BIT1ERR Bit1 Error 15 1 read-only 0 No such occurrence. #0 1 At least one bit sent as recessive is received as dominant. #1 RWRNINT Rx Warning Interrupt Flag 16 1 read-write 0 No such occurrence. #0 1 The Rx error counter transitioned from less than 96 to greater than or equal to 96. #1 TWRNINT Tx Warning Interrupt Flag 17 1 read-write 0 No such occurrence. #0 1 The Tx error counter transitioned from less than 96 to greater than or equal to 96. #1 SYNCH CAN Synchronization Status 18 1 read-only 0 FlexCAN is not synchronized to the CAN bus. #0 1 FlexCAN is synchronized to the CAN bus. #1 BOFFDONEINT Bus Off Done Interrupt 19 1 read-write 0 No such occurrence. #0 1 FlexCAN module has completed Bus Off process. #1 ERROVR Error Overrun bit 21 1 read-write 0 Overrun has not occurred. #0 1 Overrun has occured. #1 IMASK1 Interrupt Masks 1 register 0x28 32 read-write 0 0xFFFFFFFF BUF31TO0M Buffer MB i Mask 0 32 read-write 0 The corresponding buffer Interrupt is disabled. #0 1 The corresponding buffer Interrupt is enabled. #1 IFLAG1 Interrupt Flags 1 register 0x30 32 read-write 0 0xFFFFFFFF BUF0I Buffer MB0 Interrupt Or Clear FIFO bit 0 1 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. #0 1 The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. #1 BUF4TO1I Buffer MB i Interrupt Or "reserved" 1 4 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. #0000 1 The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. #0001 BUF5I Buffer MB5 Interrupt Or "Frames available in Rx FIFO" 5 1 read-write 0 No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 #0 1 MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled. #1 BUF6I Buffer MB6 Interrupt Or "Rx FIFO Warning" 6 1 read-write 0 No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 #0 1 MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1 #1 BUF7I Buffer MB7 Interrupt Or "Rx FIFO Overflow" 7 1 read-write 0 No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 #0 1 MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1 #1 BUF31TO8I Buffer MBi Interrupt 8 24 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception. #0 1 The corresponding buffer has successfully completed transmission or reception. #1 CTRL2 Control 2 register 0x34 32 read-write 0xB00000 0xFFFFFFFF EACEN Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 16 1 read-write 0 Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. #0 1 Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. #1 RRS Remote Request Storing 17 1 read-write 0 Remote Response Frame is generated. #0 1 Remote Request Frame is stored. #1 MRP Mailboxes Reception Priority 18 1 read-write 0 Matching starts from Rx FIFO and continues on Mailboxes. #0 1 Matching starts from Mailboxes and continues on Rx FIFO. #1 TASD Tx Arbitration Start Delay 19 5 read-write RFFN Number Of Rx FIFO Filters 24 4 read-write BOFFDONEMSK Bus Off Done Interrupt Mask 30 1 read-write 0 Bus Off Done interrupt disabled. #0 1 Bus Off Done interrupt enabled. #1 ESR2 Error and Status 2 register 0x38 32 read-only 0 0xFFFFFFFF IMB Inactive Mailbox 13 1 read-only 0 If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. #0 1 If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. #1 VPS Valid Priority Status 14 1 read-only 0 Contents of IMB and LPTM are invalid. #0 1 Contents of IMB and LPTM are valid. #1 LPTM Lowest Priority Tx Mailbox 16 7 read-only CRCR CRC Register 0x44 32 read-only 0 0xFFFFFFFF TXCRC Transmitted CRC value 0 15 read-only MBCRC CRC Mailbox 16 7 read-only RXFGMASK Rx FIFO Global Mask register 0x48 32 read-write 0 0 FGM Rx FIFO Global Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXFIR Rx FIFO Information Register 0x4C 32 read-only 0 0 IDHIT Identifier Acceptance Filter Hit Indicator 0 9 read-only CBT CAN Bit Timing Register 0x50 32 read-write 0 0xFFFFFFFF EPSEG2 Extended Phase Segment 2 0 5 read-write EPSEG1 Extended Phase Segment 1 5 5 read-write EPROPSEG Extended Propagation Segment 10 6 read-write ERJW Extended Resync Jump Width 16 4 read-write EPRESDIV Extended Prescaler Division Factor 21 10 read-write BTF Bit Timing Format Enable 31 1 read-write 0 Extended bit time definitions disabled. #0 1 Extended bit time definitions enabled. #1 CS0 Message Buffer 0 CS Register 0x80 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID0 Message Buffer 0 ID Register 0x84 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD00 Message Buffer 0 WORD0 Register 0x88 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD10 Message Buffer 0 WORD1 Register 0x8C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS1 Message Buffer 1 CS Register 0x90 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID1 Message Buffer 1 ID Register 0x94 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD01 Message Buffer 1 WORD0 Register 0x98 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD11 Message Buffer 1 WORD1 Register 0x9C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS2 Message Buffer 2 CS Register 0xA0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID2 Message Buffer 2 ID Register 0xA4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD02 Message Buffer 2 WORD0 Register 0xA8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD12 Message Buffer 2 WORD1 Register 0xAC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS3 Message Buffer 3 CS Register 0xB0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID3 Message Buffer 3 ID Register 0xB4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD03 Message Buffer 3 WORD0 Register 0xB8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD13 Message Buffer 3 WORD1 Register 0xBC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS4 Message Buffer 4 CS Register 0xC0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID4 Message Buffer 4 ID Register 0xC4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD04 Message Buffer 4 WORD0 Register 0xC8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD14 Message Buffer 4 WORD1 Register 0xCC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS5 Message Buffer 5 CS Register 0xD0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID5 Message Buffer 5 ID Register 0xD4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD05 Message Buffer 5 WORD0 Register 0xD8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD15 Message Buffer 5 WORD1 Register 0xDC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS6 Message Buffer 6 CS Register 0xE0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID6 Message Buffer 6 ID Register 0xE4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD06 Message Buffer 6 WORD0 Register 0xE8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD16 Message Buffer 6 WORD1 Register 0xEC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS7 Message Buffer 7 CS Register 0xF0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID7 Message Buffer 7 ID Register 0xF4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD07 Message Buffer 7 WORD0 Register 0xF8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD17 Message Buffer 7 WORD1 Register 0xFC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS8 Message Buffer 8 CS Register 0x100 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID8 Message Buffer 8 ID Register 0x104 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD08 Message Buffer 8 WORD0 Register 0x108 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD18 Message Buffer 8 WORD1 Register 0x10C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS9 Message Buffer 9 CS Register 0x110 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID9 Message Buffer 9 ID Register 0x114 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD09 Message Buffer 9 WORD0 Register 0x118 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD19 Message Buffer 9 WORD1 Register 0x11C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS10 Message Buffer 10 CS Register 0x120 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID10 Message Buffer 10 ID Register 0x124 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD010 Message Buffer 10 WORD0 Register 0x128 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD110 Message Buffer 10 WORD1 Register 0x12C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS11 Message Buffer 11 CS Register 0x130 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID11 Message Buffer 11 ID Register 0x134 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD011 Message Buffer 11 WORD0 Register 0x138 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD111 Message Buffer 11 WORD1 Register 0x13C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS12 Message Buffer 12 CS Register 0x140 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID12 Message Buffer 12 ID Register 0x144 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD012 Message Buffer 12 WORD0 Register 0x148 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD112 Message Buffer 12 WORD1 Register 0x14C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS13 Message Buffer 13 CS Register 0x150 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID13 Message Buffer 13 ID Register 0x154 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD013 Message Buffer 13 WORD0 Register 0x158 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD113 Message Buffer 13 WORD1 Register 0x15C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS14 Message Buffer 14 CS Register 0x160 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID14 Message Buffer 14 ID Register 0x164 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD014 Message Buffer 14 WORD0 Register 0x168 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD114 Message Buffer 14 WORD1 Register 0x16C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS15 Message Buffer 15 CS Register 0x170 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ESI Reserved 29 1 read-write BRS Reserved 30 1 read-write EDL Reserved 31 1 read-write ID15 Message Buffer 15 ID Register 0x174 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD015 Message Buffer 15 WORD0 Register 0x178 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD115 Message Buffer 15 WORD1 Register 0x17C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write 16 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 RXIMR%s Rx Individual Mask Registers 0x880 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 SPI0 Serial Peripheral Interface SPI0_ 0x4002C000 0 0x8C registers SPI0 26 MCR Module Configuration Register 0 32 read-write 0x4001 0xFFFFFFFF HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 SMPL_PT Sample Point 8 2 read-write 00 0 protocol clock cycles between SCK edge and SIN sample #00 01 1 protocol clock cycle between SCK edge and SIN sample #01 10 2 protocol clock cycles between SCK edge and SIN sample #10 CLR_RXF CLR_RXF 10 1 write-only 0 Do not clear the RX FIFO counter. #0 1 Clear the RX FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the TX FIFO counter. #0 1 Clear the TX FIFO counter. #1 DIS_RXF Disable Receive FIFO 12 1 read-write 0 RX FIFO is enabled. #0 1 RX FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 TX FIFO is enabled. #0 1 TX FIFO is disabled. #1 MDIS Module Disable 14 1 read-write 0 Enables the module clocks. #0 1 Allows external logic to disable the module clocks. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on the module. #0 1 Doze mode disables the module. #1 PCSIS Peripheral Chip Select x Inactive State 16 6 read-write 0 The inactive state of PCSx is low. #0 1 The inactive state of PCSx is high. #1 ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 PCSSE Peripheral Chip Select Strobe Enable 25 1 read-write 0 PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. #0 1 PCS5/ PCSS is used as an active-low PCS Strobe signal. #1 MTFE Modified Transfer Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in Debug mode. #0 1 Halt serial transfers in Debug mode. #1 DCONF SPI Configuration. 28 2 read-only 00 SPI #00 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 Enables Slave mode #0 1 Enables Master mode #1 TCR Transfer Count Register 0x8 32 read-write 0 0xFFFFFFFF SPI_TCNT SPI Transfer Counter 16 16 read-write 2 0x4 0,1 CTAR%s Clock and Transfer Attributes Register (In Master Mode) SPI0 0xC 32 read-write 0x78000000 0xFFFFFFFF BR Baud Rate Scaler 0 4 read-write DT Delay After Transfer Scaler 4 4 read-write ASC After SCK Delay Scaler 8 4 read-write CSSCK PCS to SCK Delay Scaler 12 4 read-write PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 CTAR_SLAVE Clock and Transfer Attributes Register (In Slave Mode) SPI0 0xC 32 read-write 0x78000000 0xFFFFFFFF CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write SR Status Register 0x2C 32 read-write 0x2000000 0xFFFFFFFF POPNXTPTR Pop Next Pointer 0 4 read-only RXCTR RX FIFO Counter 4 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXCTR TX FIFO Counter 12 4 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 RX FIFO is empty. #0 1 RX FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 TX FIFO is full. #0 1 TX FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No TX FIFO underflow. #0 1 TX FIFO underflow has occurred. #1 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 TXRXS TX and RX Status 30 1 read-write 0 Transmit and receive operations are disabled (The module is in Stopped state). #0 1 Transmit and receive operations are enabled (The module is in Running state). #1 TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 RSER DMA/Interrupt Request Select and Enable Register 0x30 32 read-write 0 0xFFFFFFFF RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled. #0 1 RFDF interrupt or DMA requests are enabled. #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 EOQF_RE Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 PUSHR PUSH TX FIFO Register In Master Mode SPI0 0x34 32 read-write 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-write PCS Select which PCS signals are to be asserted for the transfer 16 6 read-write 0 Negate the PCS[x] signal. #0 1 Assert the PCS[x] signal. #1 CTCNT Clear Transfer Counter 26 1 read-write 0 Do not clear the TCR[TCNT] field. #0 1 Clear the TCR[TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 CTAS Clock and Transfer Attributes Select 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 PUSHR_SLAVE PUSH TX FIFO Register In Slave Mode SPI0 0x34 32 read-write 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-write POPR POP RX FIFO Register 0x38 32 read-only 0 0xFFFFFFFF RXDATA Received Data 0 32 read-only 4 0x4 0,1,2,3 TXFR%s Transmit FIFO Registers 0x3C 32 read-only 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-only TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only 4 0x4 0,1,2,3 RXFR%s Receive FIFO Registers 0x7C 32 read-only 0 0xFFFFFFFF RXDATA Receive Data 0 32 read-only PDB0 Programmable Delay Block PDB PDB0_ 0x40036000 0 0x1A4 registers PDB0 52 SC Status and Control register 0 32 read-write 0 0xFFFFFFFF LDOK Load OK 0 1 read-write CONT Continuous Mode Enable 1 1 read-write 0 PDB operation in One-Shot mode #0 1 PDB operation in Continuous mode #1 MULT Multiplication Factor Select for Prescaler 2 2 read-write 00 Multiplication factor is 1. #00 01 Multiplication factor is 10. #01 10 Multiplication factor is 20. #10 11 Multiplication factor is 40. #11 PDBIE PDB Interrupt Enable 5 1 read-write 0 PDB interrupt disabled. #0 1 PDB interrupt enabled. #1 PDBIF PDB Interrupt Flag 6 1 read-write PDBEN PDB Enable 7 1 read-write 0 PDB disabled. Counter is off. #0 1 PDB enabled. #1 TRGSEL Trigger Input Source Select 8 4 read-write 0000 Trigger-In 0 is selected. #0000 0001 Trigger-In 1 is selected. #0001 0010 Trigger-In 2 is selected. #0010 0011 Trigger-In 3 is selected. #0011 0100 Trigger-In 4 is selected. #0100 0101 Trigger-In 5 is selected. #0101 0110 Trigger-In 6 is selected. #0110 0111 Trigger-In 7 is selected. #0111 1000 Trigger-In 8 is selected. #1000 1001 Trigger-In 9 is selected. #1001 1010 Trigger-In 10 is selected. #1010 1011 Trigger-In 11 is selected. #1011 1100 Trigger-In 12 is selected. #1100 1101 Trigger-In 13 is selected. #1101 1110 Trigger-In 14 is selected. #1110 1111 Software trigger is selected. #1111 PRESCALER Prescaler Divider Select 12 3 read-write 000 Counting uses the peripheral clock divided by multiplication factor selected by MULT. #000 001 Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT. #001 010 Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT. #010 011 Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT. #011 100 Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT. #100 101 Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT. #101 110 Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT. #110 111 Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT. #111 DMAEN DMA Enable 15 1 read-write 0 DMA disabled. #0 1 DMA enabled. #1 SWTRIG Software Trigger 16 1 write-only PDBEIE PDB Sequence Error Interrupt Enable 17 1 read-write 0 PDB sequence error interrupt disabled. #0 1 PDB sequence error interrupt enabled. #1 LDMOD Load Mode Select 18 2 read-write 00 The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK. #00 01 The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK. #01 10 The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK. #10 11 The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK. #11 MOD Modulus register 0x4 32 read-write 0xFFFF 0xFFFFFFFF MOD PDB Modulus 0 16 read-write CNT Counter register 0x8 32 read-only 0 0xFFFFFFFF CNT PDB Counter 0 16 read-only IDLY Interrupt Delay register 0xC 32 read-write 0xFFFF 0xFFFFFFFF IDLY PDB Interrupt Delay 0 16 read-write CHC1 Channel n Control register 1 0x10 32 read-write 0 0xFFFFFFFF EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. #1 BB PDB Channel Pre-Trigger Back-to-Back Operation Enable 16 8 read-write 0 PDB channel's corresponding pre-trigger back-to-back operation disabled. #0 1 PDB channel's corresponding pre-trigger back-to-back operation enabled. #1 CHS Channel n Status register 0x14 32 read-write 0 0xFFFFFFFF ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. #1 CF PDB Channel Flags 16 8 read-write CHDLY0 Channel n Delay 0 register 0x18 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write CHDLY1 Channel n Delay 1 register 0x1C 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write CHDLY2 Channel n Delay 2 register 0x20 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write CHDLY3 Channel n Delay 3 register 0x24 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write DACINTC DAC Interval Trigger n Control register 0x150 32 read-write 0 0xFFFFFFFF TOE DAC Interval Trigger Enable 0 1 read-write 0 DAC interval trigger disabled. #0 1 DAC interval trigger enabled. #1 EXT DAC External Trigger Input Enable 1 1 read-write 0 DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger. #1 DACINT DAC Interval n register 0x154 32 read-write 0 0xFFFFFFFF INT DAC Interval 0 16 read-write POEN Pulse-Out n Enable register 0x190 32 read-write 0 0xFFFFFFFF POEN PDB Pulse-Out Enable 0 8 read-write 0 PDB Pulse-Out disabled #0 1 PDB Pulse-Out enabled #1 4 0x4 0,1,2,3 PO%sDLY Pulse-Out n Delay register 0x194 32 read-write 0 0xFFFFFFFF DLY2 PDB Pulse-Out Delay 2 0 16 read-write DLY1 PDB Pulse-Out Delay 1 16 16 read-write PDB1 Programmable Delay Block PDB PDB1_ 0x40031000 0 0x1A4 registers PDB1 55 SC Status and Control register 0 32 read-write 0 0xFFFFFFFF LDOK Load OK 0 1 read-write CONT Continuous Mode Enable 1 1 read-write 0 PDB operation in One-Shot mode #0 1 PDB operation in Continuous mode #1 MULT Multiplication Factor Select for Prescaler 2 2 read-write 00 Multiplication factor is 1. #00 01 Multiplication factor is 10. #01 10 Multiplication factor is 20. #10 11 Multiplication factor is 40. #11 PDBIE PDB Interrupt Enable 5 1 read-write 0 PDB interrupt disabled. #0 1 PDB interrupt enabled. #1 PDBIF PDB Interrupt Flag 6 1 read-write PDBEN PDB Enable 7 1 read-write 0 PDB disabled. Counter is off. #0 1 PDB enabled. #1 TRGSEL Trigger Input Source Select 8 4 read-write 0000 Trigger-In 0 is selected. #0000 0001 Trigger-In 1 is selected. #0001 0010 Trigger-In 2 is selected. #0010 0011 Trigger-In 3 is selected. #0011 0100 Trigger-In 4 is selected. #0100 0101 Trigger-In 5 is selected. #0101 0110 Trigger-In 6 is selected. #0110 0111 Trigger-In 7 is selected. #0111 1000 Trigger-In 8 is selected. #1000 1001 Trigger-In 9 is selected. #1001 1010 Trigger-In 10 is selected. #1010 1011 Trigger-In 11 is selected. #1011 1100 Trigger-In 12 is selected. #1100 1101 Trigger-In 13 is selected. #1101 1110 Trigger-In 14 is selected. #1110 1111 Software trigger is selected. #1111 PRESCALER Prescaler Divider Select 12 3 read-write 000 Counting uses the peripheral clock divided by multiplication factor selected by MULT. #000 001 Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT. #001 010 Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT. #010 011 Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT. #011 100 Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT. #100 101 Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT. #101 110 Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT. #110 111 Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT. #111 DMAEN DMA Enable 15 1 read-write 0 DMA disabled. #0 1 DMA enabled. #1 SWTRIG Software Trigger 16 1 write-only PDBEIE PDB Sequence Error Interrupt Enable 17 1 read-write 0 PDB sequence error interrupt disabled. #0 1 PDB sequence error interrupt enabled. #1 LDMOD Load Mode Select 18 2 read-write 00 The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK. #00 01 The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK. #01 10 The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK. #10 11 The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK. #11 MOD Modulus register 0x4 32 read-write 0xFFFF 0xFFFFFFFF MOD PDB Modulus 0 16 read-write CNT Counter register 0x8 32 read-only 0 0xFFFFFFFF CNT PDB Counter 0 16 read-only IDLY Interrupt Delay register 0xC 32 read-write 0xFFFF 0xFFFFFFFF IDLY PDB Interrupt Delay 0 16 read-write CHC1 Channel n Control register 1 0x10 32 read-write 0 0xFFFFFFFF EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. #1 BB PDB Channel Pre-Trigger Back-to-Back Operation Enable 16 8 read-write 0 PDB channel's corresponding pre-trigger back-to-back operation disabled. #0 1 PDB channel's corresponding pre-trigger back-to-back operation enabled. #1 CHS Channel n Status register 0x14 32 read-write 0 0xFFFFFFFF ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. #1 CF PDB Channel Flags 16 8 read-write CHDLY0 Channel n Delay 0 register 0x18 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write CHDLY1 Channel n Delay 1 register 0x1C 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write CHDLY2 Channel n Delay 2 register 0x20 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write CHDLY3 Channel n Delay 3 register 0x24 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write DACINTC DAC Interval Trigger n Control register 0x150 32 read-write 0 0xFFFFFFFF TOE DAC Interval Trigger Enable 0 1 read-write 0 DAC interval trigger disabled. #0 1 DAC interval trigger enabled. #1 EXT DAC External Trigger Input Enable 1 1 read-write 0 DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger. #1 DACINT DAC Interval n register 0x154 32 read-write 0 0xFFFFFFFF INT DAC Interval 0 16 read-write POEN Pulse-Out n Enable register 0x190 32 read-write 0 0xFFFFFFFF POEN PDB Pulse-Out Enable 0 8 read-write 0 PDB Pulse-Out disabled #0 1 PDB Pulse-Out enabled #1 4 0x4 0,1,2,3 PO%sDLY Pulse-Out n Delay register 0x194 32 read-write 0 0xFFFFFFFF DLY2 PDB Pulse-Out Delay 2 0 16 read-write DLY1 PDB Pulse-Out Delay 1 16 16 read-write CRC Cyclic Redundancy Check CRC_ 0x40032000 0 0xC registers DATA CRC Data register CRC 0 32 read-write 0xFFFFFFFF 0xFFFFFFFF LL CRC Low Lower Byte 0 8 read-write LU CRC Low Upper Byte 8 8 read-write HL CRC High Lower Byte 16 8 read-write HU CRC High Upper Byte 24 8 read-write DATAL CRC_DATAL register. CRC 0 16 read-write 0xFFFF 0xFFFF DATAL DATAL stores the lower 16 bits of the 16/32 bit CRC 0 16 read-write DATALL CRC_DATALL register. CRC 0 8 read-write 0xFF 0xFF DATALL CRCLL stores the first 8 bits of the 32 bit DATA 0 8 read-write DATALU CRC_DATALU register. 0x1 8 read-write 0xFF 0xFF DATALU DATALL stores the second 8 bits of the 32 bit CRC 0 8 read-write DATAH CRC_DATAH register. CRC 0x2 16 read-write 0xFFFF 0xFFFF DATAH DATAH stores the high 16 bits of the 16/32 bit CRC 0 16 read-write DATAHL CRC_DATAHL register. CRC 0x2 8 read-write 0xFF 0xFF DATAHL DATAHL stores the third 8 bits of the 32 bit CRC 0 8 read-write DATAHU CRC_DATAHU register. 0x3 8 read-write 0xFF 0xFF DATAHU DATAHU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write GPOLY CRC Polynomial register CRC 0x4 32 read-write 0x1021 0xFFFFFFFF LOW Low Polynominal Half-word 0 16 read-write HIGH High Polynominal Half-word 16 16 read-write GPOLYL CRC_GPOLYL register. CRC 0x4 16 read-write 0xFFFF 0xFFFF GPOLYL POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value 0 16 read-write GPOLYLL CRC_GPOLYLL register. CRC 0x4 8 read-write 0xFF 0xFF GPOLYLL POLYLL stores the first 8 bits of the 32 bit CRC 0 8 read-write GPOLYLU CRC_GPOLYLU register. 0x5 8 read-write 0xFF 0xFF GPOLYLU POLYLL stores the second 8 bits of the 32 bit CRC 0 8 read-write GPOLYH CRC_GPOLYH register. CRC 0x6 16 read-write 0xFFFF 0xFFFF GPOLYH POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value 0 16 read-write GPOLYHL CRC_GPOLYHL register. CRC 0x6 8 read-write 0xFF 0xFF GPOLYHL POLYHL stores the third 8 bits of the 32 bit CRC 0 8 read-write GPOLYHU CRC_GPOLYHU register. 0x7 8 read-write 0xFF 0xFF GPOLYHU POLYHU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write CTRL CRC Control register 0x8 32 read-write 0 0xFFFFFFFF TCRC Width of CRC protocol. 24 1 read-write 0 16-bit CRC protocol. #0 1 32-bit CRC protocol. #1 WAS Write CRC Data Register As Seed 25 1 read-write 0 Writes to the CRC data register are data values. #0 1 Writes to the CRC data register are seed values. #1 FXOR Complement Read Of CRC Data Register 26 1 read-write 0 No XOR on reading. #0 1 Invert or complement the read value of the CRC Data register. #1 TOTR Type Of Transpose For Read 28 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 TOT Type Of Transpose For Writes 30 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 CTRLHU CRC_CTRLHU register. 0xB 8 read-write 0 0xFF TCRC no description available 0 1 read-write 0 16-bit CRC protocol. #0 1 32-bit CRC protocol. #1 WAS no description available 1 1 read-write 0 Writes to CRC data register are data values. #0 1 Writes to CRC data reguster are seed values. #1 FXOR no description available 2 1 read-write 0 No XOR on reading. #0 1 Invert or complement the read value of CRC data register. #1 TOTR no description available 4 2 read-write 00 No Transposition. #00 01 Bits in bytes are transposed, bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 TOT no description available 6 2 read-write 00 No Transposition. #00 01 Bits in bytes are transposed, bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 PWMA Pulse Width Modulator with nano edge placement PWMA_ 0x40033000 0 0x196 registers PWMA_CMP0 81 PWMA_RELOAD0 82 PWMA_CMP1 83 PWMA_RELOAD1 84 PWMA_CMP2 85 PWMA_RELOAD2 86 PWMA_CMP3 87 PWMA_RELOAD3 88 PWMA_CAP 89 PWMA_RERR 90 PWMA_FAULT 91 4 0x60 0,1,2,3 SM%sCNT Counter Register 0 16 read-only 0 0xFFFF CNT Counter Register Bits 0 16 read-only 4 0x60 0,1,2,3 SM%sINIT Initial Count Register 0x2 16 read-write 0 0xFFFF INIT Initial Count Register Bits 0 16 read-write 4 0x60 0,1,2,3 SM%sCTRL2 Control 2 Register 0x4 16 read-write 0 0xFFFF CLK_SEL Clock Source Select 0 2 read-write 00 The IPBus clock is used as the clock for the local prescaler and counter. #00 01 EXT_CLK is used as the clock for the local prescaler and counter. #01 10 Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. #10 RELOAD_SEL Reload Source Select 2 1 read-write 0 The local RELOAD signal is used to reload registers. #0 1 The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. #1 FORCE_SEL This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 3 3 read-write 000 The local force signal, CTRL2[FORCE], from this submodule is used to force updates. #000 001 The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. #001 010 The local reload signal from this submodule is used to force updates without regard to the state of LDOK. #010 011 The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. #011 100 The local sync signal from this submodule is used to force updates. #100 101 The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. #101 110 The external force signal, EXT_FORCE, from outside the PWM module causes updates. #110 111 The external sync signal, EXT_SYNC, from outside the PWM module causes updates. #111 FORCE Force Initialization 6 1 write-only FRCEN Force Initialization Enable 7 1 read-write 0 Initialization from a FORCE_OUT event is disabled. #0 1 Initialization from a FORCE_OUT event is enabled. #1 INIT_SEL Initialization Control Select 8 2 read-write 00 Local sync (PWM_X) causes initialization. #00 01 Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. #01 10 Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. #10 11 EXT_SYNC causes initialization. #11 PWMX_INIT PWM_X Initial Value 10 1 read-write PWM45_INIT PWM45 Initial Value 11 1 read-write PWM23_INIT PWM23 Initial Value 12 1 read-write INDEP Independent or Complementary Pair Operation 13 1 read-write 0 PWM_A and PWM_B form a complementary PWM pair. #0 1 PWM_A and PWM_B outputs are independent PWMs. #1 WAITEN WAIT Enable 14 1 read-write DBGEN Debug Enable 15 1 read-write 4 0x60 0,1,2,3 SM%sCTRL Control Register 0x6 16 read-write 0x400 0xFFFF DBLEN Double Switching Enable 0 1 read-write 0 Double switching disabled. #0 1 Double switching enabled. #1 DBLX PWMX Double Switching Enable 1 1 read-write 0 PWMX double pulse disabled. #0 1 PWMX double pulse enabled. #1 LDMOD Load Mode Select 2 1 read-write 0 Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. #0 1 Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. #1 SPLIT Split the DBLPWM signal to PWMA and PWMB 3 1 read-write 0 DBLPWM is not split. PWMA and PWMB each have double pulses. #0 1 DBLPWM is split to PWMA and PWMB. #1 PRSC Prescaler 4 3 read-write 000 PWM clock frequency = fclk #000 001 PWM clock frequency = fclk/2 #001 010 PWM clock frequency = fclk/4 #010 011 PWM clock frequency = fclk/8 #011 100 PWM clock frequency = fclk/16 #100 101 PWM clock frequency = fclk/32 #101 110 PWM clock frequency = fclk/64 #110 111 PWM clock frequency = fclk/128 #111 COMPMODE Compare Mode 7 1 read-write 0 The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. #0 1 The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. #1 DT Deadtime 8 2 read-only FULL Full Cycle Reload 10 1 read-write 0 Full-cycle reloads disabled. #0 1 Full-cycle reloads enabled. #1 HALF Half Cycle Reload 11 1 read-write 0 Half-cycle reloads disabled. #0 1 Half-cycle reloads enabled. #1 LDFQ These buffered read/write bits select the PWM load frequency 12 4 read-write 0000 Every PWM opportunity #0000 0001 Every 2 PWM opportunities #0001 0010 Every 3 PWM opportunities #0010 0011 Every 4 PWM opportunities #0011 0100 Every 5 PWM opportunities #0100 0101 Every 6 PWM opportunities #0101 0110 Every 7 PWM opportunities #0110 0111 Every 8 PWM opportunities #0111 1000 Every 9 PWM opportunities #1000 1001 Every 10 PWM opportunities #1001 1010 Every 11 PWM opportunities #1010 1011 Every 12 PWM opportunities #1011 1100 Every 13 PWM opportunities #1100 1101 Every 14 PWM opportunities #1101 1110 Every 15 PWM opportunities #1110 1111 Every 16 PWM opportunities #1111 4 0x60 0,1,2,3 SM%sVAL0 Value Register 0 0xA 16 read-write 0 0xFFFF VAL0 Value Register 0 0 16 read-write 4 0x60 0,1,2,3 SM%sFRACVAL1 Fractional Value Register 1 0xC 16 read-write 0 0xFFFF FRACVAL1 Fractional Value 1 Register 11 5 read-write 4 0x60 0,1,2,3 SM%sVAL1 Value Register 1 0xE 16 read-write 0 0xFFFF VAL1 Value Register 1 0 16 read-write 4 0x60 0,1,2,3 SM%sFRACVAL2 Fractional Value Register 2 0x10 16 read-write 0 0xFFFF FRACVAL2 Fractional Value 2 11 5 read-write 4 0x60 0,1,2,3 SM%sVAL2 Value Register 2 0x12 16 read-write 0 0xFFFF VAL2 Value Register 2 0 16 read-write 4 0x60 0,1,2,3 SM%sFRACVAL3 Fractional Value Register 3 0x14 16 read-write 0 0xFFFF FRACVAL3 Fractional Value 3 11 5 read-write 4 0x60 0,1,2,3 SM%sVAL3 Value Register 3 0x16 16 read-write 0 0xFFFF VAL3 Value Register 3 0 16 read-write 4 0x60 0,1,2,3 SM%sFRACVAL4 Fractional Value Register 4 0x18 16 read-write 0 0xFFFF FRACVAL4 Fractional Value 4 11 5 read-write 4 0x60 0,1,2,3 SM%sVAL4 Value Register 4 0x1A 16 read-write 0 0xFFFF VAL4 Value Register 4 0 16 read-write 4 0x60 0,1,2,3 SM%sFRACVAL5 Fractional Value Register 5 0x1C 16 read-write 0 0xFFFF FRACVAL5 Fractional Value 5 11 5 read-write 4 0x60 0,1,2,3 SM%sVAL5 Value Register 5 0x1E 16 read-write 0 0xFFFF VAL5 Value Register 5 0 16 read-write 4 0x60 0,1,2,3 SM%sFRCTRL Fractional Control Register 0x20 16 read-write 0 0xFFFF FRAC1_EN Fractional Cycle PWM Period Enable 1 1 read-write 0 Disable fractional cycle length for the PWM period. #0 1 Enable fractional cycle length for the PWM period. #1 FRAC23_EN Fractional Cycle Placement Enable for PWM_A 2 1 read-write 0 Disable fractional cycle placement for PWM_A. #0 1 Enable fractional cycle placement for PWM_A. #1 FRAC45_EN Fractional Cycle Placement Enable for PWM_B 4 1 read-write 0 Disable fractional cycle placement for PWM_B. #0 1 Enable fractional cycle placement for PWM_B. #1 FRAC_PU Fractional Delay Circuit Power Up 8 1 read-write 0 Turn off fractional delay logic. #0 1 Power up fractional delay logic. #1 TEST Test Status Bit 15 1 read-only 4 0x60 0,1,2,3 SM%sOCTRL Output Control Register 0x22 16 read-write 0 0xFFFF PWMXFS PWM_X Fault State 0 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMBFS PWM_B Fault State 2 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMAFS PWM_A Fault State 4 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 POLX PWM_X Output Polarity 8 1 read-write 0 PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. #0 1 PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. #1 POLB PWM_B Output Polarity 9 1 read-write 0 PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. #0 1 PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. #1 POLA PWM_A Output Polarity 10 1 read-write 0 PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. #0 1 PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. #1 PWMX_IN PWM_X Input 13 1 read-only PWMB_IN PWM_B Input 14 1 read-only PWMA_IN PWM_A Input 15 1 read-only 4 0x60 0,1,2,3 SM%sSTS Status Register 0x24 16 read-write 0 0xFFFF CMPF Compare Flags 0 6 read-write 0 No compare event has occurred for a particular VALx value. #0 1 A compare event has occurred for a particular VALx value. #1 CFX0 Capture Flag X0 6 1 read-write CFX1 Capture Flag X1 7 1 read-write CFB0 Capture Flag B0 8 1 read-write CFB1 Capture Flag B1 9 1 read-write CFA0 Capture Flag A0 10 1 read-write CFA1 Capture Flag A1 11 1 read-write RF Reload Flag 12 1 read-write 0 No new reload cycle since last STS[RF] clearing #0 1 New reload cycle since last STS[RF] clearing #1 REF Reload Error Flag 13 1 read-write 0 No reload error occurred. #0 1 Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. #1 RUF Registers Updated Flag 14 1 read-only 0 No register update has occurred since last reload. #0 1 At least one of the double buffered registers has been updated since the last reload. #1 4 0x60 0,1,2,3 SM%sINTEN Interrupt Enable Register 0x26 16 read-write 0 0xFFFF CMPIE Compare Interrupt Enables 0 6 read-write 0 The corresponding STS[CMPF] bit will not cause an interrupt request. #0 1 The corresponding STS[CMPF] bit will cause an interrupt request. #1 CX0IE Capture X 0 Interrupt Enable 6 1 read-write 0 Interrupt request disabled for STS[CFX0]. #0 1 Interrupt request enabled for STS[CFX0]. #1 CX1IE Capture X 1 Interrupt Enable 7 1 read-write 0 Interrupt request disabled for STS[CFX1]. #0 1 Interrupt request enabled for STS[CFX1]. #1 CB0IE Capture B 0 Interrupt Enable 8 1 read-write 0 Interrupt request disabled for STS[CFB0]. #0 1 Interrupt request enabled for STS[CFB0]. #1 CB1IE Capture B 1 Interrupt Enable 9 1 read-write 0 Interrupt request disabled for STS[CFB1]. #0 1 Interrupt request enabled for STS[CFB1]. #1 CA0IE Capture A 0 Interrupt Enable 10 1 read-write 0 Interrupt request disabled for STS[CFA0]. #0 1 Interrupt request enabled for STS[CFA0]. #1 CA1IE Capture A 1 Interrupt Enable 11 1 read-write 0 Interrupt request disabled for STS[CFA1]. #0 1 Interrupt request enabled for STS[CFA1]. #1 RIE Reload Interrupt Enable 12 1 read-write 0 STS[RF] CPU interrupt requests disabled #0 1 STS[RF] CPU interrupt requests enabled #1 REIE Reload Error Interrupt Enable 13 1 read-write 0 STS[REF] CPU interrupt requests disabled #0 1 STS[REF] CPU interrupt requests enabled #1 4 0x60 0,1,2,3 SM%sDMAEN DMA Enable Register 0x28 16 read-write 0 0xFFFF CX0DE Capture X0 FIFO DMA Enable 0 1 read-write CX1DE Capture X1 FIFO DMA Enable 1 1 read-write CB0DE Capture B0 FIFO DMA Enable 2 1 read-write CB1DE Capture B1 FIFO DMA Enable 3 1 read-write CA0DE Capture A0 FIFO DMA Enable 4 1 read-write CA1DE Capture A1 FIFO DMA Enable 5 1 read-write CAPTDE Capture DMA Enable Source Select 6 2 read-write 00 Read DMA requests disabled. #00 01 Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. #01 10 A local sync (VAL1 matches counter) sets the read DMA request. #10 11 A local reload (STS[RF] being set) sets the read DMA request. #11 FAND FIFO Watermark AND Control 8 1 read-write 0 Selected FIFO watermarks are OR'ed together. #0 1 Selected FIFO watermarks are AND'ed together. #1 VALDE Value Registers DMA Enable 9 1 read-write 0 DMA write requests disabled #0 1 DMA write requests for the VALx and FRACVALx registers enabled #1 4 0x60 0,1,2,3 SM%sTCTRL Output Trigger Control Register 0x2A 16 read-write 0 0xFFFF OUT_TRIG_EN Output Trigger Enables 0 6 read-write 0 PWM_OUT_TRIGx will not set when the counter value matches the VALx value. #0 1 PWM_OUT_TRIGx will set when the counter value matches the VALx value. #1 PWBOT1 Output Trigger 1 Source Select 14 1 write-only 0 Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. #0 1 Route the PWMB output to the PWM_OUT_TRIG1 port. #1 PWAOT0 Output Trigger 0 Source Select 15 1 write-only 0 Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. #0 1 Route the PWMA output to the PWM_OUT_TRIG0 port. #1 4 0x60 0,1,2,3 SM%sDISMAP0 Fault Disable Mapping Register 0 0x2C 16 read-write 0xFFFF 0xFFFF DIS0A PWM_A Fault Disable Mask 0 0 4 read-write DIS0B PWM_B Fault Disable Mask 0 4 4 read-write DIS0X PWM_X Fault Disable Mask 0 8 4 read-write 4 0x60 0,1,2,3 SM%sDISMAP1 Fault Disable Mapping Register 1 0x2E 16 read-write 0xFFFF 0xFFFF DIS1A PWM_A Fault Disable Mask 1 0 4 read-write DIS1B PWM_B Fault Disable Mask 1 4 4 read-write DIS1X PWM_X Fault Disable Mask 1 8 4 read-write 4 0x60 0,1,2,3 SM%sDTCNT0 Deadtime Count Register 0 0x30 16 read-write 0x7FF 0xFFFF DTCNT0 The DTCNT0 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC23_EN] is set) 0 16 read-write 4 0x60 0,1,2,3 SM%sDTCNT1 Deadtime Count Register 1 0x32 16 read-write 0x7FF 0xFFFF DTCNT1 The DTCNT1 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC45_EN] is set) 0 16 read-write 4 0x60 0,1,2,3 SM%sCAPTCTRLA Capture Control A Register 0x34 16 read-write 0 0xFFFF ARMA Arm A 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. #1 ONESHOTA One Shot Mode A 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. #1 EDGA0 Edge A 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGA1 Edge A 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 INP_SELA Input Select A 6 1 read-write 0 Raw PWM_A input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. #1 EDGCNTA_EN Edge Counter A Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 CFAWM Capture A FIFOs Water Mark 8 2 read-write CA0CNT Capture A0 FIFO Word Count 10 3 read-only CA1CNT Capture A1 FIFO Word Count 13 3 read-only 4 0x60 0,1,2,3 SM%sCAPTCOMPA Capture Compare A Register 0x36 16 read-write 0 0xFFFF EDGCMPA Edge Compare A 0 8 read-write EDGCNTA Edge Counter A 8 8 read-only 4 0x60 0,1,2,3 SM%sCAPTCTRLB Capture Control B Register 0x38 16 read-write 0 0xFFFF ARMB Arm B 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. #1 ONESHOTB One Shot Mode B 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. #1 EDGB0 Edge B 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGB1 Edge B 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 INP_SELB Input Select B 6 1 read-write 0 Raw PWM_B input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. #1 EDGCNTB_EN Edge Counter B Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 CFBWM Capture B FIFOs Water Mark 8 2 read-write CB0CNT Capture B0 FIFO Word Count 10 3 read-only CB1CNT Capture B1 FIFO Word Count 13 3 read-only 4 0x60 0,1,2,3 SM%sCAPTCOMPB Capture Compare B Register 0x3A 16 read-write 0 0xFFFF EDGCMPB Edge Compare B 0 8 read-write EDGCNTB Edge Counter B 8 8 read-only 4 0x60 0,1,2,3 SM%sCAPTCTRLX Capture Control X Register 0x3C 16 read-write 0 0xFFFF ARMX Arm X 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. #1 ONESHOTX One Shot Mode Aux 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. #1 EDGX0 Edge X 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGX1 Edge X 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 INP_SELX Input Select X 6 1 read-write 0 Raw PWM_X input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. #1 EDGCNTX_EN Edge Counter X Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 CFXWM Capture X FIFOs Water Mark 8 2 read-write CX0CNT Capture X0 FIFO Word Count 10 3 read-only CX1CNT Capture X1 FIFO Word Count 13 3 read-only 4 0x60 0,1,2,3 SM%sCAPTCOMPX Capture Compare X Register 0x3E 16 read-write 0 0xFFFF EDGCMPX Edge Compare X 0 8 read-write EDGCNTX Edge Counter X 8 8 read-only 4 0x60 0,1,2,3 SM%sCVAL0 Capture Value 0 Register 0x40 16 read-only 0 0xFFFF CAPTVAL0 This read-only register stores the value captured from the submodule counter 0 16 read-only 4 0x60 0,1,2,3 SM%sCVAL0CYC Capture Value 0 Cycle Register 0x42 16 read-only 0 0xFFFF CVAL0CYC This read-only register stores the cycle number corresponding to the value captured in CVAL0 0 4 read-only 4 0x60 0,1,2,3 SM%sCVAL1 Capture Value 1 Register 0x44 16 read-only 0 0xFFFF CAPTVAL1 This read-only register stores the value captured from the submodule counter 0 16 read-only 4 0x60 0,1,2,3 SM%sCVAL1CYC Capture Value 1 Cycle Register 0x46 16 read-only 0 0xFFFF CVAL1CYC This read-only register stores the cycle number corresponding to the value captured in CVAL1 0 4 read-only 4 0x60 0,1,2,3 SM%sCVAL2 Capture Value 2 Register 0x48 16 read-only 0 0xFFFF CAPTVAL2 This read-only register stores the value captured from the submodule counter 0 16 read-only 4 0x60 0,1,2,3 SM%sCVAL2CYC Capture Value 2 Cycle Register 0x4A 16 read-only 0 0xFFFF CVAL2CYC This read-only register stores the cycle number corresponding to the value captured in CVAL2 0 4 read-only 4 0x60 0,1,2,3 SM%sCVAL3 Capture Value 3 Register 0x4C 16 read-only 0 0xFFFF CAPTVAL3 This read-only register stores the value captured from the submodule counter 0 16 read-only 4 0x60 0,1,2,3 SM%sCVAL3CYC Capture Value 3 Cycle Register 0x4E 16 read-only 0 0xFFFF CVAL3CYC This read-only register stores the cycle number corresponding to the value captured in CVAL3 0 4 read-only 4 0x60 0,1,2,3 SM%sCVAL4 Capture Value 4 Register 0x50 16 read-only 0 0xFFFF CAPTVAL4 This read-only register stores the value captured from the submodule counter 0 16 read-only 4 0x60 0,1,2,3 SM%sCVAL4CYC Capture Value 4 Cycle Register 0x52 16 read-only 0 0xFFFF CVAL4CYC This read-only register stores the cycle number corresponding to the value captured in CVAL4 0 4 read-only 4 0x60 0,1,2,3 SM%sCVAL5 Capture Value 5 Register 0x54 16 read-only 0 0xFFFF CAPTVAL5 This read-only register stores the value captured from the submodule counter 0 16 read-only 4 0x60 0,1,2,3 SM%sCVAL5CYC Capture Value 5 Cycle Register 0x56 16 read-only 0 0xFFFF CVAL5CYC This read-only register stores the cycle number corresponding to the value captured in CVAL5 0 4 read-only OUTEN Output Enable Register 0x180 16 read-write 0 0xFFFF PWMX_EN PWM_X Output Enables 0 4 read-write 0 PWM_X output disabled. #0000 1 PWM_X output enabled. #0001 PWMB_EN PWM_B Output Enables 4 4 read-write 0 PWM_B output disabled. #0000 1 PWM_B output enabled. #0001 PWMA_EN PWM_A Output Enables 8 4 read-write 0 PWM_A output disabled. #0000 1 PWM_A output enabled. #0001 MASK Mask Register 0x182 16 read-write 0 0xFFFF MASKX PWM_X Masks 0 4 read-write 0 PWM_X output normal. #0000 1 PWM_X output masked. #0001 MASKB PWM_B Masks 4 4 read-write 0 PWM_B output normal. #0000 1 PWM_B output masked. #0001 MASKA PWM_A Masks 8 4 read-write 0 PWM_A output normal. #0000 1 PWM_A output masked. #0001 UPDATE_MASK Update Mask Bits Immediately 12 4 write-only 0 Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule. #0000 1 Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit. #0001 SWCOUT Software Controlled Output Register 0x184 16 read-write 0 0xFFFF SM0OUT45 Submodule 0 Software Controlled Output 45 0 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. #0 1 A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. #1 SM0OUT23 Submodule 0 Software Controlled Output 23 1 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. #0 1 A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. #1 SM1OUT45 Submodule 1 Software Controlled Output 45 2 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. #0 1 A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. #1 SM1OUT23 Submodule 1 Software Controlled Output 23 3 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. #0 1 A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. #1 SM2OUT45 Submodule 2 Software Controlled Output 45 4 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. #0 1 A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. #1 SM2OUT23 Submodule 2 Software Controlled Output 23 5 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. #0 1 A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. #1 SM3OUT45 Submodule 3 Software Controlled Output 45 6 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. #0 1 A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. #1 SM3OUT23 Submodule 3 Software Controlled Output 23 7 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. #0 1 A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. #1 DTSRCSEL PWM Source Select Register 0x186 16 read-write 0 0xFFFF SM0SEL45 Submodule 0 PWM45 Control Select 0 2 read-write 00 Generated SM0PWM45 signal is used by the deadtime logic. #00 01 Inverted generated SM0PWM45 signal is used by the deadtime logic. #01 10 SWCOUT[SM0OUT45] is used by the deadtime logic. #10 11 PWM0_EXTB signal is used by the deadtime logic. #11 SM0SEL23 Submodule 0 PWM23 Control Select 2 2 read-write 00 Generated SM0PWM23 signal is used by the deadtime logic. #00 01 Inverted generated SM0PWM23 signal is used by the deadtime logic. #01 10 SWCOUT[SM0OUT23] is used by the deadtime logic. #10 11 PWM0_EXTA signal is used by the deadtime logic. #11 SM1SEL45 Submodule 1 PWM45 Control Select 4 2 read-write 00 Generated SM1PWM45 signal is used by the deadtime logic. #00 01 Inverted generated SM1PWM45 signal is used by the deadtime logic. #01 10 SWCOUT[SM1OUT45] is used by the deadtime logic. #10 11 PWM1_EXTB signal is used by the deadtime logic. #11 SM1SEL23 Submodule 1 PWM23 Control Select 6 2 read-write 00 Generated SM1PWM23 signal is used by the deadtime logic. #00 01 Inverted generated SM1PWM23 signal is used by the deadtime logic. #01 10 SWCOUT[SM1OUT23] is used by the deadtime logic. #10 11 PWM1_EXTA signal is used by the deadtime logic. #11 SM2SEL45 Submodule 2 PWM45 Control Select 8 2 read-write 00 Generated SM2PWM45 signal is used by the deadtime logic. #00 01 Inverted generated SM2PWM45 signal is used by the deadtime logic. #01 10 SWCOUT[SM2OUT45] is used by the deadtime logic. #10 11 PWM2_EXTB signal is used by the deadtime logic. #11 SM2SEL23 Submodule 2 PWM23 Control Select 10 2 read-write 00 Generated SM2PWM23 signal is used by the deadtime logic. #00 01 Inverted generated SM2PWM23 signal is used by the deadtime logic. #01 10 SWCOUT[SM2OUT23] is used by the deadtime logic. #10 11 PWM2_EXTA signal is used by the deadtime logic. #11 SM3SEL45 Submodule 3 PWM45 Control Select 12 2 read-write 00 Generated SM3PWM45 signal is used by the deadtime logic. #00 01 Inverted generated SM3PWM45 signal is used by the deadtime logic. #01 10 SWCOUT[SM3OUT45] is used by the deadtime logic. #10 11 PWM3_EXTB signal is used by the deadtime logic. #11 SM3SEL23 Submodule 3 PWM23 Control Select 14 2 read-write 00 Generated SM3PWM23 signal is used by the deadtime logic. #00 01 Inverted generated SM3PWM23 signal is used by the deadtime logic. #01 10 SWCOUT[SM3OUT23] is used by the deadtime logic. #10 11 PWM3_EXTA signal is used by the deadtime logic. #11 MCTRL Master Control Register 0x188 16 read-write 0 0xFFFF LDOK Load Okay 0 4 read-write 0 Do not load new values. #0000 1 Load prescaler, modulus, and PWM values of the corresponding submodule. #0001 CLDOK Clear Load Okay 4 4 write-only RUN Run 8 4 read-write 0 PWM generator is disabled in the corresponding submodule. #0000 1 PWM generator is enabled in the corresponding submodule. #0001 IPOL Current Polarity 12 4 read-write 0 PWM23 is used to generate complementary PWM pair in the corresponding submodule. #0000 1 PWM45 is used to generate complementary PWM pair in the corresponding submodule. #0001 MCTRL2 Master Control 2 Register 0x18A 16 read-write 0 0xFFFF MONPLL Monitor PLL State 0 2 read-write 00 Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. #00 01 Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. #01 10 Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. These bits are write protected until the next reset. #10 11 Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. These bits are write protected until the next reset. #11 FCTRL Fault Control Register 0x18C 16 read-write 0 0xFFFF FIE Fault Interrupt Enables 0 4 read-write 0 FAULTx CPU interrupt requests disabled. #0000 1 FAULTx CPU interrupt requests enabled. #0001 FSAFE Fault Safety Mode 4 4 read-write 0 Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFPINx]. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn). #0000 1 Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL]. #0001 FAUTO Automatic Fault Clearing 8 4 read-write 0 Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending the state of FSTS[FFULL]. This is further controlled by FCTRL[FSAFE]. #0000 1 Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFLAGx]. #0001 FLVL Fault Level 12 4 read-write 0 A logic 0 on the fault input indicates a fault condition. #0000 1 A logic 1 on the fault input indicates a fault condition. #0001 FSTS Fault Status Register 0x18E 16 read-write 0 0xFFFF FFLAG Fault Flags 0 4 read-write 0 No fault on the FAULTx pin. #0000 1 Fault on the FAULTx pin. #0001 FFULL Full Cycle 4 4 read-write 0 PWM outputs are not re-enabled at the start of a full cycle #0000 1 PWM outputs are re-enabled at the start of a full cycle #0001 FFPIN Filtered Fault Pins 8 4 read-only FHALF Half Cycle Fault Recovery 12 4 read-write 0 PWM outputs are not re-enabled at the start of a half cycle. #0000 1 PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). #0001 FFILT Fault Filter Register 0x190 16 read-write 0 0xFFFF FILT_PER Fault Filter Period 0 8 read-write FILT_CNT Fault Filter Count 8 3 read-write GSTR Fault Glitch Stretch Enable 15 1 read-write 0 Fault input glitch stretching is disabled. #0 1 Input fault signals will be stretched to at least 2 IPBus clock cycles. #1 FTST Fault Test Register 0x192 16 read-write 0 0xFFFF FTEST Fault Test 0 1 read-write 0 No fault #0 1 Cause a simulated fault #1 FCTRL2 Fault Control 2 Register 0x194 16 read-write 0 0xFFFF NOCOMB No Combinational Path From Fault Input To PWM Output 0 4 read-write 0 There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs. #0000 1 The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs. #0001 PIT Periodic Interrupt Timer PIT_ 0x40037000 0 0x140 registers PIT0 48 PIT1 49 PIT2 50 PIT3 51 MCR PIT Module Control Register 0 32 read-write 0x6 0xFFFFFFFF FRZ Freeze 0 1 read-write 0 Timers continue to run in Debug mode. #0 1 Timers are stopped in Debug mode. #1 MDIS Module Disable - (PIT section) 1 1 read-write 0 Clock for standard PIT timers is enabled. #0 1 Clock for standard PIT timers is disabled. #1 4 0x10 0,1,2,3 LDVAL%s Timer Load Value Register 0x100 32 read-write 0 0xFFFFFFFF TSV Timer Start Value 0 32 read-write 4 0x10 0,1,2,3 CVAL%s Current Timer Value Register 0x104 32 read-only 0 0xFFFFFFFF TVL Current Timer Value 0 32 read-only 4 0x10 0,1,2,3 TCTRL%s Timer Control Register 0x108 32 read-write 0 0xFFFFFFFF TEN Timer Enable 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is enabled. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 CHN Chain Mode 2 1 read-write 0 Timer is not chained. #0 1 Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. #1 4 0x10 0,1,2,3 TFLG%s Timer Flag Register 0x10C 32 read-write 0 0xFFFFFFFF TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 DAC0 12-Bit Digital-to-Analog Converter DAC0_ 0x4003F000 0 0x24 registers DAC0 56 16 0x2 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 DAT%sL DAC Data Low Register 0 8 read-write 0 0xFF DATA0 DATA0 0 8 read-write 16 0x2 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 DAT%sH DAC Data High Register 0x1 8 read-write 0 0xFF DATA1 DATA1 0 4 read-write SR DAC Status Register 0x20 8 read-write 0x2 0xFF DACBFRPBF DAC Buffer Read Pointer Bottom Position Flag 0 1 read-write 0 The DAC buffer read pointer is not equal to C2[DACBFUP]. #0 1 The DAC buffer read pointer is equal to C2[DACBFUP]. #1 DACBFRPTF DAC Buffer Read Pointer Top Position Flag 1 1 read-write 0 The DAC buffer read pointer is not zero. #0 1 The DAC buffer read pointer is zero. #1 DACBFWMF DAC Buffer Watermark Flag 2 1 read-write 0 The DAC buffer read pointer has not reached the watermark level. #0 1 The DAC buffer read pointer has reached the watermark level. #1 C0 DAC Control Register 0x21 8 read-write 0 0xFF DACBBIEN DAC Buffer Read Pointer Bottom Flag Interrupt Enable 0 1 read-write 0 The DAC buffer read pointer bottom flag interrupt is disabled. #0 1 The DAC buffer read pointer bottom flag interrupt is enabled. #1 DACBTIEN DAC Buffer Read Pointer Top Flag Interrupt Enable 1 1 read-write 0 The DAC buffer read pointer top flag interrupt is disabled. #0 1 The DAC buffer read pointer top flag interrupt is enabled. #1 DACBWIEN DAC Buffer Watermark Interrupt Enable 2 1 read-write 0 The DAC buffer watermark interrupt is disabled. #0 1 The DAC buffer watermark interrupt is enabled. #1 LPEN DAC Low Power Control 3 1 read-write 0 High-Power mode #0 1 Low-Power mode #1 DACSWTRG DAC Software Trigger 4 1 write-only 0 The DAC soft trigger is not valid. #0 1 The DAC soft trigger is valid. #1 DACTRGSEL DAC Trigger Select 5 1 read-write 0 The DAC hardware trigger is selected. #0 1 The DAC software trigger is selected. #1 DACRFS DAC Reference Select 6 1 read-write 0 The DAC selects DACREF_1 as the reference voltage. #0 1 The DAC selects DACREF_2 as the reference voltage. #1 DACEN DAC Enable 7 1 read-write 0 The DAC system is disabled. #0 1 The DAC system is enabled. #1 C1 DAC Control Register 1 0x22 8 read-write 0 0xFF DACBFEN DAC Buffer Enable 0 1 read-write 0 Buffer read pointer is disabled. The converted data is always the first word of the buffer. #0 1 Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. #1 DACBFMD DAC Buffer Work Mode Select 1 2 read-write 00 Normal mode #00 01 Swing mode #01 10 One-Time Scan mode #10 11 FIFO mode #11 DACBFWM DAC Buffer Watermark Select 3 2 read-write 00 In normal mode, 1 word . In FIFO mode, 2 or less than 2 data remaining in FIFO will set watermark status bit. #00 01 In normal mode, 2 words . In FIFO mode, Max/4 or less than Max/4 data remaining in FIFO will set watermark status bit. #01 10 In normal mode, 3 words . In FIFO mode, Max/2 or less than Max/2 data remaining in FIFO will set watermark status bit. #10 11 In normal mode, 4 words . In FIFO mode, Max-2 or less than Max-2 data remaining in FIFO will set watermark status bit. #11 DMAEN DMA Enable Select 7 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time. #1 C2 DAC Control Register 2 0x23 8 read-write 0xF 0xFF DACBFUP DAC Buffer Upper Limit 0 4 read-write DACBFRP DAC Buffer Read Pointer 4 4 read-write LPTMR0 Low Power Timer LPTMR0_ 0x40040000 0 0x10 registers LPTMR0 58 CSR Low Power Timer Control Status Register 0 32 read-write 0 0xFFFFFFFF TEN Timer Enable 0 1 read-write 0 LPTMR is disabled and internal logic is reset. #0 1 LPTMR is enabled. #1 TMS Timer Mode Select 1 1 read-write 0 Time Counter mode. #0 1 Pulse Counter mode. #1 TFC Timer Free-Running Counter 2 1 read-write 0 CNR is reset whenever TCF is set. #0 1 CNR is reset on overflow. #1 TPP Timer Pin Polarity 3 1 read-write 0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. #0 1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. #1 TPS Timer Pin Select 4 2 read-write 00 Pulse counter input 0 is selected. #00 01 Pulse counter input 1 is selected. #01 10 Pulse counter input 2 is selected. #10 11 Pulse counter input 3 is selected. #11 TIE Timer Interrupt Enable 6 1 read-write 0 Timer interrupt disabled. #0 1 Timer interrupt enabled. #1 TCF Timer Compare Flag 7 1 read-write 0 The value of CNR is not equal to CMR and increments. #0 1 The value of CNR is equal to CMR and increments. #1 PSR Low Power Timer Prescale Register 0x4 32 read-write 0 0xFFFFFFFF PCS Prescaler Clock Select 0 2 read-write 00 Prescaler/glitch filter clock 0 selected. #00 01 Prescaler/glitch filter clock 1 selected. #01 10 Prescaler/glitch filter clock 2 selected. #10 11 Prescaler/glitch filter clock 3 selected. #11 PBYP Prescaler Bypass 2 1 read-write 0 Prescaler/glitch filter is enabled. #0 1 Prescaler/glitch filter is bypassed. #1 PRESCALE Prescale Value 3 4 read-write 0000 Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. #0000 0001 Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. #0001 0010 Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. #0010 0011 Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. #0011 0100 Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. #0100 0101 Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. #0101 0110 Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. #0110 0111 Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. #0111 1000 Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. #1000 1001 Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. #1001 1010 Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. #1010 1011 Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. #1011 1100 Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. #1100 1101 Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. #1101 1110 Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. #1110 1111 Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. #1111 CMR Low Power Timer Compare Register 0x8 32 read-write 0 0xFFFFFFFF COMPARE Compare Value 0 16 read-write CNR Low Power Timer Counter Register 0xC 32 read-write 0 0xFFFFFFFF COUNTER Counter Value 0 16 read-write SIM System Integration Module SIM_ 0x40047000 0 0x110C registers SOPT1 System Options Register 1 0 32 read-write 0 0xFFFF0FFF RAMSIZE RAM size 12 4 read-only 0011 16 KB #0011 0100 24 KB #0100 0101 32 KB #0101 OSC32KSEL 32K oscillator clock select 18 2 read-write 00 System oscillator (OSC32KCLK) #00 11 LPO 1 kHz #11 SOPT2 System Options Register 2 0x1004 32 read-write 0x1000 0xFFFFFFFF CLKOUTSEL CLKOUT select 5 3 read-write 010 Flash clock #010 011 LPO clock (1 kHz) #011 100 MCGIRCLK #100 101 OSCERCLK_UNDIV #101 110 OSCERCLK #110 TRACECLKSEL Debug trace clock select 12 1 read-write 0 MCGOUTCLK #0 1 Core/system clock #1 SOPT4 System Options Register 4 0x100C 32 read-write 0 0xFFFFFFFF FTM0FLT0 FTM0 Fault 0 Select 0 1 read-write 0 FTM0_FLT0 pin #0 1 CMP0 out #1 FTM0FLT1 FTM0 Fault 1 Select 1 1 read-write 0 FTM0_FLT1 pin #0 1 CMP1 out #1 FTM0FLT2 FTM0 Fault 2 Select 2 1 read-write 0 FTM0_FLT2 pin #0 1 CMP2 out #1 FTM0FLT3 Selects the source of FTM0 fault 3 3 1 read-write 0 FTM0_FLT3 pin #0 1 XBARA output 49 #1 FTM1FLT0 FTM1 Fault 0 Select 4 1 read-write 0 FTM1_FLT0 pin #0 1 CMP0 out #1 FTM3FLT0 FTM3 Fault 0 Select 12 1 read-write 0 FTM3_FLT0 pin #0 1 CMP0 out #1 FTM0TRG0SRC FlexTimer 0 Hardware Trigger 0 Source Select 16 1 read-write 0 CMP0 output drives FTM0 hardware trigger 0 #0 1 FTM1 channel match drives FTM0 hardware trigger 0 #1 FTM0TRG1SRC FlexTimer 0 Hardware Trigger 1 Source Select 17 1 read-write 0 PDB0 output trigger drives FTM0 hardware trigger 1 #0 1 FTM1 channel match drives FTM0 hardware trigger 1 #1 FTM0TRG2SRC FlexTimer 0 Hardware Trigger 2 Source Select 18 1 read-write 0 FTM0_FLT0 pin drives FTM0 hardware trigger 2 #0 1 XBARA output 34 drives FTM0 hardware trigger 2 #1 FTM1TRG0SRC FlexTimer 1 Hardware Trigger 0 Source Select 20 1 read-write 0 CMP0 output drives FTM1 hardware trigger 0 #0 1 FTM0 channel match drives FTM1 hardware trigger 0 #1 FTM1TRG2SRC FlexTimer 1 Hardware Trigger 2 Source Select 22 1 read-write 0 FTM1_FLT0 pin drives FTM1 hardware trigger 2 #0 1 XBARA output 35 drives FTM1 hardware trigger 2 #1 FTM3TRG0SRC FlexTimer 3 Hardware Trigger 0 Source Select 28 1 read-write 0 CMP0 output drives FTM3 hardware trigger 0 #0 1 FTM1 channel match drives FTM3 hardware trigger 0 #1 FTM3TRG1SRC FlexTimer 3 Hardware Trigger 1 Source Select 29 1 read-write 0 PDB1 output trigger drives FTM3 hardware trigger 1 #0 1 FTM1 channel match drives FTM3 hardware trigger 1 #1 FTM3TRG2SRC FlexTimer 3 Hardware Trigger 2 Source Select 30 1 read-write 0 FTM3_FLT0 pin drives FTM3 hardware trigger 2 #0 1 XBARA output 37 drives FTM3 hardware trigger 2 #1 SOPT5 System Options Register 5 0x1010 32 read-write 0 0xFFFFFFFF UART0TXSRC UART 0 transmit data source select 0 1 read-write 0 UART0_TX pin #0 1 UART0_TX pin modulated with FTM1 channel 0 output #1 UART0RXSRC UART 0 receive data source select 2 2 read-write 00 UART0_RX pin #00 01 CMP0 #01 10 CMP1 #10 UART1TXSRC UART 1 transmit data source select 4 1 read-write 0 UART1_TX pin #0 1 UART1_TX pin modulated with FTM1 channel 0 output #1 UART1RXSRC UART 1 receive data source select 6 2 read-write 00 UART1_RX pin #00 01 CMP0 #01 10 CMP1 #10 SOPT7 System Options Register 7 0x1018 32 read-write 0 0xFFFFFFFF ADCATRGSEL ADCA trigger select 0 4 read-write 0000 PDB external trigger pin input (PDB0_EXTRG) #0000 0001 High speed comparator 0 output #0001 0010 High speed comparator 1 output #0010 0011 High speed comparator 2 output #0011 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 0110 PIT trigger 2 #0110 0111 PIT trigger 3 #0111 1000 FTM0 trigger #1000 1001 FTM1 trigger #1001 1011 FTM3 trigger #1011 1100 XBARA output 38 #1100 1110 Low-power timer trigger #1110 ADCAALTTRGEN ADCA alternate trigger enable 6 2 read-write 00 XBARA output 12. #00 01 PDB0 trigger selected for ADCA. #01 ADCBTRGSEL ADCB trigger select 8 4 read-write 0001 High speed comparator 0 output #0001 0010 High speed comparator 1 output #0010 0011 High speed comparator 2 output #0011 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 0110 PIT trigger 2 #0110 0111 PIT trigger 3 #0111 1000 FTM0 trigger #1000 1001 FTM1 trigger #1001 1011 FTM3 trigger #1011 1100 XBARA output 41 #1100 1110 Low-power timer trigger #1110 ADCBALTTRGEN ADCB alternate trigger enable 14 2 read-write 00 XBARA output 13. #00 01 PDB1 trigger selected for ADCB #01 SOPT8 System Options Register 8 0x101C 32 read-write 0 0xFFFFFFFF FTM0SYNCBIT FTM0 Hardware Trigger 0 Software Synchronization 0 1 read-write 0 No effect #0 1 Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert. #1 FTM1SYNCBIT FTM1 Hardware Trigger 0 Software Synchronization 1 1 read-write 0 No effect. #0 1 Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert. #1 FTM3SYNCBIT FTM3 Hardware Trigger 0 Software Synchronization 3 1 read-write 0 No effect. #0 1 Write 1 to assert the TRIG0 input to FTM3, software must clear this bit to allow other trigger sources to assert. #1 FTM0CFSEL Carrier frequency selection for FTM0 output channel 8 1 read-write 0 FTM1 channel 1 output provides the carrier signal for FTM0 Timer Modulation mode. #0 1 LPTMR0 prescaler output provides the carrier signal for FTM0 Timer Modulation mode. #1 FTM3CFSEL Carrier frequency selection for FTM3 output channel 9 1 read-write 0 FTM1 channel 1 output provides the carrier signal for FTM3 Timer Modulation mode. #0 1 LPTMR0 prescaler output provides the carrier signal for FTM3 Timer Modulation mode. #1 FTM0OCH0SRC FTM0 channel 0 output source 16 1 read-write 0 FTM0_CH0 pin is output of FTM0 channel 0 output #0 1 FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by carrier frequency clock, as per FTM0CFSEL #1 FTM0OCH1SRC FTM0 channel 1 output source 17 1 read-write 0 FTM0_CH1 pin is output of FTM0 channel 1 output #0 1 FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by carrier frequency clock, as per FTM0CFSEL #1 FTM0OCH2SRC FTM0 channel 2 output source 18 1 read-write 0 FTM0_CH2 pin is output of FTM0 channel 2 output #0 1 FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by carrier frequency clock, as per FTM0CFSEL #1 FTM0OCH3SRC FTM0 channel 3 output source 19 1 read-write 0 FTM0_CH3 pin is output of FTM0 channel 3 output #0 1 FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by carrier frequency clock, as per FTM0CFSEL #1 FTM0OCH4SRC FTM0 channel 4 output source 20 1 read-write 0 FTM0_CH4 pin is output of FTM0 channel 4 output #0 1 FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by carrier frequency clock, as per FTM0CFSEL #1 FTM0OCH5SRC FTM0 channel 5 output source 21 1 read-write 0 FTM0_CH5 pin is output of FTM0 channel 5 output #0 1 FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by carrier frequency clock, as per FTM0CFSEL #1 FTM0OCH6SRC FTM0 channel 6 output source 22 1 read-write 0 FTM0_CH6 pin is output of FTM0 channel 6 output #0 1 FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by carrier frequency clock, as per FTM0CFSEL #1 FTM0OCH7SRC FTM0 channel 7 output source 23 1 read-write 0 FTM0_CH7 pin is output of FTM0 channel 7 output #0 1 FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by carrier frequency clock, as per FTM0CFSEL #1 FTM3OCH0SRC FTM3 channel 0 output source 24 1 read-write 0 FTM3_CH0 pin is output of FTM3 channel 0 output #0 1 FTM3_CH0 pin is output of FTM3 channel 0 output modulated by carrier frequency clock, as per FTM3CFSEL. #1 FTM3OCH1SRC FTM3 channel 1 output source 25 1 read-write 0 FTM3_CH1 pin is output of FTM3 channel 1 output #0 1 FTM3_CH1 pin is output of FTM3 channel 1 output modulated by carrier frequency clock, as per FTM3CFSEL. #1 FTM3OCH2SRC FTM3 channel 2 output source 26 1 read-write 0 FTM3_CH2 pin is output of FTM3 channel 2 output #0 1 FTM3_CH2 pin is output of FTM3 channel 2 output modulated by carrier frequency clock, as per FTM3CFSEL. #1 FTM3OCH3SRC FTM3 channel 3 output source 27 1 read-write 0 FTM3_CH3 pin is output of FTM3 channel 3 output #0 1 FTM3_CH3 pin is output of FTM3 channel 3 output modulated by carrier frequency clock, as per FTM3CFSEL. #1 FTM3OCH4SRC FTM3 channel 4 output source 28 1 read-write 0 FTM3_CH4 pin is output of FTM3 channel 4 output #0 1 FTM3_CH4 pin is output of FTM3 channel 4 output modulated by carrier frequency clock, as per FTM3CFSEL. #1 FTM3OCH5SRC FTM3 channel 5 output source 29 1 read-write 0 FTM3_CH5 pin is output of FTM3 channel 5 output #0 1 FTM3_CH5 pin is output of FTM3 channel 5 output modulated by carrier frequency clock, as per FTM3CFSEL. #1 FTM3OCH6SRC FTM3 channel 6 output source 30 1 read-write 0 FTM3_CH6 pin is output of FTM3 channel 6 output #0 1 FTM3_CH6 pin is output of FTM3 channel 6 output modulated by carrier frequency clock, as per FTM3CFSEL. #1 FTM3OCH7SRC FTM3 channel 7 output source 31 1 read-write 0 FTM3_CH7 pin is output of FTM3 channel 7 output #0 1 FTM3_CH7 pin is output of FTM3 channel 7 output modulated by carrier frequency clock, as per FTM3CFSEL. #1 SOPT9 System Options Register 9 0x1020 32 read-write 0 0xFFFFFFFF FTM1ICH0SRC FTM1 channel 0 input capture source select 4 2 read-write 00 FTM1_CH0 signal #00 01 CMP0 output #01 10 CMP1 output #10 FTM1ICH1SRC FTM1 channel 0 input capture source select 6 1 read-write 0 FTM1_CH1 signal #0 1 Exclusive OR of FTM1_CH1, FTM1_CH0 and XBARA output 42 #1 FTM0CLKSEL FlexTimer 0 External Clock Pin Select 24 2 read-write 00 FTM0 external clock driven by FTM_CLK0 pin #00 01 FTM0 external clock driven by FTM_CLK1 pin #01 10 FTM0 external clock driven by FTM_CLK2 pin #10 FTM1CLKSEL FlexTimer 1 External Clock Pin Select 26 2 read-write 00 FTM1 external clock driven by FTM_CLK0 pin #00 01 FTM1 external clock driven by FTM_CLK1 pin #01 10 FTM1 external clock driven by FTM_CLK2 pin #10 FTM3CLKSEL FlexTimer 3 External Clock Pin Select 30 2 read-write 00 FTM3 external clock driven by FTM_CLK0 pin #00 01 FTM3 external clock driven by FTM_CLK1 pin #01 10 FTM3 external clock driven by FTM_CLK2 pin #10 SDID System Device Identification Register 0x1024 32 read-only 0x40600100 0xF0FF0F80 PINID Pincount identification 0 4 read-only 0100 48-pin #0100 0101 64-pin #0101 1000 100-pin #1000 DIEID Device die number 7 5 read-only REVID Device revision number 12 4 read-only SERIESID Kinetis Series ID 20 4 read-only 0000 Kinetis K series #0000 0001 Kinetis L series #0001 0101 Kinetis W series #0101 0110 Kinetis V series #0110 SUBFAMID Kinetis Sub-Family ID 24 4 read-only 0001 KVx2 Subfamily (FlexTimer and ADC) #0001 0100 KVx4 Subfamily (eFlexPWM and ADC) #0100 0110 KVx6 Subfamily (eFlexPWM with FlexTimer and ADC) #0110 FAMILYID Kinetis Family ID 28 4 read-only 0100 Kinetis family of this device. This is the Vseries. #0100 SCGC4 System Clock Gating Control Register 4 0x1034 32 read-write 0xF0000030 0xFFFFFFFF EWM EWM Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 I2C0 I2C0 Clock Gate Control 6 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART0 UART0 Clock Gate Control 10 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART1 UART1 Clock Gate Control 11 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CMP Comparators Clock Gate Control 19 1 read-write 0 Clock disabled #0 1 Clock enabled #1 eFlexPWM0 eFlexPWM submodule 0 Clock Gate Control 24 1 read-write 0 Clock disabled #0 1 Clock enabled #1 eFlexPWM1 eFlexPWM submodule 1 Clock Gate Control 25 1 read-write 0 Clock disabled #0 1 Clock enabled #1 eFlexPWM2 eFlexPWM submodule 2 Clock Gate Control 26 1 read-write 0 Clock disabled #0 1 Clock enabled #1 eFlexPWM3 eFlexPWM submodule 3 Clock Gate Control 27 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC5 System Clock Gating Control Register 5 0x1038 32 read-write 0x40182 0xFFFFFFFF LPTMR Low Power Timer Access Control 0 1 read-write 0 Access disabled #0 1 Access enabled #1 PORTA Port A Clock Gate Control 9 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTB Port B Clock Gate Control 10 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTC Port C Clock Gate Control 11 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTD Port D Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTE Port E Clock Gate Control 13 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ENC This bit controls the clock gate to the ENC module. 21 1 read-write 0 Clock disabled #0 1 Clock enabled #1 XBARA XBARA Clock Gate Control 25 1 read-write 0 Clock disabled #0 1 Clock enabled #1 XBARB XBARB Clock Gate Control 26 1 read-write 0 Clock disabled #0 1 Clock enabled #1 AOI AOI Clock Gate Control 27 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ADC ADC Clock Gate Control 28 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC6 System Clock Gating Control Register 6 0x103C 32 read-write 0x1 0xFFFFFFFF FTF Flash Memory Clock Gate Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 DMAMUX DMA Mux Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FLEXCAN0 FlexCAN0 Clock Gate Control 4 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FLEXCAN1 FlexCAN1 Clock Gate Control 5 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM3 FTM3 Clock Gate Control 6 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SPI0 SPI0 Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PDB1 PDB1 Clock Gate Control 17 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CRC CRC Clock Gate Control 18 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PDB0 PDB0 Clock Gate Control 22 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PIT PIT Clock Gate Control 23 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM0 FTM0 Clock Gate Control 24 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM1 FTM1 Clock Gate Control 25 1 read-write 0 Clock disabled #0 1 Clock enabled #1 DAC0 DAC0 Clock Gate Control 31 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC7 System Clock Gating Control Register 7 0x1040 32 read-write 0x100 0xFFFFFFFF DMA DMA Clock Gate Control 8 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CLKDIV1 System Clock Divider Register 1 0x1044 32 read-write 0x10000 0xFFFFFFFF OUTDIV4 Clock 4 output divider value 16 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 OUTDIV2 Clock 2 output divider value 24 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 OUTDIV1 Clock 1 output divider value 28 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 FCFG1 Flash Configuration Register 1 0x104C 32 read-write 0xF00F0F00 0xFFFFFFFF FLASHDIS Flash Disable 0 1 read-write 0 Flash is enabled #0 1 Flash is disabled #1 FLASHDOZE Flash Doze 1 1 read-write 0 Flash remains enabled during Wait mode #0 1 Flash is disabled for the duration of Wait mode #1 PFSIZE Program flash size 24 4 read-only 0101 64 KB of program flash memory #0101 0111 128 KB of program flash memory #0111 1001 256 KB of program flash memory #1001 FCFG2 Flash Configuration Register 2 0x1050 32 read-only 0x800000 0xFFFFFFFF MAXADDR0 Max address block 0 24 7 read-only UIDH Unique Identification Register High 0x1054 32 read-only 0 0 UID Unique Identification 0 32 read-only UIDMH Unique Identification Register Mid-High 0x1058 32 read-only 0 0 UID Unique Identification 0 32 read-only UIDML Unique Identification Register Mid Low 0x105C 32 read-only 0 0 UID Unique Identification 0 32 read-only UIDL Unique Identification Register Low 0x1060 32 read-only 0 0 UID Unique Identification 0 32 read-only CLKDIV4 System Clock Divider Register 4 0x1068 32 read-write 0x10000000 0xFFFFFFFF TRACEFRAC Trace clock divider fraction 0 1 read-write TRACEDIV Trace clock divider divisor 1 3 read-write TRACEDIVEN Debug Trace Divider Control 28 1 read-write 0 Debug trace divider disabled #0 1 Debug trace divider enabled #1 MISCTRL0 Miscellaneous Control Register 0 0x106C 32 read-write 0 0xFFFFFFFF CMPWIN0SRC CMP Sample/Window Input 0 Source 8 2 read-write 00 XBARA output 16. #00 01 CMP0 Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 0. #01 10 PDB0 pluse-out channel 0. #10 11 PDB1 pluse-out channel 0. #11 CMPWIN1SRC CMP Sample/Window Input 1 Source 10 2 read-write 00 XBARA output 17. #00 01 CMP1 Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 1. #01 10 PDB0 pluse-out channel 1. #10 11 PDB1 pluse-out channel 1. #11 CMPWIN2SRC CMP Sample/Window Input 2 Source 12 2 read-write 00 XBARA output 18. #00 01 CMP2 Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 2. #01 10 PDB0 pluse-out channel 2. #10 11 PDB1 pluse-out channel 2. #11 CMPWIN3SRC CMP Sample/Window Input 3 Source 14 2 read-write 00 XBARA output 19. #00 01 CMP3 Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 3. #01 10 PDB0 pluse-out channel 3. #10 11 PDB1 pluse-out channel 3. #11 EWMINSRC EWM_IN Source 16 1 read-write 0 XBARA output 58. #0 1 EWM_IN pin #1 DACTRIGSRC DAC0 Hardware Trigger Input Source 18 2 read-write 00 XBARA output 15. #00 01 DAC0 can be triggered by both PDB0 interval trigger 0 and PDB1 interval trigger 0. #01 10 PDB0 interval trigger 0 #10 11 PDB1 interval trigger 0 #11 MISCTRL1 Miscellaneous Control Register 1 0x1070 32 read-write 0 0xFFFFFFFF SYNCXBARAPITTRIG0 Synchronize XBARA's Input PIT Trigger 0 with fast clock 8 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCXBARAPITTRIG1 Synchronize XBARA's Input PIT Trigger 1 with fast clock 9 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCXBARAPITTRIG2 Synchronize XBARA's Input PIT Trigger 2 with fast clock 10 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCXBARAPITTRIG3 Synchronize XBARA's Input PIT Trigger 3 with fast clock 11 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCXBARBPITTRIG0 Synchronize XBARB's Input PIT Trigger 0 with fast clock 12 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCXBARBPITTRIG1 Synchronize XBARB's Input PIT Trigger 1 with fast clock 13 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCDACHWTRIG Synchronize XBARA's output for DAC Hardware Trigger with flash/slow clock 16 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCEWMIN Synchronize XBARA's output for EWM's ewm_in with flash/slow clock 17 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCCMP0SAMPLEWIN Synchronize XBARA's output for CMP0's Sample/Window Input with flash/slow clock 20 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCCMP1SAMPLEWIN Synchronize XBARA's output for CMP1's Sample/Window Input with flash/slow clock 21 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCCMP2SAMPLEWIN Synchronize XBARA's output for CMP2's Sample/Window Input with flash/slow clock 22 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCCMP3SAMPLEWIN Synchronize XBARA's output for CMP3's Sample/Window Input with flash/slow clock 23 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 WDOGC WDOG Control Register 0x1100 32 read-write 0 0xFFFFFFFF WDOGCLKS WDOG Clock Select 1 1 read-write 0 Internal 1 kHz clock is source to WDOG2008 #0 1 MCGIRCLK is source to WDOG2008 #1 PWRC Power Control Register 0x1104 32 read-write 0x101 0xFFFFFFFF SRPDN NanoEdge Regulator 2.7V and 1.2V Supply Powerdown Control 0 2 read-write 00 NanoEdge regulator placed in normal mode. #00 01 NanoEdge regulator placed in powerdown mode. #01 10 NanoEdge regulator placed in normal mode and SRPDN is write protected until chip reset. #10 11 NanoEdge regulator placed in powerdown mode and SRPDN is write protected until chip reset. #11 SR27STDBY NanoEdge Regulator 2.7 V Supply Standby Control 2 2 read-write 00 NanoEdge regulator 2.7 V placed in normal mode. #00 01 NanoEdge regulator 2.7 V placed in standby mode. #01 10 NanoEdge regulator 2.7 V supply placed in normal mode and SR27STDBY is write protected until chip reset. #10 11 NanoEdge regulator 2.7 V supply placed in standby mode and SR27STDBY is write protected until chip reset. #11 SR12STDBY NanoEdge Regulator 1.2 V Supply Standby Control 6 2 read-write 00 NanoEdge regulator 1.2 V supply placed in normal mode #00 01 NanoEdge regulator 1.2 V supply placed in standby mode. #01 10 NanoEdge regulator 1.2 V supply placed in normal mode and SR12STDBY is write protected until chip reset. #10 11 NanoEdge regulator 1.2 V supply placed in standby mode and SR12STDBY is write protected until chip reset. #11 SRPWRDETEN NanoEdge PMC POWER Dectect Enable 8 1 read-write 0 Disable #0 1 Enable #1 SRPWRRDY NanoEdge PMC POWER Ready 9 1 read-write 0 Not ready #0 1 Assert PMC power output ready #1 SRPWROK NanoEdge PMC Status 16 1 read-only 0 Power supply for NanoEdge isn't ready. #0 1 Power supply for NanoEdge is OK. #1 ADCOPT ADC Channel 6/7 Mux Control Register 0x1108 32 read-write 0 0xFFFFFFFF ADCACH6SEL ADCA MUX0 selection for ADCA channel 6 0 3 read-write 000 ADCA MUX0's channel a. #000 001 ADCA MUX0's channel b. #001 010 ADCA MUX0's channel c. #010 011 ADCA MUX0's channel d. #011 100 ADCA MUX0's channel e. #100 110 ADCA MUX0's channel g. #110 ADCACH7SEL ADCA MUX1 selection for ADCA channel 7 4 3 read-write 000 ADCA MUX1's channel a. #000 001 ADCA MUX1's channel b. #001 010 ADCA MUX1's channel c. #010 100 ADCA MUX1's channel e. #100 101 ADCA MUX1's channel f. #101 110 ADCA MUX1's channel g. #110 111 PMC 1V #111 ADCBCH6SEL ADCB MUX1 selection for ADCB channel 6 8 3 read-write 000 ADCB MUX0's channel a. #000 001 ADCB MUX0's channel b. #001 010 ADCB MUX0's channel c. #010 011 ADCB MUX0's channel d. #011 100 ADCB MUX0's channel e. #100 101 ADCB MUX0's channel f. #101 110 ADCB MUX0's channel g. #110 111 PMC 1V. #111 ADCBCH7SEL ADCB MUX1 selection for ADCB channel 7 12 3 read-write 000 ADCB MUX1's channel a. #000 001 ADCB MUX1's channel b. #001 010 ADCB MUX1's channel c. #010 011 ADCB MUX1's channel d. #011 100 ADCB MUX1's channel e. #100 101 ADCB MUX1's channel f. #101 110 ADCB MUX1's channel g. #110 ROSB Enable ADC low current Mode 24 1 read-write 0 Disable ADC low current mode. #0 1 Enable ADC low current mode. #1 ADCIRCLK ADC Clock Status 25 1 read-only 0 ADC clock is fast peripherial clock. #0 1 ADC clock is MCGIRCLK. #1 PORTA Pin Control and Interrupts PORT PORTA_ 0x40049000 0 0xA4 registers PORTA 59 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0x702 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PORTB Pin Control and Interrupts PORT PORTB_ 0x4004A000 0 0xA4 registers PORTB 60 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PORTC Pin Control and Interrupts PORT PORTC_ 0x4004B000 0 0xA4 registers PORTC 61 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PORTD Pin Control and Interrupts PORT PORTD_ 0x4004C000 0 0xCC registers PORTD 62 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 DFER Digital Filter Enable Register 0xC0 32 read-write 0 0xFFFFFFFF DFE Digital Filter Enable 0 32 read-write 0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. #0 1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DFCR Digital Filter Clock Register 0xC4 32 read-write 0 0xFFFFFFFF CS Clock Source 0 1 read-write 0 Digital filters are clocked by the bus clock. #0 1 Digital filters are clocked by the LPO clock. #1 DFWR Digital Filter Width Register 0xC8 32 read-write 0 0xFFFFFFFF FILT Filter Length 0 5 read-write PORTE Pin Control and Interrupts PORT PORTE_ 0x4004D000 0 0xA4 registers PORTE 63 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 WDOG Generation 2008 Watchdog Timer WDOG_ 0x40052000 0 0x18 registers WDOG_EWM 22 STCTRLH Watchdog Status and Control Register High 0 16 read-write 0x1D2 0xFFFF WDOGEN Enables or disables the WDOG's operation 0 1 read-write 0 WDOG is disabled. #0 1 WDOG is enabled. #1 CLKSRC Selects clock source for the WDOG timer and other internal timing operations. 1 1 read-write 0 WDOG clock sourced from LPO . #0 1 WDOG clock sourced from alternate clock source. #1 IRQRSTEN Used to enable the debug breadcrumbs feature 2 1 read-write 0 WDOG time-out generates reset only. #0 1 WDOG time-out initially generates an interrupt. After WCT, it generates a reset. #1 WINEN Enables Windowing mode. 3 1 read-write 0 Windowing mode is disabled. #0 1 Windowing mode is enabled. #1 ALLOWUPDATE Enables updates to watchdog write-once registers, after the reset-triggered initial configuration window (WCT) closes, through unlock sequence 4 1 read-write 0 No further updates allowed to WDOG write-once registers. #0 1 WDOG write-once registers can be unlocked for updating. #1 DBGEN Enables or disables WDOG in Debug mode. 5 1 read-write 0 WDOG is disabled in CPU Debug mode. #0 1 WDOG is enabled in CPU Debug mode. #1 STOPEN Enables or disables WDOG in Stop mode. 6 1 read-write 0 WDOG is disabled in CPU Stop mode. #0 1 WDOG is enabled in CPU Stop mode. #1 WAITEN Enables or disables WDOG in Wait mode. 7 1 read-write 0 WDOG is disabled in CPU Wait mode. #0 1 WDOG is enabled in CPU Wait mode. #1 TESTWDOG Puts the watchdog in the functional test mode 10 1 read-write TESTSEL Effective only if TESTWDOG is set. Selects the test to be run on the watchdog timer. 11 1 read-write 0 Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test. #0 1 Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing. #1 BYTESEL This 2-bit field selects the byte to be tested when the watchdog is in the byte test mode. 12 2 read-write 00 Byte 0 selected #00 01 Byte 1 selected #01 10 Byte 2 selected #10 11 Byte 3 selected #11 DISTESTWDOG Allows the WDOG's functional test mode to be disabled permanently 14 1 read-write 0 WDOG functional test mode is not disabled. #0 1 WDOG functional test mode is disabled permanently until reset. #1 STCTRLL Watchdog Status and Control Register Low 0x2 16 read-write 0x1 0xFFFF INTFLG Interrupt flag 15 1 read-write TOVALH Watchdog Time-out Value Register High 0x4 16 read-write 0x4C 0xFFFF TOVALHIGH Defines the upper 16 bits of the 32-bit time-out value for the watchdog timer 0 16 read-write TOVALL Watchdog Time-out Value Register Low 0x6 16 read-write 0x4B4C 0xFFFF TOVALLOW Defines the lower 16 bits of the 32-bit time-out value for the watchdog timer 0 16 read-write WINH Watchdog Window Register High 0x8 16 read-write 0 0xFFFF WINHIGH Defines the upper 16 bits of the 32-bit window for the windowed mode of operation of the watchdog 0 16 read-write WINL Watchdog Window Register Low 0xA 16 read-write 0x10 0xFFFF WINLOW Defines the lower 16 bits of the 32-bit window for the windowed mode of operation of the watchdog 0 16 read-write REFRESH Watchdog Refresh register 0xC 16 read-write 0xB480 0xFFFF WDOGREFRESH Watchdog refresh register 0 16 read-write UNLOCK Watchdog Unlock register 0xE 16 read-write 0xD928 0xFFFF WDOGUNLOCK Writing the unlock sequence values to this register to makes the watchdog write-once registers writable again 0 16 read-write TMROUTH Watchdog Timer Output Register High 0x10 16 read-write 0 0xFFFF TIMEROUTHIGH Shows the value of the upper 16 bits of the watchdog timer. 0 16 read-write TMROUTL Watchdog Timer Output Register Low 0x12 16 read-write 0 0xFFFF TIMEROUTLOW Shows the value of the lower 16 bits of the watchdog timer. 0 16 read-write RSTCNT Watchdog Reset Count register 0x14 16 read-write 0 0xFFFF RSTCNT Counts the number of times the watchdog resets the system 0 16 read-write PRESC Watchdog Prescaler register 0x16 16 read-write 0x400 0xFFFF PRESCVAL 3-bit prescaler for the watchdog clock source 8 3 read-write ENC0 Quadrature Decoder ENC0_ 0x40055000 0 0x28 registers ENC0_COMPARE 66 ENC0_HOME 67 ENC0_WDOG_SAB 68 ENC0_INDEX 69 CTRL Control Register 0 16 read-write 0 0xFFFF CMPIE Compare Interrupt Enable 0 1 read-write 0 Compare interrupt is disabled #0 1 Compare interrupt is enabled #1 CMPIRQ Compare Interrupt Request 1 1 read-write 0 No match has occurred #0 1 COMP match has occurred #1 WDE Watchdog Enable 2 1 read-write 0 Watchdog timer is disabled #0 1 Watchdog timer is enabled #1 DIE Watchdog Timeout Interrupt Enable 3 1 read-write 0 Watchdog timer interrupt is disabled #0 1 Watchdog timer interrupt is enabled #1 DIRQ Watchdog Timeout Interrupt Request 4 1 read-write 0 No interrupt has occurred #0 1 Watchdog timeout interrupt has occurred #1 XNE Use Negative Edge of INDEX Pulse 5 1 read-write 0 Use positive transition edge of INDEX pulse #0 1 Use negative transition edge of INDEX pulse #1 XIP INDEX Triggered Initialization of Position Counters UPOS and LPOS 6 1 read-write 0 No action #0 1 INDEX pulse initializes the position counter #1 XIE INDEX Pulse Interrupt Enable 7 1 read-write 0 INDEX pulse interrupt is disabled #0 1 INDEX pulse interrupt is enabled #1 XIRQ INDEX Pulse Interrupt Request 8 1 read-write 0 No interrupt has occurred #0 1 INDEX pulse interrupt has occurred #1 PH1 Enable Signal Phase Count Mode 9 1 read-write 0 Use standard quadrature decoder where PHASEA and PHASEB represent a two phase quadrature signal. #0 1 Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction. If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down If CTRL[REV] = 1, PHASEB = 1, then count up #1 REV Enable Reverse Direction Counting 10 1 read-write 0 Count normally #0 1 Count in the reverse direction #1 SWIP Software Triggered Initialization of Position Counters UPOS and LPOS 11 1 write-only 0 No action #0 1 Initialize position counter #1 HNE Use Negative Edge of HOME Input 12 1 read-write 0 Use positive going edge-to-trigger initialization of position counters UPOS and LPOS #0 1 Use negative going edge-to-trigger initialization of position counters UPOS and LPOS #1 HIP Enable HOME to Initialize Position Counters UPOS and LPOS 13 1 read-write 0 No action #0 1 HOME signal initializes the position counter #1 HIE HOME Interrupt Enable 14 1 read-write 0 Disable HOME interrupts #0 1 Enable HOME interrupts #1 HIRQ HOME Signal Transition Interrupt Request 15 1 read-write 0 No interrupt #0 1 HOME signal transition interrupt request #1 FILT Input Filter Register 0x2 16 read-write 0 0xFFFF FILT_PER Input Filter Sample Period 0 8 read-write FILT_CNT Input Filter Sample Count 8 3 read-write WTR Watchdog Timeout Register 0x4 16 read-write 0 0xFFFF WDOG WDOG[15:0] is a binary representation of the number of clock cycles plus one that the watchdog timer counts before timing out and optionally generating an interrupt 0 16 read-write POSD Position Difference Counter Register 0x6 16 read-write 0 0xFFFF POSD This read/write register contains the position change in value occurring between each read of the position register 0 16 read-write POSDH Position Difference Hold Register 0x8 16 read-only 0 0xFFFF POSDH This read-only register contains a snapshot of the value of the POSD register 0 16 read-only REV Revolution Counter Register 0xA 16 read-write 0 0xFFFF REV This read/write register contains the current value of the revolution counter. 0 16 read-write REVH Revolution Hold Register 0xC 16 read-only 0 0xFFFF REVH This read-only register contains a snapshot of the value of the REV register. 0 16 read-only UPOS Upper Position Counter Register 0xE 16 read-write 0 0xFFFF POS This read/write register contains the upper (most significant) half of the position counter 0 16 read-write LPOS Lower Position Counter Register 0x10 16 read-write 0 0xFFFF POS This read/write register contains the lower (least significant) half of the position counter 0 16 read-write UPOSH Upper Position Hold Register 0x12 16 read-only 0 0xFFFF POSH This read-only register contains a snapshot of the UPOS register. 0 16 read-only LPOSH Lower Position Hold Register 0x14 16 read-only 0 0xFFFF POSH This read-only register contains a snapshot of the LPOS register. 0 16 read-only UINIT Upper Initialization Register 0x16 16 read-write 0 0xFFFF INIT This read/write register contains the value to be used to initialize the upper half of the position counter (UPOS) 0 16 read-write LINIT Lower Initialization Register 0x18 16 read-write 0 0xFFFF INIT This read/write register contains the value to be used to initialize the lower half of the position counter (LPOS) 0 16 read-write IMR Input Monitor Register 0x1A 16 read-only 0 0xFFFF HOME This is the raw HOME input. 0 1 read-only INDEX This is the raw INDEX input. 1 1 read-only PHB This is the raw PHASEB input. 2 1 read-only PHA This is the raw PHASEA input. 3 1 read-only FHOM This is the filtered version of HOME input. 4 1 read-only FIND This is the filtered version of INDEX input. 5 1 read-only FPHB This is the filtered version of PHASEB input. 6 1 read-only FPHA This is the filtered version of PHASEA input. 7 1 read-only TST Test Register 0x1C 16 read-write 0 0xFFFF TEST_COUNT These bits hold the number of quadrature advances to generate. 0 8 read-write TEST_PERIOD These bits hold the period of quadrature phase in IPBus clock cycles. 8 5 read-write QDN Quadrature Decoder Negative Signal 13 1 read-write 0 Leaves quadrature decoder signal in a positive direction #0 1 Generates a negative quadrature decoder signal #1 TCE Test Counter Enable 14 1 read-write 0 Test count is not enabled #0 1 Test count is enabled #1 TEN Test Mode Enable 15 1 read-write 0 Test module is not enabled #0 1 Test module is enabled #1 CTRL2 Control 2 Register 0x1E 16 read-write 0 0xFFFF UPDHLD Update Hold Registers 0 1 read-write 0 Disable updates of hold registers on rising edge of TRIGGER #0 1 Enable updates of hold registers on rising edge of TRIGGER #1 UPDPOS Update Position Registers 1 1 read-write 0 No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER #0 1 Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER #1 MOD Enable Modulo Counting 2 1 read-write 0 Disable modulo counting #0 1 Enable modulo counting #1 DIR Count Direction Flag 3 1 read-only 0 Last count was in the down direction #0 1 Last count was in the up direction #1 RUIE Roll-under Interrupt Enable 4 1 read-write 0 Roll-under interrupt is disabled #0 1 Roll-under interrupt is enabled #1 RUIRQ Roll-under Interrupt Request 5 1 read-write 0 No roll-under has occurred #0 1 Roll-under has occurred #1 ROIE Roll-over Interrupt Enable 6 1 read-write 0 Roll-over interrupt is disabled #0 1 Roll-over interrupt is enabled #1 ROIRQ Roll-over Interrupt Request 7 1 read-write 0 No roll-over has occurred #0 1 Roll-over has occurred #1 REVMOD Revolution Counter Modulus Enable 8 1 read-write 0 Use INDEX pulse to increment/decrement revolution counter (REV). #0 1 Use modulus counting roll-over/under to increment/decrement revolution counter (REV). #1 OUTCTL Output Control 9 1 read-write 0 POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP). #0 1 POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read. #1 SABIE Simultaneous PHASEA and PHASEB Change Interrupt Enable 10 1 read-write 0 Simultaneous PHASEA and PHASEB change interrupt disabled. #0 1 Simultaneous PHASEA and PHASEB change interrupt enabled. #1 SABIRQ Simultaneous PHASEA and PHASEB Change Interrupt Request 11 1 read-write 0 No simultaneous change of PHASEA and PHASEB has occurred. #0 1 A simultaneous change of PHASEA and PHASEB has occurred. #1 UMOD Upper Modulus Register 0x20 16 read-write 0 0xFFFF MOD This read/write register contains the upper (most significant) half of the modulus register 0 16 read-write LMOD Lower Modulus Register 0x22 16 read-write 0 0xFFFF MOD This read/write register contains the lower (least significant) half of the modulus register 0 16 read-write UCOMP Upper Position Compare Register 0x24 16 read-write 0xFFFF 0xFFFF COMP This read/write register contains the upper (most significant) half of the position compare register 0 16 read-write LCOMP Lower Position Compare Register 0x26 16 read-write 0xFFFF 0xFFFF COMP This read/write register contains the lower (least significant) half of the position compare register 0 16 read-write XBARA Crossbar Switch XBARA_ 0x40059000 0 0x40 registers XBARA 54 SEL0 Crossbar A Select Register 0 0 16 read-write 0 0xFFFF SEL0 Input (XBARA_INn) to be muxed to XBARA_OUT0 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL1 Input (XBARA_INn) to be muxed to XBARA_OUT1 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL1 Crossbar A Select Register 1 0x2 16 read-write 0 0xFFFF SEL2 Input (XBARA_INn) to be muxed to XBARA_OUT2 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL3 Input (XBARA_INn) to be muxed to XBARA_OUT3 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL2 Crossbar A Select Register 2 0x4 16 read-write 0 0xFFFF SEL4 Input (XBARA_INn) to be muxed to XBARA_OUT4 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL5 Input (XBARA_INn) to be muxed to XBARA_OUT5 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL3 Crossbar A Select Register 3 0x6 16 read-write 0 0xFFFF SEL6 Input (XBARA_INn) to be muxed to XBARA_OUT6 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL7 Input (XBARA_INn) to be muxed to XBARA_OUT7 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL4 Crossbar A Select Register 4 0x8 16 read-write 0 0xFFFF SEL8 Input (XBARA_INn) to be muxed to XBARA_OUT8 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL9 Input (XBARA_INn) to be muxed to XBARA_OUT9 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL5 Crossbar A Select Register 5 0xA 16 read-write 0 0xFFFF SEL10 Input (XBARA_INn) to be muxed to XBARA_OUT10 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL11 Input (XBARA_INn) to be muxed to XBARA_OUT11 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL6 Crossbar A Select Register 6 0xC 16 read-write 0 0xFFFF SEL12 Input (XBARA_INn) to be muxed to XBARA_OUT12 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL13 Input (XBARA_INn) to be muxed to XBARA_OUT13 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL7 Crossbar A Select Register 7 0xE 16 read-write 0 0xFFFF SEL14 Input (XBARA_INn) to be muxed to XBARA_OUT14 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL15 Input (XBARA_INn) to be muxed to XBARA_OUT15 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL8 Crossbar A Select Register 8 0x10 16 read-write 0 0xFFFF SEL16 Input (XBARA_INn) to be muxed to XBARA_OUT16 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL17 Input (XBARA_INn) to be muxed to XBARA_OUT17 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL9 Crossbar A Select Register 9 0x12 16 read-write 0 0xFFFF SEL18 Input (XBARA_INn) to be muxed to XBARA_OUT18 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL19 Input (XBARA_INn) to be muxed to XBARA_OUT19 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL10 Crossbar A Select Register 10 0x14 16 read-write 0 0xFFFF SEL20 Input (XBARA_INn) to be muxed to XBARA_OUT20 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL21 Input (XBARA_INn) to be muxed to XBARA_OUT21 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL11 Crossbar A Select Register 11 0x16 16 read-write 0 0xFFFF SEL22 Input (XBARA_INn) to be muxed to XBARA_OUT22 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL23 Input (XBARA_INn) to be muxed to XBARA_OUT23 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL12 Crossbar A Select Register 12 0x18 16 read-write 0 0xFFFF SEL24 Input (XBARA_INn) to be muxed to XBARA_OUT24 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL25 Input (XBARA_INn) to be muxed to XBARA_OUT25 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL13 Crossbar A Select Register 13 0x1A 16 read-write 0 0xFFFF SEL26 Input (XBARA_INn) to be muxed to XBARA_OUT26 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL27 Input (XBARA_INn) to be muxed to XBARA_OUT27 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL14 Crossbar A Select Register 14 0x1C 16 read-write 0 0xFFFF SEL28 Input (XBARA_INn) to be muxed to XBARA_OUT28 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL29 Input (XBARA_INn) to be muxed to XBARA_OUT29 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL15 Crossbar A Select Register 15 0x1E 16 read-write 0 0xFFFF SEL30 Input (XBARA_INn) to be muxed to XBARA_OUT30 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL31 Input (XBARA_INn) to be muxed to XBARA_OUT31 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL16 Crossbar A Select Register 16 0x20 16 read-write 0 0xFFFF SEL32 Input (XBARA_INn) to be muxed to XBARA_OUT32 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL33 Input (XBARA_INn) to be muxed to XBARA_OUT33 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL17 Crossbar A Select Register 17 0x22 16 read-write 0 0xFFFF SEL34 Input (XBARA_INn) to be muxed to XBARA_OUT34 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL35 Input (XBARA_INn) to be muxed to XBARA_OUT35 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL18 Crossbar A Select Register 18 0x24 16 read-write 0 0xFFFF SEL36 Input (XBARA_INn) to be muxed to XBARA_OUT36 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL37 Input (XBARA_INn) to be muxed to XBARA_OUT37 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL19 Crossbar A Select Register 19 0x26 16 read-write 0 0xFFFF SEL38 Input (XBARA_INn) to be muxed to XBARA_OUT38 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL39 Input (XBARA_INn) to be muxed to XBARA_OUT39 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL20 Crossbar A Select Register 20 0x28 16 read-write 0 0xFFFF SEL40 Input (XBARA_INn) to be muxed to XBARA_OUT40 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL41 Input (XBARA_INn) to be muxed to XBARA_OUT41 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL21 Crossbar A Select Register 21 0x2A 16 read-write 0 0xFFFF SEL42 Input (XBARA_INn) to be muxed to XBARA_OUT42 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL43 Input (XBARA_INn) to be muxed to XBARA_OUT43 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL22 Crossbar A Select Register 22 0x2C 16 read-write 0 0xFFFF SEL44 Input (XBARA_INn) to be muxed to XBARA_OUT44 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL45 Input (XBARA_INn) to be muxed to XBARA_OUT45 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL23 Crossbar A Select Register 23 0x2E 16 read-write 0 0xFFFF SEL46 Input (XBARA_INn) to be muxed to XBARA_OUT46 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL47 Input (XBARA_INn) to be muxed to XBARA_OUT47 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL24 Crossbar A Select Register 24 0x30 16 read-write 0 0xFFFF SEL48 Input (XBARA_INn) to be muxed to XBARA_OUT48 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL49 Input (XBARA_INn) to be muxed to XBARA_OUT49 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL25 Crossbar A Select Register 25 0x32 16 read-write 0 0xFFFF SEL50 Input (XBARA_INn) to be muxed to XBARA_OUT50 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL51 Input (XBARA_INn) to be muxed to XBARA_OUT51 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL26 Crossbar A Select Register 26 0x34 16 read-write 0 0xFFFF SEL52 Input (XBARA_INn) to be muxed to XBARA_OUT52 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL53 Input (XBARA_INn) to be muxed to XBARA_OUT53 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL27 Crossbar A Select Register 27 0x36 16 read-write 0 0xFFFF SEL54 Input (XBARA_INn) to be muxed to XBARA_OUT54 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL55 Input (XBARA_INn) to be muxed to XBARA_OUT55 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL28 Crossbar A Select Register 28 0x38 16 read-write 0 0xFFFF SEL56 Input (XBARA_INn) to be muxed to XBARA_OUT56 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL57 Input (XBARA_INn) to be muxed to XBARA_OUT57 (refer to Functional Description section for input/output assignment) 8 6 read-write SEL29 Crossbar A Select Register 29 0x3A 16 read-write 0 0xFFFF SEL58 Input (XBARA_INn) to be muxed to XBARA_OUT58 (refer to Functional Description section for input/output assignment) 0 6 read-write CTRL0 Crossbar A Control Register 0 0x3C 16 read-write 0 0xFFFF DEN0 DMA Enable for XBAR_OUT0 0 1 read-write 0 DMA disabled #0 1 DMA enabled #1 IEN0 Interrupt Enable for XBAR_OUT0 1 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 EDGE0 Active edge for edge detection on XBAR_OUT0 2 2 read-write 00 STS0 never asserts #00 01 STS0 asserts on rising edges of XBAR_OUT0 #01 10 STS0 asserts on falling edges of XBAR_OUT0 #10 11 STS0 asserts on rising and falling edges of XBAR_OUT0 #11 STS0 Edge detection status for XBAR_OUT0 4 1 read-write 0 Active edge not yet detected on XBAR_OUT0 #0 1 Active edge detected on XBAR_OUT0 #1 DEN1 DMA Enable for XBAR_OUT1 8 1 read-write 0 DMA disabled #0 1 DMA enabled #1 IEN1 Interrupt Enable for XBAR_OUT1 9 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 EDGE1 Active edge for edge detection on XBAR_OUT1 10 2 read-write 00 STS1 never asserts #00 01 STS1 asserts on rising edges of XBAR_OUT1 #01 10 STS1 asserts on falling edges of XBAR_OUT1 #10 11 STS1 asserts on rising and falling edges of XBAR_OUT1 #11 STS1 Edge detection status for XBAR_OUT1 12 1 read-write 0 Active edge not yet detected on XBAR_OUT1 #0 1 Active edge detected on XBAR_OUT1 #1 CTRL1 Crossbar A Control Register 1 0x3E 16 read-write 0 0xFFFF DEN2 DMA Enable for XBAR_OUT2 0 1 read-write 0 DMA disabled #0 1 DMA enabled #1 IEN2 Interrupt Enable for XBAR_OUT2 1 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 EDGE2 Active edge for edge detection on XBAR_OUT2 2 2 read-write 00 STS2 never asserts #00 01 STS2 asserts on rising edges of XBAR_OUT2 #01 10 STS2 asserts on falling edges of XBAR_OUT2 #10 11 STS2 asserts on rising and falling edges of XBAR_OUT2 #11 STS2 Edge detection status for XBAR_OUT2 4 1 read-write 0 Active edge not yet detected on XBAR_OUT2 #0 1 Active edge detected on XBAR_OUT2 #1 DEN3 DMA Enable for XBAR_OUT3 8 1 read-write 0 DMA disabled #0 1 DMA enabled #1 IEN3 Interrupt Enable for XBAR_OUT3 9 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 EDGE3 Active edge for edge detection on XBAR_OUT3 10 2 read-write 00 STS3 never asserts #00 01 STS3 asserts on rising edges of XBAR_OUT3 #01 10 STS3 asserts on falling edges of XBAR_OUT3 #10 11 STS3 asserts on rising and falling edges of XBAR_OUT3 #11 STS3 Edge detection status for XBAR_OUT3 12 1 read-write 0 Active edge not yet detected on XBAR_OUT3 #0 1 Active edge detected on XBAR_OUT3 #1 XBARB Crossbar Switch XBARB_ 0x4005A000 0 0x10 registers SEL0 Crossbar B Select Register 0 0 16 read-write 0 0xFFFF SEL0 Input (XBARB_INn) to be muxed to XBARB_OUT0 (refer to Functional Description section for input/output assignment) 0 5 read-write SEL1 Input (XBARB_INn) to be muxed to XBARB_OUT1 (refer to Functional Description section for input/output assignment) 8 5 read-write SEL1 Crossbar B Select Register 1 0x2 16 read-write 0 0xFFFF SEL2 Input (XBARB_INn) to be muxed to XBARB_OUT2 (refer to Functional Description section for input/output assignment) 0 5 read-write SEL3 Input (XBARB_INn) to be muxed to XBARB_OUT3 (refer to Functional Description section for input/output assignment) 8 5 read-write SEL2 Crossbar B Select Register 2 0x4 16 read-write 0 0xFFFF SEL4 Input (XBARB_INn) to be muxed to XBARB_OUT4 (refer to Functional Description section for input/output assignment) 0 5 read-write SEL5 Input (XBARB_INn) to be muxed to XBARB_OUT5 (refer to Functional Description section for input/output assignment) 8 5 read-write SEL3 Crossbar B Select Register 3 0x6 16 read-write 0 0xFFFF SEL6 Input (XBARB_INn) to be muxed to XBARB_OUT6 (refer to Functional Description section for input/output assignment) 0 5 read-write SEL7 Input (XBARB_INn) to be muxed to XBARB_OUT7 (refer to Functional Description section for input/output assignment) 8 5 read-write SEL4 Crossbar B Select Register 4 0x8 16 read-write 0 0xFFFF SEL8 Input (XBARB_INn) to be muxed to XBARB_OUT8 (refer to Functional Description section for input/output assignment) 0 5 read-write SEL9 Input (XBARB_INn) to be muxed to XBARB_OUT9 (refer to Functional Description section for input/output assignment) 8 5 read-write SEL5 Crossbar B Select Register 5 0xA 16 read-write 0 0xFFFF SEL10 Input (XBARB_INn) to be muxed to XBARB_OUT10 (refer to Functional Description section for input/output assignment) 0 5 read-write SEL11 Input (XBARB_INn) to be muxed to XBARB_OUT11 (refer to Functional Description section for input/output assignment) 8 5 read-write SEL6 Crossbar B Select Register 6 0xC 16 read-write 0 0xFFFF SEL12 Input (XBARB_INn) to be muxed to XBARB_OUT12 (refer to Functional Description section for input/output assignment) 0 5 read-write SEL13 Input (XBARB_INn) to be muxed to XBARB_OUT13 (refer to Functional Description section for input/output assignment) 8 5 read-write SEL7 Crossbar B Select Register 7 0xE 16 read-write 0 0xFFFF SEL14 Input (XBARB_INn) to be muxed to XBARB_OUT14 (refer to Functional Description section for input/output assignment) 0 5 read-write SEL15 Input (XBARB_INn) to be muxed to XBARB_OUT15 (refer to Functional Description section for input/output assignment) 8 5 read-write AOI AND/OR/INVERT module AOI_ 0x4005B000 0 0x10 registers 4 0x4 0,1,2,3 BFCRT01%s Boolean Function Term 0 and 1 Configuration Register for EVENTn 0 16 read-write 0 0xFFFF PT1_DC Product term 1, D input configuration 0 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 PT1_CC Product term 1, C input configuration 2 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT1_BC Product term 1, B input configuration 4 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT1_AC Product term 1, A input configuration 6 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 PT0_DC Product term 0, D input configuration 8 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 PT0_CC Product term 0, C input configuration 10 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT0_BC Product term 0, B input configuration 12 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT0_AC Product term 0, A input configuration 14 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 4 0x4 0,1,2,3 BFCRT23%s Boolean Function Term 2 and 3 Configuration Register for EVENTn 0x2 16 read-write 0 0xFFFF PT3_DC Product term 3, D input configuration 0 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 PT3_CC Product term 3, C input configuration 2 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT3_BC Product term 3, B input configuration 4 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT3_AC Product term 3, A input configuration 6 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 PT2_DC Product term 2, D input configuration 8 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 PT2_CC Product term 2, C input configuration 10 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT2_BC Product term 2, B input configuration 12 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT2_AC Product term 2, A input configuration 14 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 ADC Analog to digital converter ADC_ 0x4005C000 0 0xAC registers ADC_ERR 38 ADCA 39 ADCB 73 CTRL1 ADC Control Register 1 0 16 read-write 0x5005 0xFFFF SMODE ADC Scan Mode Control 0 3 read-write 000 Once (single) sequential #000 001 Once parallel #001 010 Loop sequential #010 011 Loop parallel #011 100 Triggered sequential #100 101 Triggered parallel (default) #101 CHNCFG_L CHCNF (Channel Configure Low) bits 4 4 read-write HLMTIE High Limit Interrupt Enable 8 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 LLMTIE Low Limit Interrupt Enable 9 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 ZCIE Zero Crossing Interrupt Enable 10 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 EOSIE0 End Of Scan Interrupt Enable 11 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 SYNC0 SYNC0 Enable 12 1 read-write 0 Scan is initiated by a write to CTRL1[START0] only #0 1 Use a SYNC0 input pulse or CTRL1[START0] to initiate a scan #1 START0 START0 Conversion 13 1 write-only 0 No action #0 1 Start command is issued #1 STOP0 Stop 14 1 read-write 0 Normal operation #0 1 Stop mode #1 DMAEN0 DMA enable 15 1 read-write 0 DMA is not enabled. #0 1 DMA is enabled. #1 CTRL2 ADC Control Register 2 0x2 16 read-write 0x5044 0xFFFF DIV0 Clock Divisor Select 0 6 read-write SIMULT Simultaneous mode 6 1 read-write 0 Parallel scans done independently #0 1 Parallel scans done simultaneously (default) #1 CHNCFG_H CHCNF (Channel Configure High) bits 7 4 read-write EOSIE1 End Of Scan Interrupt Enable 11 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 SYNC1 SYNC1 Enable 12 1 read-write 0 B converter parallel scan is initiated by a write to CTRL2[START1] bit only #0 1 Use a SYNC1 input pulse or CTRL2[START1] bit to initiate a B converter parallel scan #1 START1 START1 Conversion 13 1 write-only 0 No action #0 1 Start command is issued #1 STOP1 Stop 14 1 read-write 0 Normal operation #0 1 Stop mode #1 DMAEN1 DMA enable 15 1 read-write 0 DMA is not enabled. #0 1 DMA is enabled. #1 ZXCTRL1 ADC Zero Crossing Control 1 Register 0x4 16 read-write 0 0xFFFF ZCE0 Zero crossing enable 0 0 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE1 Zero crossing enable 1 2 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE2 Zero crossing enable 2 4 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE3 Zero crossing enable 3 6 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE4 Zero crossing enable 4 8 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE5 Zero crossing enable 5 10 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE6 Zero crossing enable 6 12 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE7 Zero crossing enable 7 14 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZXCTRL2 ADC Zero Crossing Control 2 Register 0x6 16 read-write 0 0xFFFF ZCE8 Zero crossing enable 8 0 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE9 Zero crossing enable 9 2 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE10 Zero crossing enable 10 4 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE11 Zero crossing enable 11 6 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE12 Zero crossing enable 12 8 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE13 Zero crossing enable 13 10 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE14 Zero crossing enable 14 12 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE15 Zero crossing enable 15 14 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 CLIST1 ADC Channel List Register 1 0x8 16 read-write 0x3210 0xFFFF SAMPLE0 Sample Field 0 0 4 read-write 0000 Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1- #0000 0001 Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1- #0001 0010 Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3- #0010 0011 Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3- #0011 0100 Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5- #0100 0101 Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5- #0101 0110 Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7- #0110 0111 Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7- #0111 1000 Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1- #1000 1001 Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1- #1001 1010 Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3- #1010 1011 Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3- #1011 1100 Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5- #1100 1101 Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5- #1101 1110 Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7- #1110 1111 Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7- #1111 SAMPLE1 Sample Field 1 4 4 read-write 0000 Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1- #0000 0001 Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1- #0001 0010 Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3- #0010 0011 Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3- #0011 0100 Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5- #0100 0101 Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5- #0101 0110 Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7- #0110 0111 Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7- #0111 1000 Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1- #1000 1001 Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1- #1001 1010 Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3- #1010 1011 Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3- #1011 1100 Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5- #1100 1101 Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5- #1101 1110 Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7- #1110 1111 Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7- #1111 SAMPLE2 Sample Field 2 8 4 read-write 0000 Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1- #0000 0001 Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1- #0001 0010 Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3- #0010 0011 Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3- #0011 0100 Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5- #0100 0101 Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5- #0101 0110 Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7- #0110 0111 Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7- #0111 1000 Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1- #1000 1001 Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1- #1001 1010 Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3- #1010 1011 Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3- #1011 1100 Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5- #1100 1101 Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5- #1101 1110 Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7- #1110 1111 Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7- #1111 SAMPLE3 Sample Field 3 12 4 read-write 0000 Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1- #0000 0001 Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1- #0001 0010 Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3- #0010 0011 Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3- #0011 0100 Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5- #0100 0101 Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5- #0101 0110 Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7- #0110 0111 Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7- #0111 1000 Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1- #1000 1001 Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1- #1001 1010 Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3- #1010 1011 Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3- #1011 1100 Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5- #1100 1101 Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5- #1101 1110 Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7- #1110 1111 Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7- #1111 CLIST2 ADC Channel List Register 2 0xA 16 read-write 0x7654 0xFFFF SAMPLE4 Sample Field 4 0 4 read-write 0000 Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1- #0000 0001 Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1- #0001 0010 Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3- #0010 0011 Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3- #0011 0100 Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5- #0100 0101 Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5- #0101 0110 Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7- #0110 0111 Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7- #0111 1000 Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1- #1000 1001 Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1- #1001 1010 Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3- #1010 1011 Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3- #1011 1100 Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5- #1100 1101 Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5- #1101 1110 Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7- #1110 1111 Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7- #1111 SAMPLE5 Sample Field 5 4 4 read-write 0000 Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1- #0000 0001 Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1- #0001 0010 Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3- #0010 0011 Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3- #0011 0100 Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5- #0100 0101 Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5- #0101 0110 Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7- #0110 0111 Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7- #0111 1000 Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1- #1000 1001 Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1- #1001 1010 Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3- #1010 1011 Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3- #1011 1100 Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5- #1100 1101 Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5- #1101 1110 Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7- #1110 1111 Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7- #1111 SAMPLE6 Sample Field 6 8 4 read-write 0000 Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1- #0000 0001 Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1- #0001 0010 Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3- #0010 0011 Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3- #0011 0100 Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5- #0100 0101 Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5- #0101 0110 Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7- #0110 0111 Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7- #0111 1000 Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1- #1000 1001 Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1- #1001 1010 Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3- #1010 1011 Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3- #1011 1100 Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5- #1100 1101 Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5- #1101 1110 Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7- #1110 1111 Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7- #1111 SAMPLE7 Sample Field 7 12 4 read-write 0000 Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1- #0000 0001 Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1- #0001 0010 Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3- #0010 0011 Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3- #0011 0100 Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5- #0100 0101 Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5- #0101 0110 Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7- #0110 0111 Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7- #0111 1000 Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1- #1000 1001 Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1- #1001 1010 Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3- #1010 1011 Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3- #1011 1100 Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5- #1100 1101 Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5- #1101 1110 Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7- #1110 1111 Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7- #1111 CLIST3 ADC Channel List Register 3 0xC 16 read-write 0xBA98 0xFFFF SAMPLE8 Sample Field 8 0 4 read-write 0000 Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1- #0000 0001 Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1- #0001 0010 Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3- #0010 0011 Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3- #0011 0100 Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5- #0100 0101 Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5- #0101 0110 Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7- #0110 0111 Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7- #0111 1000 Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1- #1000 1001 Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1- #1001 1010 Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3- #1010 1011 Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3- #1011 1100 Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5- #1100 1101 Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5- #1101 1110 Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7- #1110 1111 Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7- #1111 SAMPLE9 Sample Field 9 4 4 read-write 0000 Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1- #0000 0001 Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1- #0001 0010 Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3- #0010 0011 Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3- #0011 0100 Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5- #0100 0101 Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5- #0101 0110 Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7- #0110 0111 Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7- #0111 1000 Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1- #1000 1001 Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1- #1001 1010 Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3- #1010 1011 Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3- #1011 1100 Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5- #1100 1101 Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5- #1101 1110 Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7- #1110 1111 Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7- #1111 SAMPLE10 Sample Field 10 8 4 read-write 0000 Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1- #0000 0001 Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1- #0001 0010 Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3- #0010 0011 Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3- #0011 0100 Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5- #0100 0101 Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5- #0101 0110 Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7- #0110 0111 Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7- #0111 1000 Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1- #1000 1001 Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1- #1001 1010 Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3- #1010 1011 Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3- #1011 1100 Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5- #1100 1101 Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5- #1101 1110 Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7- #1110 1111 Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7- #1111 SAMPLE11 Sample Field 11 12 4 read-write 0000 Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1- #0000 0001 Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1- #0001 0010 Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3- #0010 0011 Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3- #0011 0100 Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5- #0100 0101 Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5- #0101 0110 Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7- #0110 0111 Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7- #0111 1000 Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1- #1000 1001 Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1- #1001 1010 Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3- #1010 1011 Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3- #1011 1100 Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5- #1100 1101 Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5- #1101 1110 Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7- #1110 1111 Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7- #1111 CLIST4 ADC Channel List Register 4 0xE 16 read-write 0xFEDC 0xFFFF SAMPLE12 Sample Field 12 0 4 read-write 0000 Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1- #0000 0001 Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1- #0001 0010 Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3- #0010 0011 Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3- #0011 0100 Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5- #0100 0101 Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5- #0101 0110 Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7- #0110 0111 Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7- #0111 1000 Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1- #1000 1001 Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1- #1001 1010 Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3- #1010 1011 Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3- #1011 1100 Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5- #1100 1101 Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5- #1101 1110 Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7- #1110 1111 Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7- #1111 SAMPLE13 Sample Field 13 4 4 read-write 0000 Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1- #0000 0001 Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1- #0001 0010 Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3- #0010 0011 Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3- #0011 0100 Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5- #0100 0101 Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5- #0101 0110 Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7- #0110 0111 Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7- #0111 1000 Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1- #1000 1001 Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1- #1001 1010 Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3- #1010 1011 Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3- #1011 1100 Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5- #1100 1101 Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5- #1101 1110 Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7- #1110 1111 Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7- #1111 SAMPLE14 Sample Field 14 8 4 read-write 0000 Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1- #0000 0001 Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1- #0001 0010 Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3- #0010 0011 Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3- #0011 0100 Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5- #0100 0101 Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5- #0101 0110 Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7- #0110 0111 Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7- #0111 1000 Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1- #1000 1001 Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1- #1001 1010 Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3- #1010 1011 Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3- #1011 1100 Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5- #1100 1101 Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5- #1101 1110 Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7- #1110 1111 Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7- #1111 SAMPLE15 Sample Field 15 12 4 read-write 0000 Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1- #0000 0001 Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1- #0001 0010 Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3- #0010 0011 Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3- #0011 0100 Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5- #0100 0101 Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5- #0101 0110 Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7- #0110 0111 Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7- #0111 1000 Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1- #1000 1001 Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1- #1001 1010 Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3- #1010 1011 Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3- #1011 1100 Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5- #1100 1101 Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5- #1101 1110 Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7- #1110 1111 Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7- #1111 SDIS ADC Sample Disable Register 0x10 16 read-write 0xF0F0 0xFFFF DS Disable Sample Bits 0 16 read-write 0 SAMPLEx channel is enabled for ADC scan. #0 1 SAMPLEx channel is disabled for ADC scan and corresponding channels after SAMPLEx also doesn not occur in an ADC scan. #1 STAT ADC Status Register 0x12 16 read-write 0 0xFFFF UNDEFINED This read-only bitfield is undefined and will always contain random data. 0 8 read-only HLMTI High Limit Interrupt 8 1 read-only 0 No high limit interrupt request #0 1 High limit exceeded, IRQ pending if CTRL1[HLMTIE] is set #1 LLMTI Low Limit Interrupt 9 1 read-only 0 No low limit interrupt request #0 1 Low limit exceeded, IRQ pending if CTRL1[LLMTIE] is set #1 ZCI Zero Crossing Interrupt 10 1 read-only 0 No zero crossing interrupt request #0 1 Zero crossing encountered, IRQ pending if CTRL1[ZCIE] is set #1 EOSI0 End of Scan Interrupt 11 1 read-write 0 A scan cycle has not been completed, no end of scan IRQ pending #0 1 A scan cycle has been completed, end of scan IRQ pending #1 EOSI1 End of Scan Interrupt 12 1 read-write 0 A scan cycle has not been completed, no end of scan IRQ pending #0 1 A scan cycle has been completed, end of scan IRQ pending #1 CIP1 Conversion in Progress 14 1 read-only 0 Idle state #0 1 A scan cycle is in progress. The ADC will ignore all sync pulses or start commands #1 CIP0 Conversion in Progress 15 1 read-only 0 Idle state #0 1 A scan cycle is in progress. The ADC will ignore all sync pulses or start commands #1 RDY ADC Ready Register 0x14 16 read-only 0 0xFFFF RDY Ready Sample 0 16 read-only 0 Sample not ready or has been read #0 1 Sample ready to be read #1 LOLIMSTAT ADC Low Limit Status Register 0x16 16 read-write 0 0xFFFF LLS Low Limit Status Bits 0 16 read-write HILIMSTAT ADC High Limit Status Register 0x18 16 read-write 0 0xFFFF HLS High Limit Status Bits 0 16 read-write ZXSTAT ADC Zero Crossing Status Register 0x1A 16 read-write 0 0xFFFF ZCS Zero Crossing Status 0 16 read-write 0 Either: A sign change did not occur in a comparison between the current channelx result and the previous channelx result, or Zero crossing control is disabled for channelx in the zero crossing control register, ZXCTRL #0 1 In a comparison between the current channelx result and the previous channelx result, a sign change condition occurred as defined in the zero crossing control register (ZXCTRL) #1 16 0x2 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 RSLT%s ADC Result Registers with sign extension 0x1C 16 read-write 0 0xFFFF RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only 16 0x2 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 LOLIM%s ADC Low Limit Registers 0x3C 16 read-write 0 0xFFFF LLMT Low Limit Bits 3 12 read-write 16 0x2 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 HILIM%s ADC High Limit Registers 0x5C 16 read-write 0x7FF8 0xFFFF HLMT High Limit Bits 3 12 read-write 16 0x2 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 OFFST%s ADC Offset Registers 0x7C 16 read-write 0 0xFFFF OFFSET ADC Offset Bits 3 12 read-write PWR ADC Power Control Register 0x9C 16 read-write 0x1DA7 0xFFFF PD0 Manual Power Down for Converter A 0 1 read-write 0 Power Up ADC converter A #0 1 Power Down ADC converter A #1 PD1 Manual Power Down for Converter B 1 1 read-write 0 Power Up ADC converter B #0 1 Power Down ADC converter B #1 APD Auto Powerdown 3 1 read-write 0 Auto Powerdown Mode is not active #0 1 Auto Powerdown Mode is active #1 PUDELAY Power Up Delay 4 6 read-write PSTS0 ADC Converter A Power Status 10 1 read-only 0 ADC Converter A is currently powered up #0 1 ADC Converter A is currently powered down #1 PSTS1 ADC Converter B Power Status 11 1 read-only 0 ADC Converter B is currently powered up #0 1 ADC Converter B is currently powered down #1 ASB Auto Standby 15 1 read-write 0 Auto standby mode disabled #0 1 Auto standby mode enabled #1 CAL ADC Calibration Register 0x9E 16 read-write 0 0xFFFF SEL_VREFLO_A Select V REFLO Source 12 1 read-write 0 VREFL pad #0 1 ADCA_CH3 #1 SEL_VREFH_A Select V REFH Source 13 1 read-write 0 VREFH pad #0 1 ADCA_CH2 #1 SEL_VREFLO_B Select V REFLO Source 14 1 read-write 0 VREFL pad #0 1 ADCB_CH3 #1 SEL_VREFH_B Select V REFH Source 15 1 read-write 0 VREFH pad #0 1 ADCB_CH2 #1 GC1 Gain Control 1 Register 0xA0 16 read-write 0 0xFFFF GAIN0 Gain Control Bit 0 0 2 read-write 00 x1 amplification #00 01 x2 amplification #01 10 x4 amplification #10 GAIN1 Gain Control Bit 1 2 2 read-write 00 x1 amplification #00 01 x2 amplification #01 10 x4 amplification #10 GAIN2 Gain Control Bit 2 4 2 read-write 00 x1 amplification #00 01 x2 amplification #01 10 x4 amplification #10 GAIN3 Gain Control Bit 3 6 2 read-write 00 x1 amplification #00 01 x2 amplification #01 10 x4 amplification #10 GAIN4 Gain Control Bit 4 8 2 read-write 00 x1 amplification #00 01 x2 amplification #01 10 x4 amplification #10 GAIN5 Gain Control Bit 5 10 2 read-write 00 x1 amplification #00 01 x2 amplification #01 10 x4 amplification #10 GAIN6 Gain Control Bit 6 12 2 read-write 00 x1 amplification #00 01 x2 amplification #01 10 x4 amplification #10 GAIN7 Gain Control Bit 7 14 2 read-write 00 x1 amplification #00 01 x2 amplification #01 10 x4 amplification #10 GC2 Gain Control 2 Register 0xA2 16 read-write 0 0xFFFF GAIN8 Gain Control Bit 8 0 2 read-write 00 x1 amplification #00 01 x2 amplification #01 10 x4 amplification #10 GAIN9 Gain Control Bit 9 2 2 read-write 00 x1 amplification #00 01 x2 amplification #01 10 x4 amplification #10 GAIN10 Gain Control Bit 10 4 2 read-write 00 x1 amplification #00 01 x2 amplification #01 10 x4 amplification #10 GAIN11 Gain Control Bit 11 6 2 read-write 00 x1 amplification #00 01 x2 amplification #01 10 x4 amplification #10 GAIN12 Gain Control Bit 12 8 2 read-write 00 x1 amplification #00 01 x2 amplification #01 10 x4 amplification #10 GAIN13 Gain Control Bit 13 10 2 read-write 00 x1 amplification #00 01 x2 amplification #01 10 x4 amplification #10 GAIN14 Gain Control Bit 14 12 2 read-write 00 x1 amplification #00 01 x2 amplification #01 10 x4 amplification #10 GAIN15 Gain Control Bit 15 14 2 read-write 00 x1 amplification #00 01 x2 amplification #01 10 x4 amplification #10 SCTRL ADC Scan Control Register 0xA4 16 read-write 0 0xFFFF SC Scan Control Bits 0 16 read-write 0 Perform sample immediately after the completion of the current sample. #0 1 Delay sample until a new sync input occurs. #1 PWR2 ADC Power Control Register 0xA6 16 read-write 0x400 0xFFFF SPEEDA ADCA Speed Control Bits 0 2 read-write 00 Conversion clock frequency <= 6.25 MHz; current consumption per converter = 6 mA #00 01 Conversion clock frequency <= 12.5 MHz; current consumption per converter = 10.8 mA #01 10 Conversion clock frequency <= 18.75 MHz; current consumption per converter = 18 mA #10 11 Conversion clock frequency <= 25 MHz; current consumption per converter = 25.2 mA #11 SPEEDB ADCB Speed Control Bits 2 2 read-write 00 Conversion clock frequency <= 6.25 MHz; current consumption per converter = 6 mA #00 01 Conversion clock frequency <= 12.5 MHz; current consumption per converter = 10.8 mA #01 10 Conversion clock frequency <= 18.75 MHz; current consumption per converter = 18 mA #10 11 Conversion clock frequency <= 25 MHz; current consumption per converter = 25.2 mA #11 DIV1 Clock Divisor Select 8 6 read-write CTRL3 ADC Control Register 3 0xA8 16 read-write 0 0xFFFF SCNT0 Sample Window Count 0 0 3 read-write SCNT1 Sample Window Count 1 3 3 read-write DMASRC DMA Trigger Source 6 1 read-write 0 DMA trigger source is end of scan interrupt #0 1 DMA trigger source is RDY bits #1 SCHLTEN ADC Scan Interrupt Enable Register 0xAA 16 read-write 0 0xFFFF SCHLTEN Scan Interrupt Enable 0 16 read-write 0 Scan interrupt is not enabled for this sample. #0 1 Scan interrupt is enabled for this sample. #1 EWM External Watchdog Monitor EWM_ 0x40061000 0 0x4 registers WDOG_EWM 22 CTRL Control Register 0 8 read-write 0 0xFF EWMEN EWM enable. 0 1 read-write ASSIN EWM_in's Assertion State Select. 1 1 read-write INEN Input Enable. 2 1 read-write INTEN Interrupt Enable. 3 1 read-write SERV Service Register 0x1 8 write-only 0 0xFF SERVICE The EWM service mechanism requires the CPU to write two values to the SERV register: a first data byte of 0xB4, followed by a second data byte of 0x2C 0 8 write-only CMPL Compare Low Register 0x2 8 read-write 0 0xFF COMPAREL To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) minimum service time is required 0 8 read-write CMPH Compare High Register 0x3 8 read-write 0xFF 0xFF COMPAREH To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) maximum service time is required 0 8 read-write MCG Multipurpose Clock Generator module MCG_ 0x40064000 0 0xE registers MCG 57 C1 MCG Control 1 Register 0 8 read-write 0x4 0xFF IREFSTEN Internal Reference Stop Enable 0 1 read-write 0 Internal reference clock is disabled in Stop mode. #0 1 Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. #1 IRCLKEN Internal Reference Clock Enable 1 1 read-write 0 MCGIRCLK inactive. #0 1 MCGIRCLK active. #1 IREFS Internal Reference Select 2 1 read-write 0 External reference clock is selected. #0 1 The slow internal reference clock is selected. #1 FRDIV FLL External Reference Divider 3 3 read-write 000 If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. #000 001 If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. #001 010 If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. #010 011 If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. #011 100 If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. #100 101 If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. #101 110 If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . #110 111 If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 . #111 CLKS Clock Source Select 6 2 read-write 00 Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit). #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 11 Encoding 3 - Reserved. #11 C2 MCG Control 2 Register 0x1 8 read-write 0x80 0xFF IRCS Internal Reference Clock Select 0 1 read-write 0 Slow internal reference clock selected. #0 1 Fast internal reference clock selected. #1 LP Low Power Select 1 1 read-write 0 FLL or PLL is not disabled in bypass modes. #0 1 FLL or PLL is disabled in bypass modes (lower power) #1 EREFS External Reference Select 2 1 read-write 0 External reference clock requested. #0 1 Oscillator requested. #1 HGO High Gain Oscillator Select 3 1 read-write 0 Configure crystal oscillator for low-power operation. #0 1 Configure crystal oscillator for high-gain operation. #1 RANGE Frequency Range Select 4 2 read-write 00 Encoding 0 - Low frequency range selected for the crystal oscillator . #00 01 Encoding 1 - High frequency range selected for the crystal oscillator . #01 FCFTRIM Fast Internal Reference Clock Fine Trim 6 1 read-write LOCRE0 Loss of Clock Reset Enable 7 1 read-write 0 Interrupt request is generated on a loss of OSC0 external reference clock. #0 1 Generate a reset request on a loss of OSC0 external reference clock. #1 C3 MCG Control 3 Register 0x2 8 read-write 0 0 SCTRIM Slow Internal Reference Clock Trim Setting 0 8 read-write C4 MCG Control 4 Register 0x3 8 read-write 0 0xE0 SCFTRIM Slow Internal Reference Clock Fine Trim 0 1 read-write FCTRIM Fast Internal Reference Clock Trim Setting 1 4 read-write DRST_DRS DCO Range Select 5 2 read-write 00 Encoding 0 - Low range (reset default). #00 01 Encoding 1 - Mid range. #01 10 Encoding 2 - Mid-high range. #10 11 Encoding 3 - High range. #11 DMX32 DCO Maximum Frequency with 32.768 kHz Reference 7 1 read-write 0 DCO has a default range of 25%. #0 1 DCO is fine-tuned for maximum frequency with 32.768 kHz reference. #1 C5 MCG Control 5 Register 0x4 8 read-write 0 0xFF PRDIV PLL External Reference Divider 0 3 read-write PLLSTEN PLL Stop Enable 5 1 read-write 0 MCGPLLCLK and MCGPLLCLK2X are disabled in any of the Stop modes. #0 1 MCGPLLCLK and MCGPLLCLK2X are enabled if system is in Normal Stop mode. #1 PLLCLKEN PLL Clock Enable 6 1 read-write 0 MCGPLLCLK is inactive. #0 1 MCGPLLCLK is active. #1 C6 MCG Control 6 Register 0x5 8 read-write 0 0xFF VDIV VCO Divider 0 5 read-write CME0 Clock Monitor Enable 5 1 read-write 0 External clock monitor is disabled for OSC0. #0 1 External clock monitor is enabled for OSC0. #1 PLLS PLL Select 6 1 read-write 0 FLL is selected. #0 1 PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 8-16 MHz prior to setting the PLLS bit). #1 LOLIE0 Loss of Lock Interrrupt Enable 7 1 read-write 0 No interrupt request is generated on loss of lock. #0 1 Generate an interrupt request on loss of lock. #1 S MCG Status Register 0x6 8 read-write 0x10 0xFF IRCST Internal Reference Clock Status 0 1 read-only 0 Source of internal reference clock is the slow clock (32 kHz IRC). #0 1 Source of internal reference clock is the fast clock (4 MHz IRC). #1 OSCINIT0 OSC Initialization 1 1 read-only CLKST Clock Mode Status 2 2 read-only 00 Encoding 0 - Output of the FLL is selected (reset default). #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 11 Encoding 3 - Output of the PLL is selected. #11 IREFST Internal Reference Status 4 1 read-only 0 Source of FLL reference clock is the external reference clock. #0 1 Source of FLL reference clock is the internal reference clock. #1 PLLST PLL Select Status 5 1 read-only 0 Source of PLLS clock is FLL clock. #0 1 Source of PLLS clock is PLL output clock. #1 LOCK0 Lock Status 6 1 read-only 0 PLL is currently unlocked. #0 1 PLL is currently locked. #1 LOLS0 Loss of Lock Status 7 1 read-write 0 PLL has not lost lock since LOLS 0 was last cleared. #0 1 PLL has lost lock since LOLS 0 was last cleared. #1 SC MCG Status and Control Register 0x8 8 read-write 0x2 0xFF LOCS0 OSC0 Loss of Clock Status 0 1 read-write 0 Loss of OSC0 has not occurred. #0 1 Loss of OSC0 has occurred. #1 FCRDIV Fast Clock Internal Reference Divider 1 3 read-write 000 Divide Factor is 1 #000 001 Divide Factor is 2. #001 010 Divide Factor is 4. #010 011 Divide Factor is 8. #011 100 Divide Factor is 16 #100 101 Divide Factor is 32 #101 110 Divide Factor is 64 #110 111 Divide Factor is 128. #111 FLTPRSRV FLL Filter Preserve Enable 4 1 read-write 0 FLL filter and FLL frequency will reset on changes to currect clock mode. #0 1 Fll filter and FLL frequency retain their previous values during new clock mode change. #1 ATMF Automatic Trim Machine Fail Flag 5 1 read-write 0 Automatic Trim Machine completed normally. #0 1 Automatic Trim Machine failed. #1 ATMS Automatic Trim Machine Select 6 1 read-write 0 32 kHz Internal Reference Clock selected. #0 1 4 MHz Internal Reference Clock selected. #1 ATME Automatic Trim Machine Enable 7 1 read-write 0 Auto Trim Machine disabled. #0 1 Auto Trim Machine enabled. #1 ATCVH MCG Auto Trim Compare Value High Register 0xA 8 read-write 0 0xFF ATCVH ATM Compare Value High 0 8 read-write ATCVL MCG Auto Trim Compare Value Low Register 0xB 8 read-write 0 0xFF ATCVL ATM Compare Value Low 0 8 read-write C8 MCG Control 8 Register 0xD 8 read-write 0x80 0xFF LOLRE PLL Loss of Lock Reset Enable 6 1 read-write 0 Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request. #0 1 Generate a reset request on a PLL loss of lock indication. #1 OSC Oscillator OSC_ 0x40065000 0 0x3 registers CR OSC Control Register 0 8 read-write 0 0xFF SC16P Oscillator 16 pF Capacitor Load Configure 0 1 read-write 0 Disable the selection. #0 1 Add 16 pF capacitor to the oscillator load. #1 SC8P Oscillator 8 pF Capacitor Load Configure 1 1 read-write 0 Disable the selection. #0 1 Add 8 pF capacitor to the oscillator load. #1 SC4P Oscillator 4 pF Capacitor Load Configure 2 1 read-write 0 Disable the selection. #0 1 Add 4 pF capacitor to the oscillator load. #1 SC2P Oscillator 2 pF Capacitor Load Configure 3 1 read-write 0 Disable the selection. #0 1 Add 2 pF capacitor to the oscillator load. #1 EREFSTEN External Reference Stop Enable 5 1 read-write 0 External reference clock is disabled in Stop mode. #0 1 External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode. #1 ERCLKEN External Reference Enable 7 1 read-write 0 External reference clock is inactive. #0 1 External reference clock is enabled. #1 DIV OSC_DIV 0x2 8 read-write 0 0xFF ERPS ERCLK prescaler 6 2 read-write 00 The divisor ratio is 1. #00 01 The divisor ratio is 2. #01 10 The divisor ratio is 4. #10 11 The divisor ratio is 8. #11 I2C0 Inter-Integrated Circuit I2C0_ 0x40066000 0 0xC registers I2C0 24 A1 I2C Address Register 1 0 8 read-write 0 0xFF AD Address 1 7 read-write F I2C Frequency Divider register 0x1 8 read-write 0 0xFF ICR ClockRate 0 6 read-write MULT Multiplier Factor 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 C1 I2C Control Register 1 0x2 8 read-write 0 0xFF DMAEN DMA Enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 WUEN Wakeup Enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 RSTA Repeat START 2 1 write-only TXAK Transmit Acknowledge Enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). #0 1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). #1 TX Transmit Mode Select 4 1 read-write 0 Receive #0 1 Transmit #1 MST Master Mode Select 5 1 read-write 0 Slave mode #0 1 Master mode #1 IICIE I2C Interrupt Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 IICEN I2C Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 S I2C Status register 0x3 8 read-write 0x80 0xFF RXAK Receive Acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 IICIF Interrupt Flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 SRW Slave Read/Write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 RAM Range Address Match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 ARBL Arbitration Lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus Busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed As A Slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 TCF Transfer Complete Flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 D I2C Data I/O register 0x4 8 read-write 0 0xFF DATA Data 0 8 read-write C2 I2C Control Register 2 0x5 8 read-write 0 0xFF AD Slave Address 0 3 read-write RMEN Range Address Matching Enable 3 1 read-write 0 Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave Baud Rate Control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 HDRS High Drive Select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 ADEXT Address Extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General Call Address Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 FLT I2C Programmable Input Glitch Filter Register 0x6 8 read-write 0 0xFF FLT I2C Programmable Filter Factor 0 4 read-write 0 No filter/bypass #0000 STARTF I2C Bus Start Detect Flag 4 1 read-write 0 No start happens on I2C bus #0 1 Start detected on I2C bus #1 SSIE I2C Bus Stop or Start Interrupt Enable 5 1 read-write 0 Stop or start detection interrupt is disabled #0 1 Stop or start detection interrupt is enabled #1 STOPF I2C Bus Stop Detect Flag 6 1 read-write 0 No stop happens on I2C bus #0 1 Stop detected on I2C bus #1 SHEN Stop Hold Enable 7 1 read-write 0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated. #0 1 Stop holdoff is enabled. #1 RA I2C Range Address register 0x7 8 read-write 0 0xFF RAD Range Slave Address 1 7 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write 0 0xFF SHTF2IE SHTF2 Interrupt Enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SHTF2 SCL High Timeout Flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF1 SCL High Timeout Flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SLTF SCL Low Timeout Flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout Counter Clock Select 4 1 read-write 0 Timeout counter counts at the frequency of the I2C module clock / 64 #0 1 Timeout counter counts at the frequency of the I2C module clock #1 SIICAEN Second I2C Address Enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 ALERTEN SMBus Alert Response Address Enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK Enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. #1 A2 I2C Address Register 2 0x9 8 read-write 0xC2 0xFF SAD SMBus Address 1 7 read-write SLTH I2C SCL Low Timeout Register High 0xA 8 read-write 0 0xFF SSLT SSLT[15:8] 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write 0 0xFF SSLT SSLT[7:0] 0 8 read-write UART0 Serial Communication Interface UART UART0_ 0x4006A000 0 0x17 registers UART0_RX_TX 31 UART0_ERR 32 BDH UART Baud Rate Registers: High 0 8 read-write 0 0xFF SBR UART Baud Rate Bits 0 5 read-write SBNS Stop Bit Number Select 5 1 read-write 0 Data frame consists of a single stop bit. #0 1 Data frame consists of two stop bits. #1 RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 LBKDIE LIN Break Detect Interrupt or DMA Request Enable 7 1 read-write 0 LBKDIF interrupt and DMA transfer requests disabled. #0 1 LBKDIF interrupt or DMA transfer requests enabled. #1 BDL UART Baud Rate Registers: Low 0x1 8 read-write 0x4 0xFF SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write 0 0xFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 C2 UART Control Register 2 0x3 8 read-write 0 0xFF SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 S1 UART Status Register 1 0x4 8 read-only 0xC0 0xFF PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write 0 0xFF RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character detection is disabled. #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 C3 UART Control Register 3 0x6 8 read-write 0 0xFF PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 T8 Transmit Bit 8 6 1 read-write R8 Received Bit 8 7 1 read-only D UART Data Register 0x7 8 read-write 0 0xFF RT Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register 0 8 read-write MA1 UART Match Address Registers 1 0x8 8 read-write 0 0xFF MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write 0 0xFF MA Match Address 0 8 read-write C4 UART Control Register 4 0xA 8 read-write 0 0xFF BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. #1 C5 UART Control Register 5 0xB 8 read-write 0 0xFF LBKDDMAS LIN Break Detect DMA Select Bit 3 1 read-write 0 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service. #0 1 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer. #1 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 ED UART Extended Data Register 0xC 8 read-only 0 0xFF PARITYE The current received dataword contained in D and C3[R8] was received with a parity error. 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 NOISY The current received dataword contained in D and C3[R8] was received with noise. 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 MODEM UART Modem Register 0xD 8 read-write 0 0xFF TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) Ensure that C2[TE] is asserted before assertion of this bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. See Hardware flow control #1 PFIFO UART FIFO Parameters 0x10 8 read-write 0 0xFF RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 CFIFO UART FIFO Control Register 0x11 8 read-write 0 0xFF RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 RXOFE Receive FIFO Overflow Interrupt Enable 2 1 read-write 0 RXOF flag does not generate an interrupt to the host. #0 1 RXOF flag generates an interrupt to the host. #1 RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 SFIFO UART FIFO Status Register 0x12 8 read-write 0xC0 0xFF RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 RXOF Receiver Buffer Overflow Flag 2 1 read-write 0 No receive buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer overflow has occurred since the last time the flag was cleared. #1 RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write 0 0xFF TXWATER Transmit Watermark 0 8 read-write TCFIFO UART FIFO Transmit Count 0x14 8 read-only 0 0xFF TXCOUNT Transmit Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write 0x1 0xFF RXWATER Receive Watermark 0 8 read-write RCFIFO UART FIFO Receive Count 0x16 8 read-only 0 0xFF RXCOUNT Receive Counter 0 8 read-only UART1 Serial Communication Interface UART UART1_ 0x4006B000 0 0x17 registers UART1_RX_TX 33 UART1_ERR 34 BDH UART Baud Rate Registers: High 0 8 read-write 0 0xFF SBR UART Baud Rate Bits 0 5 read-write SBNS Stop Bit Number Select 5 1 read-write 0 Data frame consists of a single stop bit. #0 1 Data frame consists of two stop bits. #1 RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 LBKDIE LIN Break Detect Interrupt or DMA Request Enable 7 1 read-write 0 LBKDIF interrupt and DMA transfer requests disabled. #0 1 LBKDIF interrupt or DMA transfer requests enabled. #1 BDL UART Baud Rate Registers: Low 0x1 8 read-write 0x4 0xFF SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write 0 0xFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 C2 UART Control Register 2 0x3 8 read-write 0 0xFF SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 S1 UART Status Register 1 0x4 8 read-only 0xC0 0xFF PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write 0 0xFF RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character detection is disabled. #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 C3 UART Control Register 3 0x6 8 read-write 0 0xFF PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 T8 Transmit Bit 8 6 1 read-write R8 Received Bit 8 7 1 read-only D UART Data Register 0x7 8 read-write 0 0xFF RT Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register 0 8 read-write MA1 UART Match Address Registers 1 0x8 8 read-write 0 0xFF MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write 0 0xFF MA Match Address 0 8 read-write C4 UART Control Register 4 0xA 8 read-write 0 0xFF BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. #1 C5 UART Control Register 5 0xB 8 read-write 0 0xFF LBKDDMAS LIN Break Detect DMA Select Bit 3 1 read-write 0 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service. #0 1 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer. #1 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 ED UART Extended Data Register 0xC 8 read-only 0 0xFF PARITYE The current received dataword contained in D and C3[R8] was received with a parity error. 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 NOISY The current received dataword contained in D and C3[R8] was received with noise. 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 MODEM UART Modem Register 0xD 8 read-write 0 0xFF TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) Ensure that C2[TE] is asserted before assertion of this bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. See Hardware flow control #1 PFIFO UART FIFO Parameters 0x10 8 read-write 0 0xFF RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 CFIFO UART FIFO Control Register 0x11 8 read-write 0 0xFF RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 RXOFE Receive FIFO Overflow Interrupt Enable 2 1 read-write 0 RXOF flag does not generate an interrupt to the host. #0 1 RXOF flag generates an interrupt to the host. #1 RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 SFIFO UART FIFO Status Register 0x12 8 read-write 0xC0 0xFF RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 RXOF Receiver Buffer Overflow Flag 2 1 read-write 0 No receive buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer overflow has occurred since the last time the flag was cleared. #1 RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write 0 0xFF TXWATER Transmit Watermark 0 8 read-write TCFIFO UART FIFO Transmit Count 0x14 8 read-only 0 0xFF TXCOUNT Transmit Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write 0x1 0xFF RXWATER Receive Watermark 0 8 read-write RCFIFO UART FIFO Receive Count 0x16 8 read-only 0 0xFF RXCOUNT Receive Counter 0 8 read-only CMP0 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP CMP0_ 0x40073000 0 0x6 registers CMP0 40 CR0 CMP Control Register 0 0 8 read-write 0 0xFF HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. #000 001 One sample must agree. The comparator output is simply sampled. #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 CR1 CMP Control Register 1 0x1 8 read-write 0 0xFF EN Comparator Module Enable 0 1 read-write 0 Analog Comparator is disabled. #0 1 Analog Comparator is enabled. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. #0 1 CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. #1 COS Comparator Output Select 2 1 read-write 0 Set the filtered comparator output (CMPO) to equal COUT. #0 1 Set the unfiltered comparator output (CMPO) to equal COUTA. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 PMODE Power Mode Select 4 1 read-write 0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 TRIGM Trigger Mode Enable 5 1 read-write 0 Trigger mode is disabled. #0 1 Trigger mode is enabled. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode is not selected. #0 1 Windowing mode is selected. #1 SE Sample Enable 7 1 read-write 0 Sampling mode is not selected. #0 1 Sampling mode is selected. #1 FPR CMP Filter Period Register 0x2 8 read-write 0 0xFF FILT_PER Filter Sample Period 0 8 read-write SCR CMP Status and Control Register 0x3 8 read-write 0 0xFF COUT Analog Comparator Output 0 1 read-only CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling-edge on COUT has not been detected. #0 1 Falling-edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising-edge on COUT has not been detected. #0 1 Rising-edge on COUT has occurred. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 DMAEN DMA Enable Control 6 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. #1 DACCR DAC Control Register 0x4 8 read-write 0 0xFF VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference. #0 1 Vin2 is selected as resistor ladder network supply reference. #1 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 MUXCR MUX Control Register 0x5 8 read-write 0 0xFF MSEL Minus Input Mux Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input Mux Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 CMP1 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP CMP1_ 0x40073008 0 0x6 registers CMP1 41 CR0 CMP Control Register 0 0 8 read-write 0 0xFF HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. #000 001 One sample must agree. The comparator output is simply sampled. #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 CR1 CMP Control Register 1 0x1 8 read-write 0 0xFF EN Comparator Module Enable 0 1 read-write 0 Analog Comparator is disabled. #0 1 Analog Comparator is enabled. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. #0 1 CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. #1 COS Comparator Output Select 2 1 read-write 0 Set the filtered comparator output (CMPO) to equal COUT. #0 1 Set the unfiltered comparator output (CMPO) to equal COUTA. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 PMODE Power Mode Select 4 1 read-write 0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 TRIGM Trigger Mode Enable 5 1 read-write 0 Trigger mode is disabled. #0 1 Trigger mode is enabled. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode is not selected. #0 1 Windowing mode is selected. #1 SE Sample Enable 7 1 read-write 0 Sampling mode is not selected. #0 1 Sampling mode is selected. #1 FPR CMP Filter Period Register 0x2 8 read-write 0 0xFF FILT_PER Filter Sample Period 0 8 read-write SCR CMP Status and Control Register 0x3 8 read-write 0 0xFF COUT Analog Comparator Output 0 1 read-only CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling-edge on COUT has not been detected. #0 1 Falling-edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising-edge on COUT has not been detected. #0 1 Rising-edge on COUT has occurred. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 DMAEN DMA Enable Control 6 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. #1 DACCR DAC Control Register 0x4 8 read-write 0 0xFF VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference. #0 1 Vin2 is selected as resistor ladder network supply reference. #1 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 MUXCR MUX Control Register 0x5 8 read-write 0 0xFF MSEL Minus Input Mux Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input Mux Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 CMP2 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP CMP2_ 0x40073010 0 0x6 registers CMP2 70 CR0 CMP Control Register 0 0 8 read-write 0 0xFF HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. #000 001 One sample must agree. The comparator output is simply sampled. #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 CR1 CMP Control Register 1 0x1 8 read-write 0 0xFF EN Comparator Module Enable 0 1 read-write 0 Analog Comparator is disabled. #0 1 Analog Comparator is enabled. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. #0 1 CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. #1 COS Comparator Output Select 2 1 read-write 0 Set the filtered comparator output (CMPO) to equal COUT. #0 1 Set the unfiltered comparator output (CMPO) to equal COUTA. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 PMODE Power Mode Select 4 1 read-write 0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 TRIGM Trigger Mode Enable 5 1 read-write 0 Trigger mode is disabled. #0 1 Trigger mode is enabled. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode is not selected. #0 1 Windowing mode is selected. #1 SE Sample Enable 7 1 read-write 0 Sampling mode is not selected. #0 1 Sampling mode is selected. #1 FPR CMP Filter Period Register 0x2 8 read-write 0 0xFF FILT_PER Filter Sample Period 0 8 read-write SCR CMP Status and Control Register 0x3 8 read-write 0 0xFF COUT Analog Comparator Output 0 1 read-only CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling-edge on COUT has not been detected. #0 1 Falling-edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising-edge on COUT has not been detected. #0 1 Rising-edge on COUT has occurred. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 DMAEN DMA Enable Control 6 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. #1 DACCR DAC Control Register 0x4 8 read-write 0 0xFF VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference. #0 1 Vin2 is selected as resistor ladder network supply reference. #1 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 MUXCR MUX Control Register 0x5 8 read-write 0 0xFF MSEL Minus Input Mux Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input Mux Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 CMP3 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP CMP3_ 0x40073018 0 0x6 registers CMP3 92 CR0 CMP Control Register 0 0 8 read-write 0 0xFF HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. #000 001 One sample must agree. The comparator output is simply sampled. #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 CR1 CMP Control Register 1 0x1 8 read-write 0 0xFF EN Comparator Module Enable 0 1 read-write 0 Analog Comparator is disabled. #0 1 Analog Comparator is enabled. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. #0 1 CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. #1 COS Comparator Output Select 2 1 read-write 0 Set the filtered comparator output (CMPO) to equal COUT. #0 1 Set the unfiltered comparator output (CMPO) to equal COUTA. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 PMODE Power Mode Select 4 1 read-write 0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 TRIGM Trigger Mode Enable 5 1 read-write 0 Trigger mode is disabled. #0 1 Trigger mode is enabled. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode is not selected. #0 1 Windowing mode is selected. #1 SE Sample Enable 7 1 read-write 0 Sampling mode is not selected. #0 1 Sampling mode is selected. #1 FPR CMP Filter Period Register 0x2 8 read-write 0 0xFF FILT_PER Filter Sample Period 0 8 read-write SCR CMP Status and Control Register 0x3 8 read-write 0 0xFF COUT Analog Comparator Output 0 1 read-only CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling-edge on COUT has not been detected. #0 1 Falling-edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising-edge on COUT has not been detected. #0 1 Rising-edge on COUT has occurred. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 DMAEN DMA Enable Control 6 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. #1 DACCR DAC Control Register 0x4 8 read-write 0 0xFF VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference. #0 1 Vin2 is selected as resistor ladder network supply reference. #1 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 MUXCR MUX Control Register 0x5 8 read-write 0 0xFF MSEL Minus Input Mux Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input Mux Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 LLWU Low leakage wakeup unit LLWU_ 0x4007C000 0 0x10 registers LLWU 21 PE1 LLWU Pin Enable 1 register 0 8 read-write 0 0xFF WUPE0 Wakeup Pin Enable For LLWU_P0 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE1 Wakeup Pin Enable For LLWU_P1 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE2 Wakeup Pin Enable For LLWU_P2 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE3 Wakeup Pin Enable For LLWU_P3 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE2 LLWU Pin Enable 2 register 0x1 8 read-write 0 0xFF WUPE4 Wakeup Pin Enable For LLWU_P4 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE5 Wakeup Pin Enable For LLWU_P5 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE6 Wakeup Pin Enable For LLWU_P6 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE7 Wakeup Pin Enable For LLWU_P7 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE3 LLWU Pin Enable 3 register 0x2 8 read-write 0 0xFF WUPE8 Wakeup Pin Enable For LLWU_P8 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE9 Wakeup Pin Enable For LLWU_P9 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE10 Wakeup Pin Enable For LLWU_P10 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE11 Wakeup Pin Enable For LLWU_P11 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE4 LLWU Pin Enable 4 register 0x3 8 read-write 0 0xFF WUPE12 Wakeup Pin Enable For LLWU_P12 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE13 Wakeup Pin Enable For LLWU_P13 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE14 Wakeup Pin Enable For LLWU_P14 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE15 Wakeup Pin Enable For LLWU_P15 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE5 LLWU Pin Enable 5 register 0x4 8 read-write 0 0xFF WUPE16 Wakeup Pin Enable For LLWU_P16 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE17 Wakeup Pin Enable For LLWU_P17 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE18 Wakeup Pin Enable For LLWU_P18 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE19 Wakeup Pin Enable For LLWU_P19 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE6 LLWU Pin Enable 6 register 0x5 8 read-write 0 0xFF WUPE20 Wakeup Pin Enable For LLWU_P20 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE21 Wakeup Pin Enable For LLWU_P21 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE22 Wakeup Pin Enable For LLWU_P22 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE23 Wakeup Pin Enable For LLWU_P23 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE7 LLWU Pin Enable 7 register 0x6 8 read-write 0 0xFF WUPE24 Wakeup Pin Enable For LLWU_P24 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE25 Wakeup Pin Enable For LLWU_P25 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE26 Wakeup Pin Enable For LLWU_P26 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE27 Wakeup Pin Enable For LLWU_P27 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE8 LLWU Pin Enable 8 register 0x7 8 read-write 0 0xFF WUPE28 Wakeup Pin Enable For LLWU_P28 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE29 Wakeup Pin Enable For LLWU_P29 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE30 Wakeup Pin Enable For LLWU_P30 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE31 Wakeup Pin Enable For LLWU_P31 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 ME LLWU Module Enable register 0x8 8 read-write 0 0xFF WUME0 Wakeup Module Enable For Module 0 0 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME1 Wakeup Module Enable for Module 1 1 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME2 Wakeup Module Enable For Module 2 2 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME3 Wakeup Module Enable For Module 3 3 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME4 Wakeup Module Enable For Module 4 4 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME5 Wakeup Module Enable For Module 5 5 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME6 Wakeup Module Enable For Module 6 6 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME7 Wakeup Module Enable For Module 7 7 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 PF1 LLWU Pin Flag 1 register 0x9 8 read-write 0 0xFF WUF0 Wakeup Flag For LLWU_P0 0 1 read-write 0 LLWU_P0 input was not a wakeup source #0 1 LLWU_P0 input was a wakeup source #1 WUF1 Wakeup Flag For LLWU_P1 1 1 read-write 0 LLWU_P1 input was not a wakeup source #0 1 LLWU_P1 input was a wakeup source #1 WUF2 Wakeup Flag For LLWU_P2 2 1 read-write 0 LLWU_P2 input was not a wakeup source #0 1 LLWU_P2 input was a wakeup source #1 WUF3 Wakeup Flag For LLWU_P3 3 1 read-write 0 LLWU_P3 input was not a wakeup source #0 1 LLWU_P3 input was a wakeup source #1 WUF4 Wakeup Flag For LLWU_P4 4 1 read-write 0 LLWU_P4 input was not a wakeup source #0 1 LLWU_P4 input was a wakeup source #1 WUF5 Wakeup Flag For LLWU_P5 5 1 read-write 0 LLWU_P5 input was not a wakeup source #0 1 LLWU_P5 input was a wakeup source #1 WUF6 Wakeup Flag For LLWU_P6 6 1 read-write 0 LLWU_P6 input was not a wakeup source #0 1 LLWU_P6 input was a wakeup source #1 WUF7 Wakeup Flag For LLWU_P7 7 1 read-write 0 LLWU_P7 input was not a wakeup source #0 1 LLWU_P7 input was a wakeup source #1 PF2 LLWU Pin Flag 2 register 0xA 8 read-write 0 0xFF WUF8 Wakeup Flag For LLWU_P8 0 1 read-write 0 LLWU_P8 input was not a wakeup source #0 1 LLWU_P8 input was a wakeup source #1 WUF9 Wakeup Flag For LLWU_P9 1 1 read-write 0 LLWU_P9 input was not a wakeup source #0 1 LLWU_P9 input was a wakeup source #1 WUF10 Wakeup Flag For LLWU_P10 2 1 read-write 0 LLWU_P10 input was not a wakeup source #0 1 LLWU_P10 input was a wakeup source #1 WUF11 Wakeup Flag For LLWU_P11 3 1 read-write 0 LLWU_P11 input was not a wakeup source #0 1 LLWU_P11 input was a wakeup source #1 WUF12 Wakeup Flag For LLWU_P12 4 1 read-write 0 LLWU_P12 input was not a wakeup source #0 1 LLWU_P12 input was a wakeup source #1 WUF13 Wakeup Flag For LLWU_P13 5 1 read-write 0 LLWU_P13 input was not a wakeup source #0 1 LLWU_P13 input was a wakeup source #1 WUF14 Wakeup Flag For LLWU_P14 6 1 read-write 0 LLWU_P14 input was not a wakeup source #0 1 LLWU_P14 input was a wakeup source #1 WUF15 Wakeup Flag For LLWU_P15 7 1 read-write 0 LLWU_P15 input was not a wakeup source #0 1 LLWU_P15 input was a wakeup source #1 PF3 LLWU Pin Flag 3 register 0xB 8 read-write 0 0xFF WUF16 Wakeup Flag For LLWU_P16 0 1 read-write 0 LLWU_P16 input was not a wakeup source #0 1 LLWU_P16 input was a wakeup source #1 WUF17 Wakeup Flag For LLWU_P17 1 1 read-write 0 LLWU_P17 input was not a wakeup source #0 1 LLWU_P17 input was a wakeup source #1 WUF18 Wakeup Flag For LLWU_P18 2 1 read-write 0 LLWU_P18 input was not a wakeup source #0 1 LLWU_P18 input was a wakeup source #1 WUF19 Wakeup Flag For LLWU_P19 3 1 read-write 0 LLWU_P19 input was not a wakeup source #0 1 LLWU_P19 input was a wakeup source #1 WUF20 Wakeup Flag For LLWU_P20 4 1 read-write 0 LLWU_P20 input was not a wakeup source #0 1 LLWU_P20 input was a wakeup source #1 WUF21 Wakeup Flag For LLWU_P21 5 1 read-write 0 LLWU_P21 input was not a wakeup source #0 1 LLWU_P21 input was a wakeup source #1 WUF22 Wakeup Flag For LLWU_P22 6 1 read-write 0 LLWU_P22 input was not a wakeup source #0 1 LLWU_P22 input was a wakeup source #1 WUF23 Wakeup Flag For LLWU_P23 7 1 read-write 0 LLWU_P23 input was not a wakeup source #0 1 LLWU_P23 input was a wakeup source #1 PF4 LLWU Pin Flag 4 register 0xC 8 read-write 0 0xFF WUF24 Wakeup Flag For LLWU_P24 0 1 read-write 0 LLWU_P24 input was not a wakeup source #0 1 LLWU_P24 input was a wakeup source #1 WUF25 Wakeup Flag For LLWU_P25 1 1 read-write 0 LLWU_P25 input was not a wakeup source #0 1 LLWU_P25 input was a wakeup source #1 WUF26 Wakeup Flag For LLWU_P26 2 1 read-write 0 LLWU_P26 input was not a wakeup source #0 1 LLWU_P26 input was a wakeup source #1 WUF27 Wakeup Flag For LLWU_P27 3 1 read-write 0 LLWU_P27 input was not a wakeup source #0 1 LLWU_P27 input was a wakeup source #1 WUF28 Wakeup Flag For LLWU_P28 4 1 read-write 0 LLWU_P28 input was not a wakeup source #0 1 LLWU_P28 input was a wakeup source #1 WUF29 Wakeup Flag For LLWU_P29 5 1 read-write 0 LLWU_P29 input was not a wakeup source #0 1 LLWU_P29 input was a wakeup source #1 WUF30 Wakeup Flag For LLWU_P30 6 1 read-write 0 LLWU_P30 input was not a wakeup source #0 1 LLWU_P30 input was a wakeup source #1 WUF31 Wakeup Flag For LLWU_P31 7 1 read-write 0 LLWU_P31 input was not a wakeup source #0 1 LLWU_P31 input was a wakeup source #1 MF5 LLWU Module Flag 5 register 0xD 8 read-only 0 0xFF MWUF0 Wakeup flag For module 0 0 1 read-only 0 Module 0 input was not a wakeup source #0 1 Module 0 input was a wakeup source #1 MWUF1 Wakeup flag For module 1 1 1 read-only 0 Module 1 input was not a wakeup source #0 1 Module 1 input was a wakeup source #1 MWUF2 Wakeup flag For module 2 2 1 read-only 0 Module 2 input was not a wakeup source #0 1 Module 2 input was a wakeup source #1 MWUF3 Wakeup flag For module 3 3 1 read-only 0 Module 3 input was not a wakeup source #0 1 Module 3 input was a wakeup source #1 MWUF4 Wakeup flag For module 4 4 1 read-only 0 Module 4 input was not a wakeup source #0 1 Module 4 input was a wakeup source #1 MWUF5 Wakeup flag For module 5 5 1 read-only 0 Module 5 input was not a wakeup source #0 1 Module 5 input was a wakeup source #1 MWUF6 Wakeup flag For module 6 6 1 read-only 0 Module 6 input was not a wakeup source #0 1 Module 6 input was a wakeup source #1 MWUF7 Wakeup flag For module 7 7 1 read-only 0 Module 7 input was not a wakeup source #0 1 Module 7 input was a wakeup source #1 FILT1 LLWU Pin Filter 1 register 0xE 8 read-write 0 0xFF FILTSEL Filter Pin Select 0 5 read-write 00000 Select LLWU_P0 for filter #00000 11111 Select LLWU_P31 for filter #11111 FILTE Digital Filter On External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 1 was not a wakeup source #0 1 Pin Filter 1 was a wakeup source #1 FILT2 LLWU Pin Filter 2 register 0xF 8 read-write 0 0xFF FILTSEL Filter Pin Select 0 5 read-write 00000 Select LLWU_P0 for filter #00000 11111 Select LLWU_P31 for filter #11111 FILTE Digital Filter On External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 2 was not a wakeup source #0 1 Pin Filter 2 was a wakeup source #1 PMC Power Management Controller PMC_ 0x4007D000 0 0x3 registers PMC 20 LVDSC1 Low Voltage Detect Status And Control 1 register 0 8 read-write 0x10 0xFF LVDV Low-Voltage Detect Voltage Select 0 2 read-write 00 Low trip point selected (V LVD = V LVDL ) #00 01 High trip point selected (V LVD = V LVDH ) #01 LVDRE Low-Voltage Detect Reset Enable 4 1 read-write 0 LVDF does not generate hardware resets #0 1 Force an MCU reset when LVDF = 1 #1 LVDIE Low-Voltage Detect Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVDF = 1 #1 LVDACK Low-Voltage Detect Acknowledge 6 1 write-only LVDF Low-Voltage Detect Flag 7 1 read-only 0 Low-voltage event not detected #0 1 Low-voltage event detected #1 LVDSC2 Low Voltage Detect Status And Control 2 register 0x1 8 read-write 0 0xFF LVWV Low-Voltage Warning Voltage Select 0 2 read-write 00 Low trip point selected (VLVW = VLVW1) #00 01 Mid 1 trip point selected (VLVW = VLVW2) #01 10 Mid 2 trip point selected (VLVW = VLVW3) #10 11 High trip point selected (VLVW = VLVW4) #11 LVWIE Low-Voltage Warning Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVWF = 1 #1 LVWACK Low-Voltage Warning Acknowledge 6 1 write-only LVWF Low-Voltage Warning Flag 7 1 read-only 0 Low-voltage warning event not detected #0 1 Low-voltage warning event detected #1 REGSC Regulator Status And Control register 0x2 8 read-write 0x4 0xFF BGBE Bandgap Buffer Enable 0 1 read-write 0 Bandgap buffer not enabled #0 1 Bandgap buffer enabled #1 BGBDS Bandgap Buffer Drive Select 1 1 read-write 0 Low drive #0 1 High drive #1 REGONS Regulator In Run Regulation Status 2 1 read-only 0 Regulator is in stop regulation or in transition to/from it #0 1 Regulator is in run regulation #1 ACKISO Acknowledge Isolation 3 1 read-write 0 Peripherals and I/O pads are in normal run state. #0 1 Certain peripherals and I/O pads are in an isolated and latched state. #1 BGEN Bandgap Enable In VLPx Operation 4 1 read-write 0 Bandgap voltage reference is disabled in VLPx , and VLLSx modes. #0 1 Bandgap voltage reference is enabled in VLPx , and VLLSx modes. #1 SMC System Mode Controller SMC_ 0x4007E000 0 0x4 registers PMPROT Power Mode Protection register 0 8 read-write 0 0xFF AVLLS Allow Very-Low-Leakage Stop Mode 1 1 read-write 0 Any VLLSx mode is not allowed #0 1 Any VLLSx mode is allowed #1 AVLP Allow Very-Low-Power Modes 5 1 read-write 0 VLPR, VLPW, and VLPS are not allowed. #0 1 VLPR, VLPW, and VLPS are allowed. #1 AHSRUN Allow High Speed Run mode 7 1 read-write 0 HSRUN is not allowed #0 1 HSRUN is allowed #1 PMCTRL Power Mode Control register 0x1 8 read-write 0 0xFF STOPM Stop Mode Control 0 3 read-write 000 Normal Stop (STOP) #000 010 Very-Low-Power Stop (VLPS) #010 100 Very-Low-Leakage Stop (VLLSx) #100 110 Reseved #110 STOPA Stop Aborted 3 1 read-only 0 The previous stop mode entry was successsful. #0 1 The previous stop mode entry was aborted. #1 RUNM Run Mode Control 5 2 read-write 00 Normal Run mode (RUN) #00 10 Very-Low-Power Run mode (VLPR) #10 11 High Speed Run mode (HSRUN) #11 STOPCTRL Stop Control Register 0x2 8 read-write 0x3 0xFF VLLSM VLLS Mode Control 0 3 read-write 000 VLLS0 #000 001 VLLS1 #001 010 VLLS2 #010 011 VLLS3 #011 LPOPO LPO Power Option 3 1 read-write 0 LPO clock is enabled in VLLSx #0 1 LPO clock is disabled in VLLSx #1 RAM2PO RAM2 Power Option 4 1 read-write 0 RAM2 not powered in VLLS2 #0 1 RAM2 powered in VLLS2 #1 PORPO POR Power Option 5 1 read-write 0 POR detect circuit is enabled in VLLS0 #0 1 POR detect circuit is disabled in VLLS0 #1 PSTOPO Partial Stop Option 6 2 read-write 00 STOP - Normal Stop mode #00 01 PSTOP1 - Partial Stop with both system and bus clocks disabled #01 10 PSTOP2 - Partial Stop with system clock disabled and bus clock enabled #10 PMSTAT Power Mode Status register 0x3 8 read-only 0x1 0xFF PMSTAT Power Mode Status 0 8 read-only RCM Reset Control Module RCM_ 0x4007F000 0 0xA registers SRS0 System Reset Status Register 0 0 8 read-only 0x82 0xFF WAKEUP Low Leakage Wakeup Reset 0 1 read-only 0 Reset not caused by LLWU module wakeup source #0 1 Reset caused by LLWU module wakeup source #1 LVD Low-Voltage Detect Reset 1 1 read-only 0 Reset not caused by LVD trip or POR #0 1 Reset caused by LVD trip or POR #1 LOC Loss-of-Clock Reset 2 1 read-only 0 Reset not caused by a loss of external clock. #0 1 Reset caused by a loss of external clock. #1 LOL Loss-of-Lock Reset 3 1 read-only 0 Reset not caused by a loss of lock in the PLL #0 1 Reset caused by a loss of lock in the PLL #1 WDOG Watchdog 5 1 read-only 0 Reset not caused by watchdog timeout #0 1 Reset caused by watchdog timeout #1 PIN External Reset Pin 6 1 read-only 0 Reset not caused by external reset pin #0 1 Reset caused by external reset pin #1 POR Power-On Reset 7 1 read-only 0 Reset not caused by POR #0 1 Reset caused by POR #1 SRS1 System Reset Status Register 1 0x1 8 read-only 0 0xFF LOCKUP Core Lockup 1 1 read-only 0 Reset not caused by core LOCKUP event #0 1 Reset caused by core LOCKUP event #1 SW Software 2 1 read-only 0 Reset not caused by software setting of SYSRESETREQ bit #0 1 Reset caused by software setting of SYSRESETREQ bit #1 MDM_AP MDM-AP System Reset Request 3 1 read-only 0 Reset not caused by host debugger system setting of the System Reset Request bit #0 1 Reset caused by host debugger system setting of the System Reset Request bit #1 SACKERR Stop Mode Acknowledge Error Reset 5 1 read-only 0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode #0 1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode #1 RPFC Reset Pin Filter Control register 0x4 8 read-write 0 0xFF RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes 0 2 read-write 00 All filtering disabled #00 01 Bus clock filter enabled for normal operation #01 10 LPO clock filter enabled for normal operation #10 RSTFLTSS Reset Pin Filter Select in Stop Mode 2 1 read-write 0 All filtering disabled #0 1 LPO clock filter enabled #1 RPFW Reset Pin Filter Width register 0x5 8 read-write 0 0xFF RSTFLTSEL Reset Pin Filter Bus Clock Select 0 5 read-write 00000 Bus clock filter count is 1 #00000 00001 Bus clock filter count is 2 #00001 00010 Bus clock filter count is 3 #00010 00011 Bus clock filter count is 4 #00011 00100 Bus clock filter count is 5 #00100 00101 Bus clock filter count is 6 #00101 00110 Bus clock filter count is 7 #00110 00111 Bus clock filter count is 8 #00111 01000 Bus clock filter count is 9 #01000 01001 Bus clock filter count is 10 #01001 01010 Bus clock filter count is 11 #01010 01011 Bus clock filter count is 12 #01011 01100 Bus clock filter count is 13 #01100 01101 Bus clock filter count is 14 #01101 01110 Bus clock filter count is 15 #01110 01111 Bus clock filter count is 16 #01111 10000 Bus clock filter count is 17 #10000 10001 Bus clock filter count is 18 #10001 10010 Bus clock filter count is 19 #10010 10011 Bus clock filter count is 20 #10011 10100 Bus clock filter count is 21 #10100 10101 Bus clock filter count is 22 #10101 10110 Bus clock filter count is 23 #10110 10111 Bus clock filter count is 24 #10111 11000 Bus clock filter count is 25 #11000 11001 Bus clock filter count is 26 #11001 11010 Bus clock filter count is 27 #11010 11011 Bus clock filter count is 28 #11011 11100 Bus clock filter count is 29 #11100 11101 Bus clock filter count is 30 #11101 11110 Bus clock filter count is 31 #11110 11111 Bus clock filter count is 32 #11111 SSRS0 Sticky System Reset Status Register 0 0x8 8 read-write 0x82 0xFF SWAKEUP Sticky Low Leakage Wakeup Reset 0 1 read-write 0 Reset not caused by LLWU module wakeup source #0 1 Reset caused by LLWU module wakeup source #1 SLVD Sticky Low-Voltage Detect Reset 1 1 read-write 0 Reset not caused by LVD trip or POR #0 1 Reset caused by LVD trip or POR #1 SLOC Sticky Loss-of-Clock Reset 2 1 read-write 0 Reset not caused by a loss of external clock. #0 1 Reset caused by a loss of external clock. #1 SLOL Sticky Loss-of-Lock Reset 3 1 read-write 0 Reset not caused by a loss of lock in the PLL #0 1 Reset caused by a loss of lock in the PLL #1 SWDOG Sticky Watchdog 5 1 read-write 0 Reset not caused by watchdog timeout #0 1 Reset caused by watchdog timeout #1 SPIN Sticky External Reset Pin 6 1 read-write 0 Reset not caused by external reset pin #0 1 Reset caused by external reset pin #1 SPOR Sticky Power-On Reset 7 1 read-write 0 Reset not caused by POR #0 1 Reset caused by POR #1 SSRS1 Sticky System Reset Status Register 1 0x9 8 read-write 0 0xFF SLOCKUP Sticky Core Lockup 1 1 read-write 0 Reset not caused by core LOCKUP event #0 1 Reset caused by core LOCKUP event #1 SSW Sticky Software 2 1 read-write 0 Reset not caused by software setting of SYSRESETREQ bit #0 1 Reset caused by software setting of SYSRESETREQ bit #1 SMDM_AP Sticky MDM-AP System Reset Request 3 1 read-write 0 Reset not caused by host debugger system setting of the System Reset Request bit #0 1 Reset caused by host debugger system setting of the System Reset Request bit #1 SSACKERR Sticky Stop Mode Acknowledge Error Reset 5 1 read-write 0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode #0 1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode #1 GPIOA General Purpose Input/Output GPIO GPIOA_ 0x400FF000 0 0x18 registers PORTA 59 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOB General Purpose Input/Output GPIO GPIOB_ 0x400FF040 0 0x18 registers PORTB 60 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOC General Purpose Input/Output GPIO GPIOC_ 0x400FF080 0 0x18 registers PORTC 61 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOD General Purpose Input/Output GPIO GPIOD_ 0x400FF0C0 0 0x18 registers PORTD 62 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOE General Purpose Input/Output GPIO GPIOE_ 0x400FF100 0 0x18 registers PORTE 63 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 MCM Core Platform Miscellaneous Control Module MCM_ 0xE0080000 0x8 0x3C registers MCM 17 PLASC Crossbar Switch (AXBS) Slave Configuration 0x8 16 read-only 0xF 0xFFFF ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0 8 read-only 0 A bus slave connection to AXBS input port n is absent #0 1 A bus slave connection to AXBS input port n is present #1 PLAMC Crossbar Switch (AXBS) Master Configuration 0xA 16 read-only 0x7 0xFFFF AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 8 read-only 0 A bus master connection to AXBS input port n is absent #0 1 A bus master connection to AXBS input port n is present #1 CR Control Register 0xC 32 read-write 0xF0 0xFFFFFFFF SRAMUAP SRAM_U arbitration priority 24 2 read-write 00 Round robin #00 01 Special round robin (favors SRAM backoor accesses over the processor) #01 10 Fixed priority. Processor has highest, backdoor has lowest #10 11 Fixed priority. Backdoor has highest, processor has lowest #11 SRAMUWP SRAM_U write protect 26 1 read-write SRAMLAP SRAM_L arbitration priority 28 2 read-write 00 Round robin #00 01 Special round robin (favors SRAM backoor accesses over the processor) #01 10 Fixed priority. Processor has highest, backdoor has lowest #10 11 Fixed priority. Backdoor has highest, processor has lowest #11 SRAMLWP SRAM_L Write Protect 30 1 read-write ISCR Interrupt Status and Control Register 0x10 32 read-write 0x20000 0xFFFFFFFF FIOC FPU invalid operation interrupt status 8 1 read-only 0 No interrupt #0 1 Interrupt occurred #1 FDZC FPU divide-by-zero interrupt status 9 1 read-only 0 No interrupt #0 1 Interrupt occurred #1 FOFC FPU overflow interrupt status 10 1 read-only 0 No interrupt #0 1 Interrupt occurred #1 FUFC FPU underflow interrupt status 11 1 read-only 0 No interrupt #0 1 Interrupt occurred #1 FIXC FPU inexact interrupt status 12 1 read-only 0 No interrupt #0 1 Interrupt occurred #1 FIDC FPU input denormal interrupt status 15 1 read-only 0 No interrupt #0 1 Interrupt occurred #1 FIOCE FPU invalid operation interrupt enable 24 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FDZCE FPU divide-by-zero interrupt enable 25 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FOFCE FPU overflow interrupt enable 26 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FUFCE FPU underflow interrupt enable 27 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FIXCE FPU inexact interrupt enable 28 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FIDCE FPU input denormal interrupt enable 31 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 CPO Compute Operation Control Register 0x40 32 read-write 0 0xFFFFFFFF CPOREQ Compute Operation request 0 1 read-write 0 Request is cleared. #0 1 Request Compute Operation. #1 CPOACK Compute Operation acknowledge 1 1 read-only 0 Compute operation entry has not completed or compute operation exit has completed. #0 1 Compute operation entry has completed or compute operation exit has not completed. #1 CPOWOI Compute Operation wakeup on interrupt 2 1 read-write 0 No effect. #0 1 When set, the CPOREQ is cleared on any interrupt or exception vector fetch. #1