MKE15D7 1.6 MKE15D7 Freescale Microcontroller 8 32 FTMRA_FlashConfig Flash configuration field NV_ 0x400 0 0x10 registers BACKKEY3 Backdoor Comparison Key 3. 0 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY2 Backdoor Comparison Key 2. 0x1 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY1 Backdoor Comparison Key 1. 0x2 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY0 Backdoor Comparison Key 0. 0x3 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY7 Backdoor Comparison Key 7. 0x4 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY6 Backdoor Comparison Key 6. 0x5 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY5 Backdoor Comparison Key 5. 0x6 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY4 Backdoor Comparison Key 4. 0x7 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only FSEC Non-volatile Flash Security Register 0xC 8 read-only 0xFF 0xFF SEC Flash Security 0 2 read-only RESERVED no description available 2 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 5 1 read-only KEYEN Backdoor Key Security Enable 6 2 read-only FOPT Non-volatile Flash Option Register 0xD 8 read-only 0xFF 0xFF RESERVED no description available 0 1 read-only RESERVED no description available 1 1 read-only RESERVED no description available 2 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 5 1 read-only RESERVED no description available 6 1 read-only RESERVED no description available 7 1 read-only FPROT Non-volatile P-Flash Protection Register 0xE 8 read-only 0xFF 0xFF FPLS no description available 0 2 read-only FPLDIS no description available 2 1 read-only FPHS no description available 3 2 read-only FPHDIS no description available 5 1 read-only RESERVED no description available 6 1 read-only FPOPEN no description available 7 1 read-only DFPROT Non-volatile D-Flash Protection Register 0xF 8 read-only 0xFF 0xFF DPS no description available 0 5 read-only RESERVED no description available 5 1 read-only RESERVED no description available 6 1 read-only DPOPEN no description available 7 1 read-only AIPS AIPS-Lite Bridge AIPS_ 0x40000000 0 0x84 registers MPRA Master Privilege Register A 0 32 read-write 0x77700000 0xFFFFFFFF RESERVED no description available 0 4 read-only RESERVED no description available 4 4 read-only RESERVED no description available 8 4 read-only RESERVED no description available 12 4 read-only RESERVED no description available 16 4 read-only MPL2 Master Privilege Level 20 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTW2 Master Trusted For Writes 21 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTR2 Master Trusted For Read 22 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 RESERVED no description available 23 1 read-only MPL1 Master privilege level 24 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTW1 Master trusted for writes 25 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTR1 Master trusted for read 26 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 RESERVED no description available 27 1 read-only MPL0 Master Privilege Level 28 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTW0 Master Trusted For Writes 29 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTR0 Master Trusted For Read 30 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 RESERVED no description available 31 1 read-only PACRA Peripheral Access Control Register 0x20 32 read-write 0x44444444 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 3 1 read-only TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 7 1 read-only TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 11 1 read-only TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 15 1 read-only TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 19 1 read-only TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 23 1 read-only TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 27 1 read-only TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 31 1 read-only PACRB Peripheral Access Control Register 0x24 32 read-write 0x44444444 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 3 1 read-only TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 7 1 read-only TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 11 1 read-only TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 15 1 read-only TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 19 1 read-only TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 23 1 read-only TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 27 1 read-only TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 31 1 read-only PACRC Peripheral Access Control Register 0x28 32 read-write 0x44444444 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 3 1 read-only TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 7 1 read-only TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 11 1 read-only TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 15 1 read-only TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 19 1 read-only TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 23 1 read-only TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 27 1 read-only TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 31 1 read-only PACRD Peripheral Access Control Register 0x2C 32 read-write 0x44444444 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 3 1 read-only TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 7 1 read-only TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 11 1 read-only TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 15 1 read-only TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 19 1 read-only TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 23 1 read-only TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 27 1 read-only TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 31 1 read-only PACRE Peripheral Access Control Register 0x40 32 read-write 0 0 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 3 1 read-only TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 7 1 read-only TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 11 1 read-only TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 15 1 read-only TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 19 1 read-only TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 23 1 read-only TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 27 1 read-only TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 31 1 read-only PACRF Peripheral Access Control Register 0x44 32 read-write 0 0 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 3 1 read-only TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 7 1 read-only TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 11 1 read-only TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 15 1 read-only TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 19 1 read-only TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 23 1 read-only TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 27 1 read-only TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 31 1 read-only PACRG Peripheral Access Control Register 0x48 32 read-write 0 0 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 3 1 read-only TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 7 1 read-only TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 11 1 read-only TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 15 1 read-only TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 19 1 read-only TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 23 1 read-only TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 27 1 read-only TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 31 1 read-only PACRH Peripheral Access Control Register 0x4C 32 read-write 0 0 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 3 1 read-only TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 7 1 read-only TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 11 1 read-only TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 15 1 read-only TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 19 1 read-only TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 23 1 read-only TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 27 1 read-only TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 31 1 read-only PACRI Peripheral Access Control Register 0x50 32 read-write 0 0 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 3 1 read-only TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 7 1 read-only TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 11 1 read-only TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 15 1 read-only TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 19 1 read-only TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 23 1 read-only TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 27 1 read-only TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 31 1 read-only PACRJ Peripheral Access Control Register 0x54 32 read-write 0 0 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 3 1 read-only TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 7 1 read-only TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 11 1 read-only TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 15 1 read-only TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 19 1 read-only TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 23 1 read-only TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 27 1 read-only TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 31 1 read-only PACRK Peripheral Access Control Register 0x58 32 read-write 0 0 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 3 1 read-only TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 7 1 read-only TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 11 1 read-only TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 15 1 read-only TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 19 1 read-only TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 23 1 read-only TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 27 1 read-only TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 31 1 read-only PACRL Peripheral Access Control Register 0x5C 32 read-write 0 0 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 3 1 read-only TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 7 1 read-only TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 11 1 read-only TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 15 1 read-only TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 19 1 read-only TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 23 1 read-only TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 27 1 read-only TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 31 1 read-only PACRM Peripheral Access Control Register 0x60 32 read-write 0 0 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 3 1 read-only TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 7 1 read-only TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 11 1 read-only TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 15 1 read-only TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 19 1 read-only TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 23 1 read-only TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 27 1 read-only TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 31 1 read-only PACRN Peripheral Access Control Register 0x64 32 read-write 0 0 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 3 1 read-only TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 7 1 read-only TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 11 1 read-only TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 15 1 read-only TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 19 1 read-only TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 23 1 read-only TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 27 1 read-only TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 31 1 read-only PACRO Peripheral Access Control Register 0x68 32 read-write 0 0 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 3 1 read-only TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 7 1 read-only TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 11 1 read-only TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 15 1 read-only TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 19 1 read-only TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 23 1 read-only TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 27 1 read-only TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 31 1 read-only PACRP Peripheral Access Control Register 0x6C 32 read-write 0 0 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 3 1 read-only TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 7 1 read-only TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 11 1 read-only TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 15 1 read-only TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 19 1 read-only TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 23 1 read-only TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 27 1 read-only TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 31 1 read-only PACRU Peripheral Access Control Register U 0x80 32 read-write 0 0 RESERVED no description available 0 24 read-only TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 27 1 read-only TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 RESERVED no description available 31 1 read-only DMA Enhanced direct memory access controller DMA_ 0x40008000 0 0x11C0 registers INT_DMA0 16 INT_DMA1 17 INT_DMA2 18 INT_DMA3 19 INT_DMA4 20 INT_DMA5 21 INT_DMA6 22 INT_DMA7 23 INT_DMA8 24 INT_DMA9 25 INT_DMA10 26 INT_DMA11 27 INT_DMA12 28 INT_DMA13 29 INT_DMA_Error 32 CR Control Register 0 32 read-write 0 0xFFFFFFFF RESERVED no description available 0 1 read-only EDBG Enable Debug 1 1 read-write 0 When in debug mode, the DMA continues to operate. #0 1 When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. #1 ERCA Enable Round Robin Channel Arbitration 2 1 read-write 0 Fixed priority arbitration is used for channel selection . #0 1 Round robin arbitration is used for channel selection . #1 RESERVED no description available 3 1 read-only HOE Halt On Error 4 1 read-write 0 Normal operation #0 1 Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. #1 HALT Halt DMA Operations 5 1 read-write 0 Normal operation #0 1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. #1 CLM Continuous Link Mode 6 1 read-write 0 A minor loop channel link made to itself goes through channel arbitration before being activated again. #0 1 A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. #1 EMLM Enable Minor Loop Mapping 7 1 read-write 0 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. #0 1 Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. #1 RESERVED no description available 8 8 read-only ECX Error Cancel Transfer 16 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the ES register and generating an optional error interrupt. #1 CX Cancel Transfer 17 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. #1 RESERVED no description available 18 14 read-only ES Error Status Register 0x4 32 read-only 0 0xFFFFFFFF DBE Destination Bus Error 0 1 read-only 0 No destination bus error #0 1 The last recorded error was a bus error on a destination write #1 SBE Source Bus Error 1 1 read-only 0 No source bus error #0 1 The last recorded error was a bus error on a source read #1 SGE Scatter/Gather Configuration Error 2 1 read-only 0 No scatter/gather configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. #1 NCE NBYTES/CITER Configuration Error 3 1 read-only 0 No NBYTES/CITER configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] #1 DOE Destination Offset Error 4 1 read-only 0 No destination offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. #1 DAE Destination Address Error 5 1 read-only 0 No destination address configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. #1 SOE Source Offset Error 6 1 read-only 0 No source offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. #1 SAE Source Address Error 7 1 read-only 0 No source address configuration error. #0 1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. #1 ERRCHN Error Channel Number or Cancelled Channel Number 8 4 read-only RESERVED no description available 12 2 read-only CPE Channel Priority Error 14 1 read-only 0 No channel priority error #0 1 The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique. #1 RESERVED no description available 15 1 read-only ECX Transfer Cancelled 16 1 read-only 0 No cancelled transfers #0 1 The last recorded entry was a cancelled transfer by the error cancel transfer input #1 RESERVED no description available 17 14 read-only VLD no description available 31 1 read-only 0 No ERR bits are set #0 1 At least one ERR bit is set indicating a valid error exists that has not been cleared #1 ERQ Enable Request Register 0xC 32 read-write 0 0xFFFFFFFF ERQ0 Enable DMA Request 0 0 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ1 Enable DMA Request 1 1 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ2 Enable DMA Request 2 2 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ3 Enable DMA Request 3 3 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ4 Enable DMA Request 4 4 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ5 Enable DMA Request 5 5 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ6 Enable DMA Request 6 6 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ7 Enable DMA Request 7 7 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ8 Enable DMA Request 8 8 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ9 Enable DMA Request 9 9 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ10 Enable DMA Request 10 10 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ11 Enable DMA Request 11 11 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ12 Enable DMA Request 12 12 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ13 Enable DMA Request 13 13 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 RESERVED no description available 14 18 read-only EEI Enable Error Interrupt Register 0x14 32 read-write 0 0xFFFFFFFF EEI0 Enable Error Interrupt 0 0 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI1 Enable Error Interrupt 1 1 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI2 Enable Error Interrupt 2 2 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI3 Enable Error Interrupt 3 3 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI4 Enable Error Interrupt 4 4 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI5 Enable Error Interrupt 5 5 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI6 Enable Error Interrupt 6 6 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI7 Enable Error Interrupt 7 7 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI8 Enable Error Interrupt 8 8 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI9 Enable Error Interrupt 9 9 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI10 Enable Error Interrupt 10 10 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI11 Enable Error Interrupt 11 11 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI12 Enable Error Interrupt 12 12 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI13 Enable Error Interrupt 13 13 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 RESERVED no description available 14 18 read-only CEEI Clear Enable Error Interrupt Register 0x18 8 write-only 0 0xFF CEEI Clear Enable Error Interrupt 0 4 write-only RESERVED no description available 4 2 write-only CAEE Clear All Enable Error Interrupts 6 1 write-only 0 Clear only the EEI bit specified in the CEEI field #0 1 Clear all bits in EEI #1 NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SEEI Set Enable Error Interrupt Register 0x19 8 write-only 0 0xFF SEEI Set Enable Error Interrupt 0 4 write-only RESERVED no description available 4 2 write-only SAEE Sets All Enable Error Interrupts 6 1 write-only 0 Set only the EEI bit specified in the SEEI field. #0 1 Sets all bits in EEI #1 NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERQ Clear Enable Request Register 0x1A 8 write-only 0 0xFF CERQ Clear Enable Request 0 4 write-only RESERVED no description available 4 2 write-only CAER Clear All Enable Requests 6 1 write-only 0 Clear only the ERQ bit specified in the CERQ field #0 1 Clear all bits in ERQ #1 NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SERQ Set Enable Request Register 0x1B 8 write-only 0 0xFF SERQ Set enable request 0 4 write-only RESERVED no description available 4 2 write-only SAER Set All Enable Requests 6 1 write-only 0 Set only the ERQ bit specified in the SERQ field #0 1 Set all bits in ERQ #1 NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CDNE Clear DONE Status Bit Register 0x1C 8 write-only 0 0xFF CDNE Clear DONE Bit 0 4 write-only RESERVED no description available 4 2 write-only CADN Clears All DONE Bits 6 1 write-only 0 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field #0 1 Clears all bits in TCDn_CSR[DONE] #1 NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SSRT Set START Bit Register 0x1D 8 write-only 0 0xFF SSRT Set START Bit 0 4 write-only RESERVED no description available 4 2 write-only SAST Set All START Bits (activates all channels) 6 1 write-only 0 Set only the TCDn_CSR[START] bit specified in the SSRT field #0 1 Set all bits in TCDn_CSR[START] #1 NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERR Clear Error Register 0x1E 8 write-only 0 0xFF CERR Clear Error Indicator 0 4 write-only RESERVED no description available 4 2 write-only CAEI Clear All Error Indicators 6 1 write-only 0 Clear only the ERR bit specified in the CERR field #0 1 Clear all bits in ERR #1 NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CINT Clear Interrupt Request Register 0x1F 8 write-only 0 0xFF CINT Clear Interrupt Request 0 4 write-only RESERVED no description available 4 2 write-only CAIR Clear All Interrupt Requests 6 1 write-only 0 Clear only the INT bit specified in the CINT field #0 1 Clear all bits in INT #1 NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 INT Interrupt Request Register 0x24 32 read-write 0 0xFFFFFFFF INT0 Interrupt Request 0 0 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT1 Interrupt Request 1 1 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT2 Interrupt Request 2 2 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT3 Interrupt Request 3 3 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT4 Interrupt Request 4 4 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT5 Interrupt Request 5 5 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT6 Interrupt Request 6 6 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT7 Interrupt Request 7 7 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT8 Interrupt Request 8 8 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT9 Interrupt Request 9 9 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT10 Interrupt Request 10 10 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT11 Interrupt Request 11 11 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT12 Interrupt Request 12 12 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT13 Interrupt Request 13 13 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 RESERVED no description available 14 18 read-only ERR Error Register 0x2C 32 read-write 0 0xFFFFFFFF ERR0 Error In Channel 0 0 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR1 Error In Channel 1 1 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR2 Error In Channel 2 2 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR3 Error In Channel 3 3 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR4 Error In Channel 4 4 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR5 Error In Channel 5 5 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR6 Error In Channel 6 6 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR7 Error In Channel 7 7 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR8 Error In Channel 8 8 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR9 Error In Channel 9 9 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR10 Error In Channel 10 10 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR11 Error In Channel 11 11 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR12 Error In Channel 12 12 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR13 Error In Channel 13 13 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 RESERVED no description available 14 18 read-only HRS Hardware Request Status Register 0x34 32 read-write 0 0xFFFFFFFF HRS0 Hardware Request Status Channel 0 0 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS1 Hardware Request Status Channel 1 1 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS2 Hardware Request Status Channel 2 2 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS3 Hardware Request Status Channel 3 3 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS4 Hardware Request Status Channel 4 4 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS5 Hardware Request Status Channel 5 5 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS6 Hardware Request Status Channel 6 6 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS7 Hardware Request Status Channel 7 7 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS8 Hardware Request Status Channel 8 8 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS9 Hardware Request Status Channel 9 9 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS10 Hardware Request Status Channel 10 10 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS11 Hardware Request Status Channel 11 11 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS12 Hardware Request Status Channel 12 12 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS13 Hardware Request Status Channel 13 13 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 RESERVED no description available 14 18 read-only DCHPRI3 Channel n Priority Register 0x100 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write RESERVED no description available 4 2 read-only DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI2 Channel n Priority Register 0x101 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write RESERVED no description available 4 2 read-only DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI1 Channel n Priority Register 0x102 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write RESERVED no description available 4 2 read-only DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI0 Channel n Priority Register 0x103 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write RESERVED no description available 4 2 read-only DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI7 Channel n Priority Register 0x104 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write RESERVED no description available 4 2 read-only DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI6 Channel n Priority Register 0x105 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write RESERVED no description available 4 2 read-only DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI5 Channel n Priority Register 0x106 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write RESERVED no description available 4 2 read-only DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI4 Channel n Priority Register 0x107 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write RESERVED no description available 4 2 read-only DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI11 Channel n Priority Register 0x108 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write RESERVED no description available 4 2 read-only DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI10 Channel n Priority Register 0x109 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write RESERVED no description available 4 2 read-only DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI9 Channel n Priority Register 0x10A 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write RESERVED no description available 4 2 read-only DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI8 Channel n Priority Register 0x10B 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write RESERVED no description available 4 2 read-only DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI13 Channel n Priority Register 0x10E 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write RESERVED no description available 4 2 read-only DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI12 Channel n Priority Register 0x10F 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write RESERVED no description available 4 2 read-only DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 14 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13 TCD%s_SADDR TCD Source Address 0x1000 32 read-write 0 0 SADDR Source Address 0 32 read-write 14 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13 TCD%s_SOFF TCD Signed Source Address Offset 0x1004 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write 14 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13 TCD%s_ATTR TCD Transfer Attributes 0x1006 16 read-write 0 0 DSIZE Destination Data Transfer Size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 SMOD Source Address Modulo. 11 5 read-write 0 Source address modulo feature is disabled #0 14 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13 TCD%s_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write 14 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13 TCD%s_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 14 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13 TCD%s_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 14 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13 TCD%s_SLAST TCD Last Source Address Adjustment 0x100C 32 read-write 0 0 SLAST Last source Address Adjustment 0 32 read-write 14 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13 TCD%s_DADDR TCD Destination Address 0x1010 32 read-write 0 0 DADDR Destination Address 0 32 read-write 14 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13 TCD%s_DOFF TCD Signed Destination Address Offset 0x1014 16 read-write 0 0 DOFF Destination Address Signed offset 0 16 read-write 14 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13 TCD%s_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1016 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 14 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13 TCD%s_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1016 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Link Channel Number 9 4 read-write RESERVED no description available 13 2 read-only ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 14 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13 TCD%s_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1018 32 read-write 0 0 DLASTSGA no description available 0 32 read-write 14 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13 TCD%s_CSR TCD Control and Status 0x101C 16 read-write 0 0 START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 ACTIVE Channel Active 6 1 read-write DONE Channel Done 7 1 read-write MAJORLINKCH Link Channel Number 8 4 read-write RESERVED no description available 12 2 read-only BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 14 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13 TCD%s_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x101E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 14 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13 TCD%s_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x101E 16 read-write 0 0 BITER Starting Major Iteration Count 0 9 read-write LINKCH Link Channel Number 9 4 read-write RESERVED no description available 13 2 read-only ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 FB FlexBus external bus interface FB_ 0x4000C000 0 0x64 registers 6 0xC 0,1,2,3,4,5 CSAR%s Chip Select Address Register 0 32 read-write 0 0xFFFFFFFF RESERVED no description available 0 16 read-only BA Base Address 16 16 read-write 6 0xC 0,1,2,3,4,5 CSMR%s Chip Select Mask Register 0x4 32 read-write 0 0xFFFFFFFF V Valid 0 1 read-write 0 Chip-select is invalid. #0 1 Chip-select is valid. #1 RESERVED no description available 1 7 read-only WP Write Protect 8 1 read-write 0 Write accesses are allowed. #0 1 Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle. #1 RESERVED no description available 9 7 read-only BAM Base Address Mask 16 16 read-write 0 The corresponding address bit in CSAR is used in the chip-select decode. #0 1 The corresponding address bit in CSAR is a don't care in the chip-select decode. #1 6 0xC 0,1,2,3,4,5 CSCR%s Chip Select Control Register 0x8 32 read-write 0x3FFC00 0xFFFFFFFF RESERVED no description available 0 3 read-only BSTW Burst-Write Enable 3 1 read-write 0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. #0 1 Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8 and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 BSTR Burst-Read Enable 4 1 read-write 0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. #0 1 Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports. #1 BEM Byte-Enable Mode 5 1 read-write 0 FB_BE is asserted for data write only. #0 1 FB_BE is asserted for data read and write accesses. #1 PS Port Size 6 2 read-write 00 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. #00 01 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. #01 10 16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b. #10 11 16-bit port size. Valid data sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b. #11 AA Auto-Acknowledge Enable 8 1 read-write 0 Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. #0 1 Enabled. Internal transfer acknowledge is asserted as specified by WS. #1 BLS Byte-Lane Shift 9 1 read-write 0 Not shifted. Data is left-aligned on FB_AD. #0 1 Shifted. Data is right-aligned on FB_AD. #1 WS Wait States 10 6 read-write WRAH Write Address Hold or Deselect 16 2 read-write 00 1 cycle (default for all but FB_CS0 ) #00 01 2 cycles #01 10 3 cycles #10 11 4 cycles (default for FB_CS0 ) #11 RDAH Read Address Hold or Deselect 18 2 read-write 00 When AA is 0b, 1 cycle. When AA is 1b, 0 cycles. #00 01 When AA is 0b, 2 cycles. When AA is 1b, 1 cycle. #01 10 When AA is 0b, 3 cycles. When AA is 1b, 2 cycles. #10 11 When AA is 0b, 4 cycles. When AA is 1b, 3 cycles. #11 ASET Address Setup 20 2 read-write 00 Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ). #00 01 Assert FB_CSn on the second rising clock edge after the address is asserted. #01 10 Assert FB_CSn on the third rising clock edge after the address is asserted. #10 11 Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ). #11 EXTS no description available 22 1 read-write 0 Disabled. FB_TS /FB_ALE asserts for one bus clock cycle. #0 1 Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts. #1 SWSEN Secondary Wait State Enable 23 1 read-write 0 Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. #0 1 Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. #1 RESERVED no description available 24 2 read-only SWS Secondary Wait States 26 6 read-write CSPMCR Chip Select port Multiplexing Control Register 0x60 32 read-write 0 0xFFFFFFFF RESERVED no description available 0 12 read-only GROUP5 FlexBus Signal Group 5 Multiplex control 12 4 read-write 0000 FB_TA #0000 0001 FB_CS3 . You must also write 1b to CSCR[AA]. #0001 0010 FB_BE_7_0 . You must also write 1b to CSCR[AA]. #0010 GROUP4 FlexBus Signal Group 4 Multiplex control 16 4 read-write 0000 FB_TBST #0000 0001 FB_CS2 #0001 0010 FB_BE_15_8 #0010 GROUP3 FlexBus Signal Group 3 Multiplex control 20 4 read-write 0000 FB_CS5 #0000 0001 FB_TSIZ1 #0001 0010 FB_BE_23_16 #0010 GROUP2 FlexBus Signal Group 2 Multiplex control 24 4 read-write 0000 FB_CS4 #0000 0001 FB_TSIZ0 #0001 0010 FB_BE_31_24 #0010 GROUP1 FlexBus Signal Group 1 Multiplex control 28 4 read-write 0000 FB_ALE #0000 0001 FB_CS1 #0001 0010 FB_TS #0010 MPU Memory protection unit MPU_ 0x4000D000 0 0x820 registers CESR Control/Error Status Register 0 32 read-write 0x815001 0xFFFFFFFF VLD Valid 0 1 read-write 0 MPU is disabled. All accesses from all bus masters are allowed. #0 1 MPU is enabled #1 RESERVED no description available 1 7 read-only NRGD Number Of Region Descriptors 8 4 read-only 0000 8 region descriptors #0000 0001 12 region descriptors #0001 0010 16 region descriptors #0010 NSP Number Of Slave Ports 12 4 read-only HRL Hardware Revision Level 16 4 read-only RESERVED no description available 20 3 read-only RESERVED no description available 23 1 read-only RESERVED no description available 24 3 read-only SPERR Slave Port n Error 27 5 read-write 0 No error has occurred for slave port n. #0 1 An error has occurred for slave port n. #1 5 0x8 0,1,2,3,4 EAR%s Error Address Register, slave port n 0x10 32 read-only 0 0 EADDR Error Address 0 32 read-only 5 0x8 0,1,2,3,4 EDR%s Error Detail Register, slave port n 0x14 32 read-only 0 0 ERW Error Read/Write 0 1 read-only 0 Read #0 1 Write #1 EATTR Error Attributes 1 3 read-only 000 User mode, instruction access #000 001 User mode, data access #001 010 Supervisor mode, instruction access #010 011 Supervisor mode, data access #011 EMN Error Master Number 4 4 read-only RESERVED no description available 8 8 read-only EACD Error Access Control Detail 16 16 read-only 8 0x10 0,1,2,3,4,5,6,7 RGD%s_WORD0 Region Descriptor n, Word 0 0x400 32 read-write 0 0xFFFFFFFF RESERVED no description available 0 5 read-only SRTADDR Start Address 5 27 read-write 8 0x10 0,1,2,3,4,5,6,7 RGD%s_WORD1 Region Descriptor n, Word 1 0x404 32 read-write 0xFFFFFFFF 0xFFFFFFFF RESERVED no description available 0 5 read-only ENDADDR End Address 5 27 read-write 8 0x10 0,1,2,3,4,5,6,7 RGD%s_WORD2 Region Descriptor n, Word 2 0x408 32 read-write 0x61F7DF 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write RESERVED no description available 5 1 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write RESERVED no description available 11 1 read-write M2UM Bus Master 2 User Mode Access control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write RESERVED no description available 17 1 read-write M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 RESERVED no description available 23 1 read-write M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 8 0x10 0,1,2,3,4,5,6,7 RGD%s_WORD3 Region Descriptor n, Word 3 0x40C 32 read-write 0x1 0xFFFFFFFF VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RESERVED no description available 1 31 read-only 8 0x4 0,1,2,3,4,5,6,7 RGDAAC%s Region Descriptor Alternate Access Control n 0x800 32 read-write 0x61F7DF 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write RESERVED no description available 5 1 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write RESERVED no description available 11 1 read-write M2UM Bus Master 2 User Mode Access Control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write RESERVED no description available 17 1 read-write M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 RESERVED no description available 23 1 read-write M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 IEVENT Intelligent event controller IEVENT_ 0x40019000 0 0x120 registers DRL iEvent Data Register: Low 0 32 read-write 0 0xFFFFFFFF IN_A0 Event Inputs {A0} 0 1 read-only 0 The state of the event input was negated. #0 1 The state of the event input was asserted. #1 IN_B0 Event Inputs {B0} 1 1 read-only 0 The state of the event input was negated. #0 1 The state of the event input was asserted. #1 IN_C0 Event Inputs {C0} 2 1 read-only 0 The state of the event input was negated. #0 1 The state of the event input was asserted. #1 IN_D0 Event Inputs {D0} 3 1 read-only 0 The state of the event input was negated. #0 1 The state of the event input was asserted. #1 Output_FSM0 Output Finite State Machine 0 4 3 read-only 000 The channel is disabled; FSM = idle. #000 001 The channel is enabled and waiting for the programmed event to occur; FSM = wfevt. #001 011 The programmed event has occurred and the channel is asserting its output; FSM = assert. #011 100 The channel is programmed for one-shot operation and the event has completed; FSM = os_hold. #100 101 The channel is waiting for the selected input signals to be negated before rearming; FSM = wfclr. #101 111 The event output has been acknowledged; done signals are broadcast during 1-cycle state; FSM = done. #111 Ev_Out0 Event Output 0 7 1 read-write 0 The event output is negated. #0 1 The event output is asserted. #1 IN_A1 Event Inputs {A1} 8 1 read-only 0 The state of the event input was negated. #0 IN_B1 Event Inputs {B1} 9 1 read-only 0 The state of the event input was negated. #0 1 The state of the event input was asserted. #1 IN_C1 Event Inputs {C1} 10 1 read-only 0 The state of the event input was negated. #0 1 The state of the event input was asserted. #1 IN_D1 Event Inputs {D1} 11 1 read-only 0 The state of the event input was negated. #0 1 The state of the event input was asserted. #1 Output_FSM1 Output Finite State Machine 1 12 3 read-only 000 The channel is disabled; FSM = idle. #000 001 The channel is enabled and waiting for the programmed event to occur; FSM = wfevt. #001 011 The programmed event has occurred and the channel is asserting its output; FSM = assert. #011 100 The channel is programmed for one-shot operation and the event has completed; FSM = os_hold. #100 101 The channel is waiting for the selected input signals to be negated before rearming; FSM = wfclr. #101 111 The event output has been acknowledged; done signals are broadcast during 1-cycle state; FSM = done. #111 Ev_Out1 Event Output 1 15 1 read-write 0 The event output is negated. #0 1 The event output is asserted. #1 IN_A2 Event Inputs {A2} 16 1 read-only 0 The state of the event input was negated. #0 1 The state of the event input was asserted. #1 IN_B2 Event Inputs {B2} 17 1 read-only 0 The state of the event input was negated. #0 1 The state of the event input was asserted. #1 IN_C2 Event Inputs {C2} 18 1 read-only 0 The state of the event input was negated. #0 1 The state of the event input was asserted. #1 IN_D2 Event Inputs {D2} 19 1 read-only 0 The state of the event input was negated. #0 1 The state of the event input was asserted. #1 Output_FSM2 Output Finite State Machine 2 20 3 read-only 000 The channel is disabled; FSM = idle. #000 001 The channel is enabled and waiting for the programmed event to occur; FSM = wfevt. #001 011 The programmed event has occurred and the channel is asserting its output; FSM = assert. #011 100 The channel is programmed for one-shot operation and the event has completed; FSM = os_hold. #100 101 The channel is waiting for the selected input signals to be negated before rearming; FSM = wfclr. #101 111 The event output has been acknowledged; done signals are broadcast during 1-cycle state; FSM = done. #111 Ev_Out2 Event Output 2 23 1 read-write 0 The event output is negated. #0 1 The event output is asserted. #1 IN_A3 Event Inputs {A3} 24 1 read-only 0 The state of the event input was negated. #0 1 The state of the event input was asserted. #1 IN_B3 Event Inputs {B3} 25 1 read-only 0 The state of the event input was negated. #0 1 The state of the event input was asserted. #1 IN_C3 Event Inputs {C3} 26 1 read-only 0 The state of the event input was negated. #0 1 The state of the event input was asserted. #1 IN_D3 Event Inputs {D3} 27 1 read-only 0 The state of the event input was negated. #0 1 The state of the event input was asserted. #1 Output_FSM3 Output Finite State Machine 3 28 3 read-only 000 The channel is disabled; FSM = idle. #000 001 The channel is enabled and waiting for the programmed event to occur; FSM = wfevt. #001 011 The programmed event has occurred and the channel is asserting its output; FSM = assert. #011 100 The channel is programmed for one-shot operation and the event has completed; FSM = os_hold. #100 101 The channel is waiting for the selected input signals to be negated before rearming; FSM = wfclr. #101 111 The event output has been acknowledged; done signals are broadcast during 1-cycle state; FSM = done. #111 Ev_Out3 Event Output 3 31 1 read-write 0 The event output is negated. #0 1 The event output is asserted. #1 CRL iEvent Control Register: Low 0x80 32 read-write 0 0xFFFFFFFF Type0 Output Channel Type 0 0 2 read-write 00 The channel is disabled. #00 01 The channel is defined as a DMA request output. #01 10 The channel is defined as a hardware trigger output. #10 11 The channel is defined as an interrupt request output. #11 OSE0 One-Shot Enable 0 2 1 read-write 0 The channel event output is enabled to occur multiple times. #0 1 The channel event output is enabled to occur one time. #1 DDB0 Disable Done Broadcast 0 3 1 read-write 0 The event done indicators are broadcast to the appropriate selected event inputs. #0 1 The event done indicators are not broadcast to the appropriate selected event inputs. #1 RESERVED no description available 4 3 read-only RO0 Read-Only 0 7 1 read-write 0 The iEvent configuration registers for this channel can be read and written. #0 1 The iEvent configuration registers for this channel can only be read. #1 Type1 Output Channel Type 1 8 2 read-write 00 The channel is disabled. #00 01 The channel is defined as a DMA request output. #01 10 The channel is defined as a hardware trigger output. #10 11 The channel is defined as an interrupt request output. #11 OSE1 One-Shot Enable 1 10 1 read-write 0 The channel event output is enabled to occur multiple times. #0 1 The channel event output is enabled to occur one time. #1 DDB1 Disable Done Broadcast 1 11 1 read-write 0 The event done indicators are broadcast to the appropriate selected event inputs. #0 1 The event done indicators are not broadcast to the appropriate selected event inputs. #1 RESERVED no description available 12 3 read-only RO1 Read-Only 1 15 1 read-write 0 The iEvent configuration registers for this channel can be read and written. #0 1 The iEvent configuration registers for this channel can only be read. #1 Type2 Output Channel Type 2 16 2 read-write 00 The channel is disabled. #00 01 The channel is defined as a DMA request output. #01 10 The channel is defined as a hardware trigger output. #10 11 The channel is defined as an interrupt request output. #11 OSE2 One-Shot Enable 2 18 1 read-write 0 The channel event output is enabled to occur multiple times. #0 1 The channel event output is enabled to occur one time. #1 DDB2 Disable Done Broadcast 2 19 1 read-write 0 The event done indicators are broadcast to the appropriate selected event inputs. #0 1 The event done indicators are not broadcast to the appropriate selected event inputs. #1 RESERVED no description available 20 3 read-only RO2 Read-Only 2 23 1 read-write 0 The iEvent configuration registers for this channel can be read and written. #0 1 The iEvent configuration registers for this channel can only be read. #1 Type3 Output Channel Type 3 24 2 read-write 00 The channel is disabled. #00 01 The channel is defined as a DMA request output. #01 10 The channel is defined as a hardware trigger output. #10 11 The channel is defined as an interrupt request output. #11 OSE3 One-Shot Enable 3 26 1 read-write 0 The channel event output is enabled to occur multiple times. #0 1 The channel event output is enabled to occur one time. #1 DDB3 Disable Done Broadcast 3 27 1 read-write 0 The event done indicators are broadcast to the appropriate selected event inputs. #0 1 The event done indicators are not broadcast to the appropriate selected event inputs. #1 RESERVED no description available 28 3 read-only RO3 Read-Only 3 31 1 read-write 0 The iEvent configuration registers for this channel can be read and written. #0 1 The iEvent configuration registers for this channel can only be read. #1 4 0x8 0,1,2,3 IMXCR%s iEvent Input Mux Configuration Register 0x100 32 read-only 0x4050607 0xFFFFFFFF D_Select no description available 0 4 read-only 0000 Select input[0] as D. #0000 0001 Select input[1] as D. #0001 0010 Select input[2] as D. #0010 0011 Select input[3] as D. #0011 0100 Select input[4] as D. #0100 0101 Select input[5] as D. #0101 0110 Select input[6] as D. #0110 0111 Select input[7] as D. #0111 1000 Select input[8] as D. #1000 1001 Select input[9] as D. #1001 1010 Select input[10] as D. #1010 1011 Select input[11] as D. #1011 1100 Select input[12] as D. #1100 1101 Select input[13] as D. #1101 1110 Select input[14] as D. #1110 1111 Select input[15] as D. #1111 RESERVED no description available 4 4 read-only C_Select no description available 8 4 read-only 0000 Select input[0] as C. #0000 0001 Select input[1] as C. #0001 0010 Select input[2] as C. #0010 0011 Select input[3] as C. #0011 0100 Select input[4] as C. #0100 0101 Select input[5] as C. #0101 0110 Select input[6] as C. #0110 0111 Select input[7] as C. #0111 1000 Select input[8] as C. #1000 1001 Select input[9] as C. #1001 1010 Select input[10] as C. #1010 1011 Select input[11] as C. #1011 1100 Select input[12] as C. #1100 1101 Select input[13] as C. #1101 1110 Select input[14] as C. #1110 1111 Select input[15] as C. #1111 RESERVED no description available 12 4 read-only B_Select no description available 16 4 read-only 0000 Select input[0] as B. #0000 0001 Select input[1] as B. #0001 0010 Select input[2] as B. #0010 0011 Select input[3] as B. #0011 0100 Select input[4] as B. #0100 0101 Select input[5] as B. #0101 0110 Select input[6] as B. #0110 0111 Select input[7] as B. #0111 1000 Select input[8] as B. #1000 1001 Select input[9] as B. #1001 1010 Select input[10] as B. #1010 1011 Select input[11] as B. #1011 1100 Select input[12] as B. #1100 1101 Select input[13] as B. #1101 1110 Select input[14] as B. #1110 1111 Select input[15] as B. #1111 RESERVED no description available 20 4 read-only A_Select no description available 24 4 read-only 0000 Select input[0] as A. #0000 0001 Select input[1] as A. #0001 0010 Select input[2] as A. #0010 0011 Select input[3] as A. #0011 0100 Select input[4] as A. #0100 0101 Select input[5] as A. #0101 0110 Select input[6] as A. #0110 0111 Select input[7] as A. #0111 1000 Select input[8] as A. #1000 1001 Select input[9] as A. #1001 1010 Select input[10] as A. #1010 1011 Select input[11] as A. #1011 1100 Select input[12] as A. #1100 1101 Select input[13] as A. #1101 1110 Select input[14] as A. #1110 1111 Select input[15] as A. #1111 RESERVED no description available 28 4 read-only 4 0x8 0,1,2,3 BFECR%s iEvent Boolean Function Eva1ation Configuration Register 0x104 32 read-write 0 0xFFFFFFFF PT3_DC Product Term 3, D input Configuration 0 2 read-write 00 Force the D input in this product term to a logical zero. #00 01 Pass the D input in this product term. #01 10 Complement the D input in this product term. #10 11 Force the D input in this product term to a logical one. #11 PT3_CC Product Term 3, C input Configuration 2 2 read-write 00 Force the C input in this product term to a logical zero. #00 01 Pass the C input in this product term. #01 10 Complement the C input in this product term. #10 11 Force the C input in this product term to a logical one. #11 PT3_BC Product Term 3, B input Configuration 4 2 read-write 00 Force the B input in this product term to a logical zero. #00 01 Pass the B input in this product term. #01 10 Complement the B input in this product term. #10 11 Force the B input in this product term to a logical one. #11 PT3_AC Product Term 3, A input Configuration 6 2 read-write 00 Force the A input in this product term to a logical zero. #00 01 Pass the A input in this product term. #01 10 Complement the A input in this product term. #10 11 Force the A input in this product term to a logical one. #11 PT2_DC Product Term 2, D input Configuration 8 2 read-write 00 Force the D input in this product term to a logical zero. #00 01 Pass the D input in this product term. #01 10 Complement the D input in this product term. #10 11 Force the D input in this product term to a logical one. #11 PT2_CC Product Term 2, C input Configuration 10 2 read-write 00 Force the C input in this product term to a logical zero. #00 01 Pass the C input in this product term. #01 10 Complement the C input in this product term. #10 11 Force the C input in this product term to a logical one. #11 PT2_BC Product Term 2, B input Configuration 12 2 read-write 00 Force the B input in this product term to a logical zero. #00 01 Pass the B input in this product term. #01 10 Complement the B input in this product term. #10 11 Force the B input in this product term to a logical one. #11 PT2_AC Product Term 2, A input Configuration 14 2 read-write 00 Force the A input in this product term to a logical zero. #00 01 Pass the A input in this product term. #01 10 Complement the A input in this product term. #10 11 Force the A input in this product term to a logical one. #11 PT1_DC Product Term 1, D input Configuration 16 2 read-write 00 Force the D input in this product term to a logical zero. #00 01 Pass the D input in this product term. #01 10 Complement the D input in this product term. #10 11 Force the D input in this product term to a logical one. #11 PT1_CC Product Term 1, C input Configuration 18 2 read-write 00 Force the C input in this product term to a logical zero. #00 01 Pass the C input in this product term. #01 10 Complement the C input in this product term. #10 11 Force the C input in this product term to a logical one. #11 PT1_BC Product Term 1, B input Configuration 20 2 read-write 00 Force the B input in this product term to a logical zero. #00 01 Pass the B input in this product term. #01 10 Complement the B input in this product term. #10 11 Force the B input in this product term to a logical one. #11 PT1_AC Product Term 1, A input Configuration 22 2 read-write 00 Force the A input in this product term to a logical zero. #00 01 Pass the A input in this product term. #01 10 Complement the A input in this product term. #10 11 Force the A input in this product term to a logical one. #11 PT0_DC Product Term 0, D input Configuration 24 2 read-write 00 Force the D input in this product term to a logical zero. #00 01 Pass the D input in this product term. #01 10 Complement the D input in this product term. #10 11 Force the D input in this product term to a logical one. #11 PT0_CC Product Term 0, C input Configuration 26 2 read-write 00 Force the C input in this product term to a logical zero. #00 01 Pass the C input in this product term. #01 10 Complement the C input in this product term. #10 11 Force the C input in this product term to a logical one. #11 PT0_BC Product Term 0, B input Configuration 28 2 read-write 00 Force the B input in this product term to a logical zero. #00 01 Pass the B input in this product term. #01 10 Complement the B input in this product term. #10 11 Force the B input in this product term to a logical one. #11 PT0_AC Product Term 0, A input Configuration 30 2 read-write 00 Force the A input in this product term to a logical zero. #00 01 Pass the A input in this product term. #01 10 Complement the A input in this product term. #10 11 Force the A input in this product term to a logical one. #11 FMC Flash Memory Controller FMC_ 0x4001F000 0 0x280 registers PFAPR Flash Access Protection Register 0 32 read-write 0xF000FF 0xFFFFFFFF M0AP Master 0 Access Protection 0 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M1AP Master 1 Access Protection 2 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M2AP Master 2 Access Protection 4 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M3AP Master 3 Access Protection 6 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 RESERVED no description available 8 8 read-only M0PFD Master 0 Prefetch Disable 16 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M1PFD Master 1 Prefetch Disable 17 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M2PFD Master 2 Prefetch Disable 18 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M3PFD Master 3 Prefetch Disable 19 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 RESERVED no description available 20 4 read-only RESERVED no description available 24 8 read-only PFB0CR Flash Bank 0 Control Register 0x4 32 read-write 0x3002001F 0xFFFFFFFF B0SEBE Bank 0 Single Entry Buffer Enable 0 1 read-write 0 Single entry buffer is disabled. #0 1 Single entry buffer is enabled. #1 B0IPE Bank 0 Instruction Prefetch Enable 1 1 read-write 0 Do not prefetch in response to instruction fetches. #0 1 Enable prefetches in response to instruction fetches. #1 B0DPE Bank 0 Data Prefetch Enable 2 1 read-write 0 Do not prefetch in response to data references. #0 1 Enable prefetches in response to data references. #1 B0ICE Bank 0 Instruction Cache Enable 3 1 read-write 0 Do not cache instruction fetches. #0 1 Cache instruction fetches. #1 B0DCE Bank 0 Data Cache Enable 4 1 read-write 0 Do not cache data references. #0 1 Cache data references. #1 CRC Cache Replacement Control 5 3 read-write 000 LRU replacement algorithm per set across all four ways #000 001 Reserved #001 010 Independent LRU with ways [0-1] for ifetches, [2-3] for data #010 011 Independent LRU with ways [0-2] for ifetches, [3] for data #011 1xx Reserved #1xx RESERVED no description available 8 8 read-only RESERVED no description available 16 1 read-only B0MW Bank 0 Memory Width 17 2 read-only 00 32 bits #00 01 64 bits #01 1x Reserved #1x S_B_INV Invalidate Prefetch Speculation Buffer 19 1 write-only 0 Speculation buffer and single entry buffer are not affected. #0 1 Invalidate (clear) speculation buffer and single entry buffer. #1 CINV_WAY Cache Invalidate Way x 20 4 write-only 0 No cache way invalidation for the corresponding cache #0 1 Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected #1 CLCK_WAY Cache Lock Way x 24 4 read-write 0 Cache way is unlocked and may be displaced #0 1 Cache way is locked and its contents are not displaced #1 B0RWSC Bank 0 Read Wait State Control 28 4 read-only PFB1CR Flash Bank 1 Control Register 0x8 32 read-only 0x30060000 0xFFFFFFFF RESERVED no description available 0 5 read-only RESERVED no description available 5 3 read-only RESERVED no description available 8 8 read-only RESERVED no description available 16 1 read-only B1MW Bank 1 Memory Width 17 2 read-only 00 32 bits #00 01 64 bits #01 10 Reserved #10 11 16 bits #11 RESERVED no description available 19 9 read-only B1RWSC Bank 1 Read Wait State Control 28 4 read-only 4 0x4 0,1,2,3 TAGVDW0S%s Cache Tag Storage 0x100 32 read-write 0 0xFFFFFFFF valid 1-bit valid for cache entry 0 1 read-write RESERVED no description available 1 5 read-only tag 13-bit tag for cache entry 6 13 read-write RESERVED no description available 19 13 read-only 4 0x4 0,1,2,3 TAGVDW1S%s Cache Tag Storage 0x110 32 read-write 0 0xFFFFFFFF valid 1-bit valid for cache entry 0 1 read-write RESERVED no description available 1 5 read-only tag 13-bit tag for cache entry 6 13 read-write RESERVED no description available 19 13 read-only 4 0x4 0,1,2,3 TAGVDW2S%s Cache Tag Storage 0x120 32 read-write 0 0xFFFFFFFF valid 1-bit valid for cache entry 0 1 read-write RESERVED no description available 1 5 read-only tag 13-bit tag for cache entry 6 13 read-write RESERVED no description available 19 13 read-only 4 0x4 0,1,2,3 TAGVDW3S%s Cache Tag Storage 0x130 32 read-write 0 0xFFFFFFFF valid 1-bit valid for cache entry 0 1 read-write RESERVED no description available 1 5 read-only tag 13-bit tag for cache entry 6 13 read-write RESERVED no description available 19 13 read-only 4 0x8 0,1,2,3 DATAW0S%sU Cache Data Storage (upper word) 0x200 32 read-write 0 0xFFFFFFFF data Bits [63:32] of data entry 0 32 read-write 4 0x8 0,1,2,3 DATAW0S%sL Cache Data Storage (lower word) 0x204 32 read-write 0 0xFFFFFFFF data Bits [31:0] of data entry 0 32 read-write 4 0x8 0,1,2,3 DATAW1S%sU Cache Data Storage (upper word) 0x220 32 read-write 0 0xFFFFFFFF data Bits [63:32] of data entry 0 32 read-write 4 0x8 0,1,2,3 DATAW1S%sL Cache Data Storage (lower word) 0x224 32 read-write 0 0xFFFFFFFF data Bits [31:0] of data entry 0 32 read-write 4 0x8 0,1,2,3 DATAW2S%sU Cache Data Storage (upper word) 0x240 32 read-write 0 0xFFFFFFFF data Bits [63:32] of data entry 0 32 read-write 4 0x8 0,1,2,3 DATAW2S%sL Cache Data Storage (lower word) 0x244 32 read-write 0 0xFFFFFFFF data Bits [31:0] of data entry 0 32 read-write 4 0x8 0,1,2,3 DATAW3S%sU Cache Data Storage (upper word) 0x260 32 read-write 0 0xFFFFFFFF data Bits [63:32] of data entry 0 32 read-write 4 0x8 0,1,2,3 DATAW3S%sL Cache Data Storage (lower word) 0x264 32 read-write 0 0xFFFFFFFF data Bits [31:0] of data entry 0 32 read-write DMAMUX DMA channel multiplexor DMAMUX_ 0x40021000 0 0xE registers 14 0x1 0,1,2,3,4,5,6,7,8,9,10,11,12,13 CHCFG%s Channel Configuration register 0 8 read-write 0 0xFF SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in Periodic Trigger mode. #1 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 PIT Periodic Interrupt Timer PIT_ 0x40023000 0 0x140 registers INT_PIT0 69 INT_PIT1 70 MCR PIT Module Control Register 0 32 read-write 0 0xFFFFFFFF FRZ Freeze 0 1 read-write 0 Timers continue to run in Debug mode. #0 1 Timers are stopped in Debug mode. #1 MDIS Module Disable 1 1 read-write 0 Clock for PIT timers is enabled. #0 1 Clock for PIT timers is disabled. #1 RESERVED no description available 2 30 read-only LTMR64H PIT Upper Lifetime Timer Register 0xE0 32 read-only 0 0xFFFFFFFF LTH Life Timer value 0 32 read-only LTMR64L PIT Lower Lifetime Timer Register 0xE4 32 read-only 0 0xFFFFFFFF LTL Life Timer value 0 32 read-only 4 0x10 0,1,2,3 LDVAL%s Timer Load Value Register 0x100 32 read-write 0 0xFFFFFFFF TSV Timer Start Value 0 32 read-write 4 0x10 0,1,2,3 CVAL%s Current Timer Value Register 0x104 32 read-only 0 0xFFFFFFFF TVL Current Timer Value 0 32 read-only 4 0x10 0,1,2,3 TCTRL%s Timer Control Register 0x108 32 read-write 0 0xFFFFFFFF TEN Timer Enable 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is enabled. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 CHN Chain Mode 2 1 read-write 0 Timer is not chained. #0 1 Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. #1 RESERVED no description available 3 29 read-only 4 0x10 0,1,2,3 TFLG%s Timer Flag Register 0x10C 32 read-write 0 0xFFFFFFFF TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 RESERVED no description available 1 31 read-only CRC Cyclic Redundancy Check CRC_ 0x40024000 0 0xC registers CRCLL CRC_CRCLL register. CRC 0 8 read-write 0xFF 0xFF CRCLL CRCLL stores the first 8 bits of the 32 bit CRC 0 8 read-write CRC CRC Data register CRC 0 32 read-write 0xFFFFFFFF 0xFFFFFFFF LL CRC Low Lower Byte 0 8 read-write LU CRC Low Upper Byte 8 8 read-write HL CRC High Lower Byte 16 8 read-write HU CRC High Upper Byte 24 8 read-write CRCL CRC_CRCL register. CRC 0 16 read-write 0xFFFF 0xFFFF CRCL CRCL stores the lower 16 bits of the 16/32 bit CRC 0 16 read-write CRCLU CRC_CRCLU register. 0x1 8 read-write 0xFF 0xFF CRCLU CRCLL stores the second 8 bits of the 32 bit CRC 0 8 read-write CRCHL CRC_CRCHL register. CRC 0x2 8 read-write 0xFF 0xFF CRCHL CRCHL stores the third 8 bits of the 32 bit CRC 0 8 read-write CRCH CRC_CRCH register. CRC 0x2 16 read-write 0xFFFF 0xFFFF CRCH CRCL stores the high 16 bits of the 16/32 bit CRC 0 16 read-write CRCHU CRC_CRCHU register. 0x3 8 read-write 0xFF 0xFF CRCHU CRCHU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write GPOLY CRC Polynomial register CRC 0x4 32 read-write 0x1021 0xFFFFFFFF LOW Low Polynominal Half-word 0 16 read-write HIGH High Polynominal Half-word 16 16 read-write GPOLYLL CRC_GPOLYLL register. CRC 0x4 8 read-write 0xFF 0xFF GPOLYLL POLYLL stores the first 8 bits of the 32 bit CRC 0 8 read-write GPOLYL CRC_GPOLYL register. CRC 0x4 16 read-write 0xFFFF 0xFFFF GPOLYL POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value 0 16 read-write GPOLYLU CRC_GPOLYLU register. 0x5 8 read-write 0xFF 0xFF GPOLYLU POLYLL stores the second 8 bits of the 32 bit CRC 0 8 read-write GPOLYH CRC_GPOLYH register. CRC 0x6 16 read-write 0xFFFF 0xFFFF GPOLYH POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value 0 16 read-write GPOLYHL CRC_GPOLYHL register. CRC 0x6 8 read-write 0xFF 0xFF GPOLYHL POLYHL stores the third 8 bits of the 32 bit CRC 0 8 read-write GPOLYHU CRC_GPOLYHU register. 0x7 8 read-write 0xFF 0xFF GPOLYHU POLYHU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write CTRL CRC Control register 0x8 32 read-write 0 0xFFFFFFFF RESERVED no description available 0 24 read-only TCRC no description available 24 1 read-write 0 16-bit CRC protocol. #0 1 32-bit CRC protocol. #1 WAS Write CRC Data Register As Seed 25 1 read-write 0 Writes to the CRC data register are data values. #0 1 Writes to the CRC data register are seed values. #1 FXOR Complement Read Of CRC Data Register 26 1 read-write 0 No XOR on reading. #0 1 Invert or complement the read value of the CRC Data register. #1 RESERVED no description available 27 1 read-only TOTR Type Of Transpose For Read 28 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 TOT Type Of Transpose For Writes 30 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 CTRLHU CRC_CTRLHU register. 0xB 8 read-write 0 0xFF TCRC no description available 0 1 read-write 0 16-bit CRC protocol. #0 1 32-bit CRC protocol. #1 WAS no description available 1 1 read-write 0 Writes to CRC data register are data values. #0 1 Writes to CRC data reguster are seed values. #1 FXOR no description available 2 1 read-write 0 No XOR on reading. #0 1 Invert or complement the read value of CRC data register. #1 RESERVED no description available 3 1 read-only TOTR no description available 4 2 read-write 00 No Transposition. #00 01 Bits in bytes are transposed, bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 TOT no description available 6 2 read-write 00 No Transposition. #00 01 Bits in bytes are transposed, bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 PDB0 Programmable Delay Block PDB PDB0_ 0x40025000 0 0x198 registers SC Status and Control Register 0 32 read-write 0 0xFFFFFFFF LDOK Load OK 0 1 read-write CONT Continuous Mode Enable 1 1 read-write 0 PDB operation in One-Shot mode #0 1 PDB operation in Continuous mode #1 MULT Multiplication Factor Select for Prescaler 2 2 read-write 00 Multiplication factor is 1 #00 01 Multiplication factor is 10 #01 10 Multiplication factor is 20 #10 11 Multiplication factor is 40 #11 RESERVED no description available 4 1 read-only PDBIE PDB Interrupt Enable. 5 1 read-write 0 PDB interrupt disabled #0 1 PDB interrupt enabled #1 PDBIF PDB Interrupt Flag 6 1 read-write PDBEN PDB Enable 7 1 read-write 0 PDB disabled. Counter is off. #0 1 PDB enabled. #1 TRGSEL Trigger Input Source Select 8 4 read-write 0000 Trigger-In 0 is selected #0000 0001 Trigger-In 1 is selected #0001 0010 Trigger-In 2 is selected #0010 0011 Trigger-In 3 is selected #0011 0100 Trigger-In 4 is selected #0100 0101 Trigger-In 5 is selected #0101 0110 Trigger-In 6 is selected #0110 0111 Trigger-In 7 is selected #0111 1000 Trigger-In 8 is selected #1000 1001 Trigger-In 9 is selected #1001 1010 Trigger-In 10 is selected #1010 1011 Trigger-In 11 is selected #1011 1100 Trigger-In 12 is selected #1100 1101 Trigger-In 13 is selected #1101 1110 Trigger-In 14 is selected #1110 1111 Software trigger is selected #1111 PRESCALER Prescaler Divider Select 12 3 read-write 000 Counting uses the peripheral clock divided by multiplication factor selected by MULT. #000 001 Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT. #001 010 Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT. #010 011 Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT. #011 100 Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT. #100 101 Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT. #101 110 Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT. #110 111 Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT. #111 DMAEN DMA Enable 15 1 read-write 0 DMA disabled #0 1 DMA enabled #1 SWTRIG Software Trigger 16 1 write-only PDBEIE PDB Sequence Error Interrupt Enable 17 1 read-write 0 PDB sequence error interrupt disabled. #0 1 PDB sequence error interrupt enabled. #1 LDMOD Load Mode Select 18 2 read-write 00 The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK. #00 01 The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK. #01 10 The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK. #10 11 The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK. #11 RESERVED no description available 20 12 read-only MOD Modulus Register 0x4 32 read-write 0xFFFF 0xFFFFFFFF MOD PDB Modulus 0 16 read-write RESERVED no description available 16 16 read-only CNT Counter Register 0x8 32 read-only 0 0xFFFFFFFF CNT PDB Counter 0 16 read-only RESERVED no description available 16 16 read-only IDLY Interrupt Delay Register 0xC 32 read-write 0xFFFF 0xFFFFFFFF IDLY PDB Interrupt Delay 0 16 read-write RESERVED no description available 16 16 read-only CHC1 Channel n Control Register 1 0x10 32 read-write 0 0xFFFFFFFF EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. #1 RESERVED no description available 16 16 read-only CHS Channel n Status Register 0x14 32 read-write 0 0xFFFFFFFF ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags. #1 RESERVED no description available 8 8 read-only CF PDB Channel Flags 16 8 read-write RESERVED no description available 24 8 read-only CHDLY0 Channel n Delay 0 Register 0x18 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CHDLY1 Channel n Delay 1 Register 0x1C 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CHDLY2 Channel n Delay 2 Register 0x20 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CHDLY3 Channel n Delay 3 Register 0x24 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only POEN Pulse-Out n Enable Register 0x190 32 read-write 0 0xFFFFFFFF POEN PDB Pulse-Out Enable 0 8 read-write 0 PDB Pulse-Out disabled #0 1 PDB Pulse-Out enabled #1 RESERVED no description available 8 24 read-only PODLY Pulse-Out n Delay Register 0x194 32 read-write 0 0xFFFFFFFF DLY2 PDB Pulse-Out Delay 2 0 16 read-write DLY1 PDB Pulse-Out Delay 1 16 16 read-write PDB1 Programmable Delay Block PDB PDB1_ 0x40026000 0 0x198 registers SC Status and Control Register 0 32 read-write 0 0xFFFFFFFF LDOK Load OK 0 1 read-write CONT Continuous Mode Enable 1 1 read-write 0 PDB operation in One-Shot mode #0 1 PDB operation in Continuous mode #1 MULT Multiplication Factor Select for Prescaler 2 2 read-write 00 Multiplication factor is 1 #00 01 Multiplication factor is 10 #01 10 Multiplication factor is 20 #10 11 Multiplication factor is 40 #11 RESERVED no description available 4 1 read-only PDBIE PDB Interrupt Enable. 5 1 read-write 0 PDB interrupt disabled #0 1 PDB interrupt enabled #1 PDBIF PDB Interrupt Flag 6 1 read-write PDBEN PDB Enable 7 1 read-write 0 PDB disabled. Counter is off. #0 1 PDB enabled. #1 TRGSEL Trigger Input Source Select 8 4 read-write 0000 Trigger-In 0 is selected #0000 0001 Trigger-In 1 is selected #0001 0010 Trigger-In 2 is selected #0010 0011 Trigger-In 3 is selected #0011 0100 Trigger-In 4 is selected #0100 0101 Trigger-In 5 is selected #0101 0110 Trigger-In 6 is selected #0110 0111 Trigger-In 7 is selected #0111 1000 Trigger-In 8 is selected #1000 1001 Trigger-In 9 is selected #1001 1010 Trigger-In 10 is selected #1010 1011 Trigger-In 11 is selected #1011 1100 Trigger-In 12 is selected #1100 1101 Trigger-In 13 is selected #1101 1110 Trigger-In 14 is selected #1110 1111 Software trigger is selected #1111 PRESCALER Prescaler Divider Select 12 3 read-write 000 Counting uses the peripheral clock divided by multiplication factor selected by MULT. #000 001 Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT. #001 010 Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT. #010 011 Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT. #011 100 Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT. #100 101 Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT. #101 110 Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT. #110 111 Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT. #111 DMAEN DMA Enable 15 1 read-write 0 DMA disabled #0 1 DMA enabled #1 SWTRIG Software Trigger 16 1 write-only PDBEIE PDB Sequence Error Interrupt Enable 17 1 read-write 0 PDB sequence error interrupt disabled. #0 1 PDB sequence error interrupt enabled. #1 LDMOD Load Mode Select 18 2 read-write 00 The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK. #00 01 The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK. #01 10 The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK. #10 11 The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK. #11 RESERVED no description available 20 12 read-only MOD Modulus Register 0x4 32 read-write 0xFFFF 0xFFFFFFFF MOD PDB Modulus 0 16 read-write RESERVED no description available 16 16 read-only CNT Counter Register 0x8 32 read-only 0 0xFFFFFFFF CNT PDB Counter 0 16 read-only RESERVED no description available 16 16 read-only IDLY Interrupt Delay Register 0xC 32 read-write 0xFFFF 0xFFFFFFFF IDLY PDB Interrupt Delay 0 16 read-write RESERVED no description available 16 16 read-only CHC1 Channel n Control Register 1 0x10 32 read-write 0 0xFFFFFFFF EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. #1 RESERVED no description available 16 16 read-only CHS Channel n Status Register 0x14 32 read-write 0 0xFFFFFFFF ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags. #1 RESERVED no description available 8 8 read-only CF PDB Channel Flags 16 8 read-write RESERVED no description available 24 8 read-only CHDLY0 Channel n Delay 0 Register 0x18 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CHDLY1 Channel n Delay 1 Register 0x1C 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CHDLY2 Channel n Delay 2 Register 0x20 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CHDLY3 Channel n Delay 3 Register 0x24 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only POEN Pulse-Out n Enable Register 0x190 32 read-write 0 0xFFFFFFFF POEN PDB Pulse-Out Enable 0 8 read-write 0 PDB Pulse-Out disabled #0 1 PDB Pulse-Out enabled #1 RESERVED no description available 8 24 read-only PODLY Pulse-Out n Delay Register 0x194 32 read-write 0 0xFFFFFFFF DLY2 PDB Pulse-Out Delay 2 0 16 read-write DLY1 PDB Pulse-Out Delay 1 16 16 read-write PDB2 Programmable Delay Block PDB PDB2_ 0x40027000 0 0x198 registers SC Status and Control Register 0 32 read-write 0 0xFFFFFFFF LDOK Load OK 0 1 read-write CONT Continuous Mode Enable 1 1 read-write 0 PDB operation in One-Shot mode #0 1 PDB operation in Continuous mode #1 MULT Multiplication Factor Select for Prescaler 2 2 read-write 00 Multiplication factor is 1 #00 01 Multiplication factor is 10 #01 10 Multiplication factor is 20 #10 11 Multiplication factor is 40 #11 RESERVED no description available 4 1 read-only PDBIE PDB Interrupt Enable. 5 1 read-write 0 PDB interrupt disabled #0 1 PDB interrupt enabled #1 PDBIF PDB Interrupt Flag 6 1 read-write PDBEN PDB Enable 7 1 read-write 0 PDB disabled. Counter is off. #0 1 PDB enabled. #1 TRGSEL Trigger Input Source Select 8 4 read-write 0000 Trigger-In 0 is selected #0000 0001 Trigger-In 1 is selected #0001 0010 Trigger-In 2 is selected #0010 0011 Trigger-In 3 is selected #0011 0100 Trigger-In 4 is selected #0100 0101 Trigger-In 5 is selected #0101 0110 Trigger-In 6 is selected #0110 0111 Trigger-In 7 is selected #0111 1000 Trigger-In 8 is selected #1000 1001 Trigger-In 9 is selected #1001 1010 Trigger-In 10 is selected #1010 1011 Trigger-In 11 is selected #1011 1100 Trigger-In 12 is selected #1100 1101 Trigger-In 13 is selected #1101 1110 Trigger-In 14 is selected #1110 1111 Software trigger is selected #1111 PRESCALER Prescaler Divider Select 12 3 read-write 000 Counting uses the peripheral clock divided by multiplication factor selected by MULT. #000 001 Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT. #001 010 Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT. #010 011 Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT. #011 100 Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT. #100 101 Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT. #101 110 Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT. #110 111 Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT. #111 DMAEN DMA Enable 15 1 read-write 0 DMA disabled #0 1 DMA enabled #1 SWTRIG Software Trigger 16 1 write-only PDBEIE PDB Sequence Error Interrupt Enable 17 1 read-write 0 PDB sequence error interrupt disabled. #0 1 PDB sequence error interrupt enabled. #1 LDMOD Load Mode Select 18 2 read-write 00 The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK. #00 01 The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK. #01 10 The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK. #10 11 The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK. #11 RESERVED no description available 20 12 read-only MOD Modulus Register 0x4 32 read-write 0xFFFF 0xFFFFFFFF MOD PDB Modulus 0 16 read-write RESERVED no description available 16 16 read-only CNT Counter Register 0x8 32 read-only 0 0xFFFFFFFF CNT PDB Counter 0 16 read-only RESERVED no description available 16 16 read-only IDLY Interrupt Delay Register 0xC 32 read-write 0xFFFF 0xFFFFFFFF IDLY PDB Interrupt Delay 0 16 read-write RESERVED no description available 16 16 read-only CHC1 Channel n Control Register 1 0x10 32 read-write 0 0xFFFFFFFF EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. #1 RESERVED no description available 16 16 read-only CHS Channel n Status Register 0x14 32 read-write 0 0xFFFFFFFF ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags. #1 RESERVED no description available 8 8 read-only CF PDB Channel Flags 16 8 read-write RESERVED no description available 24 8 read-only CHDLY0 Channel n Delay 0 Register 0x18 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CHDLY1 Channel n Delay 1 Register 0x1C 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CHDLY2 Channel n Delay 2 Register 0x20 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CHDLY3 Channel n Delay 3 Register 0x24 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only POEN Pulse-Out n Enable Register 0x190 32 read-write 0 0xFFFFFFFF POEN PDB Pulse-Out Enable 0 8 read-write 0 PDB Pulse-Out disabled #0 1 PDB Pulse-Out enabled #1 RESERVED no description available 8 24 read-only PODLY Pulse-Out n Delay Register 0x194 32 read-write 0 0xFFFFFFFF DLY2 PDB Pulse-Out Delay 2 0 16 read-write DLY1 PDB Pulse-Out Delay 1 16 16 read-write PDB3 Programmable Delay Block PDB PDB3_ 0x40028000 0 0x198 registers SC Status and Control Register 0 32 read-write 0 0xFFFFFFFF LDOK Load OK 0 1 read-write CONT Continuous Mode Enable 1 1 read-write 0 PDB operation in One-Shot mode #0 1 PDB operation in Continuous mode #1 MULT Multiplication Factor Select for Prescaler 2 2 read-write 00 Multiplication factor is 1 #00 01 Multiplication factor is 10 #01 10 Multiplication factor is 20 #10 11 Multiplication factor is 40 #11 RESERVED no description available 4 1 read-only PDBIE PDB Interrupt Enable. 5 1 read-write 0 PDB interrupt disabled #0 1 PDB interrupt enabled #1 PDBIF PDB Interrupt Flag 6 1 read-write PDBEN PDB Enable 7 1 read-write 0 PDB disabled. Counter is off. #0 1 PDB enabled. #1 TRGSEL Trigger Input Source Select 8 4 read-write 0000 Trigger-In 0 is selected #0000 0001 Trigger-In 1 is selected #0001 0010 Trigger-In 2 is selected #0010 0011 Trigger-In 3 is selected #0011 0100 Trigger-In 4 is selected #0100 0101 Trigger-In 5 is selected #0101 0110 Trigger-In 6 is selected #0110 0111 Trigger-In 7 is selected #0111 1000 Trigger-In 8 is selected #1000 1001 Trigger-In 9 is selected #1001 1010 Trigger-In 10 is selected #1010 1011 Trigger-In 11 is selected #1011 1100 Trigger-In 12 is selected #1100 1101 Trigger-In 13 is selected #1101 1110 Trigger-In 14 is selected #1110 1111 Software trigger is selected #1111 PRESCALER Prescaler Divider Select 12 3 read-write 000 Counting uses the peripheral clock divided by multiplication factor selected by MULT. #000 001 Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT. #001 010 Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT. #010 011 Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT. #011 100 Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT. #100 101 Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT. #101 110 Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT. #110 111 Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT. #111 DMAEN DMA Enable 15 1 read-write 0 DMA disabled #0 1 DMA enabled #1 SWTRIG Software Trigger 16 1 write-only PDBEIE PDB Sequence Error Interrupt Enable 17 1 read-write 0 PDB sequence error interrupt disabled. #0 1 PDB sequence error interrupt enabled. #1 LDMOD Load Mode Select 18 2 read-write 00 The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK. #00 01 The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK. #01 10 The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK. #10 11 The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK. #11 RESERVED no description available 20 12 read-only MOD Modulus Register 0x4 32 read-write 0xFFFF 0xFFFFFFFF MOD PDB Modulus 0 16 read-write RESERVED no description available 16 16 read-only CNT Counter Register 0x8 32 read-only 0 0xFFFFFFFF CNT PDB Counter 0 16 read-only RESERVED no description available 16 16 read-only IDLY Interrupt Delay Register 0xC 32 read-write 0xFFFF 0xFFFFFFFF IDLY PDB Interrupt Delay 0 16 read-write RESERVED no description available 16 16 read-only CHC1 Channel n Control Register 1 0x10 32 read-write 0 0xFFFFFFFF EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. #1 RESERVED no description available 16 16 read-only CHS Channel n Status Register 0x14 32 read-write 0 0xFFFFFFFF ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags. #1 RESERVED no description available 8 8 read-only CF PDB Channel Flags 16 8 read-write RESERVED no description available 24 8 read-only CHDLY0 Channel n Delay 0 Register 0x18 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CHDLY1 Channel n Delay 1 Register 0x1C 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CHDLY2 Channel n Delay 2 Register 0x20 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CHDLY3 Channel n Delay 3 Register 0x24 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only POEN Pulse-Out n Enable Register 0x190 32 read-write 0 0xFFFFFFFF POEN PDB Pulse-Out Enable 0 8 read-write 0 PDB Pulse-Out disabled #0 1 PDB Pulse-Out enabled #1 RESERVED no description available 8 24 read-only PODLY Pulse-Out n Delay Register 0x194 32 read-write 0 0xFFFFFFFF DLY2 PDB Pulse-Out Delay 2 0 16 read-write DLY1 PDB Pulse-Out Delay 1 16 16 read-write FTM0 FlexTimer Module FTM FTM0_ 0x40029000 0 0x9C registers SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 RESERVED no description available 8 24 read-only CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write RESERVED no description available 16 16 read-only MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD no description available 0 16 read-write RESERVED no description available 16 16 read-write 6 0x8 0,1,2,3,4,5 C%sSC Channel (n) Status And Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 RESERVED no description available 1 1 read-only ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 RESERVED no description available 8 24 read-only 6 0x8 0,1,2,3,4,5 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write RESERVED no description available 16 16 read-only CNTIN Counter Initial Value 0x4C 32 read-write 0 0xFFFFFFFF INIT no description available 0 16 read-write RESERVED no description available 16 16 read-write STATUS Capture And Compare Status 0x50 32 read-only 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 RESERVED no description available 8 24 read-only MODE Features Mode Selection 0x54 32 read-write 0x4 0xFFFFFFFF FTMEN FTM Enable 0 1 read-write 0 Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers. #0 1 All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions. #1 INIT Initialize The Channels Output 1 1 read-write WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 RESERVED no description available 8 24 read-only SYNC Synchronization 0x58 32 read-write 0 0xFFFFFFFF CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 REINIT FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 RESERVED no description available 8 24 read-only OUTINIT Initial State For Channels Output 0x5C 32 read-write 0 0xFFFFFFFF CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 RESERVED no description available 8 24 read-only OUTMASK Output Mask 0x60 32 read-write 0 0xFFFFFFFF CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 RESERVED no description available 8 24 read-only COMBINE Function For Linked Channels 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels For n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 7 1 read-only COMBINE1 Combine Channels For n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 15 1 read-only COMBINE2 Combine Channels For n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 23 1 read-only COMBINE3 Combine Channels For n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 31 1 read-only DEADTIME Deadtime Insertion Control 0x68 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 RESERVED no description available 8 24 read-only EXTTRIG FTM External Trigger 0x6C 32 read-write 0 0xFFFFFFFF CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-write 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 RESERVED no description available 8 24 read-write POL Channels Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 RESERVED no description available 8 24 read-write FMS Fault Mode Status 0x74 32 read-write 0 0xFFFFFFFF FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 RESERVED no description available 4 1 read-only FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 RESERVED no description available 8 24 read-only FILTER Input Capture Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write RESERVED no description available 16 16 read-write FLTCTRL Fault Control 0x7C 32 read-write 0 0xFFFFFFFF FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write RESERVED no description available 12 20 read-only QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 RESERVED no description available 8 24 read-only CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF NUMTOF TOF Frequency 0 5 read-write RESERVED no description available 5 1 read-only BDMMODE BDM Mode 6 2 read-write RESERVED no description available 8 1 read-only GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 RESERVED no description available 11 21 read-only FLTPOL FTM Fault Input Polarity 0x88 32 read-write 0 0xFFFFFFFF FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 RESERVED no description available 4 28 read-only SYNCONF Synchronization Configuration 0x8C 32 read-write 0 0xFFFFFFFF HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected. #1 RESERVED no description available 1 1 read-only CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 RESERVED no description available 3 1 read-only INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 RESERVED no description available 6 1 read-only SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 SWRSTCNT no description available 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWWRBUF no description available 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SWOM no description available 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWINVC no description available 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWSOC no description available 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 RESERVED no description available 13 3 read-only HWRSTCNT no description available 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWWRBUF no description available 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 HWOM no description available 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWINVC no description available 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWSOC no description available 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 RESERVED no description available 21 11 read-only INVCTRL FTM Inverting Control 0x90 32 read-write 0 0xFFFFFFFF INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 RESERVED no description available 4 28 read-only SWOCTRL FTM Software Output Control 0x94 32 read-write 0 0xFFFFFFFF CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 RESERVED no description available 16 16 read-only PWMLOAD FTM PWM Load 0x98 32 read-write 0 0xFFFFFFFF CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 RESERVED no description available 8 1 read-only LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 RESERVED no description available 10 22 read-only FTM1 FlexTimer Module FTM FTM1_ 0x4002A000 0 0x9C registers SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 RESERVED no description available 8 24 read-only CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write RESERVED no description available 16 16 read-only MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD no description available 0 16 read-write RESERVED no description available 16 16 read-write 2 0x8 0,1 C%sSC Channel (n) Status And Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 RESERVED no description available 1 1 read-only ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 RESERVED no description available 8 24 read-only 2 0x8 0,1 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write RESERVED no description available 16 16 read-only CNTIN Counter Initial Value 0x4C 32 read-write 0 0xFFFFFFFF INIT no description available 0 16 read-write RESERVED no description available 16 16 read-write STATUS Capture And Compare Status 0x50 32 read-only 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 RESERVED no description available 8 24 read-only MODE Features Mode Selection 0x54 32 read-write 0x4 0xFFFFFFFF FTMEN FTM Enable 0 1 read-write 0 Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers. #0 1 All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions. #1 INIT Initialize The Channels Output 1 1 read-write WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 RESERVED no description available 8 24 read-only SYNC Synchronization 0x58 32 read-write 0 0xFFFFFFFF CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 REINIT FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 RESERVED no description available 8 24 read-only OUTINIT Initial State For Channels Output 0x5C 32 read-write 0 0xFFFFFFFF CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 RESERVED no description available 8 24 read-only OUTMASK Output Mask 0x60 32 read-write 0 0xFFFFFFFF CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 RESERVED no description available 8 24 read-only COMBINE Function For Linked Channels 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels For n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 7 1 read-only COMBINE1 Combine Channels For n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 15 1 read-only COMBINE2 Combine Channels For n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 23 1 read-only COMBINE3 Combine Channels For n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 31 1 read-only DEADTIME Deadtime Insertion Control 0x68 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 RESERVED no description available 8 24 read-only EXTTRIG FTM External Trigger 0x6C 32 read-write 0 0xFFFFFFFF CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-write 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 RESERVED no description available 8 24 read-write POL Channels Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 RESERVED no description available 8 24 read-write FMS Fault Mode Status 0x74 32 read-write 0 0xFFFFFFFF FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 RESERVED no description available 4 1 read-only FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 RESERVED no description available 8 24 read-only FILTER Input Capture Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write RESERVED no description available 16 16 read-write FLTCTRL Fault Control 0x7C 32 read-write 0 0xFFFFFFFF FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write RESERVED no description available 12 20 read-only QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 RESERVED no description available 8 24 read-only CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF NUMTOF TOF Frequency 0 5 read-write RESERVED no description available 5 1 read-only BDMMODE BDM Mode 6 2 read-write RESERVED no description available 8 1 read-only GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 RESERVED no description available 11 21 read-only FLTPOL FTM Fault Input Polarity 0x88 32 read-write 0 0xFFFFFFFF FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 RESERVED no description available 4 28 read-only SYNCONF Synchronization Configuration 0x8C 32 read-write 0 0xFFFFFFFF HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected. #1 RESERVED no description available 1 1 read-only CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 RESERVED no description available 3 1 read-only INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 RESERVED no description available 6 1 read-only SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 SWRSTCNT no description available 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWWRBUF no description available 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SWOM no description available 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWINVC no description available 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWSOC no description available 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 RESERVED no description available 13 3 read-only HWRSTCNT no description available 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWWRBUF no description available 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 HWOM no description available 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWINVC no description available 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWSOC no description available 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 RESERVED no description available 21 11 read-only INVCTRL FTM Inverting Control 0x90 32 read-write 0 0xFFFFFFFF INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 RESERVED no description available 4 28 read-only SWOCTRL FTM Software Output Control 0x94 32 read-write 0 0xFFFFFFFF CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 RESERVED no description available 16 16 read-only PWMLOAD FTM PWM Load 0x98 32 read-write 0 0xFFFFFFFF CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 RESERVED no description available 8 1 read-only LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 RESERVED no description available 10 22 read-only FTM2 FlexTimer Module FTM FTM2_ 0x4002B000 0 0x9C registers SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 RESERVED no description available 8 24 read-only CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write RESERVED no description available 16 16 read-only MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD no description available 0 16 read-write RESERVED no description available 16 16 read-write 2 0x8 0,1 C%sSC Channel (n) Status And Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 RESERVED no description available 1 1 read-only ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 RESERVED no description available 8 24 read-only 2 0x8 0,1 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write RESERVED no description available 16 16 read-only CNTIN Counter Initial Value 0x4C 32 read-write 0 0xFFFFFFFF INIT no description available 0 16 read-write RESERVED no description available 16 16 read-write STATUS Capture And Compare Status 0x50 32 read-only 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 RESERVED no description available 8 24 read-only MODE Features Mode Selection 0x54 32 read-write 0x4 0xFFFFFFFF FTMEN FTM Enable 0 1 read-write 0 Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers. #0 1 All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions. #1 INIT Initialize The Channels Output 1 1 read-write WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 RESERVED no description available 8 24 read-only SYNC Synchronization 0x58 32 read-write 0 0xFFFFFFFF CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 REINIT FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 RESERVED no description available 8 24 read-only OUTINIT Initial State For Channels Output 0x5C 32 read-write 0 0xFFFFFFFF CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 RESERVED no description available 8 24 read-only OUTMASK Output Mask 0x60 32 read-write 0 0xFFFFFFFF CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 RESERVED no description available 8 24 read-only COMBINE Function For Linked Channels 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels For n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 7 1 read-only COMBINE1 Combine Channels For n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 15 1 read-only COMBINE2 Combine Channels For n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 23 1 read-only COMBINE3 Combine Channels For n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 31 1 read-only DEADTIME Deadtime Insertion Control 0x68 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 RESERVED no description available 8 24 read-only EXTTRIG FTM External Trigger 0x6C 32 read-write 0 0xFFFFFFFF CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-write 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 RESERVED no description available 8 24 read-write POL Channels Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 RESERVED no description available 8 24 read-write FMS Fault Mode Status 0x74 32 read-write 0 0xFFFFFFFF FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 RESERVED no description available 4 1 read-only FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 RESERVED no description available 8 24 read-only FILTER Input Capture Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write RESERVED no description available 16 16 read-write FLTCTRL Fault Control 0x7C 32 read-write 0 0xFFFFFFFF FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write RESERVED no description available 12 20 read-only QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 RESERVED no description available 8 24 read-only CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF NUMTOF TOF Frequency 0 5 read-write RESERVED no description available 5 1 read-only BDMMODE BDM Mode 6 2 read-write RESERVED no description available 8 1 read-only GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 RESERVED no description available 11 21 read-only FLTPOL FTM Fault Input Polarity 0x88 32 read-write 0 0xFFFFFFFF FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 RESERVED no description available 4 28 read-only SYNCONF Synchronization Configuration 0x8C 32 read-write 0 0xFFFFFFFF HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected. #1 RESERVED no description available 1 1 read-only CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 RESERVED no description available 3 1 read-only INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 RESERVED no description available 6 1 read-only SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 SWRSTCNT no description available 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWWRBUF no description available 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SWOM no description available 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWINVC no description available 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWSOC no description available 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 RESERVED no description available 13 3 read-only HWRSTCNT no description available 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWWRBUF no description available 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 HWOM no description available 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWINVC no description available 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWSOC no description available 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 RESERVED no description available 21 11 read-only INVCTRL FTM Inverting Control 0x90 32 read-write 0 0xFFFFFFFF INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 RESERVED no description available 4 28 read-only SWOCTRL FTM Software Output Control 0x94 32 read-write 0 0xFFFFFFFF CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 RESERVED no description available 16 16 read-only PWMLOAD FTM PWM Load 0x98 32 read-write 0 0xFFFFFFFF CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 RESERVED no description available 8 1 read-only LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 RESERVED no description available 10 22 read-only FTM3 FlexTimer Module FTM FTM3_ 0x4002C000 0 0x9C registers SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 RESERVED no description available 8 24 read-only CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write RESERVED no description available 16 16 read-only MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD no description available 0 16 read-write RESERVED no description available 16 16 read-write 6 0x8 0,1,2,3,4,5 C%sSC Channel (n) Status And Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 RESERVED no description available 1 1 read-only ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 RESERVED no description available 8 24 read-only 6 0x8 0,1,2,3,4,5 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write RESERVED no description available 16 16 read-only CNTIN Counter Initial Value 0x4C 32 read-write 0 0xFFFFFFFF INIT no description available 0 16 read-write RESERVED no description available 16 16 read-write STATUS Capture And Compare Status 0x50 32 read-only 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 RESERVED no description available 8 24 read-only MODE Features Mode Selection 0x54 32 read-write 0x4 0xFFFFFFFF FTMEN FTM Enable 0 1 read-write 0 Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers. #0 1 All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions. #1 INIT Initialize The Channels Output 1 1 read-write WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 RESERVED no description available 8 24 read-only SYNC Synchronization 0x58 32 read-write 0 0xFFFFFFFF CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 REINIT FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 RESERVED no description available 8 24 read-only OUTINIT Initial State For Channels Output 0x5C 32 read-write 0 0xFFFFFFFF CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 RESERVED no description available 8 24 read-only OUTMASK Output Mask 0x60 32 read-write 0 0xFFFFFFFF CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 RESERVED no description available 8 24 read-only COMBINE Function For Linked Channels 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels For n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 7 1 read-only COMBINE1 Combine Channels For n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 15 1 read-only COMBINE2 Combine Channels For n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 23 1 read-only COMBINE3 Combine Channels For n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 31 1 read-only DEADTIME Deadtime Insertion Control 0x68 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 RESERVED no description available 8 24 read-only EXTTRIG FTM External Trigger 0x6C 32 read-write 0 0xFFFFFFFF CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-write 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 RESERVED no description available 8 24 read-write POL Channels Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 RESERVED no description available 8 24 read-write FMS Fault Mode Status 0x74 32 read-write 0 0xFFFFFFFF FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 RESERVED no description available 4 1 read-only FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 RESERVED no description available 8 24 read-only FILTER Input Capture Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write RESERVED no description available 16 16 read-write FLTCTRL Fault Control 0x7C 32 read-write 0 0xFFFFFFFF FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write RESERVED no description available 12 20 read-only QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 RESERVED no description available 8 24 read-only CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF NUMTOF TOF Frequency 0 5 read-write RESERVED no description available 5 1 read-only BDMMODE BDM Mode 6 2 read-write RESERVED no description available 8 1 read-only GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 RESERVED no description available 11 21 read-only FLTPOL FTM Fault Input Polarity 0x88 32 read-write 0 0xFFFFFFFF FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 RESERVED no description available 4 28 read-only SYNCONF Synchronization Configuration 0x8C 32 read-write 0 0xFFFFFFFF HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected. #1 RESERVED no description available 1 1 read-only CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 RESERVED no description available 3 1 read-only INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 RESERVED no description available 6 1 read-only SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 SWRSTCNT no description available 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWWRBUF no description available 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SWOM no description available 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWINVC no description available 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWSOC no description available 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 RESERVED no description available 13 3 read-only HWRSTCNT no description available 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWWRBUF no description available 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 HWOM no description available 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWINVC no description available 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWSOC no description available 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 RESERVED no description available 21 11 read-only INVCTRL FTM Inverting Control 0x90 32 read-write 0 0xFFFFFFFF INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 RESERVED no description available 4 28 read-only SWOCTRL FTM Software Output Control 0x94 32 read-write 0 0xFFFFFFFF CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 RESERVED no description available 16 16 read-only PWMLOAD FTM PWM Load 0x98 32 read-write 0 0xFFFFFFFF CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 RESERVED no description available 8 1 read-only LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 RESERVED no description available 10 22 read-only RTC Real-time counter RTC_ 0x4002D000 0 0xC registers SC RTC Status and Control Register 0 32 read-write 0 0xFFFFFFFF RESERVED no description available 0 4 read-only RTCO Real-Time Counter Output 4 1 read-write 0 Real-time counter output disabled. #0 1 Real-time counter output enabled. #1 DMAE DMA Enable 5 1 read-write 0 DMA request is disabled. Software polling needed. #0 1 DMA request is enabled. #1 RTIE Real-Time Interrupt Enable 6 1 read-write 0 Real-time interrupt requests are disabled. Use software polling. #0 1 Real-time interrupt requests are enabled. #1 RTIF Real-Time Interrupt Flag 7 1 read-write 0 RTC counter has not reached the value in the RTC modulo register. #0 1 RTC counter has reached the value in the RTC modulo register. #1 RTCPS Real-Time Clock Prescaler Select 8 3 read-write 000 Off #000 001 If RTCLKS = x0, it is 1; if RTCLKS = x1, it is 128. #001 010 If RTCLKS = x0, it is 2; if RTCLKS = x1, it is 256. #010 011 If RTCLKS = x0, it is 4; if RTCLKS = x1, it is 512. #011 100 If RTCLKS = x0, it is 8; if RTCLKS = x1, it is 1024. #100 101 If RTCLKS = x0, it is 16; if RTCLKS = x1, it is 2048. #101 110 If RTCLKS = x0, it is 32; if RTCLKS = x1, it is 100. #110 111 If RTCLKS = x0, it is 64; if RTCLKS = x1, it is 1000. #111 RESERVED no description available 11 3 read-only RTCLKS Real-Time Clock Source Select 14 2 read-write 00 External clock source. #00 01 Real-time clock source is 1 kHz. #01 10 Internal clock. #10 11 Bus clock. #11 RESERVED no description available 16 16 read-only MOD RTC Modulo Register 0x4 32 read-write 0 0xFFFFFFFF MOD RTC Modulo 0 16 read-write RESERVED no description available 16 16 read-only CNT RTC Counter Register 0x8 32 read-only 0 0xFFFFFFFF CNT RTC Count 0 16 read-only RESERVED no description available 16 16 read-only TSI0 Touch Sensing Input TSI0_ 0x40030000 0 0x124 registers GENCS General Control and Status Register 0 32 read-write 0 0xFFFFFFFF STPE no description available 0 1 read-write 0 Disable TSI when MCU goes into low power modes. #0 1 Allows TSI to continue running in all low power modes. #1 STM Scan Trigger Mode. User is allowed to change this bit when TSI is not working in progress. 1 1 read-write 0 Software trigger scan. #0 1 Periodical Scan. #1 RESERVED Reserved 2 1 read-write RESERVED no description available 3 1 read-only ESOR End-of-Scan or Out-of-Range Interrupt select 4 1 read-write 0 Out-of-Range interrupt is allowed. #0 1 End-of-Scan interrupt is allowed. #1 ERIE Error Interrupt Enable 5 1 read-write 0 Interrupt disabled for error. #0 1 Interrupt enabled for error. #1 TSIIE Touch Sensing Input Interrupt Module Enable 6 1 read-write 0 Interrupt from TSI is disabled. #0 1 Interrupt from TSI is enabled. #1 TSIEN Touch Sensing Input Module Enable 7 1 read-write 0 Disable #0 1 Enable #1 SWTS Software Trigger Start 8 1 write-only SCNIP Scan In Progress status 9 1 read-only RESERVED no description available 10 2 read-only OVRF Overrun error Flag. This flag is set when a scan trigger occurs while a scan is still in progress. Write "1", when this flag is set, to clear it.. 12 1 read-write 0 No over run. #0 1 Over Run occurred. #1 EXTERF External Electrode error occurred 13 1 read-write 0 No short. #0 1 Short to VDD or VSS was detected on one or more electrodes. #1 OUTRGF Out of Range Flag. 14 1 read-write EOSF End of Scan Flag. 15 1 read-write PS Electrode Oscillator prescaler. . 16 3 read-write 000 Electrode Oscillator Frequency divided by 1 #000 001 Electrode Oscillator Frequency divided by 2 #001 010 Electrode Oscillator Frequency divided by 4 #010 011 Electrode Oscillator Frequency divided by 8 #011 100 Electrode Oscillator Frequency divided by 16 #100 101 Electrode Oscillator Frequency divided by 32 #101 110 Electrode Oscillator Frequency divided by 64 #110 111 Electrode Oscillator Frequency divided by 128 #111 NSCN Number of Consecutive Scans per Electrode electrode. 19 5 read-write 00000 Once per electrode #00000 00001 Twice per electrode #00001 00010 3 times per electrode #00010 00011 4 times per electrode #00011 00100 5 times per electrode #00100 00101 6 times per electrode #00101 00110 7 times per electrode #00110 00111 8 times per electrode #00111 01000 9 times per electrode #01000 01001 10 times per electrode #01001 01010 11 times per electrode #01010 01011 12 times per electrode #01011 01100 13 times per electrode #01100 01101 14 times per electrode #01101 01110 15 times per electrode #01110 01111 16 times per electrode #01111 10000 17 times per electrode #10000 10001 18 times per electrode #10001 10010 19 times per electrode #10010 10011 20 times per electrode #10011 10100 21 times per electrode #10100 10101 22 times per electrode #10101 10110 23 times per electrode #10110 10111 24 times per electrode #10111 11000 25 times per electrode #11000 11001 26 times per electrode #11001 11010 27 times per electrode #11010 11011 28 times per electrode #11011 11100 29 times per electrode #11100 11101 30 times per electrode #11101 11110 31 times per electrode #11110 11111 32 times per electrode #11111 RESERVED no description available 24 8 read-only SCANC SCAN Control Register 0x4 32 read-write 0 0xFFFFFFFF AMPSC Active Mode Prescaler 0 3 read-write 000 Input Clock Source divided by 1. #000 001 Input Clock Source divided by 2. #001 010 Input Clock Source divided by 4. #010 011 Input Clock Source divided by 8. #011 100 Input Clock Source divided by 16. #100 101 Input Clock Source divided by 32. #101 110 Input Clock Source divided by 64. #110 111 Input Clock Source divided by 128. #111 AMCLKS Active Mode Clock Source 3 2 read-write 00 LPOCLK #00 01 IRCLK. #01 10 ERCLK. #10 11 Not valid. #11 RESERVED no description available 5 1 read-only RESERVED no description available 6 2 read-only SMOD Scan Module 8 8 read-write 00000000 Continuous Scan. #00000000 EXTCHRG External OSC Charge Current select 16 3 read-write 000 0.5 uA charge current. #000 001 1 uA charge current. #001 010 2 uA charge current. #010 011 4 uA charge current. #011 100 8 uA charge current. #100 101 16 uA charge current. #101 110 32 uA charge current. #110 111 64 uA charge current. #111 RESERVED no description available 19 1 read-only DVOLT no description available 20 2 read-write 00 Vp = 1.33 V, Vm = 0.30 V, DV = 1.03 V. #00 01 Vp = 1.18 V, Vm = 0.45 V, DV = 0.73 V. #01 10 Vp = 1.03 V, Vm = 0.60 V, DV = 0.43 V. #10 11 Vp = 0.95 V, Vm = 0.67 V, DV = 0.29 V. #11 RESERVED no description available 22 2 read-only REFCHRG Ref OSC Charge Current select 24 3 read-write 000 0.5 uA charge current. #000 001 1 uA charge current. #001 010 2 uA charge current. #010 011 4 uA charge current. #011 100 8 uA charge current. #100 101 16 uA charge current. #101 110 32 uA charge current. #110 111 64 uA charge current. #111 RESERVED no description available 27 1 read-only RW R/W 28 4 read-write 0000 Normal operation. #0000 PEN Pin Enable Register 0x8 32 read-write 0 0xFFFFFFFF PEN0 Touch Sensing Input Pin Enable Register 0 0 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN1 Touch Sensing Input Pin Enable Register 1 1 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN2 Touch Sensing Input Pin Enable Register 2 2 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN3 Touch Sensing Input Pin Enable Register 3 3 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN4 Touch Sensing Input Pin Enable Register 4 4 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN5 Touch Sensing Input Pin Enable Register 5 5 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN6 Touch Sensing Input Pin Enable Register 6 6 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN7 Touch Sensing Input Pin Enable Register 7 7 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN8 Touch Sensing Input Pin Enable Register 8 8 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN9 Touch Sensing Input Pin Enable Register 9 9 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN10 Touch Sensing Input Pin Enable Register 10 10 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN11 Touch Sensing Input Pin Enable Register 11 11 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN12 Touch Sensing Input Pin Enable Register 12 12 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN13 Touch Sensing Input Pin Enable Register 13 13 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN14 Touch Sensing Input Pin Enable Register 14 14 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN15 Touch Sensing Input Pin Enable Register 15 15 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 LPSP Low Power Scan Pin 16 4 read-write 0000 TSI_IN[0] is active in low power mode. #0000 0001 TSI_IN[1] is active in low power mode. #0001 0010 TSI_IN[2] is active in low power mode. #0010 0011 TSI_IN[3] is active in low power mode. #0011 0100 TSI_IN[4] is active in low power mode. #0100 0101 TSI_IN[5] is active in low power mode. #0101 0110 TSI_IN[6] is active in low power mode. #0110 0111 TSI_IN[7] is active in low power mode. #0111 1000 TSI_IN[8] is active in low power mode. #1000 1001 TSI_IN[9] is active in low power mode. #1001 1010 TSI_IN[10] is active in low power mode. #1010 1011 TSI_IN[11] is active in low power mode. #1011 1100 TSI_IN[12] is active in low power mode. #1100 1101 TSI_IN[13] is active in low power mode. #1101 1110 TSI_IN[14] is active in low power mode. #1110 1111 TSI_IN[15] is active in low power mode. #1111 RESERVED no description available 20 12 read-only 8 0x4 1,3,5,7,9,11,13,15 CNTR%s Counter Register 0x100 32 read-only 0 0xFFFFFFFF CNTN1 TouchSensing Channel n-1 16-bit counter value 0 16 read-only CNTN TouchSensing Channel n 16-bit counter value 16 16 read-only THRESHOLD Low Power Channel Threshold Register 0x120 32 read-write 0 0xFFFFFFFF HTHH Touch Sensing Channel High Threshold value 0 16 read-write LTHH Touch Sensing Channel Low Threshold value 16 16 read-write SIM System Integration Module SIM_ 0x40032000 0x4 0x60 registers SOPT2 System Options Register 2 0x4 32 read-write 0x55553 0xFFFFFFFF FLLENSTOP4 no description available 0 1 read-write 0 FLL is disabled in STOP4 mode. #0 1 FLL is enbled in STOP4 mode. #1 RESETIFE no description available 1 1 read-write 0 Filter of Reset pad is disabled. #0 1 Filter of Reset pad is enabled. #1 RESERVED no description available 2 2 read-only OBEPADSELA13 no description available 4 2 read-write 00 5 mA drive strength for pad PTA13. #00 01 5 mA drive strength for pad PTA13. #01 10 15 mA drive strength for pad PTA13. #10 11 20 mA drive strength for pad PTA13. #11 OBEPADSELA12 no description available 6 2 read-write 00 5 mA drive strength for pad PTA12. #00 01 5 mA drive strength for pad PTA12. #01 10 15 mA drive strength for pad PTA12. #10 11 20 mA drive strength for pad PTA12. #11 OBEPADSELA3 no description available 8 2 read-write 00 5 mA drive strength for pad PTA3. #00 01 5 mA drive strength for pad PTA3. #01 10 15 mA drive strength for pad PTA3. #10 11 20 mA drive strength for pad PTA3. #11 OBEPADSELA2 no description available 10 2 read-write 00 5 mA drive strength for pad PTA2. #00 01 5 mA drive strength for pad PTA2. #01 10 15 mA drive strength for pad PTA2. #10 11 20 mA drive strength for pad PTA2. #11 OBEPADSELE1 no description available 12 2 read-write 00 5 mA drive strength for pad PTE1. #00 01 5 mA drive strength for pad PTE1. #01 10 15 mA drive strength for pad PTE1. #10 11 20 mA drive strength for pad PTE1. #11 OBEPADSELE0 no description available 14 2 read-write 00 5 mA drive strength for pad PTE0. #00 01 5 mA drive strength for pad PTE0. #01 10 15 mA drive strength for pad PTE0. #10 11 20 mA drive strength for pad PTE0. #11 FBSL FlexBus security level 16 2 read-write 00 All off-chip accesses (instruction and data) via the FlexBus are disallowed. #00 01 All off-chip accesses (instruction and data) via the FlexBus are disallowed. #01 10 Off-chip instruction accesses are disallowed. Data accesses are allowed. #10 11 Off-chip instruction accesses and data accesses are allowed. #11 TRACECLKSEL Debug trace clock select 18 1 read-write 0 ICSOUTCLK #0 1 Core/system clock #1 RESERVED no description available 19 2 read-only RAMSIZE The RAM size in the device. 21 1 read-only 0 RAM size is 16 KB in the device. ( 8 KB Upper SRAM. 8 KB Lower SRAM). #0 1 RAM size is 24 KB in the device. (16 KB Upper SRAM. 8 KB Lower SRAM). #1 RESERVED no description available 22 4 read-only FSIZE The flash size of the device. 26 2 read-only 00 128 KB #00 01 192 KB #01 10 256 KB #10 11 256KB #11 TSIEN no description available 28 1 read-only 0 TSI is not available in the device. #0 1 TSI is available in the device. #1 MAXCLK no description available 29 1 read-only 0 Maximum clock in the system is 36 MHz #0 1 Maximum clock in the system is 72 MHz. #1 RESERVED no description available 30 2 read-only SOPT3 System Options Register 3 0x8 32 read-write 0 0xFFFFFFFF FTM0_PDB no description available 0 4 read-write FTM1_PDB no description available 4 4 read-write FTM2_PDB no description available 8 4 read-write FTM3_PDB no description available 12 4 read-write FTM_SYNC0 no description available 16 1 read-write FTM_SYNC1 no description available 17 1 read-write FTM_SYNC2 no description available 18 1 read-write FTM_SYNC3 no description available 19 1 read-write RESERVED no description available 20 12 read-only SOPT4 System Options Register 4 0xC 32 read-write 0 0xFFFFFFFF FTM0FLT0 FTM0 Fault 0 Select 0 1 read-write 0 FTM0_FLT0 pin #0 1 CMP0 out #1 FTM0FLT1 FTM0 Fault 1 Select 1 1 read-write 0 FTM0_FLT1 pin #0 1 CMP1 out #1 FTM0FLT2 FTM0 Fault 2 Select 2 1 read-write 0 FTM0_FLT2 pin #0 1 CMP2 out #1 FTM0FLT3 FTM0 Fault 3 Select 3 1 read-write 0 FTM0_FLT3 pin #0 1 CMP3 out #1 RESERVED no description available 4 8 read-only FTM3FLT0 FTM3 Fault 0 Select 12 1 read-write 0 FTM3_FLT0 pin #0 1 CMP0 out #1 FTM3FLT1 FTM3 Fault 1 Select 13 1 read-write 0 FTM3_FLT1 pin #0 1 CMP1 out #1 FTM3FLT2 FTM3 Fault 2 Select 14 1 read-write 0 FTM3_FLT2 pin #0 1 CMP2 out #1 FTM3FLT3 FTM3 Fault 3 Select 15 1 read-write 0 FTM3_FLT3 pin #0 1 CMP3 out #1 RESERVED no description available 16 4 read-only FTM1CH0SRC FTM1 channel 0 input capture source select 20 2 read-write 00 FTM1_CH0 signal #00 01 CMP0 output #01 10 CMP1 output #10 11 CMP2 output #11 FTM2CH0SRC FTM2 channel 0 input capture source select 22 2 read-write 00 FTM2_CH0 signal #00 01 CMP1 output #01 10 CMP2 output #10 11 CMP3 output #11 FTM0CLKSEL FlexTimer 0 External Clock Pin Select 24 1 read-write 0 FTM_CLK0 pin #0 1 FTM_CLK1 pin #1 FTM1CLKSEL FTM1 External Clock Pin Select 25 1 read-write 0 FTM_CLK0 pin #0 1 FTM_CLK1 pin #1 FTM2CLKSEL FlexTimer 2 External Clock Pin Select 26 1 read-write 0 FTM2 external clock driven by FTM_CLK0 pin. #0 1 FTM2 external clock driven by FTM_CLK1 pin. #1 FTM3CLKSEL FlexTimer 3 External Clock Pin Select 27 1 read-write 0 FTM3 external clock driven by FTM_CLK0 pin. #0 1 FTM3 external clock driven by FTM_CLK1 pin. #1 RESERVED no description available 28 4 read-only SOPT5 System Options Register 5 0x10 32 read-write 0 0xFFFFFFFF UART0TXSRC UART 0 transmit data source select 0 2 read-write 00 UART0_TX pin #00 01 UART0_TX pin modulated with FTM1 channel 0 output #01 10 UART0_TX pin modulated with FTM2 channel 0 output #10 11 Reserved #11 UART0RXSRC UART 0 receive data source select 2 2 read-write 00 UART0_RX pin #00 01 CMP0 #01 10 CMP1 #10 11 Reserved #11 UART1TXSRC UART 1 transmit data source select 4 2 read-write 00 UART1_TX pin #00 01 UART1_TX pin modulated with FTM1 channel 0 output #01 10 UART1_TX pin modulated with FTM2 channel 0 output #10 11 Reserved #11 UART1RXSRC UART 1 receive data source select 6 2 read-write 00 UART1_RX pin #00 01 CMP0 #01 10 CMP1 #10 11 Reserved #11 RESERVED no description available 8 24 read-only SOPT6 System Options Register 6 0x14 32 read-write 0 0xFFFFFFFF CLKDIV no description available 0 3 read-write 000 Divided by 1. #000 001 Divided by 2. #001 010 Divided by 4. #010 011 Divided by 8. #011 100 Divided by 16. #100 RESERVED no description available 3 1 read-only CLKOS Clock source select 4 4 read-write 0000 bus_clk #0000 0001 flash_clk #0001 0010 ICSIRCLK #0010 0011 ICSFFCLK #0011 0100 ICSOUT #0100 0101 ICSDCLK #0101 0110 ICSLCLK #0110 0111 OSCOUT #0111 1000 LPOCLK #1000 1001 flex_bus clock #1001 1010 platform_clk #1010 RESERVED no description available 8 24 read-only SOPT7 System Options Register 7 0x18 32 read-write 0 0xFFFFFFFF ADC0TRGSEL ADC0 trigger select 0 4 read-write 0000 PDB external trigger pin input (PDB0_EXTRG) #0000 0001 High speed comparator 0 output #0001 0010 High speed comparator 1 output #0010 0011 High speed comparator 2 output #0011 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 0110 PIT trigger 2 #0110 0111 PIT trigger 3 #0111 1000 FTM0 trigger #1000 1001 FTM1 trigger #1001 1010 FTM2 trigger #1010 1011 FTM3 trigger #1011 1100 High speed comparator 3 output #1100 1101 RTC interrupt #1101 1110 Unused #1110 1111 Unused #1111 ADC1TRGSEL ADC1 trigger select 4 4 read-write 0000 PDB external trigger pin input (PDB0_EXTRG) #0000 0001 High speed comparator 0 output #0001 0010 High speed comparator 1 output #0010 0011 High speed comparator 2 output #0011 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 0110 PIT trigger 2 #0110 0111 PIT trigger 3 #0111 1000 FTM0 trigger #1000 1001 FTM1 trigger #1001 1010 FTM2 trigger #1010 1011 FTM3 trigger #1011 1100 High speed comparator 3 output #1100 1101 RTC interrupt #1101 1110 Unused #1110 1111 Unused #1111 ADC2TRGSEL ADC2 trigger select 8 4 read-write 0000 PDB external trigger pin input (PDB0_EXTRG) #0000 0001 High speed comparator 0 output #0001 0010 High speed comparator 1 output #0010 0011 High speed comparator 2 output #0011 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 0110 PIT trigger 2 #0110 0111 PIT trigger 3 #0111 1000 FTM0 trigger #1000 1001 FTM1 trigger #1001 1010 FTM2 trigger #1010 1011 FTM3 trigger #1011 1100 High speed comparator 3 output #1100 1101 RTC interrupt #1101 1110 Unused #1110 1111 Unused #1111 ADC3TRGSEL ADC3 trigger select 12 4 read-write 0000 PDB external trigger pin input (PDB0_EXTRG) #0000 0001 High speed comparator 0 output #0001 0010 High speed comparator 1 output #0010 0011 High speed comparator 2 output #0011 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 0110 PIT trigger 2 #0110 0111 PIT trigger 3 #0111 1000 FTM0 trigger #1000 1001 FTM1 trigger #1001 1010 FTM2 trigger #1010 1011 FTM3 trigger #1011 1100 High speed comparator 3 output #1100 1101 RTC interrupt #1101 1110 Unused #1110 1111 Unused #1111 CMP0WS CMP0 windows select 16 2 read-write 00 PDB0. #00 01 PDB1. #01 10 PDB2. #10 11 PDB3. #11 CMP1WS CMP1 windows select 18 2 read-write 00 PDB0. #00 01 PDB1. #01 10 PDB2. #10 11 PDB3. #11 CMP2WS CMP2 windows select 20 2 read-write 00 PDB0. #00 01 PDB1. #01 10 PDB2. #10 11 PDB3. #11 CMP3WS CMP3 windows select 22 2 read-write 00 PDB0. #00 01 PDB1. #01 10 PDB2. #10 11 PDB3. #11 RESERVED no description available 24 4 read-only ADC0ALTTRGEN ADC0 alternate trigger enable 28 1 read-write 0 PDB trigger selected for ADC0. #0 1 Alternate trigger selected for ADC0. #1 ADC1ALTTRGEN ADC1 alternate trigger enable 29 1 read-write 0 PDB trigger selected for ADC1. #0 1 Alternate trigger selected for ADC1. #1 ADC2ALTTRGEN ADC2 alternate trigger enable 30 1 read-write 0 PDB trigger selected for ADC2 #0 1 Alternate trigger selected for ADC2 as defined by ADC2TRGSEL. #1 ADC3ALTTRGEN ADC3 alternate trigger enable 31 1 read-write 0 PDB trigger selected for ADC3 #0 1 Alternate trigger selected for ADC3 as defined by ADC3TRGSEL. #1 SDID System Device Identification Register 0x24 32 read-only 0 0 BOID Pincount identification 0 4 read-only 0000 Reserved #0000 0001 Reserved #0001 0010 Reserved #0010 0011 Reserved #0011 0100 44-pin #0100 0101 64-pin #0101 0110 80-pin #0110 0111 Reserved #0111 1000 100-pin #1000 DIEID Device family identification 4 2 read-only RESERVED no description available 6 6 read-only REVID Device revision number 12 4 read-only RESERVED no description available 16 16 read-only SCGC5 System Clock Gating Control Register 5 0x38 32 read-write 0xD00030 0xFFFFFFFF RESERVED no description available 0 1 read-only EWM EWM Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CMT CMT Clock Gate Control 2 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RESERVED no description available 3 4 read-only IIC0 IIC0 Clock Gate Control 7 1 read-write 0 Clock disabled #0 1 Clock enabled #1 IIC1 IIC1 Clock Gate Control 8 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART0 UART0 Clock Gate Control 9 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART1 UART1 Clock Gate Control 10 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART2 UART2 Clock Gate Control 11 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART3 UART3 Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RESERVED no description available 13 1 read-only SPI0 SPI0 Clock Gate Control 14 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SPI1 SPI1 Clock Gate Control 15 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ACMP0 ACMP0 Clock Gate Control 16 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ACMP1 ACMP1 Clock Gate Control 17 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ACMP2 ACMP2 Clock Gate Control 18 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ACMP3 ACMP3 Clock Gate Control 19 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RESERVED no description available 20 12 read-only SCGC6 System Clock Gating Control Register 6 0x3C 32 read-write 0x6040000 0xFFFFFFFF RESERVED no description available 0 1 read-only DMAMUX DMAMUX Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RESERVED no description available 2 1 read-only PIT PIT Clock Gate Control 3 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CRC CRC Clock Gate Control 4 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PDB0 PDB0 Clock Gate Control 5 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PDB1 PDB1 Clock Gate Control 6 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PDB2 PDB2 Clock Gate Control 7 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PDB3 PDB3 Clock Gate Control 8 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM0 FTM0 Clock Gate Control 9 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM1 FTM1 Clock Gate Control 10 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM2 FTM2 Clock Gate Control 11 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM3 FTM3 Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RTC RTC Clock Gate Control 13 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RESERVED no description available 14 2 read-only TSI TSI Clock Gate Control 16 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RESERVED no description available 17 1 read-only RESERVED no description available 18 1 read-only PORTA Port A Clock Gate Control 19 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTB Port B Clock Gate Control 20 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTC Port C Clock Gate Control 21 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTD Port D Clock Gate Control 22 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTE Port E Clock Gate Control 23 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RESERVED no description available 24 3 read-only ADC0 ADC0 Clock Gate Control 27 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ADC1 ADC1 Clock Gate Control 28 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ADC2 ADC2 Clock Gate Control 29 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ADC3 ADC3 Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RESERVED no description available 31 1 read-only SCGC7 System Clock Gating Control Register 7 0x40 32 read-write 0xF 0xFFFFFFFF FLEXBUS FlexBus Clock Gate Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 DMA DMA Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 MPU MPU Clock Gate Control 2 1 read-write 0 Clock disabled #0 1 Clock enabled #1 IEVT IEVT Clock Gate Control 3 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RESERVED no description available 4 28 read-only CLKDIV1 System Clock Divider Register 1 0x44 32 read-write 0x100000 0xFFFFFFFF RESERVED no description available 0 12 read-only OUTDIV5 Clock 5 output divider value 12 2 read-write 00 ICSOUT divided by 1. #00 01 ICSOUT divided by 2. #01 10 Reserved. #10 11 ICSOUT divided by 4. #11 RESERVED no description available 14 2 read-only OUTDIV4 Clock 4 output divider value 16 2 read-write 00 ICSOUT divided by 2. #00 01 ICSOUT divided by 4. #01 10 Reserved. #10 11 ICSOUT divided by 8. #11 RESERVED no description available 18 2 read-only OUTDIV3 Clock 3 output divider value 20 2 read-write 00 ICSOUT divided by 4, it is valid only when Maxclk = 36 MHz. #00 01 ICSOUT divided by 8. #01 10 Reserved. #10 11 ICSOUT divided by 16, it is valid only when Maxclk = 36 MHz. #11 RESERVED no description available 22 2 read-only OUTDIV2 Clock 2 output divider value 24 2 read-write 00 ICSOUT divided by 2. #00 01 ICSOUT divided by 4. #01 10 Reserved. #10 11 ICSOUT divided by 8. #11 RESERVED no description available 26 2 read-only OUTDIV1 Clock 1 output divider value 28 2 read-write 00 ICSOUT Divided by 1. #00 01 ICSOUT Divided by 2. #01 10 Reserved. #10 11 ICSOUT Divided by 4. #11 RESERVED no description available 30 2 read-only UIDH Unique Identification Register High 0x54 32 read-only 0 0 UID Unique Identification 0 32 read-only UIDMH Unique Identification Register Mid-High 0x58 32 read-only 0 0 UID Unique Identification 0 32 read-only UIDML Unique Identification Register Mid Low 0x5C 32 read-only 0 0 UID Unique Identification (bits [63:32] 0 32 read-only UIDL Unique Identification Register Low 0x60 32 read-only 0 0 UID Unique Identification 0 32 read-only PORTA Pin Control and Interrupts PORT PORTA_ 0x40033000 0 0xCC registers 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0 0 RESERVED no description available 0 1 read-only PE Pull Enable 1 1 read-write 0 Internal pullup resistor is not enabled on the corresponding pin. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 RESERVED no description available 2 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 5 1 read-only RESERVED no description available 6 1 read-only RESERVED no description available 7 1 read-only MUX Pin Mux Control 8 3 read-write 000 Pin disabled (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 RESERVED no description available 11 4 read-only LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA request disabled. #0000 0001 DMA request on rising edge. #0001 0010 DMA request on falling edge. #0010 0011 DMA request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 RESERVED no description available 20 4 read-only ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 RESERVED no description available 25 7 read-only GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 DFER Digital Filter Enable Register 0xC0 32 read-write 0 0xFFFFFFFF DFE Digital Filter Enable 0 32 read-write 0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the field. #0 1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DFCR Digital Filter Clock Register 0xC4 32 read-write 0 0xFFFFFFFF CS Clock Source 0 1 read-write 0 Digital filters are clocked by the bus clock. #0 1 Digital filters are clocked by the 1 kHz LPO clock. #1 RESERVED no description available 1 31 read-only DFWR Digital Filter Width Register 0xC8 32 read-write 0 0xFFFFFFFF FILT Filter Length 0 5 read-write RESERVED no description available 5 27 read-only PORTB Pin Control and Interrupts PORT PORTB_ 0x40034000 0 0xCC registers 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0 0 RESERVED no description available 0 1 read-only PE Pull Enable 1 1 read-write 0 Internal pullup resistor is not enabled on the corresponding pin. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 RESERVED no description available 2 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 5 1 read-only RESERVED no description available 6 1 read-only RESERVED no description available 7 1 read-only MUX Pin Mux Control 8 3 read-write 000 Pin disabled (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 RESERVED no description available 11 4 read-only LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA request disabled. #0000 0001 DMA request on rising edge. #0001 0010 DMA request on falling edge. #0010 0011 DMA request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 RESERVED no description available 20 4 read-only ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 RESERVED no description available 25 7 read-only GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 DFER Digital Filter Enable Register 0xC0 32 read-write 0 0xFFFFFFFF DFE Digital Filter Enable 0 32 read-write 0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the field. #0 1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DFCR Digital Filter Clock Register 0xC4 32 read-write 0 0xFFFFFFFF CS Clock Source 0 1 read-write 0 Digital filters are clocked by the bus clock. #0 1 Digital filters are clocked by the 1 kHz LPO clock. #1 RESERVED no description available 1 31 read-only DFWR Digital Filter Width Register 0xC8 32 read-write 0 0xFFFFFFFF FILT Filter Length 0 5 read-write RESERVED no description available 5 27 read-only PORTC Pin Control and Interrupts PORT PORTC_ 0x40035000 0 0xCC registers 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0 0 RESERVED no description available 0 1 read-only PE Pull Enable 1 1 read-write 0 Internal pullup resistor is not enabled on the corresponding pin. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 RESERVED no description available 2 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 5 1 read-only RESERVED no description available 6 1 read-only RESERVED no description available 7 1 read-only MUX Pin Mux Control 8 3 read-write 000 Pin disabled (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 RESERVED no description available 11 4 read-only LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA request disabled. #0000 0001 DMA request on rising edge. #0001 0010 DMA request on falling edge. #0010 0011 DMA request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 RESERVED no description available 20 4 read-only ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 RESERVED no description available 25 7 read-only GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 DFER Digital Filter Enable Register 0xC0 32 read-write 0 0xFFFFFFFF DFE Digital Filter Enable 0 32 read-write 0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the field. #0 1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DFCR Digital Filter Clock Register 0xC4 32 read-write 0 0xFFFFFFFF CS Clock Source 0 1 read-write 0 Digital filters are clocked by the bus clock. #0 1 Digital filters are clocked by the 1 kHz LPO clock. #1 RESERVED no description available 1 31 read-only DFWR Digital Filter Width Register 0xC8 32 read-write 0 0xFFFFFFFF FILT Filter Length 0 5 read-write RESERVED no description available 5 27 read-only PORTD Pin Control and Interrupts PORT PORTD_ 0x40036000 0 0xCC registers 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0 0 RESERVED no description available 0 1 read-only PE Pull Enable 1 1 read-write 0 Internal pullup resistor is not enabled on the corresponding pin. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 RESERVED no description available 2 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 5 1 read-only RESERVED no description available 6 1 read-only RESERVED no description available 7 1 read-only MUX Pin Mux Control 8 3 read-write 000 Pin disabled (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 RESERVED no description available 11 4 read-only LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA request disabled. #0000 0001 DMA request on rising edge. #0001 0010 DMA request on falling edge. #0010 0011 DMA request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 RESERVED no description available 20 4 read-only ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 RESERVED no description available 25 7 read-only GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 DFER Digital Filter Enable Register 0xC0 32 read-write 0 0xFFFFFFFF DFE Digital Filter Enable 0 32 read-write 0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the field. #0 1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DFCR Digital Filter Clock Register 0xC4 32 read-write 0 0xFFFFFFFF CS Clock Source 0 1 read-write 0 Digital filters are clocked by the bus clock. #0 1 Digital filters are clocked by the 1 kHz LPO clock. #1 RESERVED no description available 1 31 read-only DFWR Digital Filter Width Register 0xC8 32 read-write 0 0xFFFFFFFF FILT Filter Length 0 5 read-write RESERVED no description available 5 27 read-only PORTE Pin Control and Interrupts PORT PORTE_ 0x40037000 0 0xCC registers 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0 0 RESERVED no description available 0 1 read-only PE Pull Enable 1 1 read-write 0 Internal pullup resistor is not enabled on the corresponding pin. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 RESERVED no description available 2 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 5 1 read-only RESERVED no description available 6 1 read-only RESERVED no description available 7 1 read-only MUX Pin Mux Control 8 3 read-write 000 Pin disabled (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 RESERVED no description available 11 4 read-only LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA request disabled. #0000 0001 DMA request on rising edge. #0001 0010 DMA request on falling edge. #0010 0011 DMA request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 RESERVED no description available 20 4 read-only ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 RESERVED no description available 25 7 read-only GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 DFER Digital Filter Enable Register 0xC0 32 read-write 0 0xFFFFFFFF DFE Digital Filter Enable 0 32 read-write 0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the field. #0 1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DFCR Digital Filter Clock Register 0xC4 32 read-write 0 0xFFFFFFFF CS Clock Source 0 1 read-write 0 Digital filters are clocked by the bus clock. #0 1 Digital filters are clocked by the 1 kHz LPO clock. #1 RESERVED no description available 1 31 read-only DFWR Digital Filter Width Register 0xC8 32 read-write 0 0xFFFFFFFF FILT Filter Length 0 5 read-write RESERVED no description available 5 27 read-only FTMRA FTMRA Family Flash Module FTMRA_ 0x40039000 0 0x12 registers INT_FTMRA 34 FSEC Flash Security Register 0 8 read-only 0 0 SEC Flash Security 0 2 read-only 00 MCU security status is secure #00 01 MCU security status is secure,it is the preferred SEC state to set MCU to secured state #01 10 MCU security status is unsecure #10 11 MCU security status is secure #11 RNV Reserved Nonvolatile Bits 2 4 read-only KEYEN Backdoor Key Security Enable 6 2 read-only 00 Backdoor key access disabled #00 01 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) #01 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 FCLKDIV Flash Clock Divider Register 0x1 8 read-write 0 0xFF FDIV Clock Divider Bits 0 7 read-write FDIVLD Clock Divider Loaded 7 1 read-only 0 FCLKDIV register has not been written. #0 1 FCLKDIV register has been written since the last reset. #1 FECCRIX Flash ECCR Index Register 0x2 8 read-write 0 0xFF ECCRIX ECC Error Register Index 0 3 read-write RESERVED no description available 3 5 read-only FCCOBIX Flash Common Command Object Index Register 0x3 8 read-write 0 0xFF CCOBIX Common Command Register Index 0 3 read-write RESERVED no description available 3 5 read-only FERCNFG Flash Error Configuration Register 0x4 8 read-write 0 0xFF SFDIE Single Bit Fault Detect Interrupt Enable 0 1 read-write 0 SFDIF interrupt disabled whenever the SFDIF flag is set #0 1 An interrupt will be requested whenever the SFDIF flag is set #1 DFDIE Double Bit Fault Detect Interrupt Enable 1 1 read-write 0 SFDIF interrupt disabled whenever the SFDIF flag is set #0 1 An interrupt will be requested whenever the SFDIF flag is set #1 RESERVED no description available 2 6 read-only FCNFG Flash Configuration Register 0x5 8 read-write 0 0xFF FSFD Force Single Bit Fault Detect 0 1 read-write 0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected #0 1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 1.3.2.7) and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set #1 FDFD Force Double Bit Fault Detect 1 1 read-write 0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected #0 1 Any flash array read operation will force the FERSTAT[DFDIF] flag to be set and an interrupt will be generated as long as the FERCNFG[DFDIE] is set #1 RESERVED no description available 2 2 read-only IGNSF Ignore Single Bit Fault 4 1 read-write 0 All single bit faults detected during array reads are reported #0 1 Single bit faults detected during array reads are not reported and the single bit fault interrupt is not generated #1 ERSAREQ Erase All Request 5 1 read-only 0 No request or request complete #0 1 Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state. #1 RESERVED no description available 6 1 read-only CCIE Command Complete Interrupt Enable 7 1 read-write 0 Command complete interrupt disabled #0 1 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. #1 FERSTAT Flash Error Status Register 0x6 8 read-write 0 0xFF SFDIF Single Bit Fault Detect Interrupt Flag 0 1 read-write 0 No single bit fault detected #0 1 Single bit fault detected and corrected or an invalid Flash array read operation attempted #1 DFDIF Double Bit Fault Detect Interrupt Flag 1 1 read-write 0 No double bit fault detected #0 1 Double bit fault detected or an invalid Flash array read operation attempted #1 RESERVED no description available 2 6 read-only FSTAT Flash Status Register 0x7 8 read-write 0 0xFF MGSTAT MGATE Command Completion Status Flag 0 2 read-only RESERVED no description available 2 1 read-only MGBUSY MGATE Busy Flag 3 1 read-only 0 MGATE is idle #0 1 MGATE is busy executing a Flash command (CCIF = 0) #1 FPVIOL Flash Protection Violation Flag 4 1 read-write 0 No protection violation detected #0 1 Protection violation detected #1 ACCERR Flash Access Error Flag 5 1 read-write 0 No access error detected #0 1 Access error detected #1 RESERVED no description available 6 1 read-only CCIF Command Complete Interrupt Flag 7 1 read-write 0 Flash command in progress #0 1 Flash command has completed #1 DFPROT D-Flash Protection Register 0x8 8 read-write 0 0xFF DPS EraseD-Flash Protection Size 0 5 read-write 00000 Flash address range: 0x00_0000 - 0x00_00FF; protected size: 256 bytes #00000 00001 Flash address range: 0x00_0000 - 0x00_01FF; protected size: 512 bytes #00001 00010 Flash address range: 0x00_0000 - 0x00_02FF; protected size: 768 bytes #00010 00011 Flash address range: 0x00_0000 - 0x00_03FF; protected size: 1024 bytes #00011 00100 Flash address range: 0x00_0000 - 0x00_04FF; protected size: 1280 bytes #00100 00101 Flash address range: 0x00_0000 - 0x00_05FF; protected size: 1536 bytes #00101 00110 Flash address range: 0x00_0000 - 0x00_06FF; protected size: 1792 bytes #00110 00111 Flash address range: 0x00_0000 - 0x00_07FF; protected size: 2048 bytes #00111 01000 Flash address range: 0x00_0000 - 0x00_08FF; protected size: 2304 bytes #01000 01001 Flash address range: 0x00_0000 - 0x00_09FF; protected size: 2560 bytes #01001 01010 Flash address range: 0x00_0000 - 0x00_0AFF; protected size: 2816 bytes #01010 01011 Flash address range: 0x00_0000 - 0x00_0BFF; protected size: 3072 bytes #01011 01100 Flash address range: 0x00_0000 - 0x00_0CFF; protected size: 3328 bytes #01100 01101 Flash address range: 0x00_0000 - 0x00_0DFF; protected size: 3584 bytes #01101 01110 Flash address range: 0x00_0000 - 0x00_0EFF; protected size: 3840 bytes #01110 01111 Flash address range: 0x00_0000 - 0x00_0FFF; protected size: 4096 bytes #01111 10000 Flash address range: 0x00_0000 - 0x00_10FF; protected size: 4352 bytes #10000 10001 Flash address range: 0x00_0000 - 0x00_11FF; protected size: 4608 bytes #10001 10010 Flash address range: 0x00_0000 - 0x00_12FF; protected size: 4864 bytes #10010 10011 Flash address range: 0x00_0000 - 0x00_13FF; protected size: 5120 bytes #10011 10100 Flash address range: 0x00_0000 - 0x00_14FF; protected size: 5376 bytes #10100 10101 Flash address range: 0x00_0000 - 0x00_15FF; protected size: 5632 bytes #10101 10110 Flash address range: 0x00_0000 - 0x00_16FF; protected size: 5888 bytes #10110 10111 Flash address range: 0x00_0000 - 0x00_17FF; protected size: 6144 bytes #10111 11000 Flash address range: 0x00_0000 - 0x00_18FF; protected size: 6400 bytes #11000 11001 Flash address range: 0x00_0000 - 0x00_19FF; protected size: 6656 bytes #11001 11010 Flash address range: 0x00_0000 - 0x00_1AFF; protected size: 6912 bytes #11010 11011 Flash address range: 0x00_0000 - 0x00_1BFF; protected size: 7168 bytes #11011 11100 Flash address range: 0x00_0000 - 0x00_1CFF; protected size: 7424 bytes #11100 11101 Flash address range: 0x00_0000 - 0x00_1DFF; protected size: 7680 bytes #11101 11110 Flash address range: 0x00_0000 - 0x00_1EFF; protected size: 7936 bytes #11110 11111 Flash address range: 0x00_0000 - 0x00_1FFF; protected size: 8192 bytes #11111 RESERVED no description available 5 2 read-only DPOPEN D-Flash Protection Control 7 1 read-write 0 Enables D-Flash memory protection from program and erase with protected address range defined by DPS bits #0 1 Disables D-Flash memory protection from program and erase #1 FPROT P-Flash Protection Register 0x9 8 read-write 0 0 FPLS Flash Protection Lower Address Size 0 2 read-write 00 Address range: 0x00_0000-0x00_07FF; protected size: 2 KB #00 01 Address range: 0x00_0000-0x00_0FFF; protected size: 4 KB #01 10 Address range: 0x00_0000-0x00_1FFF; protected size: 8 KB #10 11 Address range: 0x00_0000-0x00_3FFF; protected size: 16 KB #11 FPLDIS Flash Protection Lower Address Range Disable 2 1 read-write 0 Protection/Unprotection enabled #0 1 Protection/Unprotection disabled #1 FPHS Flash Protection Higher Address Size 3 2 read-write 00 Address range: 0x00_7C00-0x00_7FFF; protected size: 1 KB #00 01 Address range: 0x00_7800-0x00_7FFF; protected size: 2 KB #01 10 Address range: 0x00_7000-0x00_7FFF; protected size: 4 KB #10 11 Address range: 0x00_6000-0x00_7FFF; protected size: 8 KB #11 FPHDIS Flash Protection Higher Address Range Disable 5 1 read-write 0 Protection/Unprotection enabled #0 1 Protection/Unprotection disabled #1 RNV Reserved Nonvolatile Bit 6 1 read-only FPOPEN Flash Protection Operation Enable 7 1 read-write 0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS and FPLS bits #0 1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS and FPLS bits #1 FCCOBLO Flash Common Command Object Low Register 0xA 8 read-write 0 0xFF CCOBn no description available 0 8 read-write FCCOBHI Flash Common Command Object High Register 0xB 8 read-write 0 0xFF CCOBn no description available 0 8 read-write FECCRLO Flash ECC Error Results Low Register 0xE 8 read-only 0 0xFF ECCR no description available 0 8 read-only FECCRHI Flash ECC Error Results High Register 0xF 8 read-only 0 0xFF ECCR no description available 0 8 read-only FOPT Flash Option Register 0x11 8 read-only 0 0 NV Nonvolatile Bits 0 8 read-only WDOG Generation 2008 Watchdog Timer WDOG_ 0x4003A000 0 0x18 registers INT_Watchdog 38 STCTRLH Watchdog Status and Control Register High 0 16 read-write 0x1D3 0xFFFF WDOGEN no description available 0 1 read-write 0 WDOG is disabled. #0 1 WDOG is enabled. #1 CLKSRC no description available 1 1 read-write 0 WDOG clock sourced from LPO . #0 1 WDOG clock sourced from alternate clock source. #1 IRQRSTEN no description available 2 1 read-write 0 WDOG time-out generates reset only. #0 1 WDOG time-out initially generates an interrupt. After WCT, it generates a reset. #1 WINEN no description available 3 1 read-write 0 Windowing mode is disabled. #0 1 Windowing mode is enabled. #1 ALLOWUPDATE no description available 4 1 read-write 0 No further updates allowed to WDOG write-once registers. #0 1 WDOG write-once registers can be unlocked for updating. #1 DBGEN no description available 5 1 read-write 0 WDOG is disabled in CPU Debug mode. #0 1 WDOG is enabled in CPU Debug mode. #1 STOPEN no description available 6 1 read-write 0 WDOG is disabled in CPU Stop mode. #0 1 WDOG is enabled in CPU Stop mode. #1 WAITEN no description available 7 1 read-write 0 WDOG is disabled in CPU Wait mode. #0 1 WDOG is enabled in CPU Wait mode. #1 STNDBYEN no description available 8 1 read-write 0 WDOG is disabled in system Standby mode. #0 1 WDOG is enabled in system Standby mode. #1 RESERVED no description available 9 1 read-only TESTWDOG no description available 10 1 read-write TESTSEL no description available 11 1 read-write 0 Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test. #0 1 Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing. #1 BYTESEL no description available 12 2 read-write 00 Byte 0 selected #00 01 Byte 1 selected #01 10 Byte 2 selected #10 11 Byte 3 selected #11 DISTESTWDOG no description available 14 1 read-write 0 WDOG functional test mode is not disabled. #0 1 WDOG functional test mode is disabled permanently until reset. #1 RESERVED no description available 15 1 read-only STCTRLL Watchdog Status and Control Register Low 0x2 16 read-write 0x1 0xFFFF RESERVED no description available 0 15 read-write INTFLG no description available 15 1 read-write TOVALH Watchdog Time-out Value Register High 0x4 16 read-write 0x4C 0xFFFF TOVALHIGH no description available 0 16 read-write TOVALL Watchdog Time-out Value Register Low 0x6 16 read-write 0x4B4C 0xFFFF TOVALLOW no description available 0 16 read-write WINH Watchdog Window Register High 0x8 16 read-write 0 0xFFFF WINHIGH no description available 0 16 read-write WINL Watchdog Window Register Low 0xA 16 read-write 0x10 0xFFFF WINLOW no description available 0 16 read-write REFRESH Watchdog Refresh register 0xC 16 read-write 0xB480 0xFFFF WDOGREFRESH no description available 0 16 read-write UNLOCK Watchdog Unlock register 0xE 16 read-write 0xD928 0xFFFF WDOGUNLOCK no description available 0 16 read-write TMROUTH Watchdog Timer Output Register High 0x10 16 read-write 0 0xFFFF TIMEROUTHIGH no description available 0 16 read-write TMROUTL Watchdog Timer Output Register Low 0x12 16 read-write 0 0xFFFF TIMEROUTLOW no description available 0 16 read-write RSTCNT Watchdog Reset Count register 0x14 16 read-write 0 0xFFFF RSTCNT no description available 0 16 read-write PRESC Watchdog Prescaler register 0x16 16 read-write 0x400 0xFFFF RESERVED no description available 0 8 read-only PRESCVAL no description available 8 3 read-write RESERVED no description available 11 5 read-only ADC0 Analog-to-digital converter ADC ADC0_ 0x4003B000 0 0x10 registers SC1 Status and Control Register 1 0 16 read-write 0x1F 0xFFFF ADCH Input Channel Select 0 5 read-write 00000 AD0 #00000 00001 AD1 #00001 00010 AD2 #00010 00011 AD3 #00011 00100 AD4 #00100 00101 AD5 #00101 00110 AD6 #00110 00111 AD7 #00111 01000 AD8 #01000 01001 AD9 #01001 01010 AD10 #01010 01011 AD11 #01011 11111 Module disabled Reset FIFO in FIFO mode. #11111 ADCO Continuous Conversion Enable 5 1 read-write 0 One conversion following a write to the ADCSC1 when software triggered operation is selected, or one conversion following assertion of ADHWT when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversions are triggerd. #0 1 Continuous conversions initiated following a write to ADCSC1 when software triggered operation is selected. Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversions are loop triggered. #1 AIEN Interrupt Enable 6 1 read-write 0 Conversion complete interrupt disabled. #0 1 Conversion complete interrupt enabled. #1 COCO Conversion Complete Flag 7 1 read-only 0 Conversion not completed. #0 1 Conversion completed. #1 RESERVED no description available 8 8 read-only SC2 Status and Control Register 2 0x2 16 read-write 0x8 0xFFFF RESERVED no description available 0 2 read-only FFULL Result FIFO full 2 1 read-only 0 Indicates that ADC result fifo is not full and next conversion data still can be stored into fifo. #0 1 Indicates that ADC result fifo is full and next conversion will override old data if no read action. #1 FEMPTY Result FIFO empty 3 1 read-only 0 Indicates that ADC result fifo have at least one valid new data. #0 1 Indicates that ADC result fifo have no valid new data. #1 ACDSEL Compare Data Selection 4 1 read-write 0 Compare value is from the conversion result and ADC_CVA. #0 1 Compare value is from the conversion result and ADC_CVB. #1 ACFE Compare Function Enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ADTRG Conversion Trigger Select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 ADACT Conversion Active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 RESERVED no description available 8 8 read-only SC3 Status and Control Register 3 0x4 16 read-write 0 0xFFFF ADICLK Input Clock Select 0 2 read-write 00 Bus clock #00 01 Bus clock divided by 2 #01 10 Alternate clock (ALTCLK) #10 11 Asynchronous clock (ADACK) #11 MODE Conversion Mode Selection 2 2 read-write 00 8-bit conversion (N=8) #00 01 10-bit conversion (N=10) #01 10 12-bit conversion (N=12) #10 11 Reserved #11 ADLSMP Long Sample Time Configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 ADIV Clock Divide Select 5 2 read-write 00 Divide ration = 1, and clock rate = Input clock. #00 01 Divide ration = 2, and clock rate = Input clock * 2. #01 10 Divide ration = 3, and clock rate = Input clock * 4. #10 11 Divide ration = 4, and clock rate = Input clock * 8. #11 ADLPC Low-Power Configuration 7 1 read-write 0 High speed configuration. #0 1 Low power configuration:The power is reduced at the expense of maximum clock speed.. #1 RESERVED no description available 8 8 read-only SC4 Status and Control Register 4 0x6 16 read-write 0 0xFFFF AFDEP no description available 0 3 read-write 000 FIFO is disabled. #000 001 2-level FIFO is enabled. #001 010 3-level FIFO is enabled.. #010 011 4-level FIFO is enabled. #011 100 5-level FIFO is enabled. #100 101 6-level FIFO is enabled. #101 110 7-level FIFO is enabled. #110 111 8-level FIFO is enabled. #111 RESERVED no description available 3 2 read-only ACFSEL no description available 5 1 read-write 0 OR all of compare trigger. #0 1 AND all of compare trigger. #1 ASCANE no description available 6 1 read-write 0 FIFO scan mode disabled. #0 1 FIFO scan mode enabled. #1 DMAEN DMA Enable 7 1 read-write 0 DMA read request is disabled. #0 1 DMA read request is enabled, the conversion complete flag will assert the DMA request signal. #1 RESERVED no description available 8 8 read-only R Conversion Result Register 0x8 16 read-only 0 0xFFFF ADR Conversion Result 0 16 read-only CVA Compare Value Register A 0xA 16 read-write 0 0xFFFF VA Lower limit compare value 0 16 read-write CVB Compare Value Register B 0xC 16 read-write 0 0xFFFF VB Upper limit compare value 0 16 read-write APCTL Pin Control Register 0xE 16 read-write 0 0xFFFF ADPC0 ADC Pin Control 0 0 1 read-write 0 AD0 pin I/O control enabled. #0 1 AD0 pin I/O control disabled. #1 ADPC1 ADC Pin Control 1 1 1 read-write 0 AD1 pin I/O control enabled. #0 1 AD1 pin I/O control disabled. #1 ADPC2 ADC Pin Control 2 2 1 read-write 0 AD2 pin I/O control enabled. #0 1 AD2 pin I/O control disabled. #1 ADPC3 ADC Pin Control 3 3 1 read-write 0 AD3 pin I/O control enabled. #0 1 AD3 pin I/O control disabled. #1 ADPC4 ADC Pin Control 4 4 1 read-write 0 AD4 pin I/O control enabled. #0 1 AD4 pin I/O control disabled. #1 ADPC5 ADC Pin Control 5 5 1 read-write 0 AD5 pin I/O control enabled. #0 1 AD5 pin I/O control disabled. #1 ADPC6 ADC Pin Control 6 6 1 read-write 0 AD6 pin I/O control enabled. #0 1 AD6 pin I/O control disabled. #1 ADPC7 ADC Pin Control 7 7 1 read-write 0 AD7 pin I/O control enabled. #0 1 AD7 pin I/O control disabled. #1 ADPC8 ADC Pin Control 8 8 1 read-write 0 AD8 pin I/O control enabled. #0 1 AD8 pin I/O control disabled. #1 ADPC9 ADC Pin Control 9 9 1 read-write 0 AD9 pin I/O control enabled. #0 1 AD9 pin I/O control disabled. #1 ADPC10 ADC Pin Control 10 10 1 read-write 0 AD10 pin I/O control enabled. #0 1 AD10 pin I/O control disabled. #1 ADPC11 ADC Pin Control 11 11 1 read-write 0 AD11 pin I/O control enabled. #0 1 AD11 pin I/O control disabled. #1 RESERVED no description available 12 4 read-only ADC1 Analog-to-digital converter ADC ADC1_ 0x4003C000 0 0x10 registers SC1 Status and Control Register 1 0 16 read-write 0x1F 0xFFFF ADCH Input Channel Select 0 5 read-write 00000 AD0 #00000 00001 AD1 #00001 00010 AD2 #00010 00011 AD3 #00011 00100 AD4 #00100 00101 AD5 #00101 00110 AD6 #00110 00111 AD7 #00111 01000 AD8 #01000 01001 AD9 #01001 01010 AD10 #01010 01011 AD11 #01011 11111 Module disabled Reset FIFO in FIFO mode. #11111 ADCO Continuous Conversion Enable 5 1 read-write 0 One conversion following a write to the ADCSC1 when software triggered operation is selected, or one conversion following assertion of ADHWT when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversions are triggerd. #0 1 Continuous conversions initiated following a write to ADCSC1 when software triggered operation is selected. Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversions are loop triggered. #1 AIEN Interrupt Enable 6 1 read-write 0 Conversion complete interrupt disabled. #0 1 Conversion complete interrupt enabled. #1 COCO Conversion Complete Flag 7 1 read-only 0 Conversion not completed. #0 1 Conversion completed. #1 RESERVED no description available 8 8 read-only SC2 Status and Control Register 2 0x2 16 read-write 0x8 0xFFFF RESERVED no description available 0 2 read-only FFULL Result FIFO full 2 1 read-only 0 Indicates that ADC result fifo is not full and next conversion data still can be stored into fifo. #0 1 Indicates that ADC result fifo is full and next conversion will override old data if no read action. #1 FEMPTY Result FIFO empty 3 1 read-only 0 Indicates that ADC result fifo have at least one valid new data. #0 1 Indicates that ADC result fifo have no valid new data. #1 ACDSEL Compare Data Selection 4 1 read-write 0 Compare value is from the conversion result and ADC_CVA. #0 1 Compare value is from the conversion result and ADC_CVB. #1 ACFE Compare Function Enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ADTRG Conversion Trigger Select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 ADACT Conversion Active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 RESERVED no description available 8 8 read-only SC3 Status and Control Register 3 0x4 16 read-write 0 0xFFFF ADICLK Input Clock Select 0 2 read-write 00 Bus clock #00 01 Bus clock divided by 2 #01 10 Alternate clock (ALTCLK) #10 11 Asynchronous clock (ADACK) #11 MODE Conversion Mode Selection 2 2 read-write 00 8-bit conversion (N=8) #00 01 10-bit conversion (N=10) #01 10 12-bit conversion (N=12) #10 11 Reserved #11 ADLSMP Long Sample Time Configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 ADIV Clock Divide Select 5 2 read-write 00 Divide ration = 1, and clock rate = Input clock. #00 01 Divide ration = 2, and clock rate = Input clock * 2. #01 10 Divide ration = 3, and clock rate = Input clock * 4. #10 11 Divide ration = 4, and clock rate = Input clock * 8. #11 ADLPC Low-Power Configuration 7 1 read-write 0 High speed configuration. #0 1 Low power configuration:The power is reduced at the expense of maximum clock speed.. #1 RESERVED no description available 8 8 read-only SC4 Status and Control Register 4 0x6 16 read-write 0 0xFFFF AFDEP no description available 0 3 read-write 000 FIFO is disabled. #000 001 2-level FIFO is enabled. #001 010 3-level FIFO is enabled.. #010 011 4-level FIFO is enabled. #011 100 5-level FIFO is enabled. #100 101 6-level FIFO is enabled. #101 110 7-level FIFO is enabled. #110 111 8-level FIFO is enabled. #111 RESERVED no description available 3 2 read-only ACFSEL no description available 5 1 read-write 0 OR all of compare trigger. #0 1 AND all of compare trigger. #1 ASCANE no description available 6 1 read-write 0 FIFO scan mode disabled. #0 1 FIFO scan mode enabled. #1 DMAEN DMA Enable 7 1 read-write 0 DMA read request is disabled. #0 1 DMA read request is enabled, the conversion complete flag will assert the DMA request signal. #1 RESERVED no description available 8 8 read-only R Conversion Result Register 0x8 16 read-only 0 0xFFFF ADR Conversion Result 0 16 read-only CVA Compare Value Register A 0xA 16 read-write 0 0xFFFF VA Lower limit compare value 0 16 read-write CVB Compare Value Register B 0xC 16 read-write 0 0xFFFF VB Upper limit compare value 0 16 read-write APCTL Pin Control Register 0xE 16 read-write 0 0xFFFF ADPC0 ADC Pin Control 0 0 1 read-write 0 AD0 pin I/O control enabled. #0 1 AD0 pin I/O control disabled. #1 ADPC1 ADC Pin Control 1 1 1 read-write 0 AD1 pin I/O control enabled. #0 1 AD1 pin I/O control disabled. #1 ADPC2 ADC Pin Control 2 2 1 read-write 0 AD2 pin I/O control enabled. #0 1 AD2 pin I/O control disabled. #1 ADPC3 ADC Pin Control 3 3 1 read-write 0 AD3 pin I/O control enabled. #0 1 AD3 pin I/O control disabled. #1 ADPC4 ADC Pin Control 4 4 1 read-write 0 AD4 pin I/O control enabled. #0 1 AD4 pin I/O control disabled. #1 ADPC5 ADC Pin Control 5 5 1 read-write 0 AD5 pin I/O control enabled. #0 1 AD5 pin I/O control disabled. #1 ADPC6 ADC Pin Control 6 6 1 read-write 0 AD6 pin I/O control enabled. #0 1 AD6 pin I/O control disabled. #1 ADPC7 ADC Pin Control 7 7 1 read-write 0 AD7 pin I/O control enabled. #0 1 AD7 pin I/O control disabled. #1 ADPC8 ADC Pin Control 8 8 1 read-write 0 AD8 pin I/O control enabled. #0 1 AD8 pin I/O control disabled. #1 ADPC9 ADC Pin Control 9 9 1 read-write 0 AD9 pin I/O control enabled. #0 1 AD9 pin I/O control disabled. #1 ADPC10 ADC Pin Control 10 10 1 read-write 0 AD10 pin I/O control enabled. #0 1 AD10 pin I/O control disabled. #1 ADPC11 ADC Pin Control 11 11 1 read-write 0 AD11 pin I/O control enabled. #0 1 AD11 pin I/O control disabled. #1 RESERVED no description available 12 4 read-only ADC2 Analog-to-digital converter ADC ADC2_ 0x4003D000 0 0x10 registers SC1 Status and Control Register 1 0 16 read-write 0x1F 0xFFFF ADCH Input Channel Select 0 5 read-write 00000 AD0 #00000 00001 AD1 #00001 00010 AD2 #00010 00011 AD3 #00011 00100 AD4 #00100 00101 AD5 #00101 00110 AD6 #00110 00111 AD7 #00111 01000 AD8 #01000 01001 AD9 #01001 01010 AD10 #01010 01011 AD11 #01011 11111 Module disabled Reset FIFO in FIFO mode. #11111 ADCO Continuous Conversion Enable 5 1 read-write 0 One conversion following a write to the ADCSC1 when software triggered operation is selected, or one conversion following assertion of ADHWT when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversions are triggerd. #0 1 Continuous conversions initiated following a write to ADCSC1 when software triggered operation is selected. Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversions are loop triggered. #1 AIEN Interrupt Enable 6 1 read-write 0 Conversion complete interrupt disabled. #0 1 Conversion complete interrupt enabled. #1 COCO Conversion Complete Flag 7 1 read-only 0 Conversion not completed. #0 1 Conversion completed. #1 RESERVED no description available 8 8 read-only SC2 Status and Control Register 2 0x2 16 read-write 0x8 0xFFFF RESERVED no description available 0 2 read-only FFULL Result FIFO full 2 1 read-only 0 Indicates that ADC result fifo is not full and next conversion data still can be stored into fifo. #0 1 Indicates that ADC result fifo is full and next conversion will override old data if no read action. #1 FEMPTY Result FIFO empty 3 1 read-only 0 Indicates that ADC result fifo have at least one valid new data. #0 1 Indicates that ADC result fifo have no valid new data. #1 ACDSEL Compare Data Selection 4 1 read-write 0 Compare value is from the conversion result and ADC_CVA. #0 1 Compare value is from the conversion result and ADC_CVB. #1 ACFE Compare Function Enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ADTRG Conversion Trigger Select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 ADACT Conversion Active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 RESERVED no description available 8 8 read-only SC3 Status and Control Register 3 0x4 16 read-write 0 0xFFFF ADICLK Input Clock Select 0 2 read-write 00 Bus clock #00 01 Bus clock divided by 2 #01 10 Alternate clock (ALTCLK) #10 11 Asynchronous clock (ADACK) #11 MODE Conversion Mode Selection 2 2 read-write 00 8-bit conversion (N=8) #00 01 10-bit conversion (N=10) #01 10 12-bit conversion (N=12) #10 11 Reserved #11 ADLSMP Long Sample Time Configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 ADIV Clock Divide Select 5 2 read-write 00 Divide ration = 1, and clock rate = Input clock. #00 01 Divide ration = 2, and clock rate = Input clock * 2. #01 10 Divide ration = 3, and clock rate = Input clock * 4. #10 11 Divide ration = 4, and clock rate = Input clock * 8. #11 ADLPC Low-Power Configuration 7 1 read-write 0 High speed configuration. #0 1 Low power configuration:The power is reduced at the expense of maximum clock speed.. #1 RESERVED no description available 8 8 read-only SC4 Status and Control Register 4 0x6 16 read-write 0 0xFFFF AFDEP no description available 0 3 read-write 000 FIFO is disabled. #000 001 2-level FIFO is enabled. #001 010 3-level FIFO is enabled.. #010 011 4-level FIFO is enabled. #011 100 5-level FIFO is enabled. #100 101 6-level FIFO is enabled. #101 110 7-level FIFO is enabled. #110 111 8-level FIFO is enabled. #111 RESERVED no description available 3 2 read-only ACFSEL no description available 5 1 read-write 0 OR all of compare trigger. #0 1 AND all of compare trigger. #1 ASCANE no description available 6 1 read-write 0 FIFO scan mode disabled. #0 1 FIFO scan mode enabled. #1 DMAEN DMA Enable 7 1 read-write 0 DMA read request is disabled. #0 1 DMA read request is enabled, the conversion complete flag will assert the DMA request signal. #1 RESERVED no description available 8 8 read-only R Conversion Result Register 0x8 16 read-only 0 0xFFFF ADR Conversion Result 0 16 read-only CVA Compare Value Register A 0xA 16 read-write 0 0xFFFF VA Lower limit compare value 0 16 read-write CVB Compare Value Register B 0xC 16 read-write 0 0xFFFF VB Upper limit compare value 0 16 read-write APCTL Pin Control Register 0xE 16 read-write 0 0xFFFF ADPC0 ADC Pin Control 0 0 1 read-write 0 AD0 pin I/O control enabled. #0 1 AD0 pin I/O control disabled. #1 ADPC1 ADC Pin Control 1 1 1 read-write 0 AD1 pin I/O control enabled. #0 1 AD1 pin I/O control disabled. #1 ADPC2 ADC Pin Control 2 2 1 read-write 0 AD2 pin I/O control enabled. #0 1 AD2 pin I/O control disabled. #1 ADPC3 ADC Pin Control 3 3 1 read-write 0 AD3 pin I/O control enabled. #0 1 AD3 pin I/O control disabled. #1 ADPC4 ADC Pin Control 4 4 1 read-write 0 AD4 pin I/O control enabled. #0 1 AD4 pin I/O control disabled. #1 ADPC5 ADC Pin Control 5 5 1 read-write 0 AD5 pin I/O control enabled. #0 1 AD5 pin I/O control disabled. #1 ADPC6 ADC Pin Control 6 6 1 read-write 0 AD6 pin I/O control enabled. #0 1 AD6 pin I/O control disabled. #1 ADPC7 ADC Pin Control 7 7 1 read-write 0 AD7 pin I/O control enabled. #0 1 AD7 pin I/O control disabled. #1 ADPC8 ADC Pin Control 8 8 1 read-write 0 AD8 pin I/O control enabled. #0 1 AD8 pin I/O control disabled. #1 ADPC9 ADC Pin Control 9 9 1 read-write 0 AD9 pin I/O control enabled. #0 1 AD9 pin I/O control disabled. #1 ADPC10 ADC Pin Control 10 10 1 read-write 0 AD10 pin I/O control enabled. #0 1 AD10 pin I/O control disabled. #1 ADPC11 ADC Pin Control 11 11 1 read-write 0 AD11 pin I/O control enabled. #0 1 AD11 pin I/O control disabled. #1 RESERVED no description available 12 4 read-only ADC3 Analog-to-digital converter ADC ADC3_ 0x4003E000 0 0x10 registers SC1 Status and Control Register 1 0 16 read-write 0x1F 0xFFFF ADCH Input Channel Select 0 5 read-write 00000 AD0 #00000 00001 AD1 #00001 00010 AD2 #00010 00011 AD3 #00011 00100 AD4 #00100 00101 AD5 #00101 00110 AD6 #00110 00111 AD7 #00111 01000 AD8 #01000 01001 AD9 #01001 01010 AD10 #01010 01011 AD11 #01011 11111 Module disabled Reset FIFO in FIFO mode. #11111 ADCO Continuous Conversion Enable 5 1 read-write 0 One conversion following a write to the ADCSC1 when software triggered operation is selected, or one conversion following assertion of ADHWT when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversions are triggerd. #0 1 Continuous conversions initiated following a write to ADCSC1 when software triggered operation is selected. Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversions are loop triggered. #1 AIEN Interrupt Enable 6 1 read-write 0 Conversion complete interrupt disabled. #0 1 Conversion complete interrupt enabled. #1 COCO Conversion Complete Flag 7 1 read-only 0 Conversion not completed. #0 1 Conversion completed. #1 RESERVED no description available 8 8 read-only SC2 Status and Control Register 2 0x2 16 read-write 0x8 0xFFFF RESERVED no description available 0 2 read-only FFULL Result FIFO full 2 1 read-only 0 Indicates that ADC result fifo is not full and next conversion data still can be stored into fifo. #0 1 Indicates that ADC result fifo is full and next conversion will override old data if no read action. #1 FEMPTY Result FIFO empty 3 1 read-only 0 Indicates that ADC result fifo have at least one valid new data. #0 1 Indicates that ADC result fifo have no valid new data. #1 ACDSEL Compare Data Selection 4 1 read-write 0 Compare value is from the conversion result and ADC_CVA. #0 1 Compare value is from the conversion result and ADC_CVB. #1 ACFE Compare Function Enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ADTRG Conversion Trigger Select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 ADACT Conversion Active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 RESERVED no description available 8 8 read-only SC3 Status and Control Register 3 0x4 16 read-write 0 0xFFFF ADICLK Input Clock Select 0 2 read-write 00 Bus clock #00 01 Bus clock divided by 2 #01 10 Alternate clock (ALTCLK) #10 11 Asynchronous clock (ADACK) #11 MODE Conversion Mode Selection 2 2 read-write 00 8-bit conversion (N=8) #00 01 10-bit conversion (N=10) #01 10 12-bit conversion (N=12) #10 11 Reserved #11 ADLSMP Long Sample Time Configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 ADIV Clock Divide Select 5 2 read-write 00 Divide ration = 1, and clock rate = Input clock. #00 01 Divide ration = 2, and clock rate = Input clock * 2. #01 10 Divide ration = 3, and clock rate = Input clock * 4. #10 11 Divide ration = 4, and clock rate = Input clock * 8. #11 ADLPC Low-Power Configuration 7 1 read-write 0 High speed configuration. #0 1 Low power configuration:The power is reduced at the expense of maximum clock speed.. #1 RESERVED no description available 8 8 read-only SC4 Status and Control Register 4 0x6 16 read-write 0 0xFFFF AFDEP no description available 0 3 read-write 000 FIFO is disabled. #000 001 2-level FIFO is enabled. #001 010 3-level FIFO is enabled.. #010 011 4-level FIFO is enabled. #011 100 5-level FIFO is enabled. #100 101 6-level FIFO is enabled. #101 110 7-level FIFO is enabled. #110 111 8-level FIFO is enabled. #111 RESERVED no description available 3 2 read-only ACFSEL no description available 5 1 read-write 0 OR all of compare trigger. #0 1 AND all of compare trigger. #1 ASCANE no description available 6 1 read-write 0 FIFO scan mode disabled. #0 1 FIFO scan mode enabled. #1 DMAEN DMA Enable 7 1 read-write 0 DMA read request is disabled. #0 1 DMA read request is enabled, the conversion complete flag will assert the DMA request signal. #1 RESERVED no description available 8 8 read-only R Conversion Result Register 0x8 16 read-only 0 0xFFFF ADR Conversion Result 0 16 read-only CVA Compare Value Register A 0xA 16 read-write 0 0xFFFF VA Lower limit compare value 0 16 read-write CVB Compare Value Register B 0xC 16 read-write 0 0xFFFF VB Upper limit compare value 0 16 read-write APCTL Pin Control Register 0xE 16 read-write 0 0xFFFF ADPC0 ADC Pin Control 0 0 1 read-write 0 AD0 pin I/O control enabled. #0 1 AD0 pin I/O control disabled. #1 ADPC1 ADC Pin Control 1 1 1 read-write 0 AD1 pin I/O control enabled. #0 1 AD1 pin I/O control disabled. #1 ADPC2 ADC Pin Control 2 2 1 read-write 0 AD2 pin I/O control enabled. #0 1 AD2 pin I/O control disabled. #1 ADPC3 ADC Pin Control 3 3 1 read-write 0 AD3 pin I/O control enabled. #0 1 AD3 pin I/O control disabled. #1 ADPC4 ADC Pin Control 4 4 1 read-write 0 AD4 pin I/O control enabled. #0 1 AD4 pin I/O control disabled. #1 ADPC5 ADC Pin Control 5 5 1 read-write 0 AD5 pin I/O control enabled. #0 1 AD5 pin I/O control disabled. #1 ADPC6 ADC Pin Control 6 6 1 read-write 0 AD6 pin I/O control enabled. #0 1 AD6 pin I/O control disabled. #1 ADPC7 ADC Pin Control 7 7 1 read-write 0 AD7 pin I/O control enabled. #0 1 AD7 pin I/O control disabled. #1 ADPC8 ADC Pin Control 8 8 1 read-write 0 AD8 pin I/O control enabled. #0 1 AD8 pin I/O control disabled. #1 ADPC9 ADC Pin Control 9 9 1 read-write 0 AD9 pin I/O control enabled. #0 1 AD9 pin I/O control disabled. #1 ADPC10 ADC Pin Control 10 10 1 read-write 0 AD10 pin I/O control enabled. #0 1 AD10 pin I/O control disabled. #1 ADPC11 ADC Pin Control 11 11 1 read-write 0 AD11 pin I/O control enabled. #0 1 AD11 pin I/O control disabled. #1 RESERVED no description available 12 4 read-only EWM External Watchdog Monitor EWM_ 0x40041000 0 0x4 registers CTRL Control Register 0 8 read-write 0 0xFF EWMEN EWM enable. 0 1 read-write ASSIN EWM_in's Assertion State Select. 1 1 read-write INEN Input Enable. 2 1 read-write RESERVED no description available 3 5 read-only SERV Service Register 0x1 8 write-only 0 0xFF SERVICE no description available 0 8 write-only CMPL Compare Low Register 0x2 8 read-write 0 0xFF COMPAREL no description available 0 8 read-write CMPH Compare High Register 0x3 8 read-write 0xFF 0xFF COMPAREH no description available 0 8 read-write CMT Carrier Modulator Transmitter CMT_ 0x40042000 0 0xC registers CGH1 CMT Carrier Generator High Data Register 1 0 8 read-write 0 0 PH Primary Carrier High Time Data Value 0 8 read-write CGL1 CMT Carrier Generator Low Data Register 1 0x1 8 read-write 0 0 PL Primary Carrier Low Time Data Value 0 8 read-write CGH2 CMT Carrier Generator High Data Register 2 0x2 8 read-write 0 0 SH Secondary Carrier High Time Data Value 0 8 read-write CGL2 CMT Carrier Generator Low Data Register 2 0x3 8 read-write 0 0 SL Secondary Carrier Low Time Data Value 0 8 read-write OC CMT Output Control Register 0x4 8 read-write 0 0xFF RESERVED no description available 0 5 read-only IROPEN IRO Pin Enable 5 1 read-write 0 The IRO signal is disabled. #0 1 The IRO signal is enabled as output. #1 CMTPOL CMT Output Polarity 6 1 read-write 0 The IRO signal is active-low. #0 1 The IRO signal is active-high. #1 IROL IRO Latch Control 7 1 read-write MSC CMT Modulator Status and Control Register 0x5 8 read-write 0 0xFF MCGEN Modulator and Carrier Generator Enable 0 1 read-write 0 Modulator and carrier generator disabled #0 1 Modulator and carrier generator enabled #1 EOCIE End of Cycle Interrupt Enable 1 1 read-write 0 CPU interrupt is disabled. #0 1 CPU interrupt is enabled. #1 FSK FSK Mode Select 2 1 read-write 0 The CMT operates in Time or Baseband mode. #0 1 The CMT operates in FSK mode. #1 BASE Baseband Enable 3 1 read-write 0 Baseband mode is disabled. #0 1 Baseband mode is enabled. #1 EXSPC Extended Space Enable 4 1 read-write 0 Extended space is disabled. #0 1 Extended space is enabled. #1 CMTDIV CMT Clock Divide Prescaler 5 2 read-write 00 IF * 1 #00 01 IF * 2 #01 10 IF * 4 #10 11 IF * 8 #11 EOCF End Of Cycle Status Flag 7 1 read-only 0 End of modulation cycle has not occured since the flag last cleared. #0 1 End of modulator cycle has occurred. #1 CMD1 CMT Modulator Data Register Mark High 0x6 8 read-write 0 0 MB no description available 0 8 read-write CMD2 CMT Modulator Data Register Mark Low 0x7 8 read-write 0 0 MB no description available 0 8 read-write CMD3 CMT Modulator Data Register Space High 0x8 8 read-write 0 0 SB no description available 0 8 read-write CMD4 CMT Modulator Data Register Space Low 0x9 8 read-write 0 0 SB no description available 0 8 read-write PPS CMT Primary Prescaler Register 0xA 8 read-write 0 0xFF PPSDIV Primary Prescaler Divider 0 4 read-write 0000 Bus clock * 1 #0000 0001 Bus clock * 2 #0001 0010 Bus clock * 3 #0010 0011 Bus clock * 4 #0011 0100 Bus clock * 5 #0100 0101 Bus clock * 6 #0101 0110 Bus clock * 7 #0110 0111 Bus clock * 8 #0111 1000 Bus clock * 9 #1000 1001 Bus clock * 10 #1001 1010 Bus clock * 11 #1010 1011 Bus clock * 12 #1011 1100 Bus clock * 13 #1100 1101 Bus clock * 14 #1101 1110 Bus clock * 15 #1110 1111 Bus clock * 16 #1111 RESERVED no description available 4 4 read-only DMA CMT Direct Memory Access Register 0xB 8 read-write 0 0xFF DMA DMA Enable 0 1 read-write 0 DMA transfer request and done are disabled. #0 1 DMA transfer request and done are enabled. #1 RESERVED no description available 1 7 read-only ICS Internal clock source ICS_ 0x40044000 0 0x5 registers C1 ICS Control Register 1 0 8 read-write 0x4 0xFF IREFSTEN Internal Reference Stop Enable 0 1 read-write 0 Internal reference clock is disabled in stop. #0 1 Internal reference clock stays enabled in stop if IRCLKEN is set before entering stop. #1 IRCLKEN Internal Reference Clock Enable 1 1 read-write 0 ICSIRCLK inactive. #0 1 ICSIRCLK active. #1 IREFS Internal Reference Select 2 1 read-write 0 External reference clock selected. #0 1 Internal reference clock selected. #1 RDIV Reference Divider 3 3 read-write CLKS Clock Source Select 6 2 read-write 00 Output of FLL is selected. #00 01 Internal reference clock is selected. #01 10 External reference clock is selected. #10 11 Reserved, defaults to 00. #11 C2 ICS Control Register 2 0x1 8 read-write 0x40 0xFF RESERVED no description available 0 2 read-only FRDIV Fine Reference Divider 2 2 read-write LP Low Power Select 4 1 read-write 0 FLL is not disabled in bypass mode. #0 1 FLL is disabled in bypass modes unless BDM is active. #1 BDIV Bus Frequency Divider 5 3 read-write 000 Encoding 0 - Divides selected clock by 1. This value can not be written or readback in some devices. #000 001 Encoding 1 - Divides selected clock by 2. #001 010 Encoding 2 - Divides selected clock by 4 (reset default). #010 011 Encoding 3 - Divides selected clock by 8. #011 100 Encoding 4 - Divides selected clock by 16. #100 101 Encoding 5 - Divides selected clock by 32. #101 110 Encoding 6 - Divides selected clock by 64. #110 111 Encoding 7 - Divides selected clock by 128. #111 C3 ICS Control Register 3 0x2 8 read-write 0 0 SCTRIM Slow Internal Reference Clock Trim Setting 0 8 read-write C4 ICS Control Register 4 0x3 8 read-write 0x1 0xFF SCFTRIM Slow Internal Reference Clock Fine Trim 0 1 read-write RESERVED no description available 1 4 read-only CME Clock Monitor Enable 5 1 read-write 0 Clock monitor is disabled. #0 1 Clock monitor enable. #1 RLOLIE Loss of Rough Lock Interrupt Enable 6 1 read-write 0 Lose of Rough Lock Interrupt disable. #0 1 Lose of Rough Lock Interrupt enable. #1 FLOLIE Loss of Fine Lock Interrupt Enable 7 1 read-write 0 Lose of fine Lock Interrupt disable. #0 1 Lose of fine Lock Interrupt enable. #1 S ICS Status Register 0x4 8 read-only 0x10 0xFF RESERVED no description available 0 2 read-only CLKST Clock Mode Status 2 2 read-only 00 Output of FLL is selected. #00 01 FLL Bypassed, internal reference clock is selected. #01 10 FLL Bypassed, external reference clock is selected. #10 11 Reserved. #11 IREFST Internal Reference Status 4 1 read-only 0 Source of reference clock is external clock. #0 1 Source of reference clock is internal clock. #1 RLOCK Rough Lock Status 5 1 read-only 0 FLL is currently Roughly unlocked or FLL is disabled. #0 1 FLL is currently Roughly locked. #1 FLOCK Fine Lock Status 6 1 read-only 0 FLL is currently unlocked. #0 1 FLL is currently locked. #1 LOLS Loss of Lock Status 7 1 read-only 0 FLL has not lost lock since LOLS was last cleared. #0 1 FLL has lost lock since LOLS was last cleared. #1 OSC Oscillator OSC_ 0x40045000 0 0x1 registers CR OSC Control Register 0 8 read-write 0 0xFF OSCINIT OSC Initialization 0 1 read-only 0 Oscillator initialization not completes. #0 1 Oscillator initialization completed. #1 HGO High Gain Oscillator Select 1 1 read-write 0 Low power mode. #0 1 High gain mode. #1 RESERVED no description available 2 2 read-only OSCOS OSC Output Select 4 1 read-write 0 External clock source from EXTAL pin is selected. #0 1 Oscillator clock source is selected. #1 OSCSTEN OSC Enable in Stop mode 5 1 read-write 0 OSC clock is disabled in stop. #0 1 OSC clock stays enabled in stop. #1 RESERVED no description available 6 1 read-only OSCEN OSC Enable 7 1 read-write 0 OSC module disabled. #0 1 OSC module enabled. #1 I2C0 Inter-Integrated Circuit I2C I2C0_ 0x40047000 0 0xC registers INT_ADC2 40 A1 I2C Address Register 1 0 8 read-write 0 0xFF RESERVED no description available 0 1 read-only AD Address 1 7 read-write F I2C Frequency Divider register 0x1 8 read-write 0 0xFF ICR ClockRate 0 6 read-write MULT no description available 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 11 Reserved #11 C1 I2C Control Register 1 0x2 8 read-write 0 0xFF DMAEN DMA Enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled and the following conditions trigger the DMA request: While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK automatic) While FACK = 0, the first byte received matches the A1 register or is general call address. If any address matching occurs, IAAS and TCF are set. If the direction of transfer is known from master to slave, then it is not required to check the SRW. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 WUEN Wakeup Enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 RSTA Repeat START 2 1 write-only TXAK Transmit Acknowledge Enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). #0 1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). #1 TX Transmit Mode Select 4 1 read-write 0 Receive #0 1 Transmit #1 MST Master Mode Select 5 1 read-write 0 Slave mode #0 1 Master mode #1 IICIE I2C Interrupt Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 IICEN I2C Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 S I2C Status register 0x3 8 read-write 0x80 0xFF RXAK Receive Acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 IICIF Interrupt Flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 SRW Slave Read/Write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 RAM Range Address Match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 ARBL Arbitration Lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus Busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed As A Slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 TCF Transfer Complete Flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 D I2C Data I/O register 0x4 8 read-write 0 0xFF DATA Data 0 8 read-write C2 I2C Control Register 2 0x5 8 read-write 0 0xFF AD Slave Address 0 3 read-write RMEN Range Address Matching Enable 3 1 read-write 0 Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave Baud Rate Control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 HDRS High Drive Select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 ADEXT Address Extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General Call Address Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 FLT I2C Programmable Input Glitch Filter register 0x6 8 read-write 0 0xFF FLT I2C Programmable Filter Factor 0 5 read-write 0 No filter/bypass #0 STOPIE I2C Bus Stop Interrupt Enable 5 1 read-write 0 Stop detection interrupt is disabled #0 1 Stop detection interrupt is enabled #1 STOPF I2C Bus Stop Detect Flag 6 1 read-write 0 No stop happens on I2C bus #0 1 Stop detected on I2C bus #1 SHEN Stop Hold Enable 7 1 read-write 0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated. #0 1 Stop holdoff is enabled. #1 RA I2C Range Address register 0x7 8 read-write 0 0xFF RESERVED no description available 0 1 read-only RAD Range Slave Address 1 7 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write 0 0xFF SHTF2IE SHTF2 Interrupt Enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SHTF2 SCL High Timeout Flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF1 SCL High Timeout Flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SLTF SCL Low Timeout Flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout Counter Clock Select 4 1 read-write 0 Timeout counter counts at the frequency of the bus clock / 64 #0 1 Timeout counter counts at the frequency of the bus clock #1 SIICAEN Second I2C Address Enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 ALERTEN SMBus Alert Response Address Enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK Enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. #1 A2 I2C Address Register 2 0x9 8 read-write 0xC2 0xFF RESERVED no description available 0 1 read-only SAD SMBus Address 1 7 read-write SLTH I2C SCL Low Timeout Register High 0xA 8 read-write 0 0xFF SSLT no description available 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write 0 0xFF SSLT no description available 0 8 read-write I2C1 Inter-Integrated Circuit I2C I2C1_ 0x40048000 0 0xC registers A1 I2C Address Register 1 0 8 read-write 0 0xFF RESERVED no description available 0 1 read-only AD Address 1 7 read-write F I2C Frequency Divider register 0x1 8 read-write 0 0xFF ICR ClockRate 0 6 read-write MULT no description available 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 11 Reserved #11 C1 I2C Control Register 1 0x2 8 read-write 0 0xFF DMAEN DMA Enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled and the following conditions trigger the DMA request: While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK automatic) While FACK = 0, the first byte received matches the A1 register or is general call address. If any address matching occurs, IAAS and TCF are set. If the direction of transfer is known from master to slave, then it is not required to check the SRW. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 WUEN Wakeup Enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 RSTA Repeat START 2 1 write-only TXAK Transmit Acknowledge Enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). #0 1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). #1 TX Transmit Mode Select 4 1 read-write 0 Receive #0 1 Transmit #1 MST Master Mode Select 5 1 read-write 0 Slave mode #0 1 Master mode #1 IICIE I2C Interrupt Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 IICEN I2C Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 S I2C Status register 0x3 8 read-write 0x80 0xFF RXAK Receive Acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 IICIF Interrupt Flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 SRW Slave Read/Write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 RAM Range Address Match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 ARBL Arbitration Lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus Busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed As A Slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 TCF Transfer Complete Flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 D I2C Data I/O register 0x4 8 read-write 0 0xFF DATA Data 0 8 read-write C2 I2C Control Register 2 0x5 8 read-write 0 0xFF AD Slave Address 0 3 read-write RMEN Range Address Matching Enable 3 1 read-write 0 Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave Baud Rate Control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 HDRS High Drive Select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 ADEXT Address Extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General Call Address Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 FLT I2C Programmable Input Glitch Filter register 0x6 8 read-write 0 0xFF FLT I2C Programmable Filter Factor 0 5 read-write 0 No filter/bypass #0 STOPIE I2C Bus Stop Interrupt Enable 5 1 read-write 0 Stop detection interrupt is disabled #0 1 Stop detection interrupt is enabled #1 STOPF I2C Bus Stop Detect Flag 6 1 read-write 0 No stop happens on I2C bus #0 1 Stop detected on I2C bus #1 SHEN Stop Hold Enable 7 1 read-write 0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated. #0 1 Stop holdoff is enabled. #1 RA I2C Range Address register 0x7 8 read-write 0 0xFF RESERVED no description available 0 1 read-only RAD Range Slave Address 1 7 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write 0 0xFF SHTF2IE SHTF2 Interrupt Enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SHTF2 SCL High Timeout Flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF1 SCL High Timeout Flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SLTF SCL Low Timeout Flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout Counter Clock Select 4 1 read-write 0 Timeout counter counts at the frequency of the bus clock / 64 #0 1 Timeout counter counts at the frequency of the bus clock #1 SIICAEN Second I2C Address Enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 ALERTEN SMBus Alert Response Address Enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK Enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. #1 A2 I2C Address Register 2 0x9 8 read-write 0xC2 0xFF RESERVED no description available 0 1 read-only SAD SMBus Address 1 7 read-write SLTH I2C SCL Low Timeout Register High 0xA 8 read-write 0 0xFF SSLT no description available 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write 0 0xFF SSLT no description available 0 8 read-write UART0 Serial Communication Interface UART UART0_ 0x40049000 0 0x17 registers BDH UART Baud Rate Registers: High 0 8 read-write 0 0xFF SBR UART Baud Rate Bits 0 5 read-write RESERVED no description available 5 1 read-only RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 LBKDIE LIN Break Detect Interrupt or DMA Request Enable 7 1 read-write 0 LBKDIF interrupt and DMA transfer requests disabled. #0 1 LBKDIF interrupt or DMA transfer requests enabled. #1 BDL UART Baud Rate Registers: Low 0x1 8 read-write 0x4 0xFF SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write 0 0xFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 C2 UART Control Register 2 0x3 8 read-write 0 0xFF SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 ILIE Idle Line Interrupt DMA Transfer Enable 4 1 read-write 0 IDLE interrupt requests disabled. and DMA transfer #0 1 IDLE interrupt requests enabled. or DMA transfer #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 TCIE Transmission Complete Interrupt or DMA Transfer Enable 6 1 read-write 0 TC interrupt and DMA transfer requests disabled. #0 1 TC interrupt or DMA transfer requests enabled. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 S1 UART Status Register 1 0x4 8 read-only 0xC0 0xFF PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write 0 0xFF RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character is detected at one of the following lengths: 10 bit times if C1[M] = 0 11 bit times if C1[M] = 1 and C4[M10] = 0 12 bit times if C1[M] = 1, C4[M10] = 1, and S1[PE] = 1 #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 C3 UART Control Register 3 0x6 8 read-write 0 0xFF PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 T8 Transmit Bit 8 6 1 read-write R8 Received Bit 8 7 1 read-only D UART Data Register 0x7 8 read-write 0 0xFF RT no description available 0 8 read-write MA1 UART Match Address Registers 1 0x8 8 read-write 0 0xFF MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write 0 0xFF MA Match Address 0 8 read-write C4 UART Control Register 4 0xA 8 read-write 0 0xFF BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. #1 C5 UART Control Register 5 0xB 8 read-write 0 0xFF RESERVED no description available 0 3 read-only LBKDDMAS LIN Break Detect DMA Select Bit 3 1 read-write 0 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service. #0 1 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer. #1 ILDMAS Idle Line DMA Select 4 1 read-write 0 If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is asserted to request an interrupt service. #0 1 If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is asserted to request a DMA transfer. #1 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TCDMAS Transmission Complete DMA Select 6 1 read-write 0 If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request signal is asserted to request an interrupt service. #0 1 If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 ED UART Extended Data Register 0xC 8 read-only 0 0xFF RESERVED no description available 0 6 read-only PARITYE no description available 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 NOISY no description available 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 MODEM UART Modem Register 0xD 8 read-write 0 0xFF TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO) #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. #1 RESERVED no description available 4 4 read-only IR UART Infrared Register 0xE 8 read-write 0 0xFF TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 RESERVED no description available 3 5 read-only PFIFO UART FIFO Parameters 0x10 8 read-write 0 0xFF RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 111 Reserved. #111 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 111 Reserved. #111 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 CFIFO UART FIFO Control Register 0x11 8 read-write 0 0xFF RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 RXOFE Receive FIFO Overflow Interrupt Enable 2 1 read-write 0 RXOF flag does not generate an interrupt to the host. #0 1 RXOF flag generates an interrupt to the host. #1 RESERVED no description available 3 3 read-only RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 SFIFO UART FIFO Status Register 0x12 8 read-write 0xC0 0xFF RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 RXOF Receiver Buffer Overflow Flag 2 1 read-write 0 No receive buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer overflow has occurred since the last time the flag was cleared. #1 RESERVED no description available 3 3 read-only RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write 0 0xFF TXWATER Transmit Watermark 0 8 read-write TCFIFO UART FIFO Transmit Count 0x14 8 read-only 0 0xFF TXCOUNT Transmit Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write 0x1 0xFF RXWATER Receive Watermark 0 8 read-write RCFIFO UART FIFO Receive Count 0x16 8 read-only 0 0xFF RXCOUNT Receive Counter 0 8 read-only UART1 Serial Communication Interface UART UART1_ 0x4004A000 0 0xF registers BDH UART Baud Rate Registers: High 0 8 read-write 0 0xFF SBR UART Baud Rate Bits 0 5 read-write RESERVED no description available 5 1 read-only RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 LBKDIE LIN Break Detect Interrupt or DMA Request Enable 7 1 read-write 0 LBKDIF interrupt and DMA transfer requests disabled. #0 1 LBKDIF interrupt or DMA transfer requests enabled. #1 BDL UART Baud Rate Registers: Low 0x1 8 read-write 0x4 0xFF SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write 0 0xFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 C2 UART Control Register 2 0x3 8 read-write 0 0xFF SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 ILIE Idle Line Interrupt DMA Transfer Enable 4 1 read-write 0 IDLE interrupt requests disabled. and DMA transfer #0 1 IDLE interrupt requests enabled. or DMA transfer #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 TCIE Transmission Complete Interrupt or DMA Transfer Enable 6 1 read-write 0 TC interrupt and DMA transfer requests disabled. #0 1 TC interrupt or DMA transfer requests enabled. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 S1 UART Status Register 1 0x4 8 read-only 0xC0 0xFF PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write 0 0xFF RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character is detected at one of the following lengths: 10 bit times if C1[M] = 0 11 bit times if C1[M] = 1 and C4[M10] = 0 12 bit times if C1[M] = 1, C4[M10] = 1, and S1[PE] = 1 #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 C3 UART Control Register 3 0x6 8 read-write 0 0xFF PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 T8 Transmit Bit 8 6 1 read-write R8 Received Bit 8 7 1 read-only D UART Data Register 0x7 8 read-write 0 0xFF RT no description available 0 8 read-write MA1 UART Match Address Registers 1 0x8 8 read-write 0 0xFF MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write 0 0xFF MA Match Address 0 8 read-write C4 UART Control Register 4 0xA 8 read-write 0 0xFF BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. #1 C5 UART Control Register 5 0xB 8 read-write 0 0xFF RESERVED no description available 0 3 read-only LBKDDMAS LIN Break Detect DMA Select Bit 3 1 read-write 0 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service. #0 1 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer. #1 ILDMAS Idle Line DMA Select 4 1 read-write 0 If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is asserted to request an interrupt service. #0 1 If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is asserted to request a DMA transfer. #1 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TCDMAS Transmission Complete DMA Select 6 1 read-write 0 If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request signal is asserted to request an interrupt service. #0 1 If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 MODEM UART Modem Register 0xD 8 read-write 0 0xFF TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO) #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. #1 RESERVED no description available 4 4 read-only IR UART Infrared Register 0xE 8 read-write 0 0xFF TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 RESERVED no description available 3 5 read-only UART2 Serial Communication Interface UART UART2_ 0x4004B000 0 0xF registers INT_PDB0 65 BDH UART Baud Rate Registers: High 0 8 read-write 0 0xFF SBR UART Baud Rate Bits 0 5 read-write RESERVED no description available 5 1 read-only RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 LBKDIE LIN Break Detect Interrupt or DMA Request Enable 7 1 read-write 0 LBKDIF interrupt and DMA transfer requests disabled. #0 1 LBKDIF interrupt or DMA transfer requests enabled. #1 BDL UART Baud Rate Registers: Low 0x1 8 read-write 0x4 0xFF SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write 0 0xFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 C2 UART Control Register 2 0x3 8 read-write 0 0xFF SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 ILIE Idle Line Interrupt DMA Transfer Enable 4 1 read-write 0 IDLE interrupt requests disabled. and DMA transfer #0 1 IDLE interrupt requests enabled. or DMA transfer #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 TCIE Transmission Complete Interrupt or DMA Transfer Enable 6 1 read-write 0 TC interrupt and DMA transfer requests disabled. #0 1 TC interrupt or DMA transfer requests enabled. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 S1 UART Status Register 1 0x4 8 read-only 0xC0 0xFF PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write 0 0xFF RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character is detected at one of the following lengths: 10 bit times if C1[M] = 0 11 bit times if C1[M] = 1 and C4[M10] = 0 12 bit times if C1[M] = 1, C4[M10] = 1, and S1[PE] = 1 #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 C3 UART Control Register 3 0x6 8 read-write 0 0xFF PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 T8 Transmit Bit 8 6 1 read-write R8 Received Bit 8 7 1 read-only D UART Data Register 0x7 8 read-write 0 0xFF RT no description available 0 8 read-write MA1 UART Match Address Registers 1 0x8 8 read-write 0 0xFF MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write 0 0xFF MA Match Address 0 8 read-write C4 UART Control Register 4 0xA 8 read-write 0 0xFF BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. #1 C5 UART Control Register 5 0xB 8 read-write 0 0xFF RESERVED no description available 0 3 read-only LBKDDMAS LIN Break Detect DMA Select Bit 3 1 read-write 0 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service. #0 1 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer. #1 ILDMAS Idle Line DMA Select 4 1 read-write 0 If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is asserted to request an interrupt service. #0 1 If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is asserted to request a DMA transfer. #1 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TCDMAS Transmission Complete DMA Select 6 1 read-write 0 If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request signal is asserted to request an interrupt service. #0 1 If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 MODEM UART Modem Register 0xD 8 read-write 0 0xFF TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO) #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. #1 RESERVED no description available 4 4 read-only IR UART Infrared Register 0xE 8 read-write 0 0xFF TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 RESERVED no description available 3 5 read-only UART3 Serial Communication Interface UART UART3_ 0x4004C000 0 0xF registers BDH UART Baud Rate Registers: High 0 8 read-write 0 0xFF SBR UART Baud Rate Bits 0 5 read-write RESERVED no description available 5 1 read-only RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 LBKDIE LIN Break Detect Interrupt or DMA Request Enable 7 1 read-write 0 LBKDIF interrupt and DMA transfer requests disabled. #0 1 LBKDIF interrupt or DMA transfer requests enabled. #1 BDL UART Baud Rate Registers: Low 0x1 8 read-write 0x4 0xFF SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write 0 0xFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 C2 UART Control Register 2 0x3 8 read-write 0 0xFF SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 ILIE Idle Line Interrupt DMA Transfer Enable 4 1 read-write 0 IDLE interrupt requests disabled. and DMA transfer #0 1 IDLE interrupt requests enabled. or DMA transfer #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 TCIE Transmission Complete Interrupt or DMA Transfer Enable 6 1 read-write 0 TC interrupt and DMA transfer requests disabled. #0 1 TC interrupt or DMA transfer requests enabled. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 S1 UART Status Register 1 0x4 8 read-only 0xC0 0xFF PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write 0 0xFF RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character is detected at one of the following lengths: 10 bit times if C1[M] = 0 11 bit times if C1[M] = 1 and C4[M10] = 0 12 bit times if C1[M] = 1, C4[M10] = 1, and S1[PE] = 1 #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 C3 UART Control Register 3 0x6 8 read-write 0 0xFF PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 T8 Transmit Bit 8 6 1 read-write R8 Received Bit 8 7 1 read-only D UART Data Register 0x7 8 read-write 0 0xFF RT no description available 0 8 read-write MA1 UART Match Address Registers 1 0x8 8 read-write 0 0xFF MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write 0 0xFF MA Match Address 0 8 read-write C4 UART Control Register 4 0xA 8 read-write 0 0xFF BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. #1 C5 UART Control Register 5 0xB 8 read-write 0 0xFF RESERVED no description available 0 3 read-only LBKDDMAS LIN Break Detect DMA Select Bit 3 1 read-write 0 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service. #0 1 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer. #1 ILDMAS Idle Line DMA Select 4 1 read-write 0 If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is asserted to request an interrupt service. #0 1 If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is asserted to request a DMA transfer. #1 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TCDMAS Transmission Complete DMA Select 6 1 read-write 0 If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request signal is asserted to request an interrupt service. #0 1 If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 MODEM UART Modem Register 0xD 8 read-write 0 0xFF TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO) #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. #1 RESERVED no description available 4 4 read-only IR UART Infrared Register 0xE 8 read-write 0 0xFF TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 RESERVED no description available 3 5 read-only SPI0 Serial Peripheral Interface SPI SPI0_ 0x4004E000 0 0xA registers INT_SPI0 41 C1 SPI control register 1 0 8 read-write 0x4 0xFF LSBFE LSB first (shifter direction) 0 1 read-write 0 SPI serial data transfers start with most significant bit #0 1 SPI serial data transfers start with least significant bit #1 SSOE Slave select output enable 1 1 read-write 0 When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input. #0 1 When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input. #1 CPHA Clock phase 2 1 read-write 0 First edge on SPSCK occurs at the middle of the first cycle of a data transfer #0 1 First edge on SPSCK occurs at the start of the first cycle of a data transfer #1 CPOL Clock polarity 3 1 read-write 0 Active-high SPI clock (idles low) #0 1 Active-low SPI clock (idles high) #1 MSTR Master/slave mode select 4 1 read-write 0 SPI module configured as a slave SPI device #0 1 SPI module configured as a master SPI device #1 SPTIE SPI transmit interrupt enable 5 1 read-write 0 Interrupts from SPTEF inhibited (use polling) #0 1 When SPTEF is 1, hardware interrupt requested #1 SPE SPI system enable 6 1 read-write 0 SPI system inactive #0 1 SPI system enabled #1 SPIE SPI interrupt enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO (when FIFO is supported and enabled) 7 1 read-write 0 Interrupts from SPRF and MODF are inhibited-use polling (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are disabled (when FIFOMODE is 1) #0 1 Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are enabled (when FIFOMODE is 1) #1 C2 SPI control register 2 0x1 8 read-write 0 0xFF SPC0 SPI pin control 0 0 1 read-write 0 SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in. #0 1 SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI. #1 SPISWAI SPI stop in wait mode 1 1 read-write 0 SPI clocks continue to operate in wait mode #0 1 SPI clocks stop when the MCU enters wait mode #1 RXDMAE Receive DMA enable 2 1 read-write 0 DMA request for receive is disabled and interrupt from SPRF is allowed #0 1 DMA request for receive is enabled and interrupt from SPRF is disabled #1 BIDIROE Bidirectional mode output enable 3 1 read-write 0 Output driver disabled so SPI data I/O pin acts as an input #0 1 SPI I/O pin enabled as an output #1 MODFEN Master mode-fault function enable 4 1 read-write 0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI #0 1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output #1 TXDMAE Transmit DMA enable 5 1 read-write 0 DMA request for transmit is disabled and interrupt from SPTEF is allowed #0 1 DMA request for transmit is enabled and interrupt from SPTEF is disabled #1 SPIMODE SPI 8-bit or 16-bit mode 6 1 read-write 0 8-bit SPI shift register, match register, and buffers #0 1 16-bit SPI shift register, match register, and buffers #1 SPMIE SPI match interrupt enable 7 1 read-write 0 Interrupts from SPMF inhibited (use polling) #0 1 When SPMF is 1, requests a hardware interrupt #1 BR SPI baud rate register 0x2 8 read-write 0 0xFF SPR SPI baud rate divisor 0 4 read-write 0000 Baud rate divisor is 2 #0000 0001 Baud rate divisor is 4 #0001 0010 Baud rate divisor is 8 #0010 0011 Baud rate divisor is 16 #0011 0100 Baud rate divisor is 32 #0100 0101 Baud rate divisor is 64 #0101 0110 Baud rate divisor is 128 #0110 0111 Baud rate divisor is 256 #0111 1000 Baud rate divisor is 512 #1000 SPPR SPI baud rate prescale divisor 4 3 read-write 000 Baud rate prescaler divisor is 1 #000 001 Baud rate prescaler divisor is 2 #001 010 Baud rate prescaler divisor is 3 #010 011 Baud rate prescaler divisor is 4 #011 100 Baud rate prescaler divisor is 5 #100 101 Baud rate prescaler divisor is 6 #101 110 Baud rate prescaler divisor is 7 #110 111 Baud rate prescaler divisor is 8 #111 RESERVED no description available 7 1 read-only S SPI status register 0x3 8 read-only 0x20 0xFF RFIFOEF SPI read FIFO empty flag 0 1 read-only 0 Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the DL register in 8-bit mode will empty the read FIFO. #0 1 Read FIFO is empty. #1 TXFULLF Transmit FIFO full flag 1 1 read-only 0 Transmit FIFO has less than 8 bytes #0 1 Transmit FIFO has 8 bytes of data #1 TNEAREF Transmit FIFO nearly empty flag 2 1 read-only 0 Transmit FIFO has more than 16 bits (when C3[5] is 0) or more than 32 bits (when C3[5] is 1) remaining to transmit #0 1 Transmit FIFO has an amount of data equal to or less than 16 bits (when C3[5] is 0) or 32 bits (when C3[5] is 1) remaining to transmit #1 RNFULLF Receive FIFO nearly full flag 3 1 read-only 0 Receive FIFO has received less than 48 bits (when C3[4] is 0) or less than 32 bits (when C3[4] is 1) #0 1 Receive FIFO has received data of an amount equal to or greater than 48 bits (when C3[4] is 0) or 32 bits (when C3[4] is 1) #1 MODF Master mode fault flag 4 1 read-only 0 No mode fault error #0 1 Mode fault error detected #1 SPTEF SPI transmit buffer empty flag (when FIFO is not supported or not enabled) or SPI transmit FIFO empty flag (when FIFO is supported and enabled) 5 1 read-only 0 SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when FIFOMODE is 1) #0 1 SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when FIFOMODE is 1) #1 SPMF SPI match flag 6 1 read-only 0 Value in the receive data buffer does not match the value in the MH:ML registers #0 1 Value in the receive data buffer matches the value in the MH:ML registers #1 SPRF SPI read buffer full flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (when FIFO is supported and enabled) 7 1 read-only 0 No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is not full (when FIFOMODE is 1) #0 1 Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is full (when FIFOMODE is 1) #1 DH SPI data register high 0x4 8 read-write 0 0xFF Bits Data (high byte) 0 8 read-write DL SPI data register low 0x5 8 read-write 0 0xFF Bits Data (low byte) 0 8 read-write MH SPI match register high 0x6 8 read-write 0 0xFF Bits Hardware compare value (high byte) 0 8 read-write ML SPI match register low 0x7 8 read-write 0 0xFF Bits Hardware compare value (low byte) 0 8 read-write C3 SPI control register 3 0x8 8 read-write 0 0xFF FIFOMODE FIFO mode enable 0 1 read-write 0 Buffer mode disabled #0 1 Data available in the receive data buffer #1 RNFULLIEN Receive FIFO nearly full interrupt enable 1 1 read-write 0 No interrupt upon RNFULLF being set #0 1 Enable interrupts upon RNFULLF being set #1 TNEARIEN Transmit FIFO nearly empty interrupt enable 2 1 read-write 0 No interrupt upon TNEAREF being set #0 1 Enable interrupts upon TNEAREF being set #1 INTCLR Interrupt clearing mechanism select 3 1 read-write 0 These interrupts are cleared when the corresponding flags are cleared depending on the state of the FIFOs #0 1 These interrupts are cleared by writing the corresponding bits in the CI register #1 RNFULLF_MARK Receive FIFO nearly full watermark 4 1 read-write 0 RNFULLF is set when the receive FIFO has 48 bits or more #0 1 RNFULLF is set when the receive FIFO has 32 bits or more #1 TNEAREF_MARK Transmit FIFO nearly empty watermark 5 1 read-write 0 TNEAREF is set when the transmit FIFO has 16 bits or less #0 1 TNEAREF is set when the transmit FIFO has 32 bits or less #1 RESERVED no description available 6 2 read-only CI SPI clear interrupt register 0x9 8 read-write 0 0xFF SPRFCI Receive FIFO full flag clear interrupt 0 1 write-only SPTEFCI Transmit FIFO empty flag clear interrupt 1 1 write-only RNFULLFCI Receive FIFO nearly full flag clear interrupt 2 1 write-only TNEAREFCI Transmit FIFO nearly empty flag clear interrupt 3 1 write-only RXFOF Receive FIFO overflow flag 4 1 read-only 0 Receive FIFO overflow condition has not occurred #0 1 Receive FIFO overflow condition occurred #1 TXFOF Transmit FIFO overflow flag 5 1 read-only 0 Transmit FIFO overflow condition has not occurred #0 1 Transmit FIFO overflow condition occurred #1 RXFERR Receive FIFO error flag 6 1 read-only 0 No receive FIFO error occurred #0 1 A receive FIFO error occurred #1 TXFERR Transmit FIFO error flag 7 1 read-only 0 No transmit FIFO error occurred #0 1 A transmit FIFO error occurred #1 SPI1 Serial Peripheral Interface SPI SPI1_ 0x4004F000 0 0xA registers INT_SPI1 42 C1 SPI control register 1 0 8 read-write 0x4 0xFF LSBFE LSB first (shifter direction) 0 1 read-write 0 SPI serial data transfers start with most significant bit #0 1 SPI serial data transfers start with least significant bit #1 SSOE Slave select output enable 1 1 read-write 0 When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input. #0 1 When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input. #1 CPHA Clock phase 2 1 read-write 0 First edge on SPSCK occurs at the middle of the first cycle of a data transfer #0 1 First edge on SPSCK occurs at the start of the first cycle of a data transfer #1 CPOL Clock polarity 3 1 read-write 0 Active-high SPI clock (idles low) #0 1 Active-low SPI clock (idles high) #1 MSTR Master/slave mode select 4 1 read-write 0 SPI module configured as a slave SPI device #0 1 SPI module configured as a master SPI device #1 SPTIE SPI transmit interrupt enable 5 1 read-write 0 Interrupts from SPTEF inhibited (use polling) #0 1 When SPTEF is 1, hardware interrupt requested #1 SPE SPI system enable 6 1 read-write 0 SPI system inactive #0 1 SPI system enabled #1 SPIE SPI interrupt enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO (when FIFO is supported and enabled) 7 1 read-write 0 Interrupts from SPRF and MODF are inhibited-use polling (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are disabled (when FIFOMODE is 1) #0 1 Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are enabled (when FIFOMODE is 1) #1 C2 SPI control register 2 0x1 8 read-write 0 0xFF SPC0 SPI pin control 0 0 1 read-write 0 SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in. #0 1 SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI. #1 SPISWAI SPI stop in wait mode 1 1 read-write 0 SPI clocks continue to operate in wait mode #0 1 SPI clocks stop when the MCU enters wait mode #1 RXDMAE Receive DMA enable 2 1 read-write 0 DMA request for receive is disabled and interrupt from SPRF is allowed #0 1 DMA request for receive is enabled and interrupt from SPRF is disabled #1 BIDIROE Bidirectional mode output enable 3 1 read-write 0 Output driver disabled so SPI data I/O pin acts as an input #0 1 SPI I/O pin enabled as an output #1 MODFEN Master mode-fault function enable 4 1 read-write 0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI #0 1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output #1 TXDMAE Transmit DMA enable 5 1 read-write 0 DMA request for transmit is disabled and interrupt from SPTEF is allowed #0 1 DMA request for transmit is enabled and interrupt from SPTEF is disabled #1 SPIMODE SPI 8-bit or 16-bit mode 6 1 read-write 0 8-bit SPI shift register, match register, and buffers #0 1 16-bit SPI shift register, match register, and buffers #1 SPMIE SPI match interrupt enable 7 1 read-write 0 Interrupts from SPMF inhibited (use polling) #0 1 When SPMF is 1, requests a hardware interrupt #1 BR SPI baud rate register 0x2 8 read-write 0 0xFF SPR SPI baud rate divisor 0 4 read-write 0000 Baud rate divisor is 2 #0000 0001 Baud rate divisor is 4 #0001 0010 Baud rate divisor is 8 #0010 0011 Baud rate divisor is 16 #0011 0100 Baud rate divisor is 32 #0100 0101 Baud rate divisor is 64 #0101 0110 Baud rate divisor is 128 #0110 0111 Baud rate divisor is 256 #0111 1000 Baud rate divisor is 512 #1000 SPPR SPI baud rate prescale divisor 4 3 read-write 000 Baud rate prescaler divisor is 1 #000 001 Baud rate prescaler divisor is 2 #001 010 Baud rate prescaler divisor is 3 #010 011 Baud rate prescaler divisor is 4 #011 100 Baud rate prescaler divisor is 5 #100 101 Baud rate prescaler divisor is 6 #101 110 Baud rate prescaler divisor is 7 #110 111 Baud rate prescaler divisor is 8 #111 RESERVED no description available 7 1 read-only S SPI status register 0x3 8 read-only 0x20 0xFF RFIFOEF SPI read FIFO empty flag 0 1 read-only 0 Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the DL register in 8-bit mode will empty the read FIFO. #0 1 Read FIFO is empty. #1 TXFULLF Transmit FIFO full flag 1 1 read-only 0 Transmit FIFO has less than 8 bytes #0 1 Transmit FIFO has 8 bytes of data #1 TNEAREF Transmit FIFO nearly empty flag 2 1 read-only 0 Transmit FIFO has more than 16 bits (when C3[5] is 0) or more than 32 bits (when C3[5] is 1) remaining to transmit #0 1 Transmit FIFO has an amount of data equal to or less than 16 bits (when C3[5] is 0) or 32 bits (when C3[5] is 1) remaining to transmit #1 RNFULLF Receive FIFO nearly full flag 3 1 read-only 0 Receive FIFO has received less than 48 bits (when C3[4] is 0) or less than 32 bits (when C3[4] is 1) #0 1 Receive FIFO has received data of an amount equal to or greater than 48 bits (when C3[4] is 0) or 32 bits (when C3[4] is 1) #1 MODF Master mode fault flag 4 1 read-only 0 No mode fault error #0 1 Mode fault error detected #1 SPTEF SPI transmit buffer empty flag (when FIFO is not supported or not enabled) or SPI transmit FIFO empty flag (when FIFO is supported and enabled) 5 1 read-only 0 SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when FIFOMODE is 1) #0 1 SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when FIFOMODE is 1) #1 SPMF SPI match flag 6 1 read-only 0 Value in the receive data buffer does not match the value in the MH:ML registers #0 1 Value in the receive data buffer matches the value in the MH:ML registers #1 SPRF SPI read buffer full flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (when FIFO is supported and enabled) 7 1 read-only 0 No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is not full (when FIFOMODE is 1) #0 1 Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is full (when FIFOMODE is 1) #1 DH SPI data register high 0x4 8 read-write 0 0xFF Bits Data (high byte) 0 8 read-write DL SPI data register low 0x5 8 read-write 0 0xFF Bits Data (low byte) 0 8 read-write MH SPI match register high 0x6 8 read-write 0 0xFF Bits Hardware compare value (high byte) 0 8 read-write ML SPI match register low 0x7 8 read-write 0 0xFF Bits Hardware compare value (low byte) 0 8 read-write C3 SPI control register 3 0x8 8 read-write 0 0xFF FIFOMODE FIFO mode enable 0 1 read-write 0 Buffer mode disabled #0 1 Data available in the receive data buffer #1 RNFULLIEN Receive FIFO nearly full interrupt enable 1 1 read-write 0 No interrupt upon RNFULLF being set #0 1 Enable interrupts upon RNFULLF being set #1 TNEARIEN Transmit FIFO nearly empty interrupt enable 2 1 read-write 0 No interrupt upon TNEAREF being set #0 1 Enable interrupts upon TNEAREF being set #1 INTCLR Interrupt clearing mechanism select 3 1 read-write 0 These interrupts are cleared when the corresponding flags are cleared depending on the state of the FIFOs #0 1 These interrupts are cleared by writing the corresponding bits in the CI register #1 RNFULLF_MARK Receive FIFO nearly full watermark 4 1 read-write 0 RNFULLF is set when the receive FIFO has 48 bits or more #0 1 RNFULLF is set when the receive FIFO has 32 bits or more #1 TNEAREF_MARK Transmit FIFO nearly empty watermark 5 1 read-write 0 TNEAREF is set when the transmit FIFO has 16 bits or less #0 1 TNEAREF is set when the transmit FIFO has 32 bits or less #1 RESERVED no description available 6 2 read-only CI SPI clear interrupt register 0x9 8 read-write 0 0xFF SPRFCI Receive FIFO full flag clear interrupt 0 1 write-only SPTEFCI Transmit FIFO empty flag clear interrupt 1 1 write-only RNFULLFCI Receive FIFO nearly full flag clear interrupt 2 1 write-only TNEAREFCI Transmit FIFO nearly empty flag clear interrupt 3 1 write-only RXFOF Receive FIFO overflow flag 4 1 read-only 0 Receive FIFO overflow condition has not occurred #0 1 Receive FIFO overflow condition occurred #1 TXFOF Transmit FIFO overflow flag 5 1 read-only 0 Transmit FIFO overflow condition has not occurred #0 1 Transmit FIFO overflow condition occurred #1 RXFERR Receive FIFO error flag 6 1 read-only 0 No receive FIFO error occurred #0 1 A receive FIFO error occurred #1 TXFERR Transmit FIFO error flag 7 1 read-only 0 No transmit FIFO error occurred #0 1 A transmit FIFO error occurred #1 CMP0 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP CMP0_ 0x40050000 0 0x7 registers CR0 CMP Control Register 0 0 8 read-write 0 0xFF HYSTCTR Comparator hard block hysteresis control 0 1 read-write 0 Level 0 #0 1 Level 1 #1 RESERVED no description available 1 3 read-only FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. #000 001 1 consecutive sample must agree (comparator output is simply sampled). #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 RESERVED no description available 7 1 read-only CR1 CMP Control Register 1 0x1 8 read-write 0 0xFF EN Comparator Module Enable 0 1 read-write 0 Analog Comparator disabled. #0 1 Analog Comparator enabled. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 The comparator output (CMPO) is not available on the associated CMPO output pin. The pin is available for use by other on-chip functions. #0 1 The comparator output (CMPO) is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin. #1 COS Comparator Output Select 2 1 read-write 0 Set CMPO to equal COUT (filtered comparator output). #0 1 Set CMPO to equal COUTA (unfiltered comparator output). #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 PMODE Power Mode Select 4 1 read-write 0 Low Speed (LS) comparison mode selected. #0 1 High Speed (HS) comparison mode selected. #1 RESERVED no description available 5 1 read-only WE Windowing Enable 6 1 read-write 0 Windowing mode not selected. #0 1 Windowing mode selected. #1 SE Sample Enable 7 1 read-write 0 Sampling mode not selected. #0 1 Sampling mode selected. #1 FPR CMP Filter Period Register 0x2 8 read-write 0 0xFF FILT_PER Filter Sample Period 0 8 read-write SCR CMP Status and Control Register 0x3 8 read-write 0 0xFF COUT Analog Comparator Output 0 1 read-only CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling edge on COUT has not been detected. #0 1 Falling edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising edge on COUT has not been detected. #0 1 Rising edge on COUT has occurred. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RESERVED no description available 5 1 read-only DMAEN DMA Enable Control 6 1 read-write 0 DMA disabled. #0 1 DMA enabled. #1 RESERVED no description available 7 1 read-only DACCR DAC Control Register 0x4 8 read-write 0 0xFF VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference Vin. #0 1 Vin2 is selected as resistor ladder network supply reference Vin. #1 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 MUXCR MUX Control Register 0x5 8 read-write 0 0xFF MSEL Minus Input MUX Control 0 2 read-write 00 IN0 #00 01 IN1 #01 10 IN2 #10 11 6-bit DAC output is selected #11 RESERVED no description available 2 2 read-only PSEL Plus Input MUX Control 4 2 read-write 00 IN0 #00 01 IN1 #01 10 IN2 #10 11 6-bit DAC output is selected #11 RESERVED no description available 6 2 read-only MUXPE MUX Pin Enable Register 0x6 8 read-write 0 0xFF INPE Positive Input Pin Enable 0 3 read-write RESERVED no description available 3 5 read-only CMP1 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP CMP1_ 0x40051000 0 0x7 registers CR0 CMP Control Register 0 0 8 read-write 0 0xFF HYSTCTR Comparator hard block hysteresis control 0 1 read-write 0 Level 0 #0 1 Level 1 #1 RESERVED no description available 1 3 read-only FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. #000 001 1 consecutive sample must agree (comparator output is simply sampled). #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 RESERVED no description available 7 1 read-only CR1 CMP Control Register 1 0x1 8 read-write 0 0xFF EN Comparator Module Enable 0 1 read-write 0 Analog Comparator disabled. #0 1 Analog Comparator enabled. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 The comparator output (CMPO) is not available on the associated CMPO output pin. The pin is available for use by other on-chip functions. #0 1 The comparator output (CMPO) is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin. #1 COS Comparator Output Select 2 1 read-write 0 Set CMPO to equal COUT (filtered comparator output). #0 1 Set CMPO to equal COUTA (unfiltered comparator output). #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 PMODE Power Mode Select 4 1 read-write 0 Low Speed (LS) comparison mode selected. #0 1 High Speed (HS) comparison mode selected. #1 RESERVED no description available 5 1 read-only WE Windowing Enable 6 1 read-write 0 Windowing mode not selected. #0 1 Windowing mode selected. #1 SE Sample Enable 7 1 read-write 0 Sampling mode not selected. #0 1 Sampling mode selected. #1 FPR CMP Filter Period Register 0x2 8 read-write 0 0xFF FILT_PER Filter Sample Period 0 8 read-write SCR CMP Status and Control Register 0x3 8 read-write 0 0xFF COUT Analog Comparator Output 0 1 read-only CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling edge on COUT has not been detected. #0 1 Falling edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising edge on COUT has not been detected. #0 1 Rising edge on COUT has occurred. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RESERVED no description available 5 1 read-only DMAEN DMA Enable Control 6 1 read-write 0 DMA disabled. #0 1 DMA enabled. #1 RESERVED no description available 7 1 read-only DACCR DAC Control Register 0x4 8 read-write 0 0xFF VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference Vin. #0 1 Vin2 is selected as resistor ladder network supply reference Vin. #1 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 MUXCR MUX Control Register 0x5 8 read-write 0 0xFF MSEL Minus Input MUX Control 0 2 read-write 00 IN0 #00 01 IN1 #01 10 IN2 #10 11 6-bit DAC output is selected #11 RESERVED no description available 2 2 read-only PSEL Plus Input MUX Control 4 2 read-write 00 IN0 #00 01 IN1 #01 10 IN2 #10 11 6-bit DAC output is selected #11 RESERVED no description available 6 2 read-only MUXPE MUX Pin Enable Register 0x6 8 read-write 0 0xFF INPE Positive Input Pin Enable 0 3 read-write RESERVED no description available 3 5 read-only CMP2 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP CMP2_ 0x40052000 0 0x7 registers CR0 CMP Control Register 0 0 8 read-write 0 0xFF HYSTCTR Comparator hard block hysteresis control 0 1 read-write 0 Level 0 #0 1 Level 1 #1 RESERVED no description available 1 3 read-only FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. #000 001 1 consecutive sample must agree (comparator output is simply sampled). #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 RESERVED no description available 7 1 read-only CR1 CMP Control Register 1 0x1 8 read-write 0 0xFF EN Comparator Module Enable 0 1 read-write 0 Analog Comparator disabled. #0 1 Analog Comparator enabled. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 The comparator output (CMPO) is not available on the associated CMPO output pin. The pin is available for use by other on-chip functions. #0 1 The comparator output (CMPO) is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin. #1 COS Comparator Output Select 2 1 read-write 0 Set CMPO to equal COUT (filtered comparator output). #0 1 Set CMPO to equal COUTA (unfiltered comparator output). #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 PMODE Power Mode Select 4 1 read-write 0 Low Speed (LS) comparison mode selected. #0 1 High Speed (HS) comparison mode selected. #1 RESERVED no description available 5 1 read-only WE Windowing Enable 6 1 read-write 0 Windowing mode not selected. #0 1 Windowing mode selected. #1 SE Sample Enable 7 1 read-write 0 Sampling mode not selected. #0 1 Sampling mode selected. #1 FPR CMP Filter Period Register 0x2 8 read-write 0 0xFF FILT_PER Filter Sample Period 0 8 read-write SCR CMP Status and Control Register 0x3 8 read-write 0 0xFF COUT Analog Comparator Output 0 1 read-only CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling edge on COUT has not been detected. #0 1 Falling edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising edge on COUT has not been detected. #0 1 Rising edge on COUT has occurred. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RESERVED no description available 5 1 read-only DMAEN DMA Enable Control 6 1 read-write 0 DMA disabled. #0 1 DMA enabled. #1 RESERVED no description available 7 1 read-only DACCR DAC Control Register 0x4 8 read-write 0 0xFF VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference Vin. #0 1 Vin2 is selected as resistor ladder network supply reference Vin. #1 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 MUXCR MUX Control Register 0x5 8 read-write 0 0xFF MSEL Minus Input MUX Control 0 2 read-write 00 IN0 #00 01 IN1 #01 10 IN2 #10 11 6-bit DAC output is selected #11 RESERVED no description available 2 2 read-only PSEL Plus Input MUX Control 4 2 read-write 00 IN0 #00 01 IN1 #01 10 IN2 #10 11 6-bit DAC output is selected #11 RESERVED no description available 6 2 read-only MUXPE MUX Pin Enable Register 0x6 8 read-write 0 0xFF INPE Positive Input Pin Enable 0 3 read-write RESERVED no description available 3 5 read-only CMP3 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP CMP3_ 0x40053000 0 0x7 registers CR0 CMP Control Register 0 0 8 read-write 0 0xFF HYSTCTR Comparator hard block hysteresis control 0 1 read-write 0 Level 0 #0 1 Level 1 #1 RESERVED no description available 1 3 read-only FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. #000 001 1 consecutive sample must agree (comparator output is simply sampled). #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 RESERVED no description available 7 1 read-only CR1 CMP Control Register 1 0x1 8 read-write 0 0xFF EN Comparator Module Enable 0 1 read-write 0 Analog Comparator disabled. #0 1 Analog Comparator enabled. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 The comparator output (CMPO) is not available on the associated CMPO output pin. The pin is available for use by other on-chip functions. #0 1 The comparator output (CMPO) is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin. #1 COS Comparator Output Select 2 1 read-write 0 Set CMPO to equal COUT (filtered comparator output). #0 1 Set CMPO to equal COUTA (unfiltered comparator output). #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 PMODE Power Mode Select 4 1 read-write 0 Low Speed (LS) comparison mode selected. #0 1 High Speed (HS) comparison mode selected. #1 RESERVED no description available 5 1 read-only WE Windowing Enable 6 1 read-write 0 Windowing mode not selected. #0 1 Windowing mode selected. #1 SE Sample Enable 7 1 read-write 0 Sampling mode not selected. #0 1 Sampling mode selected. #1 FPR CMP Filter Period Register 0x2 8 read-write 0 0xFF FILT_PER Filter Sample Period 0 8 read-write SCR CMP Status and Control Register 0x3 8 read-write 0 0xFF COUT Analog Comparator Output 0 1 read-only CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling edge on COUT has not been detected. #0 1 Falling edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising edge on COUT has not been detected. #0 1 Rising edge on COUT has occurred. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RESERVED no description available 5 1 read-only DMAEN DMA Enable Control 6 1 read-write 0 DMA disabled. #0 1 DMA enabled. #1 RESERVED no description available 7 1 read-only DACCR DAC Control Register 0x4 8 read-write 0 0xFF VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference Vin. #0 1 Vin2 is selected as resistor ladder network supply reference Vin. #1 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 MUXCR MUX Control Register 0x5 8 read-write 0 0xFF MSEL Minus Input MUX Control 0 2 read-write 00 IN0 #00 01 IN1 #01 10 IN2 #10 11 6-bit DAC output is selected #11 RESERVED no description available 2 2 read-only PSEL Plus Input MUX Control 4 2 read-write 00 IN0 #00 01 IN1 #01 10 IN2 #10 11 6-bit DAC output is selected #11 RESERVED no description available 6 2 read-only MUXPE MUX Pin Enable Register 0x6 8 read-write 0 0xFF INPE Positive Input Pin Enable 0 3 read-write RESERVED no description available 3 5 read-only PMC Power management PMC_ 0x40054000 0 0x2 registers INT_LVD_LVW 36 SPMSC1 System Power Management Status and Control 1 Register 0 8 read-write 0x1C 0xFF BGBE Bandgap Buffer Enable 0 1 read-write 0 Bandgap buffer disabled. #0 1 Bandgap buffer enabled. #1 BGBDS Bandgap Buffer Drive Select 1 1 read-write 0 Bandgap buffer enabled in low drive mode if BGBE = 1. #0 1 Bandgap buffer enabled in high drive mode if BGBE = 1. #1 LVDE Low-Voltage Detect Enable 2 1 read-write 0 LVD logic disabled. #0 1 LVD logic enabled. #1 LVDSE Low-Voltage Detect Stop Enable 3 1 read-write 0 Low-voltage detect disabled during stop mode. #0 1 Low-voltage detect enabled during stop mode. #1 LVDRE Low-Voltage Detect Reset Enable 4 1 read-write 0 LVD events do not generate hardware resets. #0 1 Force an MCU reset when an enabled low-voltage detect event occurs. #1 LVWIE Low-Voltage Warning Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling). #0 1 Request a hardware interrupt when LVWF = 1. #1 LVWACK Low-Voltage Warning Acknowledge 6 1 write-only LVWF Low-Voltage Warning Flag 7 1 read-only 0 Low-voltage warning is not present. #0 1 Low-voltage warning is present or was present. #1 SPMSC2 System Power Management Status and Control 2 Register 0x1 8 read-write 0 0xFF RESERVED no description available 0 4 read-only LVWV Low-Voltage Warning Voltage Select 4 2 read-write 00 Low trip point selected (VLVW = VLVW1). #00 01 Middle 1 trip point selected (VLVW = VLVW2). #01 10 Middle 2 trip point selected (VLVW = VLVW3). #10 11 High trip point selected (VLVW = VLVW4). #11 LVDV Low-Voltage Detect Voltage Select 6 1 read-write 0 Low trip point selected (VLVD = VLVDL). #0 1 High trip point selected (VLVD = VLVDH). #1 RESERVED no description available 7 1 read-only SMC System mode controller SMC_ 0x40056000 0 0x4 registers PMPROT SMC Power Mode Protection Register 0 8 read-write 0 0xFF RESERVED no description available 0 1 read-only RESERVED no description available 1 1 read-only RESERVED no description available 2 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 4 1 read-only AVLP Allow Very Low Power Stop Mode 5 1 read-write 0 VLPS is not allowed. #0 1 VLPS is allowed. #1 RESERVED no description available 6 2 read-only PMCTRL SMC Power Mode Control Register 0x1 8 read-write 0 0xFF STOPM Stop Mode Control 0 3 read-write 000 STOP. #000 010 VLPS. #010 STOPA Stop Aborted 3 1 read-only 0 The previous stop mode entry was successsful. #0 1 The previous stop mode entry was aborted. #1 RESERVED no description available 4 1 read-only RESERVED no description available 5 3 read-only PMSTAT SMC Power Mode Status Register 0x3 8 read-only 0 0xFF RUN CurrCurrent Power mode is run 0 1 read-only 0 Current Power mode is not run. #0 1 Current Power mode is run. #1 STOP Current Power mode is STOP 1 1 read-only 0 Current Power mode is not stop. #0 1 Current Power mode is stop. #1 RESERVED no description available 2 2 read-only VLPS Current Power mode is VLPS 4 1 read-only 0 Current Power mode is not VLPS. #0 1 Current Power mode is VLPS. #1 RESERVED no description available 5 3 read-only RCM Reset control module RCM_ 0x40057000 0 0x6 registers SRSL RCM System Reset Status Low Register 0 8 read-only 0x82 0xFF RESERVED no description available 0 1 read-only LVD Low Voltage Detect 1 1 read-only 0 Reset not caused by LVD trip or POR. #0 1 Reset caused by LVD trip or POR. #1 LOC Loss Of Clock Reset 2 1 read-only 0 Reset not caused by Watchdog Reset. #0 1 Reset caused by loss of external clock. #1 RESERVED no description available 3 2 read-only COP COP Watchdog Reset 5 1 read-only 0 Reset not caused by Watchdog Reset. #0 1 Reset caused by Watchdog Reset. #1 PIN External RESETb Pin 6 1 read-only 0 Reset not caused by external RESETb pin. #0 1 Reset caused by external RESETb pin. #1 POR Power On Reset 7 1 read-only 0 Reset not caused by POR. #0 1 Reset caused by POR. #1 SRSH RCM System Reset Status High Register 0x1 8 read-only 0 0xFF JTAG JTAG Reset 0 1 read-only 0 Reset not caused by JTAG. #0 1 Reset caused by JTAG. #1 LOCKUP CPU LOCKUP Reset 1 1 read-only 0 Reset not caused by CPU LOCKUP. #0 1 Reset caused by CPU LOCKUP. #1 SW Software Reset 2 1 read-only 0 Reset not caused by Software Reset. #0 1 Reset caused by Software Reset. #1 MDMAP MDM-AP system reset request 3 1 read-only 0 Reset not caused by MDM-AP request. #0 1 Reset caused by MDM-AP request. #1 RESERVED no description available 4 1 read-only SACKERR Stop Mode Acknowledge Error Reset 5 1 read-only 0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode. #0 1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode. #1 RESERVED no description available 6 2 read-only RPFC RCM RESETb Pin Filter Control Register 0x4 8 read-write 0 0xFF RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes 0 2 read-write 00 All filtering disabled. #00 01 Bus Clock filter enabled. #01 10 LPO clock filter enabled. #10 11 All filtering disabled. #11 RSTFLTSS Reset Pin Filter Select in Stop Modes 2 1 read-write 0 All filtering disabled. #0 1 LPO clock filter enabled. #1 RESERVED no description available 3 5 read-only RPFW RCM RESETb Pin Filter Width Register 0x5 8 read-write 0 0xFF RSTFLTSS RESETb Pin bus clock filter width 0 5 read-write 00000 Bus Clock Filter Width is 1. #00000 00001 Bus Clock Filter Width is 2. #00001 00010 Bus Clock Filter Width is 3. #00010 00011 Bus Clock Filter Width is 4. #00011 00100 Bus Clock Filter Width is 5. #00100 00101 Bus Clock Filter Width is 6. #00101 00110 Bus Clock Filter Width is 7. #00110 00111 Bus Clock Filter Width is 8. #00111 01000 Bus Clock Filter Width is 9. #01000 01001 Bus Clock Filter Width is 10. #01001 01010 Bus Clock Filter Width is 11. #01010 01011 Bus Clock Filter Width is 12. #01011 01100 Bus Clock Filter Width is 13. #01100 01101 Bus Clock Filter Width is 14. #01101 01110 Bus Clock Filter Width is 15. #01110 01111 Bus Clock Filter Width is 16. #01111 10000 Bus Clock Filter Width is 17. #10000 10001 Bus Clock Filter Width is 18. #10001 10010 Bus Clock Filter Width is 19. #10010 10011 Bus Clock Filter Width is 20. #10011 10100 Bus Clock Filter Width is 21. #10100 10101 Bus Clock Filter Width is 22. #10101 10110 Bus Clock Filter Width is 23. #10110 10111 Bus Clock Filter Width is 24. #10111 11000 Bus Clock Filter Width is 25. #11000 11001 Bus Clock Filter Width is 26. #11001 11010 Bus Clock Filter Width is 27. #11010 11011 Bus Clock Filter Width is 28. #11011 11100 Bus Clock Filter Width is 29. #11100 11101 Bus Clock Filter Width is 30. #11101 11110 Bus Clock Filter Width is 31. #11110 11111 Bus Clock Filter Width is 32. #11111 RESERVED no description available 5 3 read-only PTA General Purpose Input/Output GPIO GPIOA_ 0x4007F000 0 0x18 registers INT_PORTA 75 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PTB General Purpose Input/Output GPIO GPIOB_ 0x4007F040 0 0x18 registers INT_PORTB 76 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PTC General Purpose Input/Output GPIO GPIOC_ 0x4007F080 0 0x18 registers INT_PORTC 77 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PTD General Purpose Input/Output GPIO GPIOD_ 0x4007F0C0 0 0x18 registers INT_PORTD 78 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PTE General Purpose Input/Output GPIO GPIOE_ 0x4007F100 0 0x18 registers INT_PORTE 79 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 SystemControl System Control Registers SCB_ 0xE000E000 0x8 0xD38 registers INT_Hard_Fault 3 INT_Mem_Manage_Fault 4 INT_Bus_Fault 5 INT_Usage_Fault 6 INT_SVCall 11 INT_PendableSrvReq 14 ACTLR Auxiliary Control Register, 0x8 32 read-write 0 0xFFFFFFFF DISMCYCINT Disables interruption of multi-cycle instructions. 0 1 read-write DISDEFWBUF Disables write buffer use during default memory map accesses. 1 1 read-write DISFOLD Disables folding of IT instructions. 2 1 read-write RESERVED Reserved 3 1 read-only RESERVED Reserved 4 1 read-only RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only RESERVED Reserved 8 1 read-only RESERVED Reserved 9 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 15 1 read-only RESERVED Reserved 16 1 read-only RESERVED Reserved 17 1 read-only RESERVED Reserved 18 1 read-only RESERVED Reserved 19 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 22 1 read-only RESERVED Reserved 23 1 read-only RESERVED Reserved 24 1 read-only RESERVED Reserved 25 1 read-only RESERVED Reserved 26 1 read-only RESERVED Reserved 27 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only CPUID CPUID Base Register 0xD00 32 read-only 0x410FC240 0xFFFFFFFF REVISION Indicates patch release: 0x0 = Patch 0 0 4 read-only PARTNO Indicates part number 4 12 read-only RESERVED (Constant) Reads as 1 16 1 read-only RESERVED (Constant) Reads as 1 17 1 read-only RESERVED (Constant) Reads as 1 18 1 read-only RESERVED (Constant) Reads as 1 19 1 read-only VARIANT Indicates processor revision: 0x2 = Revision 2 20 4 read-only IMPLEMENTER Implementer code 24 8 read-only ICSR Interrupt Control and State Register 0xD04 32 read-write 0 0xFFFFFFFF VECTACTIVE Active exception number 0 9 read-only RESERVED Reserved 9 1 read-only RESERVED Reserved 10 1 read-only RETTOBASE no description available 11 1 read-only 0 there are preempted active exceptions to execute #0 1 there are no active exceptions, or the currently-executing exception is the only active exception #1 VECTPENDING Exception number of the highest priority pending enabled exception 12 6 read-only RESERVED Reserved 18 1 read-only RESERVED Reserved 19 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only ISRPENDING no description available 22 1 read-only ISRPREEMPT no description available 23 1 read-only 0 Will not service #0 1 Will service a pending exception #1 RESERVED Reserved 24 1 read-only PENDSTCLR no description available 25 1 write-only 0 no effect #0 1 removes the pending state from the SysTick exception #1 PENDSTSET no description available 26 1 read-write 0 write: no effect; read: SysTick exception is not pending #0 1 write: changes SysTick exception state to pending; read: SysTick exception is pending #1 PENDSVCLR no description available 27 1 write-only 0 no effect #0 1 removes the pending state from the PendSV exception #1 PENDSVSET no description available 28 1 read-write 0 write: no effect; read: PendSV exception is not pending #0 1 write: changes PendSV exception state to pending; read: PendSV exception is pending #1 RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only NMIPENDSET no description available 31 1 read-write 0 write: no effect; read: NMI exception is not pending #0 1 write: changes NMI exception state to pending; read: NMI exception is pending #1 VTOR Vector Table Offset Register 0xD08 32 read-write 0 0xFFFFFFFF RESERVED Reserved 0 1 read-write RESERVED Reserved 1 1 read-write RESERVED Reserved 2 1 read-write RESERVED Reserved 3 1 read-write RESERVED Reserved 4 1 read-write RESERVED Reserved 5 1 read-write RESERVED Reserved 6 1 read-write TBLOFF Vector table base offset 7 25 read-write AIRCR Application Interrupt and Reset Control Register 0xD0C 32 read-write 0 0xFFFFFFFF VECTRESET no description available 0 1 write-only VECTCLRACTIVE no description available 1 1 write-only SYSRESETREQ no description available 2 1 write-only 0 no system reset request #0 1 asserts a signal to the outer system that requests a reset #1 RESERVED Reserved 3 1 read-only RESERVED Reserved 4 1 read-only RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only PRIGROUP Interrupt priority grouping field. This field determines the split of group priority from subpriority. 8 3 read-write RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only ENDIANNESS no description available 15 1 read-only 0 Little-endian #0 1 Big-endian #1 VECTKEY Register key 16 16 read-write SCR System Control Register 0xD10 32 read-write 0 0xFFFFFFFF RESERVED Reserved 0 1 read-only SLEEPONEXIT no description available 1 1 read-write 0 o not sleep when returning to Thread mode #0 1 enter sleep, or deep sleep, on return from an ISR #1 SLEEPDEEP no description available 2 1 read-write 0 sleep #0 1 deep sleep #1 RESERVED Reserved 3 1 read-only SEVONPEND no description available 4 1 read-write 0 only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded #0 1 enabled events and all interrupts, including disabled interrupts, can wakeup the processor #1 RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only RESERVED Reserved 8 1 read-only RESERVED Reserved 9 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 15 1 read-only RESERVED Reserved 16 1 read-only RESERVED Reserved 17 1 read-only RESERVED Reserved 18 1 read-only RESERVED Reserved 19 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 22 1 read-only RESERVED Reserved 23 1 read-only RESERVED Reserved 24 1 read-only RESERVED Reserved 25 1 read-only RESERVED Reserved 26 1 read-only RESERVED Reserved 27 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only CCR Configuration and Control Register 0xD14 32 read-write 0 0xFFFFFFFF NONBASETHRDENA no description available 0 1 read-write 0 processor can enter Thread mode only when no exception is active #0 1 processor can enter Thread mode from any level under the control of an EXC_RETURN value #1 USERSETMPEND Enables unprivileged software access to the STIR 1 1 read-write 0 disable #0 1 enable #1 RESERVED Reserved 2 1 read-only UNALIGN_TRP Enables unaligned access traps 3 1 read-write 0 do not trap unaligned halfword and word accesses #0 1 trap unaligned halfword and word accesses #1 DIV_0_TRP Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0 4 1 read-write 0 do not trap divide by 0 #0 1 trap divide by 0 #1 RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only BFHFNMIGN Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. 8 1 read-write 0 data bus faults caused by load and store instructions cause a lock-up #0 1 handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions #1 STKALIGN Indicates stack alignment on exception entry 9 1 read-write 0 4-byte aligned #0 1 8-byte aligned #1 RESERVED Reserved 10 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 15 1 read-only RESERVED Reserved 16 1 read-only RESERVED Reserved 17 1 read-only RESERVED Reserved 18 1 read-only RESERVED Reserved 19 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 22 1 read-only RESERVED Reserved 23 1 read-only RESERVED Reserved 24 1 read-only RESERVED Reserved 25 1 read-only RESERVED Reserved 26 1 read-only RESERVED Reserved 27 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only SHPR1 System Handler Priority Register 1 0xD18 32 read-write 0 0xFFFFFFFF PRI_4 Priority of system handler 4, MemManage 0 8 read-write PRI_5 Priority of system handler 5, BusFault 8 8 read-write PRI_6 Priority of system handler 6, UsageFault 16 8 read-write RESERVED Reserved 24 1 read-only RESERVED Reserved 25 1 read-only RESERVED Reserved 26 1 read-only RESERVED Reserved 27 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only SHPR2 System Handler Priority Register 2 0xD1C 32 read-write 0 0xFFFFFFFF RESERVED Reserved 0 1 read-only RESERVED Reserved 1 1 read-only RESERVED Reserved 2 1 read-only RESERVED Reserved 3 1 read-only RESERVED Reserved 4 1 read-only RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only RESERVED Reserved 8 1 read-only RESERVED Reserved 9 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 15 1 read-only RESERVED Reserved 16 1 read-only RESERVED Reserved 17 1 read-only RESERVED Reserved 18 1 read-only RESERVED Reserved 19 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 22 1 read-only RESERVED Reserved 23 1 read-only PRI_11 Priority of system handler 11, SVCall 24 8 read-write SHPR3 System Handler Priority Register 3 0xD20 32 read-write 0 0xFFFFFFFF RESERVED Reserved 0 1 read-only RESERVED Reserved 1 1 read-only RESERVED Reserved 2 1 read-only RESERVED Reserved 3 1 read-only RESERVED Reserved 4 1 read-only RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only RESERVED Reserved 8 1 read-only RESERVED Reserved 9 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 15 1 read-only PRI_14 Priority of system handler 14, PendSV 16 8 read-write PRI_15 Priority of system handler 15, SysTick exception 24 8 read-write SHCSR System Handler Control and State Register 0xD24 32 read-write 0 0xFFFFFFFF MEMFAULTACT no description available 0 1 read-write 0 exception is not active #0 1 exception is active #1 BUSFAULTACT no description available 1 1 read-write 0 exception is not active #0 1 exception is active #1 RESERVED Reserved 2 1 read-write USGFAULTACT no description available 3 1 read-write 0 exception is not active #0 1 exception is active #1 RESERVED Reserved 4 1 read-write RESERVED Reserved 5 1 read-write RESERVED Reserved 6 1 read-write SVCALLACT no description available 7 1 read-write 0 exception is not active #0 1 exception is active #1 MONITORACT no description available 8 1 read-write 0 exception is not active #0 1 exception is active #1 RESERVED Reserved 9 1 read-write PENDSVACT no description available 10 1 read-write 0 exception is not active #0 1 exception is active #1 SYSTICKACT no description available 11 1 read-write 0 exception is not active #0 1 exception is active #1 USGFAULTPENDED no description available 12 1 read-write 0 exception is not pending #0 1 exception is pending #1 MEMFAULTPENDED no description available 13 1 read-write 0 exception is not pending #0 1 exception is pending #1 BUSFAULTPENDED no description available 14 1 read-write 0 exception is not pending #0 1 exception is pending #1 SVCALLPENDED no description available 15 1 read-write 0 exception is not pending #0 1 exception is pending #1 MEMFAULTENA no description available 16 1 read-write 0 disable the exception #0 1 enable the exception #1 BUSFAULTENA no description available 17 1 read-write 0 disable the exception #0 1 enable the exception #1 USGFAULTENA no description available 18 1 read-write 0 disable the exception #0 1 enable the exception #1 RESERVED Reserved 19 1 read-write RESERVED Reserved 20 1 read-write RESERVED Reserved 21 1 read-write RESERVED Reserved 22 1 read-write RESERVED Reserved 23 1 read-write RESERVED Reserved 24 1 read-write RESERVED Reserved 25 1 read-write RESERVED Reserved 26 1 read-write RESERVED Reserved 27 1 read-write RESERVED Reserved 28 1 read-write RESERVED Reserved 29 1 read-write RESERVED Reserved 30 1 read-write RESERVED Reserved 31 1 read-write CFSR Configurable Fault Status Registers 0xD28 32 read-write 0 0xFFFFFFFF IACCVIOL no description available 0 1 read-write 0 no instruction access violation fault #0 1 the processor attempted an instruction fetch from a location that does not permit execution #1 DACCVIOL no description available 1 1 read-write 0 no data access violation fault #0 1 the processor attempted a load or store at a location that does not permit the operation #1 RESERVED Reserved 2 1 read-only MUNSTKERR no description available 3 1 read-write 0 no unstacking fault #0 1 unstack for an exception return has caused one or more access violations #1 MSTKERR no description available 4 1 read-write 0 no stacking fault #0 1 stacking for an exception entry has caused one or more access violations #1 MLSPERR no description available 5 1 read-write 0 No MemManage fault occurred during floating-point lazy state preservation #0 1 A MemManage fault occurred during floating-point lazy state preservation #1 RESERVED Reserved 6 1 read-only MMARVALID no description available 7 1 read-write 0 value in MMAR is not a valid fault address #0 1 MMAR holds a valid fault address #1 IBUSERR no description available 8 1 read-write 0 no instruction bus error #0 1 instruction bus error #1 PRECISERR no description available 9 1 read-write 0 no precise data bus error #0 1 a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault #1 IMPRECISERR no description available 10 1 read-write 0 no imprecise data bus error #0 1 a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error #1 UNSTKERR no description available 11 1 read-write 0 no unstacking fault #0 1 unstack for an exception return has caused one or more BusFaults #1 STKERR no description available 12 1 read-write 0 no stacking fault #0 1 stacking for an exception entry has caused one or more BusFaults #1 LSPERR no description available 13 1 read-write 0 No bus fault occurred during floating-point lazy state preservation #0 1 A bus fault occurred during floating-point lazy state preservation #1 RESERVED Reserved 14 1 read-only BFARVALID no description available 15 1 read-write 0 value in BFAR is not a valid fault address #0 1 BFAR holds a valid fault address #1 UNDEFINSTR no description available 16 1 read-write 0 no undefined instruction UsageFault #0 1 the processor has attempted to execute an undefined instruction #1 INVSTATE no description available 17 1 read-write 0 no invalid state UsageFault #0 1 the processor has attempted to execute an instruction that makes illegal use of the EPSR #1 INVPC no description available 18 1 read-write 0 no invalid PC load UsageFault #0 1 the processor has attempted an illegal load of EXC_RETURN to the PC #1 NOCP no description available 19 1 read-write 0 no UsageFault caused by attempting to access a coprocessor #0 1 the processor has attempted to access a coprocessor #1 RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 22 1 read-only RESERVED Reserved 23 1 read-only UNALIGNED no description available 24 1 read-write 0 no unaligned access fault, or unaligned access trapping not enabled #0 1 the processor has made an unaligned memory access #1 DIVBYZERO no description available 25 1 read-write 0 no divide by zero fault, or divide by zero trapping not enabled #0 1 the processor has executed an SDIV or UDIV instruction with a divisor of 0 #1 RESERVED Reserved 26 1 read-only RESERVED Reserved 27 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only HFSR HardFault Status register 0xD2C 32 read-write 0 0xFFFFFFFF RESERVED Reserved 0 1 read-only VECTTBL no description available 1 1 read-write 0 no BusFault on vector table read #0 1 BusFault on vector table read #1 RESERVED Reserved 2 1 read-only RESERVED Reserved 3 1 read-only RESERVED Reserved 4 1 read-only RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only RESERVED Reserved 8 1 read-only RESERVED Reserved 9 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 15 1 read-only RESERVED Reserved 16 1 read-only RESERVED Reserved 17 1 read-only RESERVED Reserved 18 1 read-only RESERVED Reserved 19 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 22 1 read-only RESERVED Reserved 23 1 read-only RESERVED Reserved 24 1 read-only RESERVED Reserved 25 1 read-only RESERVED Reserved 26 1 read-only RESERVED Reserved 27 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only FORCED no description available 30 1 read-write 0 no forced HardFault #0 1 forced HardFault #1 DEBUGEVT no description available 31 1 read-write DFSR Debug Fault Status Register 0xD30 32 read-write 0 0xFFFFFFFF HALTED no description available 0 1 read-write 0 No active halt request debug event #0 1 Halt request debug event active #1 BKPT no description available 1 1 read-write 0 No current breakpoint debug event #0 1 At least one current breakpoint debug event #1 DWTTRAP no description available 2 1 read-write 0 No current debug events generated by the DWT #0 1 At least one current debug event generated by the DWT #1 VCATCH no description available 3 1 read-write 0 No Vector catch triggered #0 1 Vector catch triggered #1 EXTERNAL no description available 4 1 read-write 0 No EDBGRQ debug event #0 1 EDBGRQ debug event #1 RESERVED Reserved 5 1 read-write RESERVED Reserved 6 1 read-write RESERVED Reserved 7 1 read-write RESERVED Reserved 8 1 read-write RESERVED Reserved 9 1 read-write RESERVED Reserved 10 1 read-write RESERVED Reserved 11 1 read-write RESERVED Reserved 12 1 read-write RESERVED Reserved 13 1 read-write RESERVED Reserved 14 1 read-write RESERVED Reserved 15 1 read-write RESERVED Reserved 16 1 read-write RESERVED Reserved 17 1 read-write RESERVED Reserved 18 1 read-write RESERVED Reserved 19 1 read-write RESERVED Reserved 20 1 read-write RESERVED Reserved 21 1 read-write RESERVED Reserved 22 1 read-write RESERVED Reserved 23 1 read-write RESERVED Reserved 24 1 read-write RESERVED Reserved 25 1 read-write RESERVED Reserved 26 1 read-write RESERVED Reserved 27 1 read-write RESERVED Reserved 28 1 read-write RESERVED Reserved 29 1 read-write RESERVED Reserved 30 1 read-write RESERVED Reserved 31 1 read-write MMFAR MemManage Address Register 0xD34 32 read-write 0 0xFFFFFFFF ADDRESS Address of MemManage fault location 0 32 read-write BFAR BusFault Address Register 0xD38 32 read-write 0 0xFFFFFFFF ADDRESS Address of the BusFault location 0 32 read-write AFSR Auxiliary Fault Status Register 0xD3C 32 read-write 0 0xFFFFFFFF AUXFAULT Latched version of the AUXFAULT inputs 0 32 read-write SysTick System timer SYST_ 0xE000E010 0 0x10 registers CSR SysTick Control and Status Register 0 32 read-write 0x4 0xFFFFFFFF ENABLE no description available 0 1 read-write 0 counter disabled #0 1 counter enabled #1 TICKINT no description available 1 1 read-write 0 counting down to 0 does not assert the SysTick exception request #0 1 counting down to 0 asserts the SysTick exception request #1 CLKSOURCE no description available 2 1 read-write 0 external clock #0 1 processor clock #1 RESERVED no description available 3 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 5 1 read-only RESERVED no description available 6 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 8 1 read-only RESERVED no description available 9 1 read-only RESERVED no description available 10 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 12 1 read-only RESERVED no description available 13 1 read-only RESERVED no description available 14 1 read-only RESERVED no description available 15 1 read-only COUNTFLAG no description available 16 1 read-write RESERVED no description available 17 1 read-only RESERVED no description available 18 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 20 1 read-only RESERVED no description available 21 1 read-only RESERVED no description available 22 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 24 1 read-only RESERVED no description available 25 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 28 1 read-only RESERVED no description available 29 1 read-only RESERVED no description available 30 1 read-only RESERVED no description available 31 1 read-only RVR SysTick Reload Value Register 0x4 32 read-write 0 0xFFFFFFFF RELOAD Value to load into the SysTick Current Value Register when the counter reaches 0 0 24 read-write RESERVED no description available 24 1 read-only RESERVED no description available 25 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 28 1 read-only RESERVED no description available 29 1 read-only RESERVED no description available 30 1 read-only RESERVED no description available 31 1 read-only CVR SysTick Current Value Register 0x8 32 read-write 0 0xFFFFFFFF CURRENT Current value at the time the register is accessed 0 24 read-write RESERVED no description available 24 1 read-only RESERVED no description available 25 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 28 1 read-only RESERVED no description available 29 1 read-only RESERVED no description available 30 1 read-only RESERVED no description available 31 1 read-only CALIB SysTick Calibration Value Register 0xC 32 read-only 0 0xFFFFFFFF TENMS Reload value to use for 10ms timing 0 24 read-only RESERVED no description available 24 1 read-only RESERVED no description available 25 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 28 1 read-only RESERVED no description available 29 1 read-only SKEW no description available 30 1 read-only 0 10ms calibration value is exact #0 1 10ms calibration value is inexact, because of the clock frequency #1 NOREF no description available 31 1 read-only 0 The reference clock is provided #0 1 The reference clock is not provided #1 NVIC Nested Vectored Interrupt Controller 0xE000E100 0 0xE04 registers NVICISER0 Interrupt Set Enable Register n 0 32 read-write 0 0xFFFFFFFF SETENA Interrupt set enable bits 0 32 read-write NVICISER1 Interrupt Set Enable Register n 0x4 32 read-write 0 0xFFFFFFFF SETENA Interrupt set enable bits 0 32 read-write NVICISER2 Interrupt Set Enable Register n 0x8 32 read-write 0 0xFFFFFFFF SETENA Interrupt set enable bits 0 32 read-write NVICISER3 Interrupt Set Enable Register n 0xC 32 read-write 0 0xFFFFFFFF SETENA Interrupt set enable bits 0 32 read-write NVICICER0 Interrupt Clear Enable Register n 0x80 32 read-write 0 0xFFFFFFFF CLRENA Interrupt clear-enable bits 0 32 read-write NVICICER1 Interrupt Clear Enable Register n 0x84 32 read-write 0 0xFFFFFFFF CLRENA Interrupt clear-enable bits 0 32 read-write NVICICER2 Interrupt Clear Enable Register n 0x88 32 read-write 0 0xFFFFFFFF CLRENA Interrupt clear-enable bits 0 32 read-write NVICICER3 Interrupt Clear Enable Register n 0x8C 32 read-write 0 0xFFFFFFFF CLRENA Interrupt clear-enable bits 0 32 read-write NVICISPR0 Interrupt Set Pending Register n 0x100 32 read-write 0 0xFFFFFFFF SETPEND Interrupt set-pending bits 0 32 read-write NVICISPR1 Interrupt Set Pending Register n 0x104 32 read-write 0 0xFFFFFFFF SETPEND Interrupt set-pending bits 0 32 read-write NVICISPR2 Interrupt Set Pending Register n 0x108 32 read-write 0 0xFFFFFFFF SETPEND Interrupt set-pending bits 0 32 read-write NVICISPR3 Interrupt Set Pending Register n 0x10C 32 read-write 0 0xFFFFFFFF SETPEND Interrupt set-pending bits 0 32 read-write NVICICPR0 Interrupt Clear Pending Register n 0x180 32 read-write 0 0xFFFFFFFF CLRPEND Interrupt clear-pending bits 0 32 read-write NVICICPR1 Interrupt Clear Pending Register n 0x184 32 read-write 0 0xFFFFFFFF CLRPEND Interrupt clear-pending bits 0 32 read-write NVICICPR2 Interrupt Clear Pending Register n 0x188 32 read-write 0 0xFFFFFFFF CLRPEND Interrupt clear-pending bits 0 32 read-write NVICICPR3 Interrupt Clear Pending Register n 0x18C 32 read-write 0 0xFFFFFFFF CLRPEND Interrupt clear-pending bits 0 32 read-write NVICIABR0 Interrupt Active bit Register n 0x200 32 read-write 0 0xFFFFFFFF ACTIVE Interrupt active flags 0 32 read-write NVICIABR1 Interrupt Active bit Register n 0x204 32 read-write 0 0xFFFFFFFF ACTIVE Interrupt active flags 0 32 read-write NVICIABR2 Interrupt Active bit Register n 0x208 32 read-write 0 0xFFFFFFFF ACTIVE Interrupt active flags 0 32 read-write NVICIABR3 Interrupt Active bit Register n 0x20C 32 read-write 0 0xFFFFFFFF ACTIVE Interrupt active flags 0 32 read-write NVICIP0 Interrupt Priority Register n 0x300 8 read-write 0 0xFF PRI0 Priority of interrupt 0 0 8 read-write NVICIP1 Interrupt Priority Register n 0x301 8 read-write 0 0xFF PRI1 Priority of interrupt 1 0 8 read-write NVICIP2 Interrupt Priority Register n 0x302 8 read-write 0 0xFF PRI2 Priority of interrupt 2 0 8 read-write NVICIP3 Interrupt Priority Register n 0x303 8 read-write 0 0xFF PRI3 Priority of interrupt 3 0 8 read-write NVICIP4 Interrupt Priority Register n 0x304 8 read-write 0 0xFF PRI4 Priority of interrupt 4 0 8 read-write NVICIP5 Interrupt Priority Register n 0x305 8 read-write 0 0xFF PRI5 Priority of interrupt 5 0 8 read-write NVICIP6 Interrupt Priority Register n 0x306 8 read-write 0 0xFF PRI6 Priority of interrupt 6 0 8 read-write NVICIP7 Interrupt Priority Register n 0x307 8 read-write 0 0xFF PRI7 Priority of interrupt 7 0 8 read-write NVICIP8 Interrupt Priority Register n 0x308 8 read-write 0 0xFF PRI8 Priority of interrupt 8 0 8 read-write NVICIP9 Interrupt Priority Register n 0x309 8 read-write 0 0xFF PRI9 Priority of interrupt 9 0 8 read-write NVICIP10 Interrupt Priority Register n 0x30A 8 read-write 0 0xFF PRI10 Priority of interrupt 10 0 8 read-write NVICIP11 Interrupt Priority Register n 0x30B 8 read-write 0 0xFF PRI11 Priority of interrupt 11 0 8 read-write NVICIP12 Interrupt Priority Register n 0x30C 8 read-write 0 0xFF PRI12 Priority of interrupt 12 0 8 read-write NVICIP13 Interrupt Priority Register n 0x30D 8 read-write 0 0xFF PRI13 Priority of interrupt 13 0 8 read-write NVICIP14 Interrupt Priority Register n 0x30E 8 read-write 0 0xFF PRI14 Priority of interrupt 14 0 8 read-write NVICIP15 Interrupt Priority Register n 0x30F 8 read-write 0 0xFF PRI15 Priority of interrupt 15 0 8 read-write NVICIP16 Interrupt Priority Register n 0x310 8 read-write 0 0xFF PRI16 Priority of interrupt 16 0 8 read-write NVICIP17 Interrupt Priority Register n 0x311 8 read-write 0 0xFF PRI17 Priority of interrupt 17 0 8 read-write NVICIP18 Interrupt Priority Register n 0x312 8 read-write 0 0xFF PRI18 Priority of interrupt 18 0 8 read-write NVICIP19 Interrupt Priority Register n 0x313 8 read-write 0 0xFF PRI19 Priority of interrupt 19 0 8 read-write NVICIP20 Interrupt Priority Register n 0x314 8 read-write 0 0xFF PRI20 Priority of interrupt 20 0 8 read-write NVICIP21 Interrupt Priority Register n 0x315 8 read-write 0 0xFF PRI21 Priority of interrupt 21 0 8 read-write NVICIP22 Interrupt Priority Register n 0x316 8 read-write 0 0xFF PRI22 Priority of interrupt 22 0 8 read-write NVICIP23 Interrupt Priority Register n 0x317 8 read-write 0 0xFF PRI23 Priority of interrupt 23 0 8 read-write NVICIP24 Interrupt Priority Register n 0x318 8 read-write 0 0xFF PRI24 Priority of interrupt 24 0 8 read-write NVICIP25 Interrupt Priority Register n 0x319 8 read-write 0 0xFF PRI25 Priority of interrupt 25 0 8 read-write NVICIP26 Interrupt Priority Register n 0x31A 8 read-write 0 0xFF PRI26 Priority of interrupt 26 0 8 read-write NVICIP27 Interrupt Priority Register n 0x31B 8 read-write 0 0xFF PRI27 Priority of interrupt 27 0 8 read-write NVICIP28 Interrupt Priority Register n 0x31C 8 read-write 0 0xFF PRI28 Priority of interrupt 28 0 8 read-write NVICIP29 Interrupt Priority Register n 0x31D 8 read-write 0 0xFF PRI29 Priority of interrupt 29 0 8 read-write NVICIP30 Interrupt Priority Register n 0x31E 8 read-write 0 0xFF PRI30 Priority of interrupt 30 0 8 read-write NVICIP31 Interrupt Priority Register n 0x31F 8 read-write 0 0xFF PRI31 Priority of interrupt 31 0 8 read-write NVICIP32 Interrupt Priority Register n 0x320 8 read-write 0 0xFF PRI32 Priority of interrupt 32 0 8 read-write NVICIP33 Interrupt Priority Register n 0x321 8 read-write 0 0xFF PRI33 Priority of interrupt 33 0 8 read-write NVICIP34 Interrupt Priority Register n 0x322 8 read-write 0 0xFF PRI34 Priority of interrupt 34 0 8 read-write NVICIP35 Interrupt Priority Register n 0x323 8 read-write 0 0xFF PRI35 Priority of interrupt 35 0 8 read-write NVICIP36 Interrupt Priority Register n 0x324 8 read-write 0 0xFF PRI36 Priority of interrupt 36 0 8 read-write NVICIP37 Interrupt Priority Register n 0x325 8 read-write 0 0xFF PRI37 Priority of interrupt 37 0 8 read-write NVICIP38 Interrupt Priority Register n 0x326 8 read-write 0 0xFF PRI38 Priority of interrupt 38 0 8 read-write NVICIP39 Interrupt Priority Register n 0x327 8 read-write 0 0xFF PRI39 Priority of interrupt 39 0 8 read-write NVICIP40 Interrupt Priority Register n 0x328 8 read-write 0 0xFF PRI40 Priority of interrupt 40 0 8 read-write NVICIP41 Interrupt Priority Register n 0x329 8 read-write 0 0xFF PRI41 Priority of interrupt 41 0 8 read-write NVICIP42 Interrupt Priority Register n 0x32A 8 read-write 0 0xFF PRI42 Priority of interrupt 42 0 8 read-write NVICIP43 Interrupt Priority Register n 0x32B 8 read-write 0 0xFF PRI43 Priority of interrupt 43 0 8 read-write NVICIP44 Interrupt Priority Register n 0x32C 8 read-write 0 0xFF PRI44 Priority of interrupt 44 0 8 read-write NVICIP45 Interrupt Priority Register n 0x32D 8 read-write 0 0xFF PRI45 Priority of interrupt 45 0 8 read-write NVICIP46 Interrupt Priority Register n 0x32E 8 read-write 0 0xFF PRI46 Priority of interrupt 46 0 8 read-write NVICIP47 Interrupt Priority Register n 0x32F 8 read-write 0 0xFF PRI47 Priority of interrupt 47 0 8 read-write NVICIP48 Interrupt Priority Register n 0x330 8 read-write 0 0xFF PRI48 Priority of interrupt 48 0 8 read-write NVICIP49 Interrupt Priority Register n 0x331 8 read-write 0 0xFF PRI49 Priority of interrupt 49 0 8 read-write NVICIP50 Interrupt Priority Register n 0x332 8 read-write 0 0xFF PRI50 Priority of interrupt 50 0 8 read-write NVICIP51 Interrupt Priority Register n 0x333 8 read-write 0 0xFF PRI51 Priority of interrupt 51 0 8 read-write NVICIP52 Interrupt Priority Register n 0x334 8 read-write 0 0xFF PRI52 Priority of interrupt 52 0 8 read-write NVICIP53 Interrupt Priority Register n 0x335 8 read-write 0 0xFF PRI53 Priority of interrupt 53 0 8 read-write NVICIP54 Interrupt Priority Register n 0x336 8 read-write 0 0xFF PRI54 Priority of interrupt 54 0 8 read-write NVICIP55 Interrupt Priority Register n 0x337 8 read-write 0 0xFF PRI55 Priority of interrupt 55 0 8 read-write NVICIP56 Interrupt Priority Register n 0x338 8 read-write 0 0xFF PRI56 Priority of interrupt 56 0 8 read-write NVICIP57 Interrupt Priority Register n 0x339 8 read-write 0 0xFF PRI57 Priority of interrupt 57 0 8 read-write NVICIP58 Interrupt Priority Register n 0x33A 8 read-write 0 0xFF PRI58 Priority of interrupt 58 0 8 read-write NVICIP59 Interrupt Priority Register n 0x33B 8 read-write 0 0xFF PRI59 Priority of interrupt 59 0 8 read-write NVICIP60 Interrupt Priority Register n 0x33C 8 read-write 0 0xFF PRI60 Priority of interrupt 60 0 8 read-write NVICIP61 Interrupt Priority Register n 0x33D 8 read-write 0 0xFF PRI61 Priority of interrupt 61 0 8 read-write NVICIP62 Interrupt Priority Register n 0x33E 8 read-write 0 0xFF PRI62 Priority of interrupt 62 0 8 read-write NVICIP63 Interrupt Priority Register n 0x33F 8 read-write 0 0xFF PRI63 Priority of interrupt 63 0 8 read-write NVICIP64 Interrupt Priority Register n 0x340 8 read-write 0 0xFF PRI64 Priority of interrupt 64 0 8 read-write NVICIP65 Interrupt Priority Register n 0x341 8 read-write 0 0xFF PRI65 Priority of interrupt 65 0 8 read-write NVICIP66 Interrupt Priority Register n 0x342 8 read-write 0 0xFF PRI66 Priority of interrupt 66 0 8 read-write NVICIP67 Interrupt Priority Register n 0x343 8 read-write 0 0xFF PRI67 Priority of interrupt 67 0 8 read-write NVICIP68 Interrupt Priority Register n 0x344 8 read-write 0 0xFF PRI68 Priority of interrupt 68 0 8 read-write NVICIP69 Interrupt Priority Register n 0x345 8 read-write 0 0xFF PRI69 Priority of interrupt 69 0 8 read-write NVICIP70 Interrupt Priority Register n 0x346 8 read-write 0 0xFF PRI70 Priority of interrupt 70 0 8 read-write NVICIP71 Interrupt Priority Register n 0x347 8 read-write 0 0xFF PRI71 Priority of interrupt 71 0 8 read-write NVICIP72 Interrupt Priority Register n 0x348 8 read-write 0 0xFF PRI72 Priority of interrupt 72 0 8 read-write NVICIP73 Interrupt Priority Register n 0x349 8 read-write 0 0xFF PRI73 Priority of interrupt 73 0 8 read-write NVICIP74 Interrupt Priority Register n 0x34A 8 read-write 0 0xFF PRI74 Priority of interrupt 74 0 8 read-write NVICIP75 Interrupt Priority Register n 0x34B 8 read-write 0 0xFF PRI75 Priority of interrupt 75 0 8 read-write NVICIP76 Interrupt Priority Register n 0x34C 8 read-write 0 0xFF PRI76 Priority of interrupt 76 0 8 read-write NVICIP77 Interrupt Priority Register n 0x34D 8 read-write 0 0xFF PRI77 Priority of interrupt 77 0 8 read-write NVICIP78 Interrupt Priority Register n 0x34E 8 read-write 0 0xFF PRI78 Priority of interrupt 78 0 8 read-write NVICIP79 Interrupt Priority Register n 0x34F 8 read-write 0 0xFF PRI79 Priority of interrupt 79 0 8 read-write NVICIP80 Interrupt Priority Register n 0x350 8 read-write 0 0xFF PRI80 Priority of interrupt 80 0 8 read-write NVICIP81 Interrupt Priority Register n 0x351 8 read-write 0 0xFF PRI81 Priority of interrupt 81 0 8 read-write NVICIP82 Interrupt Priority Register n 0x352 8 read-write 0 0xFF PRI82 Priority of interrupt 82 0 8 read-write NVICIP83 Interrupt Priority Register n 0x353 8 read-write 0 0xFF PRI83 Priority of interrupt 83 0 8 read-write NVICIP84 Interrupt Priority Register n 0x354 8 read-write 0 0xFF PRI84 Priority of interrupt 84 0 8 read-write NVICIP85 Interrupt Priority Register n 0x355 8 read-write 0 0xFF PRI85 Priority of interrupt 85 0 8 read-write NVICIP86 Interrupt Priority Register n 0x356 8 read-write 0 0xFF PRI86 Priority of interrupt 86 0 8 read-write NVICIP87 Interrupt Priority Register n 0x357 8 read-write 0 0xFF PRI87 Priority of interrupt 87 0 8 read-write NVICIP88 Interrupt Priority Register n 0x358 8 read-write 0 0xFF PRI88 Priority of interrupt 88 0 8 read-write NVICIP89 Interrupt Priority Register n 0x359 8 read-write 0 0xFF PRI89 Priority of interrupt 89 0 8 read-write NVICIP90 Interrupt Priority Register n 0x35A 8 read-write 0 0xFF PRI90 Priority of interrupt 90 0 8 read-write NVICIP91 Interrupt Priority Register n 0x35B 8 read-write 0 0xFF PRI91 Priority of interrupt 91 0 8 read-write NVICIP92 Interrupt Priority Register n 0x35C 8 read-write 0 0xFF PRI92 Priority of interrupt 92 0 8 read-write NVICIP93 Interrupt Priority Register n 0x35D 8 read-write 0 0xFF PRI93 Priority of interrupt 93 0 8 read-write NVICIP94 Interrupt Priority Register n 0x35E 8 read-write 0 0xFF PRI94 Priority of interrupt 94 0 8 read-write NVICIP95 Interrupt Priority Register n 0x35F 8 read-write 0 0xFF PRI95 Priority of interrupt 95 0 8 read-write NVICIP96 Interrupt Priority Register n 0x360 8 read-write 0 0xFF PRI96 Priority of interrupt 96 0 8 read-write NVICIP97 Interrupt Priority Register n 0x361 8 read-write 0 0xFF PRI97 Priority of interrupt 97 0 8 read-write NVICIP98 Interrupt Priority Register n 0x362 8 read-write 0 0xFF PRI98 Priority of interrupt 98 0 8 read-write NVICIP99 Interrupt Priority Register n 0x363 8 read-write 0 0xFF PRI99 Priority of interrupt 99 0 8 read-write NVICIP100 Interrupt Priority Register n 0x364 8 read-write 0 0xFF PRI100 Priority of interrupt 100 0 8 read-write NVICIP101 Interrupt Priority Register n 0x365 8 read-write 0 0xFF PRI101 Priority of interrupt 101 0 8 read-write NVICIP102 Interrupt Priority Register n 0x366 8 read-write 0 0xFF PRI102 Priority of interrupt 102 0 8 read-write NVICIP103 Interrupt Priority Register n 0x367 8 read-write 0 0xFF PRI103 Priority of interrupt 103 0 8 read-write NVICIP104 Interrupt Priority Register n 0x368 8 read-write 0 0xFF PRI104 Priority of interrupt 104 0 8 read-write NVICIP105 Interrupt Priority Register n 0x369 8 read-write 0 0xFF PRI105 Priority of interrupt 105 0 8 read-write NVICSTIR Software Trigger Interrupt Register 0xE00 32 read-write 0 0xFFFFFFFF INTID Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3. 0 9 read-write RESERVED no description available 9 1 read-write RESERVED no description available 10 1 read-write RESERVED no description available 11 1 read-write RESERVED no description available 12 1 read-write RESERVED no description available 13 1 read-write RESERVED no description available 14 1 read-write RESERVED no description available 15 1 read-write RESERVED no description available 16 1 read-write RESERVED no description available 17 1 read-write RESERVED no description available 18 1 read-write RESERVED no description available 19 1 read-write RESERVED no description available 20 1 read-write RESERVED no description available 21 1 read-write RESERVED no description available 22 1 read-write RESERVED no description available 23 1 read-write RESERVED no description available 24 1 read-write RESERVED no description available 25 1 read-write RESERVED no description available 26 1 read-write RESERVED no description available 27 1 read-write RESERVED no description available 28 1 read-write RESERVED no description available 29 1 read-write RESERVED no description available 30 1 read-write RESERVED no description available 31 1 read-write MCM Core Platform Miscellaneous Control Module MCM_ 0xE0080000 0x8 0x2C registers PLASC Crossbar Switch (AXBS) Slave Configuration 0x8 16 read-only 0x1B 0xFFFF ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0 8 read-only 0 A bus slave connection to AXBS input port n is absent #0 1 A bus slave connection to AXBS input port n is present #1 RESERVED no description available 8 8 read-only PLAMC Crossbar Switch (AXBS) Master Configuration 0xA 16 read-only 0x7 0xFFFF AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 8 read-only 0 A bus master connection to AXBS input port n is absent #0 1 A bus master connection to AXBS input port n is present #1 RESERVED no description available 8 8 read-only CR Control Register 0xC 32 read-write 0 0xFFFFFFFF RESERVED no description available 0 9 read-only CBRR Crossbar round-robin arbitration enable 9 1 read-only 0 Fixed-priority arbitration #0 1 Round-robin arbitration #1 RESERVED no description available 10 14 read-only SRAMUAP SRAM_U arbitration priority 24 2 read-write 00 Round robin #00 01 Special round robin (favors SRAM backoor accesses over the processor) #01 10 Fixed priority. Processor has highest, backdoor has lowest #10 11 Fixed priority. Backdoor has highest, processor has lowest #11 SRAMUWP SRAM_U write protect 26 1 read-write RESERVED no description available 27 1 read-only SRAMLAP SRAM_L arbitration priority 28 2 read-write 00 Round robin #00 01 Special round robin (favors SRAM backoor accesses over the processor) #01 10 Fixed priority. Processor has highest, backdoor has lowest #10 11 Fixed priority. Backdoor has highest, processor has lowest #11 SRAMLWP SRAM_L Write Protect 30 1 read-write RESERVED no description available 31 1 read-only PID Process ID register 0x30 32 read-write 0 0xFFFFFFFF PID M0_PID And M1_PID For MPU 0 8 read-write RESERVED no description available 8 24 read-only