Freescale Semiconductor, Inc. Freescale Kinetis_K MK81F25615 1.6 MK81F25615 Freescale Microcontroller Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. 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CM4 r0p1 little false true false true 4 false 8 32 FTFA_FlashConfig Flash configuration field NV_ 0x400 0 0xE registers BACKKEY3 Backdoor Comparison Key 3. 0 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY2 Backdoor Comparison Key 2. 0x1 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY1 Backdoor Comparison Key 1. 0x2 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY0 Backdoor Comparison Key 0. 0x3 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY7 Backdoor Comparison Key 7. 0x4 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY6 Backdoor Comparison Key 6. 0x5 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY5 Backdoor Comparison Key 5. 0x6 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY4 Backdoor Comparison Key 4. 0x7 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only FPROT3 Non-volatile P-Flash Protection 1 - Low Register 0x8 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FPROT2 Non-volatile P-Flash Protection 1 - High Register 0x9 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FPROT1 Non-volatile P-Flash Protection 0 - Low Register 0xA 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FPROT0 Non-volatile P-Flash Protection 0 - High Register 0xB 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FSEC Non-volatile Flash Security Register 0xC 8 read-only 0xFF 0xFF SEC Flash Security 0 2 read-only 10 MCU security status is unsecure #10 11 MCU security status is secure #11 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 10 Freescale factory access denied #10 11 Freescale factory access granted #11 MEEN no description available 4 2 read-only 10 Mass erase is disabled #10 11 Mass erase is enabled #11 KEYEN Backdoor Key Security Enable 6 2 read-only 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 FOPT Non-volatile Flash Option Register 0xD 8 read-only 0x3D 0xFF LPBOOT no description available 0 1 read-only 00 Low-power boot #0 01 Normal boot #1 BOOTPIN_OPT no description available 1 1 read-only 00 Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin #0 01 Boot source configured by FOPT (BOOTSRC_SEL) bits #1 NMI_DIS no description available 2 1 read-only 00 NMI interrupts are always blocked #0 01 NMI_b pin/interrupts reset default to enabled #1 FAST_INIT no description available 5 1 read-only 00 Slower initialization #0 01 Fast Initialization #1 BOOTSRC_SEL Boot source selection 6 2 read-only 00 Boot from Flash #00 10 Boot from ROM, configure QSPI0, and enter boot loader mode. #10 11 Boot from ROM and enter boot loader mode. #11 AIPS0 AIPS-Lite Bridge AIPS AIPS0_ 0x40000000 0 0x70 registers MPRA Master Privilege Register A 0 32 read-write 0x77700000 0xFFFFFFFF MPL4 Master 4 Privilege Level 12 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTW4 Master 4 Trusted For Writes 13 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTR4 Master 4 Trusted For Read 14 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MPL3 Master 3 Privilege Level 16 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTW3 Master 3 Trusted For Writes 17 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTR3 Master 3 Trusted For Read 18 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MPL2 Master 2 Privilege Level 20 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTW2 Master 2 Trusted For Writes 21 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTR2 Master 2 Trusted For Read 22 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MPL1 Master 1 Privilege Level 24 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTW1 Master 1 Trusted for Writes 25 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTR1 Master 1 Trusted for Read 26 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MPL0 Master 0 Privilege Level 28 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTW0 Master 0 Trusted For Writes 29 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTR0 Master 0 Trusted For Read 30 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 PACRA Peripheral Access Control Register 0x20 32 read-write 0x40004000 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRB Peripheral Access Control Register 0x24 32 read-write 0x44004404 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRC Peripheral Access Control Register 0x28 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRD Peripheral Access Control Register 0x2C 32 read-write 0x4 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRE Peripheral Access Control Register 0x40 32 read-write 0x44000000 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRF Peripheral Access Control Register 0x44 32 read-write 0x4404 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRG Peripheral Access Control Register 0x48 32 read-write 0x400444 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRH Peripheral Access Control Register 0x4C 32 read-write 0x44440444 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRI Peripheral Access Control Register 0x50 32 read-write 0x44004404 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRJ Peripheral Access Control Register 0x54 32 read-write 0x44444400 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRK Peripheral Access Control Register 0x58 32 read-write 0x400000 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRL Peripheral Access Control Register 0x5C 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRM Peripheral Access Control Register 0x60 32 read-write 0x4404444 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRN Peripheral Access Control Register 0x64 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRO Peripheral Access Control Register 0x68 32 read-write 0x444000 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRP Peripheral Access Control Register 0x6C 32 read-write 0x44444444 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 AIPS1 AIPS-Lite Bridge AIPS AIPS1_ 0x40080000 0 0x70 registers MPRA Master Privilege Register A 0 32 read-write 0x77700000 0xFFFFFFFF MPL4 Master 4 Privilege Level 12 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTW4 Master 4 Trusted For Writes 13 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTR4 Master 4 Trusted For Read 14 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MPL3 Master 3 Privilege Level 16 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTW3 Master 3 Trusted For Writes 17 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTR3 Master 3 Trusted For Read 18 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MPL2 Master 2 Privilege Level 20 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTW2 Master 2 Trusted For Writes 21 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTR2 Master 2 Trusted For Read 22 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MPL1 Master 1 Privilege Level 24 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTW1 Master 1 Trusted for Writes 25 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTR1 Master 1 Trusted for Read 26 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MPL0 Master 0 Privilege Level 28 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTW0 Master 0 Trusted For Writes 29 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTR0 Master 0 Trusted For Read 30 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 PACRA Peripheral Access Control Register 0x20 32 read-write 0x40000000 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRB Peripheral Access Control Register 0x24 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRC Peripheral Access Control Register 0x28 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRD Peripheral Access Control Register 0x2C 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRE Peripheral Access Control Register 0x40 32 read-write 0x40000000 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRF Peripheral Access Control Register 0x44 32 read-write 0x4000 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRG Peripheral Access Control Register 0x48 32 read-write 0x4000000 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRH Peripheral Access Control Register 0x4C 32 read-write 0x44000000 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRI Peripheral Access Control Register 0x50 32 read-write 0x4444 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRJ Peripheral Access Control Register 0x54 32 read-write 0x4404000 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRK Peripheral Access Control Register 0x58 32 read-write 0x4440 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRL Peripheral Access Control Register 0x5C 32 read-write 0x400004 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRM Peripheral Access Control Register 0x60 32 read-write 0x44 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRN Peripheral Access Control Register 0x64 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRO Peripheral Access Control Register 0x68 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRP Peripheral Access Control Register 0x6C 32 read-write 0 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 AXBS Crossbar switch AXBS_ 0x40004000 0 0xC04 registers 6 0x100 0,1,2,3,4,5 PRS%s Priority Registers Slave 0 32 read-write 0x43210 0xFFFFFFFF M0 Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M1 Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M2 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M3 Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M4 Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. 16 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 6 0x100 0,1,2,3,4,5 CRS%s Control Register 0x10 32 read-write 0 0xFFFFFFFF PARK Park 0 3 read-write 000 Park on master port M0 #000 001 Park on master port M1 #001 010 Park on master port M2 #010 011 Park on master port M3 #011 100 Park on master port M4 #100 101 Park on master port M5 #101 110 Park on master port M6 #110 111 Park on master port M7 #111 PCTL Parking Control 4 2 read-write 00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field #00 01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port #01 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state #10 ARB Arbitration Mode 8 2 read-write 00 Fixed priority #00 01 Round-robin, or rotating, priority #01 HLP Halt Low Priority 30 1 read-write 0 The low power mode request has the highest priority for arbitration on this slave port #0 1 The low power mode request has the lowest initial priority for arbitration on this slave port #1 RO Read Only 31 1 read-write 0 The slave port's registers are writeable #0 1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. #1 5 0x100 0,1,2,3,4 MGPCR%s Master General Purpose Control Register 0x800 32 read-write 0 0xFFFFFFFF AULB Arbitrates On Undefined Length Bursts 0 3 read-write 000 No arbitration is allowed during an undefined length burst #000 001 Arbitration is allowed at any time during an undefined length burst #001 010 Arbitration is allowed after four beats of an undefined length burst #010 011 Arbitration is allowed after eight beats of an undefined length burst #011 100 Arbitration is allowed after 16 beats of an undefined length burst #100 DMA Enhanced direct memory access controller DMA_ 0x40008000 0 0x1400 registers DMA0_DMA16 0 DMA1_DMA17 1 DMA2_DMA18 2 DMA3_DMA19 3 DMA4_DMA20 4 DMA5_DMA21 5 DMA6_DMA22 6 DMA7_DMA23 7 DMA8_DMA24 8 DMA9_DMA25 9 DMA10_DMA26 10 DMA11_DMA27 11 DMA12_DMA28 12 DMA13_DMA29 13 DMA14_DMA30 14 DMA15_DMA31 15 DMA_Error 16 CR Control Register 0 32 read-write 0x400 0xFFFFFFFF EDBG Enable Debug 1 1 read-write 0 When in debug mode, the DMA continues to operate. #0 1 When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. #1 ERCA Enable Round Robin Channel Arbitration 2 1 read-write 0 Fixed priority arbitration is used for channel selection within each group. #0 1 Round robin arbitration is used for channel selection within each group. #1 ERGA Enable Round Robin Group Arbitration 3 1 read-write 0 Fixed priority arbitration is used for selection among the groups. #0 1 Round robin arbitration is used for selection among the groups. #1 HOE Halt On Error 4 1 read-write 0 Normal operation #0 1 Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. #1 HALT Halt DMA Operations 5 1 read-write 0 Normal operation #0 1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. #1 CLM Continuous Link Mode 6 1 read-write 0 A minor loop channel link made to itself goes through channel arbitration before being activated again. #0 1 A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. #1 EMLM Enable Minor Loop Mapping 7 1 read-write 0 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. #0 1 Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. #1 GRP0PRI Channel Group 0 Priority 8 1 read-write GRP1PRI Channel Group 1 Priority 10 1 read-write ECX Error Cancel Transfer 16 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. #1 CX Cancel Transfer 17 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. #1 ES Error Status Register 0x4 32 read-only 0 0xFFFFFFFF DBE Destination Bus Error 0 1 read-only 0 No destination bus error #0 1 The last recorded error was a bus error on a destination write #1 SBE Source Bus Error 1 1 read-only 0 No source bus error #0 1 The last recorded error was a bus error on a source read #1 SGE Scatter/Gather Configuration Error 2 1 read-only 0 No scatter/gather configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. #1 NCE NBYTES/CITER Configuration Error 3 1 read-only 0 No NBYTES/CITER configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] #1 DOE Destination Offset Error 4 1 read-only 0 No destination offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. #1 DAE Destination Address Error 5 1 read-only 0 No destination address configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. #1 SOE Source Offset Error 6 1 read-only 0 No source offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. #1 SAE Source Address Error 7 1 read-only 0 No source address configuration error. #0 1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. #1 ERRCHN Error Channel Number or Canceled Channel Number 8 5 read-only CPE Channel Priority Error 14 1 read-only 0 No channel priority error #0 1 The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique. #1 GPE Group Priority Error 15 1 read-only 0 No group priority error #0 1 The last recorded error was a configuration error among the group priorities. All group priorities are not unique. #1 ECX Transfer Canceled 16 1 read-only 0 No canceled transfers #0 1 The last recorded entry was a canceled transfer by the error cancel transfer input #1 VLD Logical OR of all ERR status bits 31 1 read-only 0 No ERR bits are set. #0 1 At least one ERR bit is set indicating a valid error exists that has not been cleared. #1 ERQ Enable Request Register 0xC 32 read-write 0 0xFFFFFFFF ERQ0 Enable DMA Request 0 0 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ1 Enable DMA Request 1 1 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ2 Enable DMA Request 2 2 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ3 Enable DMA Request 3 3 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ4 Enable DMA Request 4 4 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ5 Enable DMA Request 5 5 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ6 Enable DMA Request 6 6 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ7 Enable DMA Request 7 7 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ8 Enable DMA Request 8 8 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ9 Enable DMA Request 9 9 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ10 Enable DMA Request 10 10 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ11 Enable DMA Request 11 11 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ12 Enable DMA Request 12 12 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ13 Enable DMA Request 13 13 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ14 Enable DMA Request 14 14 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ15 Enable DMA Request 15 15 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ16 Enable DMA Request 16 16 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ17 Enable DMA Request 17 17 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ18 Enable DMA Request 18 18 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ19 Enable DMA Request 19 19 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ20 Enable DMA Request 20 20 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ21 Enable DMA Request 21 21 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ22 Enable DMA Request 22 22 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ23 Enable DMA Request 23 23 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ24 Enable DMA Request 24 24 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ25 Enable DMA Request 25 25 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ26 Enable DMA Request 26 26 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ27 Enable DMA Request 27 27 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ28 Enable DMA Request 28 28 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ29 Enable DMA Request 29 29 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ30 Enable DMA Request 30 30 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ31 Enable DMA Request 31 31 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 EEI Enable Error Interrupt Register 0x14 32 read-write 0 0xFFFFFFFF EEI0 Enable Error Interrupt 0 0 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI1 Enable Error Interrupt 1 1 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI2 Enable Error Interrupt 2 2 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI3 Enable Error Interrupt 3 3 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI4 Enable Error Interrupt 4 4 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI5 Enable Error Interrupt 5 5 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI6 Enable Error Interrupt 6 6 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI7 Enable Error Interrupt 7 7 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI8 Enable Error Interrupt 8 8 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI9 Enable Error Interrupt 9 9 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI10 Enable Error Interrupt 10 10 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI11 Enable Error Interrupt 11 11 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI12 Enable Error Interrupt 12 12 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI13 Enable Error Interrupt 13 13 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI14 Enable Error Interrupt 14 14 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI15 Enable Error Interrupt 15 15 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI16 Enable Error Interrupt 16 16 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI17 Enable Error Interrupt 17 17 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI18 Enable Error Interrupt 18 18 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI19 Enable Error Interrupt 19 19 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI20 Enable Error Interrupt 20 20 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI21 Enable Error Interrupt 21 21 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI22 Enable Error Interrupt 22 22 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI23 Enable Error Interrupt 23 23 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI24 Enable Error Interrupt 24 24 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI25 Enable Error Interrupt 25 25 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI26 Enable Error Interrupt 26 26 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI27 Enable Error Interrupt 27 27 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI28 Enable Error Interrupt 28 28 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI29 Enable Error Interrupt 29 29 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI30 Enable Error Interrupt 30 30 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI31 Enable Error Interrupt 31 31 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 CEEI Clear Enable Error Interrupt Register 0x18 8 write-only 0 0xFF CEEI Clear Enable Error Interrupt 0 5 write-only CAEE Clear All Enable Error Interrupts 6 1 write-only 0 Clear only the EEI bit specified in the CEEI field #0 1 Clear all bits in EEI #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SEEI Set Enable Error Interrupt Register 0x19 8 write-only 0 0xFF SEEI Set Enable Error Interrupt 0 5 write-only SAEE Sets All Enable Error Interrupts 6 1 write-only 0 Set only the EEI bit specified in the SEEI field. #0 1 Sets all bits in EEI #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERQ Clear Enable Request Register 0x1A 8 write-only 0 0xFF CERQ Clear Enable Request 0 5 write-only CAER Clear All Enable Requests 6 1 write-only 0 Clear only the ERQ bit specified in the CERQ field #0 1 Clear all bits in ERQ #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SERQ Set Enable Request Register 0x1B 8 write-only 0 0xFF SERQ Set Enable Request 0 5 write-only SAER Set All Enable Requests 6 1 write-only 0 Set only the ERQ bit specified in the SERQ field #0 1 Set all bits in ERQ #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CDNE Clear DONE Status Bit Register 0x1C 8 write-only 0 0xFF CDNE Clear DONE Bit 0 5 write-only CADN Clears All DONE Bits 6 1 write-only 0 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field #0 1 Clears all bits in TCDn_CSR[DONE] #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SSRT Set START Bit Register 0x1D 8 write-only 0 0xFF SSRT Set START Bit 0 5 write-only SAST Set All START Bits (activates all channels) 6 1 write-only 0 Set only the TCDn_CSR[START] bit specified in the SSRT field #0 1 Set all bits in TCDn_CSR[START] #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERR Clear Error Register 0x1E 8 write-only 0 0xFF CERR Clear Error Indicator 0 5 write-only CAEI Clear All Error Indicators 6 1 write-only 0 Clear only the ERR bit specified in the CERR field #0 1 Clear all bits in ERR #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CINT Clear Interrupt Request Register 0x1F 8 write-only 0 0xFF CINT Clear Interrupt Request 0 5 write-only CAIR Clear All Interrupt Requests 6 1 write-only 0 Clear only the INT bit specified in the CINT field #0 1 Clear all bits in INT #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 INT Interrupt Request Register 0x24 32 read-write 0 0xFFFFFFFF INT0 Interrupt Request 0 0 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT1 Interrupt Request 1 1 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT2 Interrupt Request 2 2 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT3 Interrupt Request 3 3 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT4 Interrupt Request 4 4 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT5 Interrupt Request 5 5 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT6 Interrupt Request 6 6 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT7 Interrupt Request 7 7 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT8 Interrupt Request 8 8 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT9 Interrupt Request 9 9 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT10 Interrupt Request 10 10 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT11 Interrupt Request 11 11 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT12 Interrupt Request 12 12 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT13 Interrupt Request 13 13 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT14 Interrupt Request 14 14 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT15 Interrupt Request 15 15 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT16 Interrupt Request 16 16 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT17 Interrupt Request 17 17 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT18 Interrupt Request 18 18 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT19 Interrupt Request 19 19 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT20 Interrupt Request 20 20 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT21 Interrupt Request 21 21 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT22 Interrupt Request 22 22 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT23 Interrupt Request 23 23 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT24 Interrupt Request 24 24 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT25 Interrupt Request 25 25 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT26 Interrupt Request 26 26 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT27 Interrupt Request 27 27 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT28 Interrupt Request 28 28 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT29 Interrupt Request 29 29 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT30 Interrupt Request 30 30 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT31 Interrupt Request 31 31 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 ERR Error Register 0x2C 32 read-write 0 0xFFFFFFFF ERR0 Error In Channel 0 0 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR1 Error In Channel 1 1 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR2 Error In Channel 2 2 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR3 Error In Channel 3 3 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR4 Error In Channel 4 4 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR5 Error In Channel 5 5 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR6 Error In Channel 6 6 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR7 Error In Channel 7 7 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR8 Error In Channel 8 8 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR9 Error In Channel 9 9 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR10 Error In Channel 10 10 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR11 Error In Channel 11 11 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR12 Error In Channel 12 12 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR13 Error In Channel 13 13 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR14 Error In Channel 14 14 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR15 Error In Channel 15 15 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR16 Error In Channel 16 16 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR17 Error In Channel 17 17 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR18 Error In Channel 18 18 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR19 Error In Channel 19 19 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR20 Error In Channel 20 20 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR21 Error In Channel 21 21 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR22 Error In Channel 22 22 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR23 Error In Channel 23 23 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR24 Error In Channel 24 24 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR25 Error In Channel 25 25 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR26 Error In Channel 26 26 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR27 Error In Channel 27 27 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR28 Error In Channel 28 28 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR29 Error In Channel 29 29 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR30 Error In Channel 30 30 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR31 Error In Channel 31 31 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 HRS Hardware Request Status Register 0x34 32 read-only 0 0xFFFFFFFF HRS0 Hardware Request Status Channel 0 0 1 read-only 0 A hardware service request for channel 0 is not present #0 1 A hardware service request for channel 0 is present #1 HRS1 Hardware Request Status Channel 1 1 1 read-only 0 A hardware service request for channel 1 is not present #0 1 A hardware service request for channel 1 is present #1 HRS2 Hardware Request Status Channel 2 2 1 read-only 0 A hardware service request for channel 2 is not present #0 1 A hardware service request for channel 2 is present #1 HRS3 Hardware Request Status Channel 3 3 1 read-only 0 A hardware service request for channel 3 is not present #0 1 A hardware service request for channel 3 is present #1 HRS4 Hardware Request Status Channel 4 4 1 read-only 0 A hardware service request for channel 4 is not present #0 1 A hardware service request for channel 4 is present #1 HRS5 Hardware Request Status Channel 5 5 1 read-only 0 A hardware service request for channel 5 is not present #0 1 A hardware service request for channel 5 is present #1 HRS6 Hardware Request Status Channel 6 6 1 read-only 0 A hardware service request for channel 6 is not present #0 1 A hardware service request for channel 6 is present #1 HRS7 Hardware Request Status Channel 7 7 1 read-only 0 A hardware service request for channel 7 is not present #0 1 A hardware service request for channel 7 is present #1 HRS8 Hardware Request Status Channel 8 8 1 read-only 0 A hardware service request for channel 8 is not present #0 1 A hardware service request for channel 8 is present #1 HRS9 Hardware Request Status Channel 9 9 1 read-only 0 A hardware service request for channel 9 is not present #0 1 A hardware service request for channel 9 is present #1 HRS10 Hardware Request Status Channel 10 10 1 read-only 0 A hardware service request for channel 10 is not present #0 1 A hardware service request for channel 10 is present #1 HRS11 Hardware Request Status Channel 11 11 1 read-only 0 A hardware service request for channel 11 is not present #0 1 A hardware service request for channel 11 is present #1 HRS12 Hardware Request Status Channel 12 12 1 read-only 0 A hardware service request for channel 12 is not present #0 1 A hardware service request for channel 12 is present #1 HRS13 Hardware Request Status Channel 13 13 1 read-only 0 A hardware service request for channel 13 is not present #0 1 A hardware service request for channel 13 is present #1 HRS14 Hardware Request Status Channel 14 14 1 read-only 0 A hardware service request for channel 14 is not present #0 1 A hardware service request for channel 14 is present #1 HRS15 Hardware Request Status Channel 15 15 1 read-only 0 A hardware service request for channel 15 is not present #0 1 A hardware service request for channel 15 is present #1 HRS16 Hardware Request Status Channel 16 16 1 read-only 0 A hardware service request for channel 16 is not present #0 1 A hardware service request for channel 16 is present #1 HRS17 Hardware Request Status Channel 17 17 1 read-only 0 A hardware service request for channel 17 is not present #0 1 A hardware service request for channel 17 is present #1 HRS18 Hardware Request Status Channel 18 18 1 read-only 0 A hardware service request for channel 18 is not present #0 1 A hardware service request for channel 18 is present #1 HRS19 Hardware Request Status Channel 19 19 1 read-only 0 A hardware service request for channel 19 is not present #0 1 A hardware service request for channel 19 is present #1 HRS20 Hardware Request Status Channel 20 20 1 read-only 0 A hardware service request for channel 20 is not present #0 1 A hardware service request for channel 20 is present #1 HRS21 Hardware Request Status Channel 21 21 1 read-only 0 A hardware service request for channel 21 is not present #0 1 A hardware service request for channel 21 is present #1 HRS22 Hardware Request Status Channel 22 22 1 read-only 0 A hardware service request for channel 22 is not present #0 1 A hardware service request for channel 22 is present #1 HRS23 Hardware Request Status Channel 23 23 1 read-only 0 A hardware service request for channel 23 is not present #0 1 A hardware service request for channel 23 is present #1 HRS24 Hardware Request Status Channel 24 24 1 read-only 0 A hardware service request for channel 24 is not present #0 1 A hardware service request for channel 24 is present #1 HRS25 Hardware Request Status Channel 25 25 1 read-only 0 A hardware service request for channel 25 is not present #0 1 A hardware service request for channel 25 is present #1 HRS26 Hardware Request Status Channel 26 26 1 read-only 0 A hardware service request for channel 26 is not present #0 1 A hardware service request for channel 26 is present #1 HRS27 Hardware Request Status Channel 27 27 1 read-only 0 A hardware service request for channel 27 is not present #0 1 A hardware service request for channel 27 is present #1 HRS28 Hardware Request Status Channel 28 28 1 read-only 0 A hardware service request for channel 28 is not present #0 1 A hardware service request for channel 28 is present #1 HRS29 Hardware Request Status Channel 29 29 1 read-only 0 A hardware service request for channel 29 is not preset #0 1 A hardware service request for channel 29 is present #1 HRS30 Hardware Request Status Channel 30 30 1 read-only 0 A hardware service request for channel 30 is not present #0 1 A hardware service request for for channel 30 is present #1 HRS31 Hardware Request Status Channel 31 31 1 read-only 0 A hardware service request for channel 31 is not present #0 1 A hardware service request for channel 31 is present #1 EARS Enable Asynchronous Request in Stop Register 0x44 32 read-write 0 0xFFFFFFFF EDREQ_0 Enable asynchronous DMA request in stop mode for channel 0. 0 1 read-write 0 Disable asynchronous DMA request for channel 0. #0 1 Enable asynchronous DMA request for channel 0. #1 EDREQ_1 Enable asynchronous DMA request in stop mode for channel 1. 1 1 read-write 0 Disable asynchronous DMA request for channel 1 #0 1 Enable asynchronous DMA request for channel 1. #1 EDREQ_2 Enable asynchronous DMA request in stop mode for channel 2. 2 1 read-write 0 Disable asynchronous DMA request for channel 2. #0 1 Enable asynchronous DMA request for channel 2. #1 EDREQ_3 Enable asynchronous DMA request in stop mode for channel 3. 3 1 read-write 0 Disable asynchronous DMA request for channel 3. #0 1 Enable asynchronous DMA request for channel 3. #1 EDREQ_4 Enable asynchronous DMA request in stop mode for channel 4 4 1 read-write 0 Disable asynchronous DMA request for channel 4. #0 1 Enable asynchronous DMA request for channel 4. #1 EDREQ_5 Enable asynchronous DMA request in stop mode for channel 5 5 1 read-write 0 Disable asynchronous DMA request for channel 5. #0 1 Enable asynchronous DMA request for channel 5. #1 EDREQ_6 Enable asynchronous DMA request in stop mode for channel 6 6 1 read-write 0 Disable asynchronous DMA request for channel 6. #0 1 Enable asynchronous DMA request for channel 6. #1 EDREQ_7 Enable asynchronous DMA request in stop mode for channel 7 7 1 read-write 0 Disable asynchronous DMA request for channel 7. #0 1 Enable asynchronous DMA request for channel 7. #1 EDREQ_8 Enable asynchronous DMA request in stop mode for channel 8 8 1 read-write 0 Disable asynchronous DMA request for channel 8. #0 1 Enable asynchronous DMA request for channel 8. #1 EDREQ_9 Enable asynchronous DMA request in stop mode for channel 9 9 1 read-write 0 Disable asynchronous DMA request for channel 9. #0 1 Enable asynchronous DMA request for channel 9. #1 EDREQ_10 Enable asynchronous DMA request in stop mode for channel 10 10 1 read-write 0 Disable asynchronous DMA request for channel 10. #0 1 Enable asynchronous DMA request for channel 10. #1 EDREQ_11 Enable asynchronous DMA request in stop mode for channel 11 11 1 read-write 0 Disable asynchronous DMA request for channel 11. #0 1 Enable asynchronous DMA request for channel 11. #1 EDREQ_12 Enable asynchronous DMA request in stop mode for channel 12 12 1 read-write 0 Disable asynchronous DMA request for channel 12. #0 1 Enable asynchronous DMA request for channel 12. #1 EDREQ_13 Enable asynchronous DMA request in stop mode for channel 13 13 1 read-write 0 Disable asynchronous DMA request for channel 13. #0 1 Enable asynchronous DMA request for channel 13. #1 EDREQ_14 Enable asynchronous DMA request in stop mode for channel 14 14 1 read-write 0 Disable asynchronous DMA request for channel 14. #0 1 Enable asynchronous DMA request for channel 14. #1 EDREQ_15 Enable asynchronous DMA request in stop mode for channel 15 15 1 read-write 0 Disable asynchronous DMA request for channel 15. #0 1 Enable asynchronous DMA request for channel 15. #1 EDREQ_16 Enable asynchronous DMA request in stop mode for channel 16 16 1 read-write 0 Disable asynchronous DMA request for channel 16 #0 1 Enable asynchronous DMA request for channel 16 #1 EDREQ_17 Enable asynchronous DMA request in stop mode for channel 17 17 1 read-write 0 Disable asynchronous DMA request for channel 17 #0 1 Enable asynchronous DMA request for channel 17 #1 EDREQ_18 Enable asynchronous DMA request in stop mode for channel 18 18 1 read-write 0 Disable asynchronous DMA request for channel 18 #0 1 Enable asynchronous DMA request for channel 18 #1 EDREQ_19 Enable asynchronous DMA request in stop mode for channel 19 19 1 read-write 0 Disable asynchronous DMA request for channel 19 #0 1 Enable asynchronous DMA request for channel 19 #1 EDREQ_20 Enable asynchronous DMA request in stop mode for channel 20 20 1 read-write 0 Disable asynchronous DMA request for channel 20 #0 1 Enable asynchronous DMA request for channel 20 #1 EDREQ_21 Enable asynchronous DMA request in stop mode for channel 21 21 1 read-write 0 Disable asynchronous DMA request for channel 21 #0 1 Enable asynchronous DMA request for channel 21 #1 EDREQ_22 Enable asynchronous DMA request in stop mode for channel 22 22 1 read-write 0 Disable asynchronous DMA request for channel 22 #0 1 Enable asynchronous DMA request for channel 22 #1 EDREQ_23 Enable asynchronous DMA request in stop mode for channel 23 23 1 read-write 0 Disable asynchronous DMA request for channel 23 #0 1 Enable asynchronous DMA request for channel 23 #1 EDREQ_24 Enable asynchronous DMA request in stop mode for channel 24 24 1 read-write 0 Disable asynchronous DMA request for channel 24 #0 1 Enable asynchronous DMA request for channel 24 #1 EDREQ_25 Enable asynchronous DMA request in stop mode for channel 25 25 1 read-write 0 Disable asynchronous DMA request for channel 25 #0 1 Enable asynchronous DMA request for channel 25 #1 EDREQ_26 Enable asynchronous DMA request in stop mode for channel 26 26 1 read-write 0 Disable asynchronous DMA request for channel 26 #0 1 Enable asynchronous DMA request for channel 26 #1 EDREQ_27 Enable asynchronous DMA request in stop mode for channel 27 27 1 read-write 0 Disable asynchronous DMA request for channel 27 #0 1 Enable asynchronous DMA request for channel 27 #1 EDREQ_28 Enable asynchronous DMA request in stop mode for channel 28 28 1 read-write 0 Disable asynchronous DMA request for channel 28 #0 1 Enable asynchronous DMA request for channel 28 #1 EDREQ_29 Enable asynchronous DMA request in stop mode for channel 29 29 1 read-write 0 Disable asynchronous DMA request for channel 29 #0 1 Enable asynchronous DMA request for channel 29 #1 EDREQ_30 Enable asynchronous DMA request in stop mode for channel 30 30 1 read-write 0 Disable asynchronous DMA request for channel 30 #0 1 Enable asynchronous DMA request for channel 30 #1 EDREQ_31 Enable asynchronous DMA request in stop mode for channel 31 31 1 read-write 0 Disable asynchronous DMA request for channel 31 #0 1 Enable asynchronous DMA request for channel 31 #1 32 0x1 3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12,19,18,17,16,23,22,21,20,27,26,25,24,31,30,29,28 DCHPRI%s Channel n Priority Register 0x100 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write GRPPRI Channel n Current Group Priority 4 2 read-only DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 32 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 TCD%s_SADDR TCD Source Address 0x1000 32 read-write 0 0 SADDR Source Address 0 32 read-write 32 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 TCD%s_SOFF TCD Signed Source Address Offset 0x1004 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write 32 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 TCD%s_ATTR TCD Transfer Attributes 0x1006 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 32 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 TCD%s_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write 32 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 TCD%s_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 32 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 TCD%s_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 32 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 TCD%s_SLAST TCD Last Source Address Adjustment 0x100C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write 32 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 TCD%s_DADDR TCD Destination Address 0x1010 32 read-write 0 0 DADDR Destination Address 0 32 read-write 32 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 TCD%s_DOFF TCD Signed Destination Address Offset 0x1014 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write 32 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 TCD%s_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1016 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 32 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 TCD%s_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1016 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 5 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 32 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 TCD%s_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1018 32 read-write 0 0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write 32 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 TCD%s_CSR TCD Control and Status 0x101C 16 read-write 0 0 START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 ACTIVE Channel Active 6 1 read-write DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 5 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 32 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 TCD%s_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x101E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 32 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 TCD%s_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x101E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 5 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 FB FlexBus external bus interface FB_ 0x4000C000 0 0x64 registers 6 0xC 0,1,2,3,4,5 CSAR%s Chip Select Address Register 0 32 read-write 0 0xFFFFFFFF BA Base Address 16 16 read-write 6 0xC 0,1,2,3,4,5 CSMR%s Chip Select Mask Register 0x4 32 read-write 0 0xFFFFFFFF V Valid 0 1 read-write 0 Chip-select is invalid. #0 1 Chip-select is valid. #1 WP Write Protect 8 1 read-write 0 Write accesses are allowed. #0 1 Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle. #1 BAM Base Address Mask 16 16 read-write 0 The corresponding address bit in CSAR is used in the chip-select decode. #0 1 The corresponding address bit in CSAR is a don't care in the chip-select decode. #1 6 0xC 0,1,2,3,4,5 CSCR%s Chip Select Control Register 0x8 32 read-write 0x3FFC00 0xFFFFFFFF BSTW Burst-Write Enable 3 1 read-write 0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. #0 1 Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 BSTR Burst-Read Enable 4 1 read-write 0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. #0 1 Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. #1 BEM Byte-Enable Mode 5 1 read-write 0 FB_BE is asserted for data write only. #0 1 FB_BE is asserted for data read and write accesses. #1 PS Port Size 6 2 read-write 00 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. #00 01 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. #01 AA Auto-Acknowledge Enable 8 1 read-write 0 Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. #0 1 Enabled. Internal transfer acknowledge is asserted as specified by WS. #1 BLS Byte-Lane Shift 9 1 read-write 0 Not shifted. Data is left-aligned on FB_AD. #0 1 Shifted. Data is right-aligned on FB_AD. #1 WS Wait States 10 6 read-write WRAH Write Address Hold or Deselect 16 2 read-write 00 1 cycle (default for all but FB_CS0 ) #00 01 2 cycles #01 10 3 cycles #10 11 4 cycles (default for FB_CS0 ) #11 RDAH Read Address Hold or Deselect 18 2 read-write 00 When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. #00 01 When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. #01 10 When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. #10 11 When AA is 1b, 4 cycles. When AA is 0b, 3 cycles. #11 ASET Address Setup 20 2 read-write 00 Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ). #00 01 Assert FB_CSn on the second rising clock edge after the address is asserted. #01 10 Assert FB_CSn on the third rising clock edge after the address is asserted. #10 11 Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ). #11 EXTS Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS /FB_ALE is asserted. 22 1 read-write 0 Disabled. FB_TS /FB_ALE asserts for one bus clock cycle. #0 1 Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts. #1 SWSEN Secondary Wait State Enable 23 1 read-write 0 Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. #0 1 Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. #1 SWS Secondary Wait States 26 6 read-write CSPMCR Chip Select port Multiplexing Control Register 0x60 32 read-write 0 0xFFFFFFFF GROUP5 FlexBus Signal Group 5 Multiplex control 12 4 read-write 0000 FB_TA #0000 0001 FB_CS3 . You must also write 1b to CSCR[AA]. #0001 0010 FB_BE_7_0 . You must also write 1b to CSCR[AA]. #0010 GROUP4 FlexBus Signal Group 4 Multiplex control 16 4 read-write 0000 FB_TBST #0000 0001 FB_CS2 #0001 0010 FB_BE_15_8 #0010 GROUP3 FlexBus Signal Group 3 Multiplex control 20 4 read-write 0000 FB_CS5 #0000 0001 FB_TSIZ1 #0001 0010 FB_BE_23_16 #0010 GROUP2 FlexBus Signal Group 2 Multiplex control 24 4 read-write 0000 FB_CS4 #0000 0001 FB_TSIZ0 #0001 0010 FB_BE_31_24 #0010 GROUP1 FlexBus Signal Group 1 Multiplex control 28 4 read-write 0000 FB_ALE #0000 0001 FB_CS1 #0001 0010 FB_TS #0010 MPU Memory protection unit MPU_ 0x4000D000 0 0x830 registers CESR Control/Error Status Register 0 32 read-write 0x815101 0xFFFFFFFF VLD Valid 0 1 read-write 0 MPU is disabled. All accesses from all bus masters are allowed. #0 1 MPU is enabled #1 NRGD Number Of Region Descriptors 8 4 read-only 0000 8 region descriptors #0000 0001 12 region descriptors #0001 0010 16 region descriptors #0010 NSP Number Of Slave Ports 12 4 read-only HRL Hardware Revision Level 16 4 read-only SPERR Slave Port n Error 27 5 read-write 0 No error has occurred for slave port n. #00000 1 An error has occurred for slave port n. #00001 5 0x8 0,1,2,3,4 EAR%s Error Address Register, slave port n 0x10 32 read-only 0 0xFFFFFFFF EADDR Error Address 0 32 read-only 5 0x8 0,1,2,3,4 EDR%s Error Detail Register, slave port n 0x14 32 read-only 0 0xFFFFFFFF ERW Error Read/Write 0 1 read-only 0 Read #0 1 Write #1 EATTR Error Attributes 1 3 read-only 000 User mode, instruction access #000 001 User mode, data access #001 010 Supervisor mode, instruction access #010 011 Supervisor mode, data access #011 EMN Error Master Number 4 4 read-only EPID Error Process Identification 8 8 read-only EACD Error Access Control Detail 16 16 read-only 12 0x10 0,1,2,3,4,5,6,7,8,9,10,11 RGD%s_WORD0 Region Descriptor n, Word 0 0x400 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 5 27 read-write 12 0x10 0,1,2,3,4,5,6,7,8,9,10,11 RGD%s_WORD1 Region Descriptor n, Word 1 0x404 32 read-write 0xFFFFFFFF 0xFFFFFFFF ENDADDR End Address 5 27 read-write 12 0x10 0,1,2,3,4,5,6,7,8,9,10,11 RGD%s_WORD2 Region Descriptor n, Word 2 0x408 32 read-write 0x61F7DF 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0PE Bus Master 0 Process Identifier enable 5 1 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1PE Bus Master 1 Process Identifier enable 11 1 read-write M2UM Bus Master 2 User Mode Access control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 12 0x10 0,1,2,3,4,5,6,7,8,9,10,11 RGD%s_WORD3 Region Descriptor n, Word 3 0x40C 32 read-write 0x1 0xFFFFFFFF VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 PIDMASK Process Identifier Mask 16 8 read-write PID Process Identifier 24 8 read-write 12 0x4 0,1,2,3,4,5,6,7,8,9,10,11 RGDAAC%s Region Descriptor Alternate Access Control n 0x800 32 read-write 0x61F7DF 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M2UM Bus Master 2 User Mode Access Control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 SDRAM Synchronous DRAM Controller SDRAM_ 0x4000F000 0x42 0x16 registers CTRL Control Register 0x42 16 read-write 0 0 RC Refresh count 0 9 read-write RTIM Refresh timing 9 2 read-write 00 3 clocks #00 01 6 clocks #01 10 9 clocks #10 11 9 clocks #11 IS Initiate self-refresh command. 11 1 read-write 0 Take no action or issue a selfx command to exit self refresh. #0 1 SDRAM controller sends a self command to both SDRAM blocks to put them in low-power, self-refresh state where they remain until IS is cleared. When IS is cleared, the controller sends a selfx command for the SDRAMs to exit self-refresh. The refresh counter is suspended while the SDRAMs are in self-refresh; the SDRAM controls the refresh period. #1 2 0x8 0,1 AC%s Address and Control Register 0x48 32 read-write 0 0x8040 IP Initiate precharge all (pall) command. 3 1 read-write 0 Take no action. #0 1 A pall command is sent to the associated SDRAM block. During initialization, this command is executed after all DRAM controller registers are programmed. After IP is set, the next write to an appropriate SDRAM address generates the pall command to the SDRAM block. #1 PS Port size. 4 2 read-write 00 32-bit port #00 01 8-bit port #01 10 16-bit port #10 11 16-bit port #11 IMRS Initiate mode register set (mrs) command. 6 1 read-write 0 Take no action #0 1 Initiate mrs command #1 CBM Command bit location 8 3 read-write CASL CAS Latency 12 2 read-write RE Refresh enable 15 1 read-write 0 Do not refresh associated DRAM block #0 1 Refresh associated DRAM block #1 BA Base address register. 18 14 read-write 2 0x8 0,1 CM%s Control Mask 0x4C 32 read-write 0 0x1 V Valid. 0 1 read-write 0 Do not decode DRAM accesses. #0 1 Registers controlling the DRAM block are initialized; DRAM accesses can be decoded #1 WP Write protect. 8 1 read-write 0 Allow write accesses #0 1 Ignore write accesses. The DRAM controller ignores write accesses to the memory block and an address exception occurs. Write accesses to a write-protected DRAM region are compared in the chip select module for a hit. If no hit occurs, an external bus cycle is generated. If this external bus cycle is not acknowledged, an access exception occurs. #1 BAM Base address mask. 18 14 read-write 0 The associated address bit is used in decoding the DRAM hit to a memory block #0 1 The associated address bit is not used in the DRAM hit decode #1 FMC Flash Memory Controller FMC_ 0x4001F000 0 0x300 registers PFAPR Flash Access Protection Register 0 32 read-write 0x3F 0xFFFFFFFF M0AP Master 0 Access Protection 0 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M1AP Master 1 Access Protection 2 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M2AP Master 2 Access Protection 4 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M3AP Master 3 Access Protection 6 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M4AP Master 4 Access Protection 8 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M0PFD Master 0 Prefetch Disable 16 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M1PFD Master 1 Prefetch Disable 17 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M2PFD Master 2 Prefetch Disable 18 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M3PFD Master 3 Prefetch Disable 19 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M4PFD Master 4 Prefetch Disable 20 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 PFB0CR Flash Bank 0 Control Register 0x4 32 read-write 0x3004001F 0xFFFFFFFF B0SEBE Bank 0 Single Entry Buffer Enable 0 1 read-write 0 Single entry buffer is disabled. #0 1 Single entry buffer is enabled. #1 B0IPE Bank 0 Instruction Prefetch Enable 1 1 read-write 0 Do not prefetch in response to instruction fetches. #0 1 Enable prefetches in response to instruction fetches. #1 B0DPE Bank 0 Data Prefetch Enable 2 1 read-write 0 Do not prefetch in response to data references. #0 1 Enable prefetches in response to data references. #1 B0ICE Bank 0 Instruction Cache Enable 3 1 read-write 0 Do not cache instruction fetches. #0 1 Cache instruction fetches. #1 B0DCE Bank 0 Data Cache Enable 4 1 read-write 0 Do not cache data references. #0 1 Cache data references. #1 CRC Cache Replacement Control 5 3 read-write 000 LRU replacement algorithm per set across all four ways #000 010 Independent LRU with ways [0-1] for ifetches, [2-3] for data #010 011 Independent LRU with ways [0-2] for ifetches, [3] for data #011 B0MW Bank 0 Memory Width 17 2 read-only 00 32 bits #00 01 64 bits #01 10 128 bits #10 S_B_INV Invalidate Prefetch Speculation Buffer 19 1 write-only 0 Speculation buffer and single entry buffer are not affected. #0 1 Invalidate (clear) speculation buffer and single entry buffer. #1 CINV_WAY Cache Invalidate Way x 20 4 write-only 0 No cache way invalidation for the corresponding cache #0000 1 Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected #0001 CLCK_WAY Cache Lock Way x 24 4 read-write 0 Cache way is unlocked and may be displaced #0000 1 Cache way is locked and its contents are not displaced #0001 B0RWSC Bank 0 Read Wait State Control 28 4 read-only Reserved Reserved 0x8 32 read-only 0x30000000 0xFFFFFFFF 4 0x4 0,1,2,3 TAGVDW0S%s Cache Tag Storage 0x100 32 read-write 0 0xFFFFFFFF valid 1-bit valid for cache entry 0 1 read-write cache_tag 14-bit tag for cache entry 6 14 read-write 4 0x4 0,1,2,3 TAGVDW1S%s Cache Tag Storage 0x110 32 read-write 0 0xFFFFFFFF valid 1-bit valid for cache entry 0 1 read-write cache_tag 14-bit tag for cache entry 6 14 read-write 4 0x4 0,1,2,3 TAGVDW2S%s Cache Tag Storage 0x120 32 read-write 0 0xFFFFFFFF valid 1-bit valid for cache entry 0 1 read-write cache_tag 14-bit tag for cache entry 6 14 read-write 4 0x4 0,1,2,3 TAGVDW3S%s Cache Tag Storage 0x130 32 read-write 0 0xFFFFFFFF valid 1-bit valid for cache entry 0 1 read-write cache_tag 14-bit tag for cache entry 6 14 read-write 4 0x10 0,1,2,3 DATAW0S%sUM Cache Data Storage (uppermost word) 0x200 32 read-write 0 0xFFFFFFFF data Bits [127:96] of data entry 0 32 read-write 4 0x10 0,1,2,3 DATAW0S%sMU Cache Data Storage (mid-upper word) 0x204 32 read-write 0 0xFFFFFFFF data Bits [95:64] of data entry 0 32 read-write 4 0x10 0,1,2,3 DATAW0S%sML Cache Data Storage (mid-lower word) 0x208 32 read-write 0 0xFFFFFFFF data Bits [63:32] of data entry 0 32 read-write 4 0x10 0,1,2,3 DATAW0S%sLM Cache Data Storage (lowermost word) 0x20C 32 read-write 0 0xFFFFFFFF data Bits [31:0] of data entry 0 32 read-write 4 0x10 0,1,2,3 DATAW1S%sUM Cache Data Storage (uppermost word) 0x240 32 read-write 0 0xFFFFFFFF data Bits [127:96] of data entry 0 32 read-write 4 0x10 0,1,2,3 DATAW1S%sMU Cache Data Storage (mid-upper word) 0x244 32 read-write 0 0xFFFFFFFF data Bits [95:64] of data entry 0 32 read-write 4 0x10 0,1,2,3 DATAW1S%sML Cache Data Storage (mid-lower word) 0x248 32 read-write 0 0xFFFFFFFF data Bits [63:32] of data entry 0 32 read-write 4 0x10 0,1,2,3 DATAW1S%sLM Cache Data Storage (lowermost word) 0x24C 32 read-write 0 0xFFFFFFFF data Bits [31:0] of data entry 0 32 read-write 4 0x10 0,1,2,3 DATAW2S%sUM Cache Data Storage (uppermost word) 0x280 32 read-write 0 0xFFFFFFFF data Bits [127:96] of data entry 0 32 read-write 4 0x10 0,1,2,3 DATAW2S%sMU Cache Data Storage (mid-upper word) 0x284 32 read-write 0 0xFFFFFFFF data Bits [95:64] of data entry 0 32 read-write 4 0x10 0,1,2,3 DATAW2S%sML Cache Data Storage (mid-lower word) 0x288 32 read-write 0 0xFFFFFFFF data Bits [63:32] of data entry 0 32 read-write 4 0x10 0,1,2,3 DATAW2S%sLM Cache Data Storage (lowermost word) 0x28C 32 read-write 0 0xFFFFFFFF data Bits [31:0] of data entry 0 32 read-write 4 0x10 0,1,2,3 DATAW3S%sUM Cache Data Storage (uppermost word) 0x2C0 32 read-write 0 0xFFFFFFFF data Bits [127:96] of data entry 0 32 read-write 4 0x10 0,1,2,3 DATAW3S%sMU Cache Data Storage (mid-upper word) 0x2C4 32 read-write 0 0xFFFFFFFF data Bits [95:64] of data entry 0 32 read-write 4 0x10 0,1,2,3 DATAW3S%sML Cache Data Storage (mid-lower word) 0x2C8 32 read-write 0 0xFFFFFFFF data Bits [63:32] of data entry 0 32 read-write 4 0x10 0,1,2,3 DATAW3S%sLM Cache Data Storage (lowermost word) 0x2CC 32 read-write 0 0xFFFFFFFF data Bits [31:0] of data entry 0 32 read-write FTFA Flash Memory Interface FTFA_ 0x40020000 0 0x2C registers FTFA 18 Read_Collision 19 FSTAT Flash Status Register 0 8 read-write 0 0xFF MGSTAT0 Memory Controller Command Completion Status Flag 0 1 read-only FPVIOL Flash Protection Violation Flag 4 1 read-write 0 No protection violation detected #0 1 Protection violation detected #1 ACCERR Flash Access Error Flag 5 1 read-write 0 No access error detected #0 1 Access error detected #1 RDCOLERR Flash Read Collision Error Flag 6 1 read-write 0 No collision error detected #0 1 Collision error detected #1 CCIF Command Complete Interrupt Flag 7 1 read-write 0 Flash command in progress #0 1 Flash command has completed #1 FCNFG Flash Configuration Register 0x1 8 read-write 0 0xFF ERSSUSP Erase Suspend 4 1 read-write 0 No suspend requested #0 1 Suspend the current Erase Flash Sector command execution. #1 ERSAREQ Erase All Request 5 1 read-only 0 No request or request complete #0 1 Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state. #1 RDCOLLIE Read Collision Error Interrupt Enable 6 1 read-write 0 Read collision error interrupt disabled #0 1 Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]). #1 CCIE Command Complete Interrupt Enable 7 1 read-write 0 Command complete interrupt disabled #0 1 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. #1 FSEC Flash Security Register 0x2 8 read-only 0 0 SEC Flash Security 0 2 read-only 00 MCU security status is secure. #00 01 MCU security status is secure. #01 10 MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.) #10 11 MCU security status is secure. #11 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 00 Freescale factory access granted #00 01 Freescale factory access denied #01 10 Freescale factory access denied #10 11 Freescale factory access granted #11 MEEN Mass Erase Enable 4 2 read-only 00 Mass erase is enabled #00 01 Mass erase is enabled #01 10 Mass erase is disabled #10 11 Mass erase is enabled #11 KEYEN Backdoor Key Security Enable 6 2 read-only 00 Backdoor key access disabled #00 01 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) #01 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 FOPT Flash Option Register 0x3 8 read-only 0 0 OPT Nonvolatile Option 0 8 read-only 12 0x1 3,2,1,0,7,6,5,4,B,A,9,8 FCCOB%s Flash Common Command Object Registers 0x4 8 read-write 0 0xFF CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write 4 0x1 3,2,1,0 FPROT%s Program Flash Protection Registers 0x10 8 read-write 0 0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 8 0x1 H3,H2,H1,H0,L3,L2,L1,L0 XACC%s Execute-only Access Registers 0x18 8 read-only 0 0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 8 0x1 H3,H2,H1,H0,L3,L2,L1,L0 SACC%s Supervisor-only Access Registers 0x20 8 read-only 0 0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 FACSS Flash Access Segment Size Register 0x28 8 read-only 0 0 SGSIZE Segment Size 0 8 read-only FACSN Flash Access Segment Number Register 0x2B 8 read-only 0 0 NUMSG Number of Segments Indicator 0 8 read-only 100000 Program flash memory is divided into 32 segments (64 Kbytes, 128 Kbytes) #100000 101000 Program flash memory is divided into 40 segments (160 Kbytes) #101000 1000000 Program flash memory is divided into 64 segments (256 Kbytes, 512 Kbytes) #1000000 DMAMUX DMA channel multiplexor DMAMUX_ 0x40021000 0 0x20 registers 32 0x1 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 CHCFG%s Channel Configuration register 0 8 read-write 0 0xFF SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SPI0 Serial Peripheral Interface SPI SPI0_ 0x4002C000 0 0x8C registers SPI0 26 MCR Module Configuration Register 0 32 read-write 0x4001 0xFFFFFFFF HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 SMPL_PT Sample Point 8 2 read-write 00 0 protocol clock cycles between SCK edge and SIN sample #00 01 1 protocol clock cycle between SCK edge and SIN sample #01 10 2 protocol clock cycles between SCK edge and SIN sample #10 CLR_RXF CLR_RXF 10 1 write-only 0 Do not clear the RX FIFO counter. #0 1 Clear the RX FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the TX FIFO counter. #0 1 Clear the TX FIFO counter. #1 DIS_RXF Disable Receive FIFO 12 1 read-write 0 RX FIFO is enabled. #0 1 RX FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 TX FIFO is enabled. #0 1 TX FIFO is disabled. #1 MDIS Module Disable 14 1 read-write 0 Enables the module clocks. #0 1 Allows external logic to disable the module clocks. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on the module. #0 1 Doze mode disables the module. #1 PCSIS Peripheral Chip Select x Inactive State 16 6 read-write 0 The inactive state of PCSx is low. #0 1 The inactive state of PCSx is high. #1 ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 PCSSE Peripheral Chip Select Strobe Enable 25 1 read-write 0 PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. #0 1 PCS5/ PCSS is used as an active-low PCS Strobe signal. #1 MTFE Modified Transfer Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in Debug mode. #0 1 Halt serial transfers in Debug mode. #1 DCONF SPI Configuration. 28 2 read-only 00 SPI #00 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 Enables Slave mode #0 1 Enables Master mode #1 TCR Transfer Count Register 0x8 32 read-write 0 0xFFFFFFFF SPI_TCNT SPI Transfer Counter 16 16 read-write 2 0x4 0,1 CTAR%s Clock and Transfer Attributes Register (In Master Mode) SPI0 0xC 32 read-write 0x78000000 0xFFFFFFFF BR Baud Rate Scaler 0 4 read-write DT Delay After Transfer Scaler 4 4 read-write ASC After SCK Delay Scaler 8 4 read-write CSSCK PCS to SCK Delay Scaler 12 4 read-write PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 CTAR_SLAVE Clock and Transfer Attributes Register (In Slave Mode) SPI0 0xC 32 read-write 0x78000000 0xFFFFFFFF CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write SR Status Register 0x2C 32 read-write 0x2000000 0xFFFFFFFF POPNXTPTR Pop Next Pointer 0 4 read-only RXCTR RX FIFO Counter 4 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXCTR TX FIFO Counter 12 4 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 RX FIFO is empty. #0 1 RX FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 TX FIFO is full. #0 1 TX FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No TX FIFO underflow. #0 1 TX FIFO underflow has occurred. #1 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 TXRXS TX and RX Status 30 1 read-write 0 Transmit and receive operations are disabled (The module is in Stopped state). #0 1 Transmit and receive operations are enabled (The module is in Running state). #1 TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 RSER DMA/Interrupt Request Select and Enable Register 0x30 32 read-write 0 0xFFFFFFFF RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled. #0 1 RFDF interrupt or DMA requests are enabled. #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 EOQF_RE Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 PUSHR PUSH TX FIFO Register In Master Mode SPI0 0x34 32 read-write 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-write PCS Select which PCS signals are to be asserted for the transfer 16 6 read-write 0 Negate the PCS[x] signal. #0 1 Assert the PCS[x] signal. #1 CTCNT Clear Transfer Counter 26 1 read-write 0 Do not clear the TCR[TCNT] field. #0 1 Clear the TCR[TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 CTAS Clock and Transfer Attributes Select 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 PUSHR_SLAVE PUSH TX FIFO Register In Slave Mode SPI0 0x34 32 read-write 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-write POPR POP RX FIFO Register 0x38 32 read-only 0 0xFFFFFFFF RXDATA Received Data 0 32 read-only 4 0x4 0,1,2,3 TXFR%s Transmit FIFO Registers 0x3C 32 read-only 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-only TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only 4 0x4 0,1,2,3 RXFR%s Receive FIFO Registers 0x7C 32 read-only 0 0xFFFFFFFF RXDATA Receive Data 0 32 read-only SPI1 Serial Peripheral Interface SPI SPI1_ 0x4002D000 0 0x8C registers SPI1 27 MCR Module Configuration Register 0 32 read-write 0x4001 0xFFFFFFFF HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 SMPL_PT Sample Point 8 2 read-write 00 0 protocol clock cycles between SCK edge and SIN sample #00 01 1 protocol clock cycle between SCK edge and SIN sample #01 10 2 protocol clock cycles between SCK edge and SIN sample #10 CLR_RXF CLR_RXF 10 1 write-only 0 Do not clear the RX FIFO counter. #0 1 Clear the RX FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the TX FIFO counter. #0 1 Clear the TX FIFO counter. #1 DIS_RXF Disable Receive FIFO 12 1 read-write 0 RX FIFO is enabled. #0 1 RX FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 TX FIFO is enabled. #0 1 TX FIFO is disabled. #1 MDIS Module Disable 14 1 read-write 0 Enables the module clocks. #0 1 Allows external logic to disable the module clocks. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on the module. #0 1 Doze mode disables the module. #1 PCSIS Peripheral Chip Select x Inactive State 16 6 read-write 0 The inactive state of PCSx is low. #0 1 The inactive state of PCSx is high. #1 ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 PCSSE Peripheral Chip Select Strobe Enable 25 1 read-write 0 PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. #0 1 PCS5/ PCSS is used as an active-low PCS Strobe signal. #1 MTFE Modified Transfer Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in Debug mode. #0 1 Halt serial transfers in Debug mode. #1 DCONF SPI Configuration. 28 2 read-only 00 SPI #00 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 Enables Slave mode #0 1 Enables Master mode #1 TCR Transfer Count Register 0x8 32 read-write 0 0xFFFFFFFF SPI_TCNT SPI Transfer Counter 16 16 read-write 2 0x4 0,1 CTAR%s Clock and Transfer Attributes Register (In Master Mode) SPI1 0xC 32 read-write 0x78000000 0xFFFFFFFF BR Baud Rate Scaler 0 4 read-write DT Delay After Transfer Scaler 4 4 read-write ASC After SCK Delay Scaler 8 4 read-write CSSCK PCS to SCK Delay Scaler 12 4 read-write PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 CTAR_SLAVE Clock and Transfer Attributes Register (In Slave Mode) SPI1 0xC 32 read-write 0x78000000 0xFFFFFFFF CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write SR Status Register 0x2C 32 read-write 0x2000000 0xFFFFFFFF POPNXTPTR Pop Next Pointer 0 4 read-only RXCTR RX FIFO Counter 4 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXCTR TX FIFO Counter 12 4 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 RX FIFO is empty. #0 1 RX FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 TX FIFO is full. #0 1 TX FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No TX FIFO underflow. #0 1 TX FIFO underflow has occurred. #1 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 TXRXS TX and RX Status 30 1 read-write 0 Transmit and receive operations are disabled (The module is in Stopped state). #0 1 Transmit and receive operations are enabled (The module is in Running state). #1 TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 RSER DMA/Interrupt Request Select and Enable Register 0x30 32 read-write 0 0xFFFFFFFF RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled. #0 1 RFDF interrupt or DMA requests are enabled. #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 EOQF_RE Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 PUSHR PUSH TX FIFO Register In Master Mode SPI1 0x34 32 read-write 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-write PCS Select which PCS signals are to be asserted for the transfer 16 6 read-write 0 Negate the PCS[x] signal. #0 1 Assert the PCS[x] signal. #1 CTCNT Clear Transfer Counter 26 1 read-write 0 Do not clear the TCR[TCNT] field. #0 1 Clear the TCR[TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 CTAS Clock and Transfer Attributes Select 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 PUSHR_SLAVE PUSH TX FIFO Register In Slave Mode SPI1 0x34 32 read-write 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-write POPR POP RX FIFO Register 0x38 32 read-only 0 0xFFFFFFFF RXDATA Received Data 0 32 read-only 4 0x4 0,1,2,3 TXFR%s Transmit FIFO Registers 0x3C 32 read-only 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-only TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only 4 0x4 0,1,2,3 RXFR%s Receive FIFO Registers 0x7C 32 read-only 0 0xFFFFFFFF RXDATA Receive Data 0 32 read-only SPI2 Serial Peripheral Interface SPI SPI2_ 0x400AC000 0 0x8C registers SPI2 65 MCR Module Configuration Register 0 32 read-write 0x4001 0xFFFFFFFF HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 SMPL_PT Sample Point 8 2 read-write 00 0 protocol clock cycles between SCK edge and SIN sample #00 01 1 protocol clock cycle between SCK edge and SIN sample #01 10 2 protocol clock cycles between SCK edge and SIN sample #10 CLR_RXF CLR_RXF 10 1 write-only 0 Do not clear the RX FIFO counter. #0 1 Clear the RX FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the TX FIFO counter. #0 1 Clear the TX FIFO counter. #1 DIS_RXF Disable Receive FIFO 12 1 read-write 0 RX FIFO is enabled. #0 1 RX FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 TX FIFO is enabled. #0 1 TX FIFO is disabled. #1 MDIS Module Disable 14 1 read-write 0 Enables the module clocks. #0 1 Allows external logic to disable the module clocks. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on the module. #0 1 Doze mode disables the module. #1 PCSIS Peripheral Chip Select x Inactive State 16 6 read-write 0 The inactive state of PCSx is low. #0 1 The inactive state of PCSx is high. #1 ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 PCSSE Peripheral Chip Select Strobe Enable 25 1 read-write 0 PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. #0 1 PCS5/ PCSS is used as an active-low PCS Strobe signal. #1 MTFE Modified Transfer Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in Debug mode. #0 1 Halt serial transfers in Debug mode. #1 DCONF SPI Configuration. 28 2 read-only 00 SPI #00 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 Enables Slave mode #0 1 Enables Master mode #1 TCR Transfer Count Register 0x8 32 read-write 0 0xFFFFFFFF SPI_TCNT SPI Transfer Counter 16 16 read-write 2 0x4 0,1 CTAR%s Clock and Transfer Attributes Register (In Master Mode) SPI2 0xC 32 read-write 0x78000000 0xFFFFFFFF BR Baud Rate Scaler 0 4 read-write DT Delay After Transfer Scaler 4 4 read-write ASC After SCK Delay Scaler 8 4 read-write CSSCK PCS to SCK Delay Scaler 12 4 read-write PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 CTAR_SLAVE Clock and Transfer Attributes Register (In Slave Mode) SPI2 0xC 32 read-write 0x78000000 0xFFFFFFFF CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write SR Status Register 0x2C 32 read-write 0x2000000 0xFFFFFFFF POPNXTPTR Pop Next Pointer 0 4 read-only RXCTR RX FIFO Counter 4 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXCTR TX FIFO Counter 12 4 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 RX FIFO is empty. #0 1 RX FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 TX FIFO is full. #0 1 TX FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No TX FIFO underflow. #0 1 TX FIFO underflow has occurred. #1 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 TXRXS TX and RX Status 30 1 read-write 0 Transmit and receive operations are disabled (The module is in Stopped state). #0 1 Transmit and receive operations are enabled (The module is in Running state). #1 TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 RSER DMA/Interrupt Request Select and Enable Register 0x30 32 read-write 0 0xFFFFFFFF RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled. #0 1 RFDF interrupt or DMA requests are enabled. #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 EOQF_RE Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 PUSHR PUSH TX FIFO Register In Master Mode SPI2 0x34 32 read-write 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-write PCS Select which PCS signals are to be asserted for the transfer 16 6 read-write 0 Negate the PCS[x] signal. #0 1 Assert the PCS[x] signal. #1 CTCNT Clear Transfer Counter 26 1 read-write 0 Do not clear the TCR[TCNT] field. #0 1 Clear the TCR[TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 CTAS Clock and Transfer Attributes Select 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 PUSHR_SLAVE PUSH TX FIFO Register In Slave Mode SPI2 0x34 32 read-write 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-write POPR POP RX FIFO Register 0x38 32 read-only 0 0xFFFFFFFF RXDATA Received Data 0 32 read-only 4 0x4 0,1,2,3 TXFR%s Transmit FIFO Registers 0x3C 32 read-only 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-only TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only 4 0x4 0,1,2,3 RXFR%s Receive FIFO Registers 0x7C 32 read-only 0 0xFFFFFFFF RXDATA Receive Data 0 32 read-only I2S0 Inter-IC Sound / Synchronous Audio Interface I2S0_ 0x4002F000 0 0x108 registers I2S0_Tx 28 I2S0_Rx 29 TCSR SAI Transmit Control Register 0 32 read-write 0 0xFFFFFFFF FRDE FIFO Request DMA Enable 0 1 read-write 0 Disables the DMA request. #0 1 Enables the DMA request. #1 FWDE FIFO Warning DMA Enable 1 1 read-write 0 Disables the DMA request. #0 1 Enables the DMA request. #1 FRIE FIFO Request Interrupt Enable 8 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 FWIE FIFO Warning Interrupt Enable 9 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 FEIE FIFO Error Interrupt Enable 10 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 SEIE Sync Error Interrupt Enable 11 1 read-write 0 Disables interrupt. #0 1 Enables interrupt. #1 WSIE Word Start Interrupt Enable 12 1 read-write 0 Disables interrupt. #0 1 Enables interrupt. #1 FRF FIFO Request Flag 16 1 read-only 0 Transmit FIFO watermark has not been reached. #0 1 Transmit FIFO watermark has been reached. #1 FWF FIFO Warning Flag 17 1 read-only 0 No enabled transmit FIFO is empty. #0 1 Enabled transmit FIFO is empty. #1 FEF FIFO Error Flag 18 1 read-write 0 Transmit underrun not detected. #0 1 Transmit underrun detected. #1 SEF Sync Error Flag 19 1 read-write 0 Sync error not detected. #0 1 Frame sync error detected. #1 WSF Word Start Flag 20 1 read-write 0 Start of word not detected. #0 1 Start of word detected. #1 SR Software Reset 24 1 read-write 0 No effect. #0 1 Software reset. #1 FR FIFO Reset 25 1 write-only 0 No effect. #0 1 FIFO reset. #1 BCE Bit Clock Enable 28 1 read-write 0 Transmit bit clock is disabled. #0 1 Transmit bit clock is enabled. #1 DBGE Debug Enable 29 1 read-write 0 Transmitter is disabled in Debug mode, after completing the current frame. #0 1 Transmitter is enabled in Debug mode. #1 STOPE Stop Enable 30 1 read-write 0 Transmitter disabled in Stop mode. #0 1 Transmitter enabled in Stop mode. #1 TE Transmitter Enable 31 1 read-write 0 Transmitter is disabled. #0 1 Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. #1 TCR1 SAI Transmit Configuration 1 Register 0x4 32 read-write 0 0xFFFFFFFF TFW Transmit FIFO Watermark 0 3 read-write TCR2 SAI Transmit Configuration 2 Register 0x8 32 read-write 0 0xFFFFFFFF DIV Bit Clock Divide 0 8 read-write BCD Bit Clock Direction 24 1 read-write 0 Bit clock is generated externally in Slave mode. #0 1 Bit clock is generated internally in Master mode. #1 BCP Bit Clock Polarity 25 1 read-write 0 Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. #0 1 Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. #1 MSEL MCLK Select 26 2 read-write 00 Bus Clock selected. #00 01 Master Clock (MCLK) 1 option selected. #01 10 Master Clock (MCLK) 2 option selected. #10 11 Master Clock (MCLK) 3 option selected. #11 BCI Bit Clock Input 28 1 read-write 0 No effect. #0 1 Internal logic is clocked as if bit clock was externally generated. #1 BCS Bit Clock Swap 29 1 read-write 0 Use the normal bit clock source. #0 1 Swap the bit clock source. #1 SYNC Synchronous Mode 30 2 read-write 00 Asynchronous mode. #00 01 Synchronous with receiver. #01 10 Synchronous with another SAI transmitter. #10 11 Synchronous with another SAI receiver. #11 TCR3 SAI Transmit Configuration 3 Register 0xC 32 read-write 0 0xFFFFFFFF WDFL Word Flag Configuration 0 5 read-write TCE Transmit Channel Enable 16 2 read-write 0 Transmit data channel N is disabled. #00 1 Transmit data channel N is enabled. #01 CFR Channel FIFO Reset 24 2 write-only 0 No effect. #00 1 Transmit data channel N FIFO is reset. #01 TCR4 SAI Transmit Configuration 4 Register 0x10 32 read-write 0 0xFFFFFFFF FSD Frame Sync Direction 0 1 read-write 0 Frame sync is generated externally in Slave mode. #0 1 Frame sync is generated internally in Master mode. #1 FSP Frame Sync Polarity 1 1 read-write 0 Frame sync is active high. #0 1 Frame sync is active low. #1 ONDEM On Demand Mode 2 1 read-write 0 Internal frame sync is generated continuously. #0 1 Internal frame sync is generated when the FIFO warning flag is clear. #1 FSE Frame Sync Early 3 1 read-write 0 Frame sync asserts with the first bit of the frame. #0 1 Frame sync asserts one bit before the first bit of the frame. #1 MF MSB First 4 1 read-write 0 LSB is transmitted first. #0 1 MSB is transmitted first. #1 SYWD Sync Width 8 5 read-write FRSZ Frame size 16 5 read-write FPACK FIFO Packing Mode 24 2 read-write 00 FIFO packing is disabled #00 10 8-bit FIFO packing is enabled #10 11 16-bit FIFO packing is enabled #11 FCOMB FIFO Combine Mode 26 2 read-write 00 FIFO combine mode disabled. #00 01 FIFO combine mode enabled on FIFO reads (from transmit shift registers). #01 10 FIFO combine mode enabled on FIFO writes (by software). #10 11 FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). #11 FCONT FIFO Continue on Error 28 1 read-write 0 On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. #0 1 On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. #1 TCR5 SAI Transmit Configuration 5 Register 0x14 32 read-write 0 0xFFFFFFFF FBT First Bit Shifted 8 5 read-write W0W Word 0 Width 16 5 read-write WNW Word N Width 24 5 read-write 2 0x4 0,1 TDR%s SAI Transmit Data Register 0x20 32 write-only 0 0xFFFFFFFF TDR Transmit Data Register 0 32 write-only 2 0x4 0,1 TFR%s SAI Transmit FIFO Register 0x40 32 read-only 0 0xFFFFFFFF RFP Read FIFO Pointer 0 4 read-only WFP Write FIFO Pointer 16 4 read-only WCP Write Channel Pointer 31 1 read-only 0 No effect. #0 1 FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. #1 TMR SAI Transmit Mask Register 0x60 32 read-write 0 0xFFFFFFFF TWM Transmit Word Mask 0 32 read-write 0 Word N is enabled. #0 1 Word N is masked. The transmit data pins are tri-stated when masked. #1 RCSR SAI Receive Control Register 0x80 32 read-write 0 0xFFFFFFFF FRDE FIFO Request DMA Enable 0 1 read-write 0 Disables the DMA request. #0 1 Enables the DMA request. #1 FWDE FIFO Warning DMA Enable 1 1 read-write 0 Disables the DMA request. #0 1 Enables the DMA request. #1 FRIE FIFO Request Interrupt Enable 8 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 FWIE FIFO Warning Interrupt Enable 9 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 FEIE FIFO Error Interrupt Enable 10 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 SEIE Sync Error Interrupt Enable 11 1 read-write 0 Disables interrupt. #0 1 Enables interrupt. #1 WSIE Word Start Interrupt Enable 12 1 read-write 0 Disables interrupt. #0 1 Enables interrupt. #1 FRF FIFO Request Flag 16 1 read-only 0 Receive FIFO watermark not reached. #0 1 Receive FIFO watermark has been reached. #1 FWF FIFO Warning Flag 17 1 read-only 0 No enabled receive FIFO is full. #0 1 Enabled receive FIFO is full. #1 FEF FIFO Error Flag 18 1 read-write 0 Receive overflow not detected. #0 1 Receive overflow detected. #1 SEF Sync Error Flag 19 1 read-write 0 Sync error not detected. #0 1 Frame sync error detected. #1 WSF Word Start Flag 20 1 read-write 0 Start of word not detected. #0 1 Start of word detected. #1 SR Software Reset 24 1 read-write 0 No effect. #0 1 Software reset. #1 FR FIFO Reset 25 1 write-only 0 No effect. #0 1 FIFO reset. #1 BCE Bit Clock Enable 28 1 read-write 0 Receive bit clock is disabled. #0 1 Receive bit clock is enabled. #1 DBGE Debug Enable 29 1 read-write 0 Receiver is disabled in Debug mode, after completing the current frame. #0 1 Receiver is enabled in Debug mode. #1 STOPE Stop Enable 30 1 read-write 0 Receiver disabled in Stop mode. #0 1 Receiver enabled in Stop mode. #1 RE Receiver Enable 31 1 read-write 0 Receiver is disabled. #0 1 Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. #1 RCR1 SAI Receive Configuration 1 Register 0x84 32 read-write 0 0xFFFFFFFF RFW Receive FIFO Watermark 0 3 read-write RCR2 SAI Receive Configuration 2 Register 0x88 32 read-write 0 0xFFFFFFFF DIV Bit Clock Divide 0 8 read-write BCD Bit Clock Direction 24 1 read-write 0 Bit clock is generated externally in Slave mode. #0 1 Bit clock is generated internally in Master mode. #1 BCP Bit Clock Polarity 25 1 read-write 0 Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. #0 1 Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. #1 MSEL MCLK Select 26 2 read-write 00 Bus Clock selected. #00 01 Master Clock (MCLK) 1 option selected. #01 10 Master Clock (MCLK) 2 option selected. #10 11 Master Clock (MCLK) 3 option selected. #11 BCI Bit Clock Input 28 1 read-write 0 No effect. #0 1 Internal logic is clocked as if bit clock was externally generated. #1 BCS Bit Clock Swap 29 1 read-write 0 Use the normal bit clock source. #0 1 Swap the bit clock source. #1 SYNC Synchronous Mode 30 2 read-write 00 Asynchronous mode. #00 01 Synchronous with transmitter. #01 10 Synchronous with another SAI receiver. #10 11 Synchronous with another SAI transmitter. #11 RCR3 SAI Receive Configuration 3 Register 0x8C 32 read-write 0 0xFFFFFFFF WDFL Word Flag Configuration 0 5 read-write RCE Receive Channel Enable 16 2 read-write 0 Receive data channel N is disabled. #00 1 Receive data channel N is enabled. #01 CFR Channel FIFO Reset 24 2 write-only 0 No effect. #00 1 Receive data channel N FIFO is reset. #01 RCR4 SAI Receive Configuration 4 Register 0x90 32 read-write 0 0xFFFFFFFF FSD Frame Sync Direction 0 1 read-write 0 Frame Sync is generated externally in Slave mode. #0 1 Frame Sync is generated internally in Master mode. #1 FSP Frame Sync Polarity 1 1 read-write 0 Frame sync is active high. #0 1 Frame sync is active low. #1 ONDEM On Demand Mode 2 1 read-write 0 Internal frame sync is generated continuously. #0 1 Internal frame sync is generated when the FIFO warning flag is clear. #1 FSE Frame Sync Early 3 1 read-write 0 Frame sync asserts with the first bit of the frame. #0 1 Frame sync asserts one bit before the first bit of the frame. #1 MF MSB First 4 1 read-write 0 LSB is received first. #0 1 MSB is received first. #1 SYWD Sync Width 8 5 read-write FRSZ Frame Size 16 5 read-write FPACK FIFO Packing Mode 24 2 read-write 00 FIFO packing is disabled #00 10 8-bit FIFO packing is enabled #10 11 16-bit FIFO packing is enabled #11 FCOMB FIFO Combine Mode 26 2 read-write 00 FIFO combine mode disabled. #00 01 FIFO combine mode enabled on FIFO writes (from receive shift registers). #01 10 FIFO combine mode enabled on FIFO reads (by software). #10 11 FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). #11 FCONT FIFO Continue on Error 28 1 read-write 0 On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. #0 1 On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. #1 RCR5 SAI Receive Configuration 5 Register 0x94 32 read-write 0 0xFFFFFFFF FBT First Bit Shifted 8 5 read-write W0W Word 0 Width 16 5 read-write WNW Word N Width 24 5 read-write 2 0x4 0,1 RDR%s SAI Receive Data Register 0xA0 32 read-only 0 0xFFFFFFFF RDR Receive Data Register 0 32 read-only 2 0x4 0,1 RFR%s SAI Receive FIFO Register 0xC0 32 read-only 0 0xFFFFFFFF RFP Read FIFO Pointer 0 4 read-only RCP Receive Channel Pointer 15 1 read-only 0 No effect. #0 1 FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. #1 WFP Write FIFO Pointer 16 4 read-only RMR SAI Receive Mask Register 0xE0 32 read-write 0 0xFFFFFFFF RWM Receive Word Mask 0 32 read-write 0 Word N is enabled. #0 1 Word N is masked. #1 MCR SAI MCLK Control Register 0x100 32 read-write 0 0xFFFFFFFF MICS MCLK Input Clock Select 24 2 read-write 00 MCLK divider input clock 0 is selected. #00 10 MCLK divider input clock 2 is selected. #10 11 MCLK divider input clock 3 is selected. #11 MOE MCLK Output Enable 30 1 read-write 0 MCLK signal pin is configured as an input that bypasses the MCLK divider. #0 1 MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled. #1 DUF Divider Update Flag 31 1 read-only 0 MCLK divider ratio is not being updated currently. #0 1 MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set. #1 MDR SAI MCLK Divide Register 0x104 32 read-write 0 0xFFFFFFFF DIVIDE MCLK Divide 0 12 read-write FRACT MCLK Fraction 12 8 read-write CRC Cyclic Redundancy Check CRC_ 0x40032000 0 0xC registers DATA CRC Data register CRC 0 32 read-write 0xFFFFFFFF 0xFFFFFFFF LL CRC Low Lower Byte 0 8 read-write LU CRC Low Upper Byte 8 8 read-write HL CRC High Lower Byte 16 8 read-write HU CRC High Upper Byte 24 8 read-write DATAL CRC_DATAL register. CRC 0 16 read-write 0xFFFF 0xFFFF DATAL DATAL stores the lower 16 bits of the 16/32 bit CRC 0 16 read-write DATALL CRC_DATALL register. CRC 0 8 read-write 0xFF 0xFF DATALL CRCLL stores the first 8 bits of the 32 bit DATA 0 8 read-write DATALU CRC_DATALU register. 0x1 8 read-write 0xFF 0xFF DATALU DATALL stores the second 8 bits of the 32 bit CRC 0 8 read-write DATAH CRC_DATAH register. CRC 0x2 16 read-write 0xFFFF 0xFFFF DATAH DATAH stores the high 16 bits of the 16/32 bit CRC 0 16 read-write DATAHL CRC_DATAHL register. CRC 0x2 8 read-write 0xFF 0xFF DATAHL DATAHL stores the third 8 bits of the 32 bit CRC 0 8 read-write DATAHU CRC_DATAHU register. 0x3 8 read-write 0xFF 0xFF DATAHU DATAHU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write GPOLY CRC Polynomial register CRC 0x4 32 read-write 0x1021 0xFFFFFFFF LOW Low Polynominal Half-word 0 16 read-write HIGH High Polynominal Half-word 16 16 read-write GPOLYL CRC_GPOLYL register. CRC 0x4 16 read-write 0xFFFF 0xFFFF GPOLYL POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value 0 16 read-write GPOLYLL CRC_GPOLYLL register. CRC 0x4 8 read-write 0xFF 0xFF GPOLYLL POLYLL stores the first 8 bits of the 32 bit CRC 0 8 read-write GPOLYLU CRC_GPOLYLU register. 0x5 8 read-write 0xFF 0xFF GPOLYLU POLYLL stores the second 8 bits of the 32 bit CRC 0 8 read-write GPOLYH CRC_GPOLYH register. CRC 0x6 16 read-write 0xFFFF 0xFFFF GPOLYH POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value 0 16 read-write GPOLYHL CRC_GPOLYHL register. CRC 0x6 8 read-write 0xFF 0xFF GPOLYHL POLYHL stores the third 8 bits of the 32 bit CRC 0 8 read-write GPOLYHU CRC_GPOLYHU register. 0x7 8 read-write 0xFF 0xFF GPOLYHU POLYHU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write CTRL CRC Control register 0x8 32 read-write 0 0xFFFFFFFF TCRC Width of CRC protocol. 24 1 read-write 0 16-bit CRC protocol. #0 1 32-bit CRC protocol. #1 WAS Write CRC Data Register As Seed 25 1 read-write 0 Writes to the CRC data register are data values. #0 1 Writes to the CRC data register are seed values. #1 FXOR Complement Read Of CRC Data Register 26 1 read-write 0 No XOR on reading. #0 1 Invert or complement the read value of the CRC Data register. #1 TOTR Type Of Transpose For Read 28 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 TOT Type Of Transpose For Writes 30 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 CTRLHU CRC_CTRLHU register. 0xB 8 read-write 0 0xFF TCRC no description available 0 1 read-write 0 16-bit CRC protocol. #0 1 32-bit CRC protocol. #1 WAS no description available 1 1 read-write 0 Writes to CRC data register are data values. #0 1 Writes to CRC data reguster are seed values. #1 FXOR no description available 2 1 read-write 0 No XOR on reading. #0 1 Invert or complement the read value of CRC data register. #1 TOTR no description available 4 2 read-write 00 No Transposition. #00 01 Bits in bytes are transposed, bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 TOT no description available 6 2 read-write 00 No Transposition. #00 01 Bits in bytes are transposed, bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 USBDCD USB Device Charger Detection module USBDCD_ 0x40035000 0 0x1C registers USBDCD 54 CONTROL Control register 0 32 read-write 0x10000 0xFFFFFFFF IACK Interrupt Acknowledge 0 1 write-only 0 Do not clear the interrupt. #0 1 Clear the IF bit (interrupt flag). #1 IF Interrupt Flag 8 1 read-only 0 No interrupt is pending. #0 1 An interrupt is pending. #1 IE Interrupt Enable 16 1 read-write 0 Disable interrupts to the system. #0 1 Enable interrupts to the system. #1 BC12 BC1.2 compatibility. This bit cannot be changed after start detection. 17 1 read-write 0 Compatible with BC1.1 (default) #0 1 Compatible with BC1.2 #1 START Start Change Detection Sequence 24 1 write-only 0 Do not start the sequence. Writes of this value have no effect. #0 1 Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect. #1 SR Software Reset 25 1 write-only 0 Do not perform a software reset. #0 1 Perform a software reset. #1 CLOCK Clock register 0x4 32 read-write 0xC1 0xFFFFFFFF CLOCK_UNIT Unit of Measurement Encoding for Clock Speed 0 1 read-write 0 kHz Speed (between 1 kHz and 1023 kHz) #0 1 MHz Speed (between 1 MHz and 1023 MHz) #1 CLOCK_SPEED Numerical Value of Clock Speed in Binary 2 10 read-write STATUS Status register 0x8 32 read-only 0 0xFFFFFFFF SEQ_RES Charger Detection Sequence Results 16 2 read-only 00 No results to report. #00 01 Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected. #01 10 Attached to a charging port. The exact meaning depends on bit 18: 0: Attached to either a CDP or a DCP. The charger type detection has not completed. 1: Attached to a CDP. The charger type detection has completed. #10 11 Attached to a DCP. #11 SEQ_STAT Charger Detection Sequence Status 18 2 read-only 00 The module is either not enabled, or the module is enabled but the data pins have not yet been detected. #00 01 Data pin contact detection is complete. #01 10 Charging port detection is complete. #10 11 Charger type detection is complete. #11 ERR Error Flag 20 1 read-only 0 No sequence errors. #0 1 Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred. #1 TO Timeout Flag 21 1 read-only 0 The detection sequence has not been running for over 1 s. #0 1 It has been over 1 s since the data pin contact was detected and debounced. #1 ACTIVE Active Status Indicator 22 1 read-only 0 The sequence is not running. #0 1 The sequence is running. #1 SIGNAL_OVERRIDE Signal Override Register 0xC 32 read-write 0 0xFFFFFFFF PS Phase Selection 0 2 read-write 00 No overrides. Bit field must remain at this value during normal USB data communication to prevent unexpected conditions on USB_DP and USB_DM pins. (Default) #00 01 Reserved, not for customer use. #01 10 Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin. #10 11 Reserved, not for customer use. #11 TIMER0 TIMER0 register 0x10 32 read-write 0x100000 0xFFFFFFFF TUNITCON Unit Connection Timer Elapse (in ms) 0 12 read-only TSEQ_INIT Sequence Initiation Time 16 10 read-write TIMER1 TIMER1 register 0x14 32 read-write 0xA0028 0xFFFFFFFF TVDPSRC_ON Time Period Comparator Enabled 0 10 read-write TDCD_DBNC Time Period to Debounce D+ Signal 16 10 read-write TIMER2_BC11 TIMER2_BC11 register USBDCD 0x18 32 read-write 0x280001 0xFFFFFFFF CHECK_DM Time Before Check of D- Line 0 4 read-write TVDPSRC_CON Time Period Before Enabling D+ Pullup 16 10 read-write TIMER2_BC12 TIMER2_BC12 register USBDCD 0x18 32 read-write 0x10028 0xFFFFFFFF TVDMSRC_ON Sets the amount of time (in ms) that the module enables the VDM_SRC. Valid values are 0-40ms. 0 10 read-write TWAIT_AFTER_PRD Sets the amount of time (in ms) that the module waits after primary detection before start to secondary detection 16 10 read-write PDB0 Programmable Delay Block PDB0_ 0x40036000 0 0x19C registers PDB0 52 SC Status and Control register 0 32 read-write 0 0xFFFFFFFF LDOK Load OK 0 1 read-write CONT Continuous Mode Enable 1 1 read-write 0 PDB operation in One-Shot mode #0 1 PDB operation in Continuous mode #1 MULT Multiplication Factor Select for Prescaler 2 2 read-write 00 Multiplication factor is 1. #00 01 Multiplication factor is 10. #01 10 Multiplication factor is 20. #10 11 Multiplication factor is 40. #11 PDBIE PDB Interrupt Enable 5 1 read-write 0 PDB interrupt disabled. #0 1 PDB interrupt enabled. #1 PDBIF PDB Interrupt Flag 6 1 read-write PDBEN PDB Enable 7 1 read-write 0 PDB disabled. Counter is off. #0 1 PDB enabled. #1 TRGSEL Trigger Input Source Select 8 4 read-write 0000 Trigger-In 0 is selected. #0000 0001 Trigger-In 1 is selected. #0001 0010 Trigger-In 2 is selected. #0010 0011 Trigger-In 3 is selected. #0011 0100 Trigger-In 4 is selected. #0100 0101 Trigger-In 5 is selected. #0101 0110 Trigger-In 6 is selected. #0110 0111 Trigger-In 7 is selected. #0111 1000 Trigger-In 8 is selected. #1000 1001 Trigger-In 9 is selected. #1001 1010 Trigger-In 10 is selected. #1010 1011 Trigger-In 11 is selected. #1011 1100 Trigger-In 12 is selected. #1100 1101 Trigger-In 13 is selected. #1101 1110 Trigger-In 14 is selected. #1110 1111 Software trigger is selected. #1111 PRESCALER Prescaler Divider Select 12 3 read-write 000 Counting uses the peripheral clock divided by multiplication factor selected by MULT. #000 001 Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT. #001 010 Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT. #010 011 Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT. #011 100 Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT. #100 101 Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT. #101 110 Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT. #110 111 Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT. #111 DMAEN DMA Enable 15 1 read-write 0 DMA disabled. #0 1 DMA enabled. #1 SWTRIG Software Trigger 16 1 write-only PDBEIE PDB Sequence Error Interrupt Enable 17 1 read-write 0 PDB sequence error interrupt disabled. #0 1 PDB sequence error interrupt enabled. #1 LDMOD Load Mode Select 18 2 read-write 00 The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK. #00 01 The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK. #01 10 The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK. #10 11 The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK. #11 MOD Modulus register 0x4 32 read-write 0xFFFF 0xFFFFFFFF MOD PDB Modulus 0 16 read-write CNT Counter register 0x8 32 read-only 0 0xFFFFFFFF CNT PDB Counter 0 16 read-only IDLY Interrupt Delay register 0xC 32 read-write 0xFFFF 0xFFFFFFFF IDLY PDB Interrupt Delay 0 16 read-write CHC1 Channel n Control register 1 0x10 32 read-write 0 0xFFFFFFFF EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. #1 BB PDB Channel Pre-Trigger Back-to-Back Operation Enable 16 8 read-write 0 PDB channel's corresponding pre-trigger back-to-back operation disabled. #0 1 PDB channel's corresponding pre-trigger back-to-back operation enabled. #1 CHS Channel n Status register 0x14 32 read-write 0 0xFFFFFFFF ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. #1 CF PDB Channel Flags 16 8 read-write CHDLY0 Channel n Delay 0 register 0x18 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write CHDLY1 Channel n Delay 1 register 0x1C 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write DACINTC DAC Interval Trigger n Control register 0x150 32 read-write 0 0xFFFFFFFF TOE DAC Interval Trigger Enable 0 1 read-write 0 DAC interval trigger disabled. #0 1 DAC interval trigger enabled. #1 EXT DAC External Trigger Input Enable 1 1 read-write 0 DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger. #1 DACINT DAC Interval n register 0x154 32 read-write 0 0xFFFFFFFF INT DAC Interval 0 16 read-write POEN Pulse-Out n Enable register 0x190 32 read-write 0 0xFFFFFFFF POEN PDB Pulse-Out Enable 0 8 read-write 0 PDB Pulse-Out disabled #0 1 PDB Pulse-Out enabled #1 2 0x4 0,1 PO%sDLY Pulse-Out n Delay register 0x194 32 read-write 0 0xFFFFFFFF DLY2 PDB Pulse-Out Delay 2 0 16 read-write DLY1 PDB Pulse-Out Delay 1 16 16 read-write PIT0 Periodic Interrupt Timer PIT0_ 0x40037000 0 0x140 registers PIT0CH0 48 PIT0CH1 49 PIT0CH2 50 PIT0CH3 51 MCR PIT Module Control Register 0 32 read-write 0x2 0xFFFFFFFF FRZ Freeze 0 1 read-write 0 Timers continue to run in Debug mode. #0 1 Timers are stopped in Debug mode. #1 MDIS Module Disable - (PIT section) 1 1 read-write 0 Clock for standard PIT timers is enabled. #0 1 Clock for standard PIT timers is disabled. #1 4 0x10 0,1,2,3 LDVAL%s Timer Load Value Register 0x100 32 read-write 0 0xFFFFFFFF TSV Timer Start Value 0 32 read-write 4 0x10 0,1,2,3 CVAL%s Current Timer Value Register 0x104 32 read-only 0 0xFFFFFFFF TVL Current Timer Value 0 32 read-only 4 0x10 0,1,2,3 TCTRL%s Timer Control Register 0x108 32 read-write 0 0xFFFFFFFF TEN Timer Enable 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is enabled. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 CHN Chain Mode 2 1 read-write 0 Timer is not chained. #0 1 Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. #1 4 0x10 0,1,2,3 TFLG%s Timer Flag Register 0x10C 32 read-write 0 0xFFFFFFFF TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 FTM0 FlexTimer Module FTM FTM0_ 0x40038000 0 0x9C registers FTM0 42 SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD Modulo Value 0 16 read-write 8 0x8 0,1,2,3,4,5,6,7 C%sSC Channel (n) Status And Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 8 0x8 0,1,2,3,4,5,6,7 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write 0 0xFFFFFFFF INIT Initial Value Of The FTM Counter 0 16 read-write STATUS Capture And Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 MODE Features Mode Selection 0x54 32 read-write 0x4 0xFFFFFFFF FTMEN FTM Enable 0 1 read-write 0 TPM compatibility. Free running counter and synchronization compatible with TPM. #0 1 Free running counter and synchronization are different from TPM behavior. #1 INIT Initialize The Channels Output 1 1 read-write WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 SYNC Synchronization 0x58 32 read-write 0 0xFFFFFFFF CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 REINIT FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 OUTINIT Initial State For Channels Output 0x5C 32 read-write 0 0xFFFFFFFF CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 OUTMASK Output Mask 0x60 32 read-write 0 0xFFFFFFFF CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 COMBINE Function For Linked Channels 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels For n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE1 Combine Channels For n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE2 Combine Channels For n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE3 Combine Channels For n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 DEADTIME Deadtime Insertion Control 0x68 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 EXTTRIG FTM External Trigger 0x6C 32 read-write 0 0xFFFFFFFF CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 POL Channels Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FMS Fault Mode Status 0x74 32 read-write 0 0xFFFFFFFF FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FILTER Input Capture Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write 0 0xFFFFFFFF FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF NUMTOF TOF Frequency 0 5 read-write BDMMODE BDM Mode 6 2 read-write GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 FLTPOL FTM Fault Input Polarity 0x88 32 read-write 0 0xFFFFFFFF FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write 0 0xFFFFFFFF HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 SWRSTCNT FTM counter synchronization is activated by the software trigger. 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWWRBUF MOD, CNTIN, and CV registers synchronization is activated by the software trigger. 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SWOM Output mask synchronization is activated by the software trigger. 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWINVC Inverting control synchronization is activated by the software trigger. 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWSOC Software output control synchronization is activated by the software trigger. 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 HWRSTCNT FTM counter synchronization is activated by a hardware trigger. 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWWRBUF MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger. 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 HWOM Output mask synchronization is activated by a hardware trigger. 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWINVC Inverting control synchronization is activated by a hardware trigger. 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWSOC Software output control synchronization is activated by a hardware trigger. 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 INVCTRL FTM Inverting Control 0x90 32 read-write 0 0xFFFFFFFF INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 SWOCTRL FTM Software Output Control 0x94 32 read-write 0 0xFFFFFFFF CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 PWMLOAD FTM PWM Load 0x98 32 read-write 0 0xFFFFFFFF CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 FTM1 FlexTimer Module FTM FTM1_ 0x40039000 0 0x9C registers FTM1 43 SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD Modulo Value 0 16 read-write 2 0x8 0,1 C%sSC Channel (n) Status And Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 2 0x8 0,1 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write 0 0xFFFFFFFF INIT Initial Value Of The FTM Counter 0 16 read-write STATUS Capture And Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 MODE Features Mode Selection 0x54 32 read-write 0x4 0xFFFFFFFF FTMEN FTM Enable 0 1 read-write 0 TPM compatibility. Free running counter and synchronization compatible with TPM. #0 1 Free running counter and synchronization are different from TPM behavior. #1 INIT Initialize The Channels Output 1 1 read-write WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 SYNC Synchronization 0x58 32 read-write 0 0xFFFFFFFF CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 REINIT FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 OUTINIT Initial State For Channels Output 0x5C 32 read-write 0 0xFFFFFFFF CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 OUTMASK Output Mask 0x60 32 read-write 0 0xFFFFFFFF CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 COMBINE Function For Linked Channels 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels For n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE1 Combine Channels For n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE2 Combine Channels For n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE3 Combine Channels For n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 DEADTIME Deadtime Insertion Control 0x68 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 EXTTRIG FTM External Trigger 0x6C 32 read-write 0 0xFFFFFFFF CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 POL Channels Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FMS Fault Mode Status 0x74 32 read-write 0 0xFFFFFFFF FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FILTER Input Capture Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write 0 0xFFFFFFFF FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF NUMTOF TOF Frequency 0 5 read-write BDMMODE BDM Mode 6 2 read-write GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 FLTPOL FTM Fault Input Polarity 0x88 32 read-write 0 0xFFFFFFFF FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write 0 0xFFFFFFFF HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 SWRSTCNT FTM counter synchronization is activated by the software trigger. 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWWRBUF MOD, CNTIN, and CV registers synchronization is activated by the software trigger. 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SWOM Output mask synchronization is activated by the software trigger. 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWINVC Inverting control synchronization is activated by the software trigger. 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWSOC Software output control synchronization is activated by the software trigger. 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 HWRSTCNT FTM counter synchronization is activated by a hardware trigger. 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWWRBUF MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger. 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 HWOM Output mask synchronization is activated by a hardware trigger. 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWINVC Inverting control synchronization is activated by a hardware trigger. 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWSOC Software output control synchronization is activated by a hardware trigger. 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 INVCTRL FTM Inverting Control 0x90 32 read-write 0 0xFFFFFFFF INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 SWOCTRL FTM Software Output Control 0x94 32 read-write 0 0xFFFFFFFF CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 PWMLOAD FTM PWM Load 0x98 32 read-write 0 0xFFFFFFFF CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 FTM2 FlexTimer Module FTM FTM2_ 0x4003A000 0 0x9C registers FTM2 44 SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD Modulo Value 0 16 read-write 2 0x8 0,1 C%sSC Channel (n) Status And Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 2 0x8 0,1 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write 0 0xFFFFFFFF INIT Initial Value Of The FTM Counter 0 16 read-write STATUS Capture And Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 MODE Features Mode Selection 0x54 32 read-write 0x4 0xFFFFFFFF FTMEN FTM Enable 0 1 read-write 0 TPM compatibility. Free running counter and synchronization compatible with TPM. #0 1 Free running counter and synchronization are different from TPM behavior. #1 INIT Initialize The Channels Output 1 1 read-write WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 SYNC Synchronization 0x58 32 read-write 0 0xFFFFFFFF CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 REINIT FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 OUTINIT Initial State For Channels Output 0x5C 32 read-write 0 0xFFFFFFFF CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 OUTMASK Output Mask 0x60 32 read-write 0 0xFFFFFFFF CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 COMBINE Function For Linked Channels 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels For n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE1 Combine Channels For n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE2 Combine Channels For n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE3 Combine Channels For n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 DEADTIME Deadtime Insertion Control 0x68 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 EXTTRIG FTM External Trigger 0x6C 32 read-write 0 0xFFFFFFFF CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 POL Channels Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FMS Fault Mode Status 0x74 32 read-write 0 0xFFFFFFFF FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FILTER Input Capture Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write 0 0xFFFFFFFF FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF NUMTOF TOF Frequency 0 5 read-write BDMMODE BDM Mode 6 2 read-write GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 FLTPOL FTM Fault Input Polarity 0x88 32 read-write 0 0xFFFFFFFF FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write 0 0xFFFFFFFF HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 SWRSTCNT FTM counter synchronization is activated by the software trigger. 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWWRBUF MOD, CNTIN, and CV registers synchronization is activated by the software trigger. 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SWOM Output mask synchronization is activated by the software trigger. 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWINVC Inverting control synchronization is activated by the software trigger. 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWSOC Software output control synchronization is activated by the software trigger. 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 HWRSTCNT FTM counter synchronization is activated by a hardware trigger. 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWWRBUF MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger. 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 HWOM Output mask synchronization is activated by a hardware trigger. 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWINVC Inverting control synchronization is activated by a hardware trigger. 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWSOC Software output control synchronization is activated by a hardware trigger. 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 INVCTRL FTM Inverting Control 0x90 32 read-write 0 0xFFFFFFFF INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 SWOCTRL FTM Software Output Control 0x94 32 read-write 0 0xFFFFFFFF CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 PWMLOAD FTM PWM Load 0x98 32 read-write 0 0xFFFFFFFF CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 FTM3 FlexTimer Module FTM FTM3_ 0x400B9000 0 0x9C registers FTM3 71 SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD Modulo Value 0 16 read-write 8 0x8 0,1,2,3,4,5,6,7 C%sSC Channel (n) Status And Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 8 0x8 0,1,2,3,4,5,6,7 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write 0 0xFFFFFFFF INIT Initial Value Of The FTM Counter 0 16 read-write STATUS Capture And Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 MODE Features Mode Selection 0x54 32 read-write 0x4 0xFFFFFFFF FTMEN FTM Enable 0 1 read-write 0 TPM compatibility. Free running counter and synchronization compatible with TPM. #0 1 Free running counter and synchronization are different from TPM behavior. #1 INIT Initialize The Channels Output 1 1 read-write WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 SYNC Synchronization 0x58 32 read-write 0 0xFFFFFFFF CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 REINIT FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 OUTINIT Initial State For Channels Output 0x5C 32 read-write 0 0xFFFFFFFF CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 OUTMASK Output Mask 0x60 32 read-write 0 0xFFFFFFFF CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 COMBINE Function For Linked Channels 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels For n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE1 Combine Channels For n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE2 Combine Channels For n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE3 Combine Channels For n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 DEADTIME Deadtime Insertion Control 0x68 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 EXTTRIG FTM External Trigger 0x6C 32 read-write 0 0xFFFFFFFF CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 POL Channels Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FMS Fault Mode Status 0x74 32 read-write 0 0xFFFFFFFF FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FILTER Input Capture Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write 0 0xFFFFFFFF FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF NUMTOF TOF Frequency 0 5 read-write BDMMODE BDM Mode 6 2 read-write GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 FLTPOL FTM Fault Input Polarity 0x88 32 read-write 0 0xFFFFFFFF FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write 0 0xFFFFFFFF HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 SWRSTCNT FTM counter synchronization is activated by the software trigger. 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWWRBUF MOD, CNTIN, and CV registers synchronization is activated by the software trigger. 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SWOM Output mask synchronization is activated by the software trigger. 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWINVC Inverting control synchronization is activated by the software trigger. 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWSOC Software output control synchronization is activated by the software trigger. 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 HWRSTCNT FTM counter synchronization is activated by a hardware trigger. 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWWRBUF MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger. 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 HWOM Output mask synchronization is activated by a hardware trigger. 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWINVC Inverting control synchronization is activated by a hardware trigger. 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWSOC Software output control synchronization is activated by a hardware trigger. 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 INVCTRL FTM Inverting Control 0x90 32 read-write 0 0xFFFFFFFF INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 SWOCTRL FTM Software Output Control 0x94 32 read-write 0 0xFFFFFFFF CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 PWMLOAD FTM PWM Load 0x98 32 read-write 0 0xFFFFFFFF CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 ADC0 Analog-to-Digital Converter ADC0_ 0x4003B000 0 0x70 registers ADC0 39 2 0x4 A,B SC1%s ADC Status and Control Registers 1 0 32 read-write 0x1F 0xFFFFFFFF ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11010 When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11101 When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. #11101 11110 When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. #11110 11111 Module is disabled. #11111 DIFF Differential Mode Enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 AIEN Interrupt Enable 6 1 read-write 0 Conversion complete interrupt is disabled. #0 1 Conversion complete interrupt is enabled. #1 COCO Conversion Complete Flag 7 1 read-only 0 Conversion is not completed. #0 1 Conversion is completed. #1 CFG1 ADC Configuration Register 1 0x8 32 read-write 0 0xFFFFFFFF ADICLK Input Clock Select 0 2 read-write 00 Bus clock #00 01 Alternate clock 2 (ALTCLK2) #01 10 Alternate clock (ALTCLK) #10 11 Asynchronous clock (ADACK) #11 MODE Conversion mode selection 2 2 read-write 00 When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. #00 01 When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output. #01 10 When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output #10 11 When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output #11 ADLSMP Sample Time Configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 ADIV Clock Divide Select 5 2 read-write 00 The divide ratio is 1 and the clock rate is input clock. #00 01 The divide ratio is 2 and the clock rate is (input clock)/2. #01 10 The divide ratio is 4 and the clock rate is (input clock)/4. #10 11 The divide ratio is 8 and the clock rate is (input clock)/8. #11 ADLPC Low-Power Configuration 7 1 read-write 0 Normal power configuration. #0 1 Low-power configuration. The power is reduced at the expense of maximum clock speed. #1 CFG2 ADC Configuration Register 2 0xC 32 read-write 0 0xFFFFFFFF ADLSTS Long Sample Time Select 0 2 read-write 00 Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. #00 01 12 extra ADCK cycles; 16 ADCK cycles total sample time. #01 10 6 extra ADCK cycles; 10 ADCK cycles total sample time. #10 11 2 extra ADCK cycles; 6 ADCK cycles total sample time. #11 ADHSC High-Speed Configuration 2 1 read-write 0 Normal conversion sequence selected. #0 1 High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. #1 ADACKEN Asynchronous Clock Output Enable 3 1 read-write 0 Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. #0 1 Asynchronous clock and clock output is enabled regardless of the state of the ADC. #1 MUXSEL ADC Mux Select 4 1 read-write 0 ADxxa channels are selected. #0 1 ADxxb channels are selected. #1 2 0x4 A,B R%s ADC Data Result Register 0x10 32 read-only 0 0xFFFFFFFF D Data result 0 16 read-only 2 0x4 1,2 CV%s Compare Value Registers 0x18 32 read-write 0 0xFFFFFFFF CV Compare Value. 0 16 read-write SC2 Status and Control Register 2 0x20 32 read-write 0 0xFFFFFFFF REFSEL Voltage Reference Selection 0 2 read-write 00 Default voltage reference pin pair, that is, external pins VREFH and VREFL #00 01 Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU #01 DMAEN DMA Enable 2 1 read-write 0 DMA is disabled. #0 1 DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted. #1 ACREN Compare Function Range Enable 3 1 read-write 0 Range function disabled. Only CV1 is compared. #0 1 Range function enabled. Both CV1 and CV2 are compared. #1 ACFGT Compare Function Greater Than Enable 4 1 read-write 0 Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2. #0 1 Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2. #1 ACFE Compare Function Enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ADTRG Conversion Trigger Select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 ADACT Conversion Active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 SC3 Status and Control Register 3 0x24 32 read-write 0 0xFFFFFFFF AVGS Hardware Average Select 0 2 read-write 00 4 samples averaged. #00 01 8 samples averaged. #01 10 16 samples averaged. #10 11 32 samples averaged. #11 AVGE Hardware Average Enable 2 1 read-write 0 Hardware average function disabled. #0 1 Hardware average function enabled. #1 ADCO Continuous Conversion Enable 3 1 read-write 0 One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. #0 1 Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. #1 CALF Calibration Failed Flag 6 1 read-write 0 Calibration completed normally. #0 1 Calibration failed. ADC accuracy specifications are not guaranteed. #1 CAL Calibration 7 1 read-write OFS ADC Offset Correction Register 0x28 32 read-write 0x4 0xFFFFFFFF OFS Offset Error Correction Value 0 16 read-write PG ADC Plus-Side Gain Register 0x2C 32 read-write 0x8200 0xFFFFFFFF PG Plus-Side Gain 0 16 read-write MG ADC Minus-Side Gain Register 0x30 32 read-write 0x8200 0xFFFFFFFF MG Minus-Side Gain 0 16 read-write CLPD ADC Plus-Side General Calibration Value Register 0x34 32 read-write 0xA 0xFFFFFFFF CLPD Calibration Value 0 6 read-write CLPS ADC Plus-Side General Calibration Value Register 0x38 32 read-write 0x20 0xFFFFFFFF CLPS Calibration Value 0 6 read-write CLP4 ADC Plus-Side General Calibration Value Register 0x3C 32 read-write 0x200 0xFFFFFFFF CLP4 Calibration Value 0 10 read-write CLP3 ADC Plus-Side General Calibration Value Register 0x40 32 read-write 0x100 0xFFFFFFFF CLP3 Calibration Value 0 9 read-write CLP2 ADC Plus-Side General Calibration Value Register 0x44 32 read-write 0x80 0xFFFFFFFF CLP2 Calibration Value 0 8 read-write CLP1 ADC Plus-Side General Calibration Value Register 0x48 32 read-write 0x40 0xFFFFFFFF CLP1 Calibration Value 0 7 read-write CLP0 ADC Plus-Side General Calibration Value Register 0x4C 32 read-write 0x20 0xFFFFFFFF CLP0 Calibration Value 0 6 read-write CLMD ADC Minus-Side General Calibration Value Register 0x54 32 read-write 0xA 0xFFFFFFFF CLMD Calibration Value 0 6 read-write CLMS ADC Minus-Side General Calibration Value Register 0x58 32 read-write 0x20 0xFFFFFFFF CLMS Calibration Value 0 6 read-write CLM4 ADC Minus-Side General Calibration Value Register 0x5C 32 read-write 0x200 0xFFFFFFFF CLM4 Calibration Value 0 10 read-write CLM3 ADC Minus-Side General Calibration Value Register 0x60 32 read-write 0x100 0xFFFFFFFF CLM3 Calibration Value 0 9 read-write CLM2 ADC Minus-Side General Calibration Value Register 0x64 32 read-write 0x80 0xFFFFFFFF CLM2 Calibration Value 0 8 read-write CLM1 ADC Minus-Side General Calibration Value Register 0x68 32 read-write 0x40 0xFFFFFFFF CLM1 Calibration Value 0 7 read-write CLM0 ADC Minus-Side General Calibration Value Register 0x6C 32 read-write 0x20 0xFFFFFFFF CLM0 Calibration Value 0 6 read-write RTC Secure Real Time Clock RTC_ 0x4003D000 0 0x808 registers RTC 46 RTC_Seconds 47 TSR RTC Time Seconds Register 0 32 read-write 0 0xFFFFFFFF TSR Time Seconds Register 0 32 read-write TPR RTC Time Prescaler Register 0x4 32 read-write 0 0xFFFFFFFF TPR Time Prescaler Register 0 16 read-write TAR RTC Time Alarm Register 0x8 32 read-write 0 0xFFFFFFFF TAR Time Alarm Register 0 32 read-write TCR RTC Time Compensation Register 0xC 32 read-write 0 0xFFFFFFFF TCR Time Compensation Register 0 8 read-write 10000000 Time Prescaler Register overflows every 32896 clock cycles. #10000000 11111111 Time Prescaler Register overflows every 32769 clock cycles. #11111111 0 Time Prescaler Register overflows every 32768 clock cycles. #0 1 Time Prescaler Register overflows every 32767 clock cycles. #1 1111111 Time Prescaler Register overflows every 32641 clock cycles. #1111111 CIR Compensation Interval Register 8 8 read-write TCV Time Compensation Value 16 8 read-only CIC Compensation Interval Counter 24 8 read-only CR RTC Control Register 0x10 32 read-write 0 0xFFFFFFFF SWR Software Reset 0 1 read-write 0 No effect. #0 1 Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software explicitly clearing it. #1 WPE Wakeup Pin Enable 1 1 read-write 0 Wakeup pin is disabled. #0 1 Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on. #1 SUP Supervisor Access 2 1 read-write 0 Non-supervisor mode write accesses are not supported and generate a bus error. #0 1 Non-supervisor mode write accesses are supported. #1 UM Update Mode 3 1 read-write 0 Registers cannot be written when locked. #0 1 Registers can be written when locked under limited conditions. #1 WPS Wakeup Pin Select 4 1 read-write 0 Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on. #0 1 Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals. #1 OSCE Oscillator Enable 8 1 read-write 0 32.768 kHz oscillator is disabled. #0 1 32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize. #1 CLKO Clock Output 9 1 read-write 0 The 32 kHz clock is output to other peripherals. #0 1 The 32 kHz clock is not output to other peripherals. #1 SC16P Oscillator 16pF Load Configure 10 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC8P Oscillator 8pF Load Configure 11 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC4P Oscillator 4pF Load Configure 12 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC2P Oscillator 2pF Load Configure 13 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SR RTC Status Register 0x14 32 read-write 0x1 0xFFFFFFFF TIF Time Invalid Flag 0 1 read-only 0 Time is valid. #0 1 Time is invalid and time counter is read as zero. #1 TOF Time Overflow Flag 1 1 read-only 0 Time overflow has not occurred. #0 1 Time overflow has occurred and time counter is read as zero. #1 TAF Time Alarm Flag 2 1 read-only 0 Time alarm has not occurred. #0 1 Time alarm has occurred. #1 MOF Monotonic Overflow Flag 3 1 read-only 0 Monotonic counter overflow has not occurred. #0 1 Monotonic counter overflow has occurred and monotonic counter is read as zero. #1 TCE Time Counter Enable 4 1 read-write 0 Time counter is disabled. #0 1 Time counter is enabled. #1 LR RTC Lock Register 0x18 32 read-write 0xFFFF 0xFFFFFFFF TCL Time Compensation Lock 3 1 read-write 0 Time Compensation Register is locked and writes are ignored. #0 1 Time Compensation Register is not locked and writes complete as normal. #1 CRL Control Register Lock 4 1 read-write 0 Control Register is locked and writes are ignored. #0 1 Control Register is not locked and writes complete as normal. #1 SRL Status Register Lock 5 1 read-write 0 Status Register is locked and writes are ignored. #0 1 Status Register is not locked and writes complete as normal. #1 LRL Lock Register Lock 6 1 read-write 0 Lock Register is locked and writes are ignored. #0 1 Lock Register is not locked and writes complete as normal. #1 TTSL Tamper Time Seconds Lock 8 1 read-write 0 Tamper Time Seconds Register is locked and writes are ignored. #0 1 Tamper Time Seconds Register is not locked and writes complete as normal. #1 MEL Monotonic Enable Lock 9 1 read-write 0 Monotonic Enable Register is locked and writes are ignored. #0 1 Monotonic Enable Register is not locked and writes complete as normal. #1 MCLL Monotonic Counter Low Lock 10 1 read-write 0 Monotonic Counter Low Register is locked and writes are ignored. #0 1 Monotonic Counter Low Register is not locked and writes complete as normal. #1 MCHL Monotonic Counter High Lock 11 1 read-write 0 Monotonic Counter High Register is locked and writes are ignored. #0 1 Monotonic Counter High Register is not locked and writes complete as normal. #1 TEL Tamper Enable Lock 12 1 read-write 0 Tamper Enable Register is locked and writes are ignored. #0 1 Tamper Enable Register is not locked and writes complete as normal. #1 TDL Tamper Detect Lock 13 1 read-write 0 Tamper Detect Register is locked and writes are ignored. #0 1 Tamper Detect Register is not locked and writes complete as normal. #1 TTL Tamper Trim Lock 14 1 read-write 0 Tamper Trim Register is locked and writes are ignored. #0 1 Tamper Trim Register is not locked and writes complete as normal. #1 TIL Tamper Interrupt Lock 15 1 read-write 0 Tamper Interrupt Register is locked and writes are ignored. #0 1 Tamper Interrupt Register is not locked and writes complete as normal. #1 IER RTC Interrupt Enable Register 0x1C 32 read-write 0x7 0xFFFFFFFF TIIE Time Invalid Interrupt Enable 0 1 read-write 0 Time invalid flag does not generate an interrupt. #0 1 Time invalid flag does generate an interrupt. #1 TOIE Time Overflow Interrupt Enable 1 1 read-write 0 Time overflow flag does not generate an interrupt. #0 1 Time overflow flag does generate an interrupt. #1 TAIE Time Alarm Interrupt Enable 2 1 read-write 0 Time alarm flag does not generate an interrupt. #0 1 Time alarm flag does generate an interrupt. #1 MOIE Monotonic Overflow Interrupt Enable 3 1 read-write 0 Monotonic overflow flag does not generate an interrupt. #0 1 Monotonic overflow flag does generate an interrupt. #1 TSIE Time Seconds Interrupt Enable 4 1 read-write 0 Seconds interrupt is disabled. #0 1 Seconds interrupt is enabled. #1 WPON Wakeup Pin On 7 1 read-write 0 No effect. #0 1 If the wakeup pin is enabled, then the wakeup pin will assert. #1 TTSR RTC Tamper Time Seconds Register 0x20 32 read-only 0 0 TTS Tamper Time Seconds 0 32 read-only MER RTC Monotonic Enable Register 0x24 32 read-write 0 0xFFFFFFFF MCE Monotonic Counter Enable 4 1 read-write 0 Writes to the monotonic counter load the counter with the value written. #0 1 Writes to the monotonic counter increment the counter. #1 MCLR RTC Monotonic Counter Low Register 0x28 32 read-write 0 0xFFFFFFFF MCL Monotonic Counter Low 0 32 read-write MCHR RTC Monotonic Counter High Register 0x2C 32 read-write 0 0xFFFFFFFF MCH Monotonic Counter High 0 32 read-write TER RTC Tamper Enable Register 0x30 32 read-write 0 0xFFFFFFFF VTE Voltage Tamper Enable 1 1 read-write 0 Tamper source disabled. #0 1 Set the time invalid flag if the voltage tamper flag is set. #1 CTE Clock Tamper Enable 2 1 read-write 0 Tamper source disabled. #0 1 Set the time invalid flag if the clock tamper flag is set. #1 TTE Temperature Tamper Enable 3 1 read-write 0 Tamper source disabled. #0 1 Set the time invalid flag if the temperature tamper flag is set. #1 FSE Flash Security Enable 4 1 read-write 0 Tamper source disabled. #0 1 Set the time invalid flag if the flash security flag is set. #1 TME Test Mode Enable 5 1 read-write 0 Tamper source disabled. #0 1 Set the time invalid flag if the test mode flag is set. #1 TDR RTC Tamper Detect Register 0x34 32 read-write 0x1 0xFFFFFFFF VTF Voltage Tamper Flag 1 1 read-write 0 Tamper not detected. #0 1 Voltage tampering detected. #1 CTF Clock Tamper Flag 2 1 read-write 0 Tamper not detected. #0 1 Clock tampering detected. #1 TTF Temperature Tamper Flag 3 1 read-write 0 Tamper not detected. #0 1 Temperature tampering detected. #1 FSF Flash Security Flag 4 1 read-write 0 Tamper not detected. #0 1 Flash security tamper detected. #1 TMF Test Mode Flag 5 1 read-write 0 Tamper not detected. #0 1 Test mode tamper detected. #1 TTR RTC Tamper Trim Register 0x38 32 read-write 0 0xFFFFFFFF VDTH Voltage Detect Trim High 0 3 read-write VDTL Voltage Detect Trim Low 3 3 read-write CDTL Clock Detect Trim Low 6 3 read-write CDTH Clock Detect Trim High 9 3 read-write TDTL Temperature Detect Trim Low 12 5 read-write TDTH Temperature Detect Trim High 17 5 read-write TIR RTC Tamper Interrupt Register 0x3C 32 read-write 0 0xFFFFFFFF VTIE Voltage Tamper Interrupt Enable 1 1 read-write 0 Interupt disabled. #0 1 An interrupt is generated when the voltage tamper flag is set. #1 CTIE Clock Tamper Interrupt Enable 2 1 read-write 0 Interupt disabled. #0 1 An interrupt is generated when the clock tamper flag is set. #1 TTIE Temperature Tamper Interrupt Enable 3 1 read-write 0 Interupt disabled. #0 1 An interrupt is generated when the temperature tamper flag is set. #1 FSIE Flash Security Interrupt Enable 4 1 read-write 0 Interupt disabled. #0 1 An interrupt is generated when the flash security flag is set. #1 TMIE Test Mode Interrupt Enable 5 1 read-write 0 Interupt disabled. #0 1 An interrupt is generated when the test mode flag is set. #1 WAR RTC Write Access Register 0x800 32 read-write 0xFFFF 0xFFFFFFFF TSRW Time Seconds Register Write 0 1 read-write 0 Writes to the Time Seconds Register are ignored. #0 1 Writes to the Time Seconds Register complete as normal. #1 TPRW Time Prescaler Register Write 1 1 read-write 0 Writes to the Time Prescaler Register are ignored. #0 1 Writes to the Time Prescaler Register complete as normal. #1 TARW Time Alarm Register Write 2 1 read-write 0 Writes to the Time Alarm Register are ignored. #0 1 Writes to the Time Alarm Register complete as normal. #1 TCRW Time Compensation Register Write 3 1 read-write 0 Writes to the Time Compensation Register are ignored. #0 1 Writes to the Time Compensation Register complete as normal. #1 CRW Control Register Write 4 1 read-write 0 Writes to the Control Register are ignored. #0 1 Writes to the Control Register complete as normal. #1 SRW Status Register Write 5 1 read-write 0 Writes to the Status Register are ignored. #0 1 Writes to the Status Register complete as normal. #1 LRW Lock Register Write 6 1 read-write 0 Writes to the Lock Register are ignored. #0 1 Writes to the Lock Register complete as normal. #1 IERW Interrupt Enable Register Write 7 1 read-write 0 Writes to the Interupt Enable Register are ignored. #0 1 Writes to the Interrupt Enable Register complete as normal. #1 TTSW Tamper Time Seconds Write 8 1 read-write 0 Writes to the Tamper Time Seconds Register are ignored. #0 1 Writes to the Tamper Time Seconds Register complete as normal. #1 MERW Monotonic Enable Register Write 9 1 read-write 0 Writes to the Monotonic Enable Register are ignored. #0 1 Writes to the Monotonic Enable Register complete as normal. #1 MCLW Monotonic Counter Low Write 10 1 read-write 0 Writes to the Monotonic Counter Low Register are ignored. #0 1 Writes to the Monotonic Counter Low Register complete as normal. #1 MCHW Monotonic Counter High Write 11 1 read-write 0 Writes to the Monotonic Counter High Register are ignored. #0 1 Writes to the Monotonic Counter High Register complete as normal. #1 TERW Tamper Enable Register Write 12 1 read-write 0 Writes to the Tamper Enable Register are ignored. #0 1 Writes to the Tamper Enable Register complete as normal. #1 TDRW Tamper Detect Register Write 13 1 read-write 0 Writes to the Tamper Detect Register are ignored. #0 1 Writes to the Tamper Detect Register complete as normal. #1 TTRW Tamper Trim Register Write 14 1 read-write 0 Writes to the Tamper Trim Register are ignored. #0 1 Writes to the Tamper Trim Register complete as normal. #1 TIRW Tamper Interrupt Register Write 15 1 read-write 0 Writes to the Tamper Interrupt Register are ignored. #0 1 Writes to the Tamper Interrupt Register complete as normal. #1 RAR RTC Read Access Register 0x804 32 read-write 0xFFFF 0xFFFFFFFF TSRR Time Seconds Register Read 0 1 read-write 0 Reads to the Time Seconds Register are ignored. #0 1 Reads to the Time Seconds Register complete as normal. #1 TPRR Time Prescaler Register Read 1 1 read-write 0 Reads to the Time Pprescaler Register are ignored. #0 1 Reads to the Time Prescaler Register complete as normal. #1 TARR Time Alarm Register Read 2 1 read-write 0 Reads to the Time Alarm Register are ignored. #0 1 Reads to the Time Alarm Register complete as normal. #1 TCRR Time Compensation Register Read 3 1 read-write 0 Reads to the Time Compensation Register are ignored. #0 1 Reads to the Time Compensation Register complete as normal. #1 CRR Control Register Read 4 1 read-write 0 Reads to the Control Register are ignored. #0 1 Reads to the Control Register complete as normal. #1 SRR Status Register Read 5 1 read-write 0 Reads to the Status Register are ignored. #0 1 Reads to the Status Register complete as normal. #1 LRR Lock Register Read 6 1 read-write 0 Reads to the Lock Register are ignored. #0 1 Reads to the Lock Register complete as normal. #1 IERR Interrupt Enable Register Read 7 1 read-write 0 Reads to the Interrupt Enable Register are ignored. #0 1 Reads to the Interrupt Enable Register complete as normal. #1 TTSR Tamper Time Seconds Read 8 1 read-write 0 Reads to the Tamper Time Seconds Register are ignored. #0 1 Reads to the Tamper Time Seconds Register complete as normal. #1 MERR Monotonic Enable Register Read 9 1 read-write 0 Reads to the Monotonic Enable Register are ignored. #0 1 Reads to the Monotonic Enable Register complete as normal. #1 MCLR Monotonic Counter Low Read 10 1 read-write 0 Reads to the Monotonic Counter Low Register are ignored. #0 1 Reads to the Monotonic Counter Low Register complete as normal. #1 MCHR Monotonic Counter High Read 11 1 read-write 0 Reads to the Monotonic Counter High Register are ignored. #0 1 Reads to the Monotonic Counter High Register complete as normal. #1 TERR Tamper Enable Register Read 12 1 read-write 0 Reads to the Tamper Enable Register are ignored. #0 1 Reads to the Tamper Enable Register complete as normal. #1 TDRR Tamper Detect Register Read 13 1 read-write 0 Reads to the Tamper Detect Register are ignored. #0 1 Reads to the Tamper Detect Register complete as normal. #1 TTRR Tamper Trim Register Read 14 1 read-write 0 Reads to the Tamper Trim Register are ignored. #0 1 Reads to the Tamper Trim Register complete as normal. #1 TIRR Tamper Interrupt Register Read 15 1 read-write 0 Reads to the Tamper Interrupt Register are ignored. #0 1 Reads to the Tamper Interrupt Register complete as normal. #1 RFVBAT VBAT register file RFVBAT_ 0x4003E000 0 0x20 registers 8 0x4 0,1,2,3,4,5,6,7 REG%s VBAT register file register 0 32 read-write 0 0xFFFFFFFF LL Low lower byte 0 8 read-write LH Low higher byte 8 8 read-write HL High lower byte 16 8 read-write HH High higher byte 24 8 read-write LPTMR0 Low Power Timer LPTMR LPTMR0_ 0x40040000 0 0x10 registers LPTMR0_LPTMR1 58 CSR Low Power Timer Control Status Register 0 32 read-write 0 0xFFFFFFFF TEN Timer Enable 0 1 read-write 0 LPTMR is disabled and internal logic is reset. #0 1 LPTMR is enabled. #1 TMS Timer Mode Select 1 1 read-write 0 Time Counter mode. #0 1 Pulse Counter mode. #1 TFC Timer Free-Running Counter 2 1 read-write 0 CNR is reset whenever TCF is set. #0 1 CNR is reset on overflow. #1 TPP Timer Pin Polarity 3 1 read-write 0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. #0 1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. #1 TPS Timer Pin Select 4 2 read-write 00 Pulse counter input 0 is selected. #00 01 Pulse counter input 1 is selected. #01 10 Pulse counter input 2 is selected. #10 11 Pulse counter input 3 is selected. #11 TIE Timer Interrupt Enable 6 1 read-write 0 Timer interrupt disabled. #0 1 Timer interrupt enabled. #1 TCF Timer Compare Flag 7 1 read-write 0 The value of CNR is not equal to CMR and increments. #0 1 The value of CNR is equal to CMR and increments. #1 PSR Low Power Timer Prescale Register 0x4 32 read-write 0 0xFFFFFFFF PCS Prescaler Clock Select 0 2 read-write 00 Prescaler/glitch filter clock 0 selected. #00 01 Prescaler/glitch filter clock 1 selected. #01 10 Prescaler/glitch filter clock 2 selected. #10 11 Prescaler/glitch filter clock 3 selected. #11 PBYP Prescaler Bypass 2 1 read-write 0 Prescaler/glitch filter is enabled. #0 1 Prescaler/glitch filter is bypassed. #1 PRESCALE Prescale Value 3 4 read-write 0000 Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. #0000 0001 Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. #0001 0010 Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. #0010 0011 Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. #0011 0100 Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. #0100 0101 Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. #0101 0110 Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. #0110 0111 Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. #0111 1000 Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. #1000 1001 Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. #1001 1010 Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. #1010 1011 Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. #1011 1100 Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. #1100 1101 Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. #1101 1110 Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. #1110 1111 Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. #1111 CMR Low Power Timer Compare Register 0x8 32 read-write 0 0xFFFFFFFF COMPARE Compare Value 0 16 read-write CNR Low Power Timer Counter Register 0xC 32 read-write 0 0xFFFFFFFF COUNTER Counter Value 0 16 read-write LPTMR1 Low Power Timer LPTMR LPTMR1_ 0x40044000 0 0x10 registers LPTMR0_LPTMR1 58 CSR Low Power Timer Control Status Register 0 32 read-write 0 0xFFFFFFFF TEN Timer Enable 0 1 read-write 0 LPTMR is disabled and internal logic is reset. #0 1 LPTMR is enabled. #1 TMS Timer Mode Select 1 1 read-write 0 Time Counter mode. #0 1 Pulse Counter mode. #1 TFC Timer Free-Running Counter 2 1 read-write 0 CNR is reset whenever TCF is set. #0 1 CNR is reset on overflow. #1 TPP Timer Pin Polarity 3 1 read-write 0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. #0 1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. #1 TPS Timer Pin Select 4 2 read-write 00 Pulse counter input 0 is selected. #00 01 Pulse counter input 1 is selected. #01 10 Pulse counter input 2 is selected. #10 11 Pulse counter input 3 is selected. #11 TIE Timer Interrupt Enable 6 1 read-write 0 Timer interrupt disabled. #0 1 Timer interrupt enabled. #1 TCF Timer Compare Flag 7 1 read-write 0 The value of CNR is not equal to CMR and increments. #0 1 The value of CNR is equal to CMR and increments. #1 PSR Low Power Timer Prescale Register 0x4 32 read-write 0 0xFFFFFFFF PCS Prescaler Clock Select 0 2 read-write 00 Prescaler/glitch filter clock 0 selected. #00 01 Prescaler/glitch filter clock 1 selected. #01 10 Prescaler/glitch filter clock 2 selected. #10 11 Prescaler/glitch filter clock 3 selected. #11 PBYP Prescaler Bypass 2 1 read-write 0 Prescaler/glitch filter is enabled. #0 1 Prescaler/glitch filter is bypassed. #1 PRESCALE Prescale Value 3 4 read-write 0000 Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. #0000 0001 Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. #0001 0010 Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. #0010 0011 Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. #0011 0100 Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. #0100 0101 Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. #0101 0110 Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. #0110 0111 Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. #0111 1000 Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. #1000 1001 Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. #1001 1010 Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. #1010 1011 Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. #1011 1100 Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. #1100 1101 Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. #1101 1110 Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. #1110 1111 Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. #1111 CMR Low Power Timer Compare Register 0x8 32 read-write 0 0xFFFFFFFF COMPARE Compare Value 0 16 read-write CNR Low Power Timer Counter Register 0xC 32 read-write 0 0xFFFFFFFF COUNTER Counter Value 0 16 read-write RFSYS System register file RFSYS_ 0x40041000 0 0x20 registers 8 0x4 0,1,2,3,4,5,6,7 REG%s Register file register 0 32 read-write 0 0xFFFFFFFF LL Low lower byte 0 8 read-write LH Low higher byte 8 8 read-write HL High lower byte 16 8 read-write HH High higher byte 24 8 read-write DRY Tamper Detect and Secure Key Storage DRY_ 0x40042000 0x4 0x1804 registers Tamper 55 SKVR DryIce Secure Key Valid Register 0x4 32 read-write 0 0xFFFFFFFF SKV Secure Key Valid 0 8 read-write 0 Corresponding Secure Key Register has not been initialized since last invalidation, tamper or reset. #0 1 Corresponding Secure Key Register has been initialized since last invalidation, tamper or reset. #1 SKWLR DryIce Secure Key Write Lock Register 0x8 32 read-write 0xFF 0xFFFFFFFF SKWL Secure Key Write Lock 0 8 read-write 0 Corresponding Secure Key Register is locked and cannot be written by software. #0 1 Corresponding Secure Key Register can be written by software. #1 SKRLR DryIce Secure Key Read Lock Register 0xC 32 read-write 0xFF 0xFFFFFFFF SKRL Secure Key Read Lock 0 8 read-write 0 Corresponding Secure Key Register is locked and cannot be read by software. #0 1 Corresponding Secure Key Register can be read by software. #1 CR DryIce Control Register 0x10 32 read-write 0 0xFFFFFFFF SWR Software Reset 0 1 read-write 0 No effect. #0 1 Perform a software reset. #1 DEN DryIce Enable 1 1 read-write 0 DryIce clock and prescaler are disabled. #0 1 DryIce clock and prescaler are enabled. #1 TFSR Tamper Force System Reset 2 1 read-write 0 Do not force chip reset when tampering is detected. #0 1 Force chip reset when tampering is detected. #1 UM Update Mode 3 1 read-write 0 DryIce Status Register cannot be written when the Status Register Lock bit within the Lock Register (LR[SRL]) is clear. #0 1 DryIce Status Register cannot be written when the Status Register Lock bit within the Lock Register (LR[SRL]) is clear and DryIce Tamper Flag (SR[DTF]) is set. #1 ATCS Active Tamper Clock Source 4 2 read-write 0 Active Tamper Shift Register clocked by 1 Hz prescaler clock. #00 1 Active Tamper Shift Register clocked by 512 Hz prescaler clock. #01 THYS Tamper Hysteresis Select 8 1 read-write 0 Hysteresis is set to a range of 305 mV to 440 mV. #0 1 Hysteresis is set to a range of 490 mV to 705 mV. #1 TPFE Tamper Passive Filter Enable 9 1 read-write 0 Tamper pins are configured with passive input filter disabled #0 1 Tamper pins are configured with passive input filter enabled #1 TDSE Tamper Drive Strength Enable 10 1 read-write 0 Tamper pins are configured for low drive strength #0 1 Tamper pins are configured for high drive strength #1 TSRE Tamper Slew Rate Enable 11 1 read-write 0 Tamper pins are configured for slow slew rate. #0 1 Tamper pins are configured for fast slew rate. #1 SRF Secure Register File 14 2 read-write 00 VBAT Register File is a general purpose register file, it is reset on VBAT POR only and can be accessed by supervisor or non-supervisor software. #00 10 VBAT Register File is a secure register file that is reset when DryIce Tamper Flag is set. It can only be accessed by software in supervisor mode. #10 11 VBAT Register File is a secure register file that is reset when DryIce Tamper Flag is set or the DryIce Interrupt asserts. It can only be accessed by software in supervisor mode. #11 DPR DryIce Prescaler Register 17 15 read-write SR DryIce Status Register 0x14 32 read-write 0x1 0xFFFFFFFF DTF DryIce Tamper Flag 0 1 read-write 0 DryIce tampering not detected. #0 1 DryIce tampering detected. #1 TAF Tamper Acknowledge Flag 1 1 read-write 0 DryIce Tamper Flag (SR[DTF]) is clear or chip reset has not occurred after DryIce Tamper Flag (SR[DTF]) was set. #0 1 Chip reset has occurred after DryIce Tamper Flag (SR[DTF]) was set. #1 TOF Time Overflow Flag 2 1 read-write 0 Tamper not detected. #0 1 RTC time overflow tamper detected. #1 MOF Monotonic Overflow Flag 3 1 read-write 0 Tamper not detected. #0 1 RTC monotonic overflow tamper detected. #1 VTF Voltage Tamper Flag 4 1 read-write 0 Tamper not detected. #0 1 Voltage tampering detected. #1 CTF Clock Tamper Flag 5 1 read-write 0 Tamper not detected. #0 1 Clock tampering detected. #1 TTF Temperature Tamper Flag 6 1 read-write 0 Tamper not detected. #0 1 Temperature tampering detected. #1 STF Security Tamper Flag 7 1 read-write 0 Tamper not detected. #0 1 Security module tamper detected. #1 FSF Flash Security Flag 8 1 read-write 0 Tamper not detected. #0 1 Flash security tamper detected. #1 TMF Test Mode Flag 9 1 read-write 0 Tamper not detected. #0 1 Test mode tamper detected. #1 TPF Tamper Pin Flag 16 8 read-write 0 Tamper not detected. #0 1 Tamper pin tamper detected. #1 LR DryIce Lock Register 0x18 32 read-write 0xFF3FFF 0xFFFFFFFF KVL Key Valid Lock 1 1 read-write 0 Secure key valid register is locked and writes are ignored. #0 1 Secure key valid register is not locked and writes complete as normal. #1 KWL Key Write Lock 2 1 read-write 0 Secure Key Write Lock Register is locked and writes are ignored. #0 1 Secure Key Write Lock Register is not locked and writes complete as normal. #1 KRL Key Read Lock 3 1 read-write 0 Secure Key Read Lock Register is locked and writes are ignored. #0 1 Secure Key Read Lock Register is not locked and writes complete as normal. #1 CRL Control Register Lock 4 1 read-write 0 Control register is locked and writes are ignored. #0 1 Control register is not locked and writes complete as normal. #1 SRL Status Register Lock 5 1 read-write 0 Status Register is locked and writes are ignored. #0 1 Status Register is not locked and writes complete as normal. #1 LRL Lock Register Lock 6 1 read-write 0 Lock register is locked and writes are ignored. #0 1 Lock register is not locked and writes complete as normal. #1 IEL Interrupt Enable Lock 7 1 read-write 0 Interrupt enable register is locked and writes are ignored. #0 1 Interrupt enable register is not locked and writes complete as normal. #1 TSL Tamper Seconds Lock 8 1 read-write 0 Tamper seconds register is locked and writes are ignored. #0 1 Tamper seconds register is not locked and writes complete as normal. #1 TEL Tamper Enable Lock 9 1 read-write 0 Tamper enable register is locked and writes are ignored. #0 1 Tamper enable register is not locked and writes complete as normal. #1 PDL Pin Direction Lock 10 1 read-write 0 Pin direction register is locked and writes are ignored. #0 1 Pin direction register is not locked and writes complete as normal. #1 PPL Pin Polarity Lock 11 1 read-write 0 Pin polarity register is locked and writes are ignored. #0 1 Pin polarity register is not locked and writes complete as normal. #1 ATL Active Tamper Lock 12 2 read-write 0 Active tamper register is locked and writes are ignored. #00 1 Active tamper register is not locked and writes complete as normal. #01 GFL Glitch Filter Lock 16 8 read-write 0 Pin glitch filter register is locked and writes are ignored. #0 1 Pin glitch filter register is not locked and writes complete as normal. #1 IER DryIce Interrupt Enable Register 0x1C 32 read-write 0x1 0xFFFFFFFF DTIE DryIce Tamper Interrupt Enable 0 1 read-write 0 When DryIce Tamper Flag (SR[DTF]) is set, an interrupt is not generated. #0 1 When DryIce Tamper Flag (SR[DTF]) is set, an interrupt is generated. #1 TOIE Time Overflow Interrupt Enable 2 1 read-write 0 When time overflow flag is set, an interrupt is not generated. #0 1 When time overflow flag is set, an interrupt is generated. #1 MOIE Monotonic Overflow Interrupt Enable 3 1 read-write 0 When monotonic overflow flag is set, an interrupt is not generated. #0 1 When monotonic overflow flag is set, an interrupt is generated. #1 VTIE Voltage Tamper Interrupt Enable 4 1 read-write 0 When voltage tamper flag is set, an interrupt is not generated. #0 1 When voltage tamper flag is set, an interrupt is generated. #1 CTIE Clock Tamper Interrupt Enable 5 1 read-write 0 When clock tamper flag is set, an interrupt is not generated. #0 1 When clock tamper flag is set, an interrupt is generated. #1 TTIE Temperature Tamper Interrupt Enable 6 1 read-write 0 When temperature tamper flag is set, an interrupt is not generated. #0 1 When temperature tamper flag is set, an interrupt is generated. #1 STIE Security Tamper Interrupt Enable 7 1 read-write 0 When security tamper flag is set, an interrupt is not generated. #0 1 When security tamper flag is set, an interrupt is generated. #1 FSIE Flash Security Interrupt Enable 8 1 read-write 0 When flash security flag is set, an interrupt is not generated. #0 1 When flash security flag is set, an interrupt is generated. #1 TMIE Test Mode Interrupt Enable 9 1 read-write 0 When test mode flag is set, an interrupt is not generated. #0 1 When test mode flag is set, an interrupt is generated. #1 TPIE Tamper Pin Interrupt Enable 16 8 read-write 0 When corresponding tamper pin flag is set, an interrupt is not generated. #0 1 When corresponding tamper pin flag is set, an interrupt is generated. #1 TSR DryIce Tamper Seconds Register 0x20 32 read-write 0 0xFFFFFFFF TTS Tamper Time Seconds 0 32 read-write TER DryIce Tamper Enable Register 0x24 32 read-write 0 0xFFFFFFFF TOE Time Overflow Enable 2 1 read-write 0 When time overflow flag is set, tampering is not detected. #0 1 When time overflow flag is set, tampering is detected. #1 MOE Monotonic Overflow Enable 3 1 read-write 0 When monotonic overflow flag is set, tampering is not detected. #0 1 When monotonic overflow flag is set, tampering is detected. #1 VTE Voltage Tamper Enable 4 1 read-write 0 When voltage tamper flag is set, tampering is not detected. #0 1 When voltage tamper flag is set, tampering is detected. #1 CTE Clock Tamper Enable 5 1 read-write 0 When clock tamper flag is set, tampering is not detected. #0 1 When clock tamper flag is set, tampering is detected. #1 TTE Temperature Tamper Enable 6 1 read-write 0 When temperature tamper flag is set, tampering is not detected. #0 1 When temperature tamper flag is set, tampering is detected. #1 STE Security Tamper Enable 7 1 read-write 0 When security tamper flag is set, tampering is not detected. #0 1 When security tamper flag is set, tampering is detected. #1 FSE Flash Security Enable 8 1 read-write 0 When flash security flag is set, tampering is not detected. #0 1 When flash security flag is set, tampering is detected. #1 TME Test Mode Enable 9 1 read-write 0 When test mode flag is set, tampering is not detected. #0 1 When test mode flag is set, tampering is detected. #1 TPE Tamper Pin Enable 16 8 read-write 0 When corresponding tamper pin flag is set, tampering is not detected. #0 1 When corresponding tamper pin flag is set, tampering is detected. #1 PDR DryIce Pin Direction Register 0x28 32 read-write 0xFF0000 0xFFFFFFFF TPD Tamper Pin Direction 0 8 read-write 0 Tamper pin is input #0 1 Tamper pin is output and drives inverse of expected value (tamper pin is asserted) #1 TPOD Tamper Pin Output Data 16 8 read-only 0 Tamper pin output data is logic zero. #0 1 Tamper pin output data is logic one. #1 PPR DryIce Pin Polarity Register 0x2C 32 read-write 0 0xFFFFFFFF TPP Tamper Pin Polarity 0 8 read-write 0 Tamper pin expected value is not inverted. #0 1 Tamper pin expected value is inverted. #1 TPID Tamper Pin Input Data 16 8 read-only 0 Tamper pin input data (before glitch filter) is logic zero. #0 1 Tamper pin input data (before glitch filter) is logic one. #1 2 0x4 0,1 ATR%s DryIce Active Tamper Register 0x30 32 read-write 0 0xFFFFFFFF ATSR Active Tamper Shift Register 0 16 read-write ATP Active Tamper Polynomial 16 16 read-write 8 0x4 0,1,2,3,4,5,6,7 PGFR%s DryIce Pin Glitch Filter Register 0x40 32 read-write 0 0xFFFFFFFF GFW Glitch Filter Width 0 6 read-write GFP Glitch Filter Prescaler 6 1 read-write 0 The glitch filter on tamper pin is clocked by the 512 Hz prescaler clock. #0 1 The glitch filter on tamper pin is clocked by the 32.768 kHz clock. #1 GFE Glitch Filter Enable 7 1 read-write 0 The glitch filter on tamper pin is bypassed. #0 1 The glitch filter on tamper pin is enabled. #1 TPSW Tamper Pin Sample Width 8 2 read-write 00 Tamper Pin Sampling is disabled. #00 01 Tamper Pin Sample Width is 2 cycles for pull enable and 1 cycle for input buffer enable. #01 10 Tamper Pin Sample Width is 4 cycles for pull enable and 2 cycles for input buffer enable. #10 11 Tamper Pin Sample Width is 8 cycles for pull enable and 4 cycles for input buffer enable. #11 TPSF Tamper Pin Sample Frequency 10 2 read-write 00 Tamper Pin Sample Frequency is once every 8 cycles #00 01 Tamper Pin Sample Frequency is once every 32 cycles #01 10 Tamper Pin Sample Frequency is once every 128 cycles #10 11 Tamper Pin Sample Frequency is once every 512 cycles #11 TPEX Tamper Pin Expected 16 2 read-write 00 Tamper pin expected value is logic zero. #00 01 Tamper pin expected value is active tamper 0 output. #01 10 Tamper pin expected value is active tamper 1 output. #10 11 Tamper pin 0 expected value is active tamper 0 output XORed with active tamper 1 output. #11 TPE Tamper Pull Enable 24 1 read-write 0 Pull resistor is disabled on tamper pin. #0 1 Pull resistor is enabled on tamper pin. #1 TPS Tamper Pull Select 25 1 read-write 0 Tamper pin pull direction will always assert the tamper pin. #0 1 Tamper pin pull direction will always negate the tamper pin. #1 WAC DryIce Write Access Control Register 0x800 32 read-write 0xFF3FFF 0xFFFFFFFF SKVW Secure Key Valid Write 1 1 read-write 0 Writes to the secure key valid register are ignored. #0 1 Writes to the secure key valid register complete as normal. #1 SKWRW Secure Key Write Lock Register Write 2 1 read-write 0 Writes to the Secure Key Write Lock Register are ignored. #0 1 Writes to the Secure Key Write Lock Register complete as normal. #1 SKRRW Secure Key Read Lock Register Write 3 1 read-write 0 Writes to the Secure Key Read Lock Register are ignored. #0 1 Writes to the Secure Key Read Lock Register complete as normal. #1 CRW Control Register Write 4 1 read-write 0 Writes to the Control register are ignored. #0 1 Writes to the Control register complete as normal. #1 SRW Status Register Write 5 1 read-write 0 Writes to the Status Register are ignored. #0 1 Writes to the Status Register complete as normal. #1 LRW Lock Register Write 6 1 read-write 0 Writes to the Lock register are ignored. #0 1 Writes to the Lock register complete as normal. #1 IEW Interrupt Enable Write 7 1 read-write 0 Writes to the Interrupt enable register are ignored. #0 1 Writes to the Interrupt enable register complete as normal. #1 TSRW Tamper Seconds Register Write 8 1 read-write 0 Writes to the Tamper Seconds register are ignored. #0 1 Writes to the Tamper Seconds register complete as normal. #1 TEW Tamper Enable Write 9 1 read-write 0 Writes to the tamper enable register are ignored. #0 1 Writes to the tamper enable register complete as normal. #1 PDW Pin Direction Write 10 1 read-write 0 Writes to the pin direction register are ignored. #0 1 Writes to the pin direction register complete as normal. #1 PPW Pin Polarity Write 11 1 read-write 0 Writes to the pin polarity register are ignored. #0 1 Writes to the pin polarity register complete as normal. #1 ATW Active Tamper Write 12 2 read-write 0 Writes to the active tamper register are ignored. #00 1 Writes to the active tamper register complete as normal. #01 GFW Glitch Filter Write 16 8 read-write 0 Writes to the pin glitch filter register are ignored. #0 1 Writes to the pin glitch filter register complete as normal. #1 RAC DryIce Read Access Control Register 0x804 32 read-write 0xFF3FFF 0xFFFFFFFF SKVR Secure Key Valid Read 1 1 read-write 0 Reads to the secure key valid register are ignored. #0 1 Reads to the secure key valid register complete as normal. #1 SKWRR Secure Key Write Lock Register Read 2 1 read-write 0 Reads to the Secure Key Write Lock Register are ignored. #0 1 Reads to the Secure Key Write Lock Register complete as normal. #1 SKRRR Secure Key Read Lock Register Read 3 1 read-write 0 Reads to the Secure Key Read Lock Register are ignored. #0 1 Reads to the Secure Key Read Lock Register complete as normal. #1 CRR Control Register Read 4 1 read-write 0 Reads to the Control register are ignored. #0 1 Reads to the Control register complete as normal. #1 SRR Status Register Read 5 1 read-write 0 Reads to the Status Register are ignored. #0 1 Reads to the Status Register complete as normal. #1 LRR Lock Register Read 6 1 read-write 0 Reads to the Lock register are ignored. #0 1 Reads to the Lock register complete as normal. #1 IER Interrupt Enable Read 7 1 read-write 0 Reads to the Interrupt enable register are ignored. #0 1 Reads to the Interrupt enable register complete as normal. #1 TSRR Tamper Seconds Register Read 8 1 read-write 0 Reads to the tamper seconds register are ignored. #0 1 Reads to the tamper seconds register complete as normal. #1 TER Tamper Enable Read 9 1 read-write 0 Reads to the tamper enable register are ignored. #0 1 Reads to the tamper enable register complete as normal. #1 PDR Pin Direction Read 10 1 read-write 0 Reads to the pin direction register are ignored. #0 1 Reads to the pin direction register complete as normal. #1 PPR Pin Polarity Read 11 1 read-write 0 Reads to the pin polarity register are ignored. #0 1 Reads to the pin polarity register complete as normal. #1 ATR Active Tamper Read 12 2 read-write 0 Reads to the active tamper register are ignored. #00 1 Reads to the active tamper register complete as normal. #01 GFR Glitch Filter Read 16 8 read-write 0 Reads to the pin glitch filter register are ignored. #0 1 Reads to the pin glitch filter register complete as normal. #1 8 0x4 0,1,2,3,4,5,6,7 SKR%s Secure Key Register 0x1000 32 read-write 0 0xFFFFFFFF SK Secure Key 0 32 read-write SWAC Secure Write Access Control 0x1800 32 read-write 0xFF 0xFFFFFFFF SKRW Secure Key Register Write 0 8 read-write 0 Writes to the corresponding Secure Key Register are ignored. #0 1 Writes to the correspondingSecure Key Register complete as normal. #1 SRAC Secure Read Access Control 0x1804 32 read-write 0xFF 0xFFFFFFFF SKRR Secure Key Register Read 0 8 read-write 0 Reads to the corresponding Secure Key Register are ignored. #0 1 Reads to the corresponding Secure Key Register complete as normal. #1 TSI0 Touch sense input TSI0_ 0x40045000 0 0xC registers TSI0 87 GENCS TSI General Control and Status Register 0 32 read-write 0 0xFFFFFFFF EOSDMEO End-of-Scan DMA Transfer Request Enable Only 0 1 read-write 0 Do not enable the End-of-Scan DMA transfer request only. Depending on ESOR state, either Out-of-Range or End-of-Scan can trigger a DMA transfer request and interrupt. #0 1 Only the End-of-Scan event can trigger a DMA transfer request. The Out-of-Range event only and always triggers an interrupt if TSIIE is set. #1 CURSW CURSW 1 1 read-write 0 The current source pair are not swapped. #0 1 The current source pair are swapped. #1 EOSF End of Scan Flag 2 1 read-write 0 Scan not complete. #0 1 Scan complete. #1 SCNIP Scan In Progress Status 3 1 read-only 0 No scan in progress. #0 1 Scan in progress. #1 STM Scan Trigger Mode 4 1 read-write 0 Software trigger scan. #0 1 Hardware trigger scan. #1 STPE TSI STOP Enable 5 1 read-write 0 TSI is disabled when MCU goes into low power mode. #0 1 Allows TSI to continue running in all low power modes. #1 TSIIEN Touch Sensing Input Interrupt Enable 6 1 read-write 0 TSI interrupt is disabled. #0 1 TSI interrupt is enabled. #1 TSIEN Touch Sensing Input Module Enable 7 1 read-write 0 TSI module disabled. #0 1 TSI module enabled. #1 NSCN NSCN 8 5 read-write 00000 Once per electrode #00000 00001 Twice per electrode #00001 00010 3 times per electrode #00010 00011 4 times per electrode #00011 00100 5 times per electrode #00100 00101 6 times per electrode #00101 00110 7 times per electrode #00110 00111 8 times per electrode #00111 01000 9 times per electrode #01000 01001 10 times per electrode #01001 01010 11 times per electrode #01010 01011 12 times per electrode #01011 01100 13 times per electrode #01100 01101 14 times per electrode #01101 01110 15 times per electrode #01110 01111 16 times per electrode #01111 10000 17 times per electrode #10000 10001 18 times per electrode #10001 10010 19 times per electrode #10010 10011 20 times per electrode #10011 10100 21 times per electrode #10100 10101 22 times per electrode #10101 10110 23 times per electrode #10110 10111 24 times per electrode #10111 11000 25 times per electrode #11000 11001 26 times per electrode #11001 11010 27 times per electrode #11010 11011 28 times per electrode #11011 11100 29 times per electrode #11100 11101 30 times per electrode #11101 11110 31 times per electrode #11110 11111 32 times per electrode #11111 PS PS 13 3 read-write 000 Electrode Oscillator Frequency divided by 1 #000 001 Electrode Oscillator Frequency divided by 2 #001 010 Electrode Oscillator Frequency divided by 4 #010 011 Electrode Oscillator Frequency divided by 8 #011 100 Electrode Oscillator Frequency divided by 16 #100 101 Electrode Oscillator Frequency divided by 32 #101 110 Electrode Oscillator Frequency divided by 64 #110 111 Electrode Oscillator Frequency divided by 128 #111 EXTCHRG EXTCHRG 16 3 read-write 000 500 nA. #000 001 1 uA. #001 010 2 uA. #010 011 4 uA. #011 100 8 uA. #100 101 16 uA. #101 110 32 uA. #110 111 64 uA. #111 DVOLT DVOLT 19 2 read-write 00 DV = 1.026 V; VP = 1.328 V; Vm = 0.302 V. #00 01 DV = 0.592 V; VP = 1.111 V; Vm = 0.519 V. #01 10 DV = 0.342 V; VP = 0.986 V; Vm = 0.644 V. #10 11 DV = 0.197 V; VP = 0.914 V; Vm = 0.716 V. #11 REFCHRG REFCHRG 21 3 read-write 000 500 nA. #000 001 1 uA. #001 010 2 uA. #010 011 4 uA. #011 100 8 uA. #100 101 16 uA. #101 110 32 uA. #110 111 64 uA. #111 MODE TSI analog modes setup and status bits. 24 4 read-write 0000 Set TSI in capacitive sensing(non-noise detection) mode. #0000 0100 Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is disabled. #0100 1000 Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is enabled to work in higher frequencies operations. #1000 1100 Set TSI analog to work in automatic noise detection mode. #1100 ESOR End-of-scan or Out-of-Range Interrupt Selection 28 1 read-write 0 Out-of-range interrupt is allowed. #0 1 End-of-scan interrupt is allowed. #1 OUTRGF Out of Range Flag. 31 1 read-write DATA TSI DATA Register 0x4 32 read-write 0 0xFFFFFFFF TSICNT TSI Conversion Counter Value 0 16 read-only SWTS Software Trigger Start 22 1 write-only 0 No effect. #0 1 Start a scan to determine which channel is specified by TSI_DATA[TSICH]. #1 DMAEN DMA Transfer Enabled 23 1 read-write 0 Interrupt is selected when the interrupt enable bit is set and the corresponding TSI events assert. #0 1 DMA transfer request is selected when the interrupt enable bit is set and the corresponding TSI events assert. #1 TSICH TSICH 28 4 read-write 0000 Channel 0. #0000 0001 Channel 1. #0001 0010 Channel 2. #0010 0011 Channel 3. #0011 0100 Channel 4. #0100 0101 Channel 5. #0101 0110 Channel 6. #0110 0111 Channel 7. #0111 1000 Channel 8. #1000 1001 Channel 9. #1001 1010 Channel 10. #1010 1011 Channel 11. #1011 1100 Channel 12. #1100 1101 Channel 13. #1101 1110 Channel 14. #1110 1111 Channel 15. #1111 TSHD TSI Threshold Register 0x8 32 read-write 0 0xFFFFFFFF THRESL TSI Wakeup Channel Low-threshold 0 16 read-write THRESH TSI Wakeup Channel High-threshold 16 16 read-write SIM System Integration Module SIM_ 0x40047000 0 0x106C registers SOPT1 System Options Register 1 0 32 read-write 0x80000000 0xFFFF0FC0 RAMSIZE RAM size 12 4 read-only 0001 8 KB #0001 0011 16 KB #0011 0100 24 KB #0100 0101 32 KB #0101 0110 48 KB #0110 0111 64 KB #0111 1000 96 KB #1000 1001 128 KB #1001 1011 256 KB #1011 OSC32KSEL 32K oscillator clock select 18 2 read-write 00 System oscillator (OSC32KCLK) #00 10 RTC 32.768kHz oscillator #10 11 LPO 1 kHz #11 USBVSTBY USB voltage regulator in standby mode during VLPR and VLPW modes 29 1 read-write 0 USB voltage regulator not in standby during VLPR and VLPW modes. #0 1 USB voltage regulator in standby during VLPR and VLPW modes. #1 USBSSTBY USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes. 30 1 read-write 0 USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes. #0 1 USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes. #1 USBREGEN USB voltage regulator enable 31 1 read-write 0 USB voltage regulator is disabled. #0 1 USB voltage regulator is enabled. #1 SOPT1CFG SOPT1 Configuration Register 0x4 32 read-write 0 0xFFFFFFFF URWE USB voltage regulator enable write enable 24 1 read-write 0 SOPT1 USBREGEN cannot be written. #0 1 SOPT1 USBREGEN can be written. #1 UVSWE USB voltage regulator VLP standby write enable 25 1 read-write 0 SOPT1 USBVSTBY cannot be written. #0 1 SOPT1 USBVSTBY can be written. #1 USSWE USB voltage regulator stop standby write enable 26 1 read-write 0 SOPT1 USBSSTBY cannot be written. #0 1 SOPT1 USBSSTBY can be written. #1 SOPT2 System Options Register 2 0x1004 32 read-write 0x1000 0xFFFFFFFF RTCCLKOUTSEL RTC clock out select 4 1 read-write 0 RTC 1 Hz clock is output on the RTC_CLKOUT pin. #0 1 RTC 32.768kHz clock is output on the RTC_CLKOUT pin. #1 CLKOUTSEL CLKOUT select 5 3 read-write 000 FlexBus CLKOUT #000 010 Flash clock #010 011 LPO clock (1 kHz) #011 100 MCGIRCLK #100 101 RTC 32.768kHz clock #101 110 OSCERCLK0 #110 111 IRC 48 MHz clock #111 FBSL FlexBus security level 8 2 read-write 00 All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed. #00 01 All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed. #01 10 Off-chip instruction accesses are disallowed. Data accesses are allowed. #10 11 Off-chip instruction accesses and data accesses are allowed. #11 TRACECLKSEL Debug trace clock select 12 1 read-write 0 MCGOUTCLK, divided by the TRACECLK fractional divider as configured by SIM_CLKDIV4[TRACEFRAC, TRACEDIV] #0 1 Core/system clock #1 PLLFLLSEL PLL/FLL clock select 16 2 read-write 00 MCGFLLCLK clock #00 01 MCGPLLCLK clock #01 11 IRC48 MHz clock #11 USBSRC USB clock source select 18 1 read-write 0 External bypass clock (USB_CLKIN). #0 1 MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by SIM_CLKDIV2[USBFRAC, USBDIV]. #1 FLEXIOSRC FlexIO Module Clock Source Select 22 2 read-write 00 System clock #00 01 MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV]. #01 10 OSCERCLK clock #10 11 MCGIRCLK clock #11 TPMSRC TPM clock source select 24 2 read-write 00 Clock disabled #00 01 MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV]. #01 10 OSCERCLK clock #10 11 MCGIRCLK clock #11 LPUARTSRC LPUART clock source select 26 2 read-write 00 Clock disabled #00 01 MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV]. #01 10 OSCERCLK clock #10 11 MCGIRCLK clock #11 SDHCSRC SDHC clock source select 28 2 read-write 00 Core/system clock. #00 01 MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL]. #01 10 OSCERCLK clock #10 11 External bypass clock (SDHC0_CLKIN) #11 EMVSIMSRC EMVSIM Module Clock Source Select 30 2 read-write 00 Clock disabled #00 01 MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV]. #01 10 OSCERCLK clock #10 11 MCGIRCLK clock #11 SOPT4 System Options Register 4 0x100C 32 read-write 0 0xFFFFFFFF FTM0FLT0 FTM0 Fault 0 Select 0 1 read-write 0 FTM0_FLT0 pin #0 1 CMP0 out #1 FTM0FLT1 FTM0 Fault 1 Select 1 1 read-write 0 FTM0_FLT1 pin #0 1 CMP1 out #1 FTM1FLT0 FTM1 Fault 0 Select 4 1 read-write 0 FTM1_FLT0 pin #0 1 CMP0 out #1 FTM2FLT0 FTM2 Fault 0 Select 8 1 read-write 0 FTM2_FLT0 pin #0 1 CMP0 out #1 FTM3FLT0 FTM3 Fault 0 Select 12 1 read-write 0 FTM3_FLT0 pin #0 1 CMP0 out #1 FTM1CH0SRC FTM1 channel 0 input capture source select 18 2 read-write 00 FTM1_CH0 signal #00 01 CMP0 output #01 10 CMP1 output #10 11 USB start of frame pulse #11 FTM2CH0SRC FTM2 channel 0 input capture source select 20 2 read-write 00 FTM2_CH0 signal #00 01 CMP0 output #01 10 CMP1 output #10 FTM2CH1SRC FTM2 channel 1 input capture source select 22 1 read-write 0 FTM2_CH1 signal #0 1 Exclusive OR of FTM2_CH1, FTM2_CH0 and FTM1_CH1. #1 FTM0CLKSEL FlexTimer 0 External Clock Pin Select 24 1 read-write 0 FTM_CLK0 pin #0 1 FTM_CLK1 pin #1 FTM1CLKSEL FTM1 External Clock Pin Select 25 1 read-write 0 FTM_CLK0 pin #0 1 FTM_CLK1 pin #1 FTM2CLKSEL FlexTimer 2 External Clock Pin Select 26 1 read-write 0 FTM2 external clock driven by FTM_CLK0 pin. #0 1 FTM2 external clock driven by FTM_CLK1 pin. #1 FTM3CLKSEL FlexTimer 3 External Clock Pin Select 27 1 read-write 0 FTM3 external clock driven by FTM_CLK0 pin. #0 1 FTM3 external clock driven by FTM_CLK1 pin. #1 FTM0TRG0SRC FlexTimer 0 Hardware Trigger 0 Source Select 28 1 read-write 0 HSCMP0 output drives FTM0 hardware trigger 0 #0 1 FTM1 channel match drives FTM0 hardware trigger 0 #1 FTM0TRG1SRC FlexTimer 0 Hardware Trigger 1 Source Select 29 1 read-write 0 PDB output trigger 1 drives FTM0 hardware trigger 1 #0 1 FTM2 channel match drives FTM0 hardware trigger 1 #1 FTM3TRG0SRC FlexTimer 3 Hardware Trigger 0 Source Select 30 1 read-write 1 FTM1 channel match drives FTM3 hardware trigger 0 #1 FTM3TRG1SRC FlexTimer 3 Hardware Trigger 1 Source Select 31 1 read-write 1 FTM2 channel match drives FTM3 hardware trigger 1 #1 SOPT5 System Options Register 5 0x1010 32 read-write 0 0xFFFFFFFF LPUART0TXSRC LPUART0 transmit data source select 16 2 read-write 00 LPUART0_TX pin #00 01 LPUART0_TX pin modulated with TPM1 channel 0 output #01 10 LPUART0_TX pin modulated with TPM2 channel 0 output #10 LPUART0RXSRC LPUART0 receive data source select 18 2 read-write 00 LPUART0_RX pin #00 01 CMP0 output #01 10 CMP1 output #10 LPUART1TXSRC LPUART1 transmit data source select 20 2 read-write 00 LPUART1_TX pin #00 01 LPUART1_TX pin modulated with TPM1 channel 0 output #01 10 LPUART0_TX pin modulated with TPM2 channel 0 output #10 LPUART1RXSRC LPUART1 receive data source select 22 2 read-write 00 LPUART1_RX pin #00 01 CMP0 output #01 10 CMP1 output #10 SOPT7 System Options Register 7 0x1018 32 read-write 0 0xFFFFFFFF ADC0TRGSEL ADC0 trigger select 0 4 read-write 0000 PDB external trigger pin input (PDB0_EXTRG) #0000 0001 High speed comparator 0 output #0001 0010 High speed comparator 1 output #0010 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 0110 PIT trigger 2 #0110 0111 PIT trigger 3 #0111 1000 FTM0 trigger #1000 1001 FTM1 trigger #1001 1010 FTM2 trigger #1010 1011 FTM3 trigger #1011 1100 RTC alarm #1100 1101 RTC seconds #1101 1110 Low-power timer (LPTMR) trigger #1110 1111 TPM1 channel 0 (A pretrigger) and channel 1 (B pretrigger) #1111 ADC0PRETRGSEL ADC0 pretrigger select 4 1 read-write 0 Pre-trigger A #0 1 Pre-trigger B #1 ADC0ALTTRGEN ADC0 alternate trigger enable 7 1 read-write 0 PDB trigger selected for ADC0. #0 1 Alternate trigger selected for ADC0. #1 SOPT8 System Options Register 8 0x101C 32 read-write 0 0xFFFFFFFF FTM0SYNCBIT FTM0 Hardware Trigger 0 Software Synchronization 0 1 read-write 0 No effect #0 1 Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert. #1 FTM1SYNCBIT FTM1 Hardware Trigger 0 Software Synchronization 1 1 read-write 0 No effect. #0 1 Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert. #1 FTM2SYNCBIT FTM2 Hardware Trigger 0 Software Synchronization 2 1 read-write 0 No effect. #0 1 Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert. #1 FTM3SYNCBIT FTM3 Hardware Trigger 0 Software Synchronization 3 1 read-write 0 No effect. #0 1 Write 1 to assert the TRIG0 input to FTM3, software must clear this bit to allow other trigger sources to assert. #1 FTM0OCH0SRC FTM0 channel 0 output source 16 1 read-write 0 FTM0_CH0 pin is output of FTM0 channel 0 output #0 1 FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1 channel 1 output #1 FTM0OCH1SRC FTM0 channel 1 output source 17 1 read-write 0 FTM0_CH1 pin is output of FTM0 channel 1 output #0 1 FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1 channel 1 output #1 FTM0OCH2SRC FTM0 channel 2 output source 18 1 read-write 0 FTM0_CH2 pin is output of FTM0 channel 2 output #0 1 FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1 channel 1 output #1 FTM0OCH3SRC FTM0 channel 3 output source 19 1 read-write 0 FTM0_CH3 pin is output of FTM0 channel 3 output #0 1 FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1 channel 1 output #1 FTM0OCH4SRC FTM0 channel 4 output source 20 1 read-write 0 FTM0_CH4 pin is output of FTM0 channel 4 output #0 1 FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 channel 1 output #1 FTM0OCH5SRC FTM0 channel 5 output source 21 1 read-write 0 FTM0_CH5 pin is output of FTM0 channel 5 output #0 1 FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 channel 1 output #1 FTM0OCH6SRC FTM0 channel 6 output source 22 1 read-write 0 FTM0_CH6 pin is output of FTM0 channel 6 output #0 1 FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by FTM1 channel 1 output #1 FTM0OCH7SRC FTM0 channel 7 output source 23 1 read-write 0 FTM0_CH7 pin is output of FTM0 channel 7 output #0 1 FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by FTM1 channel 1 output #1 FTM3OCH0SRC FTM3 channel 0 output source 24 1 read-write 0 FTM3_CH0 pin is output of FTM3 channel 0 output #0 1 FTM3_CH0 pin is output of FTM3 channel 0 output modulated by FTM2 channel 1 output. #1 FTM3OCH1SRC FTM3 channel 1 output source 25 1 read-write 0 FTM3_CH1 pin is output of FTM3 channel 1 output #0 1 FTM3_CH1 pin is output of FTM3 channel 1 output modulated by FTM2 channel 1 output. #1 FTM3OCH2SRC FTM3 channel 2 output source 26 1 read-write 0 FTM3_CH2 pin is output of FTM3 channel 2 output #0 1 FTM3_CH2 pin is output of FTM3 channel 2 output modulated by FTM2 channel 1 output. #1 FTM3OCH3SRC FTM3 channel 3 output source 27 1 read-write 0 FTM3_CH3 pin is output of FTM3 channel 3 output #0 1 FTM3_CH3 pin is output of FTM3 channel 3 output modulated by FTM2 channel 1 output. #1 FTM3OCH4SRC FTM3 channel 4 output source 28 1 read-write 0 FTM3_CH4 pin is output of FTM3 channel 4 output #0 1 FTM3_CH4 pin is output of FTM3 channel 4 output modulated by FTM2 channel 1 output. #1 FTM3OCH5SRC FTM3 channel 5 output source 29 1 read-write 0 FTM3_CH5 pin is output of FTM3 channel 5 output #0 1 FTM3_CH5 pin is output of FTM3 channel 5 output modulated by FTM2 channel 1 output. #1 FTM3OCH6SRC FTM3 channel 6 output source 30 1 read-write 0 FTM3_CH6 pin is output of FTM3 channel 6 output #0 1 FTM3_CH6 pin is output of FTM3 channel 6 output modulated by FTM2 channel 1 output. #1 FTM3OCH7SRC FTM3 channel 7 output source 31 1 read-write 0 FTM3_CH7 pin is output of FTM3 channel 7 output #0 1 FTM3_CH7 pin is output of FTM3 channel 7 output modulated by FTM2 channel 1 output. #1 SOPT9 System Options Register 9 0x1020 32 read-write 0 0xFFFFFFFF TPM1CH0SRC TPM1 channel 0 input capture source select 18 2 read-write 00 TPM1_CH0 signal #00 01 CMP0 output #01 10 CMP1 output #10 TPM2CH0SRC TPM2 channel 0 input capture source select 20 2 read-write 00 TPM2_CH0 signal #00 01 CMP0 output #01 10 CMP1 output #10 TPM1CLKSEL TPM1 External Clock Pin Select 25 1 read-write 0 TPM_CLKIN0 pin #0 1 TPM_CLKIN1 pin #1 TPM2CLKSEL TPM2 External Clock Pin Select 26 1 read-write 0 TPM_CLKIN0 pin #0 1 TPM_CLKIN1 pin #1 SDID System Device Identification Register 0x1024 32 read-only 0xB80 0xF0F80 PINID Pincount identification 0 4 read-only 0010 32-pin #0010 0100 48-pin #0100 0101 64-pin #0101 0110 80-pin #0110 0111 81-pin or 121-pin #0111 1000 100-pin #1000 1001 121-pin #1001 1010 144-pin #1010 1011 Custom pinout (WLCSP) #1011 1100 169-pin #1100 1110 256-pin #1110 FAMID Kinetis family identification 4 3 read-only 000 K1x Family (without tamper) #000 001 K2x Family (without tamper) #001 010 K3x Family or K1x/K6x Family (with tamper) #010 011 K4x Family or K2x Family (with tamper) #011 100 K6x Family (without tamper) #100 101 K7x Family #101 DIEID Device Die ID 7 5 read-only REVID Device revision number 12 4 read-only SERIESID Kinetis Series ID 20 4 read-only 0000 Kinetis K series #0000 0001 Kinetis L series #0001 0101 Kinetis W series #0101 0110 Kinetis V series #0110 SUBFAMID Kinetis Sub-Family ID 24 4 read-only 0000 Kx0 Subfamily #0000 0001 Kx1 Subfamily (tamper detect) #0001 0010 Kx2 Subfamily #0010 0011 Kx3 Subfamily (tamper detect) #0011 0100 Kx4 Subfamily #0100 0101 Kx5 Subfamily (tamper detect) #0101 0110 Kx6 Subfamily #0110 FAMILYID Kinetis Family ID 28 4 read-only 0000 K0x Family #0000 0001 K1x Family #0001 0010 K2x Family #0010 0011 K3x Family #0011 0100 K4x Family #0100 0110 K6x Family #0110 0111 K7x Family #0111 1000 K8x Family #1000 SCGC1 System Clock Gating Control Register 1 0x1028 32 read-write 0 0xFFFFFFFF I2C2 I2C2 Clock Gate Control 6 1 read-write 0 Clock disabled #0 1 Clock enabled #1 I2C3 I2C3 Clock Gate Control 7 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC2 System Clock Gating Control Register 2 0x102C 32 read-write 0 0xFFFFFFFF LPUART0 LPUART0 Clock Gate Control 4 1 read-write 0 Clock disabled #0 1 Clock enabled #1 LPUART1 LPUART1 Clock Gate Control 5 1 read-write 0 Clock disabled #0 1 Clock enabled #1 LPUART2 LPUART2 Clock Gate Control 6 1 read-write 0 Clock disabled #0 1 Clock enabled #1 LPUART3 LPUART3 Clock Gate Control 7 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TPM1 TPM1 Clock Gate Control 9 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TPM2 TPM2 Clock Gate Control 10 1 read-write 0 Clock disabled #0 1 Clock enabled #1 DAC0 DAC0 Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 LTC LTC Clock Gate Control 17 1 read-write 0 Clock disabled #0 1 Clock enabled #1 EMVSIM0 EMVSIM0 Clock Gate Control 20 1 read-write 0 Clock disabled #0 1 Clock enabled #1 EMVSIM1 EMVSIM1 Clock Gate Control 21 1 read-write 0 Clock disabled #0 1 Clock enabled #1 LPUART4 LPUART4 Clock Gate Control 22 1 read-write 0 Clock disabled #0 1 Clock enabled #1 QSPI QSPI Clock Gate Control 26 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FLEXIO FlexIO Clock Gate Control 31 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC3 System Clock Gating Control Register 3 0x1030 32 read-write 0 0xFFFFFFFF TRNG TRNG Clock Gate Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SPI2 SPI2 Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SDHC SDHC Clock Gate Control 17 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM2 FTM2 Clock Gate Control 24 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM3 FTM3 Clock Gate Control 25 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC4 System Clock Gating Control Register 4 0x1034 32 read-write 0xF0100030 0xFFFFFFFF EWM EWM Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CMT CMT Clock Gate Control 2 1 read-write 0 Clock disabled #0 1 Clock enabled #1 I2C0 I2C0 Clock Gate Control 6 1 read-write 0 Clock disabled #0 1 Clock enabled #1 I2C1 I2C1 Clock Gate Control 7 1 read-write 0 Clock disabled #0 1 Clock enabled #1 USBOTG USB Clock Gate Control 18 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CMP Comparator Clock Gate Control 19 1 read-write 0 Clock disabled #0 1 Clock enabled #1 VREF VREF Clock Gate Control 20 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC5 System Clock Gating Control Register 5 0x1038 32 read-write 0x40182 0xFFFFFFFF LPTMR Low Power Timer Access Control 0 1 read-write 0 Access disabled #0 1 Access enabled #1 DRYICE DryIce Access Control 2 1 read-write 0 Access and interrupt disabled #0 1 Access and interrupt enabled #1 SECREG Secure Register Access Control 3 1 read-write 0 Access disabled #0 1 Access enabled #1 LPTMR1 LPTMR1 Clock Gate Control 4 1 read-write 0 Access disabled #0 1 Access enabled #1 TSI TSI Clock Gate Control 5 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTA Port A Clock Gate Control 9 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTB Port B Clock Gate Control 10 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTC Port C Clock Gate Control 11 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTD Port D Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTE Port E Clock Gate Control 13 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC6 System Clock Gating Control Register 6 0x103C 32 read-write 0x40000001 0xFFFFFFFF FTF Flash Memory Clock Gate Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 DMAMUX DMA Mux Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SPI0 SPI0 Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SPI1 SPI1 Clock Gate Control 13 1 read-write 0 Clock disabled #0 1 Clock enabled #1 I2S I2S Clock Gate Control 15 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CRC CRC Clock Gate Control 18 1 read-write 0 Clock disabled #0 1 Clock enabled #1 USBDCD USB DCD Clock Gate Control 21 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PDB PDB Clock Gate Control 22 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PIT PIT Clock Gate Control 23 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM0 FTM0 Clock Gate Control 24 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM1 FTM1 Clock Gate Control 25 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM2 FTM2 Clock Gate Control 26 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ADC0 ADC0 Clock Gate Control 27 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RTC RTC Access Control 29 1 read-write 0 Access and interrupts disabled #0 1 Access and interrupts enabled #1 DAC0 DAC0 Clock Gate Control 31 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC7 System Clock Gating Control Register 7 0x1040 32 read-write 0x6 0xFFFFFFFF FLEXBUS FlexBus Clock Gate Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 DMA DMA Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 MPU MPU Clock Gate Control 2 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SDRAMC SDRAMC Clock Gate Control 3 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CLKDIV1 System Clock Divider Register 1 0x1044 32 read-write 0x10000 0xFFFFFFFF OUTDIV4 Clock 4 output divider value 16 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 OUTDIV3 Clock 3 output divider value 20 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 OUTDIV2 Clock 2 output divider value 24 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 OUTDIV1 Clock 1 output divider value 28 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 CLKDIV2 System Clock Divider Register 2 0x1048 32 read-write 0 0xFFFFFFFF USBFRAC USB clock divider fraction 0 1 read-write USBDIV USB clock divider divisor 1 3 read-write FCFG1 Flash Configuration Register 1 0x104C 32 read-write 0xF0F0F00 0xFFFFFFFF FLASHDIS Flash Disable 0 1 read-write 0 Flash is enabled #0 1 Flash is disabled #1 FLASHDOZE Flash Doze 1 1 read-write 0 Flash remains enabled during Wait mode #0 1 Flash is disabled for the duration of Wait mode #1 PFSIZE Program flash size 24 4 read-only 0011 32 KB of program flash memory #0011 0101 64 KB of program flash memory #0101 0111 128 KB of program flash memory #0111 1001 256 KB of program flash memory #1001 1011 512 KB of program flash memory #1011 1101 1024 KB of program flash memory #1101 1111 256 KB of program flash memory #1111 FCFG2 Flash Configuration Register 2 0x1050 32 read-only 0x7FFF0000 0xFFFFFFFF MAXADDR1 Max address block 1 16 7 read-only MAXADDR0 Max address block 0 24 7 read-only UIDH Unique Identification Register High 0x1054 32 read-only 0 0xFFFFFFFF UID Unique Identification 0 32 read-only UIDMH Unique Identification Register Mid-High 0x1058 32 read-only 0 0xFFFFFFFF UID Unique Identification 0 32 read-only UIDML Unique Identification Register Mid Low 0x105C 32 read-only 0 0xFFFFFFFF UID Unique Identification 0 32 read-only UIDL Unique Identification Register Low 0x1060 32 read-only 0 0xFFFFFFFF UID Unique Identification 0 32 read-only CLKDIV3 System Clock Divider Register 3 0x1064 32 read-write 0 0xFFFFFFFF PLLFLLFRAC PLLFLL clock divider fraction 0 1 read-write PLLFLLDIV PLLFLL clock divider divisor 1 3 read-write CLKDIV4 System Clock Divider Register 4 0x1068 32 read-write 0 0xFFFFFFFF TRACEFRAC Trace clock divider fraction 0 1 read-write TRACEDIV Trace clock divider divisor 1 3 read-write PORTA Pin Control and Interrupts PORT PORTA_ 0x40049000 0 0xA4 registers PORTA 59 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0x702 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PORTB Pin Control and Interrupts PORT PORTB_ 0x4004A000 0 0xA4 registers PORTB 60 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PORTC Pin Control and Interrupts PORT PORTC_ 0x4004B000 0 0xA4 registers PORTC 61 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PORTD Pin Control and Interrupts PORT PORTD_ 0x4004C000 0 0xCC registers PORTD 62 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 DFER Digital Filter Enable Register 0xC0 32 read-write 0 0xFFFFFFFF DFE Digital Filter Enable 0 32 read-write 0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. #0 1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DFCR Digital Filter Clock Register 0xC4 32 read-write 0 0xFFFFFFFF CS Clock Source 0 1 read-write 0 Digital filters are clocked by the bus clock. #0 1 Digital filters are clocked by the LPO clock. #1 DFWR Digital Filter Width Register 0xC8 32 read-write 0 0xFFFFFFFF FILT Filter Length 0 5 read-write PORTE Pin Control and Interrupts PORT PORTE_ 0x4004D000 0 0xA4 registers PORTE 63 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 WDOG Generation 2008 Watchdog Timer WDOG_ 0x40052000 0 0x18 registers WDOG_EWM 22 STCTRLH Watchdog Status and Control Register High 0 16 read-write 0x1D3 0xFFFF WDOGEN Enables or disables the WDOG's operation 0 1 read-write 0 WDOG is disabled. #0 1 WDOG is enabled. #1 CLKSRC Selects clock source for the WDOG timer and other internal timing operations. 1 1 read-write 0 WDOG clock sourced from LPO . #0 1 WDOG clock sourced from alternate clock source. #1 IRQRSTEN Used to enable the debug breadcrumbs feature 2 1 read-write 0 WDOG time-out generates reset only. #0 1 WDOG time-out initially generates an interrupt. After WCT, it generates a reset. #1 WINEN Enables Windowing mode. 3 1 read-write 0 Windowing mode is disabled. #0 1 Windowing mode is enabled. #1 ALLOWUPDATE Enables updates to watchdog write-once registers, after the reset-triggered initial configuration window (WCT) closes, through unlock sequence 4 1 read-write 0 No further updates allowed to WDOG write-once registers. #0 1 WDOG write-once registers can be unlocked for updating. #1 DBGEN Enables or disables WDOG in Debug mode. 5 1 read-write 0 WDOG is disabled in CPU Debug mode. #0 1 WDOG is enabled in CPU Debug mode. #1 STOPEN Enables or disables WDOG in Stop mode. 6 1 read-write 0 WDOG is disabled in CPU Stop mode. #0 1 WDOG is enabled in CPU Stop mode. #1 WAITEN Enables or disables WDOG in Wait mode. 7 1 read-write 0 WDOG is disabled in CPU Wait mode. #0 1 WDOG is enabled in CPU Wait mode. #1 TESTWDOG Puts the watchdog in the functional test mode 10 1 read-write TESTSEL Effective only if TESTWDOG is set. Selects the test to be run on the watchdog timer. 11 1 read-write 0 Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test. #0 1 Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing. #1 BYTESEL This 2-bit field selects the byte to be tested when the watchdog is in the byte test mode. 12 2 read-write 00 Byte 0 selected #00 01 Byte 1 selected #01 10 Byte 2 selected #10 11 Byte 3 selected #11 DISTESTWDOG Allows the WDOG's functional test mode to be disabled permanently 14 1 read-write 0 WDOG functional test mode is not disabled. #0 1 WDOG functional test mode is disabled permanently until reset. #1 STCTRLL Watchdog Status and Control Register Low 0x2 16 read-write 0x1 0xFFFF INTFLG Interrupt flag 15 1 read-write TOVALH Watchdog Time-out Value Register High 0x4 16 read-write 0x4C 0xFFFF TOVALHIGH Defines the upper 16 bits of the 32-bit time-out value for the watchdog timer 0 16 read-write TOVALL Watchdog Time-out Value Register Low 0x6 16 read-write 0x4B4C 0xFFFF TOVALLOW Defines the lower 16 bits of the 32-bit time-out value for the watchdog timer 0 16 read-write WINH Watchdog Window Register High 0x8 16 read-write 0 0xFFFF WINHIGH Defines the upper 16 bits of the 32-bit window for the windowed mode of operation of the watchdog 0 16 read-write WINL Watchdog Window Register Low 0xA 16 read-write 0x10 0xFFFF WINLOW Defines the lower 16 bits of the 32-bit window for the windowed mode of operation of the watchdog 0 16 read-write REFRESH Watchdog Refresh register 0xC 16 read-write 0xB480 0xFFFF WDOGREFRESH Watchdog refresh register 0 16 read-write UNLOCK Watchdog Unlock register 0xE 16 read-write 0xD928 0xFFFF WDOGUNLOCK Writing the unlock sequence values to this register to makes the watchdog write-once registers writable again 0 16 read-write TMROUTH Watchdog Timer Output Register High 0x10 16 read-write 0 0xFFFF TIMEROUTHIGH Shows the value of the upper 16 bits of the watchdog timer. 0 16 read-write TMROUTL Watchdog Timer Output Register Low 0x12 16 read-write 0 0xFFFF TIMEROUTLOW Shows the value of the lower 16 bits of the watchdog timer. 0 16 read-write RSTCNT Watchdog Reset Count register 0x14 16 read-write 0 0xFFFF RSTCNT Counts the number of times the watchdog resets the system 0 16 read-write PRESC Watchdog Prescaler register 0x16 16 read-write 0x400 0xFFFF PRESCVAL 3-bit prescaler for the watchdog clock source 8 3 read-write EWM External Watchdog Monitor EWM_ 0x40061000 0 0x6 registers WDOG_EWM 22 CTRL Control Register 0 8 read-write 0 0xFF EWMEN EWM enable. 0 1 read-write ASSIN EWM_in's Assertion State Select. 1 1 read-write INEN Input Enable. 2 1 read-write INTEN Interrupt Enable. 3 1 read-write SERV Service Register 0x1 8 write-only 0 0xFF SERVICE The EWM service mechanism requires the CPU to write two values to the SERV register: a first data byte of 0xB4, followed by a second data byte of 0x2C 0 8 write-only CMPL Compare Low Register 0x2 8 read-write 0 0xFF COMPAREL To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) minimum service time is required 0 8 read-write CMPH Compare High Register 0x3 8 read-write 0xFF 0xFF COMPAREH To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) maximum service time is required 0 8 read-write CLKCTRL Clock Control Register 0x4 8 read-write 0 0xFF CLKSEL EWM has 4 possible low power clock sources for running EWM counter 0 2 read-write CLKPRESCALER Clock Prescaler Register 0x5 8 read-write 0 0xFF CLK_DIV Selected low power clock source for running the EWM counter can be prescaled as below 0 8 read-write CMT Carrier Modulator Transmitter CMT_ 0x40062000 0 0xC registers CMT 45 CGH1 CMT Carrier Generator High Data Register 1 0 8 read-write 0 0 PH Primary Carrier High Time Data Value 0 8 read-write CGL1 CMT Carrier Generator Low Data Register 1 0x1 8 read-write 0 0 PL Primary Carrier Low Time Data Value 0 8 read-write CGH2 CMT Carrier Generator High Data Register 2 0x2 8 read-write 0 0 SH Secondary Carrier High Time Data Value 0 8 read-write CGL2 CMT Carrier Generator Low Data Register 2 0x3 8 read-write 0 0 SL Secondary Carrier Low Time Data Value 0 8 read-write OC CMT Output Control Register 0x4 8 read-write 0 0xFF IROPEN IRO Pin Enable 5 1 read-write 0 The IRO signal is disabled. #0 1 The IRO signal is enabled as output. #1 CMTPOL CMT Output Polarity 6 1 read-write 0 The IRO signal is active-low. #0 1 The IRO signal is active-high. #1 IROL IRO Latch Control 7 1 read-write MSC CMT Modulator Status and Control Register 0x5 8 read-write 0 0xFF MCGEN Modulator and Carrier Generator Enable 0 1 read-write 0 Modulator and carrier generator disabled #0 1 Modulator and carrier generator enabled #1 EOCIE End of Cycle Interrupt Enable 1 1 read-write 0 CPU interrupt is disabled. #0 1 CPU interrupt is enabled. #1 FSK FSK Mode Select 2 1 read-write 0 The CMT operates in Time or Baseband mode. #0 1 The CMT operates in FSK mode. #1 BASE Baseband Enable 3 1 read-write 0 Baseband mode is disabled. #0 1 Baseband mode is enabled. #1 EXSPC Extended Space Enable 4 1 read-write 0 Extended space is disabled. #0 1 Extended space is enabled. #1 CMTDIV CMT Clock Divide Prescaler 5 2 read-write 00 IF * 1 #00 01 IF * 2 #01 10 IF * 4 #10 11 IF * 8 #11 EOCF End Of Cycle Status Flag 7 1 read-only 0 End of modulation cycle has not occured since the flag last cleared. #0 1 End of modulator cycle has occurred. #1 CMD1 CMT Modulator Data Register Mark High 0x6 8 read-write 0 0 MB MB[15:8] 0 8 read-write CMD2 CMT Modulator Data Register Mark Low 0x7 8 read-write 0 0 MB MB[7:0] 0 8 read-write CMD3 CMT Modulator Data Register Space High 0x8 8 read-write 0 0 SB SB[15:8] 0 8 read-write CMD4 CMT Modulator Data Register Space Low 0x9 8 read-write 0 0 SB SB[7:0] 0 8 read-write PPS CMT Primary Prescaler Register 0xA 8 read-write 0 0xFF PPSDIV Primary Prescaler Divider 0 4 read-write 0000 Bus clock * 1 #0000 0001 Bus clock * 2 #0001 0010 Bus clock * 3 #0010 0011 Bus clock * 4 #0011 0100 Bus clock * 5 #0100 0101 Bus clock * 6 #0101 0110 Bus clock * 7 #0110 0111 Bus clock * 8 #0111 1000 Bus clock * 9 #1000 1001 Bus clock * 10 #1001 1010 Bus clock * 11 #1010 1011 Bus clock * 12 #1011 1100 Bus clock * 13 #1100 1101 Bus clock * 14 #1101 1110 Bus clock * 15 #1110 1111 Bus clock * 16 #1111 DMA CMT Direct Memory Access Register 0xB 8 read-write 0 0xFF DMA DMA Enable 0 1 read-write 0 DMA transfer request and done are disabled. #0 1 DMA transfer request and done are enabled. #1 MCG Multipurpose Clock Generator module MCG_ 0x40064000 0 0xE registers MCG 57 C1 MCG Control 1 Register 0 8 read-write 0x4 0xFF IREFSTEN Internal Reference Stop Enable 0 1 read-write 0 Internal reference clock is disabled in Stop mode. #0 1 Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. #1 IRCLKEN Internal Reference Clock Enable 1 1 read-write 0 MCGIRCLK inactive. #0 1 MCGIRCLK active. #1 IREFS Internal Reference Select 2 1 read-write 0 External reference clock is selected. #0 1 The slow internal reference clock is selected. #1 FRDIV FLL External Reference Divider 3 3 read-write 000 If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. #000 001 If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. #001 010 If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. #010 011 If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. #011 100 If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. #100 101 If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. #101 110 If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . #110 111 If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 . #111 CLKS Clock Source Select 6 2 read-write 00 Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit). #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 11 Encoding 3 - Reserved. #11 C2 MCG Control 2 Register 0x1 8 read-write 0x80 0xFF IRCS Internal Reference Clock Select 0 1 read-write 0 Slow internal reference clock selected. #0 1 Fast internal reference clock selected. #1 LP Low Power Select 1 1 read-write 0 FLL or PLL is not disabled in bypass modes. #0 1 FLL or PLL is disabled in bypass modes (lower power) #1 EREFS External Reference Select 2 1 read-write 0 External reference clock requested. #0 1 Oscillator requested. #1 HGO High Gain Oscillator Select 3 1 read-write 0 Configure crystal oscillator for low-power operation. #0 1 Configure crystal oscillator for high-gain operation. #1 RANGE Frequency Range Select 4 2 read-write 00 Encoding 0 - Low frequency range selected for the crystal oscillator . #00 01 Encoding 1 - High frequency range selected for the crystal oscillator . #01 FCFTRIM Fast Internal Reference Clock Fine Trim 6 1 read-write LOCRE0 Loss of Clock Reset Enable 7 1 read-write 0 Interrupt request is generated on a loss of OSC0 external reference clock. #0 1 Generate a reset request on a loss of OSC0 external reference clock. #1 C3 MCG Control 3 Register 0x2 8 read-write 0 0 SCTRIM Slow Internal Reference Clock Trim Setting 0 8 read-write C4 MCG Control 4 Register 0x3 8 read-write 0 0xE0 SCFTRIM Slow Internal Reference Clock Fine Trim 0 1 read-write FCTRIM Fast Internal Reference Clock Trim Setting 1 4 read-write DRST_DRS DCO Range Select 5 2 read-write 00 Encoding 0 - Low range (reset default). #00 01 Encoding 1 - Mid range. #01 10 Encoding 2 - Mid-high range. #10 11 Encoding 3 - High range. #11 DMX32 DCO Maximum Frequency with 32.768 kHz Reference 7 1 read-write 0 DCO has a default range of 25%. #0 1 DCO is fine-tuned for maximum frequency with 32.768 kHz reference. #1 C5 MCG Control 5 Register 0x4 8 read-write 0 0xFF PRDIV PLL External Reference Divider 0 3 read-write PLLSTEN PLL Stop Enable 5 1 read-write 0 MCGPLLCLK and MCGPLLCLK2X are disabled in any of the Stop modes. #0 1 MCGPLLCLK and MCGPLLCLK2X are enabled if system is in Normal Stop mode. #1 PLLCLKEN PLL Clock Enable 6 1 read-write 0 MCGPLLCLK is inactive. #0 1 MCGPLLCLK is active. #1 C6 MCG Control 6 Register 0x5 8 read-write 0 0xFF VDIV VCO Divider 0 5 read-write CME0 Clock Monitor Enable 5 1 read-write 0 External clock monitor is disabled for OSC0. #0 1 External clock monitor is enabled for OSC0. #1 PLLS PLL Select 6 1 read-write 0 FLL is selected. #0 1 PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 8-16 MHz prior to setting the PLLS bit). #1 LOLIE0 Loss of Lock Interrrupt Enable 7 1 read-write 0 No interrupt request is generated on loss of lock. #0 1 Generate an interrupt request on loss of lock. #1 S MCG Status Register 0x6 8 read-write 0x10 0xFF IRCST Internal Reference Clock Status 0 1 read-only 0 Source of internal reference clock is the slow clock (32 kHz IRC). #0 1 Source of internal reference clock is the fast clock (4 MHz IRC). #1 OSCINIT0 OSC Initialization 1 1 read-only CLKST Clock Mode Status 2 2 read-only 00 Encoding 0 - Output of the FLL is selected (reset default). #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 11 Encoding 3 - Output of the PLL is selected. #11 IREFST Internal Reference Status 4 1 read-only 0 Source of FLL reference clock is the external reference clock. #0 1 Source of FLL reference clock is the internal reference clock. #1 PLLST PLL Select Status 5 1 read-only 0 Source of PLLS clock is FLL clock. #0 1 Source of PLLS clock is PLL output clock. #1 LOCK0 Lock Status 6 1 read-only 0 PLL is currently unlocked. #0 1 PLL is currently locked. #1 LOLS0 Loss of Lock Status 7 1 read-write 0 PLL has not lost lock since LOLS 0 was last cleared. #0 1 PLL has lost lock since LOLS 0 was last cleared. #1 SC MCG Status and Control Register 0x8 8 read-write 0x2 0xFF LOCS0 OSC0 Loss of Clock Status 0 1 read-write 0 Loss of OSC0 has not occurred. #0 1 Loss of OSC0 has occurred. #1 FCRDIV Fast Clock Internal Reference Divider 1 3 read-write 000 Divide Factor is 1 #000 001 Divide Factor is 2. #001 010 Divide Factor is 4. #010 011 Divide Factor is 8. #011 100 Divide Factor is 16 #100 101 Divide Factor is 32 #101 110 Divide Factor is 64 #110 111 Divide Factor is 128. #111 FLTPRSRV FLL Filter Preserve Enable 4 1 read-write 0 FLL filter and FLL frequency will reset on changes to currect clock mode. #0 1 Fll filter and FLL frequency retain their previous values during new clock mode change. #1 ATMF Automatic Trim Machine Fail Flag 5 1 read-write 0 Automatic Trim Machine completed normally. #0 1 Automatic Trim Machine failed. #1 ATMS Automatic Trim Machine Select 6 1 read-write 0 32 kHz Internal Reference Clock selected. #0 1 4 MHz Internal Reference Clock selected. #1 ATME Automatic Trim Machine Enable 7 1 read-write 0 Auto Trim Machine disabled. #0 1 Auto Trim Machine enabled. #1 ATCVH MCG Auto Trim Compare Value High Register 0xA 8 read-write 0 0xFF ATCVH ATM Compare Value High 0 8 read-write ATCVL MCG Auto Trim Compare Value Low Register 0xB 8 read-write 0 0xFF ATCVL ATM Compare Value Low 0 8 read-write C7 MCG Control 7 Register 0xC 8 read-write 0 0xFF OSCSEL MCG OSC Clock Select 0 2 read-write 00 Selects Oscillator (OSCCLK0). #00 01 Selects 32 kHz RTC Oscillator. #01 10 Selects Oscillator (OSCCLK1). #10 C8 MCG Control 8 Register 0xD 8 read-write 0x80 0xFF LOCS1 RTC Loss of Clock Status 0 1 read-write 0 Loss of RTC has not occur. #0 1 Loss of RTC has occur #1 CME1 Clock Monitor Enable1 5 1 read-write 0 External clock monitor is disabled for RTC clock. #0 1 External clock monitor is enabled for RTC clock. #1 LOLRE PLL Loss of Lock Reset Enable 6 1 read-write 0 Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request. #0 1 Generate a reset request on a PLL loss of lock indication. #1 LOCRE1 Loss of Clock Reset Enable 7 1 read-write 0 Interrupt request is generated on a loss of RTC external reference clock. #0 1 Generate a reset request on a loss of RTC external reference clock #1 OSC Oscillator OSC_ 0x40065000 0 0x3 registers CR OSC Control Register 0 8 read-write 0 0xFF SC16P Oscillator 16 pF Capacitor Load Configure 0 1 read-write 0 Disable the selection. #0 1 Add 16 pF capacitor to the oscillator load. #1 SC8P Oscillator 8 pF Capacitor Load Configure 1 1 read-write 0 Disable the selection. #0 1 Add 8 pF capacitor to the oscillator load. #1 SC4P Oscillator 4 pF Capacitor Load Configure 2 1 read-write 0 Disable the selection. #0 1 Add 4 pF capacitor to the oscillator load. #1 SC2P Oscillator 2 pF Capacitor Load Configure 3 1 read-write 0 Disable the selection. #0 1 Add 2 pF capacitor to the oscillator load. #1 EREFSTEN External Reference Stop Enable 5 1 read-write 0 External reference clock is disabled in Stop mode. #0 1 External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode. #1 ERCLKEN External Reference Enable 7 1 read-write 0 External reference clock is inactive. #0 1 External reference clock is enabled. #1 DIV OSC_DIV 0x2 8 read-write 0 0xFF ERPS ERCLK prescaler 6 2 read-write 00 The divisor ratio is 1. #00 01 The divisor ratio is 2. #01 10 The divisor ratio is 4. #10 11 The divisor ratio is 8. #11 I2C0 Inter-Integrated Circuit I2C I2C0_ 0x40066000 0 0xD registers I2C0 24 A1 I2C Address Register 1 0 8 read-write 0 0xFF AD Address 1 7 read-write F I2C Frequency Divider register 0x1 8 read-write 0 0xFF ICR ClockRate 0 6 read-write MULT Multiplier Factor 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 C1 I2C Control Register 1 0x2 8 read-write 0 0xFF DMAEN DMA Enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 WUEN Wakeup Enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 RSTA Repeat START 2 1 write-only TXAK Transmit Acknowledge Enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). #0 1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). #1 TX Transmit Mode Select 4 1 read-write 0 Receive #0 1 Transmit #1 MST Master Mode Select 5 1 read-write 0 Slave mode #0 1 Master mode #1 IICIE I2C Interrupt Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 IICEN I2C Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 S I2C Status register 0x3 8 read-write 0x80 0xFF RXAK Receive Acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 IICIF Interrupt Flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 SRW Slave Read/Write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 RAM Range Address Match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 ARBL Arbitration Lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus Busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed As A Slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 TCF Transfer Complete Flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 D I2C Data I/O register 0x4 8 read-write 0 0xFF DATA Data 0 8 read-write C2 I2C Control Register 2 0x5 8 read-write 0 0xFF AD Slave Address 0 3 read-write RMEN Range Address Matching Enable 3 1 read-write 0 Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave Baud Rate Control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 HDRS High Drive Select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 ADEXT Address Extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General Call Address Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 FLT I2C Programmable Input Glitch Filter Register 0x6 8 read-write 0 0xFF FLT I2C Programmable Filter Factor 0 4 read-write 0 No filter/bypass #0000 STARTF I2C Bus Start Detect Flag 4 1 read-write 0 No start happens on I2C bus #0 1 Start detected on I2C bus #1 SSIE I2C Bus Stop or Start Interrupt Enable 5 1 read-write 0 Stop or start detection interrupt is disabled #0 1 Stop or start detection interrupt is enabled #1 STOPF I2C Bus Stop Detect Flag 6 1 read-write 0 No stop happens on I2C bus #0 1 Stop detected on I2C bus #1 SHEN Stop Hold Enable 7 1 read-write 0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated. #0 1 Stop holdoff is enabled. #1 RA I2C Range Address register 0x7 8 read-write 0 0xFF RAD Range Slave Address 1 7 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write 0 0xFF SHTF2IE SHTF2 Interrupt Enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SHTF2 SCL High Timeout Flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF1 SCL High Timeout Flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SLTF SCL Low Timeout Flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout Counter Clock Select 4 1 read-write 0 Timeout counter counts at the frequency of the I2C module clock / 64 #0 1 Timeout counter counts at the frequency of the I2C module clock #1 SIICAEN Second I2C Address Enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 ALERTEN SMBus Alert Response Address Enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK Enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. #1 A2 I2C Address Register 2 0x9 8 read-write 0xC2 0xFF SAD SMBus Address 1 7 read-write SLTH I2C SCL Low Timeout Register High 0xA 8 read-write 0 0xFF SSLT SSLT[15:8] 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write 0 0xFF SSLT SSLT[7:0] 0 8 read-write S2 I2C Status register 2 0xC 8 read-write 0x1 0xFF EMPTY Empty flag 0 1 read-only 0 Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer. #0 1 Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer. #1 ERROR Error flag 1 1 read-write 0 The buffer is not full and all write/read operations have no errors. #0 1 There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the buffer is busy). #1 I2C1 Inter-Integrated Circuit I2C I2C1_ 0x40067000 0 0xD registers I2C1 25 A1 I2C Address Register 1 0 8 read-write 0 0xFF AD Address 1 7 read-write F I2C Frequency Divider register 0x1 8 read-write 0 0xFF ICR ClockRate 0 6 read-write MULT Multiplier Factor 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 C1 I2C Control Register 1 0x2 8 read-write 0 0xFF DMAEN DMA Enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 WUEN Wakeup Enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 RSTA Repeat START 2 1 write-only TXAK Transmit Acknowledge Enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). #0 1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). #1 TX Transmit Mode Select 4 1 read-write 0 Receive #0 1 Transmit #1 MST Master Mode Select 5 1 read-write 0 Slave mode #0 1 Master mode #1 IICIE I2C Interrupt Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 IICEN I2C Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 S I2C Status register 0x3 8 read-write 0x80 0xFF RXAK Receive Acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 IICIF Interrupt Flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 SRW Slave Read/Write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 RAM Range Address Match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 ARBL Arbitration Lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus Busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed As A Slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 TCF Transfer Complete Flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 D I2C Data I/O register 0x4 8 read-write 0 0xFF DATA Data 0 8 read-write C2 I2C Control Register 2 0x5 8 read-write 0 0xFF AD Slave Address 0 3 read-write RMEN Range Address Matching Enable 3 1 read-write 0 Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave Baud Rate Control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 HDRS High Drive Select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 ADEXT Address Extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General Call Address Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 FLT I2C Programmable Input Glitch Filter Register 0x6 8 read-write 0 0xFF FLT I2C Programmable Filter Factor 0 4 read-write 0 No filter/bypass #0000 STARTF I2C Bus Start Detect Flag 4 1 read-write 0 No start happens on I2C bus #0 1 Start detected on I2C bus #1 SSIE I2C Bus Stop or Start Interrupt Enable 5 1 read-write 0 Stop or start detection interrupt is disabled #0 1 Stop or start detection interrupt is enabled #1 STOPF I2C Bus Stop Detect Flag 6 1 read-write 0 No stop happens on I2C bus #0 1 Stop detected on I2C bus #1 SHEN Stop Hold Enable 7 1 read-write 0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated. #0 1 Stop holdoff is enabled. #1 RA I2C Range Address register 0x7 8 read-write 0 0xFF RAD Range Slave Address 1 7 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write 0 0xFF SHTF2IE SHTF2 Interrupt Enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SHTF2 SCL High Timeout Flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF1 SCL High Timeout Flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SLTF SCL Low Timeout Flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout Counter Clock Select 4 1 read-write 0 Timeout counter counts at the frequency of the I2C module clock / 64 #0 1 Timeout counter counts at the frequency of the I2C module clock #1 SIICAEN Second I2C Address Enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 ALERTEN SMBus Alert Response Address Enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK Enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. #1 A2 I2C Address Register 2 0x9 8 read-write 0xC2 0xFF SAD SMBus Address 1 7 read-write SLTH I2C SCL Low Timeout Register High 0xA 8 read-write 0 0xFF SSLT SSLT[15:8] 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write 0 0xFF SSLT SSLT[7:0] 0 8 read-write S2 I2C Status register 2 0xC 8 read-write 0x1 0xFF EMPTY Empty flag 0 1 read-only 0 Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer. #0 1 Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer. #1 ERROR Error flag 1 1 read-write 0 The buffer is not full and all write/read operations have no errors. #0 1 There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the buffer is busy). #1 I2C2 Inter-Integrated Circuit I2C I2C2_ 0x400E6000 0 0xD registers I2C2 74 A1 I2C Address Register 1 0 8 read-write 0 0xFF AD Address 1 7 read-write F I2C Frequency Divider register 0x1 8 read-write 0 0xFF ICR ClockRate 0 6 read-write MULT Multiplier Factor 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 C1 I2C Control Register 1 0x2 8 read-write 0 0xFF DMAEN DMA Enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 WUEN Wakeup Enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 RSTA Repeat START 2 1 write-only TXAK Transmit Acknowledge Enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). #0 1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). #1 TX Transmit Mode Select 4 1 read-write 0 Receive #0 1 Transmit #1 MST Master Mode Select 5 1 read-write 0 Slave mode #0 1 Master mode #1 IICIE I2C Interrupt Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 IICEN I2C Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 S I2C Status register 0x3 8 read-write 0x80 0xFF RXAK Receive Acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 IICIF Interrupt Flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 SRW Slave Read/Write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 RAM Range Address Match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 ARBL Arbitration Lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus Busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed As A Slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 TCF Transfer Complete Flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 D I2C Data I/O register 0x4 8 read-write 0 0xFF DATA Data 0 8 read-write C2 I2C Control Register 2 0x5 8 read-write 0 0xFF AD Slave Address 0 3 read-write RMEN Range Address Matching Enable 3 1 read-write 0 Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave Baud Rate Control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 HDRS High Drive Select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 ADEXT Address Extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General Call Address Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 FLT I2C Programmable Input Glitch Filter Register 0x6 8 read-write 0 0xFF FLT I2C Programmable Filter Factor 0 4 read-write 0 No filter/bypass #0000 STARTF I2C Bus Start Detect Flag 4 1 read-write 0 No start happens on I2C bus #0 1 Start detected on I2C bus #1 SSIE I2C Bus Stop or Start Interrupt Enable 5 1 read-write 0 Stop or start detection interrupt is disabled #0 1 Stop or start detection interrupt is enabled #1 STOPF I2C Bus Stop Detect Flag 6 1 read-write 0 No stop happens on I2C bus #0 1 Stop detected on I2C bus #1 SHEN Stop Hold Enable 7 1 read-write 0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated. #0 1 Stop holdoff is enabled. #1 RA I2C Range Address register 0x7 8 read-write 0 0xFF RAD Range Slave Address 1 7 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write 0 0xFF SHTF2IE SHTF2 Interrupt Enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SHTF2 SCL High Timeout Flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF1 SCL High Timeout Flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SLTF SCL Low Timeout Flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout Counter Clock Select 4 1 read-write 0 Timeout counter counts at the frequency of the I2C module clock / 64 #0 1 Timeout counter counts at the frequency of the I2C module clock #1 SIICAEN Second I2C Address Enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 ALERTEN SMBus Alert Response Address Enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK Enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. #1 A2 I2C Address Register 2 0x9 8 read-write 0xC2 0xFF SAD SMBus Address 1 7 read-write SLTH I2C SCL Low Timeout Register High 0xA 8 read-write 0 0xFF SSLT SSLT[15:8] 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write 0 0xFF SSLT SSLT[7:0] 0 8 read-write S2 I2C Status register 2 0xC 8 read-write 0x1 0xFF EMPTY Empty flag 0 1 read-only 0 Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer. #0 1 Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer. #1 ERROR Error flag 1 1 read-write 0 The buffer is not full and all write/read operations have no errors. #0 1 There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the buffer is busy). #1 I2C3 Inter-Integrated Circuit I2C I2C3_ 0x400E7000 0 0xD registers I2C3 91 A1 I2C Address Register 1 0 8 read-write 0 0xFF AD Address 1 7 read-write F I2C Frequency Divider register 0x1 8 read-write 0 0xFF ICR ClockRate 0 6 read-write MULT Multiplier Factor 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 C1 I2C Control Register 1 0x2 8 read-write 0 0xFF DMAEN DMA Enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 WUEN Wakeup Enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 RSTA Repeat START 2 1 write-only TXAK Transmit Acknowledge Enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). #0 1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). #1 TX Transmit Mode Select 4 1 read-write 0 Receive #0 1 Transmit #1 MST Master Mode Select 5 1 read-write 0 Slave mode #0 1 Master mode #1 IICIE I2C Interrupt Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 IICEN I2C Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 S I2C Status register 0x3 8 read-write 0x80 0xFF RXAK Receive Acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 IICIF Interrupt Flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 SRW Slave Read/Write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 RAM Range Address Match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 ARBL Arbitration Lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus Busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed As A Slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 TCF Transfer Complete Flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 D I2C Data I/O register 0x4 8 read-write 0 0xFF DATA Data 0 8 read-write C2 I2C Control Register 2 0x5 8 read-write 0 0xFF AD Slave Address 0 3 read-write RMEN Range Address Matching Enable 3 1 read-write 0 Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave Baud Rate Control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 HDRS High Drive Select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 ADEXT Address Extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General Call Address Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 FLT I2C Programmable Input Glitch Filter Register 0x6 8 read-write 0 0xFF FLT I2C Programmable Filter Factor 0 4 read-write 0 No filter/bypass #0000 STARTF I2C Bus Start Detect Flag 4 1 read-write 0 No start happens on I2C bus #0 1 Start detected on I2C bus #1 SSIE I2C Bus Stop or Start Interrupt Enable 5 1 read-write 0 Stop or start detection interrupt is disabled #0 1 Stop or start detection interrupt is enabled #1 STOPF I2C Bus Stop Detect Flag 6 1 read-write 0 No stop happens on I2C bus #0 1 Stop detected on I2C bus #1 SHEN Stop Hold Enable 7 1 read-write 0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated. #0 1 Stop holdoff is enabled. #1 RA I2C Range Address register 0x7 8 read-write 0 0xFF RAD Range Slave Address 1 7 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write 0 0xFF SHTF2IE SHTF2 Interrupt Enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SHTF2 SCL High Timeout Flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF1 SCL High Timeout Flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SLTF SCL Low Timeout Flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout Counter Clock Select 4 1 read-write 0 Timeout counter counts at the frequency of the I2C module clock / 64 #0 1 Timeout counter counts at the frequency of the I2C module clock #1 SIICAEN Second I2C Address Enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 ALERTEN SMBus Alert Response Address Enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK Enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. #1 A2 I2C Address Register 2 0x9 8 read-write 0xC2 0xFF SAD SMBus Address 1 7 read-write SLTH I2C SCL Low Timeout Register High 0xA 8 read-write 0 0xFF SSLT SSLT[15:8] 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write 0 0xFF SSLT SSLT[7:0] 0 8 read-write S2 I2C Status register 2 0xC 8 read-write 0x1 0xFF EMPTY Empty flag 0 1 read-only 0 Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer. #0 1 Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer. #1 ERROR Error flag 1 1 read-write 0 The buffer is not full and all write/read operations have no errors. #0 1 There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the buffer is busy). #1 USB0 Universal Serial Bus, OTG Capable Controller USB0_ 0x40072000 0 0x15D registers USB0 53 PERID Peripheral ID register 0 8 read-only 0x4 0xFF ID Peripheral Identification 0 6 read-only IDCOMP Peripheral ID Complement register 0x4 8 read-only 0xFB 0xFF NID Ones' complement of PERID[ID] bits. 0 6 read-only REV Peripheral Revision register 0x8 8 read-only 0x33 0xFF REV Revision 0 8 read-only ADDINFO Peripheral Additional Info register 0xC 8 read-only 0x1 0xFF IEHOST This bit is set if host mode is enabled. 0 1 read-only OTGISTAT OTG Interrupt Status register 0x10 8 read-write 0 0xFF AVBUSCHG This bit is set when a change in VBUS is detected on an A device. 0 1 read-write B_SESS_CHG This bit is set when a change in VBUS is detected on a B device. 2 1 read-write SESSVLDCHG This bit is set when a change in VBUS is detected indicating a session valid or a session no longer valid 3 1 read-write LINE_STATE_CHG This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits) are stable without change for 1 millisecond, and the value of the line state is different from the last time when the line state was stable 5 1 read-write ONEMSEC This bit is set when the 1 millisecond timer expires 6 1 read-write IDCHG This bit is set when a change in the ID Signal from the USB connector is sensed. 7 1 read-write OTGICR OTG Interrupt Control register 0x14 8 read-write 0 0xFF AVBUSEN A VBUS Valid Interrupt Enable 0 1 read-write 0 Disables the AVBUSCHG interrupt. #0 1 Enables the AVBUSCHG interrupt. #1 BSESSEN B Session END Interrupt Enable 2 1 read-write 0 Disables the B_SESS_CHG interrupt. #0 1 Enables the B_SESS_CHG interrupt. #1 SESSVLDEN Session Valid Interrupt Enable 3 1 read-write 0 Disables the SESSVLDCHG interrupt. #0 1 Enables the SESSVLDCHG interrupt. #1 LINESTATEEN Line State Change Interrupt Enable 5 1 read-write 0 Disables the LINE_STAT_CHG interrupt. #0 1 Enables the LINE_STAT_CHG interrupt. #1 ONEMSECEN One Millisecond Interrupt Enable 6 1 read-write 0 Diables the 1ms timer interrupt. #0 1 Enables the 1ms timer interrupt. #1 IDEN ID Interrupt Enable 7 1 read-write 0 The ID interrupt is disabled #0 1 The ID interrupt is enabled #1 OTGSTAT OTG Status register 0x18 8 read-write 0 0xFF AVBUSVLD A VBUS Valid 0 1 read-write 0 The VBUS voltage is below the A VBUS Valid threshold. #0 1 The VBUS voltage is above the A VBUS Valid threshold. #1 BSESSEND B Session End 2 1 read-write 0 The VBUS voltage is above the B session end threshold. #0 1 The VBUS voltage is below the B session end threshold. #1 SESS_VLD Session Valid 3 1 read-write 0 The VBUS voltage is below the B session valid threshold #0 1 The VBUS voltage is above the B session valid threshold. #1 LINESTATESTABLE Indicates that the internal signals that control the LINE_STATE_CHG field of OTGISTAT are stable for at least 1 ms 5 1 read-write 0 The LINE_STAT_CHG bit is not yet stable. #0 1 The LINE_STAT_CHG bit has been debounced and is stable. #1 ONEMSECEN This bit is reserved for the 1ms count, but it is not useful to software. 6 1 read-write ID Indicates the current state of the ID pin on the USB connector 7 1 read-write 0 Indicates a Type A cable is plugged into the USB connector. #0 1 Indicates no cable is attached or a Type B cable is plugged into the USB connector. #1 OTGCTL OTG Control register 0x1C 8 read-write 0 0xFF OTGEN On-The-Go pullup/pulldown resistor enable 2 1 read-write 0 If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+ and D- Data Line pull-down resistors are engaged. #0 1 The pull-up and pull-down controls in this register are used. #1 DMLOW D- Data Line pull-down resistor enable 4 1 read-write 0 D- pulldown resistor is not enabled. #0 1 D- pulldown resistor is enabled. #1 DPLOW D+ Data Line pull-down resistor enable 5 1 read-write 0 D+ pulldown resistor is not enabled. #0 1 D+ pulldown resistor is enabled. #1 DPHIGH D+ Data Line pullup resistor enable 7 1 read-write 0 D+ pullup resistor is not enabled #0 1 D+ pullup resistor is enabled #1 ISTAT Interrupt Status register 0x80 8 read-write 0 0xFF USBRST This bit is set when the USB Module has decoded a valid USB reset 0 1 read-write ERROR This bit is set when any of the error conditions within Error Interrupt Status (ERRSTAT) register occur 1 1 read-write SOFTOK This bit is set when the USB Module receives a Start Of Frame (SOF) token 2 1 read-write TOKDNE This bit is set when the current token being processed has completed 3 1 read-write SLEEP This bit is set when the USB Module detects a constant idle on the USB bus for 3 ms 4 1 read-write RESUME This bit is set when a K-state is observed on the DP/DM signals for 2 5 1 read-write ATTACH Attach Interrupt 6 1 read-write 0 No Attach is detected since the last time the ATTACH bit was cleared. #0 1 A peripheral is now present and must be configured (a stable non-SE0 state is detected for more than 2.5 us). #1 STALL Stall Interrupt 7 1 read-write INTEN Interrupt Enable register 0x84 8 read-write 0 0xFF USBRSTEN USBRST Interrupt Enable 0 1 read-write 0 Disables the USBRST interrupt. #0 1 Enables the USBRST interrupt. #1 ERROREN ERROR Interrupt Enable 1 1 read-write 0 Disables the ERROR interrupt. #0 1 Enables the ERROR interrupt. #1 SOFTOKEN SOFTOK Interrupt Enable 2 1 read-write 0 Disbles the SOFTOK interrupt. #0 1 Enables the SOFTOK interrupt. #1 TOKDNEEN TOKDNE Interrupt Enable 3 1 read-write 0 Disables the TOKDNE interrupt. #0 1 Enables the TOKDNE interrupt. #1 SLEEPEN SLEEP Interrupt Enable 4 1 read-write 0 Disables the SLEEP interrupt. #0 1 Enables the SLEEP interrupt. #1 RESUMEEN RESUME Interrupt Enable 5 1 read-write 0 Disables the RESUME interrupt. #0 1 Enables the RESUME interrupt. #1 ATTACHEN ATTACH Interrupt Enable 6 1 read-write 0 Disables the ATTACH interrupt. #0 1 Enables the ATTACH interrupt. #1 STALLEN STALL Interrupt Enable 7 1 read-write 0 Diasbles the STALL interrupt. #0 1 Enables the STALL interrupt. #1 ERRSTAT Error Interrupt Status register 0x88 8 read-write 0 0xFF PIDERR This bit is set when the PID check field fails. 0 1 read-write CRC5EOF This error interrupt has two functions 1 1 read-write CRC16 This bit is set when a data packet is rejected due to a CRC16 error. 2 1 read-write DFN8 This bit is set if the data field received was not 8 bits in length 3 1 read-write BTOERR This bit is set when a bus turnaround timeout error occurs 4 1 read-write DMAERR This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given the bus before it needs to receive or transmit data 5 1 read-write OWNERR This field is valid when the USB Module is operating in peripheral mode (CTL[HOSTMODEEN]=0) 6 1 read-write BTSERR This bit is set when a bit stuff error is detected 7 1 read-write ERREN Error Interrupt Enable register 0x8C 8 read-write 0 0xFF PIDERREN PIDERR Interrupt Enable 0 1 read-write 0 Disables the PIDERR interrupt. #0 1 Enters the PIDERR interrupt. #1 CRC5EOFEN CRC5/EOF Interrupt Enable 1 1 read-write 0 Disables the CRC5/EOF interrupt. #0 1 Enables the CRC5/EOF interrupt. #1 CRC16EN CRC16 Interrupt Enable 2 1 read-write 0 Disables the CRC16 interrupt. #0 1 Enables the CRC16 interrupt. #1 DFN8EN DFN8 Interrupt Enable 3 1 read-write 0 Disables the DFN8 interrupt. #0 1 Enables the DFN8 interrupt. #1 BTOERREN BTOERR Interrupt Enable 4 1 read-write 0 Disables the BTOERR interrupt. #0 1 Enables the BTOERR interrupt. #1 DMAERREN DMAERR Interrupt Enable 5 1 read-write 0 Disables the DMAERR interrupt. #0 1 Enables the DMAERR interrupt. #1 OWNERREN OWNERR Interrupt Enable 6 1 read-write 0 Disables the OWNERR interrupt. #0 1 Enables the OWNERR interrupt. #1 BTSERREN BTSERR Interrupt Enable 7 1 read-write 0 Disables the BTSERR interrupt. #0 1 Enables the BTSERR interrupt. #1 STAT Status register 0x90 8 read-only 0 0xFF ODD This bit is set if the last buffer descriptor updated was in the odd bank of the BDT. 2 1 read-only TX Transmit Indicator 3 1 read-only 0 The most recent transaction was a receive operation. #0 1 The most recent transaction was a transmit operation. #1 ENDP This four-bit field encodes the endpoint address that received or transmitted the previous token 4 4 read-only CTL Control register 0x94 8 read-write 0 0xFF USBENSOFEN USB Enable 0 1 read-write 0 Disables the USB Module. #0 1 Enables the USB Module. #1 ODDRST Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which then specifies the EVEN BDT bank 1 1 read-write RESUME When set to 1 this bit enables the USB Module to execute resume signaling 2 1 read-write HOSTMODEEN When set to 1, this bit enables the USB Module to operate in Host mode 3 1 read-write RESET Setting this bit enables the USB Module to generate USB reset signaling 4 1 read-write TXSUSPENDTOKENBUSY In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB token 5 1 read-write SE0 Live USB Single Ended Zero signal 6 1 read-write JSTATE Live USB differential receiver JSTATE signal 7 1 read-write ADDR Address register 0x98 8 read-write 0 0xFF ADDR USB Address 0 7 read-write LSEN Low Speed Enable bit 7 1 read-write BDTPAGE1 BDT Page register 1 0x9C 8 read-write 0 0xFF BDTBA Provides address bits 15 through 9 of the BDT base address. 1 7 read-write FRMNUML Frame Number register Low 0xA0 8 read-write 0 0xFF FRM This 8-bit field and the 3-bit field in the Frame Number Register High are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory 0 8 read-write FRMNUMH Frame Number register High 0xA4 8 read-write 0 0xFF FRM This 3-bit field and the 8-bit field in the Frame Number Register Low are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory 0 3 read-write TOKEN Token register 0xA8 8 read-write 0 0xFF TOKENENDPT Holds the Endpoint address for the token command 0 4 read-write TOKENPID Contains the token type executed by the USB module. 4 4 read-write 0001 OUT Token. USB Module performs an OUT (TX) transaction. #0001 1001 IN Token. USB Module performs an In (RX) transaction. #1001 1101 SETUP Token. USB Module performs a SETUP (TX) transaction #1101 SOFTHLD SOF Threshold register 0xAC 8 read-write 0 0xFF CNT Represents the SOF count threshold in byte times when SOFDYNTHLD=0 or 8 byte times when SOFDYNTHLD=1 0 8 read-write BDTPAGE2 BDT Page Register 2 0xB0 8 read-write 0 0xFF BDTBA Provides address bits 23 through 16 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory 0 8 read-write BDTPAGE3 BDT Page Register 3 0xB4 8 read-write 0 0xFF BDTBA Provides address bits 31 through 24 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory 0 8 read-write 16 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 ENDPT%s Endpoint Control register 0xC0 8 read-write 0 0xFF EPHSHK When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint 0 1 read-write EPSTALL When set this bit indicates that the endpoint is called 1 1 read-write EPTXEN This bit, when set, enables the endpoint for TX transfers. See 2 1 read-write EPRXEN This bit, when set, enables the endpoint for RX transfers. See 3 1 read-write EPCTLDIS This bit, when set, disables control (SETUP) transfers 4 1 read-write RETRYDIS This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only 6 1 read-write HOSTWOHUB Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only 7 1 read-write 0 Low-speed device connected to Host through a hub. PRE_PID will be generated as required. #0 1 Low-speed device directly connected. No hub, or no low-speed device attached. #1 USBCTRL USB Control register 0x100 8 read-write 0xC0 0xFF UARTSEL Selects USB signals to be used as UART signals. 4 1 read-write 0 USB signals not used as UART signals. #0 1 USB signals used as UART signals. #1 UARTCHLS UART Signal Channel Select 5 1 read-write 0 USB DP/DM signals used as UART TX/RX. #0 1 USB DP/DM signals used as UART RX/TX. #1 PDE Enables the weak pulldowns on the USB transceiver. 6 1 read-write 0 Weak pulldowns are disabled on D+ and D-. #0 1 Weak pulldowns are enabled on D+ and D-. #1 SUSP Places the USB transceiver into the suspend state. 7 1 read-write 0 USB transceiver is not in suspend state. #0 1 USB transceiver is in suspend state. #1 OBSERVE USB OTG Observe register 0x104 8 read-only 0x50 0xFF DMPD Provides observability of the D- Pulldown enable at the USB transceiver. 4 1 read-only 0 D- pulldown disabled. #0 1 D- pulldown enabled. #1 DPPD Provides observability of the D+ Pulldown enable at the USB transceiver. 6 1 read-only 0 D+ pulldown disabled. #0 1 D+ pulldown enabled. #1 DPPU Provides observability of the D+ Pullup enable at the USB transceiver. 7 1 read-only 0 D+ pullup disabled. #0 1 D+ pullup enabled. #1 CONTROL USB OTG Control register 0x108 8 read-write 0 0xFF DPPULLUPNONOTG Provides control of the DP Pullup in USBOTG, if USB is configured in non-OTG device mode. 4 1 read-write 0 DP Pullup in non-OTG device mode is not enabled. #0 1 DP Pullup in non-OTG device mode is enabled. #1 USBTRC0 USB Transceiver Control register 0 0x10C 8 read-write 0 0xFF USB_RESUME_INT USB Asynchronous Interrupt 0 1 read-only 0 No interrupt was generated. #0 1 Interrupt was generated because of the USB asynchronous interrupt. #1 SYNC_DET Synchronous USB Interrupt Detect 1 1 read-only 0 Synchronous interrupt has not been detected. #0 1 Synchronous interrupt has been detected. #1 USB_CLK_RECOVERY_INT Combined USB Clock Recovery interrupt status 2 1 read-only VREDG_DET VBUS Rising Edge Interrupt Detect 3 1 read-write 0 VBUS rising edge interrupt has not been detected. #0 1 VBUS rising edge interrupt has been detected. #1 VFEDG_DET VBUS Falling Edge Interrupt Detect 4 1 read-write 0 VBUS falling edge interrupt has not been detected. #0 1 VBUS falling edge interrupt has been detected. #1 USBRESMEN Asynchronous Resume Interrupt Enable 5 1 read-write 0 USB asynchronous wakeup from suspend mode disabled. #0 1 USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+ and D- pins. This interrupt should only be enabled when the Transceiver is suspended. #1 USBRESET USB Reset 7 1 write-only 0 Normal USB module operation. #0 1 Returns the USB module to its reset state. #1 USBFRMADJUST Frame Adjust Register 0x114 8 read-write 0 0xFF ADJ Frame Adjustment 0 8 read-write MISCCTRL Miscellaneous Control register 0x12C 8 read-write 0 0xFF SOFDYNTHLD Dynamic SOF Threshold Compare mode 0 1 read-write 0 SOF_TOK interrupt is set when byte times SOF threshold is reached. #0 1 SOF_TOK interrupt is set when 8 byte times SOF threshold is reached or overstepped. #1 SOFBUSSET SOF_TOK Interrupt Generation Mode Select 1 1 read-write 0 SOF_TOK interrupt is set according to SOF threshold value. #0 1 SOF_TOK interrupt is set when SOF counter reaches 0. #1 OWNERRISODIS OWN Error Detect for ISO IN / ISO OUT Disable 2 1 read-write 0 OWN error detect for ISO IN / ISO OUT is not disabled. #0 1 OWN error detect for ISO IN / ISO OUT is disabled. #1 VREDG_EN VBUS Rising Edge Interrupt Enable 3 1 read-write 0 VBUS rising edge interrupt disabled. #0 1 VBUS rising edge interrupt enabled. #1 VFEDG_EN VBUS Falling Edge Interrupt Enable 4 1 read-write 0 VBUS falling edge interrupt disabled. #0 1 VBUS falling edge interrupt enabled. #1 CLK_RECOVER_CTRL USB Clock recovery control 0x140 8 read-write 0 0xFF RESTART_IFRTRIM_EN Restart from IFR trim value 5 1 read-write 0 Trim fine adjustment always works based on the previous updated trim fine value (default) #0 1 Trim fine restarts from the IFR trim value whenever bus_reset/bus_resume is detected or module enable is desasserted #1 RESET_RESUME_ROUGH_EN Reset/resume to rough phase enable 6 1 read-write 0 Always works in tracking phase after the 1st time rough to track transition (default) #0 1 Go back to rough stage whenever bus reset or bus resume occurs #1 CLOCK_RECOVER_EN Crystal-less USB enable 7 1 read-write 0 Disable clock recovery block (default) #0 1 Enable clock recovery block #1 CLK_RECOVER_IRC_EN IRC48M oscillator enable register 0x144 8 read-write 0x1 0xFF REG_EN IRC48M regulator enable 0 1 read-write 0 IRC48M local regulator is disabled #0 1 IRC48M local regulator is enabled (default) #1 IRC_EN IRC48M enable 1 1 read-write 0 Disable the IRC48M module (default) #0 1 Enable the IRC48M module #1 CLK_RECOVER_INT_EN Clock recovery combined interrupt enable 0x154 8 read-write 0x10 0xFF OVF_ERROR_EN Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT. 4 1 read-write 0 The interrupt will be masked #0 1 The interrupt will be enabled (default) #1 CLK_RECOVER_INT_STATUS Clock recovery separated interrupt status 0x15C 8 read-write 0 0xFF OVF_ERROR Indicates that the USB clock recovery algorithm has detected that the frequency trim adjustment needed for the IRC48M output clock is outside the available TRIM_FINE adjustment range for the IRC48M module 4 1 read-write 0 No interrupt is reported #0 1 Unmasked interrupt has been generated #1 CMP0 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP CMP0_ 0x40073000 0 0x6 registers CMP0 40 CR0 CMP Control Register 0 0 8 read-write 0 0xFF HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. #000 001 One sample must agree. The comparator output is simply sampled. #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 CR1 CMP Control Register 1 0x1 8 read-write 0 0xFF EN Comparator Module Enable 0 1 read-write 0 Analog Comparator is disabled. #0 1 Analog Comparator is enabled. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. #0 1 CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. #1 COS Comparator Output Select 2 1 read-write 0 Set the filtered comparator output (CMPO) to equal COUT. #0 1 Set the unfiltered comparator output (CMPO) to equal COUTA. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 PMODE Power Mode Select 4 1 read-write 0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 TRIGM Trigger Mode Enable 5 1 read-write 0 Trigger mode is disabled. #0 1 Trigger mode is enabled. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode is not selected. #0 1 Windowing mode is selected. #1 SE Sample Enable 7 1 read-write 0 Sampling mode is not selected. #0 1 Sampling mode is selected. #1 FPR CMP Filter Period Register 0x2 8 read-write 0 0xFF FILT_PER Filter Sample Period 0 8 read-write SCR CMP Status and Control Register 0x3 8 read-write 0 0xFF COUT Analog Comparator Output 0 1 read-only CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling-edge on COUT has not been detected. #0 1 Falling-edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising-edge on COUT has not been detected. #0 1 Rising-edge on COUT has occurred. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 DMAEN DMA Enable Control 6 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. #1 DACCR DAC Control Register 0x4 8 read-write 0 0xFF VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference. #0 1 Vin2 is selected as resistor ladder network supply reference. #1 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 MUXCR MUX Control Register 0x5 8 read-write 0 0xFF MSEL Minus Input Mux Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input Mux Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 CMP1 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP CMP1_ 0x40073008 0 0x6 registers CMP1 41 CR0 CMP Control Register 0 0 8 read-write 0 0xFF HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. #000 001 One sample must agree. The comparator output is simply sampled. #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 CR1 CMP Control Register 1 0x1 8 read-write 0 0xFF EN Comparator Module Enable 0 1 read-write 0 Analog Comparator is disabled. #0 1 Analog Comparator is enabled. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. #0 1 CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. #1 COS Comparator Output Select 2 1 read-write 0 Set the filtered comparator output (CMPO) to equal COUT. #0 1 Set the unfiltered comparator output (CMPO) to equal COUTA. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 PMODE Power Mode Select 4 1 read-write 0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 TRIGM Trigger Mode Enable 5 1 read-write 0 Trigger mode is disabled. #0 1 Trigger mode is enabled. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode is not selected. #0 1 Windowing mode is selected. #1 SE Sample Enable 7 1 read-write 0 Sampling mode is not selected. #0 1 Sampling mode is selected. #1 FPR CMP Filter Period Register 0x2 8 read-write 0 0xFF FILT_PER Filter Sample Period 0 8 read-write SCR CMP Status and Control Register 0x3 8 read-write 0 0xFF COUT Analog Comparator Output 0 1 read-only CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling-edge on COUT has not been detected. #0 1 Falling-edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising-edge on COUT has not been detected. #0 1 Rising-edge on COUT has occurred. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 DMAEN DMA Enable Control 6 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. #1 DACCR DAC Control Register 0x4 8 read-write 0 0xFF VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference. #0 1 Vin2 is selected as resistor ladder network supply reference. #1 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 MUXCR MUX Control Register 0x5 8 read-write 0 0xFF MSEL Minus Input Mux Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input Mux Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 VREF Voltage Reference VREF_ 0x40074000 0 0x2 registers TRM VREF Trim Register 0 8 read-write 0 0x40 TRIM Trim bits 0 6 read-write 000000 Min #0 111111 Max #111111 CHOPEN Chop oscillator enable. When set, internal chopping operation is enabled and the internal analog offset will be minimized. 6 1 read-write 0 Chop oscillator is disabled. #0 1 Chop oscillator is enabled. #1 SC VREF Status and Control Register 0x1 8 read-write 0 0xFF MODE_LV Buffer Mode selection 0 2 read-write 00 Bandgap on only, for stabilization and startup #00 01 High power buffer mode enabled #01 10 Low-power buffer mode enabled #10 VREFST Internal Voltage Reference stable 2 1 read-only 0 The module is disabled or not stable. #0 1 The module is stable. #1 ICOMPEN Second order curvature compensation enable 5 1 read-write 0 Disabled #0 1 Enabled #1 REGEN Regulator enable 6 1 read-write 0 Internal 1.75 V regulator is disabled. #0 1 Internal 1.75 V regulator is enabled. #1 VREFEN Internal Voltage Reference enable 7 1 read-write 0 The module is disabled. #0 1 The module is enabled. #1 LLWU Low leakage wakeup unit LLWU_ 0x4007C000 0 0x12 registers LLWU 21 PE1 LLWU Pin Enable 1 register 0 8 read-write 0 0xFF WUPE0 Wakeup Pin Enable For LLWU_P0 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE1 Wakeup Pin Enable For LLWU_P1 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE2 Wakeup Pin Enable For LLWU_P2 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE3 Wakeup Pin Enable For LLWU_P3 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE2 LLWU Pin Enable 2 register 0x1 8 read-write 0 0xFF WUPE4 Wakeup Pin Enable For LLWU_P4 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE5 Wakeup Pin Enable For LLWU_P5 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE6 Wakeup Pin Enable For LLWU_P6 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE7 Wakeup Pin Enable For LLWU_P7 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE3 LLWU Pin Enable 3 register 0x2 8 read-write 0 0xFF WUPE8 Wakeup Pin Enable For LLWU_P8 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE9 Wakeup Pin Enable For LLWU_P9 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE10 Wakeup Pin Enable For LLWU_P10 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE11 Wakeup Pin Enable For LLWU_P11 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE4 LLWU Pin Enable 4 register 0x3 8 read-write 0 0xFF WUPE12 Wakeup Pin Enable For LLWU_P12 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE13 Wakeup Pin Enable For LLWU_P13 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE14 Wakeup Pin Enable For LLWU_P14 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE15 Wakeup Pin Enable For LLWU_P15 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE5 LLWU Pin Enable 5 register 0x4 8 read-write 0 0xFF WUPE16 Wakeup Pin Enable For LLWU_P16 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE17 Wakeup Pin Enable For LLWU_P17 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE18 Wakeup Pin Enable For LLWU_P18 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE19 Wakeup Pin Enable For LLWU_P19 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE6 LLWU Pin Enable 6 register 0x5 8 read-write 0 0xFF WUPE20 Wakeup Pin Enable For LLWU_P20 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE21 Wakeup Pin Enable For LLWU_P21 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE22 Wakeup Pin Enable For LLWU_P22 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE23 Wakeup Pin Enable For LLWU_P23 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE7 LLWU Pin Enable 7 register 0x6 8 read-write 0 0xFF WUPE24 Wakeup Pin Enable For LLWU_P24 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE25 Wakeup Pin Enable For LLWU_P25 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE26 Wakeup Pin Enable For LLWU_P26 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE27 Wakeup Pin Enable For LLWU_P27 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE8 LLWU Pin Enable 8 register 0x7 8 read-write 0 0xFF WUPE28 Wakeup Pin Enable For LLWU_P28 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE29 Wakeup Pin Enable For LLWU_P29 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE30 Wakeup Pin Enable For LLWU_P30 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE31 Wakeup Pin Enable For LLWU_P31 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 ME LLWU Module Enable register 0x8 8 read-write 0 0xFF WUME0 Wakeup Module Enable For Module 0 0 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME1 Wakeup Module Enable for Module 1 1 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME2 Wakeup Module Enable For Module 2 2 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME3 Wakeup Module Enable For Module 3 3 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME4 Wakeup Module Enable For Module 4 4 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME5 Wakeup Module Enable For Module 5 5 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME6 Wakeup Module Enable For Module 6 6 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME7 Wakeup Module Enable For Module 7 7 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 PF1 LLWU Pin Flag 1 register 0x9 8 read-write 0 0xFF WUF0 Wakeup Flag For LLWU_P0 0 1 read-write 0 LLWU_P0 input was not a wakeup source #0 1 LLWU_P0 input was a wakeup source #1 WUF1 Wakeup Flag For LLWU_P1 1 1 read-write 0 LLWU_P1 input was not a wakeup source #0 1 LLWU_P1 input was a wakeup source #1 WUF2 Wakeup Flag For LLWU_P2 2 1 read-write 0 LLWU_P2 input was not a wakeup source #0 1 LLWU_P2 input was a wakeup source #1 WUF3 Wakeup Flag For LLWU_P3 3 1 read-write 0 LLWU_P3 input was not a wakeup source #0 1 LLWU_P3 input was a wakeup source #1 WUF4 Wakeup Flag For LLWU_P4 4 1 read-write 0 LLWU_P4 input was not a wakeup source #0 1 LLWU_P4 input was a wakeup source #1 WUF5 Wakeup Flag For LLWU_P5 5 1 read-write 0 LLWU_P5 input was not a wakeup source #0 1 LLWU_P5 input was a wakeup source #1 WUF6 Wakeup Flag For LLWU_P6 6 1 read-write 0 LLWU_P6 input was not a wakeup source #0 1 LLWU_P6 input was a wakeup source #1 WUF7 Wakeup Flag For LLWU_P7 7 1 read-write 0 LLWU_P7 input was not a wakeup source #0 1 LLWU_P7 input was a wakeup source #1 PF2 LLWU Pin Flag 2 register 0xA 8 read-write 0 0xFF WUF8 Wakeup Flag For LLWU_P8 0 1 read-write 0 LLWU_P8 input was not a wakeup source #0 1 LLWU_P8 input was a wakeup source #1 WUF9 Wakeup Flag For LLWU_P9 1 1 read-write 0 LLWU_P9 input was not a wakeup source #0 1 LLWU_P9 input was a wakeup source #1 WUF10 Wakeup Flag For LLWU_P10 2 1 read-write 0 LLWU_P10 input was not a wakeup source #0 1 LLWU_P10 input was a wakeup source #1 WUF11 Wakeup Flag For LLWU_P11 3 1 read-write 0 LLWU_P11 input was not a wakeup source #0 1 LLWU_P11 input was a wakeup source #1 WUF12 Wakeup Flag For LLWU_P12 4 1 read-write 0 LLWU_P12 input was not a wakeup source #0 1 LLWU_P12 input was a wakeup source #1 WUF13 Wakeup Flag For LLWU_P13 5 1 read-write 0 LLWU_P13 input was not a wakeup source #0 1 LLWU_P13 input was a wakeup source #1 WUF14 Wakeup Flag For LLWU_P14 6 1 read-write 0 LLWU_P14 input was not a wakeup source #0 1 LLWU_P14 input was a wakeup source #1 WUF15 Wakeup Flag For LLWU_P15 7 1 read-write 0 LLWU_P15 input was not a wakeup source #0 1 LLWU_P15 input was a wakeup source #1 PF3 LLWU Pin Flag 3 register 0xB 8 read-write 0 0xFF WUF16 Wakeup Flag For LLWU_P16 0 1 read-write 0 LLWU_P16 input was not a wakeup source #0 1 LLWU_P16 input was a wakeup source #1 WUF17 Wakeup Flag For LLWU_P17 1 1 read-write 0 LLWU_P17 input was not a wakeup source #0 1 LLWU_P17 input was a wakeup source #1 WUF18 Wakeup Flag For LLWU_P18 2 1 read-write 0 LLWU_P18 input was not a wakeup source #0 1 LLWU_P18 input was a wakeup source #1 WUF19 Wakeup Flag For LLWU_P19 3 1 read-write 0 LLWU_P19 input was not a wakeup source #0 1 LLWU_P19 input was a wakeup source #1 WUF20 Wakeup Flag For LLWU_P20 4 1 read-write 0 LLWU_P20 input was not a wakeup source #0 1 LLWU_P20 input was a wakeup source #1 WUF21 Wakeup Flag For LLWU_P21 5 1 read-write 0 LLWU_P21 input was not a wakeup source #0 1 LLWU_P21 input was a wakeup source #1 WUF22 Wakeup Flag For LLWU_P22 6 1 read-write 0 LLWU_P22 input was not a wakeup source #0 1 LLWU_P22 input was a wakeup source #1 WUF23 Wakeup Flag For LLWU_P23 7 1 read-write 0 LLWU_P23 input was not a wakeup source #0 1 LLWU_P23 input was a wakeup source #1 PF4 LLWU Pin Flag 4 register 0xC 8 read-write 0 0xFF WUF24 Wakeup Flag For LLWU_P24 0 1 read-write 0 LLWU_P24 input was not a wakeup source #0 1 LLWU_P24 input was a wakeup source #1 WUF25 Wakeup Flag For LLWU_P25 1 1 read-write 0 LLWU_P25 input was not a wakeup source #0 1 LLWU_P25 input was a wakeup source #1 WUF26 Wakeup Flag For LLWU_P26 2 1 read-write 0 LLWU_P26 input was not a wakeup source #0 1 LLWU_P26 input was a wakeup source #1 WUF27 Wakeup Flag For LLWU_P27 3 1 read-write 0 LLWU_P27 input was not a wakeup source #0 1 LLWU_P27 input was a wakeup source #1 WUF28 Wakeup Flag For LLWU_P28 4 1 read-write 0 LLWU_P28 input was not a wakeup source #0 1 LLWU_P28 input was a wakeup source #1 WUF29 Wakeup Flag For LLWU_P29 5 1 read-write 0 LLWU_P29 input was not a wakeup source #0 1 LLWU_P29 input was a wakeup source #1 WUF30 Wakeup Flag For LLWU_P30 6 1 read-write 0 LLWU_P30 input was not a wakeup source #0 1 LLWU_P30 input was a wakeup source #1 WUF31 Wakeup Flag For LLWU_P31 7 1 read-write 0 LLWU_P31 input was not a wakeup source #0 1 LLWU_P31 input was a wakeup source #1 MF5 LLWU Module Flag 5 register 0xD 8 read-only 0 0xFF MWUF0 Wakeup flag For module 0 0 1 read-only 0 Module 0 input was not a wakeup source #0 1 Module 0 input was a wakeup source #1 MWUF1 Wakeup flag For module 1 1 1 read-only 0 Module 1 input was not a wakeup source #0 1 Module 1 input was a wakeup source #1 MWUF2 Wakeup flag For module 2 2 1 read-only 0 Module 2 input was not a wakeup source #0 1 Module 2 input was a wakeup source #1 MWUF3 Wakeup flag For module 3 3 1 read-only 0 Module 3 input was not a wakeup source #0 1 Module 3 input was a wakeup source #1 MWUF4 Wakeup flag For module 4 4 1 read-only 0 Module 4 input was not a wakeup source #0 1 Module 4 input was a wakeup source #1 MWUF5 Wakeup flag For module 5 5 1 read-only 0 Module 5 input was not a wakeup source #0 1 Module 5 input was a wakeup source #1 MWUF6 Wakeup flag For module 6 6 1 read-only 0 Module 6 input was not a wakeup source #0 1 Module 6 input was a wakeup source #1 MWUF7 Wakeup flag For module 7 7 1 read-only 0 Module 7 input was not a wakeup source #0 1 Module 7 input was a wakeup source #1 FILT1 LLWU Pin Filter 1 register 0xE 8 read-write 0 0xFF FILTSEL Filter Pin Select 0 5 read-write 00000 Select LLWU_P0 for filter #00000 11111 Select LLWU_P31 for filter #11111 FILTE Digital Filter On External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 1 was not a wakeup source #0 1 Pin Filter 1 was a wakeup source #1 FILT2 LLWU Pin Filter 2 register 0xF 8 read-write 0 0xFF FILTSEL Filter Pin Select 0 5 read-write 00000 Select LLWU_P0 for filter #00000 11111 Select LLWU_P31 for filter #11111 FILTE Digital Filter On External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 2 was not a wakeup source #0 1 Pin Filter 2 was a wakeup source #1 FILT3 LLWU Pin Filter 3 register 0x10 8 read-write 0 0xFF FILTSEL Filter Pin Select 0 5 read-write 00000 Select LLWU_P0 for filter #00000 11111 Select LLWU_P31 for filter #11111 FILTE Digital Filter On External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 3 was not a wakeup source #0 1 Pin Filter 3 was a wakeup source #1 FILT4 LLWU Pin Filter 4 register 0x11 8 read-write 0 0xFF FILTSEL Filter Pin Select 0 5 read-write 00000 Select LLWU_P0 for filter #00000 11111 Select LLWU_P31 for filter #11111 FILTE Digital Filter On External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 4 was not a wakeup source #0 1 Pin Filter 4 was a wakeup source #1 PMC Power Management Controller PMC_ 0x4007D000 0 0xC registers LVD_LVW 20 LVDSC1 Low Voltage Detect Status And Control 1 register 0 8 read-write 0x10 0xFF LVDV Low-Voltage Detect Voltage Select 0 2 read-write 00 Low trip point selected (V LVD = V LVDL ) #00 01 High trip point selected (V LVD = V LVDH ) #01 LVDRE Low-Voltage Detect Reset Enable 4 1 read-write 0 LVDF does not generate hardware resets #0 1 Force an MCU reset when LVDF = 1 #1 LVDIE Low-Voltage Detect Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVDF = 1 #1 LVDACK Low-Voltage Detect Acknowledge 6 1 write-only LVDF Low-Voltage Detect Flag 7 1 read-only 0 Low-voltage event not detected #0 1 Low-voltage event detected #1 LVDSC2 Low Voltage Detect Status And Control 2 register 0x1 8 read-write 0 0xFF LVWV Low-Voltage Warning Voltage Select 0 2 read-write 00 Low trip point selected (VLVW = VLVW1) #00 01 Mid 1 trip point selected (VLVW = VLVW2) #01 10 Mid 2 trip point selected (VLVW = VLVW3) #10 11 High trip point selected (VLVW = VLVW4) #11 LVWIE Low-Voltage Warning Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVWF = 1 #1 LVWACK Low-Voltage Warning Acknowledge 6 1 write-only LVWF Low-Voltage Warning Flag 7 1 read-only 0 Low-voltage warning event not detected #0 1 Low-voltage warning event detected #1 REGSC Regulator Status And Control register 0x2 8 read-write 0x4 0xFF BGBE Bandgap Buffer Enable 0 1 read-write 0 Bandgap buffer not enabled #0 1 Bandgap buffer enabled #1 REGONS Regulator In Run Regulation Status 2 1 read-only 0 Regulator is in stop regulation or in transition to/from it #0 1 Regulator is in run regulation #1 ACKISO Acknowledge Isolation 3 1 read-write 0 Peripherals and I/O pads are in normal run state. #0 1 Certain peripherals and I/O pads are in an isolated and latched state. #1 BGEN Bandgap Enable In VLPx Operation 4 1 read-write 0 Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes. #0 1 Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes. #1 HVDSC1 High Voltage Detect Status And Control 1 register 0xB 8 read-write 0x1 0xFF HVDV High-Voltage Detect Voltage Select 0 1 read-write 0 Low trip point selected (V HVD = V HVDL ) #0 1 High trip point selected (V HVD = V HVDH ) #1 HVDRE High-Voltage Detect Reset Enable 4 1 read-write 0 HVDF does not generate hardware resets #0 1 Force an MCU reset when HVDF = 1 #1 HVDIE High-Voltage Detect Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when HVDF = 1 #1 HVDACK High-Voltage Detect Acknowledge 6 1 write-only HVDF High-Voltage Detect Flag 7 1 read-only 0 High-voltage event not detected #0 1 High-voltage event detected #1 SMC System Mode Controller SMC_ 0x4007E000 0 0x4 registers PMPROT Power Mode Protection register 0 8 read-write 0x20 0xFF AVLLS Allow Very-Low-Leakage Stop Mode 1 1 read-write 0 Any VLLSx mode is not allowed #0 1 Any VLLSx mode is allowed #1 ALLS Allow Low-Leakage Stop Mode 3 1 read-write 0 Any LLSx mode is not allowed #0 1 Any LLSx mode is allowed #1 AVLP Allow Very-Low-Power Modes 5 1 read-write 0 VLPR, VLPW, and VLPS are not allowed. #0 1 VLPR, VLPW, and VLPS are allowed. #1 AHSRUN Allow High Speed Run mode 7 1 read-write 0 HSRUN is not allowed #0 1 HSRUN is allowed #1 PMCTRL Power Mode Control register 0x1 8 read-write 0x40 0xFF STOPM Stop Mode Control 0 3 read-write 000 Normal Stop (STOP) #000 010 Very-Low-Power Stop (VLPS) #010 011 Low-Leakage Stop (LLSx) #011 100 Very-Low-Leakage Stop (VLLSx) #100 110 Reseved #110 STOPA Stop Aborted 3 1 read-only 0 The previous stop mode entry was successsful. #0 1 The previous stop mode entry was aborted. #1 RUNM Run Mode Control 5 2 read-write 00 Normal Run mode (RUN) #00 10 Very-Low-Power Run mode (VLPR) #10 11 High Speed Run mode (HSRUN) #11 STOPCTRL Stop Control Register 0x2 8 read-write 0x3 0xFF LLSM LLS or VLLS Mode Control 0 3 read-write 000 VLLS0 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx #000 001 VLLS1 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx #001 010 VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx #010 011 VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx #011 LPOPO LPO Power Option 3 1 read-write 0 LPO clock is enabled in LLS/VLLSx #0 1 LPO clock is disabled in LLS/VLLSx #1 RAM2PO RAM2 Power Option 4 1 read-write 0 RAM2 not powered in LLS2/VLLS2 #0 1 RAM2 powered in LLS2/VLLS2 #1 PORPO POR Power Option 5 1 read-write 0 POR detect circuit is enabled in VLLS0 #0 1 POR detect circuit is disabled in VLLS0 #1 PSTOPO Partial Stop Option 6 2 read-write 00 STOP - Normal Stop mode #00 01 PSTOP1 - Partial Stop with both system and bus clocks disabled #01 10 PSTOP2 - Partial Stop with system clock disabled and bus clock enabled #10 PMSTAT Power Mode Status register 0x3 8 read-only 0x4 0xFF PMSTAT Power Mode Status 0 8 read-only RCM Reset Control Module RCM_ 0x4007F000 0 0xA registers SRS0 System Reset Status Register 0 0 8 read-only 0x82 0xFF WAKEUP Low Leakage Wakeup Reset 0 1 read-only 0 Reset not caused by LLWU module wakeup source #0 1 Reset caused by LLWU module wakeup source #1 LVD Low-Voltage Detect Reset 1 1 read-only 0 Reset not caused by LVD trip or POR #0 1 Reset caused by LVD trip or POR #1 LOC Loss-of-Clock Reset 2 1 read-only 0 Reset not caused by a loss of external clock. #0 1 Reset caused by a loss of external clock. #1 LOL Loss-of-Lock Reset 3 1 read-only 0 Reset not caused by a loss of lock in the PLL #0 1 Reset caused by a loss of lock in the PLL #1 WDOG Watchdog 5 1 read-only 0 Reset not caused by watchdog timeout #0 1 Reset caused by watchdog timeout #1 PIN External Reset Pin 6 1 read-only 0 Reset not caused by external reset pin #0 1 Reset caused by external reset pin #1 POR Power-On Reset 7 1 read-only 0 Reset not caused by POR #0 1 Reset caused by POR #1 SRS1 System Reset Status Register 1 0x1 8 read-only 0 0xFF JTAG JTAG Generated Reset 0 1 read-only 0 Reset not caused by JTAG #0 1 Reset caused by JTAG #1 LOCKUP Core Lockup 1 1 read-only 0 Reset not caused by core LOCKUP event #0 1 Reset caused by core LOCKUP event #1 SW Software 2 1 read-only 0 Reset not caused by software setting of SYSRESETREQ bit #0 1 Reset caused by software setting of SYSRESETREQ bit #1 MDM_AP MDM-AP System Reset Request 3 1 read-only 0 Reset not caused by host debugger system setting of the System Reset Request bit #0 1 Reset caused by host debugger system setting of the System Reset Request bit #1 SACKERR Stop Mode Acknowledge Error Reset 5 1 read-only 0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode #0 1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode #1 TAMPER Tamper detect 7 1 read-only 0 Reset not caused by tamper detect #0 1 Reset caused by tamper detect. #1 RPFC Reset Pin Filter Control register 0x4 8 read-write 0 0xFF RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes 0 2 read-write 00 All filtering disabled #00 01 Bus clock filter enabled for normal operation #01 10 LPO clock filter enabled for normal operation #10 RSTFLTSS Reset Pin Filter Select in Stop Mode 2 1 read-write 0 All filtering disabled #0 1 LPO clock filter enabled #1 RPFW Reset Pin Filter Width register 0x5 8 read-write 0 0xFF RSTFLTSEL Reset Pin Filter Bus Clock Select 0 5 read-write 00000 Bus clock filter count is 1 #00000 00001 Bus clock filter count is 2 #00001 00010 Bus clock filter count is 3 #00010 00011 Bus clock filter count is 4 #00011 00100 Bus clock filter count is 5 #00100 00101 Bus clock filter count is 6 #00101 00110 Bus clock filter count is 7 #00110 00111 Bus clock filter count is 8 #00111 01000 Bus clock filter count is 9 #01000 01001 Bus clock filter count is 10 #01001 01010 Bus clock filter count is 11 #01010 01011 Bus clock filter count is 12 #01011 01100 Bus clock filter count is 13 #01100 01101 Bus clock filter count is 14 #01101 01110 Bus clock filter count is 15 #01110 01111 Bus clock filter count is 16 #01111 10000 Bus clock filter count is 17 #10000 10001 Bus clock filter count is 18 #10001 10010 Bus clock filter count is 19 #10010 10011 Bus clock filter count is 20 #10011 10100 Bus clock filter count is 21 #10100 10101 Bus clock filter count is 22 #10101 10110 Bus clock filter count is 23 #10110 10111 Bus clock filter count is 24 #10111 11000 Bus clock filter count is 25 #11000 11001 Bus clock filter count is 26 #11001 11010 Bus clock filter count is 27 #11010 11011 Bus clock filter count is 28 #11011 11100 Bus clock filter count is 29 #11100 11101 Bus clock filter count is 30 #11101 11110 Bus clock filter count is 31 #11110 11111 Bus clock filter count is 32 #11111 FM Force Mode Register 0x6 8 read-write 0 0xFF FORCEROM Force ROM Boot 1 2 read-write 00 No effect #00 01 Force boot from ROM with RCM_MR[1] set. #01 10 Force boot from ROM with RCM_MR[2] set. #10 11 Force boot from ROM with RCM_MR[2:1] set. #11 MR Mode Register 0x7 8 read-write 0 0xFF BOOTROM Boot ROM Configuration 1 2 read-write 00 Boot from Flash #00 01 Boot from ROM due to BOOTCFG0 pin assertion #01 10 Boot form ROM due to FOPT[7] configuration #10 11 Boot from ROM due to both BOOTCFG0 pin assertion and FOPT[7] configuration #11 SSRS0 Sticky System Reset Status Register 0 0x8 8 read-write 0x82 0xFF SWAKEUP Sticky Low Leakage Wakeup Reset 0 1 read-write 0 Reset not caused by LLWU module wakeup source #0 1 Reset caused by LLWU module wakeup source #1 SLVD Sticky Low-Voltage Detect Reset 1 1 read-write 0 Reset not caused by LVD trip or POR #0 1 Reset caused by LVD trip or POR #1 SLOC Sticky Loss-of-Clock Reset 2 1 read-write 0 Reset not caused by a loss of external clock. #0 1 Reset caused by a loss of external clock. #1 SLOL Sticky Loss-of-Lock Reset 3 1 read-write 0 Reset not caused by a loss of lock in the PLL #0 1 Reset caused by a loss of lock in the PLL #1 SWDOG Sticky Watchdog 5 1 read-write 0 Reset not caused by watchdog timeout #0 1 Reset caused by watchdog timeout #1 SPIN Sticky External Reset Pin 6 1 read-write 0 Reset not caused by external reset pin #0 1 Reset caused by external reset pin #1 SPOR Sticky Power-On Reset 7 1 read-write 0 Reset not caused by POR #0 1 Reset caused by POR #1 SSRS1 Sticky System Reset Status Register 1 0x9 8 read-write 0 0xFF SJTAG Sticky JTAG Generated Reset 0 1 read-write 0 Reset not caused by JTAG #0 1 Reset caused by JTAG #1 SLOCKUP Sticky Core Lockup 1 1 read-write 0 Reset not caused by core LOCKUP event #0 1 Reset caused by core LOCKUP event #1 SSW Sticky Software 2 1 read-write 0 Reset not caused by software setting of SYSRESETREQ bit #0 1 Reset caused by software setting of SYSRESETREQ bit #1 SMDM_AP Sticky MDM-AP System Reset Request 3 1 read-write 0 Reset not caused by host debugger system setting of the System Reset Request bit #0 1 Reset caused by host debugger system setting of the System Reset Request bit #1 SSACKERR Sticky Stop Mode Acknowledge Error Reset 5 1 read-write 0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode #0 1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode #1 STAMPER Sticky Tamper detect 7 1 read-write 0 Reset not caused by tamper detect #0 1 Reset caused by tamper detect. #1 TRNG0 RNG 0x400A0000 0 0xF8 registers TRNG0 23 TRNG0_MCTL RNG Miscellaneous Control Register 0 32 read-write 0x12001 0xFFFFFFFF SAMP_MODE Sample Mode 0 2 read-write 00 use Von Neumann data into both Entropy shifter and Statistical Checker #00 01 use raw data into both Entropy shifter and Statistical Checker #01 10 use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker #10 OSC_DIV Oscillator Divide 2 2 read-write 00 use ring oscillator with no divide #00 01 use ring oscillator divided-by-2 #01 10 use ring oscillator divided-by-4 #10 11 use ring oscillator divided-by-8 #11 UNUSED This bit is unused but write-able. Must be left as zero. 4 1 read-write TRNG_ACC TRNG Access Mode 5 1 read-write RST_DEF Reset Defaults 6 1 write-only FOR_SCLK Force System Clock 7 1 read-write FCT_FAIL Read only: Frequency Count Fail 8 1 read-only FCT_VAL Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT. 9 1 read-only ENT_VAL Read only: Entropy Valid 10 1 read-only TST_OUT Read only: Test point inside ring oscillator. 11 1 read-only ERR Read: Error status 12 1 read-write TSTOP_OK TRNG_OK_TO_STOP 13 1 read-only PRGM Programming Mode Select 16 1 read-write TRNG0_SCMISC RNG Statistical Check Miscellaneous Register 0x4 32 read-write 0x1001F 0xFFFFFFFF LRUN_MAX LONG RUN MAX LIMIT 0 8 read-write RTY_CT RETRY COUNT 16 4 read-write TRNG0_PKRRNG RNG Poker Range Register 0x8 32 read-write 0x9A3 0xFFFFFFFF PKR_RNG Poker Range 0 16 read-write TRNG0_PKRMAX RNG Poker Maximum Limit Register TRNG0 0xC 32 read-write 0x6920 0xFFFFFFFF PKR_MAX Poker Maximum Limit 0 24 read-write TRNG0_PKRSQ RNG Poker Square Calculation Result Register TRNG0 0xC 32 read-only 0 0xFFFFFFFF PKR_SQ Poker Square Calculation Result 0 24 read-only TRNG0_SDCTL RNG Seed Control Register 0x10 32 read-write 0xC8009C4 0xFFFFFFFF SAMP_SIZE Sample Size 0 16 read-write ENT_DLY Entropy Delay 16 16 read-write TRNG0_SBLIM RNG Sparse Bit Limit Register TRNG0 0x14 32 read-write 0x3F 0xFFFFFFFF SB_LIM Sparse Bit Limit 0 10 read-write TRNG0_TOTSAM RNG Total Samples Register TRNG0 0x14 32 read-only 0 0xFFFFFFFF TOT_SAM Total Samples 0 20 read-only TRNG0_FRQMIN RNG Frequency Count Minimum Limit Register 0x18 32 read-write 0x640 0xFFFFFFFF FRQ_MIN Frequency Count Minimum Limit 0 22 read-write TRNG0_FRQCNT RNG Frequency Count Register TRNG0 0x1C 32 read-only 0 0xFFFFFFFF FRQ_CT Frequency Count 0 22 read-only TRNG0_FRQMAX RNG Frequency Count Maximum Limit Register TRNG0 0x1C 32 read-write 0x6400 0xFFFFFFFF FRQ_MAX Frequency Counter Maximum Limit 0 22 read-write TRNG0_SCMC RNG Statistical Check Monobit Count Register TRNG0 0x20 32 read-only 0 0xFFFFFFFF MONO_CT Monobit Count 0 16 read-only TRNG0_SCML RNG Statistical Check Monobit Limit Register TRNG0 0x20 32 read-write 0x10C0568 0xFFFFFFFF MONO_MAX Monobit Maximum Limit 0 16 read-write MONO_RNG Monobit Range 16 16 read-write TRNG0_SCR1C RNG Statistical Check Run Length 1 Count Register TRNG0 0x24 32 read-only 0 0xFFFFFFFF R1_0_CT Runs of Zero, Length 1 Count 0 15 read-only R1_1_CT Runs of One, Length 1 Count 16 15 read-only TRNG0_SCR1L RNG Statistical Check Run Length 1 Limit Register TRNG0 0x24 32 read-write 0xB20195 0xFFFFFFFF RUN1_MAX Run Length 1 Maximum Limit 0 15 read-write RUN1_RNG Run Length 1 Range 16 15 read-write TRNG0_SCR2C RNG Statistical Check Run Length 2 Count Register TRNG0 0x28 32 read-only 0 0xFFFFFFFF R2_0_CT Runs of Zero, Length 2 Count 0 14 read-only R2_1_CT Runs of One, Length 2 Count 16 14 read-only TRNG0_SCR2L RNG Statistical Check Run Length 2 Limit Register TRNG0 0x28 32 read-write 0x7A00DC 0xFFFFFFFF RUN2_MAX Run Length 2 Maximum Limit 0 14 read-write RUN2_RNG Run Length 2 Range 16 14 read-write TRNG0_SCR3C RNG Statistical Check Run Length 3 Count Register TRNG0 0x2C 32 read-only 0 0xFFFFFFFF R3_0_CT Runs of Zeroes, Length 3 Count 0 13 read-only R3_1_CT Runs of Ones, Length 3 Count 16 13 read-only TRNG0_SCR3L RNG Statistical Check Run Length 3 Limit Register TRNG0 0x2C 32 read-write 0x58007D 0xFFFFFFFF RUN3_MAX Run Length 3 Maximum Limit 0 13 read-write RUN3_RNG Run Length 3 Range 16 13 read-write TRNG0_SCR4C RNG Statistical Check Run Length 4 Count Register TRNG0 0x30 32 read-only 0 0xFFFFFFFF R4_0_CT Runs of Zero, Length 4 Count 0 12 read-only R4_1_CT Runs of One, Length 4 Count 16 12 read-only TRNG0_SCR4L RNG Statistical Check Run Length 4 Limit Register TRNG0 0x30 32 read-write 0x40004B 0xFFFFFFFF RUN4_MAX Run Length 4 Maximum Limit 0 12 read-write RUN4_RNG Run Length 4 Range 16 12 read-write TRNG0_SCR5C RNG Statistical Check Run Length 5 Count Register TRNG0 0x34 32 read-only 0 0xFFFFFFFF R5_0_CT Runs of Zero, Length 5 Count 0 11 read-only R5_1_CT Runs of One, Length 5 Count 16 11 read-only TRNG0_SCR5L RNG Statistical Check Run Length 5 Limit Register TRNG0 0x34 32 read-write 0x2E002F 0xFFFFFFFF RUN5_MAX Run Length 5 Maximum Limit 0 11 read-write RUN5_RNG Run Length 5 Range 16 11 read-write TRNG0_SCR6PC RNG Statistical Check Run Length 6+ Count Register TRNG0 0x38 32 read-only 0 0xFFFFFFFF R6P_0_CT Runs of Zero, Length 6+ Count 0 11 read-only R6P_1_CT Runs of One, Length 6+ Count 16 11 read-only TRNG0_SCR6PL RNG Statistical Check Run Length 6+ Limit Register TRNG0 0x38 32 read-write 0x2E002F 0xFFFFFFFF RUN6P_MAX Run Length 6+ Maximum Limit 0 11 read-write RUN6P_RNG Run Length 6+ Range 16 11 read-write TRNG0_STATUS RNG Status Register 0x3C 32 read-only 0 0xFFFFFFFF TF1BR0 Test Fail, 1-Bit Run, Sampling 0s. If TF1BR0=1, the 1-Bit Run, Sampling 0s Test has failed. 0 1 read-only TF1BR1 Test Fail, 1-Bit Run, Sampling 1s. If TF1BR1=1, the 1-Bit Run, Sampling 1s Test has failed. 1 1 read-only TF2BR0 Test Fail, 2-Bit Run, Sampling 0s. If TF2BR0=1, the 2-Bit Run, Sampling 0s Test has failed. 2 1 read-only TF2BR1 Test Fail, 2-Bit Run, Sampling 1s. If TF2BR1=1, the 2-Bit Run, Sampling 1s Test has failed. 3 1 read-only TF3BR0 Test Fail, 3-Bit Run, Sampling 0s. If TF3BR0=1, the 3-Bit Run, Sampling 0s Test has failed. 4 1 read-only TF3BR1 Test Fail, 3-Bit Run, Sampling 1s. If TF3BR1=1, the 3-Bit Run, Sampling 1s Test has failed. 5 1 read-only TF4BR0 Test Fail, 4-Bit Run, Sampling 0s. If TF4BR0=1, the 4-Bit Run, Sampling 0s Test has failed. 6 1 read-only TF4BR1 Test Fail, 4-Bit Run, Sampling 1s. If TF4BR1=1, the 4-Bit Run, Sampling 1s Test has failed. 7 1 read-only TF5BR0 Test Fail, 5-Bit Run, Sampling 0s. If TF5BR0=1, the 5-Bit Run, Sampling 0s Test has failed. 8 1 read-only TF5BR1 Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed. 9 1 read-only TF6PBR0 Test Fail, 6 Plus Bit Run, Sampling 0s 10 1 read-only TF6PBR1 Test Fail, 6 Plus Bit Run, Sampling 1s 11 1 read-only TFSB Test Fail, Sparse Bit. If TFSB=1, the Sparse Bit Test has failed. 12 1 read-only TFLR Test Fail, Long Run. If TFLR=1, the Long Run Test has failed. 13 1 read-only TFP Test Fail, Poker. If TFP=1, the Poker Test has failed. 14 1 read-only TFMB Test Fail, Mono Bit. If TFMB=1, the Mono Bit Test has failed. 15 1 read-only RETRY_CT RETRY COUNT 16 4 read-only TRNG0_ENT0 RNG TRNG Entropy Read Register 0x40 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT1 RNG TRNG Entropy Read Register 0x44 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT2 RNG TRNG Entropy Read Register 0x48 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT3 RNG TRNG Entropy Read Register 0x4C 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT4 RNG TRNG Entropy Read Register 0x50 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT5 RNG TRNG Entropy Read Register 0x54 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT6 RNG TRNG Entropy Read Register 0x58 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT7 RNG TRNG Entropy Read Register 0x5C 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT8 RNG TRNG Entropy Read Register 0x60 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT9 RNG TRNG Entropy Read Register 0x64 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT10 RNG TRNG Entropy Read Register 0x68 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT11 RNG TRNG Entropy Read Register 0x6C 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT12 RNG TRNG Entropy Read Register 0x70 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT13 RNG TRNG Entropy Read Register 0x74 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT14 RNG TRNG Entropy Read Register 0x78 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_ENT15 RNG TRNG Entropy Read Register 0x7C 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only TRNG0_PKRCNT10 RNG Statistical Check Poker Count 1 and 0 Register 0x80 32 read-only 0 0xFFFFFFFF PKR_0_CT Poker 0h Count 0 16 read-only PKR_1_CT Poker 1h Count 16 16 read-only TRNG0_PKRCNT32 RNG Statistical Check Poker Count 3 and 2 Register 0x84 32 read-only 0 0xFFFFFFFF PKR_2_CT Poker 2h Count 0 16 read-only PKR_3_CT Poker 3h Count 16 16 read-only TRNG0_PKRCNT54 RNG Statistical Check Poker Count 5 and 4 Register 0x88 32 read-only 0 0xFFFFFFFF PKR_4_CT Poker 4h Count 0 16 read-only PKR_5_CT Poker 5h Count 16 16 read-only TRNG0_PKRCNT76 RNG Statistical Check Poker Count 7 and 6 Register 0x8C 32 read-only 0 0xFFFFFFFF PKR_6_CT Poker 6h Count 0 16 read-only PKR_7_CT Poker 7h Count 16 16 read-only TRNG0_PKRCNT98 RNG Statistical Check Poker Count 9 and 8 Register 0x90 32 read-only 0 0xFFFFFFFF PKR_8_CT Poker 8h Count 0 16 read-only PKR_9_CT Poker 9h Count 16 16 read-only TRNG0_PKRCNTBA RNG Statistical Check Poker Count B and A Register 0x94 32 read-only 0 0xFFFFFFFF PKR_A_CT Poker Ah Count 0 16 read-only PKR_B_CT Poker Bh Count 16 16 read-only TRNG0_PKRCNTDC RNG Statistical Check Poker Count D and C Register 0x98 32 read-only 0 0xFFFFFFFF PKR_C_CT Poker Ch Count 0 16 read-only PKR_D_CT Poker Dh Count 16 16 read-only TRNG0_PKRCNTFE RNG Statistical Check Poker Count F and E Register 0x9C 32 read-only 0 0xFFFFFFFF PKR_E_CT Poker Eh Count 0 16 read-only PKR_F_CT Poker Fh Count 16 16 read-only TRNG0_SEC_CFG RNG Security Configuration Register 0xB0 32 read-write 0 0xFFFFFFFF SH0 Reserved. DRNG specific, not applicable to this version. 0 1 read-write 0 See DRNG version. #0 1 See DRNG version. #1 NO_PRGM If set the TRNG registers cannot be programmed 1 1 read-write 0 Programability of registers controlled only by the RNG Miscellaneous Control Register's access mode bit. #0 1 Overides RNG Miscellaneous Control Register access mode and prevents TRNG register programming. #1 SK_VAL Reserved. DRNG-specific, not applicable to this version. 2 1 read-write 0 See DRNG version. #0 1 See DRNG version. #1 TRNG0_INT_CTRL RNG Interrupt Control Register 0xB4 32 read-write 0xFFFFFFFF 0xFFFFFFFF HW_ERR Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. 0 1 read-write 0 Corresponding bit of INT_STATUS cleared. #0 1 Corresponding bit of INT_STATUS active. #1 ENT_VAL Same behavior as bit 0 above. 1 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 FRQ_CT_FAIL Same behavior as bit 0 above. 2 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 UNUSED Reserved but writeable. 3 29 read-write TRNG0_INT_MASK RNG Mask Register 0xB8 32 read-write 0 0xFFFFFFFF HW_ERR Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. 0 1 read-write 0 Corresponding interrupt of INT_STATUS is masked. #0 1 Corresponding bit of INT_STATUS is active. #1 ENT_VAL Same behavior as bit 0 above. 1 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 FRQ_CT_FAIL Same behavior as bit 0 above. 2 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 TRNG0_INT_STATUS RNG Interrupt Status Register 0xBC 32 read-write 0 0xFFFFFFFF HW_ERR Read: Error status 0 1 read-only 0 no error #0 1 error detected. #1 ENT_VAL Read only: Entropy Valid 1 1 read-only 0 Busy generation entropy. Any value read is invalid. #0 1 TRNG can be stopped and entropy is valid if read. #1 FRQ_CT_FAIL Read only: Frequency Count Fail 2 1 read-write 0 No hardware nor self test frequency errors. #0 1 The frequency counter has detected a failure. #1 TRNG0_VID1 RNG Version ID Register (MS) 0xF0 32 read-only 0x300100 0xFFFFFFFF RNG_MIN_REV Shows the Freescale IP's Minor revision of the TRNG. 0 8 read-only 0x00 Minor revision number for TRNG. #0 RNG_MAJ_REV Shows the Freescale IP's Major revision of the TRNG. 8 8 read-only 0x01 Major revision number for TRNG. #1 RNG_IP_ID Shows the Freescale IP ID. 16 16 read-only TRNG0_VID2 RNG Version ID Register (LS) 0xF4 32 read-only 0 0xFFFFFFFF RNG_CONFIG_OPT Shows the Freescale IP's Configuaration options for the TRNG. 0 8 read-only 0x00 TRNG_CONFIG_OPT for TRNG. #0 RNG_ECO_REV Shows the Freescale IP's ECO revision of the TRNG. 8 8 read-only 0x00 TRNG_ECO_REV for TRNG. #0 RNG_INTG_OPT Shows the Freescale integration options for the TRNG. 16 8 read-only 0x00 INTG_OPT for TRNG. #0 RNG_ERA Shows the Freescale compile options for the TRNG. 24 8 read-only 0x00 COMPILE_OPT for TRNG. #0 SDHC Secured Digital Host Controller SDHC_ 0x400B1000 0 0x100 registers SDHC 81 DSADDR DMA System Address register 0 32 read-write 0 0xFFFFFFFF DSADDR DMA System Address 2 30 read-write BLKATTR Block Attributes register 0x4 32 read-write 0 0xFFFFFFFF BLKSIZE Transfer Block Size 0 13 read-write 0 No data transfer. #0 1 1 Byte #1 10 2 Bytes #10 11 3 Bytes #11 100 4 Bytes #100 111111111 511 Bytes #111111111 1000000000 512 Bytes #1000000000 100000000000 2048 Bytes #100000000000 1000000000000 4096 Bytes #1000000000000 BLKCNT Blocks Count For Current Transfer 16 16 read-write 0 Stop count. #0 1 1 block #1 10 2 blocks #10 1111111111111111 65535 blocks #1111111111111111 CMDARG Command Argument register 0x8 32 read-write 0 0xFFFFFFFF CMDARG Command Argument 0 32 read-write XFERTYP Transfer Type register 0xC 32 read-write 0 0xFFFFFFFF DMAEN DMA Enable 0 1 read-write 0 Disable #0 1 Enable #1 BCEN Block Count Enable 1 1 read-write 0 Disable #0 1 Enable #1 AC12EN Auto CMD12 Enable 2 1 read-write 0 Disable #0 1 Enable #1 DTDSEL Data Transfer Direction Select 4 1 read-write 0 Write host to card. #0 1 Read card to host. #1 MSBSEL Multi/Single Block Select 5 1 read-write 0 Single block. #0 1 Multiple blocks. #1 RSPTYP Response Type Select 16 2 read-write 00 No response. #00 01 Response length 136. #01 10 Response length 48. #10 11 Response length 48, check busy after response. #11 CCCEN Command CRC Check Enable 19 1 read-write 0 Disable #0 1 Enable #1 CICEN Command Index Check Enable 20 1 read-write 0 Disable #0 1 Enable #1 DPSEL Data Present Select 21 1 read-write 0 No data present. #0 1 Data present. #1 CMDTYP Command Type 22 2 read-write 00 Normal other commands. #00 01 Suspend CMD52 for writing bus suspend in CCCR. #01 10 Resume CMD52 for writing function select in CCCR. #10 11 Abort CMD12, CMD52 for writing I/O abort in CCCR. #11 CMDINX Command Index 24 6 read-write CMDRSP0 Command Response 0 0x10 32 read-only 0 0xFFFFFFFF CMDRSP0 Command Response 0 0 32 read-only CMDRSP1 Command Response 1 0x14 32 read-only 0 0xFFFFFFFF CMDRSP1 Command Response 1 0 32 read-only CMDRSP2 Command Response 2 0x18 32 read-only 0 0xFFFFFFFF CMDRSP2 Command Response 2 0 32 read-only CMDRSP3 Command Response 3 0x1C 32 read-only 0 0xFFFFFFFF CMDRSP3 Command Response 3 0 32 read-only DATPORT Buffer Data Port register 0x20 32 read-write 0 0xFFFFFFFF DATCONT Data Content 0 32 read-write PRSSTAT Present State register 0x24 32 read-only 0 0xFFFFFFFF CIHB Command Inhibit (CMD) 0 1 read-only 0 Can issue command using only CMD line. #0 1 Cannot issue command. #1 CDIHB Command Inhibit (DAT) 1 1 read-only 0 Can issue command which uses the DAT line. #0 1 Cannot issue command which uses the DAT line. #1 DLA Data Line Active 2 1 read-only 0 DAT line inactive. #0 1 DAT line active. #1 SDSTB SD Clock Stable 3 1 read-only 0 Clock is changing frequency and not stable. #0 1 Clock is stable. #1 IPGOFF Bus Clock Gated Off Internally 4 1 read-only 0 Bus clock is active. #0 1 Bus clock is gated off. #1 HCKOFF System Clock Gated Off Internally 5 1 read-only 0 System clock is active. #0 1 System clock is gated off. #1 PEROFF SDHC clock Gated Off Internally 6 1 read-only 0 SDHC clock is active. #0 1 SDHC clock is gated off. #1 SDOFF SD Clock Gated Off Internally 7 1 read-only 0 SD clock is active. #0 1 SD clock is gated off. #1 WTA Write Transfer Active 8 1 read-only 0 No valid data. #0 1 Transferring data. #1 RTA Read Transfer Active 9 1 read-only 0 No valid data. #0 1 Transferring data. #1 BWEN Buffer Write Enable 10 1 read-only 0 Write disable, the buffer can hold valid data less than the write watermark level. #0 1 Write enable, the buffer can hold valid data greater than the write watermark level. #1 BREN Buffer Read Enable 11 1 read-only 0 Read disable, valid data less than the watermark level exist in the buffer. #0 1 Read enable, valid data greater than the watermark level exist in the buffer. #1 CINS Card Inserted 16 1 read-only 0 Power on reset or no card. #0 1 Card inserted. #1 CLSL CMD Line Signal Level 23 1 read-only DLSL DAT Line Signal Level 24 8 read-only PROCTL Protocol Control register 0x28 32 read-write 0x20 0xFFFFFFFF LCTL LED Control 0 1 read-write 0 LED off. #0 1 LED on. #1 DTW Data Transfer Width 1 2 read-write 00 1-bit mode #00 01 4-bit mode #01 10 8-bit mode #10 D3CD DAT3 As Card Detection Pin 3 1 read-write 0 DAT3 does not monitor card Insertion. #0 1 DAT3 as card detection pin. #1 EMODE Endian Mode 4 2 read-write 00 Big endian mode #00 01 Half word big endian mode #01 10 Little endian mode #10 CDTL Card Detect Test Level 6 1 read-write 0 Card detect test level is 0, no card inserted. #0 1 Card detect test level is 1, card inserted. #1 CDSS Card Detect Signal Selection 7 1 read-write 0 Card detection level is selected for normal purpose. #0 1 Card detection test level is selected for test purpose. #1 DMAS DMA Select 8 2 read-write 00 No DMA or simple DMA is selected. #00 01 ADMA1 is selected. #01 10 ADMA2 is selected. #10 SABGREQ Stop At Block Gap Request 16 1 read-write 0 Transfer #0 1 Stop #1 CREQ Continue Request 17 1 read-write 0 No effect. #0 1 Restart #1 RWCTL Read Wait Control 18 1 read-write 0 Disable read wait control, and stop SD clock at block gap when SABGREQ is set. #0 1 Enable read wait control, and assert read wait without stopping SD clock at block gap when SABGREQ bit is set. #1 IABG Interrupt At Block Gap 19 1 read-write 0 Disabled #0 1 Enabled #1 WECINT Wakeup Event Enable On Card Interrupt 24 1 read-write 0 Disabled #0 1 Enabled #1 WECINS Wakeup Event Enable On SD Card Insertion 25 1 read-write 0 Disabled #0 1 Enabled #1 WECRM Wakeup Event Enable On SD Card Removal 26 1 read-write 0 Disabled #0 1 Enabled #1 SYSCTL System Control register 0x2C 32 read-write 0x8008 0xFFFFFFFF IPGEN IPG Clock Enable 0 1 read-write 0 Bus clock will be internally gated off. #0 1 Bus clock will not be automatically gated off. #1 HCKEN System Clock Enable 1 1 read-write 0 System clock will be internally gated off. #0 1 System clock will not be automatically gated off. #1 PEREN Peripheral Clock Enable 2 1 read-write 0 SDHC clock will be internally gated off. #0 1 SDHC clock will not be automatically gated off. #1 SDCLKEN SD Clock Enable 3 1 read-write DVS Divisor 4 4 read-write 0 Divisor by 1. #0000 1 Divisor by 2. #0001 1110 Divisor by 15. #1110 1111 Divisor by 16. #1111 SDCLKFS SDCLK Frequency Select 8 8 read-write 1 Base clock divided by 2. #1 10 Base clock divided by 4. #10 100 Base clock divided by 8. #100 1000 Base clock divided by 16. #1000 10000 Base clock divided by 32. #10000 100000 Base clock divided by 64. #100000 1000000 Base clock divided by 128. #1000000 10000000 Base clock divided by 256. #10000000 DTOCV Data Timeout Counter Value 16 4 read-write 0000 SDCLK x 2 13 #0000 0001 SDCLK x 2 14 #0001 1110 SDCLK x 2 27 #1110 RSTA Software Reset For ALL 24 1 write-only 0 No reset. #0 1 Reset. #1 RSTC Software Reset For CMD Line 25 1 write-only 0 No reset. #0 1 Reset. #1 RSTD Software Reset For DAT Line 26 1 write-only 0 No reset. #0 1 Reset. #1 INITA Initialization Active 27 1 read-write IRQSTAT Interrupt Status register 0x30 32 read-write 0 0xFFFFFFFF CC Command Complete 0 1 read-write 0 Command not complete. #0 1 Command complete. #1 TC Transfer Complete 1 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 BGE Block Gap Event 2 1 read-write 0 No block gap event. #0 1 Transaction stopped at block gap. #1 DINT DMA Interrupt 3 1 read-write 0 No DMA Interrupt. #0 1 DMA Interrupt is generated. #1 BWR Buffer Write Ready 4 1 read-write 0 Not ready to write buffer. #0 1 Ready to write buffer. #1 BRR Buffer Read Ready 5 1 read-write 0 Not ready to read buffer. #0 1 Ready to read buffer. #1 CINS Card Insertion 6 1 read-write 0 Card state unstable or removed. #0 1 Card inserted. #1 CRM Card Removal 7 1 read-write 0 Card state unstable or inserted. #0 1 Card removed. #1 CINT Card Interrupt 8 1 read-write 0 No Card Interrupt. #0 1 Generate Card Interrupt. #1 CTOE Command Timeout Error 16 1 read-write 0 No error. #0 1 Time out. #1 CCE Command CRC Error 17 1 read-write 0 No error. #0 1 CRC Error generated. #1 CEBE Command End Bit Error 18 1 read-write 0 No error. #0 1 End Bit Error generated. #1 CIE Command Index Error 19 1 read-write 0 No error. #0 1 Error. #1 DTOE Data Timeout Error 20 1 read-write 0 No error. #0 1 Time out. #1 DCE Data CRC Error 21 1 read-write 0 No error. #0 1 Error. #1 DEBE Data End Bit Error 22 1 read-write 0 No error. #0 1 Error. #1 AC12E Auto CMD12 Error 24 1 read-write 0 No error. #0 1 Error. #1 DMAE DMA Error 28 1 read-write 0 No error. #0 1 Error. #1 IRQSTATEN Interrupt Status Enable register 0x34 32 read-write 0x117F013F 0xFFFFFFFF CCSEN Command Complete Status Enable 0 1 read-write 0 Masked #0 1 Enabled #1 TCSEN Transfer Complete Status Enable 1 1 read-write 0 Masked #0 1 Enabled #1 BGESEN Block Gap Event Status Enable 2 1 read-write 0 Masked #0 1 Enabled #1 DINTSEN DMA Interrupt Status Enable 3 1 read-write 0 Masked #0 1 Enabled #1 BWRSEN Buffer Write Ready Status Enable 4 1 read-write 0 Masked #0 1 Enabled #1 BRRSEN Buffer Read Ready Status Enable 5 1 read-write 0 Masked #0 1 Enabled #1 CINSEN Card Insertion Status Enable 6 1 read-write 0 Masked #0 1 Enabled #1 CRMSEN Card Removal Status Enable 7 1 read-write 0 Masked #0 1 Enabled #1 CINTSEN Card Interrupt Status Enable 8 1 read-write 0 Masked #0 1 Enabled #1 CTOESEN Command Timeout Error Status Enable 16 1 read-write 0 Masked #0 1 Enabled #1 CCESEN Command CRC Error Status Enable 17 1 read-write 0 Masked #0 1 Enabled #1 CEBESEN Command End Bit Error Status Enable 18 1 read-write 0 Masked #0 1 Enabled #1 CIESEN Command Index Error Status Enable 19 1 read-write 0 Masked #0 1 Enabled #1 DTOESEN Data Timeout Error Status Enable 20 1 read-write 0 Masked #0 1 Enabled #1 DCESEN Data CRC Error Status Enable 21 1 read-write 0 Masked #0 1 Enabled #1 DEBESEN Data End Bit Error Status Enable 22 1 read-write 0 Masked #0 1 Enabled #1 AC12ESEN Auto CMD12 Error Status Enable 24 1 read-write 0 Masked #0 1 Enabled #1 DMAESEN DMA Error Status Enable 28 1 read-write 0 Masked #0 1 Enabled #1 IRQSIGEN Interrupt Signal Enable register 0x38 32 read-write 0 0xFFFFFFFF CCIEN Command Complete Interrupt Enable 0 1 read-write 0 Masked #0 1 Enabled #1 TCIEN Transfer Complete Interrupt Enable 1 1 read-write 0 Masked #0 1 Enabled #1 BGEIEN Block Gap Event Interrupt Enable 2 1 read-write 0 Masked #0 1 Enabled #1 DINTIEN DMA Interrupt Enable 3 1 read-write 0 Masked #0 1 Enabled #1 BWRIEN Buffer Write Ready Interrupt Enable 4 1 read-write 0 Masked #0 1 Enabled #1 BRRIEN Buffer Read Ready Interrupt Enable 5 1 read-write 0 Masked #0 1 Enabled #1 CINSIEN Card Insertion Interrupt Enable 6 1 read-write 0 Masked #0 1 Enabled #1 CRMIEN Card Removal Interrupt Enable 7 1 read-write 0 Masked #0 1 Enabled #1 CINTIEN Card Interrupt Enable 8 1 read-write 0 Masked #0 1 Enabled #1 CTOEIEN Command Timeout Error Interrupt Enable 16 1 read-write 0 Masked #0 1 Enabled #1 CCEIEN Command CRC Error Interrupt Enable 17 1 read-write 0 Masked #0 1 Enabled #1 CEBEIEN Command End Bit Error Interrupt Enable 18 1 read-write 0 Masked #0 1 Enabled #1 CIEIEN Command Index Error Interrupt Enable 19 1 read-write 0 Masked #0 1 Enabled #1 DTOEIEN Data Timeout Error Interrupt Enable 20 1 read-write 0 Masked #0 1 Enabled #1 DCEIEN Data CRC Error Interrupt Enable 21 1 read-write 0 Masked #0 1 Enabled #1 DEBEIEN Data End Bit Error Interrupt Enable 22 1 read-write 0 Masked #0 1 Enabled #1 AC12EIEN Auto CMD12 Error Interrupt Enable 24 1 read-write 0 Masked #0 1 Enabled #1 DMAEIEN DMA Error Interrupt Enable 28 1 read-write 0 Masked #0 1 Enabled #1 AC12ERR Auto CMD12 Error Status Register 0x3C 32 read-only 0 0xFFFFFFFF AC12NE Auto CMD12 Not Executed 0 1 read-only 0 Executed. #0 1 Not executed. #1 AC12TOE Auto CMD12 Timeout Error 1 1 read-only 0 No error. #0 1 Time out. #1 AC12EBE Auto CMD12 End Bit Error 2 1 read-only 0 No error. #0 1 End bit error generated. #1 AC12CE Auto CMD12 CRC Error 3 1 read-only 0 No CRC error. #0 1 CRC error met in Auto CMD12 response. #1 AC12IE Auto CMD12 Index Error 4 1 read-only 0 No error. #0 1 Error, the CMD index in response is not CMD12. #1 CNIBAC12E Command Not Issued By Auto CMD12 Error 7 1 read-only 0 No error. #0 1 Not issued. #1 HTCAPBLT Host Controller Capabilities 0x40 32 read-only 0x7F30000 0xFFFFFFFF MBL Max Block Length 16 3 read-only 000 512 bytes #000 001 1024 bytes #001 010 2048 bytes #010 011 4096 bytes #011 ADMAS ADMA Support 20 1 read-only 0 Advanced DMA not supported. #0 1 Advanced DMA supported. #1 HSS High Speed Support 21 1 read-only 0 High speed not supported. #0 1 High speed supported. #1 DMAS DMA Support 22 1 read-only 0 DMA not supported. #0 1 DMA supported. #1 SRS Suspend/Resume Support 23 1 read-only 0 Not supported. #0 1 Supported. #1 VS33 Voltage Support 3.3 V 24 1 read-only 0 3.3 V not supported. #0 1 3.3 V supported. #1 WML Watermark Level Register 0x44 32 read-write 0x100010 0xFFFFFFFF RDWML Read Watermark Level 0 8 read-write WRWML Write Watermark Level 16 8 read-write FEVT Force Event register 0x50 32 write-only 0 0xFFFFFFFF AC12NE Force Event Auto Command 12 Not Executed 0 1 write-only AC12TOE Force Event Auto Command 12 Time Out Error 1 1 write-only AC12CE Force Event Auto Command 12 CRC Error 2 1 write-only AC12EBE Force Event Auto Command 12 End Bit Error 3 1 write-only AC12IE Force Event Auto Command 12 Index Error 4 1 write-only CNIBAC12E Force Event Command Not Executed By Auto Command 12 Error 7 1 write-only CTOE Force Event Command Time Out Error 16 1 write-only CCE Force Event Command CRC Error 17 1 write-only CEBE Force Event Command End Bit Error 18 1 write-only CIE Force Event Command Index Error 19 1 write-only DTOE Force Event Data Time Out Error 20 1 write-only DCE Force Event Data CRC Error 21 1 write-only DEBE Force Event Data End Bit Error 22 1 write-only AC12E Force Event Auto Command 12 Error 24 1 write-only DMAE Force Event DMA Error 28 1 write-only CINT Force Event Card Interrupt 31 1 write-only ADMAES ADMA Error Status register 0x54 32 read-only 0 0xFFFFFFFF ADMAES ADMA Error State (When ADMA Error Is Occurred.) 0 2 read-only ADMALME ADMA Length Mismatch Error 2 1 read-only 0 No error. #0 1 Error. #1 ADMADCE ADMA Descriptor Error 3 1 read-only 0 No error. #0 1 Error. #1 ADSADDR ADMA System Addressregister 0x58 32 read-write 0 0xFFFFFFFF ADSADDR ADMA System Address 2 30 read-write VENDOR Vendor Specific register 0xC0 32 read-write 0x1 0xFFFFFFFF EXBLKNU Exact Block Number Block Read Enable For SDIO CMD53 1 1 read-write 0 None exact block read. #0 1 Exact block read for SDIO CMD53. #1 INTSTVAL Internal State Value 16 8 read-only MMCBOOT MMC Boot register 0xC4 32 read-write 0 0xFFFFFFFF DTOCVACK Boot ACK Time Out Counter Value 0 4 read-write 0000 SDCLK x 2^8 #0000 0001 SDCLK x 2^9 #0001 0010 SDCLK x 2^10 #0010 0011 SDCLK x 2^11 #0011 0100 SDCLK x 2^12 #0100 0101 SDCLK x 2^13 #0101 0110 SDCLK x 2^14 #0110 0111 SDCLK x 2^15 #0111 1110 SDCLK x 2^22 #1110 BOOTACK Boot Ack Mode Select 4 1 read-write 0 No ack. #0 1 Ack. #1 BOOTMODE Boot Mode Select 5 1 read-write 0 Normal boot. #0 1 Alternative boot. #1 BOOTEN Boot Mode Enable 6 1 read-write 0 Fast boot disable. #0 1 Fast boot enable. #1 AUTOSABGEN When boot, enable auto stop at block gap function 7 1 read-write BOOTBLKCNT Defines the stop at block gap value of automatic mode 16 16 read-write HOSTVER Host Controller Version 0xFC 32 read-only 0x1201 0xFFFFFFFF SVN Specification Version Number 0 8 read-only 1 SD host specification version 2.0, supports test event register and ADMA. #1 VVN Vendor Version Number 8 8 read-only 0 Freescale SDHC version 1.0 #0 10000 Freescale SDHC version 2.0 #10000 10001 Freescale SDHC version 2.1 #10001 10010 Freescale SDHC version 2.2 #10010 LPUART0 Universal Asynchronous Receiver/Transmitter LPUART LPUART0_ 0x400C4000 0 0x20 registers LPUART0 30 BAUD LPUART Baud Rate Register 0 32 read-write 0xF000004 0xFFFFFFFF SBR Baud Rate Modulo Divisor. 0 13 read-write SBNS Stop Bit Number Select 13 1 read-write 0 One stop bit. #0 1 Two stop bits. #1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write 0 Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. #1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write 0 Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. #1 RESYNCDIS Resynchronization Disable 16 1 read-write 0 Resynchronization during received data word is supported #0 1 Resynchronization during received data word is disabled #1 BOTHEDGE Both Edge Sampling 17 1 read-write 0 Receiver samples input data using the rising edge of the baud rate clock. #0 1 Receiver samples input data using the rising and falling edge of the baud rate clock. #1 MATCFG Match Configuration 18 2 read-write 00 Address Match Wakeup #00 01 Idle Match Wakeup #01 10 Match On and Match Off #10 11 Enables RWU on Data Match and Match On/Off for transmitter CTS input #11 RDMAE Receiver Full DMA Enable 21 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 TDMAE Transmitter DMA Enable 23 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 OSR Over Sampling Ratio 24 5 read-write M10 10-bit Mode select 29 1 read-write 0 Receiver and transmitter use 8-bit or 9-bit data characters. #0 1 Receiver and transmitter use 10-bit data characters. #1 MAEN2 Match Address Mode Enable 2 30 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA2]. #1 MAEN1 Match Address Mode Enable 1 31 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA1]. #1 STAT LPUART Status Register 0x4 32 read-write 0xC00000 0xFFFFFFFF MA2F Match 2 Flag 14 1 read-write 0 Received data is not equal to MA2 #0 1 Received data is equal to MA2 #1 MA1F Match 1 Flag 15 1 read-write 0 Received data is not equal to MA1 #0 1 Received data is equal to MA1 #1 PF Parity Error Flag 16 1 read-write 0 No parity error. #0 1 Parity error. #1 FE Framing Error Flag 17 1 read-write 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 NF Noise Flag 18 1 read-write 0 No noise detected. #0 1 Noise detected in the received character in LPUART_DATA. #1 OR Receiver Overrun Flag 19 1 read-write 0 No overrun. #0 1 Receive overrun (new LPUART data lost). #1 IDLE Idle Line Flag 20 1 read-write 0 No idle line detected. #0 1 Idle line was detected. #1 RDRF Receive Data Register Full Flag 21 1 read-only 0 Receive data buffer empty. #0 1 Receive data buffer full. #1 TC Transmission Complete Flag 22 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 23 1 read-only 0 Transmit data buffer full. #0 1 Transmit data buffer empty. #1 RAF Receiver Active Flag 24 1 read-only 0 LPUART receiver idle waiting for a start bit. #0 1 LPUART receiver active (LPUART_RX input not idle). #1 LBKDE LIN Break Detection Enable 25 1 read-write 0 Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1). #1 BRK13 Break Character Generation Length 26 1 read-write 0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1). #1 RWUID Receive Wake Up Idle Detect 27 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match. #1 RXINV Receive Data Inversion 28 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 MSBF MSB First 29 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. #1 RXEDGIF LPUART_RX Pin Active Edge Interrupt Flag 30 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 CTRL LPUART Control Register 0x8 32 read-write 0 0xFFFFFFFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Configures RWU for idle-line wakeup. #0 1 Configures RWU with address-mark wakeup. #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Receiver and transmitter use 8-bit data characters. #0 1 Receiver and transmitter use 9-bit data characters. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin. #0 1 Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input. #1 DOZEEN Doze Enable 6 1 read-write 0 LPUART is enabled in Doze mode. #0 1 LPUART is disabled in Doze mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - LPUART_RX and LPUART_TX use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). #1 IDLECFG Idle Configuration 8 3 read-write 000 1 idle character #000 001 2 idle characters #001 010 4 idle characters #010 011 8 idle characters #011 100 16 idle characters #100 101 32 idle characters #101 110 64 idle characters #110 111 128 idle characters #111 MA2IE Match 2 Interrupt Enable 14 1 read-write 0 MA2F interrupt disabled #0 1 MA2F interrupt enabled #1 MA1IE Match 1 Interrupt Enable 15 1 read-write 0 MA1F interrupt disabled #0 1 MA1F interrupt enabled #1 SBK Send Break 16 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 RWU Receiver Wakeup Control 17 1 read-write 0 Normal receiver operation. #0 1 LPUART receiver in standby waiting for wakeup condition. #1 RE Receiver Enable 18 1 read-write 0 Receiver disabled. #0 1 Receiver enabled. #1 TE Transmitter Enable 19 1 read-write 0 Transmitter disabled. #0 1 Transmitter enabled. #1 ILIE Idle Line Interrupt Enable 20 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 RIE Receiver Interrupt Enable 21 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TIE Transmit Interrupt Enable 23 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 PEIE Parity Error Interrupt Enable 24 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 FEIE Framing Error Interrupt Enable 25 1 read-write 0 FE interrupts disabled; use polling. #0 1 Hardware interrupt requested when FE is set. #1 NEIE Noise Error Interrupt Enable 26 1 read-write 0 NF interrupts disabled; use polling. #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 27 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 TXINV Transmit Data Inversion 28 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 TXDIR LPUART_TX Pin Direction in Single-Wire Mode 29 1 read-write 0 LPUART_TX pin is an input in single-wire mode. #0 1 LPUART_TX pin is an output in single-wire mode. #1 R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write DATA LPUART Data Register 0xC 32 read-write 0x1000 0xFFFFFFFF R0T0 Read receive data buffer 0 or write transmit data buffer 0. 0 1 read-write R1T1 Read receive data buffer 1 or write transmit data buffer 1. 1 1 read-write R2T2 Read receive data buffer 2 or write transmit data buffer 2. 2 1 read-write R3T3 Read receive data buffer 3 or write transmit data buffer 3. 3 1 read-write R4T4 Read receive data buffer 4 or write transmit data buffer 4. 4 1 read-write R5T5 Read receive data buffer 5 or write transmit data buffer 5. 5 1 read-write R6T6 Read receive data buffer 6 or write transmit data buffer 6. 6 1 read-write R7T7 Read receive data buffer 7 or write transmit data buffer 7. 7 1 read-write R8T8 Read receive data buffer 8 or write transmit data buffer 8. 8 1 read-write R9T9 Read receive data buffer 9 or write transmit data buffer 9. 9 1 read-write IDLINE Idle Line 11 1 read-only 0 Receiver was not idle before receiving this character. #0 1 Receiver was idle before receiving this character. #1 RXEMPT Receive Buffer Empty 12 1 read-only 0 Receive buffer contains valid data. #0 1 Receive buffer is empty, data returned on read is not valid. #1 FRETSC Frame Error / Transmit Special Character 13 1 read-write 0 The dataword was received without a frame error on read, transmit a normal character on write. #0 1 The dataword was received with a frame error, transmit an idle or break character on transmit. #1 PARITYE The current received dataword contained in DATA[R9:R0] was received with a parity error. 14 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 NOISY The current received dataword contained in DATA[R9:R0] was received with noise. 15 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 MATCH LPUART Match Address Register 0x10 32 read-write 0 0xFFFFFFFF MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x14 32 read-write 0 0xFFFFFFFF TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full. #1 TXCTSC Transmit CTS Configuration 4 1 read-write 0 CTS input is sampled at the start of each character. #0 1 CTS input is sampled when the transmitter is idle. #1 TXCTSSRC Transmit CTS Source 5 1 read-write 0 CTS input is the LPUART_CTS pin. #0 1 CTS input is the inverted Receiver Match result. #1 RTSWATER Receive RTS Configuration 8 8 read-write 0 RTS asserts when the receiver FIFO is full or receiving a character that causes the FIFO to become full. #0 1 RTS asserts when the receive FIFO is less than or equal to the RXWATER configuration and negates when the receive FIFO is greater than the RXWATER configuration. #1 TNP Transmitter narrow pulse 16 2 read-write 00 1/OSR. #00 01 2/OSR. #01 10 3/OSR. #10 11 4/OSR. #11 IREN Infrared enable 18 1 read-write 0 IR disabled. #0 1 IR enabled. #1 FIFO LPUART FIFO Register 0x18 32 read-write 0x22 0xFFFFFFFF RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 111 Receive FIFO/Buffer depth = 256 datawords. #111 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 111 Transmit FIFO/Buffer depth = 256 datawords #111 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 RXUFE Receive FIFO Underflow Interrupt Enable 8 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 9 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 RXIDEN Receiver Idle Empty Enable 10 3 read-write 000 Disable RDRF assertion due to partially filled FIFO when receiver is idle. #000 001 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. #001 010 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. #010 011 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. #011 100 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. #100 101 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. #101 110 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. #110 111 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. #111 RXFLUSH Receive FIFO/Buffer Flush 14 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 TXFLUSH Transmit FIFO/Buffer Flush 15 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 RXUF Receiver Buffer Underflow Flag 16 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXOF Transmitter Buffer Overflow Flag 17 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 RXEMPT Receive Buffer/FIFO Empty 22 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 TXEMPT Transmit Buffer/FIFO Empty 23 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 WATER LPUART Watermark Register 0x1C 32 read-write 0 0xFFFFFFFF TXWATER Transmit Watermark 0 8 read-write TXCOUNT Transmit Counter 8 8 read-only RXWATER Receive Watermark 16 8 read-write RXCOUNT Receive Counter 24 8 read-only LPUART1 Universal Asynchronous Receiver/Transmitter LPUART LPUART1_ 0x400C5000 0 0x20 registers LPUART1 31 BAUD LPUART Baud Rate Register 0 32 read-write 0xF000004 0xFFFFFFFF SBR Baud Rate Modulo Divisor. 0 13 read-write SBNS Stop Bit Number Select 13 1 read-write 0 One stop bit. #0 1 Two stop bits. #1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write 0 Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. #1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write 0 Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. #1 RESYNCDIS Resynchronization Disable 16 1 read-write 0 Resynchronization during received data word is supported #0 1 Resynchronization during received data word is disabled #1 BOTHEDGE Both Edge Sampling 17 1 read-write 0 Receiver samples input data using the rising edge of the baud rate clock. #0 1 Receiver samples input data using the rising and falling edge of the baud rate clock. #1 MATCFG Match Configuration 18 2 read-write 00 Address Match Wakeup #00 01 Idle Match Wakeup #01 10 Match On and Match Off #10 11 Enables RWU on Data Match and Match On/Off for transmitter CTS input #11 RDMAE Receiver Full DMA Enable 21 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 TDMAE Transmitter DMA Enable 23 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 OSR Over Sampling Ratio 24 5 read-write M10 10-bit Mode select 29 1 read-write 0 Receiver and transmitter use 8-bit or 9-bit data characters. #0 1 Receiver and transmitter use 10-bit data characters. #1 MAEN2 Match Address Mode Enable 2 30 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA2]. #1 MAEN1 Match Address Mode Enable 1 31 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA1]. #1 STAT LPUART Status Register 0x4 32 read-write 0xC00000 0xFFFFFFFF MA2F Match 2 Flag 14 1 read-write 0 Received data is not equal to MA2 #0 1 Received data is equal to MA2 #1 MA1F Match 1 Flag 15 1 read-write 0 Received data is not equal to MA1 #0 1 Received data is equal to MA1 #1 PF Parity Error Flag 16 1 read-write 0 No parity error. #0 1 Parity error. #1 FE Framing Error Flag 17 1 read-write 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 NF Noise Flag 18 1 read-write 0 No noise detected. #0 1 Noise detected in the received character in LPUART_DATA. #1 OR Receiver Overrun Flag 19 1 read-write 0 No overrun. #0 1 Receive overrun (new LPUART data lost). #1 IDLE Idle Line Flag 20 1 read-write 0 No idle line detected. #0 1 Idle line was detected. #1 RDRF Receive Data Register Full Flag 21 1 read-only 0 Receive data buffer empty. #0 1 Receive data buffer full. #1 TC Transmission Complete Flag 22 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 23 1 read-only 0 Transmit data buffer full. #0 1 Transmit data buffer empty. #1 RAF Receiver Active Flag 24 1 read-only 0 LPUART receiver idle waiting for a start bit. #0 1 LPUART receiver active (LPUART_RX input not idle). #1 LBKDE LIN Break Detection Enable 25 1 read-write 0 Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1). #1 BRK13 Break Character Generation Length 26 1 read-write 0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1). #1 RWUID Receive Wake Up Idle Detect 27 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match. #1 RXINV Receive Data Inversion 28 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 MSBF MSB First 29 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. #1 RXEDGIF LPUART_RX Pin Active Edge Interrupt Flag 30 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 CTRL LPUART Control Register 0x8 32 read-write 0 0xFFFFFFFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Configures RWU for idle-line wakeup. #0 1 Configures RWU with address-mark wakeup. #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Receiver and transmitter use 8-bit data characters. #0 1 Receiver and transmitter use 9-bit data characters. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin. #0 1 Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input. #1 DOZEEN Doze Enable 6 1 read-write 0 LPUART is enabled in Doze mode. #0 1 LPUART is disabled in Doze mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - LPUART_RX and LPUART_TX use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). #1 IDLECFG Idle Configuration 8 3 read-write 000 1 idle character #000 001 2 idle characters #001 010 4 idle characters #010 011 8 idle characters #011 100 16 idle characters #100 101 32 idle characters #101 110 64 idle characters #110 111 128 idle characters #111 MA2IE Match 2 Interrupt Enable 14 1 read-write 0 MA2F interrupt disabled #0 1 MA2F interrupt enabled #1 MA1IE Match 1 Interrupt Enable 15 1 read-write 0 MA1F interrupt disabled #0 1 MA1F interrupt enabled #1 SBK Send Break 16 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 RWU Receiver Wakeup Control 17 1 read-write 0 Normal receiver operation. #0 1 LPUART receiver in standby waiting for wakeup condition. #1 RE Receiver Enable 18 1 read-write 0 Receiver disabled. #0 1 Receiver enabled. #1 TE Transmitter Enable 19 1 read-write 0 Transmitter disabled. #0 1 Transmitter enabled. #1 ILIE Idle Line Interrupt Enable 20 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 RIE Receiver Interrupt Enable 21 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TIE Transmit Interrupt Enable 23 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 PEIE Parity Error Interrupt Enable 24 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 FEIE Framing Error Interrupt Enable 25 1 read-write 0 FE interrupts disabled; use polling. #0 1 Hardware interrupt requested when FE is set. #1 NEIE Noise Error Interrupt Enable 26 1 read-write 0 NF interrupts disabled; use polling. #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 27 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 TXINV Transmit Data Inversion 28 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 TXDIR LPUART_TX Pin Direction in Single-Wire Mode 29 1 read-write 0 LPUART_TX pin is an input in single-wire mode. #0 1 LPUART_TX pin is an output in single-wire mode. #1 R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write DATA LPUART Data Register 0xC 32 read-write 0x1000 0xFFFFFFFF R0T0 Read receive data buffer 0 or write transmit data buffer 0. 0 1 read-write R1T1 Read receive data buffer 1 or write transmit data buffer 1. 1 1 read-write R2T2 Read receive data buffer 2 or write transmit data buffer 2. 2 1 read-write R3T3 Read receive data buffer 3 or write transmit data buffer 3. 3 1 read-write R4T4 Read receive data buffer 4 or write transmit data buffer 4. 4 1 read-write R5T5 Read receive data buffer 5 or write transmit data buffer 5. 5 1 read-write R6T6 Read receive data buffer 6 or write transmit data buffer 6. 6 1 read-write R7T7 Read receive data buffer 7 or write transmit data buffer 7. 7 1 read-write R8T8 Read receive data buffer 8 or write transmit data buffer 8. 8 1 read-write R9T9 Read receive data buffer 9 or write transmit data buffer 9. 9 1 read-write IDLINE Idle Line 11 1 read-only 0 Receiver was not idle before receiving this character. #0 1 Receiver was idle before receiving this character. #1 RXEMPT Receive Buffer Empty 12 1 read-only 0 Receive buffer contains valid data. #0 1 Receive buffer is empty, data returned on read is not valid. #1 FRETSC Frame Error / Transmit Special Character 13 1 read-write 0 The dataword was received without a frame error on read, transmit a normal character on write. #0 1 The dataword was received with a frame error, transmit an idle or break character on transmit. #1 PARITYE The current received dataword contained in DATA[R9:R0] was received with a parity error. 14 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 NOISY The current received dataword contained in DATA[R9:R0] was received with noise. 15 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 MATCH LPUART Match Address Register 0x10 32 read-write 0 0xFFFFFFFF MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x14 32 read-write 0 0xFFFFFFFF TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full. #1 TXCTSC Transmit CTS Configuration 4 1 read-write 0 CTS input is sampled at the start of each character. #0 1 CTS input is sampled when the transmitter is idle. #1 TXCTSSRC Transmit CTS Source 5 1 read-write 0 CTS input is the LPUART_CTS pin. #0 1 CTS input is the inverted Receiver Match result. #1 RTSWATER Receive RTS Configuration 8 8 read-write 0 RTS asserts when the receiver FIFO is full or receiving a character that causes the FIFO to become full. #0 1 RTS asserts when the receive FIFO is less than or equal to the RXWATER configuration and negates when the receive FIFO is greater than the RXWATER configuration. #1 TNP Transmitter narrow pulse 16 2 read-write 00 1/OSR. #00 01 2/OSR. #01 10 3/OSR. #10 11 4/OSR. #11 IREN Infrared enable 18 1 read-write 0 IR disabled. #0 1 IR enabled. #1 FIFO LPUART FIFO Register 0x18 32 read-write 0x22 0xFFFFFFFF RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 111 Receive FIFO/Buffer depth = 256 datawords. #111 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 111 Transmit FIFO/Buffer depth = 256 datawords #111 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 RXUFE Receive FIFO Underflow Interrupt Enable 8 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 9 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 RXIDEN Receiver Idle Empty Enable 10 3 read-write 000 Disable RDRF assertion due to partially filled FIFO when receiver is idle. #000 001 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. #001 010 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. #010 011 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. #011 100 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. #100 101 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. #101 110 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. #110 111 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. #111 RXFLUSH Receive FIFO/Buffer Flush 14 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 TXFLUSH Transmit FIFO/Buffer Flush 15 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 RXUF Receiver Buffer Underflow Flag 16 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXOF Transmitter Buffer Overflow Flag 17 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 RXEMPT Receive Buffer/FIFO Empty 22 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 TXEMPT Transmit Buffer/FIFO Empty 23 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 WATER LPUART Watermark Register 0x1C 32 read-write 0 0xFFFFFFFF TXWATER Transmit Watermark 0 8 read-write TXCOUNT Transmit Counter 8 8 read-only RXWATER Receive Watermark 16 8 read-write RXCOUNT Receive Counter 24 8 read-only LPUART2 Universal Asynchronous Receiver/Transmitter LPUART LPUART2_ 0x400C6000 0 0x20 registers LPUART2 32 BAUD LPUART Baud Rate Register 0 32 read-write 0xF000004 0xFFFFFFFF SBR Baud Rate Modulo Divisor. 0 13 read-write SBNS Stop Bit Number Select 13 1 read-write 0 One stop bit. #0 1 Two stop bits. #1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write 0 Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. #1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write 0 Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. #1 RESYNCDIS Resynchronization Disable 16 1 read-write 0 Resynchronization during received data word is supported #0 1 Resynchronization during received data word is disabled #1 BOTHEDGE Both Edge Sampling 17 1 read-write 0 Receiver samples input data using the rising edge of the baud rate clock. #0 1 Receiver samples input data using the rising and falling edge of the baud rate clock. #1 MATCFG Match Configuration 18 2 read-write 00 Address Match Wakeup #00 01 Idle Match Wakeup #01 10 Match On and Match Off #10 11 Enables RWU on Data Match and Match On/Off for transmitter CTS input #11 RDMAE Receiver Full DMA Enable 21 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 TDMAE Transmitter DMA Enable 23 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 OSR Over Sampling Ratio 24 5 read-write M10 10-bit Mode select 29 1 read-write 0 Receiver and transmitter use 8-bit or 9-bit data characters. #0 1 Receiver and transmitter use 10-bit data characters. #1 MAEN2 Match Address Mode Enable 2 30 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA2]. #1 MAEN1 Match Address Mode Enable 1 31 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA1]. #1 STAT LPUART Status Register 0x4 32 read-write 0xC00000 0xFFFFFFFF MA2F Match 2 Flag 14 1 read-write 0 Received data is not equal to MA2 #0 1 Received data is equal to MA2 #1 MA1F Match 1 Flag 15 1 read-write 0 Received data is not equal to MA1 #0 1 Received data is equal to MA1 #1 PF Parity Error Flag 16 1 read-write 0 No parity error. #0 1 Parity error. #1 FE Framing Error Flag 17 1 read-write 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 NF Noise Flag 18 1 read-write 0 No noise detected. #0 1 Noise detected in the received character in LPUART_DATA. #1 OR Receiver Overrun Flag 19 1 read-write 0 No overrun. #0 1 Receive overrun (new LPUART data lost). #1 IDLE Idle Line Flag 20 1 read-write 0 No idle line detected. #0 1 Idle line was detected. #1 RDRF Receive Data Register Full Flag 21 1 read-only 0 Receive data buffer empty. #0 1 Receive data buffer full. #1 TC Transmission Complete Flag 22 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 23 1 read-only 0 Transmit data buffer full. #0 1 Transmit data buffer empty. #1 RAF Receiver Active Flag 24 1 read-only 0 LPUART receiver idle waiting for a start bit. #0 1 LPUART receiver active (LPUART_RX input not idle). #1 LBKDE LIN Break Detection Enable 25 1 read-write 0 Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1). #1 BRK13 Break Character Generation Length 26 1 read-write 0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1). #1 RWUID Receive Wake Up Idle Detect 27 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match. #1 RXINV Receive Data Inversion 28 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 MSBF MSB First 29 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. #1 RXEDGIF LPUART_RX Pin Active Edge Interrupt Flag 30 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 CTRL LPUART Control Register 0x8 32 read-write 0 0xFFFFFFFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Configures RWU for idle-line wakeup. #0 1 Configures RWU with address-mark wakeup. #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Receiver and transmitter use 8-bit data characters. #0 1 Receiver and transmitter use 9-bit data characters. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin. #0 1 Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input. #1 DOZEEN Doze Enable 6 1 read-write 0 LPUART is enabled in Doze mode. #0 1 LPUART is disabled in Doze mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - LPUART_RX and LPUART_TX use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). #1 IDLECFG Idle Configuration 8 3 read-write 000 1 idle character #000 001 2 idle characters #001 010 4 idle characters #010 011 8 idle characters #011 100 16 idle characters #100 101 32 idle characters #101 110 64 idle characters #110 111 128 idle characters #111 MA2IE Match 2 Interrupt Enable 14 1 read-write 0 MA2F interrupt disabled #0 1 MA2F interrupt enabled #1 MA1IE Match 1 Interrupt Enable 15 1 read-write 0 MA1F interrupt disabled #0 1 MA1F interrupt enabled #1 SBK Send Break 16 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 RWU Receiver Wakeup Control 17 1 read-write 0 Normal receiver operation. #0 1 LPUART receiver in standby waiting for wakeup condition. #1 RE Receiver Enable 18 1 read-write 0 Receiver disabled. #0 1 Receiver enabled. #1 TE Transmitter Enable 19 1 read-write 0 Transmitter disabled. #0 1 Transmitter enabled. #1 ILIE Idle Line Interrupt Enable 20 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 RIE Receiver Interrupt Enable 21 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TIE Transmit Interrupt Enable 23 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 PEIE Parity Error Interrupt Enable 24 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 FEIE Framing Error Interrupt Enable 25 1 read-write 0 FE interrupts disabled; use polling. #0 1 Hardware interrupt requested when FE is set. #1 NEIE Noise Error Interrupt Enable 26 1 read-write 0 NF interrupts disabled; use polling. #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 27 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 TXINV Transmit Data Inversion 28 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 TXDIR LPUART_TX Pin Direction in Single-Wire Mode 29 1 read-write 0 LPUART_TX pin is an input in single-wire mode. #0 1 LPUART_TX pin is an output in single-wire mode. #1 R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write DATA LPUART Data Register 0xC 32 read-write 0x1000 0xFFFFFFFF R0T0 Read receive data buffer 0 or write transmit data buffer 0. 0 1 read-write R1T1 Read receive data buffer 1 or write transmit data buffer 1. 1 1 read-write R2T2 Read receive data buffer 2 or write transmit data buffer 2. 2 1 read-write R3T3 Read receive data buffer 3 or write transmit data buffer 3. 3 1 read-write R4T4 Read receive data buffer 4 or write transmit data buffer 4. 4 1 read-write R5T5 Read receive data buffer 5 or write transmit data buffer 5. 5 1 read-write R6T6 Read receive data buffer 6 or write transmit data buffer 6. 6 1 read-write R7T7 Read receive data buffer 7 or write transmit data buffer 7. 7 1 read-write R8T8 Read receive data buffer 8 or write transmit data buffer 8. 8 1 read-write R9T9 Read receive data buffer 9 or write transmit data buffer 9. 9 1 read-write IDLINE Idle Line 11 1 read-only 0 Receiver was not idle before receiving this character. #0 1 Receiver was idle before receiving this character. #1 RXEMPT Receive Buffer Empty 12 1 read-only 0 Receive buffer contains valid data. #0 1 Receive buffer is empty, data returned on read is not valid. #1 FRETSC Frame Error / Transmit Special Character 13 1 read-write 0 The dataword was received without a frame error on read, transmit a normal character on write. #0 1 The dataword was received with a frame error, transmit an idle or break character on transmit. #1 PARITYE The current received dataword contained in DATA[R9:R0] was received with a parity error. 14 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 NOISY The current received dataword contained in DATA[R9:R0] was received with noise. 15 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 MATCH LPUART Match Address Register 0x10 32 read-write 0 0xFFFFFFFF MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x14 32 read-write 0 0xFFFFFFFF TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full. #1 TXCTSC Transmit CTS Configuration 4 1 read-write 0 CTS input is sampled at the start of each character. #0 1 CTS input is sampled when the transmitter is idle. #1 TXCTSSRC Transmit CTS Source 5 1 read-write 0 CTS input is the LPUART_CTS pin. #0 1 CTS input is the inverted Receiver Match result. #1 RTSWATER Receive RTS Configuration 8 8 read-write 0 RTS asserts when the receiver FIFO is full or receiving a character that causes the FIFO to become full. #0 1 RTS asserts when the receive FIFO is less than or equal to the RXWATER configuration and negates when the receive FIFO is greater than the RXWATER configuration. #1 TNP Transmitter narrow pulse 16 2 read-write 00 1/OSR. #00 01 2/OSR. #01 10 3/OSR. #10 11 4/OSR. #11 IREN Infrared enable 18 1 read-write 0 IR disabled. #0 1 IR enabled. #1 FIFO LPUART FIFO Register 0x18 32 read-write 0x22 0xFFFFFFFF RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 111 Receive FIFO/Buffer depth = 256 datawords. #111 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 111 Transmit FIFO/Buffer depth = 256 datawords #111 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 RXUFE Receive FIFO Underflow Interrupt Enable 8 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 9 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 RXIDEN Receiver Idle Empty Enable 10 3 read-write 000 Disable RDRF assertion due to partially filled FIFO when receiver is idle. #000 001 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. #001 010 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. #010 011 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. #011 100 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. #100 101 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. #101 110 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. #110 111 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. #111 RXFLUSH Receive FIFO/Buffer Flush 14 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 TXFLUSH Transmit FIFO/Buffer Flush 15 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 RXUF Receiver Buffer Underflow Flag 16 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXOF Transmitter Buffer Overflow Flag 17 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 RXEMPT Receive Buffer/FIFO Empty 22 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 TXEMPT Transmit Buffer/FIFO Empty 23 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 WATER LPUART Watermark Register 0x1C 32 read-write 0 0xFFFFFFFF TXWATER Transmit Watermark 0 8 read-write TXCOUNT Transmit Counter 8 8 read-only RXWATER Receive Watermark 16 8 read-write RXCOUNT Receive Counter 24 8 read-only LPUART3 Universal Asynchronous Receiver/Transmitter LPUART LPUART3_ 0x400C7000 0 0x20 registers LPUART3 33 BAUD LPUART Baud Rate Register 0 32 read-write 0xF000004 0xFFFFFFFF SBR Baud Rate Modulo Divisor. 0 13 read-write SBNS Stop Bit Number Select 13 1 read-write 0 One stop bit. #0 1 Two stop bits. #1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write 0 Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. #1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write 0 Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. #1 RESYNCDIS Resynchronization Disable 16 1 read-write 0 Resynchronization during received data word is supported #0 1 Resynchronization during received data word is disabled #1 BOTHEDGE Both Edge Sampling 17 1 read-write 0 Receiver samples input data using the rising edge of the baud rate clock. #0 1 Receiver samples input data using the rising and falling edge of the baud rate clock. #1 MATCFG Match Configuration 18 2 read-write 00 Address Match Wakeup #00 01 Idle Match Wakeup #01 10 Match On and Match Off #10 11 Enables RWU on Data Match and Match On/Off for transmitter CTS input #11 RDMAE Receiver Full DMA Enable 21 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 TDMAE Transmitter DMA Enable 23 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 OSR Over Sampling Ratio 24 5 read-write M10 10-bit Mode select 29 1 read-write 0 Receiver and transmitter use 8-bit or 9-bit data characters. #0 1 Receiver and transmitter use 10-bit data characters. #1 MAEN2 Match Address Mode Enable 2 30 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA2]. #1 MAEN1 Match Address Mode Enable 1 31 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA1]. #1 STAT LPUART Status Register 0x4 32 read-write 0xC00000 0xFFFFFFFF MA2F Match 2 Flag 14 1 read-write 0 Received data is not equal to MA2 #0 1 Received data is equal to MA2 #1 MA1F Match 1 Flag 15 1 read-write 0 Received data is not equal to MA1 #0 1 Received data is equal to MA1 #1 PF Parity Error Flag 16 1 read-write 0 No parity error. #0 1 Parity error. #1 FE Framing Error Flag 17 1 read-write 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 NF Noise Flag 18 1 read-write 0 No noise detected. #0 1 Noise detected in the received character in LPUART_DATA. #1 OR Receiver Overrun Flag 19 1 read-write 0 No overrun. #0 1 Receive overrun (new LPUART data lost). #1 IDLE Idle Line Flag 20 1 read-write 0 No idle line detected. #0 1 Idle line was detected. #1 RDRF Receive Data Register Full Flag 21 1 read-only 0 Receive data buffer empty. #0 1 Receive data buffer full. #1 TC Transmission Complete Flag 22 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 23 1 read-only 0 Transmit data buffer full. #0 1 Transmit data buffer empty. #1 RAF Receiver Active Flag 24 1 read-only 0 LPUART receiver idle waiting for a start bit. #0 1 LPUART receiver active (LPUART_RX input not idle). #1 LBKDE LIN Break Detection Enable 25 1 read-write 0 Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1). #1 BRK13 Break Character Generation Length 26 1 read-write 0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1). #1 RWUID Receive Wake Up Idle Detect 27 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match. #1 RXINV Receive Data Inversion 28 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 MSBF MSB First 29 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. #1 RXEDGIF LPUART_RX Pin Active Edge Interrupt Flag 30 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 CTRL LPUART Control Register 0x8 32 read-write 0 0xFFFFFFFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Configures RWU for idle-line wakeup. #0 1 Configures RWU with address-mark wakeup. #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Receiver and transmitter use 8-bit data characters. #0 1 Receiver and transmitter use 9-bit data characters. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin. #0 1 Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input. #1 DOZEEN Doze Enable 6 1 read-write 0 LPUART is enabled in Doze mode. #0 1 LPUART is disabled in Doze mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - LPUART_RX and LPUART_TX use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). #1 IDLECFG Idle Configuration 8 3 read-write 000 1 idle character #000 001 2 idle characters #001 010 4 idle characters #010 011 8 idle characters #011 100 16 idle characters #100 101 32 idle characters #101 110 64 idle characters #110 111 128 idle characters #111 MA2IE Match 2 Interrupt Enable 14 1 read-write 0 MA2F interrupt disabled #0 1 MA2F interrupt enabled #1 MA1IE Match 1 Interrupt Enable 15 1 read-write 0 MA1F interrupt disabled #0 1 MA1F interrupt enabled #1 SBK Send Break 16 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 RWU Receiver Wakeup Control 17 1 read-write 0 Normal receiver operation. #0 1 LPUART receiver in standby waiting for wakeup condition. #1 RE Receiver Enable 18 1 read-write 0 Receiver disabled. #0 1 Receiver enabled. #1 TE Transmitter Enable 19 1 read-write 0 Transmitter disabled. #0 1 Transmitter enabled. #1 ILIE Idle Line Interrupt Enable 20 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 RIE Receiver Interrupt Enable 21 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TIE Transmit Interrupt Enable 23 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 PEIE Parity Error Interrupt Enable 24 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 FEIE Framing Error Interrupt Enable 25 1 read-write 0 FE interrupts disabled; use polling. #0 1 Hardware interrupt requested when FE is set. #1 NEIE Noise Error Interrupt Enable 26 1 read-write 0 NF interrupts disabled; use polling. #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 27 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 TXINV Transmit Data Inversion 28 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 TXDIR LPUART_TX Pin Direction in Single-Wire Mode 29 1 read-write 0 LPUART_TX pin is an input in single-wire mode. #0 1 LPUART_TX pin is an output in single-wire mode. #1 R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write DATA LPUART Data Register 0xC 32 read-write 0x1000 0xFFFFFFFF R0T0 Read receive data buffer 0 or write transmit data buffer 0. 0 1 read-write R1T1 Read receive data buffer 1 or write transmit data buffer 1. 1 1 read-write R2T2 Read receive data buffer 2 or write transmit data buffer 2. 2 1 read-write R3T3 Read receive data buffer 3 or write transmit data buffer 3. 3 1 read-write R4T4 Read receive data buffer 4 or write transmit data buffer 4. 4 1 read-write R5T5 Read receive data buffer 5 or write transmit data buffer 5. 5 1 read-write R6T6 Read receive data buffer 6 or write transmit data buffer 6. 6 1 read-write R7T7 Read receive data buffer 7 or write transmit data buffer 7. 7 1 read-write R8T8 Read receive data buffer 8 or write transmit data buffer 8. 8 1 read-write R9T9 Read receive data buffer 9 or write transmit data buffer 9. 9 1 read-write IDLINE Idle Line 11 1 read-only 0 Receiver was not idle before receiving this character. #0 1 Receiver was idle before receiving this character. #1 RXEMPT Receive Buffer Empty 12 1 read-only 0 Receive buffer contains valid data. #0 1 Receive buffer is empty, data returned on read is not valid. #1 FRETSC Frame Error / Transmit Special Character 13 1 read-write 0 The dataword was received without a frame error on read, transmit a normal character on write. #0 1 The dataword was received with a frame error, transmit an idle or break character on transmit. #1 PARITYE The current received dataword contained in DATA[R9:R0] was received with a parity error. 14 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 NOISY The current received dataword contained in DATA[R9:R0] was received with noise. 15 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 MATCH LPUART Match Address Register 0x10 32 read-write 0 0xFFFFFFFF MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x14 32 read-write 0 0xFFFFFFFF TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full. #1 TXCTSC Transmit CTS Configuration 4 1 read-write 0 CTS input is sampled at the start of each character. #0 1 CTS input is sampled when the transmitter is idle. #1 TXCTSSRC Transmit CTS Source 5 1 read-write 0 CTS input is the LPUART_CTS pin. #0 1 CTS input is the inverted Receiver Match result. #1 RTSWATER Receive RTS Configuration 8 8 read-write 0 RTS asserts when the receiver FIFO is full or receiving a character that causes the FIFO to become full. #0 1 RTS asserts when the receive FIFO is less than or equal to the RXWATER configuration and negates when the receive FIFO is greater than the RXWATER configuration. #1 TNP Transmitter narrow pulse 16 2 read-write 00 1/OSR. #00 01 2/OSR. #01 10 3/OSR. #10 11 4/OSR. #11 IREN Infrared enable 18 1 read-write 0 IR disabled. #0 1 IR enabled. #1 FIFO LPUART FIFO Register 0x18 32 read-write 0x22 0xFFFFFFFF RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 111 Receive FIFO/Buffer depth = 256 datawords. #111 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 111 Transmit FIFO/Buffer depth = 256 datawords #111 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 RXUFE Receive FIFO Underflow Interrupt Enable 8 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 9 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 RXIDEN Receiver Idle Empty Enable 10 3 read-write 000 Disable RDRF assertion due to partially filled FIFO when receiver is idle. #000 001 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. #001 010 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. #010 011 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. #011 100 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. #100 101 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. #101 110 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. #110 111 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. #111 RXFLUSH Receive FIFO/Buffer Flush 14 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 TXFLUSH Transmit FIFO/Buffer Flush 15 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 RXUF Receiver Buffer Underflow Flag 16 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXOF Transmitter Buffer Overflow Flag 17 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 RXEMPT Receive Buffer/FIFO Empty 22 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 TXEMPT Transmit Buffer/FIFO Empty 23 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 WATER LPUART Watermark Register 0x1C 32 read-write 0 0xFFFFFFFF TXWATER Transmit Watermark 0 8 read-write TXCOUNT Transmit Counter 8 8 read-only RXWATER Receive Watermark 16 8 read-write RXCOUNT Receive Counter 24 8 read-only LPUART4 Universal Asynchronous Receiver/Transmitter LPUART LPUART4_ 0x400D6000 0 0x20 registers LPUART4 34 BAUD LPUART Baud Rate Register 0 32 read-write 0xF000004 0xFFFFFFFF SBR Baud Rate Modulo Divisor. 0 13 read-write SBNS Stop Bit Number Select 13 1 read-write 0 One stop bit. #0 1 Two stop bits. #1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write 0 Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. #1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write 0 Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. #1 RESYNCDIS Resynchronization Disable 16 1 read-write 0 Resynchronization during received data word is supported #0 1 Resynchronization during received data word is disabled #1 BOTHEDGE Both Edge Sampling 17 1 read-write 0 Receiver samples input data using the rising edge of the baud rate clock. #0 1 Receiver samples input data using the rising and falling edge of the baud rate clock. #1 MATCFG Match Configuration 18 2 read-write 00 Address Match Wakeup #00 01 Idle Match Wakeup #01 10 Match On and Match Off #10 11 Enables RWU on Data Match and Match On/Off for transmitter CTS input #11 RDMAE Receiver Full DMA Enable 21 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 TDMAE Transmitter DMA Enable 23 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 OSR Over Sampling Ratio 24 5 read-write M10 10-bit Mode select 29 1 read-write 0 Receiver and transmitter use 8-bit or 9-bit data characters. #0 1 Receiver and transmitter use 10-bit data characters. #1 MAEN2 Match Address Mode Enable 2 30 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA2]. #1 MAEN1 Match Address Mode Enable 1 31 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA1]. #1 STAT LPUART Status Register 0x4 32 read-write 0xC00000 0xFFFFFFFF MA2F Match 2 Flag 14 1 read-write 0 Received data is not equal to MA2 #0 1 Received data is equal to MA2 #1 MA1F Match 1 Flag 15 1 read-write 0 Received data is not equal to MA1 #0 1 Received data is equal to MA1 #1 PF Parity Error Flag 16 1 read-write 0 No parity error. #0 1 Parity error. #1 FE Framing Error Flag 17 1 read-write 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 NF Noise Flag 18 1 read-write 0 No noise detected. #0 1 Noise detected in the received character in LPUART_DATA. #1 OR Receiver Overrun Flag 19 1 read-write 0 No overrun. #0 1 Receive overrun (new LPUART data lost). #1 IDLE Idle Line Flag 20 1 read-write 0 No idle line detected. #0 1 Idle line was detected. #1 RDRF Receive Data Register Full Flag 21 1 read-only 0 Receive data buffer empty. #0 1 Receive data buffer full. #1 TC Transmission Complete Flag 22 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 23 1 read-only 0 Transmit data buffer full. #0 1 Transmit data buffer empty. #1 RAF Receiver Active Flag 24 1 read-only 0 LPUART receiver idle waiting for a start bit. #0 1 LPUART receiver active (LPUART_RX input not idle). #1 LBKDE LIN Break Detection Enable 25 1 read-write 0 Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1). #1 BRK13 Break Character Generation Length 26 1 read-write 0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1). #1 RWUID Receive Wake Up Idle Detect 27 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match. #1 RXINV Receive Data Inversion 28 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 MSBF MSB First 29 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. #1 RXEDGIF LPUART_RX Pin Active Edge Interrupt Flag 30 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 CTRL LPUART Control Register 0x8 32 read-write 0 0xFFFFFFFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Configures RWU for idle-line wakeup. #0 1 Configures RWU with address-mark wakeup. #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Receiver and transmitter use 8-bit data characters. #0 1 Receiver and transmitter use 9-bit data characters. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin. #0 1 Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input. #1 DOZEEN Doze Enable 6 1 read-write 0 LPUART is enabled in Doze mode. #0 1 LPUART is disabled in Doze mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - LPUART_RX and LPUART_TX use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). #1 IDLECFG Idle Configuration 8 3 read-write 000 1 idle character #000 001 2 idle characters #001 010 4 idle characters #010 011 8 idle characters #011 100 16 idle characters #100 101 32 idle characters #101 110 64 idle characters #110 111 128 idle characters #111 MA2IE Match 2 Interrupt Enable 14 1 read-write 0 MA2F interrupt disabled #0 1 MA2F interrupt enabled #1 MA1IE Match 1 Interrupt Enable 15 1 read-write 0 MA1F interrupt disabled #0 1 MA1F interrupt enabled #1 SBK Send Break 16 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 RWU Receiver Wakeup Control 17 1 read-write 0 Normal receiver operation. #0 1 LPUART receiver in standby waiting for wakeup condition. #1 RE Receiver Enable 18 1 read-write 0 Receiver disabled. #0 1 Receiver enabled. #1 TE Transmitter Enable 19 1 read-write 0 Transmitter disabled. #0 1 Transmitter enabled. #1 ILIE Idle Line Interrupt Enable 20 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 RIE Receiver Interrupt Enable 21 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TIE Transmit Interrupt Enable 23 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 PEIE Parity Error Interrupt Enable 24 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 FEIE Framing Error Interrupt Enable 25 1 read-write 0 FE interrupts disabled; use polling. #0 1 Hardware interrupt requested when FE is set. #1 NEIE Noise Error Interrupt Enable 26 1 read-write 0 NF interrupts disabled; use polling. #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 27 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 TXINV Transmit Data Inversion 28 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 TXDIR LPUART_TX Pin Direction in Single-Wire Mode 29 1 read-write 0 LPUART_TX pin is an input in single-wire mode. #0 1 LPUART_TX pin is an output in single-wire mode. #1 R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write DATA LPUART Data Register 0xC 32 read-write 0x1000 0xFFFFFFFF R0T0 Read receive data buffer 0 or write transmit data buffer 0. 0 1 read-write R1T1 Read receive data buffer 1 or write transmit data buffer 1. 1 1 read-write R2T2 Read receive data buffer 2 or write transmit data buffer 2. 2 1 read-write R3T3 Read receive data buffer 3 or write transmit data buffer 3. 3 1 read-write R4T4 Read receive data buffer 4 or write transmit data buffer 4. 4 1 read-write R5T5 Read receive data buffer 5 or write transmit data buffer 5. 5 1 read-write R6T6 Read receive data buffer 6 or write transmit data buffer 6. 6 1 read-write R7T7 Read receive data buffer 7 or write transmit data buffer 7. 7 1 read-write R8T8 Read receive data buffer 8 or write transmit data buffer 8. 8 1 read-write R9T9 Read receive data buffer 9 or write transmit data buffer 9. 9 1 read-write IDLINE Idle Line 11 1 read-only 0 Receiver was not idle before receiving this character. #0 1 Receiver was idle before receiving this character. #1 RXEMPT Receive Buffer Empty 12 1 read-only 0 Receive buffer contains valid data. #0 1 Receive buffer is empty, data returned on read is not valid. #1 FRETSC Frame Error / Transmit Special Character 13 1 read-write 0 The dataword was received without a frame error on read, transmit a normal character on write. #0 1 The dataword was received with a frame error, transmit an idle or break character on transmit. #1 PARITYE The current received dataword contained in DATA[R9:R0] was received with a parity error. 14 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 NOISY The current received dataword contained in DATA[R9:R0] was received with noise. 15 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 MATCH LPUART Match Address Register 0x10 32 read-write 0 0xFFFFFFFF MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x14 32 read-write 0 0xFFFFFFFF TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full. #1 TXCTSC Transmit CTS Configuration 4 1 read-write 0 CTS input is sampled at the start of each character. #0 1 CTS input is sampled when the transmitter is idle. #1 TXCTSSRC Transmit CTS Source 5 1 read-write 0 CTS input is the LPUART_CTS pin. #0 1 CTS input is the inverted Receiver Match result. #1 RTSWATER Receive RTS Configuration 8 8 read-write 0 RTS asserts when the receiver FIFO is full or receiving a character that causes the FIFO to become full. #0 1 RTS asserts when the receive FIFO is less than or equal to the RXWATER configuration and negates when the receive FIFO is greater than the RXWATER configuration. #1 TNP Transmitter narrow pulse 16 2 read-write 00 1/OSR. #00 01 2/OSR. #01 10 3/OSR. #10 11 4/OSR. #11 IREN Infrared enable 18 1 read-write 0 IR disabled. #0 1 IR enabled. #1 FIFO LPUART FIFO Register 0x18 32 read-write 0x22 0xFFFFFFFF RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 111 Receive FIFO/Buffer depth = 256 datawords. #111 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 111 Transmit FIFO/Buffer depth = 256 datawords #111 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 RXUFE Receive FIFO Underflow Interrupt Enable 8 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 9 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 RXIDEN Receiver Idle Empty Enable 10 3 read-write 000 Disable RDRF assertion due to partially filled FIFO when receiver is idle. #000 001 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. #001 010 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. #010 011 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. #011 100 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. #100 101 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. #101 110 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. #110 111 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. #111 RXFLUSH Receive FIFO/Buffer Flush 14 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 TXFLUSH Transmit FIFO/Buffer Flush 15 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 RXUF Receiver Buffer Underflow Flag 16 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXOF Transmitter Buffer Overflow Flag 17 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 RXEMPT Receive Buffer/FIFO Empty 22 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 TXEMPT Transmit Buffer/FIFO Empty 23 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 WATER LPUART Watermark Register 0x1C 32 read-write 0 0xFFFFFFFF TXWATER Transmit Watermark 0 8 read-write TXCOUNT Transmit Counter 8 8 read-only RXWATER Receive Watermark 16 8 read-write RXCOUNT Receive Counter 24 8 read-only TPM1 Timer/PWM Module TPM TPM1_ 0x400C9000 0 0x88 registers TPM1 88 SC Status and Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CMOD Clock Mode Selection 3 2 read-write 00 TPM counter is disabled #00 01 TPM counter increments on every TPM counter clock #01 10 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock #10 CPWMS Center-Aligned PWM Select 5 1 read-write 0 TPM counter operates in up counting mode. #0 1 TPM counter operates in up-down counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling or DMA request. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 DMA DMA Enable 8 1 read-write 0 Disables DMA transfers. #0 1 Enables DMA transfers. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter value 0 16 read-write MOD Modulo 0x8 32 read-write 0xFFFF 0xFFFFFFFF MOD Modulo value 0 16 read-write 2 0x8 0,1 C%sSC Channel (n) Status and Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 2 0x8 0,1 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write STATUS Capture and Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 TOF Timer Overflow Flag 8 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 COMBINE Combine Channel Register 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels 0 and 1 0 1 read-write 0 Channels 0 and 1 are independent. #0 1 Channels 0 and 1 are combined. #1 COMSWAP0 Combine Channel 0 and 1 Swap 1 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 POL Channel Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FILTER Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Filter Value 0 4 read-write CH1FVAL Channel 1 Filter Value 4 4 read-write QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Enables the quadrature decoder mode 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 TOFDIR Indicates if the TOF bit was set on the top or the bottom of counting. 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). #1 QUADIR Counter Direction in Quadrature Decode Mode 2 1 read-only 0 Counter direction is decreasing (counter decrement). #0 1 Counter direction is increasing (counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase encoding mode. #0 1 Count and direction encoding mode. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF DOZEEN Doze Enable 5 1 read-write 0 Internal TPM counter continues in Doze mode. #0 1 Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. #1 DBGMODE Debug Mode 6 2 read-write 00 TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. #00 11 TPM counter continues in debug mode. #11 GTBSYNC Global Time Base Synchronization 8 1 read-write 0 Global timebase synchronization disabled. #0 1 Global timebase synchronization enabled. #1 GTBEEN Global time base enable 9 1 read-write 0 All channels use the internally generated TPM counter as their timebase #0 1 All channels use an externally generated global timebase as their timebase #1 CSOT Counter Start on Trigger 16 1 read-write 0 TPM counter starts to increment immediately, once it is enabled. #0 1 TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. #1 CSOO Counter Stop On Overflow 17 1 read-write 0 TPM counter continues incrementing or decrementing after overflow #0 1 TPM counter stops incrementing or decrementing after overflow. #1 CROT Counter Reload On Trigger 18 1 read-write 0 Counter is not reloaded due to a rising edge on the selected input trigger #0 1 Counter is reloaded when a rising edge is detected on the selected input trigger #1 CPOT Counter Pause On Trigger 19 1 read-write TRGPOL Trigger Polarity 22 1 read-write 0 Trigger is active high. #0 1 Trigger is active low. #1 TRGSRC Trigger Source 23 1 read-write 0 Trigger source selected by TRGSEL is external. #0 1 Trigger source selected by TRGSEL is internal (channel pin input capture). #1 TRGSEL Trigger Select 24 4 read-write 0001 Channel 0 pin input capture #0001 0010 Channel 1 pin input capture #0010 0011 Channel 0 or Channel 1 pin input capture #0011 TPM2 Timer/PWM Module TPM TPM2_ 0x400CA000 0 0x88 registers TPM2 89 SC Status and Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CMOD Clock Mode Selection 3 2 read-write 00 TPM counter is disabled #00 01 TPM counter increments on every TPM counter clock #01 10 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock #10 CPWMS Center-Aligned PWM Select 5 1 read-write 0 TPM counter operates in up counting mode. #0 1 TPM counter operates in up-down counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling or DMA request. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 DMA DMA Enable 8 1 read-write 0 Disables DMA transfers. #0 1 Enables DMA transfers. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter value 0 16 read-write MOD Modulo 0x8 32 read-write 0xFFFF 0xFFFFFFFF MOD Modulo value 0 16 read-write 2 0x8 0,1 C%sSC Channel (n) Status and Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 2 0x8 0,1 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write STATUS Capture and Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 TOF Timer Overflow Flag 8 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 COMBINE Combine Channel Register 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels 0 and 1 0 1 read-write 0 Channels 0 and 1 are independent. #0 1 Channels 0 and 1 are combined. #1 COMSWAP0 Combine Channel 0 and 1 Swap 1 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 POL Channel Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FILTER Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Filter Value 0 4 read-write CH1FVAL Channel 1 Filter Value 4 4 read-write QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Enables the quadrature decoder mode 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 TOFDIR Indicates if the TOF bit was set on the top or the bottom of counting. 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). #1 QUADIR Counter Direction in Quadrature Decode Mode 2 1 read-only 0 Counter direction is decreasing (counter decrement). #0 1 Counter direction is increasing (counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase encoding mode. #0 1 Count and direction encoding mode. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF DOZEEN Doze Enable 5 1 read-write 0 Internal TPM counter continues in Doze mode. #0 1 Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. #1 DBGMODE Debug Mode 6 2 read-write 00 TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. #00 11 TPM counter continues in debug mode. #11 GTBSYNC Global Time Base Synchronization 8 1 read-write 0 Global timebase synchronization disabled. #0 1 Global timebase synchronization enabled. #1 GTBEEN Global time base enable 9 1 read-write 0 All channels use the internally generated TPM counter as their timebase #0 1 All channels use an externally generated global timebase as their timebase #1 CSOT Counter Start on Trigger 16 1 read-write 0 TPM counter starts to increment immediately, once it is enabled. #0 1 TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. #1 CSOO Counter Stop On Overflow 17 1 read-write 0 TPM counter continues incrementing or decrementing after overflow #0 1 TPM counter stops incrementing or decrementing after overflow. #1 CROT Counter Reload On Trigger 18 1 read-write 0 Counter is not reloaded due to a rising edge on the selected input trigger #0 1 Counter is reloaded when a rising edge is detected on the selected input trigger #1 CPOT Counter Pause On Trigger 19 1 read-write TRGPOL Trigger Polarity 22 1 read-write 0 Trigger is active high. #0 1 Trigger is active low. #1 TRGSRC Trigger Source 23 1 read-write 0 Trigger source selected by TRGSEL is external. #0 1 Trigger source selected by TRGSEL is internal (channel pin input capture). #1 TRGSEL Trigger Select 24 4 read-write 0001 Channel 0 pin input capture #0001 0010 Channel 1 pin input capture #0010 0011 Channel 0 or Channel 1 pin input capture #0011 DAC0 12-Bit Digital-to-Analog Converter DAC0_ 0x400CC000 0 0x24 registers DAC0 56 16 0x2 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 DAT%sL DAC Data Low Register 0 8 read-write 0 0xFF DATA0 DATA0 0 8 read-write 16 0x2 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 DAT%sH DAC Data High Register 0x1 8 read-write 0 0xFF DATA1 DATA1 0 4 read-write SR DAC Status Register 0x20 8 read-write 0x2 0xFF DACBFRPBF DAC Buffer Read Pointer Bottom Position Flag 0 1 read-write 0 The DAC buffer read pointer is not equal to C2[DACBFUP]. #0 1 The DAC buffer read pointer is equal to C2[DACBFUP]. #1 DACBFRPTF DAC Buffer Read Pointer Top Position Flag 1 1 read-write 0 The DAC buffer read pointer is not zero. #0 1 The DAC buffer read pointer is zero. #1 DACBFWMF DAC Buffer Watermark Flag 2 1 read-write 0 The DAC buffer read pointer has not reached the watermark level. #0 1 The DAC buffer read pointer has reached the watermark level. #1 C0 DAC Control Register 0x21 8 read-write 0 0xFF DACBBIEN DAC Buffer Read Pointer Bottom Flag Interrupt Enable 0 1 read-write 0 The DAC buffer read pointer bottom flag interrupt is disabled. #0 1 The DAC buffer read pointer bottom flag interrupt is enabled. #1 DACBTIEN DAC Buffer Read Pointer Top Flag Interrupt Enable 1 1 read-write 0 The DAC buffer read pointer top flag interrupt is disabled. #0 1 The DAC buffer read pointer top flag interrupt is enabled. #1 DACBWIEN DAC Buffer Watermark Interrupt Enable 2 1 read-write 0 The DAC buffer watermark interrupt is disabled. #0 1 The DAC buffer watermark interrupt is enabled. #1 LPEN DAC Low Power Control 3 1 read-write 0 High-Power mode #0 1 Low-Power mode #1 DACSWTRG DAC Software Trigger 4 1 write-only 0 The DAC soft trigger is not valid. #0 1 The DAC soft trigger is valid. #1 DACTRGSEL DAC Trigger Select 5 1 read-write 0 The DAC hardware trigger is selected. #0 1 The DAC software trigger is selected. #1 DACRFS DAC Reference Select 6 1 read-write 0 The DAC selects DACREF_1 as the reference voltage. #0 1 The DAC selects DACREF_2 as the reference voltage. #1 DACEN DAC Enable 7 1 read-write 0 The DAC system is disabled. #0 1 The DAC system is enabled. #1 C1 DAC Control Register 1 0x22 8 read-write 0 0xFF DACBFEN DAC Buffer Enable 0 1 read-write 0 Buffer read pointer is disabled. The converted data is always the first word of the buffer. #0 1 Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. #1 DACBFMD DAC Buffer Work Mode Select 1 2 read-write 00 Normal mode #00 01 Swing mode #01 10 One-Time Scan mode #10 11 FIFO mode #11 DACBFWM DAC Buffer Watermark Select 3 2 read-write 00 In normal mode, 1 word . In FIFO mode, 2 or less than 2 data remaining in FIFO will set watermark status bit. #00 01 In normal mode, 2 words . In FIFO mode, Max/4 or less than Max/4 data remaining in FIFO will set watermark status bit. #01 10 In normal mode, 3 words . In FIFO mode, Max/2 or less than Max/2 data remaining in FIFO will set watermark status bit. #10 11 In normal mode, 4 words . In FIFO mode, Max-2 or less than Max-2 data remaining in FIFO will set watermark status bit. #11 DMAEN DMA Enable Select 7 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time. #1 C2 DAC Control Register 2 0x23 8 read-write 0xF 0xFF DACBFUP DAC Buffer Upper Limit 0 4 read-write DACBFRP DAC Buffer Read Pointer 4 4 read-write LTC0 LTC 0x400D1000 0 0xF00 registers LTC0 104 LTC0_MD LTC Mode Register (non-PKHA/non-RNG use) LTC0 0 32 read-write 0 0xFFFFFFFF ENC Encrypt/Decrypt. This bit selects encryption or decryption. 0 1 read-write 0 Decrypt. #0 1 Encrypt. #1 ICV_TEST ICV Checking / Test AES fault detection 1 1 read-write AS Algorithm State 2 2 read-write 00 Update #00 01 Initialize #01 10 Finalize #10 11 Initialize/Finalize #11 AAI Additional Algorithm information 4 9 read-write ALG Algorithm. This field specifies which algorithm is being selected. 16 8 read-write 00010000 AES #10000 00100000 DES #100000 00100001 3DES #100001 LTC0_MDPK LTC Mode Register (PublicKey) LTC0 0 32 read-write 0 0xFFFFFFFF PKHA_MODE_LS PKHA_MODE least significant 12 bits 0 12 read-write PKHA_MODE_MS PKHA_MODE most-significant 4 bits 16 4 read-write ALG Algorithm. This field specifies which algorithm is being selected. 20 4 read-write 1000 PKHA #1000 LTC0_KS LTC Key Size Register 0x8 32 read-write 0 0xFFFFFFFF KS Key Size. This is the size of a Key measured in bytes 0 6 read-write LTC0_DS LTC Data Size Register 0x10 32 read-write 0 0xFFFFFFFF DS Data Size 0 12 read-write LTC0_ICVS LTC ICV Size Register 0x18 32 read-write 0 0xFFFFFFFF ICVS ICV Size, in Bytes. 0 5 read-write LTC0_COM LTC Command Register 0x30 32 read-write 0 0xFFFFFFFF ALL Reset All Internal Logic 0 1 write-only 0 Do Not Reset #0 1 Reset all CHAs in use by this CCB. #1 AES Reset AESA. Writing a 1 to this bit resets the AES Accelerator core engine. 1 1 write-only 0 Do Not Reset #0 1 Reset AES Accelerator #1 DES Reset DESA. Writing a 1 to this bit resets the DES Accelerator. 2 1 write-only 0 Do Not Reset #0 1 Reset DES Accelerator #1 PK Reset PKHA. Writing a 1 to this bit resets the Public Key Hardware Accelerator. 6 1 write-only 0 Do Not Reset #0 1 Reset Public Key Hardware Accelerator #1 LTC0_CTL LTC Control Register 0x34 32 read-write 0 0xFFFFFFFF IM Interrupt Mask. Once this bit is set, it can only be cleared by hard reset. 0 1 read-write 0 Interrupt not masked. #0 1 Interrupt masked #1 PDE PKHA Register DMA Enable. 4 1 read-write 0 DMA Request and Done signals disabled for the PKHA Registers. #0 1 DMA Request and Done signals enabled for the PKHA Registers. #1 IFE Input FIFO DMA Enable. 8 1 read-write 0 DMA Request and Done signals disabled for the Input FIFO. #0 1 DMA Request and Done signals enabled for the Input FIFO. #1 IFR Input FIFO DMA Request Size 9 1 read-write 0 DMA request size is 1 entry. #0 1 DMA request size is 4 entries. #1 OFE Output FIFO DMA Enable. 12 1 read-write 0 DMA Request and Done signals disabled for the Output FIFO. #0 1 DMA Request and Done signals enabled for the Output FIFO. #1 OFR Output FIFO DMA Request Size 13 1 read-write 0 DMA request size is 1 entry. #0 1 DMA request size is 4 entries. #1 IFS Input FIFO Byte Swap. Byte swap all data that is written to the Input FIFO. 16 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 OFS Output FIFO Byte Swap. Byte swap all data that is read from the Onput FIFO. 17 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 KIS Key Register Input Byte Swap 20 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 KOS Key Register Output Byte Swap 21 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 CIS Context Register Input Byte Swap 22 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 COS Context Register Output Byte Swap 23 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 KAL Key Register Access Lock 31 1 read-write 0 Key Register is readable. #0 1 Key Register is not readable. #1 LTC0_CW LTC Clear Written Register 0x40 32 read-write 0 0xFFFFFFFF CM Clear the Mode Register. Writing a one to this bit causes the Mode Register to be cleared. 0 1 write-only CDS Clear the Data Size Register 2 1 write-only CICV Clear the ICV Size Register. Writing a one to this bit causes the ICV Size Register to be cleared. 3 1 write-only CCR Clear the Context Register. Writing a one to this bit causes the Context Register to be cleared. 5 1 write-only CKR Clear the Key Register 6 1 write-only CPKA Clear the PKHA A Size Register 12 1 write-only CPKB Clear the PKHA B Size Register 13 1 write-only CPKN Clear the PKHA N Size Register 14 1 write-only CPKE Clear the PKHA E Size Register 15 1 write-only COF Clear Output FIFO. Writing a 1 to this bit causes the Output FIFO to be cleared. 30 1 write-only CIF Clear Input FIFO. Writing a 1 to this bit causes the Input Data FIFO. 31 1 write-only LTC0_STA LTC Status Register 0x48 32 read-write 0 0xFFFFFFFF AB AESA Busy 1 1 read-only 0 AESA Idle #0 1 AESA Busy. #1 DB DESA Busy 2 1 read-only 0 DESA Idle #0 1 DESA Busy. #1 PB PKHA Busy 6 1 read-only 0 PKHA Idle #0 1 PKHA Busy. #1 DI Done Interrupt 16 1 read-write EI Error Interrupt 20 1 read-only 0 Not Error. #0 1 Error Interrupt. #1 PKP Public Key is Prime 28 1 read-only PKO Public Key Operation is One 29 1 read-only PKZ Public Key Operation is Zero 30 1 read-only LTC0_ESTA LTC Error Status Register 0x4C 32 read-only 0 0xFFFFFFFF ERRID1 Error ID 1 0 4 read-only 0001 Mode Error #0001 0010 Data Size Error, including PKHA N Register Size Error #0010 0011 Key Size Error, including PKHA E Register Size Error #0011 0100 PKHA A Register Size Error #0100 0101 PKHA B Register Size Error #0101 0110 Data Arrived out of Sequence Error #0110 0111 PKHA Divide by Zero Error #0111 1000 PKHA Modulus Even Error #1000 1001 DES Key Parity Error #1001 1010 ICV Check Failed #1010 1011 Internal Hardware Failure #1011 1100 CCM AAD Size Error (either 1. AAD flag in B0 =1 and no AAD type provided, 2. AAD flag in B0 = 0 and AAD povided, or 3. AAD flag in B0 =1 and not enough AAD provided - expecting more based on AAD size.) #1100 1111 Invalid Crypto Engine Selected #1111 CL1 algorithms. The algorithms field indicates which algorithm is asserting an error. Others reserved 8 4 read-only 0000 LTC General Error #0000 0001 AES #0001 0010 DES #0010 1000 Public Key #1000 LTC0_AADSZ LTC AAD Size Register 0x58 32 read-write 0 0xFFFFFFFF AADSZ AAD size in Bytes, mod 16. 0 4 read-write AL AAD Last. Only AAD data will be written into the Input FIFO. 31 1 read-write LTC0_IVSZ LTC IV Size Register 0x60 32 read-write 0 0xFFFFFFFF IVSZ IV size in Bytes, mod 16. 0 4 read-write IL IV Last. Only IV data will be written into the Input FIFO. 31 1 read-write LTC0_DPAMS LTC DPA Mask Seed Register 0x68 32 write-only 0 0xFFFFFFFF DPAMS Differential Power Analysis Mask Seed 0 32 write-only LTC0_PKASZ LTC PKHA A Size Register 0x80 32 read-write 0 0xFFFFFFFF PKASZ PKHA A Size. This is the size of the numeric value, in bytes, contained within the PKHA A Register. 0 9 read-write LTC0_PKBSZ LTC PKHA B Size Register 0x88 32 read-write 0 0xFFFFFFFF PKBSZ PKHA B Size. This is the size of the numeric value, in bytes, contained within the PKHA B Register. 0 9 read-write LTC0_PKNSZ LTC PKHA N Size Register 0x90 32 read-write 0 0xFFFFFFFF PKNSZ PKHA N Size. This is the size of the numeric value, in bytes, contained within the PKHA N Register. 0 9 read-write LTC0_PKESZ LTC PKHA E Size Register 0x98 32 read-write 0 0xFFFFFFFF PKESZ PKHA E Size. This is the size of the numeric value, in bytes, contained within the PKHA E Register. 0 9 read-write LTC0_CTX_0 LTC Context Register 0x100 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC0_CTX_1 LTC Context Register 0x104 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC0_CTX_2 LTC Context Register 0x108 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC0_CTX_3 LTC Context Register 0x10C 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC0_CTX_4 LTC Context Register 0x110 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC0_CTX_5 LTC Context Register 0x114 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC0_CTX_6 LTC Context Register 0x118 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC0_CTX_7 LTC Context Register 0x11C 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC0_CTX_8 LTC Context Register 0x120 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC0_CTX_9 LTC Context Register 0x124 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC0_CTX_10 LTC Context Register 0x128 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC0_CTX_11 LTC Context Register 0x12C 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC0_CTX_12 LTC Context Register 0x130 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC0_CTX_13 LTC Context Register 0x134 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC0_CTX_14 LTC Context Register 0x138 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC0_CTX_15 LTC Context Register 0x13C 32 read-write 0 0xFFFFFFFF CTX CTX 0 32 read-write LTC0_KEY_0 LTC Key Registers 0x200 32 read-write 0 0xFFFFFFFF KEY KEY 0 32 read-write LTC0_KEY_1 LTC Key Registers 0x204 32 read-write 0 0xFFFFFFFF KEY KEY 0 32 read-write LTC0_KEY_2 LTC Key Registers 0x208 32 read-write 0 0xFFFFFFFF KEY KEY 0 32 read-write LTC0_KEY_3 LTC Key Registers 0x20C 32 read-write 0 0xFFFFFFFF KEY KEY 0 32 read-write LTC0_KEY_4 LTC Key Registers 0x210 32 read-write 0 0xFFFFFFFF KEY KEY 0 32 read-write LTC0_KEY_5 LTC Key Registers 0x214 32 read-write 0 0xFFFFFFFF KEY KEY 0 32 read-write LTC0_KEY_6 LTC Key Registers 0x218 32 read-write 0 0xFFFFFFFF KEY KEY 0 32 read-write LTC0_KEY_7 LTC Key Registers 0x21C 32 read-write 0 0xFFFFFFFF KEY KEY 0 32 read-write LTC0_RNG4_DRNG_STATUS LTC RNG4 DRNG Status 0x300 32 read-only 0 0xFFFFFFFF IF0 Instantiated Flag 0. State Handle 0 has been instantiated. 0 1 read-only IF1 Instantiated Flag 1. State Handle 1 has been instantiated. 1 1 read-only PR0 Prediction Resistance State Handle 0 4 1 read-only PR1 Prediction Resistance State Handle 1 5 1 read-only TF0 Test Flag State Handle 0. State Handle 0 has been instantiated as a test (deterministic) instance. 8 1 read-only TF1 Test Flag State Handle 1. State Handle 1 has been instantiated as a test (deterministic) instance. 9 1 read-only ERRCODE Error Code 16 4 read-only CE Catastrophic Error 20 1 read-only LTC0_RNG4_DRNG_INTERVAL_0 LTC RNG4 DRNG Interval 0 Register 0x310 32 read-only 0 0xFFFFFFFF RESINT0 This read-only register holds the Reseed Interval for State Handle 0. 0 32 read-only LTC0_RNG4_DRNG_INTERVAL_1 LTC RNG4 DRNG Interval 1 Register 0x314 32 read-only 0 0xFFFFFFFF RESINT1 This read-only register holds the Reseed Interval for State Handle 1. 0 32 read-only LTC0_RNG4_DRNG_HASH_CONTROL LTC RNG4 DRNG Hash Control Register 0x340 32 read-write 0 0xFFFFFFFF HD Hashing Done. This bit asserts when the hashing engine is done. 0 1 read-only HB Hashing Begin. Writing this bit will cause the Hashing Engine to begin hashing. 1 1 write-only HI Hashing Initialize. Writing this bit will initialize the Hashing Engine. 2 1 write-only HTM Hashing Test Mode. Writing this bit will put RNG in Hashing Test Mode. 3 1 read-write HTC Hashing Test Mode Clear. Writing this bit will take the RNG out of hashing test mode. 4 1 write-only LTC0_RNG4_DRNG_HASH_DIGEST LTC RNG4 DRNG Hash Digest Register 0x344 32 read-only 0 0xFFFFFFFF HASHMD Hashing Message Digest Register 0 32 read-only LTC0_RNG4_DRNG_DEBUG_BUFFER LTC RNG4 DRNG Debug Buffer 0x348 32 write-only 0 0xFFFFFFFF HASHBUF This write-only register provides access to the internal SHA-256 hashing engine's 64-byte buffer 0 32 write-only LTC0_VID1 LTC Version ID Register 0x4F0 32 read-only 0x340100 0xFFFFFFFF MIN_REV Minor revision number(0x00). 0 8 read-only MAJ_REV Major revision number(0x01). 8 8 read-only IP_ID ID(0x0038). 16 16 read-only LTC0_CHAVID LTC CHA Version ID Register 0x4F8 32 read-only 0x440151 0xFFFFFF AESREV AES Revision Number(0x1). 0 4 read-only AESVID AES Version ID(0x5). 4 4 read-only DESREV DES Revision Number(0x1). 8 4 read-only DESVID DES Version ID(0x0). 12 4 read-only PKHAREV PK Revision Number(0x4). 16 4 read-only PKHAVID PK Version ID(0x4). 20 4 read-only LTC0_FIFOSTA LTC FIFO Status Register 0x7C0 32 read-only 0 0xFFFFFFFF IFL Input FIFO Level. These bits indicate the current number of entries in the Input FIFO. 0 7 read-only IFF Input FIFO Full. The Input FIFO is full and should not be written to. 15 1 read-only OFL Output FIFO Level. These bits indicate the current number of entries in the Output FIFO. 16 7 read-only OFF Output FIFO Full. The Output FIFO is full and should not be written to. 31 1 read-only LTC0_IFIFO LTC Input Data FIFO 0x7E0 32 write-only 0 0xFFFFFFFF IFIFO IFIFO 0 32 write-only LTC0_OFIFO LTC Output Data FIFO 0x7F0 32 read-only 0 0xFFFFFFFF OFIFO Output FIFO 0 32 read-only LTC0_PKA0_0 LTC PKHA A0 0 Register LTC0 0x800 32 read-write 0 0xFFFFFFFF PKHA_A0 A0 VALUE 0 32 read-write LTC0_PKA_0 LTC PKHA A 0 Register LTC0 0x800 32 read-write 0 0xFFFFFFFF LTC0_PKA0_1 LTC PKHA A0 1 Register LTC0 0x804 32 read-write 0 0xFFFFFFFF PKHA_A0 A0 VALUE 0 32 read-write LTC0_PKA_1 LTC PKHA A 1 Register LTC0 0x804 32 read-write 0 0xFFFFFFFF LTC0_PKA0_2 LTC PKHA A0 2 Register LTC0 0x808 32 read-write 0 0xFFFFFFFF PKHA_A0 A0 VALUE 0 32 read-write LTC0_PKA_2 LTC PKHA A 2 Register LTC0 0x808 32 read-write 0 0xFFFFFFFF LTC0_PKA0_3 LTC PKHA A0 3 Register LTC0 0x80C 32 read-write 0 0xFFFFFFFF PKHA_A0 A0 VALUE 0 32 read-write LTC0_PKA_3 LTC PKHA A 3 Register LTC0 0x80C 32 read-write 0 0xFFFFFFFF LTC0_PKA0_4 LTC PKHA A0 4 Register LTC0 0x810 32 read-write 0 0xFFFFFFFF PKHA_A0 A0 VALUE 0 32 read-write LTC0_PKA_4 LTC PKHA A 4 Register LTC0 0x810 32 read-write 0 0xFFFFFFFF LTC0_PKA0_5 LTC PKHA A0 5 Register LTC0 0x814 32 read-write 0 0xFFFFFFFF PKHA_A0 A0 VALUE 0 32 read-write LTC0_PKA_5 LTC PKHA A 5 Register LTC0 0x814 32 read-write 0 0xFFFFFFFF LTC0_PKA0_6 LTC PKHA A0 6 Register LTC0 0x818 32 read-write 0 0xFFFFFFFF PKHA_A0 A0 VALUE 0 32 read-write LTC0_PKA_6 LTC PKHA A 6 Register LTC0 0x818 32 read-write 0 0xFFFFFFFF LTC0_PKA0_7 LTC PKHA A0 7 Register LTC0 0x81C 32 read-write 0 0xFFFFFFFF PKHA_A0 A0 VALUE 0 32 read-write LTC0_PKA_7 LTC PKHA A 7 Register LTC0 0x81C 32 read-write 0 0xFFFFFFFF LTC0_PKA0_8 LTC PKHA A0 8 Register LTC0 0x820 32 read-write 0 0xFFFFFFFF PKHA_A0 A0 VALUE 0 32 read-write LTC0_PKA_8 LTC PKHA A 8 Register LTC0 0x820 32 read-write 0 0xFFFFFFFF LTC0_PKA0_9 LTC PKHA A0 9 Register LTC0 0x824 32 read-write 0 0xFFFFFFFF PKHA_A0 A0 VALUE 0 32 read-write LTC0_PKA_9 LTC PKHA A 9 Register LTC0 0x824 32 read-write 0 0xFFFFFFFF LTC0_PKA0_10 LTC PKHA A0 10 Register LTC0 0x828 32 read-write 0 0xFFFFFFFF PKHA_A0 A0 VALUE 0 32 read-write LTC0_PKA_10 LTC PKHA A 10 Register LTC0 0x828 32 read-write 0 0xFFFFFFFF LTC0_PKA0_11 LTC PKHA A0 11 Register LTC0 0x82C 32 read-write 0 0xFFFFFFFF PKHA_A0 A0 VALUE 0 32 read-write LTC0_PKA_11 LTC PKHA A 11 Register LTC0 0x82C 32 read-write 0 0xFFFFFFFF LTC0_PKA0_12 LTC PKHA A0 12 Register LTC0 0x830 32 read-write 0 0xFFFFFFFF PKHA_A0 A0 VALUE 0 32 read-write LTC0_PKA_12 LTC PKHA A 12 Register LTC0 0x830 32 read-write 0 0xFFFFFFFF LTC0_PKA0_13 LTC PKHA A0 13 Register LTC0 0x834 32 read-write 0 0xFFFFFFFF PKHA_A0 A0 VALUE 0 32 read-write LTC0_PKA_13 LTC PKHA A 13 Register LTC0 0x834 32 read-write 0 0xFFFFFFFF LTC0_PKA0_14 LTC PKHA A0 14 Register LTC0 0x838 32 read-write 0 0xFFFFFFFF PKHA_A0 A0 VALUE 0 32 read-write LTC0_PKA_14 LTC PKHA A 14 Register LTC0 0x838 32 read-write 0 0xFFFFFFFF LTC0_PKA0_15 LTC PKHA A0 15 Register LTC0 0x83C 32 read-write 0 0xFFFFFFFF PKHA_A0 A0 VALUE 0 32 read-write LTC0_PKA_15 LTC PKHA A 15 Register LTC0 0x83C 32 read-write 0 0xFFFFFFFF LTC0_PKA1_0 LTC PKHA A1 0 Register LTC0 0x840 32 read-write 0 0xFFFFFFFF PKHA_A1 A1 VALUE 0 32 read-write LTC0_PKA_16 LTC PKHA A 16 Register LTC0 0x840 32 read-write 0 0xFFFFFFFF LTC0_PKA1_1 LTC PKHA A1 1 Register LTC0 0x844 32 read-write 0 0xFFFFFFFF PKHA_A1 A1 VALUE 0 32 read-write LTC0_PKA_17 LTC PKHA A 17 Register LTC0 0x844 32 read-write 0 0xFFFFFFFF LTC0_PKA1_2 LTC PKHA A1 2 Register LTC0 0x848 32 read-write 0 0xFFFFFFFF PKHA_A1 A1 VALUE 0 32 read-write LTC0_PKA_18 LTC PKHA A 18 Register LTC0 0x848 32 read-write 0 0xFFFFFFFF LTC0_PKA1_3 LTC PKHA A1 3 Register LTC0 0x84C 32 read-write 0 0xFFFFFFFF PKHA_A1 A1 VALUE 0 32 read-write LTC0_PKA_19 LTC PKHA A 19 Register LTC0 0x84C 32 read-write 0 0xFFFFFFFF LTC0_PKA1_4 LTC PKHA A1 4 Register LTC0 0x850 32 read-write 0 0xFFFFFFFF PKHA_A1 A1 VALUE 0 32 read-write LTC0_PKA_20 LTC PKHA A 20 Register LTC0 0x850 32 read-write 0 0xFFFFFFFF LTC0_PKA1_5 LTC PKHA A1 5 Register LTC0 0x854 32 read-write 0 0xFFFFFFFF PKHA_A1 A1 VALUE 0 32 read-write LTC0_PKA_21 LTC PKHA A 21 Register LTC0 0x854 32 read-write 0 0xFFFFFFFF LTC0_PKA1_6 LTC PKHA A1 6 Register LTC0 0x858 32 read-write 0 0xFFFFFFFF PKHA_A1 A1 VALUE 0 32 read-write LTC0_PKA_22 LTC PKHA A 22 Register LTC0 0x858 32 read-write 0 0xFFFFFFFF LTC0_PKA1_7 LTC PKHA A1 7 Register LTC0 0x85C 32 read-write 0 0xFFFFFFFF PKHA_A1 A1 VALUE 0 32 read-write LTC0_PKA_23 LTC PKHA A 23 Register LTC0 0x85C 32 read-write 0 0xFFFFFFFF LTC0_PKA1_8 LTC PKHA A1 8 Register LTC0 0x860 32 read-write 0 0xFFFFFFFF PKHA_A1 A1 VALUE 0 32 read-write LTC0_PKA_24 LTC PKHA A 24 Register LTC0 0x860 32 read-write 0 0xFFFFFFFF LTC0_PKA1_9 LTC PKHA A1 9 Register LTC0 0x864 32 read-write 0 0xFFFFFFFF PKHA_A1 A1 VALUE 0 32 read-write LTC0_PKA_25 LTC PKHA A 25 Register LTC0 0x864 32 read-write 0 0xFFFFFFFF LTC0_PKA1_10 LTC PKHA A1 10 Register LTC0 0x868 32 read-write 0 0xFFFFFFFF PKHA_A1 A1 VALUE 0 32 read-write LTC0_PKA_26 LTC PKHA A 26 Register LTC0 0x868 32 read-write 0 0xFFFFFFFF LTC0_PKA1_11 LTC PKHA A1 11 Register LTC0 0x86C 32 read-write 0 0xFFFFFFFF PKHA_A1 A1 VALUE 0 32 read-write LTC0_PKA_27 LTC PKHA A 27 Register LTC0 0x86C 32 read-write 0 0xFFFFFFFF LTC0_PKA1_12 LTC PKHA A1 12 Register LTC0 0x870 32 read-write 0 0xFFFFFFFF PKHA_A1 A1 VALUE 0 32 read-write LTC0_PKA_28 LTC PKHA A 28 Register LTC0 0x870 32 read-write 0 0xFFFFFFFF LTC0_PKA1_13 LTC PKHA A1 13 Register LTC0 0x874 32 read-write 0 0xFFFFFFFF PKHA_A1 A1 VALUE 0 32 read-write LTC0_PKA_29 LTC PKHA A 29 Register LTC0 0x874 32 read-write 0 0xFFFFFFFF LTC0_PKA1_14 LTC PKHA A1 14 Register LTC0 0x878 32 read-write 0 0xFFFFFFFF PKHA_A1 A1 VALUE 0 32 read-write LTC0_PKA_30 LTC PKHA A 30 Register LTC0 0x878 32 read-write 0 0xFFFFFFFF LTC0_PKA1_15 LTC PKHA A1 15 Register LTC0 0x87C 32 read-write 0 0xFFFFFFFF PKHA_A1 A1 VALUE 0 32 read-write LTC0_PKA_31 LTC PKHA A 31 Register LTC0 0x87C 32 read-write 0 0xFFFFFFFF LTC0_PKA2_0 LTC PKHA A2 0 Register LTC0 0x880 32 read-write 0 0xFFFFFFFF PKHA_A2 A2 VALUE 0 32 read-write LTC0_PKA_32 LTC PKHA A 32 Register LTC0 0x880 32 read-write 0 0xFFFFFFFF LTC0_PKA2_1 LTC PKHA A2 1 Register LTC0 0x884 32 read-write 0 0xFFFFFFFF PKHA_A2 A2 VALUE 0 32 read-write LTC0_PKA_33 LTC PKHA A 33 Register LTC0 0x884 32 read-write 0 0xFFFFFFFF LTC0_PKA2_2 LTC PKHA A2 2 Register LTC0 0x888 32 read-write 0 0xFFFFFFFF PKHA_A2 A2 VALUE 0 32 read-write LTC0_PKA_34 LTC PKHA A 34 Register LTC0 0x888 32 read-write 0 0xFFFFFFFF LTC0_PKA2_3 LTC PKHA A2 3 Register LTC0 0x88C 32 read-write 0 0xFFFFFFFF PKHA_A2 A2 VALUE 0 32 read-write LTC0_PKA_35 LTC PKHA A 35 Register LTC0 0x88C 32 read-write 0 0xFFFFFFFF LTC0_PKA2_4 LTC PKHA A2 4 Register LTC0 0x890 32 read-write 0 0xFFFFFFFF PKHA_A2 A2 VALUE 0 32 read-write LTC0_PKA_36 LTC PKHA A 36 Register LTC0 0x890 32 read-write 0 0xFFFFFFFF LTC0_PKA2_5 LTC PKHA A2 5 Register LTC0 0x894 32 read-write 0 0xFFFFFFFF PKHA_A2 A2 VALUE 0 32 read-write LTC0_PKA_37 LTC PKHA A 37 Register LTC0 0x894 32 read-write 0 0xFFFFFFFF LTC0_PKA2_6 LTC PKHA A2 6 Register LTC0 0x898 32 read-write 0 0xFFFFFFFF PKHA_A2 A2 VALUE 0 32 read-write LTC0_PKA_38 LTC PKHA A 38 Register LTC0 0x898 32 read-write 0 0xFFFFFFFF LTC0_PKA2_7 LTC PKHA A2 7 Register LTC0 0x89C 32 read-write 0 0xFFFFFFFF PKHA_A2 A2 VALUE 0 32 read-write LTC0_PKA_39 LTC PKHA A 39 Register LTC0 0x89C 32 read-write 0 0xFFFFFFFF LTC0_PKA2_8 LTC PKHA A2 8 Register LTC0 0x8A0 32 read-write 0 0xFFFFFFFF PKHA_A2 A2 VALUE 0 32 read-write LTC0_PKA_40 LTC PKHA A 40 Register LTC0 0x8A0 32 read-write 0 0xFFFFFFFF LTC0_PKA2_9 LTC PKHA A2 9 Register LTC0 0x8A4 32 read-write 0 0xFFFFFFFF PKHA_A2 A2 VALUE 0 32 read-write LTC0_PKA_41 LTC PKHA A 41 Register LTC0 0x8A4 32 read-write 0 0xFFFFFFFF LTC0_PKA2_10 LTC PKHA A2 10 Register LTC0 0x8A8 32 read-write 0 0xFFFFFFFF PKHA_A2 A2 VALUE 0 32 read-write LTC0_PKA_42 LTC PKHA A 42 Register LTC0 0x8A8 32 read-write 0 0xFFFFFFFF LTC0_PKA2_11 LTC PKHA A2 11 Register LTC0 0x8AC 32 read-write 0 0xFFFFFFFF PKHA_A2 A2 VALUE 0 32 read-write LTC0_PKA_43 LTC PKHA A 43 Register LTC0 0x8AC 32 read-write 0 0xFFFFFFFF LTC0_PKA2_12 LTC PKHA A2 12 Register LTC0 0x8B0 32 read-write 0 0xFFFFFFFF PKHA_A2 A2 VALUE 0 32 read-write LTC0_PKA_44 LTC PKHA A 44 Register LTC0 0x8B0 32 read-write 0 0xFFFFFFFF LTC0_PKA2_13 LTC PKHA A2 13 Register LTC0 0x8B4 32 read-write 0 0xFFFFFFFF PKHA_A2 A2 VALUE 0 32 read-write LTC0_PKA_45 LTC PKHA A 45 Register LTC0 0x8B4 32 read-write 0 0xFFFFFFFF LTC0_PKA2_14 LTC PKHA A2 14 Register LTC0 0x8B8 32 read-write 0 0xFFFFFFFF PKHA_A2 A2 VALUE 0 32 read-write LTC0_PKA_46 LTC PKHA A 46 Register LTC0 0x8B8 32 read-write 0 0xFFFFFFFF LTC0_PKA2_15 LTC PKHA A2 15 Register LTC0 0x8BC 32 read-write 0 0xFFFFFFFF PKHA_A2 A2 VALUE 0 32 read-write LTC0_PKA_47 LTC PKHA A 47 Register LTC0 0x8BC 32 read-write 0 0xFFFFFFFF LTC0_PKA3_0 LTC PKHA A3 0 Register LTC0 0x8C0 32 read-write 0 0xFFFFFFFF PKHA_A3 A3 VALUE 0 32 read-write LTC0_PKA_48 LTC PKHA A 48 Register LTC0 0x8C0 32 read-write 0 0xFFFFFFFF LTC0_PKA3_1 LTC PKHA A3 1 Register LTC0 0x8C4 32 read-write 0 0xFFFFFFFF PKHA_A3 A3 VALUE 0 32 read-write LTC0_PKA_49 LTC PKHA A 49 Register LTC0 0x8C4 32 read-write 0 0xFFFFFFFF LTC0_PKA3_2 LTC PKHA A3 2 Register LTC0 0x8C8 32 read-write 0 0xFFFFFFFF PKHA_A3 A3 VALUE 0 32 read-write LTC0_PKA_50 LTC PKHA A 50 Register LTC0 0x8C8 32 read-write 0 0xFFFFFFFF LTC0_PKA3_3 LTC PKHA A3 3 Register LTC0 0x8CC 32 read-write 0 0xFFFFFFFF PKHA_A3 A3 VALUE 0 32 read-write LTC0_PKA_51 LTC PKHA A 51 Register LTC0 0x8CC 32 read-write 0 0xFFFFFFFF LTC0_PKA3_4 LTC PKHA A3 4 Register LTC0 0x8D0 32 read-write 0 0xFFFFFFFF PKHA_A3 A3 VALUE 0 32 read-write LTC0_PKA_52 LTC PKHA A 52 Register LTC0 0x8D0 32 read-write 0 0xFFFFFFFF LTC0_PKA3_5 LTC PKHA A3 5 Register LTC0 0x8D4 32 read-write 0 0xFFFFFFFF PKHA_A3 A3 VALUE 0 32 read-write LTC0_PKA_53 LTC PKHA A 53 Register LTC0 0x8D4 32 read-write 0 0xFFFFFFFF LTC0_PKA3_6 LTC PKHA A3 6 Register LTC0 0x8D8 32 read-write 0 0xFFFFFFFF PKHA_A3 A3 VALUE 0 32 read-write LTC0_PKA_54 LTC PKHA A 54 Register LTC0 0x8D8 32 read-write 0 0xFFFFFFFF LTC0_PKA3_7 LTC PKHA A3 7 Register LTC0 0x8DC 32 read-write 0 0xFFFFFFFF PKHA_A3 A3 VALUE 0 32 read-write LTC0_PKA_55 LTC PKHA A 55 Register LTC0 0x8DC 32 read-write 0 0xFFFFFFFF LTC0_PKA3_8 LTC PKHA A3 8 Register LTC0 0x8E0 32 read-write 0 0xFFFFFFFF PKHA_A3 A3 VALUE 0 32 read-write LTC0_PKA_56 LTC PKHA A 56 Register LTC0 0x8E0 32 read-write 0 0xFFFFFFFF LTC0_PKA3_9 LTC PKHA A3 9 Register LTC0 0x8E4 32 read-write 0 0xFFFFFFFF PKHA_A3 A3 VALUE 0 32 read-write LTC0_PKA_57 LTC PKHA A 57 Register LTC0 0x8E4 32 read-write 0 0xFFFFFFFF LTC0_PKA3_10 LTC PKHA A3 10 Register LTC0 0x8E8 32 read-write 0 0xFFFFFFFF PKHA_A3 A3 VALUE 0 32 read-write LTC0_PKA_58 LTC PKHA A 58 Register LTC0 0x8E8 32 read-write 0 0xFFFFFFFF LTC0_PKA3_11 LTC PKHA A3 11 Register LTC0 0x8EC 32 read-write 0 0xFFFFFFFF PKHA_A3 A3 VALUE 0 32 read-write LTC0_PKA_59 LTC PKHA A 59 Register LTC0 0x8EC 32 read-write 0 0xFFFFFFFF LTC0_PKA3_12 LTC PKHA A3 12 Register LTC0 0x8F0 32 read-write 0 0xFFFFFFFF PKHA_A3 A3 VALUE 0 32 read-write LTC0_PKA_60 LTC PKHA A 60 Register LTC0 0x8F0 32 read-write 0 0xFFFFFFFF LTC0_PKA3_13 LTC PKHA A3 13 Register LTC0 0x8F4 32 read-write 0 0xFFFFFFFF PKHA_A3 A3 VALUE 0 32 read-write LTC0_PKA_61 LTC PKHA A 61 Register LTC0 0x8F4 32 read-write 0 0xFFFFFFFF LTC0_PKA3_14 LTC PKHA A3 14 Register LTC0 0x8F8 32 read-write 0 0xFFFFFFFF PKHA_A3 A3 VALUE 0 32 read-write LTC0_PKA_62 LTC PKHA A 62 Register LTC0 0x8F8 32 read-write 0 0xFFFFFFFF LTC0_PKA3_15 LTC PKHA A3 15 Register LTC0 0x8FC 32 read-write 0 0xFFFFFFFF PKHA_A3 A3 VALUE 0 32 read-write LTC0_PKA_63 LTC PKHA A 63 Register LTC0 0x8FC 32 read-write 0 0xFFFFFFFF LTC0_PKB0_0 LTC PKHA B0 0 Register LTC0 0xA00 32 read-write 0 0xFFFFFFFF PKHA_B0 B0 VALUE 0 32 read-write LTC0_PKB_0 LTC PKHA B 0 Register LTC0 0xA00 32 read-write 0 0xFFFFFFFF LTC0_PKB0_1 LTC PKHA B0 1 Register LTC0 0xA04 32 read-write 0 0xFFFFFFFF PKHA_B0 B0 VALUE 0 32 read-write LTC0_PKB_1 LTC PKHA B 1 Register LTC0 0xA04 32 read-write 0 0xFFFFFFFF LTC0_PKB0_2 LTC PKHA B0 2 Register LTC0 0xA08 32 read-write 0 0xFFFFFFFF PKHA_B0 B0 VALUE 0 32 read-write LTC0_PKB_2 LTC PKHA B 2 Register LTC0 0xA08 32 read-write 0 0xFFFFFFFF LTC0_PKB0_3 LTC PKHA B0 3 Register LTC0 0xA0C 32 read-write 0 0xFFFFFFFF PKHA_B0 B0 VALUE 0 32 read-write LTC0_PKB_3 LTC PKHA B 3 Register LTC0 0xA0C 32 read-write 0 0xFFFFFFFF LTC0_PKB0_4 LTC PKHA B0 4 Register LTC0 0xA10 32 read-write 0 0xFFFFFFFF PKHA_B0 B0 VALUE 0 32 read-write LTC0_PKB_4 LTC PKHA B 4 Register LTC0 0xA10 32 read-write 0 0xFFFFFFFF LTC0_PKB0_5 LTC PKHA B0 5 Register LTC0 0xA14 32 read-write 0 0xFFFFFFFF PKHA_B0 B0 VALUE 0 32 read-write LTC0_PKB_5 LTC PKHA B 5 Register LTC0 0xA14 32 read-write 0 0xFFFFFFFF LTC0_PKB0_6 LTC PKHA B0 6 Register LTC0 0xA18 32 read-write 0 0xFFFFFFFF PKHA_B0 B0 VALUE 0 32 read-write LTC0_PKB_6 LTC PKHA B 6 Register LTC0 0xA18 32 read-write 0 0xFFFFFFFF LTC0_PKB0_7 LTC PKHA B0 7 Register LTC0 0xA1C 32 read-write 0 0xFFFFFFFF PKHA_B0 B0 VALUE 0 32 read-write LTC0_PKB_7 LTC PKHA B 7 Register LTC0 0xA1C 32 read-write 0 0xFFFFFFFF LTC0_PKB0_8 LTC PKHA B0 8 Register LTC0 0xA20 32 read-write 0 0xFFFFFFFF PKHA_B0 B0 VALUE 0 32 read-write LTC0_PKB_8 LTC PKHA B 8 Register LTC0 0xA20 32 read-write 0 0xFFFFFFFF LTC0_PKB0_9 LTC PKHA B0 9 Register LTC0 0xA24 32 read-write 0 0xFFFFFFFF PKHA_B0 B0 VALUE 0 32 read-write LTC0_PKB_9 LTC PKHA B 9 Register LTC0 0xA24 32 read-write 0 0xFFFFFFFF LTC0_PKB0_10 LTC PKHA B0 10 Register LTC0 0xA28 32 read-write 0 0xFFFFFFFF PKHA_B0 B0 VALUE 0 32 read-write LTC0_PKB_10 LTC PKHA B 10 Register LTC0 0xA28 32 read-write 0 0xFFFFFFFF LTC0_PKB0_11 LTC PKHA B0 11 Register LTC0 0xA2C 32 read-write 0 0xFFFFFFFF PKHA_B0 B0 VALUE 0 32 read-write LTC0_PKB_11 LTC PKHA B 11 Register LTC0 0xA2C 32 read-write 0 0xFFFFFFFF LTC0_PKB0_12 LTC PKHA B0 12 Register LTC0 0xA30 32 read-write 0 0xFFFFFFFF PKHA_B0 B0 VALUE 0 32 read-write LTC0_PKB_12 LTC PKHA B 12 Register LTC0 0xA30 32 read-write 0 0xFFFFFFFF LTC0_PKB0_13 LTC PKHA B0 13 Register LTC0 0xA34 32 read-write 0 0xFFFFFFFF PKHA_B0 B0 VALUE 0 32 read-write LTC0_PKB_13 LTC PKHA B 13 Register LTC0 0xA34 32 read-write 0 0xFFFFFFFF LTC0_PKB0_14 LTC PKHA B0 14 Register LTC0 0xA38 32 read-write 0 0xFFFFFFFF PKHA_B0 B0 VALUE 0 32 read-write LTC0_PKB_14 LTC PKHA B 14 Register LTC0 0xA38 32 read-write 0 0xFFFFFFFF LTC0_PKB0_15 LTC PKHA B0 15 Register LTC0 0xA3C 32 read-write 0 0xFFFFFFFF PKHA_B0 B0 VALUE 0 32 read-write LTC0_PKB_15 LTC PKHA B 15 Register LTC0 0xA3C 32 read-write 0 0xFFFFFFFF LTC0_PKB1_0 LTC PKHA B1 0 Register LTC0 0xA40 32 read-write 0 0xFFFFFFFF PKHA_B1 B1 VALUE 0 32 read-write LTC0_PKB_16 LTC PKHA B 16 Register LTC0 0xA40 32 read-write 0 0xFFFFFFFF LTC0_PKB1_1 LTC PKHA B1 1 Register LTC0 0xA44 32 read-write 0 0xFFFFFFFF PKHA_B1 B1 VALUE 0 32 read-write LTC0_PKB_17 LTC PKHA B 17 Register LTC0 0xA44 32 read-write 0 0xFFFFFFFF LTC0_PKB1_2 LTC PKHA B1 2 Register LTC0 0xA48 32 read-write 0 0xFFFFFFFF PKHA_B1 B1 VALUE 0 32 read-write LTC0_PKB_18 LTC PKHA B 18 Register LTC0 0xA48 32 read-write 0 0xFFFFFFFF LTC0_PKB1_3 LTC PKHA B1 3 Register LTC0 0xA4C 32 read-write 0 0xFFFFFFFF PKHA_B1 B1 VALUE 0 32 read-write LTC0_PKB_19 LTC PKHA B 19 Register LTC0 0xA4C 32 read-write 0 0xFFFFFFFF LTC0_PKB1_4 LTC PKHA B1 4 Register LTC0 0xA50 32 read-write 0 0xFFFFFFFF PKHA_B1 B1 VALUE 0 32 read-write LTC0_PKB_20 LTC PKHA B 20 Register LTC0 0xA50 32 read-write 0 0xFFFFFFFF LTC0_PKB1_5 LTC PKHA B1 5 Register LTC0 0xA54 32 read-write 0 0xFFFFFFFF PKHA_B1 B1 VALUE 0 32 read-write LTC0_PKB_21 LTC PKHA B 21 Register LTC0 0xA54 32 read-write 0 0xFFFFFFFF LTC0_PKB1_6 LTC PKHA B1 6 Register LTC0 0xA58 32 read-write 0 0xFFFFFFFF PKHA_B1 B1 VALUE 0 32 read-write LTC0_PKB_22 LTC PKHA B 22 Register LTC0 0xA58 32 read-write 0 0xFFFFFFFF LTC0_PKB1_7 LTC PKHA B1 7 Register LTC0 0xA5C 32 read-write 0 0xFFFFFFFF PKHA_B1 B1 VALUE 0 32 read-write LTC0_PKB_23 LTC PKHA B 23 Register LTC0 0xA5C 32 read-write 0 0xFFFFFFFF LTC0_PKB1_8 LTC PKHA B1 8 Register LTC0 0xA60 32 read-write 0 0xFFFFFFFF PKHA_B1 B1 VALUE 0 32 read-write LTC0_PKB_24 LTC PKHA B 24 Register LTC0 0xA60 32 read-write 0 0xFFFFFFFF LTC0_PKB1_9 LTC PKHA B1 9 Register LTC0 0xA64 32 read-write 0 0xFFFFFFFF PKHA_B1 B1 VALUE 0 32 read-write LTC0_PKB_25 LTC PKHA B 25 Register LTC0 0xA64 32 read-write 0 0xFFFFFFFF LTC0_PKB1_10 LTC PKHA B1 10 Register LTC0 0xA68 32 read-write 0 0xFFFFFFFF PKHA_B1 B1 VALUE 0 32 read-write LTC0_PKB_26 LTC PKHA B 26 Register LTC0 0xA68 32 read-write 0 0xFFFFFFFF LTC0_PKB1_11 LTC PKHA B1 11 Register LTC0 0xA6C 32 read-write 0 0xFFFFFFFF PKHA_B1 B1 VALUE 0 32 read-write LTC0_PKB_27 LTC PKHA B 27 Register LTC0 0xA6C 32 read-write 0 0xFFFFFFFF LTC0_PKB1_12 LTC PKHA B1 12 Register LTC0 0xA70 32 read-write 0 0xFFFFFFFF PKHA_B1 B1 VALUE 0 32 read-write LTC0_PKB_28 LTC PKHA B 28 Register LTC0 0xA70 32 read-write 0 0xFFFFFFFF LTC0_PKB1_13 LTC PKHA B1 13 Register LTC0 0xA74 32 read-write 0 0xFFFFFFFF PKHA_B1 B1 VALUE 0 32 read-write LTC0_PKB_29 LTC PKHA B 29 Register LTC0 0xA74 32 read-write 0 0xFFFFFFFF LTC0_PKB1_14 LTC PKHA B1 14 Register LTC0 0xA78 32 read-write 0 0xFFFFFFFF PKHA_B1 B1 VALUE 0 32 read-write LTC0_PKB_30 LTC PKHA B 30 Register LTC0 0xA78 32 read-write 0 0xFFFFFFFF LTC0_PKB1_15 LTC PKHA B1 15 Register LTC0 0xA7C 32 read-write 0 0xFFFFFFFF PKHA_B1 B1 VALUE 0 32 read-write LTC0_PKB_31 LTC PKHA B 31 Register LTC0 0xA7C 32 read-write 0 0xFFFFFFFF LTC0_PKB2_0 LTC PKHA B2 0 Register LTC0 0xA80 32 read-write 0 0xFFFFFFFF PKHA_B2 B2 VALUE 0 32 read-write LTC0_PKB_32 LTC PKHA B 32 Register LTC0 0xA80 32 read-write 0 0xFFFFFFFF LTC0_PKB2_1 LTC PKHA B2 1 Register LTC0 0xA84 32 read-write 0 0xFFFFFFFF PKHA_B2 B2 VALUE 0 32 read-write LTC0_PKB_33 LTC PKHA B 33 Register LTC0 0xA84 32 read-write 0 0xFFFFFFFF LTC0_PKB2_2 LTC PKHA B2 2 Register LTC0 0xA88 32 read-write 0 0xFFFFFFFF PKHA_B2 B2 VALUE 0 32 read-write LTC0_PKB_34 LTC PKHA B 34 Register LTC0 0xA88 32 read-write 0 0xFFFFFFFF LTC0_PKB2_3 LTC PKHA B2 3 Register LTC0 0xA8C 32 read-write 0 0xFFFFFFFF PKHA_B2 B2 VALUE 0 32 read-write LTC0_PKB_35 LTC PKHA B 35 Register LTC0 0xA8C 32 read-write 0 0xFFFFFFFF LTC0_PKB2_4 LTC PKHA B2 4 Register LTC0 0xA90 32 read-write 0 0xFFFFFFFF PKHA_B2 B2 VALUE 0 32 read-write LTC0_PKB_36 LTC PKHA B 36 Register LTC0 0xA90 32 read-write 0 0xFFFFFFFF LTC0_PKB2_5 LTC PKHA B2 5 Register LTC0 0xA94 32 read-write 0 0xFFFFFFFF PKHA_B2 B2 VALUE 0 32 read-write LTC0_PKB_37 LTC PKHA B 37 Register LTC0 0xA94 32 read-write 0 0xFFFFFFFF LTC0_PKB2_6 LTC PKHA B2 6 Register LTC0 0xA98 32 read-write 0 0xFFFFFFFF PKHA_B2 B2 VALUE 0 32 read-write LTC0_PKB_38 LTC PKHA B 38 Register LTC0 0xA98 32 read-write 0 0xFFFFFFFF LTC0_PKB2_7 LTC PKHA B2 7 Register LTC0 0xA9C 32 read-write 0 0xFFFFFFFF PKHA_B2 B2 VALUE 0 32 read-write LTC0_PKB_39 LTC PKHA B 39 Register LTC0 0xA9C 32 read-write 0 0xFFFFFFFF LTC0_PKB2_8 LTC PKHA B2 8 Register LTC0 0xAA0 32 read-write 0 0xFFFFFFFF PKHA_B2 B2 VALUE 0 32 read-write LTC0_PKB_40 LTC PKHA B 40 Register LTC0 0xAA0 32 read-write 0 0xFFFFFFFF LTC0_PKB2_9 LTC PKHA B2 9 Register LTC0 0xAA4 32 read-write 0 0xFFFFFFFF PKHA_B2 B2 VALUE 0 32 read-write LTC0_PKB_41 LTC PKHA B 41 Register LTC0 0xAA4 32 read-write 0 0xFFFFFFFF LTC0_PKB2_10 LTC PKHA B2 10 Register LTC0 0xAA8 32 read-write 0 0xFFFFFFFF PKHA_B2 B2 VALUE 0 32 read-write LTC0_PKB_42 LTC PKHA B 42 Register LTC0 0xAA8 32 read-write 0 0xFFFFFFFF LTC0_PKB2_11 LTC PKHA B2 11 Register LTC0 0xAAC 32 read-write 0 0xFFFFFFFF PKHA_B2 B2 VALUE 0 32 read-write LTC0_PKB_43 LTC PKHA B 43 Register LTC0 0xAAC 32 read-write 0 0xFFFFFFFF LTC0_PKB2_12 LTC PKHA B2 12 Register LTC0 0xAB0 32 read-write 0 0xFFFFFFFF PKHA_B2 B2 VALUE 0 32 read-write LTC0_PKB_44 LTC PKHA B 44 Register LTC0 0xAB0 32 read-write 0 0xFFFFFFFF LTC0_PKB2_13 LTC PKHA B2 13 Register LTC0 0xAB4 32 read-write 0 0xFFFFFFFF PKHA_B2 B2 VALUE 0 32 read-write LTC0_PKB_45 LTC PKHA B 45 Register LTC0 0xAB4 32 read-write 0 0xFFFFFFFF LTC0_PKB2_14 LTC PKHA B2 14 Register LTC0 0xAB8 32 read-write 0 0xFFFFFFFF PKHA_B2 B2 VALUE 0 32 read-write LTC0_PKB_46 LTC PKHA B 46 Register LTC0 0xAB8 32 read-write 0 0xFFFFFFFF LTC0_PKB2_15 LTC PKHA B2 15 Register LTC0 0xABC 32 read-write 0 0xFFFFFFFF PKHA_B2 B2 VALUE 0 32 read-write LTC0_PKB_47 LTC PKHA B 47 Register LTC0 0xABC 32 read-write 0 0xFFFFFFFF LTC0_PKB3_0 LTC PKHA B3 0 Register LTC0 0xAC0 32 read-write 0 0xFFFFFFFF PKHA_B3 B3 VALUE 0 32 read-write LTC0_PKB_48 LTC PKHA B 48 Register LTC0 0xAC0 32 read-write 0 0xFFFFFFFF LTC0_PKB3_1 LTC PKHA B3 1 Register LTC0 0xAC4 32 read-write 0 0xFFFFFFFF PKHA_B3 B3 VALUE 0 32 read-write LTC0_PKB_49 LTC PKHA B 49 Register LTC0 0xAC4 32 read-write 0 0xFFFFFFFF LTC0_PKB3_2 LTC PKHA B3 2 Register LTC0 0xAC8 32 read-write 0 0xFFFFFFFF PKHA_B3 B3 VALUE 0 32 read-write LTC0_PKB_50 LTC PKHA B 50 Register LTC0 0xAC8 32 read-write 0 0xFFFFFFFF LTC0_PKB3_3 LTC PKHA B3 3 Register LTC0 0xACC 32 read-write 0 0xFFFFFFFF PKHA_B3 B3 VALUE 0 32 read-write LTC0_PKB_51 LTC PKHA B 51 Register LTC0 0xACC 32 read-write 0 0xFFFFFFFF LTC0_PKB3_4 LTC PKHA B3 4 Register LTC0 0xAD0 32 read-write 0 0xFFFFFFFF PKHA_B3 B3 VALUE 0 32 read-write LTC0_PKB_52 LTC PKHA B 52 Register LTC0 0xAD0 32 read-write 0 0xFFFFFFFF LTC0_PKB3_5 LTC PKHA B3 5 Register LTC0 0xAD4 32 read-write 0 0xFFFFFFFF PKHA_B3 B3 VALUE 0 32 read-write LTC0_PKB_53 LTC PKHA B 53 Register LTC0 0xAD4 32 read-write 0 0xFFFFFFFF LTC0_PKB3_6 LTC PKHA B3 6 Register LTC0 0xAD8 32 read-write 0 0xFFFFFFFF PKHA_B3 B3 VALUE 0 32 read-write LTC0_PKB_54 LTC PKHA B 54 Register LTC0 0xAD8 32 read-write 0 0xFFFFFFFF LTC0_PKB3_7 LTC PKHA B3 7 Register LTC0 0xADC 32 read-write 0 0xFFFFFFFF PKHA_B3 B3 VALUE 0 32 read-write LTC0_PKB_55 LTC PKHA B 55 Register LTC0 0xADC 32 read-write 0 0xFFFFFFFF LTC0_PKB3_8 LTC PKHA B3 8 Register LTC0 0xAE0 32 read-write 0 0xFFFFFFFF PKHA_B3 B3 VALUE 0 32 read-write LTC0_PKB_56 LTC PKHA B 56 Register LTC0 0xAE0 32 read-write 0 0xFFFFFFFF LTC0_PKB3_9 LTC PKHA B3 9 Register LTC0 0xAE4 32 read-write 0 0xFFFFFFFF PKHA_B3 B3 VALUE 0 32 read-write LTC0_PKB_57 LTC PKHA B 57 Register LTC0 0xAE4 32 read-write 0 0xFFFFFFFF LTC0_PKB3_10 LTC PKHA B3 10 Register LTC0 0xAE8 32 read-write 0 0xFFFFFFFF PKHA_B3 B3 VALUE 0 32 read-write LTC0_PKB_58 LTC PKHA B 58 Register LTC0 0xAE8 32 read-write 0 0xFFFFFFFF LTC0_PKB3_11 LTC PKHA B3 11 Register LTC0 0xAEC 32 read-write 0 0xFFFFFFFF PKHA_B3 B3 VALUE 0 32 read-write LTC0_PKB_59 LTC PKHA B 59 Register LTC0 0xAEC 32 read-write 0 0xFFFFFFFF LTC0_PKB3_12 LTC PKHA B3 12 Register LTC0 0xAF0 32 read-write 0 0xFFFFFFFF PKHA_B3 B3 VALUE 0 32 read-write LTC0_PKB_60 LTC PKHA B 60 Register LTC0 0xAF0 32 read-write 0 0xFFFFFFFF LTC0_PKB3_13 LTC PKHA B3 13 Register LTC0 0xAF4 32 read-write 0 0xFFFFFFFF PKHA_B3 B3 VALUE 0 32 read-write LTC0_PKB_61 LTC PKHA B 61 Register LTC0 0xAF4 32 read-write 0 0xFFFFFFFF LTC0_PKB3_14 LTC PKHA B3 14 Register LTC0 0xAF8 32 read-write 0 0xFFFFFFFF PKHA_B3 B3 VALUE 0 32 read-write LTC0_PKB_62 LTC PKHA B 62 Register LTC0 0xAF8 32 read-write 0 0xFFFFFFFF LTC0_PKB3_15 LTC PKHA B3 15 Register LTC0 0xAFC 32 read-write 0 0xFFFFFFFF PKHA_B3 B3 VALUE 0 32 read-write LTC0_PKB_63 LTC PKHA B 63 Register LTC0 0xAFC 32 read-write 0 0xFFFFFFFF LTC0_PKN0_0 LTC PKHA N0 0 Register LTC0 0xC00 32 read-write 0 0xFFFFFFFF PKHA_N0 N0 VALUE 0 32 read-write LTC0_PKN_0 LTC PKHA N 0 Register LTC0 0xC00 32 read-write 0 0xFFFFFFFF LTC0_PKN0_1 LTC PKHA N0 1 Register LTC0 0xC04 32 read-write 0 0xFFFFFFFF PKHA_N0 N0 VALUE 0 32 read-write LTC0_PKN_1 LTC PKHA N 1 Register LTC0 0xC04 32 read-write 0 0xFFFFFFFF LTC0_PKN0_2 LTC PKHA N0 2 Register LTC0 0xC08 32 read-write 0 0xFFFFFFFF PKHA_N0 N0 VALUE 0 32 read-write LTC0_PKN_2 LTC PKHA N 2 Register LTC0 0xC08 32 read-write 0 0xFFFFFFFF LTC0_PKN0_3 LTC PKHA N0 3 Register LTC0 0xC0C 32 read-write 0 0xFFFFFFFF PKHA_N0 N0 VALUE 0 32 read-write LTC0_PKN_3 LTC PKHA N 3 Register LTC0 0xC0C 32 read-write 0 0xFFFFFFFF LTC0_PKN0_4 LTC PKHA N0 4 Register LTC0 0xC10 32 read-write 0 0xFFFFFFFF PKHA_N0 N0 VALUE 0 32 read-write LTC0_PKN_4 LTC PKHA N 4 Register LTC0 0xC10 32 read-write 0 0xFFFFFFFF LTC0_PKN0_5 LTC PKHA N0 5 Register LTC0 0xC14 32 read-write 0 0xFFFFFFFF PKHA_N0 N0 VALUE 0 32 read-write LTC0_PKN_5 LTC PKHA N 5 Register LTC0 0xC14 32 read-write 0 0xFFFFFFFF LTC0_PKN0_6 LTC PKHA N0 6 Register LTC0 0xC18 32 read-write 0 0xFFFFFFFF PKHA_N0 N0 VALUE 0 32 read-write LTC0_PKN_6 LTC PKHA N 6 Register LTC0 0xC18 32 read-write 0 0xFFFFFFFF LTC0_PKN0_7 LTC PKHA N0 7 Register LTC0 0xC1C 32 read-write 0 0xFFFFFFFF PKHA_N0 N0 VALUE 0 32 read-write LTC0_PKN_7 LTC PKHA N 7 Register LTC0 0xC1C 32 read-write 0 0xFFFFFFFF LTC0_PKN0_8 LTC PKHA N0 8 Register LTC0 0xC20 32 read-write 0 0xFFFFFFFF PKHA_N0 N0 VALUE 0 32 read-write LTC0_PKN_8 LTC PKHA N 8 Register LTC0 0xC20 32 read-write 0 0xFFFFFFFF LTC0_PKN0_9 LTC PKHA N0 9 Register LTC0 0xC24 32 read-write 0 0xFFFFFFFF PKHA_N0 N0 VALUE 0 32 read-write LTC0_PKN_9 LTC PKHA N 9 Register LTC0 0xC24 32 read-write 0 0xFFFFFFFF LTC0_PKN0_10 LTC PKHA N0 10 Register LTC0 0xC28 32 read-write 0 0xFFFFFFFF PKHA_N0 N0 VALUE 0 32 read-write LTC0_PKN_10 LTC PKHA N 10 Register LTC0 0xC28 32 read-write 0 0xFFFFFFFF LTC0_PKN0_11 LTC PKHA N0 11 Register LTC0 0xC2C 32 read-write 0 0xFFFFFFFF PKHA_N0 N0 VALUE 0 32 read-write LTC0_PKN_11 LTC PKHA N 11 Register LTC0 0xC2C 32 read-write 0 0xFFFFFFFF LTC0_PKN0_12 LTC PKHA N0 12 Register LTC0 0xC30 32 read-write 0 0xFFFFFFFF PKHA_N0 N0 VALUE 0 32 read-write LTC0_PKN_12 LTC PKHA N 12 Register LTC0 0xC30 32 read-write 0 0xFFFFFFFF LTC0_PKN0_13 LTC PKHA N0 13 Register LTC0 0xC34 32 read-write 0 0xFFFFFFFF PKHA_N0 N0 VALUE 0 32 read-write LTC0_PKN_13 LTC PKHA N 13 Register LTC0 0xC34 32 read-write 0 0xFFFFFFFF LTC0_PKN0_14 LTC PKHA N0 14 Register LTC0 0xC38 32 read-write 0 0xFFFFFFFF PKHA_N0 N0 VALUE 0 32 read-write LTC0_PKN_14 LTC PKHA N 14 Register LTC0 0xC38 32 read-write 0 0xFFFFFFFF LTC0_PKN0_15 LTC PKHA N0 15 Register LTC0 0xC3C 32 read-write 0 0xFFFFFFFF PKHA_N0 N0 VALUE 0 32 read-write LTC0_PKN_15 LTC PKHA N 15 Register LTC0 0xC3C 32 read-write 0 0xFFFFFFFF LTC0_PKN1_0 LTC PKHA N1 0 Register LTC0 0xC40 32 read-write 0 0xFFFFFFFF PKHA_N1 N1 VALUE 0 32 read-write LTC0_PKN_16 LTC PKHA N 16 Register LTC0 0xC40 32 read-write 0 0xFFFFFFFF LTC0_PKN1_1 LTC PKHA N1 1 Register LTC0 0xC44 32 read-write 0 0xFFFFFFFF PKHA_N1 N1 VALUE 0 32 read-write LTC0_PKN_17 LTC PKHA N 17 Register LTC0 0xC44 32 read-write 0 0xFFFFFFFF LTC0_PKN1_2 LTC PKHA N1 2 Register LTC0 0xC48 32 read-write 0 0xFFFFFFFF PKHA_N1 N1 VALUE 0 32 read-write LTC0_PKN_18 LTC PKHA N 18 Register LTC0 0xC48 32 read-write 0 0xFFFFFFFF LTC0_PKN1_3 LTC PKHA N1 3 Register LTC0 0xC4C 32 read-write 0 0xFFFFFFFF PKHA_N1 N1 VALUE 0 32 read-write LTC0_PKN_19 LTC PKHA N 19 Register LTC0 0xC4C 32 read-write 0 0xFFFFFFFF LTC0_PKN1_4 LTC PKHA N1 4 Register LTC0 0xC50 32 read-write 0 0xFFFFFFFF PKHA_N1 N1 VALUE 0 32 read-write LTC0_PKN_20 LTC PKHA N 20 Register LTC0 0xC50 32 read-write 0 0xFFFFFFFF LTC0_PKN1_5 LTC PKHA N1 5 Register LTC0 0xC54 32 read-write 0 0xFFFFFFFF PKHA_N1 N1 VALUE 0 32 read-write LTC0_PKN_21 LTC PKHA N 21 Register LTC0 0xC54 32 read-write 0 0xFFFFFFFF LTC0_PKN1_6 LTC PKHA N1 6 Register LTC0 0xC58 32 read-write 0 0xFFFFFFFF PKHA_N1 N1 VALUE 0 32 read-write LTC0_PKN_22 LTC PKHA N 22 Register LTC0 0xC58 32 read-write 0 0xFFFFFFFF LTC0_PKN1_7 LTC PKHA N1 7 Register LTC0 0xC5C 32 read-write 0 0xFFFFFFFF PKHA_N1 N1 VALUE 0 32 read-write LTC0_PKN_23 LTC PKHA N 23 Register LTC0 0xC5C 32 read-write 0 0xFFFFFFFF LTC0_PKN1_8 LTC PKHA N1 8 Register LTC0 0xC60 32 read-write 0 0xFFFFFFFF PKHA_N1 N1 VALUE 0 32 read-write LTC0_PKN_24 LTC PKHA N 24 Register LTC0 0xC60 32 read-write 0 0xFFFFFFFF LTC0_PKN1_9 LTC PKHA N1 9 Register LTC0 0xC64 32 read-write 0 0xFFFFFFFF PKHA_N1 N1 VALUE 0 32 read-write LTC0_PKN_25 LTC PKHA N 25 Register LTC0 0xC64 32 read-write 0 0xFFFFFFFF LTC0_PKN1_10 LTC PKHA N1 10 Register LTC0 0xC68 32 read-write 0 0xFFFFFFFF PKHA_N1 N1 VALUE 0 32 read-write LTC0_PKN_26 LTC PKHA N 26 Register LTC0 0xC68 32 read-write 0 0xFFFFFFFF LTC0_PKN1_11 LTC PKHA N1 11 Register LTC0 0xC6C 32 read-write 0 0xFFFFFFFF PKHA_N1 N1 VALUE 0 32 read-write LTC0_PKN_27 LTC PKHA N 27 Register LTC0 0xC6C 32 read-write 0 0xFFFFFFFF LTC0_PKN1_12 LTC PKHA N1 12 Register LTC0 0xC70 32 read-write 0 0xFFFFFFFF PKHA_N1 N1 VALUE 0 32 read-write LTC0_PKN_28 LTC PKHA N 28 Register LTC0 0xC70 32 read-write 0 0xFFFFFFFF LTC0_PKN1_13 LTC PKHA N1 13 Register LTC0 0xC74 32 read-write 0 0xFFFFFFFF PKHA_N1 N1 VALUE 0 32 read-write LTC0_PKN_29 LTC PKHA N 29 Register LTC0 0xC74 32 read-write 0 0xFFFFFFFF LTC0_PKN1_14 LTC PKHA N1 14 Register LTC0 0xC78 32 read-write 0 0xFFFFFFFF PKHA_N1 N1 VALUE 0 32 read-write LTC0_PKN_30 LTC PKHA N 30 Register LTC0 0xC78 32 read-write 0 0xFFFFFFFF LTC0_PKN1_15 LTC PKHA N1 15 Register LTC0 0xC7C 32 read-write 0 0xFFFFFFFF PKHA_N1 N1 VALUE 0 32 read-write LTC0_PKN_31 LTC PKHA N 31 Register LTC0 0xC7C 32 read-write 0 0xFFFFFFFF LTC0_PKN2_0 LTC PKHA N2 0 Register LTC0 0xC80 32 read-write 0 0xFFFFFFFF PKHA_N2 N2 VALUE 0 32 read-write LTC0_PKN_32 LTC PKHA N 32 Register LTC0 0xC80 32 read-write 0 0xFFFFFFFF LTC0_PKN2_1 LTC PKHA N2 1 Register LTC0 0xC84 32 read-write 0 0xFFFFFFFF PKHA_N2 N2 VALUE 0 32 read-write LTC0_PKN_33 LTC PKHA N 33 Register LTC0 0xC84 32 read-write 0 0xFFFFFFFF LTC0_PKN2_2 LTC PKHA N2 2 Register LTC0 0xC88 32 read-write 0 0xFFFFFFFF PKHA_N2 N2 VALUE 0 32 read-write LTC0_PKN_34 LTC PKHA N 34 Register LTC0 0xC88 32 read-write 0 0xFFFFFFFF LTC0_PKN2_3 LTC PKHA N2 3 Register LTC0 0xC8C 32 read-write 0 0xFFFFFFFF PKHA_N2 N2 VALUE 0 32 read-write LTC0_PKN_35 LTC PKHA N 35 Register LTC0 0xC8C 32 read-write 0 0xFFFFFFFF LTC0_PKN2_4 LTC PKHA N2 4 Register LTC0 0xC90 32 read-write 0 0xFFFFFFFF PKHA_N2 N2 VALUE 0 32 read-write LTC0_PKN_36 LTC PKHA N 36 Register LTC0 0xC90 32 read-write 0 0xFFFFFFFF LTC0_PKN2_5 LTC PKHA N2 5 Register LTC0 0xC94 32 read-write 0 0xFFFFFFFF PKHA_N2 N2 VALUE 0 32 read-write LTC0_PKN_37 LTC PKHA N 37 Register LTC0 0xC94 32 read-write 0 0xFFFFFFFF LTC0_PKN2_6 LTC PKHA N2 6 Register LTC0 0xC98 32 read-write 0 0xFFFFFFFF PKHA_N2 N2 VALUE 0 32 read-write LTC0_PKN_38 LTC PKHA N 38 Register LTC0 0xC98 32 read-write 0 0xFFFFFFFF LTC0_PKN2_7 LTC PKHA N2 7 Register LTC0 0xC9C 32 read-write 0 0xFFFFFFFF PKHA_N2 N2 VALUE 0 32 read-write LTC0_PKN_39 LTC PKHA N 39 Register LTC0 0xC9C 32 read-write 0 0xFFFFFFFF LTC0_PKN2_8 LTC PKHA N2 8 Register LTC0 0xCA0 32 read-write 0 0xFFFFFFFF PKHA_N2 N2 VALUE 0 32 read-write LTC0_PKN_40 LTC PKHA N 40 Register LTC0 0xCA0 32 read-write 0 0xFFFFFFFF LTC0_PKN2_9 LTC PKHA N2 9 Register LTC0 0xCA4 32 read-write 0 0xFFFFFFFF PKHA_N2 N2 VALUE 0 32 read-write LTC0_PKN_41 LTC PKHA N 41 Register LTC0 0xCA4 32 read-write 0 0xFFFFFFFF LTC0_PKN2_10 LTC PKHA N2 10 Register LTC0 0xCA8 32 read-write 0 0xFFFFFFFF PKHA_N2 N2 VALUE 0 32 read-write LTC0_PKN_42 LTC PKHA N 42 Register LTC0 0xCA8 32 read-write 0 0xFFFFFFFF LTC0_PKN2_11 LTC PKHA N2 11 Register LTC0 0xCAC 32 read-write 0 0xFFFFFFFF PKHA_N2 N2 VALUE 0 32 read-write LTC0_PKN_43 LTC PKHA N 43 Register LTC0 0xCAC 32 read-write 0 0xFFFFFFFF LTC0_PKN2_12 LTC PKHA N2 12 Register LTC0 0xCB0 32 read-write 0 0xFFFFFFFF PKHA_N2 N2 VALUE 0 32 read-write LTC0_PKN_44 LTC PKHA N 44 Register LTC0 0xCB0 32 read-write 0 0xFFFFFFFF LTC0_PKN2_13 LTC PKHA N2 13 Register LTC0 0xCB4 32 read-write 0 0xFFFFFFFF PKHA_N2 N2 VALUE 0 32 read-write LTC0_PKN_45 LTC PKHA N 45 Register LTC0 0xCB4 32 read-write 0 0xFFFFFFFF LTC0_PKN2_14 LTC PKHA N2 14 Register LTC0 0xCB8 32 read-write 0 0xFFFFFFFF PKHA_N2 N2 VALUE 0 32 read-write LTC0_PKN_46 LTC PKHA N 46 Register LTC0 0xCB8 32 read-write 0 0xFFFFFFFF LTC0_PKN2_15 LTC PKHA N2 15 Register LTC0 0xCBC 32 read-write 0 0xFFFFFFFF PKHA_N2 N2 VALUE 0 32 read-write LTC0_PKN_47 LTC PKHA N 47 Register LTC0 0xCBC 32 read-write 0 0xFFFFFFFF LTC0_PKN3_0 LTC PKHA N3 0 Register LTC0 0xCC0 32 read-write 0 0xFFFFFFFF PKHA_N3 N3 VALUE 0 32 read-write LTC0_PKN_48 LTC PKHA N 48 Register LTC0 0xCC0 32 read-write 0 0xFFFFFFFF LTC0_PKN3_1 LTC PKHA N3 1 Register LTC0 0xCC4 32 read-write 0 0xFFFFFFFF PKHA_N3 N3 VALUE 0 32 read-write LTC0_PKN_49 LTC PKHA N 49 Register LTC0 0xCC4 32 read-write 0 0xFFFFFFFF LTC0_PKN3_2 LTC PKHA N3 2 Register LTC0 0xCC8 32 read-write 0 0xFFFFFFFF PKHA_N3 N3 VALUE 0 32 read-write LTC0_PKN_50 LTC PKHA N 50 Register LTC0 0xCC8 32 read-write 0 0xFFFFFFFF LTC0_PKN3_3 LTC PKHA N3 3 Register LTC0 0xCCC 32 read-write 0 0xFFFFFFFF PKHA_N3 N3 VALUE 0 32 read-write LTC0_PKN_51 LTC PKHA N 51 Register LTC0 0xCCC 32 read-write 0 0xFFFFFFFF LTC0_PKN3_4 LTC PKHA N3 4 Register LTC0 0xCD0 32 read-write 0 0xFFFFFFFF PKHA_N3 N3 VALUE 0 32 read-write LTC0_PKN_52 LTC PKHA N 52 Register LTC0 0xCD0 32 read-write 0 0xFFFFFFFF LTC0_PKN3_5 LTC PKHA N3 5 Register LTC0 0xCD4 32 read-write 0 0xFFFFFFFF PKHA_N3 N3 VALUE 0 32 read-write LTC0_PKN_53 LTC PKHA N 53 Register LTC0 0xCD4 32 read-write 0 0xFFFFFFFF LTC0_PKN3_6 LTC PKHA N3 6 Register LTC0 0xCD8 32 read-write 0 0xFFFFFFFF PKHA_N3 N3 VALUE 0 32 read-write LTC0_PKN_54 LTC PKHA N 54 Register LTC0 0xCD8 32 read-write 0 0xFFFFFFFF LTC0_PKN3_7 LTC PKHA N3 7 Register LTC0 0xCDC 32 read-write 0 0xFFFFFFFF PKHA_N3 N3 VALUE 0 32 read-write LTC0_PKN_55 LTC PKHA N 55 Register LTC0 0xCDC 32 read-write 0 0xFFFFFFFF LTC0_PKN3_8 LTC PKHA N3 8 Register LTC0 0xCE0 32 read-write 0 0xFFFFFFFF PKHA_N3 N3 VALUE 0 32 read-write LTC0_PKN_56 LTC PKHA N 56 Register LTC0 0xCE0 32 read-write 0 0xFFFFFFFF LTC0_PKN3_9 LTC PKHA N3 9 Register LTC0 0xCE4 32 read-write 0 0xFFFFFFFF PKHA_N3 N3 VALUE 0 32 read-write LTC0_PKN_57 LTC PKHA N 57 Register LTC0 0xCE4 32 read-write 0 0xFFFFFFFF LTC0_PKN3_10 LTC PKHA N3 10 Register LTC0 0xCE8 32 read-write 0 0xFFFFFFFF PKHA_N3 N3 VALUE 0 32 read-write LTC0_PKN_58 LTC PKHA N 58 Register LTC0 0xCE8 32 read-write 0 0xFFFFFFFF LTC0_PKN3_11 LTC PKHA N3 11 Register LTC0 0xCEC 32 read-write 0 0xFFFFFFFF PKHA_N3 N3 VALUE 0 32 read-write LTC0_PKN_59 LTC PKHA N 59 Register LTC0 0xCEC 32 read-write 0 0xFFFFFFFF LTC0_PKN3_12 LTC PKHA N3 12 Register LTC0 0xCF0 32 read-write 0 0xFFFFFFFF PKHA_N3 N3 VALUE 0 32 read-write LTC0_PKN_60 LTC PKHA N 60 Register LTC0 0xCF0 32 read-write 0 0xFFFFFFFF LTC0_PKN3_13 LTC PKHA N3 13 Register LTC0 0xCF4 32 read-write 0 0xFFFFFFFF PKHA_N3 N3 VALUE 0 32 read-write LTC0_PKN_61 LTC PKHA N 61 Register LTC0 0xCF4 32 read-write 0 0xFFFFFFFF LTC0_PKN3_14 LTC PKHA N3 14 Register LTC0 0xCF8 32 read-write 0 0xFFFFFFFF PKHA_N3 N3 VALUE 0 32 read-write LTC0_PKN_62 LTC PKHA N 62 Register LTC0 0xCF8 32 read-write 0 0xFFFFFFFF LTC0_PKN3_15 LTC PKHA N3 15 Register LTC0 0xCFC 32 read-write 0 0xFFFFFFFF PKHA_N3 N3 VALUE 0 32 read-write LTC0_PKN_63 LTC PKHA N 63 Register LTC0 0xCFC 32 read-write 0 0xFFFFFFFF LTC0_PKE0_0 LTC PKHA E0 0 Register LTC0 0xE00 32 read-write 0 0xFFFFFFFF PKHA_E0 E0 VALUE 0 32 read-write LTC0_PKE_0 LTC PKHA E 0 Register LTC0 0xE00 32 read-write 0 0xFFFFFFFF LTC0_PKE0_1 LTC PKHA E0 1 Register LTC0 0xE04 32 read-write 0 0xFFFFFFFF PKHA_E0 E0 VALUE 0 32 read-write LTC0_PKE_1 LTC PKHA E 1 Register LTC0 0xE04 32 read-write 0 0xFFFFFFFF LTC0_PKE0_2 LTC PKHA E0 2 Register LTC0 0xE08 32 read-write 0 0xFFFFFFFF PKHA_E0 E0 VALUE 0 32 read-write LTC0_PKE_2 LTC PKHA E 2 Register LTC0 0xE08 32 read-write 0 0xFFFFFFFF LTC0_PKE0_3 LTC PKHA E0 3 Register LTC0 0xE0C 32 read-write 0 0xFFFFFFFF PKHA_E0 E0 VALUE 0 32 read-write LTC0_PKE_3 LTC PKHA E 3 Register LTC0 0xE0C 32 read-write 0 0xFFFFFFFF LTC0_PKE0_4 LTC PKHA E0 4 Register LTC0 0xE10 32 read-write 0 0xFFFFFFFF PKHA_E0 E0 VALUE 0 32 read-write LTC0_PKE_4 LTC PKHA E 4 Register LTC0 0xE10 32 read-write 0 0xFFFFFFFF LTC0_PKE0_5 LTC PKHA E0 5 Register LTC0 0xE14 32 read-write 0 0xFFFFFFFF PKHA_E0 E0 VALUE 0 32 read-write LTC0_PKE_5 LTC PKHA E 5 Register LTC0 0xE14 32 read-write 0 0xFFFFFFFF LTC0_PKE0_6 LTC PKHA E0 6 Register LTC0 0xE18 32 read-write 0 0xFFFFFFFF PKHA_E0 E0 VALUE 0 32 read-write LTC0_PKE_6 LTC PKHA E 6 Register LTC0 0xE18 32 read-write 0 0xFFFFFFFF LTC0_PKE0_7 LTC PKHA E0 7 Register LTC0 0xE1C 32 read-write 0 0xFFFFFFFF PKHA_E0 E0 VALUE 0 32 read-write LTC0_PKE_7 LTC PKHA E 7 Register LTC0 0xE1C 32 read-write 0 0xFFFFFFFF LTC0_PKE0_8 LTC PKHA E0 8 Register LTC0 0xE20 32 read-write 0 0xFFFFFFFF PKHA_E0 E0 VALUE 0 32 read-write LTC0_PKE_8 LTC PKHA E 8 Register LTC0 0xE20 32 read-write 0 0xFFFFFFFF LTC0_PKE0_9 LTC PKHA E0 9 Register LTC0 0xE24 32 read-write 0 0xFFFFFFFF PKHA_E0 E0 VALUE 0 32 read-write LTC0_PKE_9 LTC PKHA E 9 Register LTC0 0xE24 32 read-write 0 0xFFFFFFFF LTC0_PKE0_10 LTC PKHA E0 10 Register LTC0 0xE28 32 read-write 0 0xFFFFFFFF PKHA_E0 E0 VALUE 0 32 read-write LTC0_PKE_10 LTC PKHA E 10 Register LTC0 0xE28 32 read-write 0 0xFFFFFFFF LTC0_PKE0_11 LTC PKHA E0 11 Register LTC0 0xE2C 32 read-write 0 0xFFFFFFFF PKHA_E0 E0 VALUE 0 32 read-write LTC0_PKE_11 LTC PKHA E 11 Register LTC0 0xE2C 32 read-write 0 0xFFFFFFFF LTC0_PKE0_12 LTC PKHA E0 12 Register LTC0 0xE30 32 read-write 0 0xFFFFFFFF PKHA_E0 E0 VALUE 0 32 read-write LTC0_PKE_12 LTC PKHA E 12 Register LTC0 0xE30 32 read-write 0 0xFFFFFFFF LTC0_PKE0_13 LTC PKHA E0 13 Register LTC0 0xE34 32 read-write 0 0xFFFFFFFF PKHA_E0 E0 VALUE 0 32 read-write LTC0_PKE_13 LTC PKHA E 13 Register LTC0 0xE34 32 read-write 0 0xFFFFFFFF LTC0_PKE0_14 LTC PKHA E0 14 Register LTC0 0xE38 32 read-write 0 0xFFFFFFFF PKHA_E0 E0 VALUE 0 32 read-write LTC0_PKE_14 LTC PKHA E 14 Register LTC0 0xE38 32 read-write 0 0xFFFFFFFF LTC0_PKE0_15 LTC PKHA E0 15 Register LTC0 0xE3C 32 read-write 0 0xFFFFFFFF PKHA_E0 E0 VALUE 0 32 read-write LTC0_PKE_15 LTC PKHA E 15 Register LTC0 0xE3C 32 read-write 0 0xFFFFFFFF LTC0_PKE1_0 LTC PKHA E1 0 Register LTC0 0xE40 32 read-write 0 0xFFFFFFFF PKHA_E1 E1 VALUE 0 32 read-write LTC0_PKE_16 LTC PKHA E 16 Register LTC0 0xE40 32 read-write 0 0xFFFFFFFF LTC0_PKE1_1 LTC PKHA E1 1 Register LTC0 0xE44 32 read-write 0 0xFFFFFFFF PKHA_E1 E1 VALUE 0 32 read-write LTC0_PKE_17 LTC PKHA E 17 Register LTC0 0xE44 32 read-write 0 0xFFFFFFFF LTC0_PKE1_2 LTC PKHA E1 2 Register LTC0 0xE48 32 read-write 0 0xFFFFFFFF PKHA_E1 E1 VALUE 0 32 read-write LTC0_PKE_18 LTC PKHA E 18 Register LTC0 0xE48 32 read-write 0 0xFFFFFFFF LTC0_PKE1_3 LTC PKHA E1 3 Register LTC0 0xE4C 32 read-write 0 0xFFFFFFFF PKHA_E1 E1 VALUE 0 32 read-write LTC0_PKE_19 LTC PKHA E 19 Register LTC0 0xE4C 32 read-write 0 0xFFFFFFFF LTC0_PKE1_4 LTC PKHA E1 4 Register LTC0 0xE50 32 read-write 0 0xFFFFFFFF PKHA_E1 E1 VALUE 0 32 read-write LTC0_PKE_20 LTC PKHA E 20 Register LTC0 0xE50 32 read-write 0 0xFFFFFFFF LTC0_PKE1_5 LTC PKHA E1 5 Register LTC0 0xE54 32 read-write 0 0xFFFFFFFF PKHA_E1 E1 VALUE 0 32 read-write LTC0_PKE_21 LTC PKHA E 21 Register LTC0 0xE54 32 read-write 0 0xFFFFFFFF LTC0_PKE1_6 LTC PKHA E1 6 Register LTC0 0xE58 32 read-write 0 0xFFFFFFFF PKHA_E1 E1 VALUE 0 32 read-write LTC0_PKE_22 LTC PKHA E 22 Register LTC0 0xE58 32 read-write 0 0xFFFFFFFF LTC0_PKE1_7 LTC PKHA E1 7 Register LTC0 0xE5C 32 read-write 0 0xFFFFFFFF PKHA_E1 E1 VALUE 0 32 read-write LTC0_PKE_23 LTC PKHA E 23 Register LTC0 0xE5C 32 read-write 0 0xFFFFFFFF LTC0_PKE1_8 LTC PKHA E1 8 Register LTC0 0xE60 32 read-write 0 0xFFFFFFFF PKHA_E1 E1 VALUE 0 32 read-write LTC0_PKE_24 LTC PKHA E 24 Register LTC0 0xE60 32 read-write 0 0xFFFFFFFF LTC0_PKE1_9 LTC PKHA E1 9 Register LTC0 0xE64 32 read-write 0 0xFFFFFFFF PKHA_E1 E1 VALUE 0 32 read-write LTC0_PKE_25 LTC PKHA E 25 Register LTC0 0xE64 32 read-write 0 0xFFFFFFFF LTC0_PKE1_10 LTC PKHA E1 10 Register LTC0 0xE68 32 read-write 0 0xFFFFFFFF PKHA_E1 E1 VALUE 0 32 read-write LTC0_PKE_26 LTC PKHA E 26 Register LTC0 0xE68 32 read-write 0 0xFFFFFFFF LTC0_PKE1_11 LTC PKHA E1 11 Register LTC0 0xE6C 32 read-write 0 0xFFFFFFFF PKHA_E1 E1 VALUE 0 32 read-write LTC0_PKE_27 LTC PKHA E 27 Register LTC0 0xE6C 32 read-write 0 0xFFFFFFFF LTC0_PKE1_12 LTC PKHA E1 12 Register LTC0 0xE70 32 read-write 0 0xFFFFFFFF PKHA_E1 E1 VALUE 0 32 read-write LTC0_PKE_28 LTC PKHA E 28 Register LTC0 0xE70 32 read-write 0 0xFFFFFFFF LTC0_PKE1_13 LTC PKHA E1 13 Register LTC0 0xE74 32 read-write 0 0xFFFFFFFF PKHA_E1 E1 VALUE 0 32 read-write LTC0_PKE_29 LTC PKHA E 29 Register LTC0 0xE74 32 read-write 0 0xFFFFFFFF LTC0_PKE1_14 LTC PKHA E1 14 Register LTC0 0xE78 32 read-write 0 0xFFFFFFFF PKHA_E1 E1 VALUE 0 32 read-write LTC0_PKE_30 LTC PKHA E 30 Register LTC0 0xE78 32 read-write 0 0xFFFFFFFF LTC0_PKE1_15 LTC PKHA E1 15 Register LTC0 0xE7C 32 read-write 0 0xFFFFFFFF PKHA_E1 E1 VALUE 0 32 read-write LTC0_PKE_31 LTC PKHA E 31 Register LTC0 0xE7C 32 read-write 0 0xFFFFFFFF LTC0_PKE2_0 LTC PKHA E2 0 Register LTC0 0xE80 32 read-write 0 0xFFFFFFFF PKHA_E2 E2 VALUE 0 32 read-write LTC0_PKE_32 LTC PKHA E 32 Register LTC0 0xE80 32 read-write 0 0xFFFFFFFF LTC0_PKE2_1 LTC PKHA E2 1 Register LTC0 0xE84 32 read-write 0 0xFFFFFFFF PKHA_E2 E2 VALUE 0 32 read-write LTC0_PKE_33 LTC PKHA E 33 Register LTC0 0xE84 32 read-write 0 0xFFFFFFFF LTC0_PKE2_2 LTC PKHA E2 2 Register LTC0 0xE88 32 read-write 0 0xFFFFFFFF PKHA_E2 E2 VALUE 0 32 read-write LTC0_PKE_34 LTC PKHA E 34 Register LTC0 0xE88 32 read-write 0 0xFFFFFFFF LTC0_PKE2_3 LTC PKHA E2 3 Register LTC0 0xE8C 32 read-write 0 0xFFFFFFFF PKHA_E2 E2 VALUE 0 32 read-write LTC0_PKE_35 LTC PKHA E 35 Register LTC0 0xE8C 32 read-write 0 0xFFFFFFFF LTC0_PKE2_4 LTC PKHA E2 4 Register LTC0 0xE90 32 read-write 0 0xFFFFFFFF PKHA_E2 E2 VALUE 0 32 read-write LTC0_PKE_36 LTC PKHA E 36 Register LTC0 0xE90 32 read-write 0 0xFFFFFFFF LTC0_PKE2_5 LTC PKHA E2 5 Register LTC0 0xE94 32 read-write 0 0xFFFFFFFF PKHA_E2 E2 VALUE 0 32 read-write LTC0_PKE_37 LTC PKHA E 37 Register LTC0 0xE94 32 read-write 0 0xFFFFFFFF LTC0_PKE2_6 LTC PKHA E2 6 Register LTC0 0xE98 32 read-write 0 0xFFFFFFFF PKHA_E2 E2 VALUE 0 32 read-write LTC0_PKE_38 LTC PKHA E 38 Register LTC0 0xE98 32 read-write 0 0xFFFFFFFF LTC0_PKE2_7 LTC PKHA E2 7 Register LTC0 0xE9C 32 read-write 0 0xFFFFFFFF PKHA_E2 E2 VALUE 0 32 read-write LTC0_PKE_39 LTC PKHA E 39 Register LTC0 0xE9C 32 read-write 0 0xFFFFFFFF LTC0_PKE2_8 LTC PKHA E2 8 Register LTC0 0xEA0 32 read-write 0 0xFFFFFFFF PKHA_E2 E2 VALUE 0 32 read-write LTC0_PKE_40 LTC PKHA E 40 Register LTC0 0xEA0 32 read-write 0 0xFFFFFFFF LTC0_PKE2_9 LTC PKHA E2 9 Register LTC0 0xEA4 32 read-write 0 0xFFFFFFFF PKHA_E2 E2 VALUE 0 32 read-write LTC0_PKE_41 LTC PKHA E 41 Register LTC0 0xEA4 32 read-write 0 0xFFFFFFFF LTC0_PKE2_10 LTC PKHA E2 10 Register LTC0 0xEA8 32 read-write 0 0xFFFFFFFF PKHA_E2 E2 VALUE 0 32 read-write LTC0_PKE_42 LTC PKHA E 42 Register LTC0 0xEA8 32 read-write 0 0xFFFFFFFF LTC0_PKE2_11 LTC PKHA E2 11 Register LTC0 0xEAC 32 read-write 0 0xFFFFFFFF PKHA_E2 E2 VALUE 0 32 read-write LTC0_PKE_43 LTC PKHA E 43 Register LTC0 0xEAC 32 read-write 0 0xFFFFFFFF LTC0_PKE2_12 LTC PKHA E2 12 Register LTC0 0xEB0 32 read-write 0 0xFFFFFFFF PKHA_E2 E2 VALUE 0 32 read-write LTC0_PKE_44 LTC PKHA E 44 Register LTC0 0xEB0 32 read-write 0 0xFFFFFFFF LTC0_PKE2_13 LTC PKHA E2 13 Register LTC0 0xEB4 32 read-write 0 0xFFFFFFFF PKHA_E2 E2 VALUE 0 32 read-write LTC0_PKE_45 LTC PKHA E 45 Register LTC0 0xEB4 32 read-write 0 0xFFFFFFFF LTC0_PKE2_14 LTC PKHA E2 14 Register LTC0 0xEB8 32 read-write 0 0xFFFFFFFF PKHA_E2 E2 VALUE 0 32 read-write LTC0_PKE_46 LTC PKHA E 46 Register LTC0 0xEB8 32 read-write 0 0xFFFFFFFF LTC0_PKE2_15 LTC PKHA E2 15 Register LTC0 0xEBC 32 read-write 0 0xFFFFFFFF PKHA_E2 E2 VALUE 0 32 read-write LTC0_PKE_47 LTC PKHA E 47 Register LTC0 0xEBC 32 read-write 0 0xFFFFFFFF LTC0_PKE3_0 LTC PKHA E3 0 Register LTC0 0xEC0 32 read-write 0 0xFFFFFFFF PKHA_E3 E3 VALUE 0 32 read-write LTC0_PKE_48 LTC PKHA E 48 Register LTC0 0xEC0 32 read-write 0 0xFFFFFFFF LTC0_PKE3_1 LTC PKHA E3 1 Register LTC0 0xEC4 32 read-write 0 0xFFFFFFFF PKHA_E3 E3 VALUE 0 32 read-write LTC0_PKE_49 LTC PKHA E 49 Register LTC0 0xEC4 32 read-write 0 0xFFFFFFFF LTC0_PKE3_2 LTC PKHA E3 2 Register LTC0 0xEC8 32 read-write 0 0xFFFFFFFF PKHA_E3 E3 VALUE 0 32 read-write LTC0_PKE_50 LTC PKHA E 50 Register LTC0 0xEC8 32 read-write 0 0xFFFFFFFF LTC0_PKE3_3 LTC PKHA E3 3 Register LTC0 0xECC 32 read-write 0 0xFFFFFFFF PKHA_E3 E3 VALUE 0 32 read-write LTC0_PKE_51 LTC PKHA E 51 Register LTC0 0xECC 32 read-write 0 0xFFFFFFFF LTC0_PKE3_4 LTC PKHA E3 4 Register LTC0 0xED0 32 read-write 0 0xFFFFFFFF PKHA_E3 E3 VALUE 0 32 read-write LTC0_PKE_52 LTC PKHA E 52 Register LTC0 0xED0 32 read-write 0 0xFFFFFFFF LTC0_PKE3_5 LTC PKHA E3 5 Register LTC0 0xED4 32 read-write 0 0xFFFFFFFF PKHA_E3 E3 VALUE 0 32 read-write LTC0_PKE_53 LTC PKHA E 53 Register LTC0 0xED4 32 read-write 0 0xFFFFFFFF LTC0_PKE3_6 LTC PKHA E3 6 Register LTC0 0xED8 32 read-write 0 0xFFFFFFFF PKHA_E3 E3 VALUE 0 32 read-write LTC0_PKE_54 LTC PKHA E 54 Register LTC0 0xED8 32 read-write 0 0xFFFFFFFF LTC0_PKE3_7 LTC PKHA E3 7 Register LTC0 0xEDC 32 read-write 0 0xFFFFFFFF PKHA_E3 E3 VALUE 0 32 read-write LTC0_PKE_55 LTC PKHA E 55 Register LTC0 0xEDC 32 read-write 0 0xFFFFFFFF LTC0_PKE3_8 LTC PKHA E3 8 Register LTC0 0xEE0 32 read-write 0 0xFFFFFFFF PKHA_E3 E3 VALUE 0 32 read-write LTC0_PKE_56 LTC PKHA E 56 Register LTC0 0xEE0 32 read-write 0 0xFFFFFFFF LTC0_PKE3_9 LTC PKHA E3 9 Register LTC0 0xEE4 32 read-write 0 0xFFFFFFFF PKHA_E3 E3 VALUE 0 32 read-write LTC0_PKE_57 LTC PKHA E 57 Register LTC0 0xEE4 32 read-write 0 0xFFFFFFFF LTC0_PKE3_10 LTC PKHA E3 10 Register LTC0 0xEE8 32 read-write 0 0xFFFFFFFF PKHA_E3 E3 VALUE 0 32 read-write LTC0_PKE_58 LTC PKHA E 58 Register LTC0 0xEE8 32 read-write 0 0xFFFFFFFF LTC0_PKE3_11 LTC PKHA E3 11 Register LTC0 0xEEC 32 read-write 0 0xFFFFFFFF PKHA_E3 E3 VALUE 0 32 read-write LTC0_PKE_59 LTC PKHA E 59 Register LTC0 0xEEC 32 read-write 0 0xFFFFFFFF LTC0_PKE3_12 LTC PKHA E3 12 Register LTC0 0xEF0 32 read-write 0 0xFFFFFFFF PKHA_E3 E3 VALUE 0 32 read-write LTC0_PKE_60 LTC PKHA E 60 Register LTC0 0xEF0 32 read-write 0 0xFFFFFFFF LTC0_PKE3_13 LTC PKHA E3 13 Register LTC0 0xEF4 32 read-write 0 0xFFFFFFFF PKHA_E3 E3 VALUE 0 32 read-write LTC0_PKE_61 LTC PKHA E 61 Register LTC0 0xEF4 32 read-write 0 0xFFFFFFFF LTC0_PKE3_14 LTC PKHA E3 14 Register LTC0 0xEF8 32 read-write 0 0xFFFFFFFF PKHA_E3 E3 VALUE 0 32 read-write LTC0_PKE_62 LTC PKHA E 62 Register LTC0 0xEF8 32 read-write 0 0xFFFFFFFF LTC0_PKE3_15 LTC PKHA E3 15 Register LTC0 0xEFC 32 read-write 0 0xFFFFFFFF PKHA_E3 E3 VALUE 0 32 read-write LTC0_PKE_63 LTC PKHA E 63 Register LTC0 0xEFC 32 read-write 0 0xFFFFFFFF EMVSIM0 EMVSIM EMVSIM EMVSIM0_ 0x400D4000 0 0x4C registers EMVSIM0 37 VER_ID Version ID Register 0 32 read-only 0 0xFFFFFFFF VER Version ID of the module 0 32 read-only PARAM Parameter Register 0x4 32 read-only 0x1010 0xFFFFFFFF RX_FIFO_DEPTH Receive FIFO Depth 0 8 read-only TX_FIFO_DEPTH Transmit FIFO Depth 8 8 read-only CLKCFG Clock Configuration Register 0x8 32 read-write 0 0xFFFFFFFF CLK_PRSC Clock Prescaler Value 0 8 read-write GPCNT1_CLK_SEL General Purpose Counter 1 Clock Select 8 2 read-write 00 Disabled / Reset (default) #00 01 Card Clock #01 10 Receive Clock #10 11 ETU Clock (transmit clock) #11 GPCNT0_CLK_SEL General Purpose Counter 0 Clock Select 10 2 read-write 00 Disabled / Reset (default) #00 01 Card Clock #01 10 Receive Clock #10 11 ETU Clock (transmit clock) #11 DIVISOR Baud Rate Divisor Register 0xC 32 read-write 0x174 0xFFFFFFFF DIVISOR_VALUE Divisor (F/D) Value 0 9 read-write CTRL Control Register 0x10 32 read-write 0x1000006 0xFFFFFFFF IC Inverse Convention 0 1 read-write 0 Direction convention transfers enabled (default) #0 1 Inverse convention transfers enabled #1 ICM Initial Character Mode 1 1 read-write 0 Initial Character Mode disabled #0 1 Initial Character Mode enabled (default) #1 ANACK Auto NACK Enable 2 1 read-write 0 NACK generation on errors disabled #0 1 NACK generation on errors enabled (default) #1 ONACK Overrun NACK Enable 3 1 read-write 0 NACK generation on overrun is disabled (default) #0 1 NACK generation on overrun is enabled #1 FLSH_RX Flush Receiver Bit 8 1 write-only 0 EMV SIM Receiver normal operation (default) #0 1 EMV SIM Receiver held in Reset #1 FLSH_TX Flush Transmitter Bit 9 1 write-only 0 EMV SIM Transmitter normal operation (default) #0 1 EMV SIM Transmitter held in Reset #1 SW_RST Software Reset Bit 10 1 write-only 0 EMV SIM Normal operation (default) #0 1 EMV SIM held in Reset #1 KILL_CLOCKS Kill all internal clocks 11 1 read-write 0 EMV SIM input clock enabled (default) #0 1 EMV SIM input clock is disabled #1 DOZE_EN Doze Enable 12 1 read-write 0 DOZE instruction will gate all internal EMV SIM clocks as well as the Smart Card clock when the transmit FIFO is empty (default) #0 1 DOZE instruction has no effect on EMV SIM module #1 STOP_EN STOP Enable 13 1 read-write 0 STOP instruction shuts down all EMV SIM clocks (default) #0 1 STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card) #1 RCV_EN Receiver Enable 16 1 read-write 0 EMV SIM Receiver disabled (default) #0 1 EMV SIM Receiver enabled #1 XMT_EN Transmitter Enable 17 1 read-write 0 EMV SIM Transmitter disabled (default) #0 1 EMV SIM Transmitter enabled #1 RCVR_11 Receiver 11 ETU Mode Enable 18 1 read-write 0 Receiver configured for 12 ETU operation mode (default) #0 1 Receiver configured for 11 ETU operation mode #1 RX_DMA_EN Receive DMA Enable 19 1 read-write 0 No DMA Read Request asserted for Receiver (default) #0 1 DMA Read Request asserted for Receiver #1 TX_DMA_EN Transmit DMA Enable 20 1 read-write 0 No DMA Write Request asserted for Transmitter (default) #0 1 DMA Write Request asserted for Transmitter #1 INV_CRC_VAL Invert bits in the CRC Output Value 24 1 read-write 0 Bits in CRC Output value will not be inverted. #0 1 Bits in CRC Output value will be inverted. (default) #1 CRC_OUT_FLIP CRC Output Value Bit Reversal or Flip 25 1 read-write 0 Bits within the CRC output bytes will not be reversed i.e. 15:0 will remain 15:0 (default) #0 1 Bits within the CRC output bytes will be reversed i.e. 15:0 will become {8:15,0:7} #1 CRC_IN_FLIP CRC Input Byte's Bit Reversal or Flip Control 26 1 read-write 0 Bits in the input byte will not be reversed (i.e. 7:0 will remain 7:0) before the CRC calculation (default) #0 1 Bits in the input byte will be reversed (i.e. 7:0 will become 0:7) before CRC calculation #1 CWT_EN Character Wait Time Counter Enable 27 1 read-write 0 Character Wait time Counter is disabled (default) #0 1 Character Wait time counter is enabled #1 LRC_EN LRC Enable 28 1 read-write 0 8-bit Linear Redundancy Checking disabled (default) #0 1 8-bit Linear Redundancy Checking enabled #1 CRC_EN CRC Enable 29 1 read-write 0 16-bit Cyclic Redundancy Checking disabled (default) #0 1 16-bit Cyclic Redundancy Checking enabled #1 XMT_CRC_LRC Transmit CRC or LRC Enable 30 1 read-write 0 No CRC or LRC value is transmitted (default) #0 1 Transmit LRC or CRC info when FIFO empties (whichever is enabled) #1 BWT_EN Block Wait Time Counter Enable 31 1 read-write 0 Disable BWT, BGT Counters (default) #0 1 Enable BWT, BGT Counters #1 INT_MASK Interrupt Mask Register 0x14 32 read-write 0xFFFF 0xFFFFFFFF RDT_IM Receive Data Threshold Interrupt Mask 0 1 read-write 0 RDTF interrupt enabled #0 1 RDTF interrupt masked (default) #1 TC_IM Transmit Complete Interrupt Mask 1 1 read-write 0 TCF interrupt enabled #0 1 TCF interrupt masked (default) #1 RFO_IM Receive FIFO Overflow Interrupt Mask 2 1 read-write 0 RFO interrupt enabled #0 1 RFO interrupt masked (default) #1 ETC_IM Early Transmit Complete Interrupt Mask 3 1 read-write 0 ETC interrupt enabled #0 1 ETC interrupt masked (default) #1 TFE_IM Transmit FIFO Empty Interrupt Mask 4 1 read-write 0 TFE interrupt enabled #0 1 TFE interrupt masked (default) #1 TNACK_IM Transmit NACK Threshold Interrupt Mask 5 1 read-write 0 TNTE interrupt enabled #0 1 TNTE interrupt masked (default) #1 TFF_IM Transmit FIFO Full Interrupt Mask 6 1 read-write 0 TFF interrupt enabled #0 1 TFF interrupt masked (default) #1 TDT_IM Transmit Data Threshold Interrupt Mask 7 1 read-write 0 TDTF interrupt enabled #0 1 TDTF interrupt masked (default) #1 GPCNT0_IM General Purpose Timer 0 Timeout Interrupt Mask 8 1 read-write 0 GPCNT0_TO interrupt enabled #0 1 GPCNT0_TO interrupt masked (default) #1 CWT_ERR_IM Character Wait Time Error Interrupt Mask 9 1 read-write 0 CWT_ERR interrupt enabled #0 1 CWT_ERR interrupt masked (default) #1 RNACK_IM Receiver NACK Threshold Interrupt Mask 10 1 read-write 0 RTE interrupt enabled #0 1 RTE interrupt masked (default) #1 BWT_ERR_IM Block Wait Time Error Interrupt Mask 11 1 read-write 0 BWT_ERR interrupt enabled #0 1 BWT_ERR interrupt masked (default) #1 BGT_ERR_IM Block Guard Time Error Interrupt 12 1 read-write 0 BGT_ERR interrupt enabled #0 1 BGT_ERR interrupt masked (default) #1 GPCNT1_IM General Purpose Counter 1 Timeout Interrupt Mask 13 1 read-write 0 GPCNT1_TO interrupt enabled #0 1 GPCNT1_TO interrupt masked (default) #1 RX_DATA_IM Receive Data Interrupt Mask 14 1 read-write 0 RX_DATA interrupt enabled #0 1 RX_DATA interrupt masked (default) #1 PEF_IM Parity Error Interrupt Mask 15 1 read-write 0 PEF interrupt enabled #0 1 PEF interrupt masked (default) #1 RX_THD Receiver Threshold Register 0x18 32 read-write 0x1 0xFFFFFFFF RDT Receiver Data Threshold Value 0 4 read-write RNCK_THD Receiver NACK Threshold Value 8 4 read-write 0 Zero Threshold. RTE will not be set #0000 TX_THD Transmitter Threshold Register 0x1C 32 read-write 0xF 0xFFFFFFFF TDT Transmitter Data Threshold Value 0 4 read-write TNCK_THD Transmitter NACK Threshold Value 8 4 read-write 0 TNTE will never be set; retransmission after NACK reception is disabled. #0000 1 TNTE will be set after 1 nack is received; 0 retransmissions occurs. #0001 RX_STATUS Receive Status Register 0x20 32 read-write 0 0xFFFFFFFF RFO Receive FIFO Overflow Flag 0 1 read-write 0 No overrun error has occurred (default) #0 1 A byte was received when the received FIFO was already full #1 RX_DATA Receive Data Interrupt Flag 4 1 read-write 0 No new byte is received #0 1 New byte is received ans stored in Receive FIFO #1 RDTF Receive Data Threshold Interrupt Flag 5 1 read-only 0 Number of unread bytes in receive FIFO less than the value set by RDT[3:0] (default). #0 1 Number of unread bytes in receive FIFO greater or than equal to value set by RDT[3:0]. #1 LRC_OK LRC Check OK Flag 6 1 read-only 0 Current LRC value does not match remainder. #0 1 Current calculated LRC value matches the expected result (i.e. zero). #1 CRC_OK CRC Check OK Flag 7 1 read-only 0 Current CRC value does not match remainder. #0 1 Current calculated CRC value matches the expected result. #1 CWT_ERR Character Wait Time Error Flag 8 1 read-write 0 No CWT violation has occurred (default). #0 1 Time between two consecutive characters has exceeded the value in CHAR_WAIT. #1 RTE Received NACK Threshold Error Flag 9 1 read-write 0 Number of NACKs generated by the receiver is less than the value programmed in RTH[3:0] #0 1 Number of NACKs generated by the receiver is equal to the value programmed in RTH[3:0] #1 BWT_ERR Block Wait Time Error Flag 10 1 read-write 0 Block wait time not exceeded #0 1 Block wait time was exceeded #1 BGT_ERR Block Guard Time Error Flag 11 1 read-write 0 Block guard time was sufficient #0 1 Block guard time was too small #1 PEF Parity Error Flag 12 1 read-write 0 No parity error detected #0 1 Parity error detected #1 FEF Frame Error Flag 13 1 read-write 0 No frame error detected #0 1 Frame error detected #1 RX_WPTR Receive FIFO Write Pointer Value 16 4 read-only RX_CNT Receive FIFO Byte Count 24 5 read-only 0 FIFO is emtpy #00000 TX_STATUS Transmitter Status Register 0x24 32 read-write 0xB8 0xFFFFFFFF TNTE Transmit NACK Threshold Error Flag 0 1 read-write 0 Transmit NACK threshold has not been reached (default) #0 1 Transmit NACK threshold reached; transmitter frozen #1 TFE Transmit FIFO Empty Flag 3 1 read-write 0 Transmit FIFO is not empty #0 1 Transmit FIFO is empty (default) #1 ETCF Early Transmit Complete Flag 4 1 read-write 0 Transmit pending or in progress #0 1 Transmit complete (default) #1 TCF Transmit Complete Flag 5 1 read-write 0 Transmit pending or in progress #0 1 Transmit complete (default) #1 TFF Transmit FIFO Full Flag 6 1 read-write 0 Transmit FIFO Full condition has not occurred (default) #0 1 A Transmit FIFO Full condition has occurred #1 TDTF Transmit Data Threshold Flag 7 1 read-only 0 Number of bytes in FIFO is greater than TDT[3:0], or bit has been cleared #0 1 Number of bytes in FIFO is less than or equal to TDT[3:0] (default) #1 GPCNT0_TO General Purpose Counter 0 Timeout Flag 8 1 read-write 0 GPCNT0_VAL time not reached, or bit has been cleared. (default) #0 1 General Purpose counter has reached the GPCNT0_VAL value #1 GPCNT1_TO General Purpose Counter 1 Timeout Flag 9 1 read-write 0 GPCNT1_VAL time not reached, or bit has been cleared. (default) #0 1 General Purpose counter has reached the GPCNT1_VAL value #1 TX_RPTR Transmit FIFO Read Pointer 16 4 read-only TX_CNT Transmit FIFO Byte Count 24 5 read-only 0 FIFO is emtpy #00000 PCSR Port Control and Status Register 0x28 32 read-write 0x1000000 0xFFFFFFFF SAPD Auto Power Down Enable 0 1 read-write 0 Auto power down disabled (default) #0 1 Auto power down enabled #1 SVCC_EN Vcc Enable for Smart Card 1 1 read-write 0 Smart Card Voltage disabled (default) #0 1 Smart Card Voltage enabled #1 VCCENP VCC Enable Polarity Control 2 1 read-write 0 VCC_EN is active high. Polarity of SVCC_EN is unchanged. #0 1 VCC_EN is active low. Polarity of SVCC_EN is inverted. #1 SRST Reset to Smart Card 3 1 read-write 0 Smart Card Reset is asserted (default) #0 1 Smart Card Reset is de-asserted #1 SCEN Clock Enable for Smart Card 4 1 read-write 0 Smart Card Clock Disabled #0 1 Smart Card Clock Enabled #1 SCSP Smart Card Clock Stop Polarity 5 1 read-write 0 Clock is logic 0 when stopped by SCEN #0 1 Clock is logic 1 when stopped by SCEN #1 SPD Auto Power Down Control 7 1 read-write 0 No effect (default) #0 1 Start Auto Powerdown or Power Down is in progress #1 SPDIM Smart Card Presence Detect Interrupt Mask 24 1 read-write 0 SIM presence detect interrupt is enabled #0 1 SIM presence detect interrupt is masked (default) #1 SPDIF Smart Card Presence Detect Interrupt Flag 25 1 read-write 0 No insertion or removal of Smart Card detected on Port (default) #0 1 Insertion or removal of Smart Card detected on Port #1 SPDP Smart Card Presence Detect Pin Status 26 1 read-only 0 SIM Presence Detect pin is logic low #0 1 SIM Presence Detectpin is logic high #1 SPDES SIM Presence Detect Edge Select 27 1 read-write 0 Falling edge on the pin (default) #0 1 Rising edge on the pin #1 RX_BUF Receive Data Read Buffer 0x2C 32 read-only 0 0xFFFFFFFF RX_BYTE Receive Data Byte Read 0 8 read-only TX_BUF Transmit Data Buffer 0x30 32 read-write 0 0xFFFFFFFF TX_BYTE Transmit Data Byte 0 8 write-only TX_GETU Transmitter Guard ETU Value Register 0x34 32 read-write 0 0xFFFFFFFF GETU Transmitter Guard Time Value in ETU 0 8 read-write 0 no additional ETUs inserted (default) #0 1 1 additional ETU inserted #1 CWT_VAL Character Wait Time Value Register 0x38 32 read-write 0xFFFF 0xFFFFFFFF CWT Character Wait Time Value 0 16 read-write BWT_VAL Block Wait Time Value Register 0x3C 32 read-write 0xFFFFFFFF 0xFFFFFFFF BWT Block Wait Time Value 0 32 read-write BGT_VAL Block Guard Time Value Register 0x40 32 read-write 0 0xFFFFFFFF BGT Block Guard Time Value 0 16 read-write GPCNT0_VAL General Purpose Counter 0 Timeout Value Register 0x44 32 read-write 0xFFFF 0xFFFFFFFF GPCNT0 General Purpose Counter 0 Timeout Value 0 16 read-write GPCNT1_VAL General Purpose Counter 1 Timeout Value 0x48 32 read-write 0xFFFF 0xFFFFFFFF GPCNT1 General Purpose Counter 1 Timeout Value 0 16 read-write EMVSIM1 EMVSIM EMVSIM EMVSIM1_ 0x400D5000 0 0x4C registers EMVSIM1 38 VER_ID Version ID Register 0 32 read-only 0 0xFFFFFFFF VER Version ID of the module 0 32 read-only PARAM Parameter Register 0x4 32 read-only 0x1010 0xFFFFFFFF RX_FIFO_DEPTH Receive FIFO Depth 0 8 read-only TX_FIFO_DEPTH Transmit FIFO Depth 8 8 read-only CLKCFG Clock Configuration Register 0x8 32 read-write 0 0xFFFFFFFF CLK_PRSC Clock Prescaler Value 0 8 read-write GPCNT1_CLK_SEL General Purpose Counter 1 Clock Select 8 2 read-write 00 Disabled / Reset (default) #00 01 Card Clock #01 10 Receive Clock #10 11 ETU Clock (transmit clock) #11 GPCNT0_CLK_SEL General Purpose Counter 0 Clock Select 10 2 read-write 00 Disabled / Reset (default) #00 01 Card Clock #01 10 Receive Clock #10 11 ETU Clock (transmit clock) #11 DIVISOR Baud Rate Divisor Register 0xC 32 read-write 0x174 0xFFFFFFFF DIVISOR_VALUE Divisor (F/D) Value 0 9 read-write CTRL Control Register 0x10 32 read-write 0x1000006 0xFFFFFFFF IC Inverse Convention 0 1 read-write 0 Direction convention transfers enabled (default) #0 1 Inverse convention transfers enabled #1 ICM Initial Character Mode 1 1 read-write 0 Initial Character Mode disabled #0 1 Initial Character Mode enabled (default) #1 ANACK Auto NACK Enable 2 1 read-write 0 NACK generation on errors disabled #0 1 NACK generation on errors enabled (default) #1 ONACK Overrun NACK Enable 3 1 read-write 0 NACK generation on overrun is disabled (default) #0 1 NACK generation on overrun is enabled #1 FLSH_RX Flush Receiver Bit 8 1 write-only 0 EMV SIM Receiver normal operation (default) #0 1 EMV SIM Receiver held in Reset #1 FLSH_TX Flush Transmitter Bit 9 1 write-only 0 EMV SIM Transmitter normal operation (default) #0 1 EMV SIM Transmitter held in Reset #1 SW_RST Software Reset Bit 10 1 write-only 0 EMV SIM Normal operation (default) #0 1 EMV SIM held in Reset #1 KILL_CLOCKS Kill all internal clocks 11 1 read-write 0 EMV SIM input clock enabled (default) #0 1 EMV SIM input clock is disabled #1 DOZE_EN Doze Enable 12 1 read-write 0 DOZE instruction will gate all internal EMV SIM clocks as well as the Smart Card clock when the transmit FIFO is empty (default) #0 1 DOZE instruction has no effect on EMV SIM module #1 STOP_EN STOP Enable 13 1 read-write 0 STOP instruction shuts down all EMV SIM clocks (default) #0 1 STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card) #1 RCV_EN Receiver Enable 16 1 read-write 0 EMV SIM Receiver disabled (default) #0 1 EMV SIM Receiver enabled #1 XMT_EN Transmitter Enable 17 1 read-write 0 EMV SIM Transmitter disabled (default) #0 1 EMV SIM Transmitter enabled #1 RCVR_11 Receiver 11 ETU Mode Enable 18 1 read-write 0 Receiver configured for 12 ETU operation mode (default) #0 1 Receiver configured for 11 ETU operation mode #1 RX_DMA_EN Receive DMA Enable 19 1 read-write 0 No DMA Read Request asserted for Receiver (default) #0 1 DMA Read Request asserted for Receiver #1 TX_DMA_EN Transmit DMA Enable 20 1 read-write 0 No DMA Write Request asserted for Transmitter (default) #0 1 DMA Write Request asserted for Transmitter #1 INV_CRC_VAL Invert bits in the CRC Output Value 24 1 read-write 0 Bits in CRC Output value will not be inverted. #0 1 Bits in CRC Output value will be inverted. (default) #1 CRC_OUT_FLIP CRC Output Value Bit Reversal or Flip 25 1 read-write 0 Bits within the CRC output bytes will not be reversed i.e. 15:0 will remain 15:0 (default) #0 1 Bits within the CRC output bytes will be reversed i.e. 15:0 will become {8:15,0:7} #1 CRC_IN_FLIP CRC Input Byte's Bit Reversal or Flip Control 26 1 read-write 0 Bits in the input byte will not be reversed (i.e. 7:0 will remain 7:0) before the CRC calculation (default) #0 1 Bits in the input byte will be reversed (i.e. 7:0 will become 0:7) before CRC calculation #1 CWT_EN Character Wait Time Counter Enable 27 1 read-write 0 Character Wait time Counter is disabled (default) #0 1 Character Wait time counter is enabled #1 LRC_EN LRC Enable 28 1 read-write 0 8-bit Linear Redundancy Checking disabled (default) #0 1 8-bit Linear Redundancy Checking enabled #1 CRC_EN CRC Enable 29 1 read-write 0 16-bit Cyclic Redundancy Checking disabled (default) #0 1 16-bit Cyclic Redundancy Checking enabled #1 XMT_CRC_LRC Transmit CRC or LRC Enable 30 1 read-write 0 No CRC or LRC value is transmitted (default) #0 1 Transmit LRC or CRC info when FIFO empties (whichever is enabled) #1 BWT_EN Block Wait Time Counter Enable 31 1 read-write 0 Disable BWT, BGT Counters (default) #0 1 Enable BWT, BGT Counters #1 INT_MASK Interrupt Mask Register 0x14 32 read-write 0xFFFF 0xFFFFFFFF RDT_IM Receive Data Threshold Interrupt Mask 0 1 read-write 0 RDTF interrupt enabled #0 1 RDTF interrupt masked (default) #1 TC_IM Transmit Complete Interrupt Mask 1 1 read-write 0 TCF interrupt enabled #0 1 TCF interrupt masked (default) #1 RFO_IM Receive FIFO Overflow Interrupt Mask 2 1 read-write 0 RFO interrupt enabled #0 1 RFO interrupt masked (default) #1 ETC_IM Early Transmit Complete Interrupt Mask 3 1 read-write 0 ETC interrupt enabled #0 1 ETC interrupt masked (default) #1 TFE_IM Transmit FIFO Empty Interrupt Mask 4 1 read-write 0 TFE interrupt enabled #0 1 TFE interrupt masked (default) #1 TNACK_IM Transmit NACK Threshold Interrupt Mask 5 1 read-write 0 TNTE interrupt enabled #0 1 TNTE interrupt masked (default) #1 TFF_IM Transmit FIFO Full Interrupt Mask 6 1 read-write 0 TFF interrupt enabled #0 1 TFF interrupt masked (default) #1 TDT_IM Transmit Data Threshold Interrupt Mask 7 1 read-write 0 TDTF interrupt enabled #0 1 TDTF interrupt masked (default) #1 GPCNT0_IM General Purpose Timer 0 Timeout Interrupt Mask 8 1 read-write 0 GPCNT0_TO interrupt enabled #0 1 GPCNT0_TO interrupt masked (default) #1 CWT_ERR_IM Character Wait Time Error Interrupt Mask 9 1 read-write 0 CWT_ERR interrupt enabled #0 1 CWT_ERR interrupt masked (default) #1 RNACK_IM Receiver NACK Threshold Interrupt Mask 10 1 read-write 0 RTE interrupt enabled #0 1 RTE interrupt masked (default) #1 BWT_ERR_IM Block Wait Time Error Interrupt Mask 11 1 read-write 0 BWT_ERR interrupt enabled #0 1 BWT_ERR interrupt masked (default) #1 BGT_ERR_IM Block Guard Time Error Interrupt 12 1 read-write 0 BGT_ERR interrupt enabled #0 1 BGT_ERR interrupt masked (default) #1 GPCNT1_IM General Purpose Counter 1 Timeout Interrupt Mask 13 1 read-write 0 GPCNT1_TO interrupt enabled #0 1 GPCNT1_TO interrupt masked (default) #1 RX_DATA_IM Receive Data Interrupt Mask 14 1 read-write 0 RX_DATA interrupt enabled #0 1 RX_DATA interrupt masked (default) #1 PEF_IM Parity Error Interrupt Mask 15 1 read-write 0 PEF interrupt enabled #0 1 PEF interrupt masked (default) #1 RX_THD Receiver Threshold Register 0x18 32 read-write 0x1 0xFFFFFFFF RDT Receiver Data Threshold Value 0 4 read-write RNCK_THD Receiver NACK Threshold Value 8 4 read-write 0 Zero Threshold. RTE will not be set #0000 TX_THD Transmitter Threshold Register 0x1C 32 read-write 0xF 0xFFFFFFFF TDT Transmitter Data Threshold Value 0 4 read-write TNCK_THD Transmitter NACK Threshold Value 8 4 read-write 0 TNTE will never be set; retransmission after NACK reception is disabled. #0000 1 TNTE will be set after 1 nack is received; 0 retransmissions occurs. #0001 RX_STATUS Receive Status Register 0x20 32 read-write 0 0xFFFFFFFF RFO Receive FIFO Overflow Flag 0 1 read-write 0 No overrun error has occurred (default) #0 1 A byte was received when the received FIFO was already full #1 RX_DATA Receive Data Interrupt Flag 4 1 read-write 0 No new byte is received #0 1 New byte is received ans stored in Receive FIFO #1 RDTF Receive Data Threshold Interrupt Flag 5 1 read-only 0 Number of unread bytes in receive FIFO less than the value set by RDT[3:0] (default). #0 1 Number of unread bytes in receive FIFO greater or than equal to value set by RDT[3:0]. #1 LRC_OK LRC Check OK Flag 6 1 read-only 0 Current LRC value does not match remainder. #0 1 Current calculated LRC value matches the expected result (i.e. zero). #1 CRC_OK CRC Check OK Flag 7 1 read-only 0 Current CRC value does not match remainder. #0 1 Current calculated CRC value matches the expected result. #1 CWT_ERR Character Wait Time Error Flag 8 1 read-write 0 No CWT violation has occurred (default). #0 1 Time between two consecutive characters has exceeded the value in CHAR_WAIT. #1 RTE Received NACK Threshold Error Flag 9 1 read-write 0 Number of NACKs generated by the receiver is less than the value programmed in RTH[3:0] #0 1 Number of NACKs generated by the receiver is equal to the value programmed in RTH[3:0] #1 BWT_ERR Block Wait Time Error Flag 10 1 read-write 0 Block wait time not exceeded #0 1 Block wait time was exceeded #1 BGT_ERR Block Guard Time Error Flag 11 1 read-write 0 Block guard time was sufficient #0 1 Block guard time was too small #1 PEF Parity Error Flag 12 1 read-write 0 No parity error detected #0 1 Parity error detected #1 FEF Frame Error Flag 13 1 read-write 0 No frame error detected #0 1 Frame error detected #1 RX_WPTR Receive FIFO Write Pointer Value 16 4 read-only RX_CNT Receive FIFO Byte Count 24 5 read-only 0 FIFO is emtpy #00000 TX_STATUS Transmitter Status Register 0x24 32 read-write 0xB8 0xFFFFFFFF TNTE Transmit NACK Threshold Error Flag 0 1 read-write 0 Transmit NACK threshold has not been reached (default) #0 1 Transmit NACK threshold reached; transmitter frozen #1 TFE Transmit FIFO Empty Flag 3 1 read-write 0 Transmit FIFO is not empty #0 1 Transmit FIFO is empty (default) #1 ETCF Early Transmit Complete Flag 4 1 read-write 0 Transmit pending or in progress #0 1 Transmit complete (default) #1 TCF Transmit Complete Flag 5 1 read-write 0 Transmit pending or in progress #0 1 Transmit complete (default) #1 TFF Transmit FIFO Full Flag 6 1 read-write 0 Transmit FIFO Full condition has not occurred (default) #0 1 A Transmit FIFO Full condition has occurred #1 TDTF Transmit Data Threshold Flag 7 1 read-only 0 Number of bytes in FIFO is greater than TDT[3:0], or bit has been cleared #0 1 Number of bytes in FIFO is less than or equal to TDT[3:0] (default) #1 GPCNT0_TO General Purpose Counter 0 Timeout Flag 8 1 read-write 0 GPCNT0_VAL time not reached, or bit has been cleared. (default) #0 1 General Purpose counter has reached the GPCNT0_VAL value #1 GPCNT1_TO General Purpose Counter 1 Timeout Flag 9 1 read-write 0 GPCNT1_VAL time not reached, or bit has been cleared. (default) #0 1 General Purpose counter has reached the GPCNT1_VAL value #1 TX_RPTR Transmit FIFO Read Pointer 16 4 read-only TX_CNT Transmit FIFO Byte Count 24 5 read-only 0 FIFO is emtpy #00000 PCSR Port Control and Status Register 0x28 32 read-write 0x1000000 0xFFFFFFFF SAPD Auto Power Down Enable 0 1 read-write 0 Auto power down disabled (default) #0 1 Auto power down enabled #1 SVCC_EN Vcc Enable for Smart Card 1 1 read-write 0 Smart Card Voltage disabled (default) #0 1 Smart Card Voltage enabled #1 VCCENP VCC Enable Polarity Control 2 1 read-write 0 VCC_EN is active high. Polarity of SVCC_EN is unchanged. #0 1 VCC_EN is active low. Polarity of SVCC_EN is inverted. #1 SRST Reset to Smart Card 3 1 read-write 0 Smart Card Reset is asserted (default) #0 1 Smart Card Reset is de-asserted #1 SCEN Clock Enable for Smart Card 4 1 read-write 0 Smart Card Clock Disabled #0 1 Smart Card Clock Enabled #1 SCSP Smart Card Clock Stop Polarity 5 1 read-write 0 Clock is logic 0 when stopped by SCEN #0 1 Clock is logic 1 when stopped by SCEN #1 SPD Auto Power Down Control 7 1 read-write 0 No effect (default) #0 1 Start Auto Powerdown or Power Down is in progress #1 SPDIM Smart Card Presence Detect Interrupt Mask 24 1 read-write 0 SIM presence detect interrupt is enabled #0 1 SIM presence detect interrupt is masked (default) #1 SPDIF Smart Card Presence Detect Interrupt Flag 25 1 read-write 0 No insertion or removal of Smart Card detected on Port (default) #0 1 Insertion or removal of Smart Card detected on Port #1 SPDP Smart Card Presence Detect Pin Status 26 1 read-only 0 SIM Presence Detect pin is logic low #0 1 SIM Presence Detectpin is logic high #1 SPDES SIM Presence Detect Edge Select 27 1 read-write 0 Falling edge on the pin (default) #0 1 Rising edge on the pin #1 RX_BUF Receive Data Read Buffer 0x2C 32 read-only 0 0xFFFFFFFF RX_BYTE Receive Data Byte Read 0 8 read-only TX_BUF Transmit Data Buffer 0x30 32 read-write 0 0xFFFFFFFF TX_BYTE Transmit Data Byte 0 8 write-only TX_GETU Transmitter Guard ETU Value Register 0x34 32 read-write 0 0xFFFFFFFF GETU Transmitter Guard Time Value in ETU 0 8 read-write 0 no additional ETUs inserted (default) #0 1 1 additional ETU inserted #1 CWT_VAL Character Wait Time Value Register 0x38 32 read-write 0xFFFF 0xFFFFFFFF CWT Character Wait Time Value 0 16 read-write BWT_VAL Block Wait Time Value Register 0x3C 32 read-write 0xFFFFFFFF 0xFFFFFFFF BWT Block Wait Time Value 0 32 read-write BGT_VAL Block Guard Time Value Register 0x40 32 read-write 0 0xFFFFFFFF BGT Block Guard Time Value 0 16 read-write GPCNT0_VAL General Purpose Counter 0 Timeout Value Register 0x44 32 read-write 0xFFFF 0xFFFFFFFF GPCNT0 General Purpose Counter 0 Timeout Value 0 16 read-write GPCNT1_VAL General Purpose Counter 1 Timeout Value 0x48 32 read-write 0xFFFF 0xFFFFFFFF GPCNT1 General Purpose Counter 1 Timeout Value 0 16 read-write QuadSPI0 QuadSPI QuadSPI0_ 0x400DA000 0 0x410 registers QuadSPI0 100 MCR Module Configuration Register 0 32 read-write 0xF400C 0xFFFFFFFF SWRSTSD Software reset for Serial Flash domain 0 1 read-write 0 No action #0 1 Serial Flash domain flops are reset. Does not reset configuration registers. It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects. The software resets need the clock to be running to propagate to the design. The MCR[MDIS] should therefore be set to 0 when the software reset bits are asserted. Also, before they can be deasserted again (by setting MCR[SWRSTSD] to 0), it is recommended to set the MCR[MDIS] bit to 1. Once the software resets have been deasserted, the normal operation can be started by setting the MCR[MDIS] bit to 0. #1 SWRSTHD Software reset for AHB domain 1 1 read-write 0 No action #0 1 AHB domain flops are reset. Does not reset configuration registers. It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects. The software resets need the clock to be running to propagate to the design. The MCR[MDIS] should therefore be set to 0 when the software reset bits are asserted. Also, before they can be deasserted again (by setting MCR[SWRSTHD] to 0), it is recommended to set the MCR[MDIS] bit to 1. Once the software resets have been deasserted, the normal operation can be started by setting the MCR[MDIS] bit to 0. #1 END_CFG Defines the endianness of the QSPI module.For more details refer to Byte Ordering Endianess 2 2 read-write DQS_LAT_EN DQS Latency Enable: This field is valid when latency is included in between read access from FLash in case when QSPI_MCR[DQS_EN] is 1 5 1 read-write 0 DQS Latency disabled #0 1 DQS feature with latency included enabled #1 DQS_EN DQS enable: This field is valid for both SDR and DDR mode 6 1 read-write 0 DQS disabled. #0 1 DQS enabled- When enabled, the incoming data is sampled on both the edges of DQS input when QSPI_MCR[DDR_EN] is set, else, on only one edge when QSPI_MCR[DDR_EN] is 0. The QSPI_SMPR[DDR_SMP] values are ignored. #1 DDR_EN DDR mode enable: 7 1 read-write 0 2x and 4x clocks are disabled for SDR instructions only #0 1 2x and 4x clocks are enabled supports both SDR and DDR instruction. #1 CLR_RXF Clear RX FIFO. Invalidate the RX Buffer. This is a self-clearing field. 10 1 write-only 0 No action. #0 1 Read and write pointers of the RX Buffer are reset to 0. QSPI_RBSR[RDBFL] is reset to 0. #1 CLR_TXF Clear TX FIFO/Buffer. Invalidate the TX Buffer content. This is a self-clearing field. 11 1 write-only 0 No action. #0 1 Read and write pointers of the TX Buffer are reset to 0. QSPI_TBSR[TRCTR] is reset to 0. #1 MDIS Module Disable 14 1 read-write 0 Enable QuadSPI clocks. #0 1 Allow external logic to disable QuadSPI clocks. #1 SCLKCFG Serial Clock Configuration 24 8 read-write IPCR IP Configuration Register 0x8 32 read-write 0 0xFFFFFFFF IDATSZ IP data transfer size: Defines the data transfer size in bytes of the IP command. 0 16 read-write PAR_EN When set, a transaction to two serial flash devices is triggered in parallel mode 16 1 read-write SEQID Points to a sequence in the Look-up-table 24 4 read-write FLSHCR Flash Configuration Register 0xC 32 read-write 0x303 0xFFFFFFFF TCSS Serial flash CS setup time in terms of serial flash clock cycles 0 4 read-write TCSH Serial flash CS hold time in terms of serial flash clock cycles 8 4 read-write TDH Serial flash Data In hold time: This helps in meeting the Data In Hold time requirement of a Flash 16 2 read-write 00 Data aligned with the posedge of Internal reference clock of QuadSPI #00 01 Data aligned with 2x serial flash half clock #01 10 Data aligned with 4x serial flash half clock #10 BUF0CR Buffer0 Configuration Register 0x10 32 read-write 0x2 0xFFFFFFFF MSTRID Master ID: The ID of the AHB master associated with BUFFER0 0 4 read-write ADATSZ AHB data transfer size 8 7 read-write HP_EN High Priority Enable: When set, the master associated with this buffer is assigned a priority higher than the rest of the masters 31 1 read-write BUF1CR Buffer1 Configuration Register 0x14 32 read-write 0x3 0xFFFFFFFF MSTRID Master ID: The ID of the AHB master associated with BUFFER1 0 4 read-write ADATSZ AHB data transfer size 8 7 read-write BUF2CR Buffer2 Configuration Register 0x18 32 read-write 0x4 0xFFFFFFFF MSTRID Master ID: The ID of the AHB master associated with BUFFER2 0 4 read-write ADATSZ AHB data transfer size 8 7 read-write BUF3CR Buffer3 Configuration Register 0x1C 32 read-write 0x80000000 0xFFFFFFFF MSTRID Master ID: The ID of the AHB master associated with BUFFER3 0 4 read-write ADATSZ AHB data transfer size 8 7 read-write ALLMST All master enable: When set, buffer3 acts as an all-master buffer 31 1 read-write BFGENCR Buffer Generic Configuration Register 0x20 32 read-write 0 0xFFFFFFFF SEQID Points to a sequence in the Look-up-table 12 4 read-write PAR_EN When set, a transaction to two serial flash devices is triggered in parallel mode 16 1 read-write SOCCR SOC Configuration Register 0x24 32 read-write 0 0xFFFFFFFF QSPISRC QSPI clock source select 0 3 read-write 000 Core/system clock #000 001 MCGFLL clock #001 010 MCGPLL clock #010 011 MCGPLL 2x clock (DDR mode specific) #011 100 IRC48M clock #100 101 OSCERCLK clock #101 110 MCGIRCLK clock #110 DQSLPEN When this bit is set the internal generated DQS is selected and looped back to QuadSPI, without going to DQS pad. DQSPADLPEN should be cleared when this bit is set. 8 1 read-write 0 DQS loop back is disabled #0 1 DQS loop back is enabled #1 DQSPADLPEN When this bit is set the internal generated DQS will be sent to the DQS pad first and then looped back to QuadSPI. DQSLPEN should be cleared when this bit is set. 9 1 read-write 0 DQS loop back from DQS pad is disabled #0 1 DQS loop back from DQS pad is enabled #1 DQSPHASEL Select phase shift for internal DQS generation. These bits are always zero in SDR mode. 10 2 read-write 00 No phase shift #00 01 Select 45 degree phase shift #01 10 Select 90 degree phase shift #10 11 Select 135 degree phase shift #11 DQSINVSEL Select clock source for internal DQS generation 12 1 read-write 0 Use 1x internal reference clock for the DQS generation #0 1 Use inverse 1x internal reference clock for the DQS generation #1 CK2EN Flash CK2 clock pin enable 13 1 read-write 0 CK2 flash clock is disabled #0 1 CK2 flash clock is enabled #1 DIFFCKEN Differential flash clock pins enable 14 1 read-write 0 Differential flash clock is disabled #0 1 Differential flash clock is enabled #1 OCTEN Octal data pins enable 15 1 read-write 0 QSPI0B_DATAx pins are assigned to QSPI Port B #0 1 QSPI0B_DATAx pins are assigned to QSPI Port A #1 DLYTAPSELA Delay chain tap number selection for QSPI Port A DQS 16 6 read-write 000000 Select 1 delay chain tap #0 000001 Select 2 delay chain tap #1 0000010 Select 3 delay chain tap #10 0000011 Select 4 delay chain tap #11 00000100 Select 5 delay chain tap #100 00000101 Select 6 delay chain tap #101 00000110 Select 7 delay chain tap #110 00000111 Select 8 delay chain tap #111 000001000 Select 9 delay chain tap #1000 000001001 Select 10 delay chain tap #1001 000001010 Select 11 delay chain tap #1010 000001011 Select 12 delay chain tap #1011 000001100 Select 13 delay chain tap #1100 000001101 Select 14 delay chain tap #1101 000001110 Select 15 delay chain tap #1110 000001111 Select 16 delay chain tap #1111 0000010000 Select 17 delay chain tap #10000 0000010001 Select 18 delay chain tap #10001 0000010010 Select 19 delay chain tap #10010 0000010011 Select 20 delay chain tap #10011 0000010100 Select 21 delay chain tap #10100 0000010101 Select 22 delay chain tap #10101 0000010110 Select 23 delay chain tap #10110 0000010111 Select 24 delay chain tap #10111 0000011000 Select 25 delay chain tap #11000 0000011001 Select 26 delay chain tap #11001 0000011010 Select 27 delay chain tap #11010 0000011011 Select 28 delay chain tap #11011 0000011100 Select 29 delay chain tap #11100 0000011101 Select 30 delay chain tap #11101 0000011110 Select 31 delay chain tap #11110 0000011111 Select 32 delay chain tap #11111 00000100000 Select 33 delay chain tap #100000 00000100001 Select 34 delay chain tap #100001 00000100010 Select 35 delay chain tap #100010 00000100011 Select 36 delay chain tap #100011 00000100100 Select 37 delay chain tap #100100 00000100101 Select 38 delay chain tap #100101 00000100110 Select 39 delay chain tap #100110 00000100111 Select 40 delay chain tap #100111 00000101000 Select 41 delay chain tap #101000 00000101001 Select 42 delay chain tap #101001 00000101010 Select 43 delay chain tap #101010 00000101011 Select 44 delay chain tap #101011 00000101100 Select 45 delay chain tap #101100 00000101101 Select 46 delay chain tap #101101 00000101110 Select 47 delay chain tap #101110 00000101111 Select 48 delay chain tap #101111 00000110000 Select 49 delay chain tap #110000 00000110001 Select 50 delay chain tap #110001 00000110010 Select 51 delay chain tap #110010 00000110011 Select 52 delay chain tap #110011 00000110100 Select 53 delay chain tap #110100 00000110101 Select 54 delay chain tap #110101 00000110110 Select 55 delay chain tap #110110 00000110111 Select 56 delay chain tap #110111 00000111000 Select 57 delay chain tap #111000 00000111001 Select 58 delay chain tap #111001 00000111010 Select 59 delay chain tap #111010 00000111011 Select 60 delay chain tap #111011 00000111100 Select 61 delay chain tap #111100 00000111101 Select 62 delay chain tap #111101 00000111110 Select 63 delay chain tap #111110 00000111111 Select 64 delay chain tap #111111 DLYTAPSELB Delay chain tap number selection for QSPI Port B DQS 24 6 read-write 000000 Select 1 delay chain tap #0 000001 Select 2 delay chain tap #1 0000010 Select 3 delay chain tap #10 0000011 Select 4 delay chain tap #11 00000100 Select 5 delay chain tap #100 00000101 Select 6 delay chain tap #101 00000110 Select 7 delay chain tap #110 00000111 Select 8 delay chain tap #111 000001000 Select 9 delay chain tap #1000 000001001 Select 10 delay chain tap #1001 000001010 Select 11 delay chain tap #1010 000001011 Select 12 delay chain tap #1011 000001100 Select 13 delay chain tap #1100 000001101 Select 14 delay chain tap #1101 000001110 Select 15 delay chain tap #1110 000001111 Select 16 delay chain tap #1111 0000010000 Select 17 delay chain tap #10000 0000010001 Select 18 delay chain tap #10001 0000010010 Select 19 delay chain tap #10010 0000010011 Select 20 delay chain tap #10011 0000010100 Select 21 delay chain tap #10100 0000010101 Select 22 delay chain tap #10101 0000010110 Select 23 delay chain tap #10110 0000010111 Select 24 delay chain tap #10111 0000011000 Select 25 delay chain tap #11000 0000011001 Select 26 delay chain tap #11001 0000011010 Select 27 delay chain tap #11010 0000011011 Select 28 delay chain tap #11011 0000011100 Select 29 delay chain tap #11100 0000011101 Select 30 delay chain tap #11101 0000011110 Select 31 delay chain tap #11110 0000011111 Select 32 delay chain tap #11111 00000100000 Select 33 delay chain tap #100000 00000100001 Select 34 delay chain tap #100001 00000100010 Select 35 delay chain tap #100010 00000100011 Select 36 delay chain tap #100011 00000100100 Select 37 delay chain tap #100100 00000100101 Select 38 delay chain tap #100101 00000100110 Select 39 delay chain tap #100110 00000100111 Select 40 delay chain tap #100111 00000101000 Select 41 delay chain tap #101000 00000101001 Select 42 delay chain tap #101001 00000101010 Select 43 delay chain tap #101010 00000101011 Select 44 delay chain tap #101011 00000101100 Select 45 delay chain tap #101100 00000101101 Select 46 delay chain tap #101101 00000101110 Select 47 delay chain tap #101110 00000101111 Select 48 delay chain tap #101111 00000110000 Select 49 delay chain tap #110000 00000110001 Select 50 delay chain tap #110001 00000110010 Select 51 delay chain tap #110010 00000110011 Select 52 delay chain tap #110011 00000110100 Select 53 delay chain tap #110100 00000110101 Select 54 delay chain tap #110101 00000110110 Select 55 delay chain tap #110110 00000110111 Select 56 delay chain tap #110111 00000111000 Select 57 delay chain tap #111000 00000111001 Select 58 delay chain tap #111001 00000111010 Select 59 delay chain tap #111010 00000111011 Select 60 delay chain tap #111011 00000111100 Select 61 delay chain tap #111100 00000111101 Select 62 delay chain tap #111101 00000111110 Select 63 delay chain tap #111110 00000111111 Select 64 delay chain tap #111111 BUF0IND Buffer0 Top Index Register 0x30 32 read-write 0 0xFFFFFFFF TPINDX0 Top index of buffer 0. 3 29 read-write BUF1IND Buffer1 Top Index Register 0x34 32 read-write 0 0xFFFFFFFF TPINDX1 Top index of buffer 1. 3 29 read-write BUF2IND Buffer2 Top Index Register 0x38 32 read-write 0 0xFFFFFFFF TPINDX2 Top index of buffer 2. 3 29 read-write SFAR Serial Flash Address Register 0x100 32 read-write 0 0xFFFFFFFF SFADR Serial Flash Address. The register content is used as byte address for all following IP Commands. 0 32 read-write SFACR Serial Flash Address Configuration Register 0x104 32 read-write 0 0xFFFFFFFF CAS Column Address Space 0 4 read-write WA Word Addressable 16 1 read-write 0 Byte addressable serial flash mode. #0 1 Word (2 byte) addressable serial flash mode. #1 SMPR Sampling Register 0x108 32 read-write 0 0xFFFFFFFF HSENA Half Speed serial flash clock Enable 0 1 read-write 0 Disable divide by 2 of serial flash clock for half speed commands #0 1 Enable divide by 2 of serial flash clock for half speed commands #1 HSPHS Half Speed Phase selection for SDR instructions. 1 1 read-write 0 Select sampling at non-inverted clock #0 1 Select sampling at inverted clock #1 HSDLY Half Speed Delay selection for SDR instructions. 2 1 read-write 0 One clock cycle delay #0 1 Two clock cycle delay #1 FSPHS Full Speed Phase selection for SDR instructions. 5 1 read-write 0 Select sampling at non-inverted clock #0 1 Select sampling at inverted clock. This bit is also used in DQS mode and ignored when using non-DQS DDR instructions. #1 FSDLY Full Speed Delay selection for SDR instructions. Select the delay with respect to the reference edge for the sample point valid for full speed commands: 6 1 read-write 0 One clock cycle delay #0 1 Two clock cycles delay. This bit is also used in DQS mode and ignored when using non-DQS DDR instructions. #1 DDRSMP DDR Sampling point 16 3 read-write RBSR RX Buffer Status Register 0x10C 32 read-only 0 0xFFFFFFFF RDBFL RX Buffer Fill Level, indicates how many entries of 4 bytes are still available in the RX Buffer 8 5 read-only RDCTR Read Counter, indicates how many entries of 4 bytes have been removed from the RX Buffer 16 16 read-only RBCT RX Buffer Control Register 0x110 32 read-write 0 0xFFFFFFFF WMRK RX Buffer Watermark: This field determines when the readout action of the RX Buffer is triggered 0 4 read-write RXBRD RX Buffer Readout: This bit specifies the access scheme for the RX Buffer readout. 8 1 read-write 0 RX Buffer content is read using the AHB Bus registers QSPI_ARDB0 to QSPI_ARDB15. For details, refer to Exclusive Access to Serial Flash for AHB Commands. #0 1 RX Buffer content is read using the IP Bus registers QSPI_RBDR0 to QSPI_RBDR15. #1 TBSR TX Buffer Status Register 0x150 32 read-only 0 0xFFFFFFFF TRBFL TX Buffer Fill Level 8 5 read-only TRCTR Transmit Counter 16 16 read-only TBDR TX Buffer Data Register 0x154 32 read-write 0 0xFFFFFFFF TXDATA TX Data On write access the data is written into the next available entry of the TX Buffer and the QPSI_TBSR[TRBFL] field is updated accordingly 0 32 read-write TBCT Tx Buffer Control Register 0x158 32 read-write 0 0xFFFFFFFF WMRK Determines the watermark for the TX Buffer 0 4 read-write SR Status Register 0x15C 32 read-only 0x2003800 0xFFFFFFFF BUSY Module Busy: Asserted when module is currently busy handling a transaction to an external flash device 0 1 read-only IP_ACC IP Access: Asserted when transaction currently executed was initiated by IP bus. 1 1 read-only AHB_ACC AHB Access: Asserted when the transaction currently executed was initiated by AHB bus. 2 1 read-only AHBGNT AHB Command priority Granted: Asserted when another module has been granted priority of AHB Commands against IP Commands 5 1 read-only AHBTRN AHB Access Transaction pending: Asserted when there is a pending request on the AHB interface 6 1 read-only AHB0NE AHB 0 Buffer Not Empty: Asserted when AHB 0 buffer contains data. 7 1 read-only AHB1NE AHB 1 Buffer Not Empty: Asserted when AHB 1 buffer contains data. 8 1 read-only AHB2NE AHB 2 Buffer Not Empty: Asserted when AHB 2 buffer contains data. 9 1 read-only AHB3NE AHB 3 Buffer Not Empty: Asserted when AHB 3 buffer contains data. 10 1 read-only AHB0FUL AHB 0 Buffer Full: Asserted when AHB 0 buffer is full. 11 1 read-only AHB1FUL AHB 1 Buffer Full: Asserted when AHB 1 buffer is full. 12 1 read-only AHB2FUL AHB 2 Buffer Full: Asserted when AHB 2 buffer is full. 13 1 read-only AHB3FUL AHB 3 Buffer Full: Asserted when AHB 3 buffer is full. 14 1 read-only RXWE RX Buffer Watermark Exceeded: Asserted when the number of valid entries in the RX Buffer exceeds the number given in the QSPI_RBCT[WMRK] field 16 1 read-only RXFULL RX Buffer Full: Asserted when the RX Buffer is full, i 19 1 read-only RXDMA RX Buffer DMA: Asserted when RX Buffer read out via DMA is active i.e DMA is requested or running. 23 1 read-only TXEDA Tx Buffer Enough Data Available 24 1 read-only TXWA TX Buffer watermark Available 25 1 read-only TXDMA TXDMA 26 1 read-only TXFULL TX Buffer Full: Asserted when no more data can be stored. 27 1 read-only DLPSMP Data learning pattern sampling point: The sampling point found by the controller with the data learning pattern 29 3 read-only FR Flag Register 0x160 32 read-write 0x8000000 0xFFFFFFFF TFF IP Command Transaction Finished Flag: Set when the QuadSPI module has finished a running IP Command 0 1 read-write IPGEF IP Command Trigger during AHB Grant Error Flag: Set when the following condition occurs: A write access occurs to the QSPI_IPCR[SEQID] field and the QSPI_SR[AHBGNT] bit is set 4 1 read-write IPIEF IP Command Trigger could not be executed Error Flag 6 1 read-write IPAEF IP Command Trigger during AHB Access Error Flag 7 1 read-write IUEF IP Command Usage Error Flag: Set when in parallel flash mode the execution of an IP Command is started with more than one pad enabled and the sequence pointed to by the sequence ID contains a WRITE or a WRITE_DDR command 11 1 read-write ABOF AHB Buffer Overflow Flag: Set when the size of the AHB access exceeds the size of the AHB buffer 12 1 read-write AIBSEF AHB Illegal Burst Size Error Flag: Set whenever the total burst size(size x beat) of an AHB transaction is greater than the prefetch data size 13 1 read-write AITEF AHB Illegal transaction error flag 14 1 read-write ABSEF AHB Sequence Error Flag: Set when the execution of an AHB Command is started with a WRITE or WRITE_DDR Command in the sequence pointed to by the QSPI_BUFxCR register 15 1 read-write RBDF RX Buffer Drain Flag: Will be set if the QuadSPI_SR[RXWE] status bit is asserted 16 1 read-write RBOF RX Buffer Overflow Flag: Set when not all the data read from the serial flash device could be pushed into the RX Buffer 17 1 read-write ILLINE Illegal Instruction Error Flag: Set when an illegal instruction is encountered by the controller in any of the sequences 23 1 read-write TBUF TX Buffer Underrun Flag: Set when the module tried to pull data although TX Buffer was emptyor the buffer contains less than 128bits of data 26 1 read-write TBFF TX Buffer Fill Flag: Before writing to the TX buffer, this bit should be cleared 27 1 read-write DLPFF Data Learning Pattern Failure Flag: Set when DATA_LEARN instruction was encountered in a sequence but no sampling point was found for the data learning patternin case only 8 bit data learning is requested for non DQS mode 31 1 read-write RSER Interrupt and DMA Request Select and Enable Register 0x164 32 read-write 0 0xFFFFFFFF TFIE Transaction Finished Interrupt Enable 0 1 read-write 0 No TFF interrupt will be generated #0 1 TFF interrupt will be generated #1 IPGEIE IP Command Trigger during AHB Grant Error Interrupt Enable 4 1 read-write 0 No IPGEF interrupt will be generated #0 1 IPGEF interrupt will be generated #1 IPIEIE IP Command Trigger during IP Access Error Interrupt Enable 6 1 read-write 0 No IPIEF interrupt will be generated #0 1 IPIEF interrupt will be generated #1 IPAEIE IP Command Trigger during AHB Access Error Interrupt Enable 7 1 read-write 0 No IPAEF interrupt will be generated #0 1 IPAEF interrupt will be generated #1 IUEIE IP Command Usage Error Interrupt Enable 11 1 read-write 0 No IUEF interrupt will be generated #0 1 IUEF interrupt will be generated #1 ABOIE AHB Buffer Overflow Interrupt Enable 12 1 read-write 0 No ABOF interrupt will be generated #0 1 ABOF interrupt will be generated #1 AIBSIE AHB Illegal Burst Size Interrupt Enable 13 1 read-write 0 No AIBSEF interrupt will be generated #0 1 AIBSEF interrupt will be generated #1 AITIE AHB Illegal transaction interrupt enable. 14 1 read-write 0 No AITEF interrupt will be generated #0 1 AITEF interrupt will be generated #1 ABSEIE AHB Sequence Error Interrupt Enable: Triggered by ABSEF flags of QSPI_FR 15 1 read-write 0 No ABSEF interrupt will be generated #0 1 ABSEF interrupt will be generated #1 RBDIE RX Buffer Drain Interrupt Enable: Enables generation of IRQ requests for RX Buffer Drain 16 1 read-write 0 No RBDF interrupt will be generated #0 1 RBDF Interrupt will be generated #1 RBOIE RX Buffer Overflow Interrupt Enable 17 1 read-write 0 No RBOF interrupt will be generated #0 1 RBOF interrupt will be generated #1 RBDDE RX Buffer Drain DMA Enable: Enables generation of DMA requests for RX Buffer Drain 21 1 read-write 0 No DMA request will be generated #0 1 DMA request will be generated #1 ILLINIE Illegal Instruction Error Interrupt Enable. Triggered by ILLINE flag in QSPI_FR 23 1 read-write 0 No ILLINE interrupt will be generated #0 1 ILLINE interrupt will be generated #1 TBFDE TX Buffer Fill DMA Enable 25 1 read-write 0 No DMA request will be generated #0 1 DMA request will be generated #1 TBUIE TX Buffer Underrun Interrupt Enable 26 1 read-write 0 No TBUF interrupt will be generated #0 1 TBUF interrupt will be generated #1 TBFIE TX Buffer Fill Interrupt Enable 27 1 read-write 0 No TBFF interrupt will be generated #0 1 TBFF interrupt will be generated #1 DLPFIE Data Learning Pattern Failure Interrupt enable . Triggered by DLPFF flag in QSPI_FR register 31 1 read-write 0 No DLPFF interrupt will be generated #0 1 DLPFF interrupt will be generated #1 SPNDST Sequence Suspend Status Register 0x168 32 read-only 0 0xFFFFFFFF SUSPND When set, it signifies that a sequence is in suspended state 0 1 read-only SPDBUF Suspended Buffer: Provides the suspended buffer number. Valid only when SUSPND is set to 1'b1 6 2 read-only DATLFT Data left: Provides information about the amount of data left to be read in the suspended sequence 9 6 read-only SPTRCLR Sequence Pointer Clear Register 0x16C 32 read-write 0 0xFFFFFFFF BFPTRC Buffer Pointer Clear: 1: Clears the sequence pointer for AHB accesses as defined in QuadSPI_BFGENCR 0 1 write-only IPPTRC IP Pointer Clear: 1: Clears the sequence pointer for IP accesses as defined in QuadSPI_IPCR This is a self-clearing field 8 1 write-only SFA1AD Serial Flash A1 Top Address 0x180 32 read-write 0x6FFFFC00 0xFFFFFFFF TPADA1 Top address for Serial Flash A1. In effect, TPADxx is the first location of the next memory. 10 22 read-write SFA2AD Serial Flash A2 Top Address 0x184 32 read-write 0x6FFFFC00 0xFFFFFFFF TPADA2 Top address for Serial Flash A2. In effect, TPxxAD is the first location of the next memory. 10 22 read-write SFB1AD Serial Flash B1Top Address 0x188 32 read-write 0x6FFFFC00 0xFFFFFFFF TPADB1 Top address for Serial Flash B1.In effect, TPxxAD is the first location of the next memory. 10 22 read-write SFB2AD Serial Flash B2Top Address 0x18C 32 read-write 0x6FFFFC00 0xFFFFFFFF TPADB2 Top address for Serial Flash B2. In effect, TPxxAD is the first location of the next memory. 10 22 read-write DLPR Data Learn Pattern Register 0x190 32 read-write 0xAA553443 0xFFFFFFFF DLPV Data Learning Pattern Value: This value is used for data learning in DDR and DQS mode 0 32 read-write 16 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 RBDR%s RX Buffer Data Register 0x200 32 read-only 0 0xFFFFFFFF RXDATA RX Data 0 32 read-only LUTKEY LUT Key Register 0x300 32 read-write 0x5AF05AF0 0xFFFFFFFF KEY The key to lock or unlock the LUT. The KEY is 0x5AF05AF0. The read value is always 0x5AF05AF0 0 32 read-write LCKCR LUT Lock Configuration Register 0x304 32 read-write 0x2 0xFFFFFFFF LOCK Locks the LUT when the following condition is met: This register is written just after the LUTKEYLUT Key Register The LUT key register was written with 0x5AF05AF0 key 0 1 read-write UNLOCK Unlocks the LUT when the following two conditions are met: 1 1 1 read-write 64 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63 LUT%s Look-up Table register 0x310 32 read-write 0 0xFFFFFFFF OPRND0 Operand for INSTR0. 0 8 read-write PAD0 Pad information for INSTR0. 8 2 read-write 00 1 Pad #00 01 2 Pads #01 10 4 Pads #10 11 8 Pads #11 INSTR0 Instruction 0 10 6 read-write OPRND1 Operand for INSTR1. 16 8 read-write PAD1 Pad information for INSTR1. 24 2 read-write 00 1 Pad #00 01 2 Pads #01 10 4 Pads #10 11 8 Pads #11 INSTR1 Instruction 1 26 6 read-write OTFAD OTFAD OTFAD_ 0x400DAC00 0 0x1E0 registers CR Control Register 0 32 read-write 0 0xFFFFFFFF FSVM Force Security Violation Mode 2 1 read-write 0 No effect on the operating mode. #0 1 Force entry into SVM after a write with this data bit set and the data bit associated with FLDM cleared. SR[MODE] signals the operating mode. #1 FLDM Force Logically Disabled Mode 3 1 read-write 0 No effect on the operating mode. #0 1 Force entry into LDM after a write with this data bit set. SR[MODE] signals the operating mode. #1 RRAE Restricted Register Access Enable 7 1 read-write 0 Register access is fully enabled. The OTFAD programming model registers can be accessed "normally". #0 1 Register access is restricted and only the CR, SR and CRC can be accessed; others are treated as RAZ/WI. #1 CCTX CRC Context 16 2 read-write 00 Enable CTX0 CRC check. #00 01 Enable CTX1 CRC check. #01 10 Enable CTX2 CRC check. #10 11 Enable CTX3 CRC check. #11 CRCE CRC Enable 20 1 read-write 0 CRC-32 is disabled. #0 1 CRC-32 for the context defined by CR[CCTRX] is enabled. #1 CRCI CRC Initialization 21 1 write-only 0 CRC data register is unaffected. #0 1 CRC data register is immediately initialized after a write with this data bit set. #1 GE Global OTFAD Enable 31 1 read-write 0 OTFAD has decryption disabled, and bypasses all data fetched by the QuadSPI. #0 1 OTFAD has decryption enabled, and processes fetched data as defined by the hardware configuration. #1 SR Status Register 0x4 32 read-only 0x40 0xFFFFFFFF MDPCP MDPC Present 1 1 read-only MODE Operating Mode 2 2 read-only 00 Operating in Normal mode (NRM) #00 01 Unused (reserved) #01 10 Operating in Security Violation Mode (SVM) #10 11 Operating in Logically Disabled Mode (LDM) #11 NCTX Number of Contexts 4 4 read-only HRL Hardware Revision Level 24 4 read-only RRAM Restricted Register Access Mode 28 1 read-only 0 Register access is fully enabled. The OTFAD programming model registers can be accessed "normally". #0 1 Register access is restricted and only the CR, SR and CRC can be accessed; others are treated as RAZ/WI. #1 GEM Global Enable Mode 29 1 read-only 0 OTFAD is disabled, and bypasses all data fetched by the QuadSPI. #0 1 OTFAD is enabled, and processes data fetched by the QuadSPI as defined by the hardware configuration. #1 CRC Cyclic Redundancy Check Register 0x8 32 read-write 0 0xFFFFFFFF CRCD CRC Data. 0 32 read-write 4 0x40 0,1,2,3 CTX%s_KEY_W0 AES Key Word0 0x100 32 read-write 0 0xFFFFFFFF W0KEY AES Key 0 32 read-write 4 0x40 0,1,2,3 CTX%s_KEY_W1 AES Key Word1 0x104 32 read-write 0 0xFFFFFFFF W1KEY AES Key 0 32 read-write 4 0x40 0,1,2,3 CTX%s_KEY_W2 AES Key Word2 0x108 32 read-write 0 0xFFFFFFFF W2KEY AES Key 0 32 read-write 4 0x40 0,1,2,3 CTX%s_KEY_W3 AES Key Word3 0x10C 32 read-write 0 0xFFFFFFFF W3KEY AES Key 0 32 read-write 4 0x40 0,1,2,3 CTX%s_CTR_W0 AES Counter Word0 0x110 32 read-write 0 0xFFFFFFFF W0CTR AES Counter 0 32 read-write 4 0x40 0,1,2,3 CTX%s_CTR_W1 AES Counter Word1 0x114 32 read-write 0 0xFFFFFFFF W1CTR AES Counter 0 32 read-write 4 0x40 0,1,2,3 CTX%s_RGD_W0 AES Region Descriptor Word0 0x118 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 10 22 read-write 4 0x40 0,1,2,3 CTX%s_RGD_W1 AES Region Descriptor Word1 0x11C 32 read-write 0x3F8 0xFFFFFFFF VLD Valid 0 1 read-write 0 Context is invalid. #0 1 Context is valid. #1 ADE Aes Decryption Enable. 1 1 read-write 0 Bypass the fetched data. #0 1 Perform the CTR-AES128 mode decryption on the fetched data. #1 RO Read-Only 2 1 read-write 0 The context registers can be accessed normally (as defined by SR[RRAM]). #0 1 The context registers are read-only and accesses may be further restricted based on SR[RRAM]. #1 ENDADDR End Address 10 22 read-write FLEXIO0 The FLEXIO Memory Map/Register Definition can be found here. FLEXIO0_ 0x400DF000 0 0x7A0 registers FLEXIO0 70 VERID Version ID Register 0 32 read-only 0x1010001 0xFFFFFFFF FEATURE Feature Specification Number 0 16 read-only 0 Standard features implemented. #0 1 Supports state, logic and parallel modes. #1 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x10200808 0xFFFFFFFF SHIFTER Shifter Number 0 8 read-only TIMER Timer Number 8 8 read-only PIN Pin Number 16 8 read-only TRIGGER Trigger Number 24 8 read-only CTRL FlexIO Control Register 0x8 32 read-write 0 0xFFFFFFFF FLEXEN FlexIO Enable 0 1 read-write 0 FlexIO module is disabled. #0 1 FlexIO module is enabled. #1 SWRST Software Reset 1 1 read-write 0 Software reset is disabled #0 1 Software reset is enabled, all FlexIO registers except the Control Register are reset. #1 FASTACC Fast Access 2 1 read-write 0 Configures for normal register accesses to FlexIO #0 1 Configures for fast register accesses to FlexIO #1 DBGE Debug Enable 30 1 read-write 0 FlexIO is disabled in debug modes. #0 1 FlexIO is enabled in debug modes #1 DOZEN Doze Enable 31 1 read-write 0 FlexIO enabled in Doze modes. #0 1 FlexIO disabled in Doze modes. #1 PIN Pin State Register 0xC 32 read-only 0 0xFFFFFFFF PDI Pin Data Input 0 32 read-only SHIFTSTAT Shifter Status Register 0x10 32 read-write 0 0xFFFFFFFF SSF Shifter Status Flag 0 8 read-write 0 Status flag is clear #0 1 Status flag is set #1 SHIFTERR Shifter Error Register 0x14 32 read-write 0 0xFFFFFFFF SEF Shifter Error Flags 0 8 read-write 0 Shifter Error Flag is clear #0 1 Shifter Error Flag is set #1 TIMSTAT Timer Status Register 0x18 32 read-write 0 0xFFFFFFFF TSF Timer Status Flags 0 8 read-write 0 Timer Status Flag is clear #0 1 Timer Status Flag is set #1 SHIFTSIEN Shifter Status Interrupt Enable 0x20 32 read-write 0 0xFFFFFFFF SSIE Shifter Status Interrupt Enable 0 8 read-write 0 Shifter Status Flag interrupt disabled #0 1 Shifter Status Flag interrupt enabled #1 SHIFTEIEN Shifter Error Interrupt Enable 0x24 32 read-write 0 0xFFFFFFFF SEIE Shifter Error Interrupt Enable 0 8 read-write 0 Shifter Error Flag interrupt disabled #0 1 Shifter Error Flag interrupt enabled #1 TIMIEN Timer Interrupt Enable Register 0x28 32 read-write 0 0xFFFFFFFF TEIE Timer Status Interrupt Enable 0 8 read-write 0 Timer Status Flag interrupt is disabled #0 1 Timer Status Flag interrupt is enabled #1 SHIFTSDEN Shifter Status DMA Enable 0x30 32 read-write 0 0xFFFFFFFF SSDE Shifter Status DMA Enable 0 8 read-write 0 Shifter Status Flag DMA request is disabled #0 1 Shifter Status Flag DMA request is enabled #1 SHIFTSTATE Shifter State Register 0x40 32 read-write 0 0xFFFFFFFF STATE Current State Pointer 0 3 read-write 8 0x4 0,1,2,3,4,5,6,7 SHIFTCTL%s Shifter Control N Register 0x80 32 read-write 0 0xFFFFFFFF SMOD Shifter Mode 0 3 read-write 000 Disabled. #000 001 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. #001 010 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. #010 100 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. #100 101 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. #101 110 State mode. SHIFTBUF contents are used for storing programmable state attributes. #110 111 Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. #111 PINPOL Shifter Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Shifter Pin Select 8 5 read-write PINCFG Shifter Pin Configuration 16 2 read-write 00 Shifter pin output disabled #00 01 Shifter pin open drain or bidirectional output enable #01 10 Shifter pin bidirectional output data #10 11 Shifter pin output #11 TIMPOL Timer Polarity 23 1 read-write 0 Shift on posedge of Shift clock #0 1 Shift on negedge of Shift clock #1 TIMSEL Timer Select 24 3 read-write 8 0x4 0,1,2,3,4,5,6,7 SHIFTCFG%s Shifter Configuration N Register 0x100 32 read-write 0 0xFFFFFFFF SSTART Shifter Start bit 0 2 read-write 00 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable #00 01 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift #01 10 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 #10 11 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 #11 SSTOP Shifter Stop bit 4 2 read-write 00 Stop bit disabled for transmitter/receiver/match store #00 01 Reserved for transmitter/receiver/match store #01 10 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 #10 11 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 #11 INSRC Input Source 8 1 read-write 0 Pin #0 1 Shifter N+1 Output #1 PWIDTH Parallel Width 16 5 read-write 8 0x4 0,1,2,3,4,5,6,7 SHIFTBUF%s Shifter Buffer N Register 0x200 32 read-write 0 0xFFFFFFFF SHIFTBUF Shift Buffer 0 32 read-write 8 0x4 0,1,2,3,4,5,6,7 SHIFTBUFBIS%s Shifter Buffer N Bit Swapped Register 0x280 32 read-write 0 0xFFFFFFFF SHIFTBUFBIS Shift Buffer 0 32 read-write 8 0x4 0,1,2,3,4,5,6,7 SHIFTBUFBYS%s Shifter Buffer N Byte Swapped Register 0x300 32 read-write 0 0xFFFFFFFF SHIFTBUFBYS Shift Buffer 0 32 read-write 8 0x4 0,1,2,3,4,5,6,7 SHIFTBUFBBS%s Shifter Buffer N Bit Byte Swapped Register 0x380 32 read-write 0 0xFFFFFFFF SHIFTBUFBBS Shift Buffer 0 32 read-write 8 0x4 0,1,2,3,4,5,6,7 TIMCTL%s Timer Control N Register 0x400 32 read-write 0 0xFFFFFFFF TIMOD Timer Mode 0 2 read-write 00 Timer Disabled. #00 01 Dual 8-bit counters baud/bit mode. #01 10 Dual 8-bit counters PWM mode. #10 11 Single 16-bit counter mode. #11 PINPOL Timer Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Timer Pin Select 8 5 read-write PINCFG Timer Pin Configuration 16 2 read-write 00 Timer pin output disabled #00 01 Timer pin open drain or bidirectional output enable #01 10 Timer pin bidirectional output data #10 11 Timer pin output #11 TRGSRC Trigger Source 22 1 read-write 0 External trigger selected #0 1 Internal trigger selected #1 TRGPOL Trigger Polarity 23 1 read-write 0 Trigger active high #0 1 Trigger active low #1 TRGSEL Trigger Select 24 6 read-write 8 0x4 0,1,2,3,4,5,6,7 TIMCFG%s Timer Configuration N Register 0x480 32 read-write 0 0xFFFFFFFF TSTART Timer Start Bit 1 1 read-write 0 Start bit disabled #0 1 Start bit enabled #1 TSTOP Timer Stop Bit 4 2 read-write 00 Stop bit disabled #00 01 Stop bit is enabled on timer compare #01 10 Stop bit is enabled on timer disable #10 11 Stop bit is enabled on timer compare and timer disable #11 TIMENA Timer Enable 8 3 read-write 000 Timer always enabled #000 001 Timer enabled on Timer N-1 enable #001 010 Timer enabled on Trigger high #010 011 Timer enabled on Trigger high and Pin high #011 100 Timer enabled on Pin rising edge #100 101 Timer enabled on Pin rising edge and Trigger high #101 110 Timer enabled on Trigger rising edge #110 111 Timer enabled on Trigger rising or falling edge #111 TIMDIS Timer Disable 12 3 read-write 000 Timer never disabled #000 001 Timer disabled on Timer N-1 disable #001 010 Timer disabled on Timer compare #010 011 Timer disabled on Timer compare and Trigger Low #011 100 Timer disabled on Pin rising or falling edge #100 101 Timer disabled on Pin rising or falling edge provided Trigger is high #101 110 Timer disabled on Trigger falling edge #110 TIMRST Timer Reset 16 3 read-write 000 Timer never reset #000 010 Timer reset on Timer Pin equal to Timer Output #010 011 Timer reset on Timer Trigger equal to Timer Output #011 100 Timer reset on Timer Pin rising edge #100 110 Timer reset on Trigger rising edge #110 111 Timer reset on Trigger rising or falling edge #111 TIMDEC Timer Decrement 20 2 read-write 00 Decrement counter on FlexIO clock, Shift clock equals Timer output. #00 01 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. #01 10 Decrement counter on Pin input (both edges), Shift clock equals Pin input. #10 11 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. #11 TIMOUT Timer Output 24 2 read-write 00 Timer output is logic one when enabled and is not affected by timer reset #00 01 Timer output is logic zero when enabled and is not affected by timer reset #01 10 Timer output is logic one when enabled and on timer reset #10 11 Timer output is logic zero when enabled and on timer reset #11 8 0x4 0,1,2,3,4,5,6,7 TIMCMP%s Timer Compare N Register 0x500 32 read-write 0 0xFFFFFFFF CMP Timer Compare Value 0 16 read-write 8 0x4 0,1,2,3,4,5,6,7 SHIFTBUFNBS%s Shifter Buffer N Nibble Byte Swapped Register 0x680 32 read-write 0 0xFFFFFFFF SHIFTBUFNBS Shift Buffer 0 32 read-write 8 0x4 0,1,2,3,4,5,6,7 SHIFTBUFHWS%s Shifter Buffer N Half Word Swapped Register 0x700 32 read-write 0 0xFFFFFFFF SHIFTBUFHWS Shift Buffer 0 32 read-write 8 0x4 0,1,2,3,4,5,6,7 SHIFTBUFNIS%s Shifter Buffer N Nibble Swapped Register 0x780 32 read-write 0 0xFFFFFFFF SHIFTBUFNIS Shift Buffer 0 32 read-write GPIOA General Purpose Input/Output GPIO GPIOA_ 0x400FF000 0 0x18 registers PORTA 59 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOB General Purpose Input/Output GPIO GPIOB_ 0x400FF040 0 0x18 registers PORTB 60 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOC General Purpose Input/Output GPIO GPIOC_ 0x400FF080 0 0x18 registers PORTC 61 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOD General Purpose Input/Output GPIO GPIOD_ 0x400FF0C0 0 0x18 registers PORTD 62 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOE General Purpose Input/Output GPIO GPIOE_ 0x400FF100 0 0x18 registers PORTE 63 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 MCM Core Platform Miscellaneous Control Module MCM_ 0xE0080000 0x8 0x3C registers MCM 17 PLASC Crossbar Switch (AXBS) Slave Configuration 0x8 16 read-only 0x3F 0xFFFF ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0 8 read-only 0 A bus slave connection to AXBS input port n is absent #0 1 A bus slave connection to AXBS input port n is present #1 PLAMC Crossbar Switch (AXBS) Master Configuration 0xA 16 read-only 0x1F 0xFFFF AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 8 read-only 0 A bus master connection to AXBS input port n is absent #0 1 A bus master connection to AXBS input port n is present #1 CR Control Register 0xC 32 read-write 0 0xFFFFFFFF SRAMUAP SRAM_U arbitration priority 24 2 read-write 00 Round robin #00 01 Special round robin (favors SRAM backoor accesses over the processor) #01 10 Fixed priority. Processor has highest, backdoor has lowest #10 11 Fixed priority. Backdoor has highest, processor has lowest #11 SRAMUWP SRAM_U write protect 26 1 read-write SRAMLAP SRAM_L arbitration priority 28 2 read-write 00 Round robin #00 01 Special round robin (favors SRAM backoor accesses over the processor) #01 10 Fixed priority. Processor has highest, backdoor has lowest #10 11 Fixed priority. Backdoor has highest, processor has lowest #11 SRAMLWP SRAM_L Write Protect 30 1 read-write ISCR Interrupt Status Register 0x10 32 read-write 0 0xFFFFFFFF FIOC FPU invalid operation interrupt status 8 1 read-only 0 No interrupt #0 1 Interrupt occurred #1 FDZC FPU divide-by-zero interrupt status 9 1 read-only 0 No interrupt #0 1 Interrupt occurred #1 FOFC FPU overflow interrupt status 10 1 read-only 0 No interrupt #0 1 Interrupt occurred #1 FUFC FPU underflow interrupt status 11 1 read-only 0 No interrupt #0 1 Interrupt occurred #1 FIXC FPU inexact interrupt status 12 1 read-only 0 No interrupt #0 1 Interrupt occurred #1 FIDC FPU input denormal interrupt status 15 1 read-only 0 No interrupt #0 1 Interrupt occurred #1 FIOCE FPU invalid operation interrupt enable 24 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FDZCE FPU divide-by-zero interrupt enable 25 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FOFCE FPU overflow interrupt enable 26 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FUFCE FPU underflow interrupt enable 27 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FIXCE FPU inexact interrupt enable 28 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FIDCE FPU input denormal interrupt enable 31 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FADR Fault address register 0x20 32 read-only 0 0 ADDRESS Fault address 0 32 read-only FATR Fault attributes register 0x24 32 read-only 0 0 BEDA Bus error access type 0 1 read-only 0 Instruction #0 1 Data #1 BEMD Bus error privilege level 1 1 read-only 0 User mode #0 1 Supervisor/privileged mode #1 BESZ Bus error size 4 2 read-only 00 8-bit access #00 01 16-bit access #01 10 32-bit access #10 BEWT Bus error write 7 1 read-only 0 Read access #0 1 Write access #1 BEMN Bus error master number 8 4 read-only BEOVR Bus error overrun 31 1 read-only 0 No bus error overrun #0 1 Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to reflect this new bus error. #1 FDR Fault data register 0x28 32 read-only 0 0 DATA Fault data 0 32 read-only PID Process ID register 0x30 32 read-write 0 0xFFFFFFFF PID M0_PID And M1_PID For MPU 0 8 read-write CPO Compute Operation Control Register 0x40 32 read-write 0 0xFFFFFFFF CPOREQ Compute Operation request 0 1 read-write 0 Request is cleared. #0 1 Request Compute Operation. #1 CPOACK Compute Operation acknowledge 1 1 read-only 0 Compute operation entry has not completed or compute operation exit has completed. #0 1 Compute operation entry has completed or compute operation exit has not completed. #1 CPOWOI Compute Operation wakeup on interrupt 2 1 read-write 0 No effect. #0 1 When set, the CPOREQ is cleared on any interrupt or exception vector fetch. #1 CAU Memory Mapped Cryptographic Acceleration Unit (MMCAU) 0xE0081000 0 0xB6C registers CAU_DIRECT0 Direct access register 0 0 32 write-only 0 0xFFFFFFFF CAU_DIRECT0 Direct register 0 0 32 write-only CAU_DIRECT1 Direct access register 1 0x4 32 write-only 0 0xFFFFFFFF CAU_DIRECT1 Direct register 1 0 32 write-only CAU_DIRECT2 Direct access register 2 0x8 32 write-only 0 0xFFFFFFFF CAU_DIRECT2 Direct register 2 0 32 write-only CAU_DIRECT3 Direct access register 3 0xC 32 write-only 0 0xFFFFFFFF CAU_DIRECT3 Direct register 3 0 32 write-only CAU_DIRECT4 Direct access register 4 0x10 32 write-only 0 0xFFFFFFFF CAU_DIRECT4 Direct register 4 0 32 write-only CAU_DIRECT5 Direct access register 5 0x14 32 write-only 0 0xFFFFFFFF CAU_DIRECT5 Direct register 5 0 32 write-only CAU_DIRECT6 Direct access register 6 0x18 32 write-only 0 0xFFFFFFFF CAU_DIRECT6 Direct register 6 0 32 write-only CAU_DIRECT7 Direct access register 7 0x1C 32 write-only 0 0xFFFFFFFF CAU_DIRECT7 Direct register 7 0 32 write-only CAU_DIRECT8 Direct access register 8 0x20 32 write-only 0 0xFFFFFFFF CAU_DIRECT8 Direct register 8 0 32 write-only CAU_DIRECT9 Direct access register 9 0x24 32 write-only 0 0xFFFFFFFF CAU_DIRECT9 Direct register 9 0 32 write-only CAU_DIRECT10 Direct access register 10 0x28 32 write-only 0 0xFFFFFFFF CAU_DIRECT10 Direct register 10 0 32 write-only CAU_DIRECT11 Direct access register 11 0x2C 32 write-only 0 0xFFFFFFFF CAU_DIRECT11 Direct register 11 0 32 write-only CAU_DIRECT12 Direct access register 12 0x30 32 write-only 0 0xFFFFFFFF CAU_DIRECT12 Direct register 12 0 32 write-only CAU_DIRECT13 Direct access register 13 0x34 32 write-only 0 0xFFFFFFFF CAU_DIRECT13 Direct register 13 0 32 write-only CAU_DIRECT14 Direct access register 14 0x38 32 write-only 0 0xFFFFFFFF CAU_DIRECT14 Direct register 14 0 32 write-only CAU_DIRECT15 Direct access register 15 0x3C 32 write-only 0 0xFFFFFFFF CAU_DIRECT15 Direct register 15 0 32 write-only CAU_LDR_CASR Status register - Load Register command 0x840 32 write-only 0x20000000 0xFFFFFFFF IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 CAU_LDR_CAA Accumulator register - Load Register command 0x844 32 write-only 0 0xFFFFFFFF ACC ACC 0 32 write-only CAU_LDR_CA0 General Purpose Register 0 - Load Register command 0x848 32 write-only 0 0xFFFFFFFF CA0 CA0 0 32 write-only CAU_LDR_CA1 General Purpose Register 1 - Load Register command 0x84C 32 write-only 0 0xFFFFFFFF CA1 CA1 0 32 write-only CAU_LDR_CA2 General Purpose Register 2 - Load Register command 0x850 32 write-only 0 0xFFFFFFFF CA2 CA2 0 32 write-only CAU_LDR_CA3 General Purpose Register 3 - Load Register command 0x854 32 write-only 0 0xFFFFFFFF CA3 CA3 0 32 write-only CAU_LDR_CA4 General Purpose Register 4 - Load Register command 0x858 32 write-only 0 0xFFFFFFFF CA4 CA4 0 32 write-only CAU_LDR_CA5 General Purpose Register 5 - Load Register command 0x85C 32 write-only 0 0xFFFFFFFF CA5 CA5 0 32 write-only CAU_LDR_CA6 General Purpose Register 6 - Load Register command 0x860 32 write-only 0 0xFFFFFFFF CA6 CA6 0 32 write-only CAU_LDR_CA7 General Purpose Register 7 - Load Register command 0x864 32 write-only 0 0xFFFFFFFF CA7 CA7 0 32 write-only CAU_LDR_CA8 General Purpose Register 8 - Load Register command 0x868 32 write-only 0 0xFFFFFFFF CA8 CA8 0 32 write-only CAU_STR_CASR Status register - Store Register command 0x880 32 read-only 0x20000000 0xFFFFFFFF IC no description available 0 1 read-only 0 No illegal commands issued #0 1 Illegal command issued #1 DPE no description available 1 1 read-only 0 No error detected #0 1 DES key parity error detected #1 VER CAU version 28 4 read-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 CAU_STR_CAA Accumulator register - Store Register command 0x884 32 read-only 0 0xFFFFFFFF ACC ACC 0 32 read-only CAU_STR_CA0 General Purpose Register 0 - Store Register command 0x888 32 read-only 0 0xFFFFFFFF CA0 CA0 0 32 read-only CAU_STR_CA1 General Purpose Register 1 - Store Register command 0x88C 32 read-only 0 0xFFFFFFFF CA1 CA1 0 32 read-only CAU_STR_CA2 General Purpose Register 2 - Store Register command 0x890 32 read-only 0 0xFFFFFFFF CA2 CA2 0 32 read-only CAU_STR_CA3 General Purpose Register 3 - Store Register command 0x894 32 read-only 0 0xFFFFFFFF CA3 CA3 0 32 read-only CAU_STR_CA4 General Purpose Register 4 - Store Register command 0x898 32 read-only 0 0xFFFFFFFF CA4 CA4 0 32 read-only CAU_STR_CA5 General Purpose Register 5 - Store Register command 0x89C 32 read-only 0 0xFFFFFFFF CA5 CA5 0 32 read-only CAU_STR_CA6 General Purpose Register 6 - Store Register command 0x8A0 32 read-only 0 0xFFFFFFFF CA6 CA6 0 32 read-only CAU_STR_CA7 General Purpose Register 7 - Store Register command 0x8A4 32 read-only 0 0xFFFFFFFF CA7 CA7 0 32 read-only CAU_STR_CA8 General Purpose Register 8 - Store Register command 0x8A8 32 read-only 0 0xFFFFFFFF CA8 CA8 0 32 read-only CAU_ADR_CASR Status register - Add Register command 0x8C0 32 write-only 0x20000000 0xFFFFFFFF IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 CAU_ADR_CAA Accumulator register - Add to register command 0x8C4 32 write-only 0 0xFFFFFFFF ACC ACC 0 32 write-only CAU_ADR_CA0 General Purpose Register 0 - Add to register command 0x8C8 32 write-only 0 0xFFFFFFFF CA0 CA0 0 32 write-only CAU_ADR_CA1 General Purpose Register 1 - Add to register command 0x8CC 32 write-only 0 0xFFFFFFFF CA1 CA1 0 32 write-only CAU_ADR_CA2 General Purpose Register 2 - Add to register command 0x8D0 32 write-only 0 0xFFFFFFFF CA2 CA2 0 32 write-only CAU_ADR_CA3 General Purpose Register 3 - Add to register command 0x8D4 32 write-only 0 0xFFFFFFFF CA3 CA3 0 32 write-only CAU_ADR_CA4 General Purpose Register 4 - Add to register command 0x8D8 32 write-only 0 0xFFFFFFFF CA4 CA4 0 32 write-only CAU_ADR_CA5 General Purpose Register 5 - Add to register command 0x8DC 32 write-only 0 0xFFFFFFFF CA5 CA5 0 32 write-only CAU_ADR_CA6 General Purpose Register 6 - Add to register command 0x8E0 32 write-only 0 0xFFFFFFFF CA6 CA6 0 32 write-only CAU_ADR_CA7 General Purpose Register 7 - Add to register command 0x8E4 32 write-only 0 0xFFFFFFFF CA7 CA7 0 32 write-only CAU_ADR_CA8 General Purpose Register 8 - Add to register command 0x8E8 32 write-only 0 0xFFFFFFFF CA8 CA8 0 32 write-only CAU_RADR_CASR Status register - Reverse and Add to Register command 0x900 32 write-only 0x20000000 0xFFFFFFFF IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 CAU_RADR_CAA Accumulator register - Reverse and Add to Register command 0x904 32 write-only 0 0xFFFFFFFF ACC ACC 0 32 write-only CAU_RADR_CA0 General Purpose Register 0 - Reverse and Add to Register command 0x908 32 write-only 0 0xFFFFFFFF CA0 CA0 0 32 write-only CAU_RADR_CA1 General Purpose Register 1 - Reverse and Add to Register command 0x90C 32 write-only 0 0xFFFFFFFF CA1 CA1 0 32 write-only CAU_RADR_CA2 General Purpose Register 2 - Reverse and Add to Register command 0x910 32 write-only 0 0xFFFFFFFF CA2 CA2 0 32 write-only CAU_RADR_CA3 General Purpose Register 3 - Reverse and Add to Register command 0x914 32 write-only 0 0xFFFFFFFF CA3 CA3 0 32 write-only CAU_RADR_CA4 General Purpose Register 4 - Reverse and Add to Register command 0x918 32 write-only 0 0xFFFFFFFF CA4 CA4 0 32 write-only CAU_RADR_CA5 General Purpose Register 5 - Reverse and Add to Register command 0x91C 32 write-only 0 0xFFFFFFFF CA5 CA5 0 32 write-only CAU_RADR_CA6 General Purpose Register 6 - Reverse and Add to Register command 0x920 32 write-only 0 0xFFFFFFFF CA6 CA6 0 32 write-only CAU_RADR_CA7 General Purpose Register 7 - Reverse and Add to Register command 0x924 32 write-only 0 0xFFFFFFFF CA7 CA7 0 32 write-only CAU_RADR_CA8 General Purpose Register 8 - Reverse and Add to Register command 0x928 32 write-only 0 0xFFFFFFFF CA8 CA8 0 32 write-only CAU_XOR_CASR Status register - Exclusive Or command 0x980 32 write-only 0x20000000 0xFFFFFFFF IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 CAU_XOR_CAA Accumulator register - Exclusive Or command 0x984 32 write-only 0 0xFFFFFFFF ACC ACC 0 32 write-only CAU_XOR_CA0 General Purpose Register 0 - Exclusive Or command 0x988 32 write-only 0 0xFFFFFFFF CA0 CA0 0 32 write-only CAU_XOR_CA1 General Purpose Register 1 - Exclusive Or command 0x98C 32 write-only 0 0xFFFFFFFF CA1 CA1 0 32 write-only CAU_XOR_CA2 General Purpose Register 2 - Exclusive Or command 0x990 32 write-only 0 0xFFFFFFFF CA2 CA2 0 32 write-only CAU_XOR_CA3 General Purpose Register 3 - Exclusive Or command 0x994 32 write-only 0 0xFFFFFFFF CA3 CA3 0 32 write-only CAU_XOR_CA4 General Purpose Register 4 - Exclusive Or command 0x998 32 write-only 0 0xFFFFFFFF CA4 CA4 0 32 write-only CAU_XOR_CA5 General Purpose Register 5 - Exclusive Or command 0x99C 32 write-only 0 0xFFFFFFFF CA5 CA5 0 32 write-only CAU_XOR_CA6 General Purpose Register 6 - Exclusive Or command 0x9A0 32 write-only 0 0xFFFFFFFF CA6 CA6 0 32 write-only CAU_XOR_CA7 General Purpose Register 7 - Exclusive Or command 0x9A4 32 write-only 0 0xFFFFFFFF CA7 CA7 0 32 write-only CAU_XOR_CA8 General Purpose Register 8 - Exclusive Or command 0x9A8 32 write-only 0 0xFFFFFFFF CA8 CA8 0 32 write-only CAU_ROTL_CASR Status register - Rotate Left command 0x9C0 32 write-only 0x20000000 0xFFFFFFFF IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 CAU_ROTL_CAA Accumulator register - Rotate Left command 0x9C4 32 write-only 0 0xFFFFFFFF ACC ACC 0 32 write-only CAU_ROTL_CA0 General Purpose Register 0 - Rotate Left command 0x9C8 32 write-only 0 0xFFFFFFFF CA0 CA0 0 32 write-only CAU_ROTL_CA1 General Purpose Register 1 - Rotate Left command 0x9CC 32 write-only 0 0xFFFFFFFF CA1 CA1 0 32 write-only CAU_ROTL_CA2 General Purpose Register 2 - Rotate Left command 0x9D0 32 write-only 0 0xFFFFFFFF CA2 CA2 0 32 write-only CAU_ROTL_CA3 General Purpose Register 3 - Rotate Left command 0x9D4 32 write-only 0 0xFFFFFFFF CA3 CA3 0 32 write-only CAU_ROTL_CA4 General Purpose Register 4 - Rotate Left command 0x9D8 32 write-only 0 0xFFFFFFFF CA4 CA4 0 32 write-only CAU_ROTL_CA5 General Purpose Register 5 - Rotate Left command 0x9DC 32 write-only 0 0xFFFFFFFF CA5 CA5 0 32 write-only CAU_ROTL_CA6 General Purpose Register 6 - Rotate Left command 0x9E0 32 write-only 0 0xFFFFFFFF CA6 CA6 0 32 write-only CAU_ROTL_CA7 General Purpose Register 7 - Rotate Left command 0x9E4 32 write-only 0 0xFFFFFFFF CA7 CA7 0 32 write-only CAU_ROTL_CA8 General Purpose Register 8 - Rotate Left command 0x9E8 32 write-only 0 0xFFFFFFFF CA8 CA8 0 32 write-only CAU_AESC_CASR Status register - AES Column Operation command 0xB00 32 write-only 0x20000000 0xFFFFFFFF IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 CAU_AESC_CAA Accumulator register - AES Column Operation command 0xB04 32 write-only 0 0xFFFFFFFF ACC ACC 0 32 write-only CAU_AESC_CA0 General Purpose Register 0 - AES Column Operation command 0xB08 32 write-only 0 0xFFFFFFFF CA0 CA0 0 32 write-only CAU_AESC_CA1 General Purpose Register 1 - AES Column Operation command 0xB0C 32 write-only 0 0xFFFFFFFF CA1 CA1 0 32 write-only CAU_AESC_CA2 General Purpose Register 2 - AES Column Operation command 0xB10 32 write-only 0 0xFFFFFFFF CA2 CA2 0 32 write-only CAU_AESC_CA3 General Purpose Register 3 - AES Column Operation command 0xB14 32 write-only 0 0xFFFFFFFF CA3 CA3 0 32 write-only CAU_AESC_CA4 General Purpose Register 4 - AES Column Operation command 0xB18 32 write-only 0 0xFFFFFFFF CA4 CA4 0 32 write-only CAU_AESC_CA5 General Purpose Register 5 - AES Column Operation command 0xB1C 32 write-only 0 0xFFFFFFFF CA5 CA5 0 32 write-only CAU_AESC_CA6 General Purpose Register 6 - AES Column Operation command 0xB20 32 write-only 0 0xFFFFFFFF CA6 CA6 0 32 write-only CAU_AESC_CA7 General Purpose Register 7 - AES Column Operation command 0xB24 32 write-only 0 0xFFFFFFFF CA7 CA7 0 32 write-only CAU_AESC_CA8 General Purpose Register 8 - AES Column Operation command 0xB28 32 write-only 0 0xFFFFFFFF CA8 CA8 0 32 write-only CAU_AESIC_CASR Status register - AES Inverse Column Operation command 0xB40 32 write-only 0x20000000 0xFFFFFFFF IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 CAU_AESIC_CAA Accumulator register - AES Inverse Column Operation command 0xB44 32 write-only 0 0xFFFFFFFF ACC ACC 0 32 write-only CAU_AESIC_CA0 General Purpose Register 0 - AES Inverse Column Operation command 0xB48 32 write-only 0 0xFFFFFFFF CA0 CA0 0 32 write-only CAU_AESIC_CA1 General Purpose Register 1 - AES Inverse Column Operation command 0xB4C 32 write-only 0 0xFFFFFFFF CA1 CA1 0 32 write-only CAU_AESIC_CA2 General Purpose Register 2 - AES Inverse Column Operation command 0xB50 32 write-only 0 0xFFFFFFFF CA2 CA2 0 32 write-only CAU_AESIC_CA3 General Purpose Register 3 - AES Inverse Column Operation command 0xB54 32 write-only 0 0xFFFFFFFF CA3 CA3 0 32 write-only CAU_AESIC_CA4 General Purpose Register 4 - AES Inverse Column Operation command 0xB58 32 write-only 0 0xFFFFFFFF CA4 CA4 0 32 write-only CAU_AESIC_CA5 General Purpose Register 5 - AES Inverse Column Operation command 0xB5C 32 write-only 0 0xFFFFFFFF CA5 CA5 0 32 write-only CAU_AESIC_CA6 General Purpose Register 6 - AES Inverse Column Operation command 0xB60 32 write-only 0 0xFFFFFFFF CA6 CA6 0 32 write-only CAU_AESIC_CA7 General Purpose Register 7 - AES Inverse Column Operation command 0xB64 32 write-only 0 0xFFFFFFFF CA7 CA7 0 32 write-only CAU_AESIC_CA8 General Purpose Register 8 - AES Inverse Column Operation command 0xB68 32 write-only 0 0xFFFFFFFF CA8 CA8 0 32 write-only LMEM Local Memory Controller LMEM_ 0xE0082000 0 0x824 registers PCCCR Cache control register 0 32 read-write 0 0xFFFFFFFF ENCACHE Cache enable 0 1 read-write 0 Cache disabled #0 1 Cache enabled #1 ENWRBUF Enable Write Buffer 1 1 read-write 0 Write buffer disabled #0 1 Write buffer enabled #1 PCCR2 Forces all cacheable spaces to write through 2 1 read-write PCCR3 Forces no allocation on cache misses (must also have PCCR2 asserted) 3 1 read-write INVW0 Invalidate Way 0 24 1 read-write 0 No operation #0 1 When setting the GO bit, invalidate all lines in way 0. #1 PUSHW0 Push Way 0 25 1 read-write 0 No operation #0 1 When setting the GO bit, push all modified lines in way 0 #1 INVW1 Invalidate Way 1 26 1 read-write 0 No operation #0 1 When setting the GO bit, invalidate all lines in way 1 #1 PUSHW1 Push Way 1 27 1 read-write 0 No operation #0 1 When setting the GO bit, push all modified lines in way 1 #1 GO Initiate Cache Command 31 1 read-write 0 Write: no effect. Read: no cache command active. #0 1 Write: initiate command indicated by bits 27-24. Read: cache command active. #1 PCCLCR Cache line control register 0x4 32 read-write 0 0xFFFFFFFF LGO Initiate Cache Line Command 0 1 read-write 0 Write: no effect. Read: no line command active. #0 1 Write: initiate line command indicated by bits 27-24. Read: line command active. #1 CACHEADDR Cache address 2 10 read-write WSEL Way select 14 1 read-write 0 Way 0 #0 1 Way 1 #1 TDSEL Tag/Data Select 16 1 read-write 0 Data #0 1 Tag #1 LCIVB Line Command Initial Valid Bit 20 1 read-only LCIMB Line Command Initial Modified Bit 21 1 read-only LCWAY Line Command Way 22 1 read-only LCMD Line Command 24 2 read-write 00 Search and read or write #00 01 Invalidate #01 10 Push #10 11 Clear #11 LADSEL Line Address Select 26 1 read-write 0 Cache address #0 1 Physical address #1 LACC Line access type 27 1 read-write 0 Read #0 1 Write #1 PCCSAR Cache search address register 0x8 32 read-write 0 0xFFFFFFFF LGO Initiate Cache Line Command 0 1 read-write 0 Write: no effect. Read: no line command active. #0 1 Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active. #1 PHYADDR Physical Address 2 30 read-write PCCCVR Cache read/write value register 0xC 32 read-write 0 0xFFFFFFFF DATA Cache read/write Data 0 32 read-write PCCRMR Cache regions mode register 0x20 32 read-write 0xAA0FA000 0xFFFFFFFF R15 Region 15 mode 0 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R14 Region 14 mode 2 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R13 Region 13 mode 4 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R12 Region 12 mode 6 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R11 Region 11 mode 8 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R10 Region 10 mode 10 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R9 Region 9 mode 12 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R8 Region 8 mode 14 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R7 Region 7 mode 16 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R6 Region 6 mode 18 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R5 Region 5 mode 20 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R4 Region 4 mode 22 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R3 Region 3 mode 24 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R2 Region 2 mode 26 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R1 Region 1 mode 28 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R0 Region 0 mode 30 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 PSCCR Cache control register 0x800 32 read-write 0 0xFFFFFFFF ENCACHE Cache enable 0 1 read-write 0 Cache disabled #0 1 Cache enabled #1 ENWRBUF Enable Write Buffer 1 1 read-write 0 Write buffer disabled #0 1 Write buffer enabled #1 INVW0 Invalidate Way 0 24 1 read-write 0 No operation #0 1 When setting the GO bit, invalidate all lines in way 0. #1 PUSHW0 Push Way 0 25 1 read-write 0 No operation #0 1 When setting the GO bit, push all modified lines in way 0 #1 INVW1 Invalidate Way 1 26 1 read-write 0 No operation #0 1 When setting the GO bit, invalidate all lines in way 1 #1 PUSHW1 Push Way 1 27 1 read-write 0 No operation #0 1 When setting the GO bit, push all modified lines in way 1 #1 GO Initiate Cache Command 31 1 read-write 0 Write: no effect. Read: no cache command active. #0 1 Write: initiate command indicated by bits 27-24. Read: cache command active. #1 PSCLCR Cache line control register 0x804 32 read-write 0 0xFFFFFFFF LGO Initiate Cache Line Command 0 1 read-write 0 Write: no effect. Read: no line command active. #0 1 Write: initiate line command indicated by bits 27-24. Read: line command active. #1 CACHEADDR Cache address 2 10 read-write WSEL Way select 14 1 read-write 0 Way 0 #0 1 Way 1 #1 TDSEL Tag/Data Select 16 1 read-write 0 Data #0 1 Tag #1 LCIVB Line Command Initial Valid Bit 20 1 read-only LCIMB Line Command Initial Modified Bit 21 1 read-only LCWAY Line Command Way 22 1 read-only LCMD Line Command 24 2 read-write 00 Search and read or write #00 01 Invalidate #01 10 Push #10 11 Clear #11 LADSEL Line Address Select 26 1 read-write 0 Cache address #0 1 Physical address #1 LACC Line access type 27 1 read-write 0 Read #0 1 Write #1 PSCSAR Cache search address register 0x808 32 read-write 0 0xFFFFFFFF LGO Initiate Cache Line Command 0 1 read-write 0 Write: no effect. Read: no line command active. #0 1 Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active. #1 PHYADDR Physical Address 2 30 read-write PSCCVR Cache read/write value register 0x80C 32 read-write 0 0xFFFFFFFF DATA Cache read/write Data 0 32 read-write PSCRMR Cache regions mode register 0x820 32 read-write 0xAA0FA000 0xFFFFFFFF R15 Region 15 mode 0 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R14 Region 14 mode 2 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R13 Region 13 mode 4 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R12 Region 12 mode 6 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R11 Region 11 mode 8 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R10 Region 10 mode 10 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R9 Region 9 mode 12 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R8 Region 8 mode 14 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R7 Region 7 mode 16 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R6 Region 6 mode 18 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R5 Region 5 mode 20 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R4 Region 4 mode 22 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R3 Region 3 mode 24 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R2 Region 2 mode 26 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R1 Region 1 mode 28 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R0 Region 0 mode 30 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11