ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. ESPRESSIF ESP32-S2-ULP RISC-V ULP 1 32-bit RISC-V MCU Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. RV32IMC r0p0 little false false 4 false 32 32 0x00000000 0xFFFFFFFF RTC_IO Low-power Input/Output RTCIO 0x0000A400 0x0 0xF0 registers RTC_GPIO_OUT RTC GPIO output register 0x0 0x20 GPIO_OUT_DATA GPIO0 ~ 21 output register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. 10 22 read-write RTC_GPIO_OUT_W1TS RTC GPIO output bit set register 0x4 0x20 GPIO_OUT_DATA_W1TS GPIO0 ~ 21 output set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_OUT_REG. 10 22 write-only RTC_GPIO_OUT_W1TC RTC GPIO output bit clear register 0x8 0x20 GPIO_OUT_DATA_W1TC GPIO0 ~ 21 output clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_OUT_REG. 10 22 write-only RTC_GPIO_ENABLE RTC GPIO output enable register 0xC 0x20 REG_RTCIO_REG_GPIO_ENABLE GPIO0 ~ 21 output enable. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. If the bit is set to 1, it means this GPIO pad is output. 10 22 read-write RTC_GPIO_ENABLE_W1TS RTC GPIO output enable bit set register 0x10 0x20 REG_RTCIO_REG_GPIO_ENABLE_W1TS GPIO0 ~ 21 output enable set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_ENABLE_REG. 10 22 write-only RTC_GPIO_ENABLE_W1TC RTC GPIO output enable bit clear register 0x14 0x20 REG_RTCIO_REG_GPIO_ENABLE_W1TC GPIO0 ~ 21 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_ENABLE_REG. 10 22 write-only RTC_GPIO_STATUS RTC GPIO interrupt status register 0x18 0x20 GPIO_STATUS_INT GPIO0 ~ 21 interrupt status register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. This register should be used together with RTCIO_RTC_GPIO_PINn_INT_TYPE in RTCIO_RTC_GPIO_PINn_REG. 0: no interrupt; 1: corresponding interrupt. 10 22 read-write RTC_GPIO_STATUS_W1TS RTC GPIO interrupt status bit set register 0x1C 0x20 GPIO_STATUS_INT_W1TS GPIO0 ~ 21 interrupt set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be set to 1. Recommended operation: use this register to set RTCIO_GPIO_STATUS_INT. 10 22 write-only RTC_GPIO_STATUS_W1TC RTC GPIO interrupt status bit clear register 0x20 0x20 GPIO_STATUS_INT_W1TC GPIO0 ~ 21 interrupt clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be cleared. Recommended operation: use this register to clear RTCIO_GPIO_STATUS_INT. 10 22 write-only RTC_GPIO_IN RTC GPIO input register 0x24 0x20 GPIO_IN_NEXT GPIO0 ~ 21 input value. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. Each bit represents a pad input value, 1 for high level, and 0 for low level. 10 22 read-only 22 0x4 RTC_GPIO_PIN%s RTC configuration for pin %s 0x28 0x20 GPIO_PIN_PAD_DRIVER Pad driver selection. 0: normal output. 1: open drain. 2 1 read-write GPIO_PIN_INT_TYPE GPIO interrupt type selection. 0: GPIO interrupt disabled. 1: rising edge trigger. 2: falling edge trigger. 3: any edge trigger. 4: low level trigger. 5: high level trigger. 7 3 read-write GPIO_PIN_WAKEUP_ENABLE GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. 10 1 read-write RTC_DEBUG_SEL RTC debug select register 0x80 0x20 RTC_DEBUG_SEL0 0 5 read-write RTC_DEBUG_SEL1 5 5 read-write RTC_DEBUG_SEL2 10 5 read-write RTC_DEBUG_SEL3 15 5 read-write RTC_DEBUG_SEL4 20 5 read-write RTC_DEBUG_12M_NO_GATING 25 1 read-write 15 0x4 TOUCH_PAD%s Touch pad %s configuration register 0x84 0x20 0x52000000 FUN_IE Input enable in normal execution. 13 1 read-write SLP_OE Output enable in sleep mode. 14 1 read-write SLP_IE Input enable in sleep mode. 15 1 read-write SLP_SEL 0: no sleep mode. 1: enable sleep mode. 16 1 read-write FUN_SEL Function selection. 17 2 read-write MUX_SEL Connect the RTC pad input to digital pad input. 0 is available. 19 1 read-write XPD Touch sensor power on. 20 1 read-write TIE_OPT The tie option of touch sensor. 0: tie low. 1: tie high. 21 1 read-write START Start touch sensor. 22 1 read-write DAC Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. 23 3 read-write RUE Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 27 1 read-write RDE Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 28 1 read-write DRV Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 29 2 read-write XTAL_32P_PAD 32KHz crystal P-pad configuration register 0xC0 0x20 0x40000000 X32P_FUN_IE Input enable in normal execution. 13 1 read-write X32P_SLP_OE output enable in sleep mode. 14 1 read-write X32P_SLP_IE input enable in sleep mode. 15 1 read-write X32P_SLP_SEL 1: enable sleep mode. 0: no sleep mode. 16 1 read-write X32P_FUN_SEL Function selection. 17 2 read-write X32P_MUX_SEL 1: use RTC GPIO. 0: use digital GPIO. 19 1 read-write X32P_RUE Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 27 1 read-write X32P_RDE Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 28 1 read-write X32P_DRV Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 29 2 read-write XTAL_32N_PAD 32KHz crystal N-pad configuration register 0xC4 0x20 0x40000000 X32N_FUN_IE Input enable in normal execution. 13 1 read-write X32N_SLP_OE Output enable in sleep mode. 14 1 read-write X32N_SLP_IE Input enable in sleep mode. 15 1 read-write X32N_SLP_SEL 1: enable sleep mode. 0: no sleep mode. 16 1 read-write X32N_FUN_SEL Function selection. 17 2 read-write X32N_MUX_SEL 1: use RTC GPIO. 0: use digital GPIO. 19 1 read-write X32N_RUE Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 27 1 read-write X32N_RDE Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 28 1 read-write X32N_DRV Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 29 2 read-write PAD_DAC1 DAC1 configuration register 0xC8 0x20 0x40000000 PDAC1_DAC Configure DAC_1 output when RTCIO_PDAC1_DAC_XPD_FORCE is set to 1. 3 8 read-write PDAC1_XPD_DAC When RTCIO_PDAC1_DAC_XPD_FORCE is set to 1, 1: enable DAC_1 output. 0: disable DAC_1 output. 11 1 read-write PDAC1_DAC_XPD_FORCE 1: use RTCIO_PDAC1_XPD_DAC to control DAC_1 output. 0: use SAR ADC FSM to control DAC_1 output. 12 1 read-write PDAC1_FUN_IE Input enable in normal execution. 13 1 read-write PDAC1_SLP_OE Output enable in sleep mode 14 1 read-write PDAC1_SLP_IE Input enable in sleep mode 15 1 read-write PDAC1_SLP_SEL 1: enable sleep mode. 0: no sleep mode 16 1 read-write PDAC1_FUN_SEL DAC_1 function selection. 17 2 read-write PDAC1_MUX_SEL 1: use RTC GPIO. 0: use digital GPIO 19 1 read-write PDAC1_RUE Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 27 1 read-write PDAC1_RDE Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 28 1 read-write PDAC1_DRV Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 29 2 read-write PAD_DAC2 DAC2 configuration register 0xCC 0x20 0x40000000 PDAC2_DAC Configure DAC_2 output when RTCIO_PDAC2_DAC_XPD_FORCE is set to 1. 3 8 read-write PDAC2_XPD_DAC When RTCIO_PDAC2_DAC_XPD_FORCE is set to 1, 1: enable DAC_2 output. 0: disable DAC_2 output. 11 1 read-write PDAC2_DAC_XPD_FORCE 1: use RTCIO_PDAC2_XPD_DAC to control DAC_2 output. 0: use SAR ADC FSM to control DAC_2 output. 12 1 read-write PDAC2_FUN_IE Input enable in normal execution. 13 1 read-write PDAC2_SLP_OE Output enable in sleep mode. 14 1 read-write PDAC2_SLP_IE Input enable in sleep mode. 15 1 read-write PDAC2_SLP_SEL 1: enable sleep mode. 0: no sleep mode. 16 1 read-write PDAC2_FUN_SEL DAC_2 function selection. 17 2 read-write PDAC2_MUX_SEL 1: use RTC GPIO. 0: use digital GPIO. 19 1 read-write PDAC2_RUE Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 27 1 read-write PDAC2_RDE Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 28 1 read-write PDAC2_DRV Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 29 2 read-write RTC_PAD19 Touch pad 19 configuration register 0xD0 0x20 0x50000000 FUN_IE Input enable in normal execution. 13 1 read-write SLP_OE Output enable in sleep mode. 14 1 read-write SLP_IE Input enable in sleep mode. 15 1 read-write SLP_SEL 1: enable sleep mode. 0: no sleep mode 16 1 read-write FUN_SEL Function selection. 17 2 read-write MUX_SEL 1: use RTC GPIO. 0: use digital GPIO. 19 1 read-write RUE Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 27 1 read-write RDE Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 28 1 read-write DRV Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 29 2 read-write RTC_PAD20 Touch pad 20 configuration register 0xD4 0x20 0x50000000 FUN_IE Input enable in normal execution. 13 1 read-write SLP_OE Output enable in sleep mode. 14 1 read-write SLP_IE Input enable in sleep mode. 15 1 read-write SLP_SEL 1: enable sleep mode. 0: no sleep mode. 16 1 read-write FUN_SEL Function selection. 17 2 read-write MUX_SEL 1: use RTC GPIO. 0: use digital GPIO. 19 1 read-write RUE Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 27 1 read-write RDE Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 28 1 read-write DRV Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 29 2 read-write RTC_PAD21 Touch pad 21 configuration register 0xD8 0x20 0x50000000 FUN_IE Input enable in normal execution. 13 1 read-write SLP_OE Output enable in sleep mode. 14 1 read-write SLP_IE Input enable in sleep mode. 15 1 read-write SLP_SEL 1: enable sleep mode. 0: no sleep mode. 16 1 read-write FUN_SEL Function selection. 17 2 read-write MUX_SEL 1: use RTC GPIO. 0: use digital GPIO. 19 1 read-write RUE Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 27 1 read-write RDE Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 28 1 read-write DRV Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 29 2 read-write EXT_WAKEUP0 External wake up configuration register 0xDC 0x20 SEL GPIO[0-17] can be used to wake up the chip when the chip is in the sleep mode. This register prompts the pad source to wake up the chip when the latter is indeep/light sleep mode. 0: select GPIO0; 1: select GPIO2, etc 27 5 read-write XTL_EXT_CTR Crystal power down enable GPIO source 0xE0 0x20 SEL Select the external crystal power down enable source to get into sleep mode. 0: select GPIO0. 1: select GPIO1, etc. The input value on this pin XOR RTC_CNTL_EXT_XTL_CONF_REG[30] is the crystal power down enable signal. 27 5 read-write SAR_I2C_IO RTC I2C pad selection 0xE4 0x20 SAR_DEBUG_BIT_SEL 23 5 read-write SAR_I2C_SCL_SEL Selects a pad the RTC I2C SCL signal connects to. 0: use TOUCH PAD0. 1: use TOUCH PAD2. 28 2 read-write SAR_I2C_SDA_SEL Selects a pad the RTC I2C SDA signal connects to. 0: use TOUCH PAD1. 1: use TOUCH PAD3. 30 2 read-write RTC_IO_TOUCH_CTRL Touch control register 0xE8 0x20 IO_TOUCH_BUFSEL 0 4 read-write IO_TOUCH_BUFMODE 4 1 read-write RTC_IO_DATE Version control register 0x1FC 0x20 0x01903170 IO_DATE Version control register 0 28 read-write RTC_CNTL Real-Time Clock Control RTC_CNTL 0x00008000 0x0 0x138 registers RISCV_START_INT 6 SW_INT 7 SWD_INT 8 ULP_CP_TIMER Configure coprocessor timer 0xF8 0x20 ULP_CP_PC_INIT ULP coprocessor PC initial address 0 11 read-write ULP_CP_GPIO_WAKEUP_ENA Enable the option of ULP coprocessor woken up by RTC GPIO 29 1 read-write ULP_CP_GPIO_WAKEUP_CLR Disable the option of ULP coprocessor woken up by RTC GPIO 30 1 write-only ULP_CP_SLP_TIMER_EN ULP coprocessor timer enable bit. 0: Disable hardware Timer. 1: Enable hardware timer 31 1 read-write ULP_CP_CTRL ULP-FSM configuration register 0xFC 0x20 0x00100200 ULP_CP_MEM_ADDR_INIT 0 11 read-write ULP_CP_MEM_ADDR_SIZE 11 11 read-write ULP_CP_MEM_OFFSET_CLR 22 1 write-only ULP_CP_CLK_FO ULP-FSM clock force on 28 1 read-write ULP_CP_RESET ULP-FSM clock software reset 29 1 read-write ULP_CP_FORCE_START_TOP Write 1 to start ULP-FSM by software 30 1 read-write ULP_CP_START_TOP Write 1 to start ULP-FSM 31 1 read-write COCPU_CTRL ULP-RISCV configuration register 0x100 0x20 0x008A0810 COCPU_CLK_FO ULP-RISCV clock force on 0 1 read-write COCPU_START_2_RESET_DIS Time from ULP-RISCV startup to pull down reset 1 6 read-write COCPU_START_2_INTR_EN Time from ULP-RISCV startup to send out RISCV_START_INT interrupt 7 6 read-write COCPU_SHUT Shut down ULP-RISCV 13 1 read-write COCPU_SHUT_2_CLK_DIS Time from shut down ULP-RISCV to disable clock 14 8 read-write COCPU_SHUT_RESET_EN This bit is used to reset ULP-RISCV 22 1 read-write COCPU_SEL 0: select ULP-RISCV. 1: select ULP-FSM 23 1 read-write COCPU_DONE_FORCE 0: select ULP-FSM DONE signal. 1: select ULP-RISCV DONE signal 24 1 read-write COCPU_DONE DONE signal. Write 1 to this bit, ULP-RISCV will go to HALT and the timer starts counting 25 1 read-write COCPU_SW_INT_TRIGGER Trigger ULP-RISCV register interrupt 26 1 write-only ULP_CP_TIMER_1 Configure sleep cycle of the timer 0x130 0x20 0x0000C800 ULP_CP_TIMER_SLP_CYCLE Set sleep cycles for ULP coprocessor timer 8 24 read-write RTC_I2C Low-power I2C (Inter-Integrated Circuit) Controller RTC_I2C 0x0000EC00 0x0 0x7C registers SCL_LOW Configure the low level width of SCL 0x0 0x20 0x00000100 PERIOD This register is used to configure how many clock cycles SCL remains low. 0 20 read-write CTRL Transmission setting 0x4 0x20 SDA_FORCE_OUT SDA output mode. 0: open drain. 1: push pull. 0 1 read-write SCL_FORCE_OUT SCL output mode. 0: open drain. 1: push pull. 1 1 read-write MS_MODE Set this bit to configure RTC I²C as a master. 2 1 read-write TRANS_START Set this bit to 1, RTC I2C starts sending data. 3 1 read-write TX_LSB_FIRST This bit is used to control the sending mode. 0: send data from the most significant bit. 1: send data from the least significant bit. 4 1 read-write RX_LSB_FIRST This bit is used to control the storage mode for received data. 0: receive data from the most significant bit. 1: receive data from the least significant bit. 5 1 read-write CLK_GATE_EN RTC I²C controller clock gate. 29 1 read-write RESET RTC I²C software reset. 30 1 read-write CLK_EN rtc i2c reg clk gating 31 1 read-write STATUS RTC I2C status 0x8 0x20 ACK_REC The received ACK value. 0: ACK. 1: NACK. 0 1 read-only SLAVE_RW 0: master writes to slave. 1: master reads from slave. 1 1 read-only ARB_LOST When the RTC I2C loses control of SCL line, the register changes to 1. 2 1 read-only BUS_BUSY 0: RTC I2C bus is in idle state. 1: RTC I2C bus is busy transferring data. 3 1 read-only SLAVE_ADDRESSED When the address sent by the master matches the address of the slave, then this bit will be set. 4 1 read-only BYTE_TRANS This field changes to 1 when one byte is transferred. 5 1 read-only OP_CNT Indicate which operation is working. 6 2 read-only SHIFT shifter content 16 8 read-only SCL_MAIN_STATE_LAST i2c last main status 24 3 read-only SCL_STATE_LAST scl last status 28 3 read-only TO Configure RTC I2C timeout 0xC 0x20 0x00010000 TIME_OUT Timeout threshold 0 20 read-write SLAVE_ADDR Configure slave address 0x10 0x20 SLAVE_ADDR slave address 0 15 read-write ADDR_10BIT_EN This field is used to enable the slave 10-bit addressing mode. 31 1 read-write SCL_HIGH Configure the high level width of SCL 0x14 0x20 0x00000100 PERIOD This register is used to configure how many cycles SCL remains high. 0 20 read-write SDA_DUTY Configure the SDA hold time after a negative SCL edge 0x18 0x20 0x00000010 NUM The number of clock cycles between the SDA switch and the falling edge of SCL. 0 20 read-write SCL_START_PERIOD Configure the delay between the SDA and SCL negative edge for a start condition 0x1C 0x20 0x00000008 SCL_START_PERIOD Number of clock cycles to wait after generating a start condition. 0 20 read-write SCL_STOP_PERIOD Configure the delay between SDA and SCL positive edge for a stop condition 0x20 0x20 0x00000008 SCL_STOP_PERIOD Number of clock cycles to wait before generating a stop condition. 0 20 read-write INT_CLR Clear RTC I2C interrupt 0x24 0x20 SLAVE_TRAN_COMP_INT_CLR RTC_I2C_SLAVE_TRAN_COMP_INT interrupt clear bit 0 1 write-only ARBITRATION_LOST_INT_CLR RTC_I2C_ARBITRATION_LOST_INT interrupt clear bit 1 1 write-only MASTER_TRAN_COMP_INT_CLR RTC_I2C_MASTER_TRAN_COMP_INT interrupt clear bit 2 1 write-only TRANS_COMPLETE_INT_CLR RTC_I2C_TRANS_COMPLETE_INT interrupt clear bit 3 1 write-only TIME_OUT_INT_CLR RTC_I2C_TIME_OUT_INT interrupt clear bit 4 1 write-only ACK_ERR_INT_CLR RTC_I2C_ACK_ERR_INT interrupt clear bit 5 1 write-only RX_DATA_INT_CLR RTC_I2C_RX_DATA_INT interrupt clear bit 6 1 write-only TX_DATA_INT_CLR RTC_I2C_TX_DATA_INT interrupt clear bit 7 1 write-only DETECT_START_INT_CLR RTC_I2C_DETECT_START_INT interrupt clear bit 8 1 write-only INT_RAW RTC I2C raw interrupt 0x28 0x20 SLAVE_TRAN_COMP_INT_RAW RTC_I2C_SLAVE_TRAN_COMP_INT interrupt raw bit 0 1 read-only ARBITRATION_LOST_INT_RAW RTC_I2C_ARBITRATION_LOST_INT interrupt raw bit 1 1 read-only MASTER_TRAN_COMP_INT_RAW RTC_I2C_MASTER_TRAN_COMP_INT interrupt raw bit 2 1 read-only TRANS_COMPLETE_INT_RAW RTC_I2C_TRANS_COMPLETE_INT interrupt raw bit 3 1 read-only TIME_OUT_INT_RAW RTC_I2C_TIME_OUT_INT interrupt raw bit 4 1 read-only ACK_ERR_INT_RAW RTC_I2C_ACK_ERR_INT interrupt raw bit 5 1 read-only RX_DATA_INT_RAW RTC_I2C_RX_DATA_INT interrupt raw bit 6 1 read-only TX_DATA_INT_RAW RTC_I2C_TX_DATA_INT interrupt raw bit 7 1 read-only DETECT_START_INT_RAW RTC_I2C_DETECT_START_INT interrupt raw bit 8 1 read-only INT_ST RTC I2C interrupt status 0x2C 0x20 SLAVE_TRAN_COMP_INT_ST RTC_I2C_SLAVE_TRAN_COMP_INT interrupt status bit 0 1 read-only ARBITRATION_LOST_INT_ST RTC_I2C_ARBITRATION_LOST_INT interrupt status bit 1 1 read-only MASTER_TRAN_COMP_INT_ST RTC_I2C_MASTER_TRAN_COMP_INT interrupt status bit 2 1 read-only TRANS_COMPLETE_INT_ST RTC_I2C_TRANS_COMPLETE_INT interrupt status bit 3 1 read-only TIME_OUT_INT_ST RTC_I2C_TIME_OUT_INT interrupt status bit 4 1 read-only ACK_ERR_INT_ST RTC_I2C_ACK_ERR_INT interrupt status bit 5 1 read-only RX_DATA_INT_ST RTC_I2C_RX_DATA_INT interrupt status bit 6 1 read-only TX_DATA_INT_ST RTC_I2C_TX_DATA_INT interrupt status bit 7 1 read-only DETECT_START_INT_ST RTC_I2C_DETECT_START_INT interrupt status bit 8 1 read-only INT_ENA Enable RTC I2C interrupt 0x30 0x20 SLAVE_TRAN_COMP_INT_ENA RTC_I2C_SLAVE_TRAN_COMP_INT interrupt enable bit 0 1 read-write ARBITRATION_LOST_INT_ENA RTC_I2C_ARBITRATION_LOST_INT interrupt enable bit 1 1 read-write MASTER_TRAN_COMP_INT_ENA RTC_I2C_MASTER_TRAN_COMP_INT interrupt enable bit 2 1 read-write TRANS_COMPLETE_INT_ENA RTC_I2C_TRANS_COMPLETE_INT interrupt enable bit 3 1 read-write TIME_OUT_INT_ENA RTC_I2C_TIME_OUT_INT interrupt enable bit 4 1 read-write ACK_ERR_INT_ENA RTC_I2C_ACK_ERR_INT interrupt enable bit 5 1 read-write RX_DATA_INT_ENA RTC_I2C_RX_DATA_INT interrupt enable bit 6 1 read-write TX_DATA_INT_ENA RTC_I2C_TX_DATA_INT interrupt enable bit 7 1 read-write DETECT_START_INT_ENA RTC_I2C_DETECT_START_INT interrupt enable bit 8 1 read-write DATA RTC I2C read data 0x34 0x20 RDATA Data received 0 8 read-only SLAVE_TX_DATA The data sent by slave 8 8 read-write DONE RTC I2C transmission is done. 31 1 read-only CMD0 RTC I2C Command 0 0x38 0x20 0x00000903 COMMAND0 Content of command 0. For more information, please refer to the register I2C_COMD0_REG in Chapter I²C Controller 0 14 read-write COMMAND0_DONE When command 0 is done, this bit changes to 1. 31 1 read-only CMD1 RTC I2C Command 1 0x3C 0x20 0x00001901 COMMAND1 Content of command 1. For more information, please refer to the register I2C_COMD1_REG in Chapter I²C Controller. 0 14 read-write COMMAND1_DONE When command 1 is done, this bit changes to 1. 31 1 read-only CMD2 RTC I2C Command 2 0x40 0x20 0x00000902 COMMAND2 Content of command 2. For more information, please refer to the register I2C_COMD2_REG in Chapter I²C Controller. 0 14 read-write COMMAND2_DONE When command 2 is done, this bit changes to 1. 31 1 read-only CMD3 RTC I2C Command 3 0x44 0x20 0x00000101 COMMAND3 Content of command 3. For more information, please refer to the register I2C_COMD3_REG in Chapter I²C Controller. 0 14 read-write COMMAND3_DONE When command 3 is done, this bit changes to 1. 31 1 read-only CMD4 RTC I2C Command 4 0x48 0x20 0x00000901 COMMAND4 Content of command 4. For more information, please refer to the register I2C_COMD4_REG in Chapter I²C Controller. 0 14 read-write COMMAND4_DONE When command 4 is done, this bit changes to 1. 31 1 read-only CMD5 RTC I2C Command 5 0x4C 0x20 0x00001701 COMMAND5 Content of command 5. For more information, please refer to the register I2C_COMD5_REG in Chapter I²C Controller. 0 14 read-write COMMAND5_DONE When command 5 is done, this bit changes to 1. 31 1 read-only CMD6 RTC I2C Command 6 0x50 0x20 0x00001901 COMMAND6 Content of command 6. For more information, please refer to the register I2C_COMD6_REG in Chapter I²C Controller. 0 14 read-write COMMAND6_DONE When command 6 is done, this bit changes to 1. 31 1 read-only CMD7 RTC I2C Command 7 0x54 0x20 0x00000904 COMMAND7 Content of command 7. For more information, please refer to the register I2C_COMD7_REG in Chapter I²C Controller. 0 14 read-write COMMAND7_DONE When command 7 is done, this bit changes to 1. 31 1 read-only CMD8 RTC I2C Command 8 0x58 0x20 0x00001901 COMMAND8 Content of command 8. For more information, please refer to the register I2C_COMD8_REG in Chapter I²C Controller. 0 14 read-write COMMAND8_DONE When command 8 is done, this bit changes to 1. 31 1 read-only CMD9 RTC I2C Command 9 0x5C 0x20 0x00000903 COMMAND9 Content of command 9. For more information, please refer to the register I2C_COMD9_REG in Chapter I²C Controller 0 14 read-write COMMAND9_DONE When command 9 is done, this bit changes to 1. 31 1 read-only CMD10 RTC I2C Command 10 0x60 0x20 0x00000101 COMMAND10 Content of command 10. For more information, please refer to the register I2C_COMD10_REG in Chapter I²C Controller. 0 14 read-write COMMAND10_DONE When command 10 is done, this bit changes to 1. 31 1 read-only CMD11 RTC I2C Command 11 0x64 0x20 0x00000901 COMMAND11 Content of command 11. For more information, please refer to the register I2C_COMD11_REG in Chapter I²C Controller. 0 14 read-write COMMAND11_DONE When command 11 is done, this bit changes to 1. 31 1 read-only CMD12 RTC I2C Command 12 0x68 0x20 0x00001701 COMMAND12 Content of command 12. For more information, please refer to the register I2C_COMD12_REG in Chapter I²C Controller. 0 14 read-write COMMAND12_DONE When command 12 is done, this bit changes to 1. 31 1 read-only CMD13 RTC I2C Command 13 0x6C 0x20 0x00001901 COMMAND13 Content of command 13. For more information, please refer to the register I2C_COMD13_REG in Chapter I²C Controller. 0 14 read-write COMMAND13_DONE When command 13 is done, this bit changes to 1. 31 1 read-only CMD14 RTC I2C Command 14 0x70 0x20 COMMAND14 Content of command 14. For more information, please refer to the register I2C_COMD14_REG in Chapter I²C Controller. 0 14 read-write COMMAND14_DONE When command 14 is done, this bit changes to 1. 31 1 read-only CMD15 RTC I2C Command 15 0x74 0x20 COMMAND15 Content of command 15. For more information, please refer to the register I2C_COMD15_REG in Chapter I²C Controller. 0 14 read-write COMMAND15_DONE When command 15 is done, this bit changes to 1. 31 1 read-only DATE Version control register 0xFC 0x20 0x01905310 DATE Version control register 0 28 read-write SENS SENS Peripheral SENS 0x0000C800 0x0 0x110 registers TOUCH_DONE_INT 0 TOUCH_INACTIVE_INT 1 TOUCH_ACTIVE_INT 2 SARADC1_DONE_INT 3 SARADC2_DONE_INT 4 TSENS_DONE_INT 5 SAR_SLAVE_ADDR1 Configure slave addresses 0-1 of RTC I2C 0x40 0x20 I2C_SLAVE_ADDR1 RTC I2C slave address 1 0 11 read-write I2C_SLAVE_ADDR0 RTC I2C slave address 0 11 11 read-write MEAS_STATUS 22 8 read-only SAR_SLAVE_ADDR2 Configure slave addresses 2-3 of RTC I2C 0x44 0x20 I2C_SLAVE_ADDR3 RTC I2C slave address 3 0 11 read-write I2C_SLAVE_ADDR2 RTC I2C slave address 2 11 11 read-write SAR_SLAVE_ADDR3 Configure slave addresses 4-5 of RTC I2C 0x48 0x20 I2C_SLAVE_ADDR5 RTC I2C slave address 5 0 11 read-write I2C_SLAVE_ADDR4 RTC I2C slave address 4 11 11 read-write SAR_SLAVE_ADDR4 Configure slave addresses 6-7 of RTC I2C 0x4C 0x20 I2C_SLAVE_ADDR7 RTC I2C slave address 7 0 11 read-write I2C_SLAVE_ADDR6 RTC I2C slave address 6 11 11 read-write SAR_I2C_CTRL Configure RTC I2C transmission 0x58 0x20 SAR_I2C_CTRL RTC I2C control data. Active only when SENS_SAR_I2C_START_FORCE = 1. 0 28 read-write SAR_I2C_START Start RTC I2C. Active only when SENS_SAR_I2C_START_FORCE = 1 28 1 read-write SAR_I2C_START_FORCE 0: RTC I2C started by FSM. 1: RTC I2C started by software. 29 1 read-write SAR_COCPU_INT_RAW Interrupt raw bit of ULP-RISCV 0x128 0x20 COCPU_TOUCH_DONE_INT_RAW TOUCH_DONE_INT interrupt raw bit 0 1 read-only COCPU_TOUCH_INACTIVE_INT_RAW TOUCH_INACTIVE_INT interrupt raw bit 1 1 read-only COCPU_TOUCH_ACTIVE_INT_RAW TOUCH_ACTIVE_INT interrupt raw bit 2 1 read-only COCPU_SARADC1_INT_RAW SARADC1_DONE_INT interrupt raw bit 3 1 read-only COCPU_SARADC2_INT_RAW SARADC2_DONE_INT interrupt raw bit 4 1 read-only COCPU_TSENS_INT_RAW TSENS_DONE_INT interrupt raw bit 5 1 read-only COCPU_START_INT_RAW RISCV_START_INT interrupt raw bit 6 1 read-only COCPU_SW_INT_RAW SW_INT interrupt raw bit 7 1 read-only COCPU_SWD_INT_RAW SWD_INT interrupt raw bit 8 1 read-only SAR_COCPU_INT_ENA Interrupt enable bit of ULP-RISCV 0x12C 0x20 COCPU_TOUCH_DONE_INT_ENA TOUCH_DONE_INT interrupt enable bit 0 1 read-write COCPU_TOUCH_INACTIVE_INT_ENA TOUCH_INACTIVE_INT interrupt enable bit 1 1 read-write COCPU_TOUCH_ACTIVE_INT_ENA TOUCH_ACTIVE_INT interrupt enable bit 2 1 read-write COCPU_SARADC1_INT_ENA SARADC1_DONE_INT interrupt enable bit 3 1 read-write COCPU_SARADC2_INT_ENA SARADC2_DONE_INT interrupt enable bit 4 1 read-write COCPU_TSENS_INT_ENA TSENS_DONE_INT interrupt enable bit 5 1 read-write COCPU_START_INT_ENA RISCV_START_INT interrupt enable bit 6 1 read-write COCPU_SW_INT_ENA SW_INT interrupt enable bit 7 1 read-write COCPU_SWD_INT_ENA SWD_INT interrupt enable bit 8 1 read-write SAR_COCPU_INT_ST Interrupt status bit of ULP-RISCV 0x130 0x20 COCPU_TOUCH_DONE_INT_ST TOUCH_DONE_INT interrupt status bit 0 1 read-only COCPU_TOUCH_INACTIVE_INT_ST TOUCH_INACTIVE_INT interrupt status bit 1 1 read-only COCPU_TOUCH_ACTIVE_INT_ST TOUCH_ACTIVE_INT interrupt status bit 2 1 read-only COCPU_SARADC1_INT_ST SARADC1_DONE_INT interrupt status bit 3 1 read-only COCPU_SARADC2_INT_ST SARADC2_DONE_INT interrupt status bit 4 1 read-only COCPU_TSENS_INT_ST TSENS_DONE_INT interrupt status bit 5 1 read-only COCPU_START_INT_ST RISCV_START_INT interrupt status bit 6 1 read-only COCPU_SW_INT_ST SW_INT interrupt status bit 7 1 read-only COCPU_SWD_INT_ST SWD_INT interrupt status bit 8 1 read-only SAR_COCPU_INT_CLR Interrupt clear bit of ULP-RISCV 0x134 0x20 COCPU_TOUCH_DONE_INT_CLR TOUCH_DONE_INT interrupt clear bit 0 1 write-only COCPU_TOUCH_INACTIVE_INT_CLR TOUCH_INACTIVE_INT interrupt clear bit 1 1 write-only COCPU_TOUCH_ACTIVE_INT_CLR TOUCH_ACTIVE_INT interrupt clear bit 2 1 write-only COCPU_SARADC1_INT_CLR SARADC1_DONE_INT interrupt clear bit 3 1 write-only COCPU_SARADC2_INT_CLR SARADC2_DONE_INT interrupt clear bit 4 1 write-only COCPU_TSENS_INT_CLR TSENS_DONE_INT interrupt clear bit 5 1 write-only COCPU_START_INT_CLR RISCV_START_INT interrupt clear bit 6 1 write-only COCPU_SW_INT_CLR SW_INT interrupt clear bit 7 1 write-only COCPU_SWD_INT_CLR SWD_INT interrupt clear bit 8 1 write-only