ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. ESPRESSIF ESP32-C2 ESP32 C-Series 9 32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. RV32IMC r0p0 little false false 4 false 32 32 0x00000000 0xFFFFFFFF APB_CTRL APB (Advanced Peripheral Bus) Controller APB_CTRL 0x60026000 0x0 0xA0 registers APB_CTRL 12 SYSCLK_CONF APB_CTRL_SYSCLK_CONF_REG 0x0 0x20 0x00000001 PRE_DIV_CNT reg_pre_div_cnt 0 10 read-write CLK_320M_EN reg_clk_320m_en 10 1 read-write CLK_EN reg_clk_en 11 1 read-write RST_TICK_CNT reg_rst_tick_cnt 12 1 read-write TICK_CONF APB_CTRL_TICK_CONF_REG 0x4 0x20 0x00010727 XTAL_TICK_NUM reg_xtal_tick_num 0 8 read-write CK8M_TICK_NUM reg_ck8m_tick_num 8 8 read-write TICK_ENABLE reg_tick_enable 16 1 read-write CLK_OUT_EN APB_CTRL_CLK_OUT_EN_REG 0x8 0x20 0x000007FF CLK20_OEN reg_clk20_oen 0 1 read-write CLK22_OEN reg_clk22_oen 1 1 read-write CLK44_OEN reg_clk44_oen 2 1 read-write CLK_BB_OEN reg_clk_bb_oen 3 1 read-write CLK80_OEN reg_clk80_oen 4 1 read-write CLK160_OEN reg_clk160_oen 5 1 read-write CLK_320M_OEN reg_clk_320m_oen 6 1 read-write CLK_ADC_INF_OEN reg_clk_adc_inf_oen 7 1 read-write CLK_DAC_CPU_OEN reg_clk_dac_cpu_oen 8 1 read-write CLK40X_BB_OEN reg_clk40x_bb_oen 9 1 read-write CLK_XTAL_OEN reg_clk_xtal_oen 10 1 read-write WIFI_BB_CFG APB_CTRL_WIFI_BB_CFG_REG 0xC 0x20 WIFI_BB_CFG reg_wifi_bb_cfg 0 32 read-write WIFI_BB_CFG_2 APB_CTRL_WIFI_BB_CFG_2_REG 0x10 0x20 WIFI_BB_CFG_2 reg_wifi_bb_cfg_2 0 32 read-write WIFI_CLK_EN APB_CTRL_WIFI_CLK_EN_REG 0x14 0x20 0xFFFCE030 WIFI_CLK_EN reg_wifi_clk_en 0 32 read-write WIFI_RST_EN APB_CTRL_WIFI_RST_EN_REG 0x18 0x20 WIFI_RST reg_wifi_rst 0 32 read-write HOST_INF_SEL APB_CTRL_HOST_INF_SEL_REG 0x1C 0x20 PERI_IO_SWAP reg_peri_io_swap 0 8 read-write EXT_MEM_PMS_LOCK APB_CTRL_EXT_MEM_PMS_LOCK_REG 0x20 0x20 EXT_MEM_PMS_LOCK reg_ext_mem_pms_lock 0 1 read-write FLASH_ACE0_ATTR APB_CTRL_FLASH_ACE0_ATTR_REG 0x28 0x20 0x00000003 FLASH_ACE0_ATTR reg_flash_ace0_attr 0 2 read-write FLASH_ACE1_ATTR APB_CTRL_FLASH_ACE1_ATTR_REG 0x2C 0x20 0x00000003 FLASH_ACE1_ATTR reg_flash_ace1_attr 0 2 read-write FLASH_ACE2_ATTR APB_CTRL_FLASH_ACE2_ATTR_REG 0x30 0x20 0x00000003 FLASH_ACE2_ATTR reg_flash_ace2_attr 0 2 read-write FLASH_ACE3_ATTR APB_CTRL_FLASH_ACE3_ATTR_REG 0x34 0x20 0x00000003 FLASH_ACE3_ATTR reg_flash_ace3_attr 0 2 read-write FLASH_ACE0_ADDR APB_CTRL_FLASH_ACE0_ADDR_REG 0x38 0x20 S reg_flash_ace0_addr_s 0 32 read-write FLASH_ACE1_ADDR APB_CTRL_FLASH_ACE1_ADDR_REG 0x3C 0x20 0x00400000 S reg_flash_ace1_addr_s 0 32 read-write FLASH_ACE2_ADDR APB_CTRL_FLASH_ACE2_ADDR_REG 0x40 0x20 0x00800000 S reg_flash_ace2_addr_s 0 32 read-write FLASH_ACE3_ADDR APB_CTRL_FLASH_ACE3_ADDR_REG 0x44 0x20 0x00C00000 S reg_flash_ace3_addr_s 0 32 read-write FLASH_ACE0_SIZE APB_CTRL_FLASH_ACE0_SIZE_REG 0x48 0x20 0x00000400 FLASH_ACE0_SIZE reg_flash_ace0_size 0 13 read-write FLASH_ACE1_SIZE APB_CTRL_FLASH_ACE1_SIZE_REG 0x4C 0x20 0x00000400 FLASH_ACE1_SIZE reg_flash_ace1_size 0 13 read-write FLASH_ACE2_SIZE APB_CTRL_FLASH_ACE2_SIZE_REG 0x50 0x20 0x00000400 FLASH_ACE2_SIZE reg_flash_ace2_size 0 13 read-write FLASH_ACE3_SIZE APB_CTRL_FLASH_ACE3_SIZE_REG 0x54 0x20 0x00000400 FLASH_ACE3_SIZE reg_flash_ace3_size 0 13 read-write SPI_MEM_PMS_CTRL APB_CTRL_SPI_MEM_PMS_CTRL_REG 0x88 0x20 SPI_MEM_REJECT_INT reg_spi_mem_reject_int 0 1 read-only SPI_MEM_REJECT_CLR reg_spi_mem_reject_clr 1 1 write-only SPI_MEM_REJECT_CDE reg_spi_mem_reject_cde 2 5 read-only SPI_MEM_REJECT_ADDR APB_CTRL_SPI_MEM_REJECT_ADDR_REG 0x8C 0x20 SPI_MEM_REJECT_ADDR reg_spi_mem_reject_addr 0 32 read-only SDIO_CTRL APB_CTRL_SDIO_CTRL_REG 0x90 0x20 SDIO_WIN_ACCESS_EN reg_sdio_win_access_en 0 1 read-write REDCY_SIG0 APB_CTRL_REDCY_SIG0_REG_REG 0x94 0x20 REDCY_SIG0 reg_redcy_sig0 0 31 read-write REDCY_ANDOR reg_redcy_andor 31 1 read-only REDCY_SIG1 APB_CTRL_REDCY_SIG1_REG_REG 0x98 0x20 REDCY_SIG1 reg_redcy_sig1 0 31 read-write REDCY_NANDOR reg_redcy_nandor 31 1 read-only FRONT_END_MEM_PD APB_CTRL_FRONT_END_MEM_PD_REG 0x9C 0x20 0x00000055 AGC_MEM_FORCE_PU reg_agc_mem_force_pu 0 1 read-write AGC_MEM_FORCE_PD reg_agc_mem_force_pd 1 1 read-write PBUS_MEM_FORCE_PU reg_pbus_mem_force_pu 2 1 read-write PBUS_MEM_FORCE_PD reg_pbus_mem_force_pd 3 1 read-write DC_MEM_FORCE_PU reg_dc_mem_force_pu 4 1 read-write DC_MEM_FORCE_PD reg_dc_mem_force_pd 5 1 read-write FREQ_MEM_FORCE_PU reg_freq_mem_force_pu 6 1 read-write FREQ_MEM_FORCE_PD reg_freq_mem_force_pd 7 1 read-write RETENTION_CTRL APB_CTRL_RETENTION_CTRL_REG 0xA0 0x20 RETENTION_LINK_ADDR reg_retention_link_addr 0 27 read-write NOBYPASS_CPU_ISO_RST reg_nobypass_cpu_iso_rst 27 1 read-write CLKGATE_FORCE_ON Memory power configuration registers 0xA4 0x20 0x0000007F ROM_CLKGATE_FORCE_ON Set the bit to 1 to force rom always have clock, for low power can clear to 0 then only when have access the rom have clock 0 3 read-write SRAM_CLKGATE_FORCE_ON Set the bit to 1 to force sram always have clock, for low power can clear to 0 then only when have access the sram have clock 3 4 read-write MEM_POWER_DOWN Memory power configuration registers 0xA8 0x20 0x0000007F ROM_POWER_DOWN Set 1 to let rom power down 0 3 read-write SRAM_POWER_DOWN Set 1 to let sram power down 3 4 read-write MEM_POWER_UP Memory power configuration registers 0xAC 0x20 0x0000007F ROM_POWER_UP Set 1 to let rom power up 0 3 read-write SRAM_POWER_UP Set 1 to let sram power up 3 4 read-write RND_DATA APB_CTRL_RND_DATA_REG 0xB0 0x20 RND_DATA reg_rnd_data 0 32 read-only PERI_BACKUP_CONFIG APB_CTRL_PERI_BACKUP_CONFIG_REG_REG 0xB4 0x20 0x00006480 PERI_BACKUP_FLOW_ERR reg_peri_backup_flow_err 1 2 read-only PERI_BACKUP_BURST_LIMIT reg_peri_backup_burst_limit 4 5 read-write PERI_BACKUP_TOUT_THRES reg_peri_backup_tout_thres 9 10 read-write PERI_BACKUP_SIZE reg_peri_backup_size 19 10 read-write PERI_BACKUP_START reg_peri_backup_start 29 1 write-only PERI_BACKUP_TO_MEM reg_peri_backup_to_mem 30 1 read-write PERI_BACKUP_ENA reg_peri_backup_ena 31 1 read-write PERI_BACKUP_APB_ADDR APB_CTRL_PERI_BACKUP_APB_ADDR_REG_REG 0xB8 0x20 BACKUP_APB_START_ADDR reg_backup_apb_start_addr 0 32 read-write PERI_BACKUP_MEM_ADDR APB_CTRL_PERI_BACKUP_MEM_ADDR_REG_REG 0xBC 0x20 BACKUP_MEM_START_ADDR reg_backup_mem_start_addr 0 32 read-write PERI_BACKUP_INT_RAW APB_CTRL_PERI_BACKUP_INT_RAW_REG 0xC0 0x20 PERI_BACKUP_DONE_INT_RAW reg_peri_backup_done_int_raw 0 1 read-only PERI_BACKUP_ERR_INT_RAW reg_peri_backup_err_int_raw 1 1 read-only PERI_BACKUP_INT_ST APB_CTRL_PERI_BACKUP_INT_ST_REG 0xC4 0x20 PERI_BACKUP_DONE_INT_ST reg_peri_backup_done_int_st 0 1 read-only PERI_BACKUP_ERR_INT_ST reg_peri_backup_err_int_st 1 1 read-only PERI_BACKUP_INT_ENA APB_CTRL_PERI_BACKUP_INT_ENA_REG 0xC8 0x20 PERI_BACKUP_DONE_INT_ENA reg_peri_backup_done_int_ena 0 1 read-write PERI_BACKUP_ERR_INT_ENA reg_peri_backup_err_int_ena 1 1 read-write PERI_BACKUP_INT_CLR APB_CTRL_PERI_BACKUP_INT_CLR_REG 0xD0 0x20 PERI_BACKUP_DONE_INT_CLR reg_peri_backup_done_int_clr 0 1 write-only PERI_BACKUP_ERR_INT_CLR reg_peri_backup_err_int_clr 1 1 write-only DATE APB_CTRL_DATE_REG 0x3FC 0x20 0x02106080 DATE reg_dateVersion control 0 32 read-write APB_SARADC SAR (Successive Approximation Register) Analog-to-Digital Converter APB_SARADC 0x60040000 0x0 0x68 registers APB_ADC 32 CTRL register description 0x0 0x20 0x40038240 SARADC_START_FORCE Need add description 0 1 read-write SARADC_START Need add description 1 1 read-write SARADC_SAR_CLK_GATED Need add description 6 1 read-write SARADC_SAR_CLK_DIV SAR clock divider 7 8 read-write SARADC_SAR_PATT_LEN 0 ~ 15 means length 1 ~ 16 15 3 read-write SARADC_SAR_PATT_P_CLEAR clear the pointer of pattern table for DIG ADC1 CTRL 23 1 read-write SARADC_XPD_SAR_FORCE force option to xpd sar blocks 27 2 read-write SARADC_WAIT_ARB_CYCLE wait arbit signal stable after sar_done 30 2 read-write CTRL2 register description 0x4 0x20 0x0000A1FE SARADC_MEAS_NUM_LIMIT Need add description 0 1 read-write SARADC_MAX_MEAS_NUM max conversion number 1 8 read-write SARADC_SAR1_INV 1: data to DIG ADC1 CTRL is inverted, otherwise not 9 1 read-write SARADC_SAR2_INV 1: data to DIG ADC2 CTRL is inverted, otherwise not 10 1 read-write SARADC_TIMER_TARGET to set saradc timer target 12 12 read-write SARADC_TIMER_EN to enable saradc timer trigger 24 1 read-write FILTER_CTRL1 register description 0x8 0x20 FILTER_FACTOR1 Need add description 26 3 read-write FILTER_FACTOR0 Need add description 29 3 read-write FSM_WAIT register description 0xC 0x20 0x00FF0808 SARADC_XPD_WAIT Need add description 0 8 read-write SARADC_RSTB_WAIT Need add description 8 8 read-write SARADC_STANDBY_WAIT Need add description 16 8 read-write SAR1_STATUS register description 0x10 0x20 SARADC_SAR1_STATUS Need add description 0 32 read-only SAR2_STATUS register description 0x14 0x20 SARADC_SAR2_STATUS Need add description 0 32 read-only SAR_PATT_TAB1 register description 0x18 0x20 0x00FFFFFF SARADC_SAR_PATT_TAB1 item 0 ~ 3 for pattern table 1 (each item one byte) 0 24 read-write SAR_PATT_TAB2 register description 0x1C 0x20 0x00FFFFFF SARADC_SAR_PATT_TAB2 Item 4 ~ 7 for pattern table 1 (each item one byte) 0 24 read-write ONETIME_SAMPLE register description 0x20 0x20 0x1A000000 SARADC_ONETIME_ATTEN Need add description 23 2 read-write SARADC_ONETIME_CHANNEL Need add description 25 4 read-write SARADC_ONETIME_START Need add description 29 1 read-write SARADC2_ONETIME_SAMPLE Need add description 30 1 read-write SARADC1_ONETIME_SAMPLE Need add description 31 1 read-write APB_ADC_ARB_CTRL register description 0x24 0x20 0x00000900 ADC_ARB_APB_FORCE adc2 arbiter force to enableapb controller 2 1 read-write ADC_ARB_RTC_FORCE adc2 arbiter force to enable rtc controller 3 1 read-write ADC_ARB_WIFI_FORCE adc2 arbiter force to enable wifi controller 4 1 read-write ADC_ARB_GRANT_FORCE adc2 arbiter force grant 5 1 read-write ADC_ARB_APB_PRIORITY Set adc2 arbiterapb priority 6 2 read-write ADC_ARB_RTC_PRIORITY Set adc2 arbiter rtc priority 8 2 read-write ADC_ARB_WIFI_PRIORITY Set adc2 arbiter wifi priority 10 2 read-write ADC_ARB_FIX_PRIORITY adc2 arbiter uses fixed priority 12 1 read-write FILTER_CTRL0 register description 0x28 0x20 0x03740000 FILTER_CHANNEL1 Need add description 18 4 read-write FILTER_CHANNEL0 apb_adc1_filter_factor 22 4 read-write FILTER_RESET enable apb_adc1_filter 31 1 read-write SAR1DATA_STATUS register description 0x2C 0x20 APB_SARADC1_DATA Need add description 0 17 read-only SAR2DATA_STATUS register description 0x30 0x20 APB_SARADC2_DATA Need add description 0 17 read-only THRES0_CTRL register description 0x34 0x20 0x0003FFED THRES0_CHANNEL Need add description 0 4 read-write THRES0_HIGH saradc1's thres0 monitor thres 5 13 read-write THRES0_LOW saradc1's thres0 monitor thres 18 13 read-write THRES1_CTRL register description 0x38 0x20 0x0003FFED THRES1_CHANNEL Need add description 0 4 read-write THRES1_HIGH saradc1's thres0 monitor thres 5 13 read-write THRES1_LOW saradc1's thres0 monitor thres 18 13 read-write THRES_CTRL register description 0x3C 0x20 THRES_ALL_EN Need add description 27 1 read-write THRES3_EN Need add description 28 1 read-write THRES2_EN Need add description 29 1 read-write THRES1_EN Need add description 30 1 read-write THRES0_EN Need add description 31 1 read-write INT_ENA register description 0x40 0x20 THRES1_LOW_INT_ENA Need add description 26 1 read-write THRES0_LOW_INT_ENA Need add description 27 1 read-write THRES1_HIGH_INT_ENA Need add description 28 1 read-write THRES0_HIGH_INT_ENA Need add description 29 1 read-write APB_SARADC2_DONE_INT_ENA Need add description 30 1 read-write APB_SARADC1_DONE_INT_ENA Need add description 31 1 read-write INT_RAW register description 0x44 0x20 THRES1_LOW_INT_RAW Need add description 26 1 read-only THRES0_LOW_INT_RAW Need add description 27 1 read-only THRES1_HIGH_INT_RAW Need add description 28 1 read-only THRES0_HIGH_INT_RAW Need add description 29 1 read-only APB_SARADC2_DONE_INT_RAW Need add description 30 1 read-only APB_SARADC1_DONE_INT_RAW Need add description 31 1 read-only INT_ST register description 0x48 0x20 THRES1_LOW_INT_ST Need add description 26 1 read-only THRES0_LOW_INT_ST Need add description 27 1 read-only THRES1_HIGH_INT_ST Need add description 28 1 read-only THRES0_HIGH_INT_ST Need add description 29 1 read-only APB_SARADC2_DONE_INT_ST Need add description 30 1 read-only APB_SARADC1_DONE_INT_ST Need add description 31 1 read-only INT_CLR register description 0x4C 0x20 THRES1_LOW_INT_CLR Need add description 26 1 write-only THRES0_LOW_INT_CLR Need add description 27 1 write-only THRES1_HIGH_INT_CLR Need add description 28 1 write-only THRES0_HIGH_INT_CLR Need add description 29 1 write-only APB_SARADC2_DONE_INT_CLR Need add description 30 1 write-only APB_SARADC1_DONE_INT_CLR Need add description 31 1 write-only DMA_CONF register description 0x50 0x20 0x000000FF APB_ADC_EOF_NUM the dma_in_suc_eof gen when sample cnt = spi_eof_num 0 16 read-write APB_ADC_RESET_FSM reset_apb_adc_state 30 1 read-write APB_ADC_TRANS enable apb_adc use spi_dma 31 1 read-write APB_ADC_CLKM_CONF register description 0x54 0x20 0x00000004 REG_CLKM_DIV_NUM Integral I2S clock divider value 0 8 read-write REG_CLKM_DIV_B Fractional clock divider numerator value 8 6 read-write REG_CLKM_DIV_A Fractional clock divider denominator value 14 6 read-write CLK_EN Need add description 20 1 read-write REG_CLK_SEL Set this bit to enable clk_apll 21 2 read-write APB_TSENS_CTRL register description 0x58 0x20 0x00018000 REG_TSENS_OUT Need add description 0 8 read-only REG_TSENS_IN_INV Need add description 13 1 read-write REG_TSENS_CLK_DIV Need add description 14 8 read-write REG_TSENS_PU Need add description 22 1 read-write APB_TSENS_CTRL2 register description 0x5C 0x20 0x00004002 REG_TSENS_XPD_WAIT Need add description 0 12 read-write REG_TSENS_XPD_FORCE Need add description 12 2 read-write REG_TSENS_CLK_INV Need add description 14 1 read-write TSENS_CLK_SEL Need add description 15 1 read-write CALI register description 0x60 0x20 0x00008000 CFG Need add description 0 17 read-write APB_CTRL_DATE register description 0x3FC 0x20 0x02107210 DATE Need add description 0 32 read-write ASSIST_DEBUG Debug Assist ASSIST_DEBUG 0x600CE000 0x0 0x38 registers ASSIST_DEBUG Assist debug interrupt 40 CORE_0_MONTR_ENA core0 monitor enable configuration register 0x0 0x20 CORE_0_SP_SPILL_MIN_ENA enbale sp underlow monitor 0 1 read-write CORE_0_SP_SPILL_MAX_ENA enbale sp overflow monitor 1 1 read-write CORE_0_INTR_RAW core0 monitor interrupt status register 0x4 0x20 CORE_0_SP_SPILL_MIN_RAW sp underlow monitor interrupt status register 0 1 read-only CORE_0_SP_SPILL_MAX_RAW sp overflow monitor interupt status register 1 1 read-only CORE_0_INTR_ENA core0 monitor interrupt enable register 0x8 0x20 CORE_0_SP_SPILL_MIN_INTR_ENA enbale sp underlow monitor interrupt 0 1 read-write CORE_0_SP_SPILL_MAX_INTR_ENA enbale sp overflow monitor interrupt 1 1 read-write CORE_0_INTR_CLR core0 monitor interrupt clr register 0xC 0x20 CORE_0_SP_SPILL_MIN_CLR clr sp underlow monitor interrupt 0 1 write-only CORE_0_SP_SPILL_MAX_CLR clr sp overflow monitor interrupt 1 1 write-only CORE_0_SP_MIN stack min value 0x10 0x20 CORE_0_SP_MIN core0 sp region configuration regsiter 0 32 read-write CORE_0_SP_MAX stack max value 0x14 0x20 0xFFFFFFFF CORE_0_SP_MAX core0 sp pc status register 0 32 read-write CORE_0_SP_PC stack monitor pc status register 0x18 0x20 CORE_0_SP_PC This regsiter stores the PC when trigger stack monitor. 0 32 read-only CORE_0_RCD_EN record enable configuration register 0x1C 0x20 CORE_0_RCD_RECORDEN Set 1 to enable record PC 0 1 read-write CORE_0_RCD_PDEBUGEN Set 1 to enable cpu pdebug function, must set this bit can get cpu PC 1 1 read-write CORE_0_RCD_PDEBUGPC record status regsiter 0x20 0x20 CORE_0_RCD_PDEBUGPC recorded PC 0 32 read-only CORE_0_RCD_PDEBUGSP record status regsiter 0x24 0x20 CORE_0_RCD_PDEBUGSP recorded sp 0 32 read-only CORE_0_LASTPC_BEFORE_EXCEPTION cpu status register 0x28 0x20 CORE_0_LASTPC_BEFORE_EXC cpu's lastpc before exception 0 32 read-only CORE_0_DEBUG_MODE cpu status register 0x2C 0x20 CORE_0_DEBUG_MODE cpu debug mode status, 1 means cpu enter debug mode. 0 1 read-only CORE_0_DEBUG_MODULE_ACTIVE cpu debug_module active status 1 1 read-only CLOCK_GATE clock gate register 0x30 0x20 0x00000001 CLK_EN clock gate register 0 1 read-write DATE version register 0x1FC 0x20 0x02106020 DATE version register 0 28 read-write BB BB Peripheral BB 0x6001D000 0x0 0x4 registers BBPD_CTRL Baseband control register 0x54 0x20 DC_EST_FORCE_PD 0 1 read-write DC_EST_FORCE_PU 1 1 read-write FFT_FORCE_PD 2 1 read-write FFT_FORCE_PU 3 1 read-write DMA DMA (Direct Memory Access) Controller DMA 0x6003F000 0x0 0x84 registers DMA_CH0 33 INT_RAW_CH0 DMA_INT_RAW_CH0_REG. 0x0 0x20 IN_DONE The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. 0 1 read-write IN_SUC_EOF The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. 1 1 read-write IN_ERR_EOF The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved. 2 1 read-write OUT_DONE The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. 3 1 read-write OUT_EOF The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. 4 1 read-write IN_DSCR_ERR The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. 5 1 read-write OUT_DSCR_ERR The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. 6 1 read-write IN_DSCR_EMPTY The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0. 7 1 read-write OUT_TOTAL_EOF The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. 8 1 read-write INFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. 9 1 read-write INFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. 10 1 read-write OUTFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. 11 1 read-write OUTFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. 12 1 read-write INT_ST_CH0 DMA_INT_ST_CH0_REG. 0x4 0x20 IN_DONE The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only IN_SUC_EOF The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only IN_ERR_EOF The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only OUT_DONE The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 3 1 read-only OUT_EOF The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 4 1 read-only IN_DSCR_ERR The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-only OUT_DSCR_ERR The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-only IN_DSCR_EMPTY The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-only OUT_TOTAL_EOF The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-only INFIFO_OVF The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-only INFIFO_UDF The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-only OUTFIFO_OVF The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-only OUTFIFO_UDF The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 read-only INT_ENA_CH0 DMA_INT_ENA_CH0_REG. 0x8 0x20 IN_DONE The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write IN_SUC_EOF The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write IN_ERR_EOF The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write OUT_DONE The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 3 1 read-write OUT_EOF The interrupt enable bit for the OUT_EOF_CH_INT interrupt. 4 1 read-write IN_DSCR_ERR The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-write OUT_DSCR_ERR The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-write IN_DSCR_EMPTY The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-write OUT_TOTAL_EOF The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-write INFIFO_OVF The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-write INFIFO_UDF The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-write OUTFIFO_OVF The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-write OUTFIFO_UDF The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 read-write INT_CLR_CH0 DMA_INT_CLR_CH0_REG. 0xC 0x20 IN_DONE Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only IN_SUC_EOF Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only IN_ERR_EOF Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 write-only OUT_DONE Set this bit to clear the OUT_DONE_CH_INT interrupt. 3 1 write-only OUT_EOF Set this bit to clear the OUT_EOF_CH_INT interrupt. 4 1 write-only IN_DSCR_ERR Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. 5 1 write-only OUT_DSCR_ERR Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. 6 1 write-only IN_DSCR_EMPTY Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 write-only OUT_TOTAL_EOF Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 write-only INFIFO_OVF Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 9 1 write-only INFIFO_UDF Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 10 1 write-only OUTFIFO_OVF Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 write-only OUTFIFO_UDF Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 write-only AHB_TEST DMA_AHB_TEST_REG. 0x40 0x20 AHB_TESTMODE reserved 0 3 read-write AHB_TESTADDR reserved 4 2 read-write MISC_CONF DMA_MISC_CONF_REG. 0x44 0x20 AHBM_RST_INTER Set this bit, then clear this bit to reset the internal ahb FSM. 0 1 read-write ARB_PRI_DIS Set this bit to disable priority arbitration function. 2 1 read-write CLK_EN reg_clk_en 3 1 read-write DATE DMA_DATE_REG. 0x48 0x20 0x02105280 DATE register version. 0 32 read-write IN_CONF0_CH0 DMA_IN_CONF0_CH0_REG. 0x70 0x20 IN_RST This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. 0 1 read-write IN_LOOP_TEST reserved 1 1 read-write INDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. 2 1 read-write IN_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. 3 1 read-write MEM_TRANS_EN Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. 4 1 read-write IN_CONF1_CH0 DMA_IN_CONF1_CH0_REG. 0x74 0x20 IN_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 read-write INFIFO_STATUS_CH0 DMA_INFIFO_STATUS_CH0_REG. 0x78 0x20 0x07800003 INFIFO_FULL L1 Rx FIFO full signal for Rx channel 0. 0 1 read-only INFIFO_EMPTY L1 Rx FIFO empty signal for Rx channel 0. 1 1 read-only INFIFO_CNT The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. 2 6 read-only IN_REMAIN_UNDER_1B reserved 23 1 read-only IN_REMAIN_UNDER_2B reserved 24 1 read-only IN_REMAIN_UNDER_3B reserved 25 1 read-only IN_REMAIN_UNDER_4B reserved 26 1 read-only IN_BUF_HUNGRY reserved 27 1 read-only IN_POP_CH0 DMA_IN_POP_CH0_REG. 0x7C 0x20 0x00000800 INFIFO_RDATA This register stores the data popping from DMA FIFO. 0 12 read-only INFIFO_POP Set this bit to pop data from DMA FIFO. 12 1 read-write IN_LINK_CH0 DMA_IN_LINK_CH0_REG. 0x80 0x20 0x01100000 INLINK_ADDR This register stores the 20 least significant bits of the first inlink descriptor's address. 0 20 read-write INLINK_AUTO_RET Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. 20 1 read-write INLINK_STOP Set this bit to stop dealing with the inlink descriptors. 21 1 read-write INLINK_START Set this bit to start dealing with the inlink descriptors. 22 1 read-write INLINK_RESTART Set this bit to mount a new inlink descriptor. 23 1 read-write INLINK_PARK 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. 24 1 read-only IN_STATE_CH0 DMA_IN_STATE_CH0_REG. 0x84 0x20 INLINK_DSCR_ADDR This register stores the current inlink descriptor's address. 0 18 read-only IN_DSCR_STATE reserved 18 2 read-only IN_STATE reserved 20 3 read-only IN_SUC_EOF_DES_ADDR_CH0 DMA_IN_SUC_EOF_DES_ADDR_CH0_REG. 0x88 0x20 IN_SUC_EOF_DES_ADDR This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 read-only IN_ERR_EOF_DES_ADDR_CH0 DMA_IN_ERR_EOF_DES_ADDR_CH0_REG. 0x8C 0x20 IN_ERR_EOF_DES_ADDR This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 32 read-only IN_DSCR_CH0 DMA_IN_DSCR_CH0_REG. 0x90 0x20 INLINK_DSCR The address of the current inlink descriptor x. 0 32 read-only IN_DSCR_BF0_CH0 DMA_IN_DSCR_BF0_CH0_REG. 0x94 0x20 INLINK_DSCR_BF0 The address of the last inlink descriptor x-1. 0 32 read-only IN_DSCR_BF1_CH0 DMA_IN_DSCR_BF1_CH0_REG. 0x98 0x20 INLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 read-only IN_PRI_CH0 DMA_IN_PRI_CH0_REG. 0x9C 0x20 RX_PRI The priority of Rx channel 0. The larger of the value, the higher of the priority. 0 4 read-write IN_PERI_SEL_CH0 DMA_IN_PERI_SEL_CH0_REG. 0xA0 0x20 0x0000003F PERI_IN_SEL This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 read-write OUT_CONF0_CH0 DMA_OUT_CONF0_CH0_REG. 0xD0 0x20 0x00000008 OUT_RST This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. 0 1 read-write OUT_LOOP_TEST reserved 1 1 read-write OUT_AUTO_WRBACK Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. 2 1 read-write OUT_EOF_MODE EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA 3 1 read-write OUTDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. 4 1 read-write OUT_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. 5 1 read-write OUT_CONF1_CH0 DMA_OUT_CONF1_CH0_REG. 0xD4 0x20 OUT_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 read-write OUTFIFO_STATUS_CH0 DMA_OUTFIFO_STATUS_CH0_REG. 0xD8 0x20 0x07800002 OUTFIFO_FULL L1 Tx FIFO full signal for Tx channel 0. 0 1 read-only OUTFIFO_EMPTY L1 Tx FIFO empty signal for Tx channel 0. 1 1 read-only OUTFIFO_CNT The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. 2 6 read-only OUT_REMAIN_UNDER_1B reserved 23 1 read-only OUT_REMAIN_UNDER_2B reserved 24 1 read-only OUT_REMAIN_UNDER_3B reserved 25 1 read-only OUT_REMAIN_UNDER_4B reserved 26 1 read-only OUT_PUSH_CH0 DMA_OUT_PUSH_CH0_REG. 0xDC 0x20 OUTFIFO_WDATA This register stores the data that need to be pushed into DMA FIFO. 0 9 read-write OUTFIFO_PUSH Set this bit to push data into DMA FIFO. 9 1 read-write OUT_LINK_CH0 DMA_OUT_LINK_CH0_REG. 0xE0 0x20 0x00800000 OUTLINK_ADDR This register stores the 20 least significant bits of the first outlink descriptor's address. 0 20 read-write OUTLINK_STOP Set this bit to stop dealing with the outlink descriptors. 20 1 read-write OUTLINK_START Set this bit to start dealing with the outlink descriptors. 21 1 read-write OUTLINK_RESTART Set this bit to restart a new outlink from the last address. 22 1 read-write OUTLINK_PARK 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. 23 1 read-only OUT_STATE_CH0 DMA_OUT_STATE_CH0_REG. 0xE4 0x20 OUTLINK_DSCR_ADDR This register stores the current outlink descriptor's address. 0 18 read-only OUT_DSCR_STATE reserved 18 2 read-only OUT_STATE reserved 20 3 read-only OUT_EOF_DES_ADDR_CH0 DMA_OUT_EOF_DES_ADDR_CH0_REG. 0xE8 0x20 OUT_EOF_DES_ADDR This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. 0 32 read-only OUT_EOF_BFR_DES_ADDR_CH0 DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG. 0xEC 0x20 OUT_EOF_BFR_DES_ADDR This register stores the address of the outlink descriptor before the last outlink descriptor. 0 32 read-only OUT_DSCR_CH0 DMA_OUT_DSCR_CH0_REG. 0xF0 0x20 OUTLINK_DSCR The address of the current outlink descriptor y. 0 32 read-only OUT_DSCR_BF0_CH0 DMA_OUT_DSCR_BF0_CH0_REG. 0xF4 0x20 OUTLINK_DSCR_BF0 The address of the last outlink descriptor y-1. 0 32 read-only OUT_DSCR_BF1_CH0 DMA_OUT_DSCR_BF1_CH0_REG. 0xF8 0x20 OUTLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 read-only OUT_PRI_CH0 DMA_OUT_PRI_CH0_REG. 0xFC 0x20 TX_PRI The priority of Tx channel 0. The larger of the value, the higher of the priority. 0 4 read-write OUT_PERI_SEL_CH0 DMA_OUT_PERI_SEL_CH0_REG. 0x100 0x20 0x0000003F PERI_OUT_SEL This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 read-write ECC ECC (ECC Hardware Accelerator) ECC 0x6003E000 0x0 0x18 registers MULT_INT_RAW I2S interrupt raw register, valid in level. 0xC 0x20 CALC_DONE_INT_RAW The raw interrupt status bit for the i2s_tx_hung_int interrupt 0 1 read-only MULT_INT_ST I2S interrupt status register. 0x10 0x20 CALC_DONE_INT_ST The masked interrupt status bit for the i2s_rx_done_int interrupt 0 1 read-only MULT_INT_ENA I2S interrupt enable register. 0x14 0x20 CALC_DONE_INT_ENA The interrupt enable bit for the i2s_rx_done_int interrupt 0 1 read-write MULT_INT_CLR I2S interrupt clear register. 0x18 0x20 CALC_DONE_INT_CLR Set this bit to clear the i2s_rx_done_int interrupt 0 1 write-only MULT_CONF I2S RX configure register 0x1C 0x20 START Set this bit to reset receiver 0 1 read-write RESET Set this bit to reset Rx AFIFO 1 1 write-only KEY_LENGTH Set this bit to start receiving data 2 1 read-write SECURITY_MODE Set this bit to enable slave receiver mode 3 1 read-write CLK_EN clk gate 4 1 read-write WORK_MODE Reserved 5 3 read-write VERIFICATION_RESULT Reserve 8 1 read-only MULT_DATE Version control register 0xFC 0x20 0x02012230 DATE ECC mult version control register 0 28 read-write 32 0x1 K_MEM[%s] The memory that stores k. 0x100 0x8 32 0x1 PX_MEM[%s] The memory that stores Px. 0x120 0x8 32 0x1 PY_MEM[%s] The memory that stores Py. 0x140 0x8 EFUSE eFuse Controller EFUSE 0x60008800 0x0 0xC0 registers EFUSE 20 PGM_DATA0 Register 0 that stores data to be programmed. 0x0 0x20 PGM_DATA_0 The content of the 0th 32-bit data to be programmed. 0 32 read-write PGM_DATA1 Register 1 that stores data to be programmed. 0x4 0x20 PGM_DATA_1 The content of the 1st 32-bit data to be programmed. 0 32 read-write PGM_DATA2 Register 2 that stores data to be programmed. 0x8 0x20 PGM_DATA_2 The content of the 2nd 32-bit data to be programmed. 0 32 read-write PGM_DATA3 Register 3 that stores data to be programmed. 0xC 0x20 PGM_DATA_3 The content of the 3rd 32-bit data to be programmed. 0 32 read-write PGM_DATA4 Register 4 that stores data to be programmed. 0x10 0x20 PGM_DATA_4 The content of the 4th 32-bit data to be programmed. 0 32 read-write PGM_DATA5 Register 5 that stores data to be programmed. 0x14 0x20 PGM_DATA_5 The content of the 5th 32-bit data to be programmed. 0 32 read-write PGM_DATA6 Register 6 that stores data to be programmed. 0x18 0x20 PGM_DATA_6 The content of the 6th 32-bit data to be programmed. 0 32 read-write PGM_DATA7 Register 7 that stores data to be programmed. 0x1C 0x20 PGM_DATA_7 The content of the 7th 32-bit data to be programmed. 0 32 read-write PGM_CHECK_VALUE0 Register 0 that stores the RS code to be programmed. 0x20 0x20 PGM_RS_DATA_0 The content of the 0th 32-bit RS code to be programmed. 0 32 read-write PGM_CHECK_VALUE1 Register 1 that stores the RS code to be programmed. 0x24 0x20 PGM_RS_DATA_1 The content of the 1st 32-bit RS code to be programmed. 0 32 read-write PGM_CHECK_VALUE2 Register 2 that stores the RS code to be programmed. 0x28 0x20 PGM_RS_DATA_2 The content of the 2nd 32-bit RS code to be programmed. 0 32 read-write RD_WR_DIS BLOCK0 data register 0. 0x2C 0x20 WR_DIS Disable programming of individual eFuses. 0 8 read-only RD_REPEAT_DATA0 BLOCK0 data register 1. 0x30 0x20 RD_DIS The bit be set to disable software read high/low 128-bit of BLK3. 0 2 read-only WDT_DELAY_SEL Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000. 2 2 read-only DIS_PAD_JTAG Set this bit to disable pad jtag. 4 1 read-only DIS_DOWNLOAD_ICACHE The bit be set to disable icache in download mode. 5 1 read-only DIS_DOWNLOAD_MANUAL_ENCRYPT The bit be set to disable manual encryption. 6 1 read-only SPI_BOOT_ENCRYPT_DECRYPT_CNT These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable. 7 3 read-only XTS_KEY_LENGTH_256 The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise, XTS_AES use 128-bit eFuse data in BLOCK3. 10 1 read-only UART_PRINT_CONTROL Set this bit to disable usb printing. 11 2 read-only FORCE_SEND_RESUME Set this bit to force ROM code to send a resume command during SPI boot. 13 1 read-only DIS_DOWNLOAD_MODE Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7). 14 1 read-only DIS_DIRECT_BOOT This bit set means disable direct_boot mode. 15 1 read-only ENABLE_SECURITY_DOWNLOAD Set this bit to enable secure UART download mode. 16 1 read-only FLASH_TPUW Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value. Otherwise, the waiting time is twice the configurable value. 17 4 read-only SECURE_BOOT_EN The bit be set to enable secure boot. 21 1 read-only RPT4_RESERVED Reserved (used for four backups method). 22 10 read-only RD_BLK1_DATA0 BLOCK1 data register 0. 0x34 0x20 SYSTEM_DATA0 Stores the bits [0:31] of system data. 0 32 read-only RD_BLK1_DATA1 BLOCK1 data register 1. 0x38 0x20 SYSTEM_DATA1 Stores the bits [32:63] of system data. 0 32 read-only RD_BLK1_DATA2 BLOCK1 data register 2. 0x3C 0x20 SYSTEM_DATA2 Stores the bits [64:87] of system data. 0 24 read-only RD_BLK2_DATA0 Register 0 of BLOCK2. 0x40 0x20 BLK2_DATA0 Store the bit [0:31] of MAC. 0 32 read-only RD_BLK2_DATA1 Register 1 of BLOCK2. 0x44 0x20 MAC_ID_HIGH Store the bit [31:47] of MAC. 0 16 read-only WAFER_VERSION Store wafer version. 16 3 read-only PKG_VERSION Store package version. 19 3 read-only BLK2_EFUSE_VERSION Store efuse version. 22 3 read-only RF_REF_I_BIAS_CONFIG Store rf configuration parameters. 25 4 read-only LDO_VOL_BIAS_CONFIG_LOW Store the bit [0:2] of ido configuration parameters. 29 3 read-only RD_BLK2_DATA2 Register 2 of BLOCK2. 0x48 0x20 LDO_VOL_BIAS_CONFIG_HIGH Store the bit [3:29] of ido configuration parameters. 0 27 read-only PVT_LOW Store the bit [0:4] of pvt. 27 5 read-only RD_BLK2_DATA3 Register 3 of BLOCK2. 0x4C 0x20 PVT_HIGH Store the bit [5:14] of pvt. 0 10 read-only ADC_CALIBRATION_0 Store the bit [0:21] of ADC calibration data. 10 22 read-only RD_BLK2_DATA4 Register 4 of BLOCK2. 0x50 0x20 ADC_CALIBRATION_1 Store the bit [22:53] of ADC calibration data. 0 32 read-only RD_BLK2_DATA5 Register 5 of BLOCK2. 0x54 0x20 ADC_CALIBRATION_2 Store the bit [54:85] of ADC calibration data. 0 32 read-only RD_BLK2_DATA6 Register 6 of BLOCK2. 0x58 0x20 ADC_CALIBRATION_3 Store the bit [86:96] of ADC calibration data. 0 11 read-only BLK2_RESERVED_DATA_0 Store the bit [0:20] of block2 reserved data. 11 21 read-only RD_BLK2_DATA7 Register 7 of BLOCK2. 0x5C 0x20 BLK2_RESERVED_DATA_1 Store the bit [21:52] of block2 reserved data. 0 32 read-only RD_BLK3_DATA0 Register 0 of BLOCK3. 0x60 0x20 BLK3_DATA0 Store the first 32-bit of Block3. 0 32 read-only RD_BLK3_DATA1 Register 1 of BLOCK3. 0x64 0x20 BLK3_DATA1 Store the second 32-bit of Block3. 0 32 read-only RD_BLK3_DATA2 Register 2 of BLOCK3. 0x68 0x20 BLK3_DATA2 Store the third 32-bit of Block3. 0 32 read-only RD_BLK3_DATA3 Register 3 of BLOCK3. 0x6C 0x20 BLK3_DATA3 Store the fourth 32-bit of Block3. 0 32 read-only RD_BLK3_DATA4 Register 4 of BLOCK3. 0x70 0x20 BLK3_DATA4 Store the fifth 32-bit of Block3. 0 32 read-only RD_BLK3_DATA5 Register 5 of BLOCK3. 0x74 0x20 BLK3_DATA5 Store the sixth 32-bit of Block3. 0 32 read-only RD_BLK3_DATA6 Register 6 of BLOCK3. 0x78 0x20 BLK3_DATA6 Store the seventh 32-bit of Block3. 0 32 read-only RD_BLK3_DATA7 Register 7 of BLOCK3. 0x7C 0x20 BLK3_DATA7 Store the eighth 32-bit of Block3. 0 32 read-only RD_REPEAT_ERR Programming error record register 0 of BLOCK0. 0x80 0x20 RD_DIS_ERR If any bit in RD_DIS is 1, then it indicates a programming error. 0 2 read-only WDT_DELAY_SEL_ERR If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error. 2 2 read-only DIS_PAD_JTAG_ERR If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error. 4 1 read-only DIS_DOWNLOAD_ICACHE_ERR If any bit in this filed is 1, then it indicates a programming error. 5 1 read-only DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR If any bit in DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error. 6 1 read-only SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR If any bit in SPI_BOOT_ENCRYPT_DECRYPT_CNT is 1, then it indicates a programming error. 7 3 read-only XTS_KEY_LENGTH_256_ERR If any bit in XTS_KEY_LENGTH_256 is 1, then it indicates a programming error. 10 1 read-only UART_PRINT_CONTROL_ERR If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error. 11 2 read-only FORCE_SEND_RESUME_ERR If any bit in FORCE_SEND_RESUME is 1, then it indicates a programming error. 13 1 read-only DIS_DOWNLOAD_MODE_ERR If any bit in this filed is 1, then it indicates a programming error. 14 1 read-only DIS_DIRECT_BOOT_ERR If any bit in this filed is 1, then it indicates a programming error. 15 1 read-only ENABLE_SECURITY_DOWNLOAD_ERR If any bit in this filed is 1, then it indicates a programming error. 16 1 read-only FLASH_TPUW_ERR If any bit in this filed is 1, then it indicates a programming error. 17 4 read-only SECURE_BOOT_EN_ERR If any bit in this filed is 1, then it indicates a programming error. 21 1 read-only RPT4_RESERVED_ERR Reserved. 22 10 read-only RD_RS_ERR Programming error record register 0 of BLOCK1-10. 0x84 0x20 BLK1_ERR_NUM The value of this signal means the number of error bytes in block1. 0 3 read-only BLK1_FAIL 0: Means no failure and that the data of block1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. 3 1 read-only BLK2_ERR_NUM The value of this signal means the number of error bytes in block2. 4 3 read-only BLK2_FAIL 0: Means no failure and that the data of block2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. 7 1 read-only BLK3_ERR_NUM The value of this signal means the number of error bytes in block3. 8 3 read-only BLK3_FAIL 0: Means no failure and that the block3 data is reliable 1: Means that programming user data failed and the number of error bytes is over 6. 11 1 read-only CLK eFuse clcok configuration register. 0x88 0x20 0x00000002 EFUSE_MEM_FORCE_PD Set this bit to force eFuse SRAM into power-saving mode. 0 1 read-write MEM_CLK_FORCE_ON Set this bit and force to activate clock signal of eFuse SRAM. 1 1 read-write EFUSE_MEM_FORCE_PU Set this bit to force eFuse SRAM into working mode. 2 1 read-write EN Set this bit and force to enable clock signal of eFuse memory. 16 1 read-write CONF eFuse operation mode configuraiton register 0x8C 0x20 OP_CODE 0x5A5A: Operate programming command 0x5AA5: Operate read command. 0 16 read-write STATUS eFuse status register. 0x90 0x20 STATE Indicates the state of the eFuse state machine. 0 4 read-only OTP_LOAD_SW The value of OTP_LOAD_SW. 4 1 read-only OTP_VDDQ_C_SYNC2 The value of OTP_VDDQ_C_SYNC2. 5 1 read-only OTP_STROBE_SW The value of OTP_STROBE_SW. 6 1 read-only OTP_CSB_SW The value of OTP_CSB_SW. 7 1 read-only OTP_PGENB_SW The value of OTP_PGENB_SW. 8 1 read-only OTP_VDDQ_IS_SW The value of OTP_VDDQ_IS_SW. 9 1 read-only BLK0_VALID_BIT_CNT Record the number of bit '1' in BLOCK0. 10 6 read-only CMD eFuse command register. 0x94 0x20 READ_CMD Set this bit to send read command. 0 1 read-write PGM_CMD Set this bit to send programming command. 1 1 read-write BLK_NUM The serial number of the block to be programmed. Value 0-3 corresponds to block number 0-3, respectively. 2 2 read-write INT_RAW eFuse raw interrupt register. 0x98 0x20 READ_DONE_INT_RAW The raw bit signal for read_done interrupt. 0 1 read-write PGM_DONE_INT_RAW The raw bit signal for pgm_done interrupt. 1 1 read-write INT_ST eFuse interrupt status register. 0x9C 0x20 READ_DONE_INT_ST The status signal for read_done interrupt. 0 1 read-only PGM_DONE_INT_ST The status signal for pgm_done interrupt. 1 1 read-only INT_ENA eFuse interrupt enable register. 0x100 0x20 READ_DONE_INT_ENA The enable signal for read_done interrupt. 0 1 read-write PGM_DONE_INT_ENA The enable signal for pgm_done interrupt. 1 1 read-write INT_CLR eFuse interrupt clear register. 0x104 0x20 READ_DONE_INT_CLR The clear signal for read_done interrupt. 0 1 write-only PGM_DONE_INT_CLR The clear signal for pgm_done interrupt. 1 1 write-only DAC_CONF Controls the eFuse programming voltage. 0x108 0x20 0x0001FE1C DAC_CLK_DIV Controls the division factor of the rising clock of the programming voltage. 0 8 read-write DAC_CLK_PAD_SEL Don't care. 8 1 read-write DAC_NUM Controls the rising period of the programming voltage. 9 8 read-write OE_CLR Reduces the power supply of the programming voltage. 17 1 read-write RD_TIM_CONF Configures read timing parameters. 0x10C 0x20 0x12010201 THR_A Configures hold time for efuse read. 0 8 read-write TRD Configures pulse time for efuse read. 8 8 read-write TSUR_A Configures setup time for efuse read. 16 8 read-write READ_INIT_NUM Configures the initial read time of eFuse. 24 8 read-write WR_TIM_CONF0 Configurarion register 0 of eFuse programming timing parameters. 0x110 0x20 0x00C80101 THP_A Configures hold time for efuse program. 0 8 read-write TPGM_INACTIVE Configures pulse time for burning '0' bit. 8 8 read-write TPGM Configures pulse time for burning '1' bit. 16 16 read-write WR_TIM_CONF1 Configurarion register 1 of eFuse programming timing parameters. 0x114 0x20 0x00300001 TSUP_A Configures setup time for efuse program. 0 8 read-write PWR_ON_NUM Configures the power up time for VDDQ. 8 16 read-write WR_TIM_CONF2 Configurarion register 2 of eFuse programming timing parameters. 0x118 0x20 0x00000190 PWR_OFF_NUM Configures the power outage time for VDDQ. 0 16 read-write DATE eFuse version register. 0x1FC 0x20 0x02108190 DATE Stores eFuse version. 0 28 read-write EXTMEM External Memory EXTMEM 0x600C4000 0x0 0x94 registers ICACHE_CTRL This description will be updated in the near future. 0x0 0x20 ICACHE_ENABLE The bit is used to activate the data cache. 0: disable, 1: enable 0 1 read-write ICACHE_CTRL1 This description will be updated in the near future. 0x4 0x20 0x00000003 ICACHE_SHUT_IBUS The bit is used to disable core0 ibus, 0: enable, 1: disable 0 1 read-write ICACHE_SHUT_DBUS The bit is used to disable core1 ibus, 0: enable, 1: disable 1 1 read-write ICACHE_TAG_POWER_CTRL This description will be updated in the near future. 0x8 0x20 0x00000005 ICACHE_TAG_MEM_FORCE_ON The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating. 0 1 read-write ICACHE_TAG_MEM_FORCE_PD The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down 1 1 read-write ICACHE_TAG_MEM_FORCE_PU The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up 2 1 read-write ICACHE_SYNC_CTRL This description will be updated in the near future. 0x28 0x20 0x00000001 ICACHE_INVALIDATE_ENA The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. 0 1 read-write ICACHE_SYNC_DONE The bit is used to indicate invalidate operation is finished. 1 1 read-only ICACHE_SYNC_ADDR This description will be updated in the near future. 0x2C 0x20 ICACHE_SYNC_ADDR The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG. 0 32 read-write ICACHE_SYNC_SIZE This description will be updated in the near future. 0x30 0x20 ICACHE_SYNC_SIZE The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG. 0 23 read-write IBUS_TO_FLASH_START_VADDR This description will be updated in the near future. 0x54 0x20 0x42000000 IBUS_TO_FLASH_START_VADDR The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. 0 32 read-write IBUS_TO_FLASH_END_VADDR This description will be updated in the near future. 0x58 0x20 0x423FFFFF IBUS_TO_FLASH_END_VADDR The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. 0 32 read-write DBUS_TO_FLASH_START_VADDR This description will be updated in the near future. 0x5C 0x20 0x3C000000 DBUS_TO_FLASH_START_VADDR The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. 0 32 read-write DBUS_TO_FLASH_END_VADDR This description will be updated in the near future. 0x60 0x20 0x3C3FFFFF DBUS_TO_FLASH_END_VADDR The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. 0 32 read-write CACHE_ACS_CNT_CLR This description will be updated in the near future. 0x64 0x20 IBUS_ACS_CNT_CLR The bit is used to clear ibus counter. 0 1 write-only DBUS_ACS_CNT_CLR The bit is used to clear dbus counter. 1 1 write-only CACHE_ILG_INT_ENA This description will be updated in the near future. 0x78 0x20 ICACHE_SYNC_OP_FAULT_INT_ENA The bit is used to enable interrupt by sync configurations fault. 0 1 read-write ICACHE_PRELOAD_OP_FAULT_INT_ENA The bit is used to enable interrupt by preload configurations fault. 1 1 read-write MMU_ENTRY_FAULT_INT_ENA The bit is used to enable interrupt by mmu entry fault. 5 1 read-write IBUS_CNT_OVF_INT_ENA The bit is used to enable interrupt by ibus counter overflow. 7 1 read-write DBUS_CNT_OVF_INT_ENA The bit is used to enable interrupt by dbus counter overflow. 8 1 read-write CACHE_ILG_INT_CLR This description will be updated in the near future. 0x7C 0x20 ICACHE_SYNC_OP_FAULT_INT_CLR The bit is used to clear interrupt by sync configurations fault. 0 1 write-only ICACHE_PRELOAD_OP_FAULT_INT_CLR The bit is used to clear interrupt by preload configurations fault. 1 1 write-only MMU_ENTRY_FAULT_INT_CLR The bit is used to clear interrupt by mmu entry fault. 5 1 write-only IBUS_CNT_OVF_INT_CLR The bit is used to clear interrupt by ibus counter overflow. 7 1 write-only DBUS_CNT_OVF_INT_CLR The bit is used to clear interrupt by dbus counter overflow. 8 1 write-only CACHE_ILG_INT_ST This description will be updated in the near future. 0x80 0x20 ICACHE_SYNC_OP_FAULT_ST The bit is used to indicate interrupt by sync configurations fault. 0 1 read-only ICACHE_PRELOAD_OP_FAULT_ST The bit is used to indicate interrupt by preload configurations fault. 1 1 read-only MMU_ENTRY_FAULT_ST The bit is used to indicate interrupt by mmu entry fault. 5 1 read-only IBUS_ACS_CNT_OVF_ST The bit is used to indicate interrupt by ibus access flash/spiram counter overflow. 7 1 read-only IBUS_ACS_MISS_CNT_OVF_ST The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow. 8 1 read-only DBUS_ACS_CNT_OVF_ST The bit is used to indicate interrupt by dbus access flash/spiram counter overflow. 9 1 read-only DBUS_ACS_FLASH_MISS_CNT_OVF_ST The bit is used to indicate interrupt by dbus access flash miss counter overflow. 10 1 read-only CORE0_ACS_CACHE_INT_ENA This description will be updated in the near future. 0x84 0x20 CORE0_IBUS_ACS_MSK_IC_INT_ENA The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access. 0 1 read-write CORE0_IBUS_WR_IC_INT_ENA The bit is used to enable interrupt by ibus trying to write icache 1 1 read-write CORE0_IBUS_REJECT_INT_ENA The bit is used to enable interrupt by authentication fail. 2 1 read-write CORE0_DBUS_ACS_MSK_IC_INT_ENA The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access. 3 1 read-write CORE0_DBUS_REJECT_INT_ENA The bit is used to enable interrupt by authentication fail. 4 1 read-write CORE0_DBUS_WR_IC_INT_ENA The bit is used to enable interrupt by dbus trying to write icache 5 1 read-write CORE0_ACS_CACHE_INT_CLR This description will be updated in the near future. 0x88 0x20 CORE0_IBUS_ACS_MSK_IC_INT_CLR The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access. 0 1 write-only CORE0_IBUS_WR_IC_INT_CLR The bit is used to clear interrupt by ibus trying to write icache 1 1 write-only CORE0_IBUS_REJECT_INT_CLR The bit is used to clear interrupt by authentication fail. 2 1 write-only CORE0_DBUS_ACS_MSK_IC_INT_CLR The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access. 3 1 write-only CORE0_DBUS_REJECT_INT_CLR The bit is used to clear interrupt by authentication fail. 4 1 write-only CORE0_DBUS_WR_IC_INT_CLR The bit is used to clear interrupt by dbus trying to write icache 5 1 write-only CORE0_ACS_CACHE_INT_ST This description will be updated in the near future. 0x8C 0x20 CORE0_IBUS_ACS_MSK_ICACHE_ST The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access. 0 1 read-only CORE0_IBUS_WR_ICACHE_ST The bit is used to indicate interrupt by ibus trying to write icache 1 1 read-only CORE0_IBUS_REJECT_ST The bit is used to indicate interrupt by authentication fail. 2 1 read-only CORE0_DBUS_ACS_MSK_ICACHE_ST The bit is used to indicate interrupt by cpu access icache while the core0_dbus is disabled or icache is disabled which include speculative access. 3 1 read-only CORE0_DBUS_REJECT_ST The bit is used to indicate interrupt by authentication fail. 4 1 read-only CORE0_DBUS_WR_ICACHE_ST The bit is used to indicate interrupt by dbus trying to write icache 5 1 read-only CORE0_DBUS_REJECT_ST This description will be updated in the near future. 0x90 0x20 CORE0_DBUS_ATTR The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. 0 3 read-only CORE0_DBUS_WORLD The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1 3 1 read-only CORE0_DBUS_REJECT_VADDR This description will be updated in the near future. 0x94 0x20 0xFFFFFFFF CORE0_DBUS_VADDR The bits are used to indicate the virtual address of CPU access dbus when authentication fail. 0 32 read-only CORE0_IBUS_REJECT_ST This description will be updated in the near future. 0x98 0x20 CORE0_IBUS_ATTR The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able 0 3 read-only CORE0_IBUS_WORLD The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1 3 1 read-only CORE0_IBUS_REJECT_VADDR This description will be updated in the near future. 0x9C 0x20 0xFFFFFFFF CORE0_IBUS_VADDR The bits are used to indicate the virtual address of CPU access ibus when authentication fail. 0 32 read-only CACHE_MMU_FAULT_CONTENT This description will be updated in the near future. 0xA0 0x20 CACHE_MMU_FAULT_CONTENT The bits are used to indicate the content of mmu entry which cause mmu fault.. 0 8 read-only CACHE_MMU_FAULT_CODE The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache. 10 4 read-only CACHE_MMU_FAULT_VADDR This description will be updated in the near future. 0xA4 0x20 CACHE_MMU_FAULT_VADDR The bits are used to indicate the virtual address which cause mmu fault.. 0 32 read-only CACHE_WRAP_AROUND_CTRL This description will be updated in the near future. 0xA8 0x20 CACHE_FLASH_WRAP_AROUND The bit is used to enable wrap around mode when read data from flash. 0 1 read-write CACHE_MMU_POWER_CTRL This description will be updated in the near future. 0xAC 0x20 0x00000005 CACHE_MMU_MEM_FORCE_ON The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable 0 1 read-write CACHE_MMU_MEM_FORCE_PD The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down 1 1 read-write CACHE_MMU_MEM_FORCE_PU The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up 2 1 read-write CACHE_STATE This description will be updated in the near future. 0xB0 0x20 0x00000001 ICACHE_STATE The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state 0 12 read-only CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE This description will be updated in the near future. 0xB4 0x20 RECORD_DISABLE_DB_ENCRYPT Reserved. 0 1 read-write RECORD_DISABLE_G0CB_DECRYPT Reserved. 1 1 read-write CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON This description will be updated in the near future. 0xB8 0x20 0x00000007 CLK_FORCE_ON_MANUAL_CRYPT The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating. 0 1 read-write CLK_FORCE_ON_AUTO_CRYPT The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating. 1 1 read-write CLK_FORCE_ON_CRYPT The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating. 2 1 read-write CACHE_PRELOAD_INT_CTRL This description will be updated in the near future. 0xBC 0x20 ICACHE_PRELOAD_INT_ST The bit is used to indicate the interrupt by icache pre-load done. 0 1 read-only ICACHE_PRELOAD_INT_ENA The bit is used to enable the interrupt by icache pre-load done. 1 1 read-write ICACHE_PRELOAD_INT_CLR The bit is used to clear the interrupt by icache pre-load done. 2 1 write-only CACHE_SYNC_INT_CTRL This description will be updated in the near future. 0xC0 0x20 ICACHE_SYNC_INT_ST The bit is used to indicate the interrupt by icache sync done. 0 1 read-only ICACHE_SYNC_INT_ENA The bit is used to enable the interrupt by icache sync done. 1 1 read-write ICACHE_SYNC_INT_CLR The bit is used to clear the interrupt by icache sync done. 2 1 write-only CACHE_MMU_OWNER This description will be updated in the near future. 0xC4 0x20 CACHE_MMU_OWNER The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus 0 4 read-write CACHE_CONF_MISC This description will be updated in the near future. 0xC8 0x20 0x00000007 CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT The bit is used to disable checking mmu entry fault by preload operation. 0 1 read-write CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT The bit is used to disable checking mmu entry fault by sync operation. 1 1 read-write CACHE_TRACE_ENA The bit is used to enable cache trace function. 2 1 read-write CACHE_MMU_PAGE_SIZE This bit is used to choose mmu page size. 2:64KB. 1. 32KB. 0: 16KB 3 2 read-write ICACHE_FREEZE This description will be updated in the near future. 0xCC 0x20 ENA The bit is used to enable icache freeze mode 0 1 read-write MODE The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss 1 1 read-write DONE The bit is used to indicate icache freeze success 2 1 read-only ICACHE_ATOMIC_OPERATE_ENA This description will be updated in the near future. 0xD0 0x20 0x00000001 ICACHE_ATOMIC_OPERATE_ENA The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation. 0 1 read-write CACHE_REQUEST This description will be updated in the near future. 0xD4 0x20 BYPASS The bit is used to disable request recording which could cause performance issue 0 1 read-write CLOCK_GATE This description will be updated in the near future. 0x100 0x20 0x00000001 CLK_EN clock gate enable. 0 1 read-write REG_DATE This description will be updated in the near future. 0x3FC 0x20 0x02107050 DATE version information 0 28 read-write GPIO General Purpose Input/Output GPIO 0x60004000 0x0 0x314 registers GPIO 13 GPIO_NMI 14 BT_SELECT GPIO bit select register 0x0 0x20 BT_SEL GPIO bit select register 0 32 read-write OUT GPIO output register 0x4 0x20 DATA_ORIG GPIO output register for GPIO0-24 0 25 read-write OUT_W1TS GPIO output set register 0x8 0x20 OUT_W1TS GPIO output set register for GPIO0-24 0 25 write-only OUT_W1TC GPIO output clear register 0xC 0x20 OUT_W1TC GPIO output clear register for GPIO0-24 0 25 write-only SDIO_SELECT GPIO sdio select register 0x1C 0x20 SDIO_SEL GPIO sdio select register 0 8 read-write ENABLE GPIO output enable register 0x20 0x20 DATA GPIO output enable register for GPIO0-24 0 25 read-write ENABLE_W1TS GPIO output enable set register 0x24 0x20 ENABLE_W1TS GPIO output enable set register for GPIO0-24 0 25 write-only ENABLE_W1TC GPIO output enable clear register 0x28 0x20 ENABLE_W1TC GPIO output enable clear register for GPIO0-24 0 25 write-only STRAP pad strapping register 0x38 0x20 STRAPPING pad strapping register 0 16 read-only IN GPIO input register 0x3C 0x20 DATA_NEXT GPIO input register for GPIO0-24 0 25 read-only STATUS GPIO interrupt status register 0x44 0x20 INTERRUPT GPIO interrupt status register for GPIO0-24 0 25 read-write STATUS_W1TS GPIO interrupt status set register 0x48 0x20 STATUS_W1TS GPIO interrupt status set register for GPIO0-24 0 25 write-only STATUS_W1TC GPIO interrupt status clear register 0x4C 0x20 STATUS_W1TC GPIO interrupt status clear register for GPIO0-24 0 25 write-only PCPU_INT GPIO PRO_CPU interrupt status register 0x5C 0x20 PROCPU_INT GPIO PRO_CPU interrupt status register for GPIO0-24 0 25 read-only PCPU_NMI_INT GPIO PRO_CPU(not shielded) interrupt status register 0x60 0x20 PROCPU_NMI_INT GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-24 0 25 read-only CPUSDIO_INT GPIO CPUSDIO interrupt status register 0x64 0x20 SDIO_INT GPIO CPUSDIO interrupt status register for GPIO0-24 0 25 read-only 25 0x4 0-24 PIN%s GPIO pin configuration register 0x74 0x20 SYNC2_BYPASS set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. 0 2 read-write PAD_DRIVER set this bit to select pad driver. 1:open-drain. 0:normal. 2 1 read-write SYNC1_BYPASS set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. 3 2 read-write INT_TYPE set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level 7 3 read-write WAKEUP_ENABLE set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 10 1 read-write CONFIG reserved 11 2 read-write INT_ENA set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. 13 5 read-write STATUS_NEXT GPIO interrupt source register 0x14C 0x20 STATUS_INTERRUPT_NEXT GPIO interrupt source register for GPIO0-24 0 26 read-only 128 0x4 0-127 FUNC%s_IN_SEL_CFG GPIO input function configuration register 0x154 0x20 IN_SEL set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 5 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 5 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 6 1 read-write 25 0x4 0-24 FUNC%s_OUT_SEL_CFG GPIO output function select register 0x554 0x20 0x00000080 OUT_SEL The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. 0 8 read-write INV_SEL set this bit to invert output signal.1:invert.0:not invert. 8 1 read-write OEN_SEL set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. 9 1 read-write OEN_INV_SEL set this bit to invert output enable signal.1:invert.0:not invert. 10 1 read-write CLOCK_GATE GPIO clock gate register 0x62C 0x20 0x00000001 CLK_EN set this bit to enable GPIO clock gate 0 1 read-write REG_DATE GPIO version register 0x6FC 0x20 0x02106190 REG_DATE version register 0 28 read-write I2C0 I2C (Inter-Integrated Circuit) Controller 0 I2C 0x60013000 0x0 0x88 registers I2C_MST 11 I2C_EXT0 22 SCL_LOW_PERIOD Configures the low level width of the SCL Clock 0x0 0x20 SCL_LOW_PERIOD This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles. 0 9 read-write CTR Transmission setting 0x4 0x20 0x0000020B SDA_FORCE_OUT 0: direct output, 1: open drain output. 0 1 read-write SCL_FORCE_OUT 0: direct output, 1: open drain output. 1 1 read-write SAMPLE_SCL_LEVEL This register is used to select the sample mode. 1: sample SDA data on the SCL low level. 0: sample SDA data on the SCL high level. 2 1 read-write RX_FULL_ACK_LEVEL This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. 3 1 read-write MS_MODE Set this bit to configure the module as an I2C Master. Clear this bit to configure the module as an I2C Slave. 4 1 read-write TRANS_START Set this bit to start sending the data in txfifo. 5 1 write-only TX_LSB_FIRST This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit. 6 1 read-write RX_LSB_FIRST This bit is used to control the storage mode for received data. 1: receive data from the least significant bit, 0: receive data from the most significant bit. 7 1 read-write CLK_EN Reserved 8 1 read-write ARBITRATION_EN This is the enable bit for arbitration_lost. 9 1 read-write FSM_RST This register is used to reset the scl FMS. 10 1 write-only CONF_UPGATE synchronization bit 11 1 write-only SLV_TX_AUTO_START_EN This is the enable bit for slave to send data automatically 12 1 read-write SR Describe I2C work status. 0x8 0x20 RESP_REC The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. 0 1 read-only ARB_LOST When the I2C controller loses control of SCL line, this register changes to 1. 3 1 read-only BUS_BUSY 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. 4 1 read-only RXFIFO_CNT This field represents the amount of data needed to be sent. 8 5 read-only TXFIFO_CNT This field stores the amount of received data in RAM. 18 5 read-only SCL_MAIN_STATE_LAST This field indicates the states of the I2C module state machine. 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK 24 3 read-only SCL_STATE_LAST This field indicates the states of the state machine used to produce SCL. 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop 28 3 read-only TO Setting time out control for receiving data. 0xC 0x20 0x00000010 TIME_OUT_VALUE This register is used to configure the timeout for receiving a data bit in APB clock cycles. 0 5 read-write TIME_OUT_EN This is the enable bit for time out control. 5 1 read-write FIFO_ST FIFO status register. 0x14 0x20 RXFIFO_RADDR This is the offset address of the APB reading from rxfifo 0 4 read-only RXFIFO_WADDR This is the offset address of i2c module receiving data and writing to rxfifo. 5 4 read-only TXFIFO_RADDR This is the offset address of i2c module reading from txfifo. 10 4 read-only TXFIFO_WADDR This is the offset address of APB bus writing to txfifo. 15 4 read-only FIFO_CONF FIFO configuration register. 0x18 0x20 0x00004046 RXFIFO_WM_THRHD The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. 0 4 read-write TXFIFO_WM_THRHD The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. 5 4 read-write NONFIFO_EN Set this bit to enable APB nonfifo access. 10 1 read-write RX_FIFO_RST Set this bit to reset rx-fifo. 12 1 read-write TX_FIFO_RST Set this bit to reset tx-fifo. 13 1 read-write FIFO_PRT_EN The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. 14 1 read-write DATA Rx FIFO read data. 0x1C 0x20 FIFO_RDATA The value of rx FIFO read data. 0 8 read-write INT_RAW Raw interrupt status 0x20 0x20 0x00000002 RXFIFO_WM_INT_RAW The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. 0 1 read-only TXFIFO_WM_INT_RAW The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. 1 1 read-only RXFIFO_OVF_INT_RAW The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. 2 1 read-only END_DETECT_INT_RAW The raw interrupt bit for the I2C_END_DETECT_INT interrupt. 3 1 read-only BYTE_TRANS_DONE_INT_RAW The raw interrupt bit for the I2C_END_DETECT_INT interrupt. 4 1 read-only ARBITRATION_LOST_INT_RAW The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. 5 1 read-only MST_TXFIFO_UDF_INT_RAW The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. 6 1 read-only TRANS_COMPLETE_INT_RAW The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. 7 1 read-only TIME_OUT_INT_RAW The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. 8 1 read-only TRANS_START_INT_RAW The raw interrupt bit for the I2C_TRANS_START_INT interrupt. 9 1 read-only NACK_INT_RAW The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. 10 1 read-only TXFIFO_OVF_INT_RAW The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. 11 1 read-only RXFIFO_UDF_INT_RAW The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. 12 1 read-only SCL_ST_TO_INT_RAW The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. 13 1 read-only SCL_MAIN_ST_TO_INT_RAW The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. 14 1 read-only DET_START_INT_RAW The raw interrupt bit for I2C_DET_START_INT interrupt. 15 1 read-only INT_CLR Interrupt clear bits 0x24 0x20 RXFIFO_WM_INT_CLR Set this bit to clear I2C_RXFIFO_WM_INT interrupt. 0 1 write-only TXFIFO_WM_INT_CLR Set this bit to clear I2C_TXFIFO_WM_INT interrupt. 1 1 write-only RXFIFO_OVF_INT_CLR Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. 2 1 write-only END_DETECT_INT_CLR Set this bit to clear the I2C_END_DETECT_INT interrupt. 3 1 write-only BYTE_TRANS_DONE_INT_CLR Set this bit to clear the I2C_END_DETECT_INT interrupt. 4 1 write-only ARBITRATION_LOST_INT_CLR Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. 5 1 write-only MST_TXFIFO_UDF_INT_CLR Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. 6 1 write-only TRANS_COMPLETE_INT_CLR Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. 7 1 write-only TIME_OUT_INT_CLR Set this bit to clear the I2C_TIME_OUT_INT interrupt. 8 1 write-only TRANS_START_INT_CLR Set this bit to clear the I2C_TRANS_START_INT interrupt. 9 1 write-only NACK_INT_CLR Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. 10 1 write-only TXFIFO_OVF_INT_CLR Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. 11 1 write-only RXFIFO_UDF_INT_CLR Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. 12 1 write-only SCL_ST_TO_INT_CLR Set this bit to clear I2C_SCL_ST_TO_INT interrupt. 13 1 write-only SCL_MAIN_ST_TO_INT_CLR Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. 14 1 write-only DET_START_INT_CLR Set this bit to clear I2C_DET_START_INT interrupt. 15 1 write-only INT_ENA Interrupt enable bits 0x28 0x20 RXFIFO_WM_INT_ENA The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. 0 1 read-write TXFIFO_WM_INT_ENA The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. 1 1 read-write RXFIFO_OVF_INT_ENA The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. 2 1 read-write END_DETECT_INT_ENA The interrupt enable bit for the I2C_END_DETECT_INT interrupt. 3 1 read-write BYTE_TRANS_DONE_INT_ENA The interrupt enable bit for the I2C_END_DETECT_INT interrupt. 4 1 read-write ARBITRATION_LOST_INT_ENA The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. 5 1 read-write MST_TXFIFO_UDF_INT_ENA The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. 6 1 read-write TRANS_COMPLETE_INT_ENA The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. 7 1 read-write TIME_OUT_INT_ENA The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. 8 1 read-write TRANS_START_INT_ENA The interrupt enable bit for the I2C_TRANS_START_INT interrupt. 9 1 read-write NACK_INT_ENA The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. 10 1 read-write TXFIFO_OVF_INT_ENA The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. 11 1 read-write RXFIFO_UDF_INT_ENA The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. 12 1 read-write SCL_ST_TO_INT_ENA The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. 13 1 read-write SCL_MAIN_ST_TO_INT_ENA The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. 14 1 read-write DET_START_INT_ENA The interrupt enable bit for I2C_DET_START_INT interrupt. 15 1 read-write INT_STATUS Status of captured I2C communication events 0x2C 0x20 RXFIFO_WM_INT_ST The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. 0 1 read-only TXFIFO_WM_INT_ST The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. 1 1 read-only RXFIFO_OVF_INT_ST The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. 2 1 read-only END_DETECT_INT_ST The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. 3 1 read-only BYTE_TRANS_DONE_INT_ST The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. 4 1 read-only ARBITRATION_LOST_INT_ST The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. 5 1 read-only MST_TXFIFO_UDF_INT_ST The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. 6 1 read-only TRANS_COMPLETE_INT_ST The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. 7 1 read-only TIME_OUT_INT_ST The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. 8 1 read-only TRANS_START_INT_ST The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. 9 1 read-only NACK_INT_ST The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. 10 1 read-only TXFIFO_OVF_INT_ST The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. 11 1 read-only RXFIFO_UDF_INT_ST The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. 12 1 read-only SCL_ST_TO_INT_ST The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. 13 1 read-only SCL_MAIN_ST_TO_INT_ST The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. 14 1 read-only DET_START_INT_ST The masked interrupt status bit for I2C_DET_START_INT interrupt. 15 1 read-only SDA_HOLD Configures the hold time after a negative SCL edge. 0x30 0x20 TIME This register is used to configure the time to hold the data after the negative edge of SCL, in I2C module clock cycles. 0 9 read-write SDA_SAMPLE Configures the sample time after a positive SCL edge. 0x34 0x20 TIME This register is used to configure for how long SDA is sampled, in I2C module clock cycles. 0 9 read-write SCL_HIGH_PERIOD Configures the high level width of SCL 0x38 0x20 SCL_HIGH_PERIOD This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles. 0 9 read-write SCL_WAIT_HIGH_PERIOD This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles. 9 7 read-write SCL_START_HOLD Configures the delay between the SDA and SCL negative edge for a start condition 0x40 0x20 0x00000008 TIME This register is used to configure the time between the negative edge of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles. 0 9 read-write SCL_RSTART_SETUP Configures the delay between the positive edge of SCL and the negative edge of SDA 0x44 0x20 0x00000008 TIME This register is used to configure the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles. 0 9 read-write SCL_STOP_HOLD Configures the delay after the SCL clock edge for a stop condition 0x48 0x20 0x00000008 TIME This register is used to configure the delay after the STOP condition, in I2C module clock cycles. 0 9 read-write SCL_STOP_SETUP Configures the delay between the SDA and SCL positive edge for a stop condition 0x4C 0x20 0x00000008 TIME This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles. 0 9 read-write FILTER_CFG SCL and SDA filter configuration register 0x50 0x20 0x00000300 SCL_FILTER_THRES When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse. 0 4 read-write SDA_FILTER_THRES When a pulse on the SDA input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse. 4 4 read-write SCL_FILTER_EN This is the filter enable bit for SCL. 8 1 read-write SDA_FILTER_EN This is the filter enable bit for SDA. 9 1 read-write CLK_CONF I2C CLK configuration register 0x54 0x20 0x00200000 SCLK_DIV_NUM the integral part of the fractional divisor for i2c module 0 8 read-write SCLK_DIV_A the numerator of the fractional part of the fractional divisor for i2c module 8 6 read-write SCLK_DIV_B the denominator of the fractional part of the fractional divisor for i2c module 14 6 read-write SCLK_SEL The clock selection for i2c module:0-XTAL,1-CLK_8MHz. 20 1 read-write SCLK_ACTIVE The clock switch for i2c module 21 1 read-write 8 0x4 0-7 COMD%s I2C command register %s 0x58 0x20 COMMAND This is the content of command 0. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more Information. 0 14 read-write COMMAND_DONE When command 0 is done in I2C Master mode, this bit changes to high level. 31 1 read-write SCL_ST_TIME_OUT SCL status time out register 0x78 0x20 0x00000010 SCL_ST_TO_I2C The threshold value of SCL_FSM state unchanged period. It should be o more than 23 0 5 read-write SCL_MAIN_ST_TIME_OUT SCL main status time out register 0x7C 0x20 0x00000010 SCL_MAIN_ST_TO_I2C The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 0 5 read-write SCL_SP_CONF Power configuration register 0x80 0x20 SCL_RST_SLV_EN When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]. 0 1 read-write SCL_RST_SLV_NUM Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. 1 5 read-write SCL_PD_EN The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. 6 1 read-write SDA_PD_EN The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. 7 1 read-write DATE Version register 0xF8 0x20 0x02106243 DATE This is the the version register. 0 32 read-write TXFIFO_START_ADDR I2C TXFIFO base address register 0x100 0x20 TXFIFO_START_ADDR This is the I2C txfifo first address. 0 32 read-only RXFIFO_START_ADDR I2C RXFIFO base address register 0x180 0x20 RXFIFO_START_ADDR This is the I2C rxfifo first address. 0 32 read-only INTERRUPT_CORE0 Interrupt Controller (Core 0) INTERRUPT_CORE0 0x600C2000 0x0 0x150 registers WIFI_MAC 0 WIFI_MAC_NMI 1 WIFI_PWR 2 WIFI_BB 3 BT_MAC 4 BT_BB 5 BT_BB_NMI 6 LP_TIMER 7 COEX 8 BLE_TIMER 9 BLE_SEC 10 CACHE_IA 25 ICACHE_PRELOAD0 30 ICACHE_SYNC0 31 ECC 35 FROM_CPU_INTR0 36 FROM_CPU_INTR1 37 FROM_CPU_INTR2 38 FROM_CPU_INTR3 39 ETS_CORE0_PIF_PMS_SIZE 41 MAC_INTR_MAP register description 0x0 0x20 WIFI_MAC_INT_MAP Need add description 0 5 read-write WIFI_MAC_NMI_MAP register description 0x4 0x20 WIFI_MAC_NMI_MAP Need add description 0 5 read-write WIFI_PWR_INT_MAP register description 0x8 0x20 WIFI_PWR_INT_MAP Need add description 0 5 read-write WIFI_BB_INT_MAP register description 0xC 0x20 WIFI_BB_INT_MAP Need add description 0 5 read-write BT_MAC_INT_MAP register description 0x10 0x20 BT_MAC_INT_MAP Need add description 0 5 read-write BT_BB_INT_MAP register description 0x14 0x20 BT_BB_INT_MAP Need add description 0 5 read-write BT_BB_NMI_MAP register description 0x18 0x20 BT_BB_NMI_MAP Need add description 0 5 read-write LP_TIMER_INT_MAP register description 0x1C 0x20 LP_TIMER_INT_MAP Need add description 0 5 read-write COEX_INT_MAP register description 0x20 0x20 COEX_INT_MAP Need add description 0 5 read-write BLE_TIMER_INT_MAP register description 0x24 0x20 BLE_TIMER_INT_MAP Need add description 0 5 read-write BLE_SEC_INT_MAP register description 0x28 0x20 BLE_SEC_INT_MAP Need add description 0 5 read-write I2C_MST_INT_MAP register description 0x2C 0x20 I2C_MST_INT_MAP Need add description 0 5 read-write APB_CTRL_INTR_MAP register description 0x30 0x20 APB_CTRL_INTR_MAP Need add description 0 5 read-write GPIO_INTERRUPT_PRO_MAP register description 0x34 0x20 GPIO_INTERRUPT_PRO_MAP Need add description 0 5 read-write GPIO_INTERRUPT_PRO_NMI_MAP register description 0x38 0x20 GPIO_INTERRUPT_PRO_NMI_MAP Need add description 0 5 read-write SPI_INTR_1_MAP register description 0x3C 0x20 SPI_INTR_1_MAP Need add description 0 5 read-write SPI_INTR_2_MAP register description 0x40 0x20 SPI_INTR_2_MAP Need add description 0 5 read-write UART_INTR_MAP register description 0x44 0x20 UART_INTR_MAP Need add description 0 5 read-write UART1_INTR_MAP register description 0x48 0x20 UART1_INTR_MAP Need add description 0 5 read-write LEDC_INT_MAP register description 0x4C 0x20 LEDC_INT_MAP Need add description 0 5 read-write EFUSE_INT_MAP register description 0x50 0x20 EFUSE_INT_MAP Need add description 0 5 read-write RTC_CORE_INTR_MAP register description 0x54 0x20 RTC_CORE_INTR_MAP Need add description 0 5 read-write I2C_EXT0_INTR_MAP register description 0x58 0x20 I2C_EXT0_INTR_MAP Need add description 0 5 read-write TG_T0_INT_MAP register description 0x5C 0x20 TG_T0_INT_MAP Need add description 0 5 read-write TG_WDT_INT_MAP register description 0x60 0x20 TG_WDT_INT_MAP Need add description 0 5 read-write CACHE_IA_INT_MAP register description 0x64 0x20 CACHE_IA_INT_MAP Need add description 0 5 read-write SYSTIMER_TARGET0_INT_MAP register description 0x68 0x20 SYSTIMER_TARGET0_INT_MAP Need add description 0 5 read-write SYSTIMER_TARGET1_INT_MAP register description 0x6C 0x20 SYSTIMER_TARGET1_INT_MAP Need add description 0 5 read-write SYSTIMER_TARGET2_INT_MAP register description 0x70 0x20 SYSTIMER_TARGET2_INT_MAP Need add description 0 5 read-write SPI_MEM_REJECT_INTR_MAP register description 0x74 0x20 SPI_MEM_REJECT_INTR_MAP Need add description 0 5 read-write ICACHE_PRELOAD_INT_MAP register description 0x78 0x20 ICACHE_PRELOAD_INT_MAP Need add description 0 5 read-write ICACHE_SYNC_INT_MAP register description 0x7C 0x20 ICACHE_SYNC_INT_MAP Need add description 0 5 read-write APB_ADC_INT_MAP register description 0x80 0x20 APB_ADC_INT_MAP Need add description 0 5 read-write DMA_CH0_INT_MAP register description 0x84 0x20 DMA_CH0_INT_MAP Need add description 0 5 read-write SHA_INT_MAP register description 0x88 0x20 SHA_INT_MAP Need add description 0 5 read-write ECC_INT_MAP register description 0x8C 0x20 ECC_INT_MAP Need add description 0 5 read-write CPU_INTR_FROM_CPU_0_MAP register description 0x90 0x20 CPU_INTR_FROM_CPU_0_MAP Need add description 0 5 read-write CPU_INTR_FROM_CPU_1_MAP register description 0x94 0x20 CPU_INTR_FROM_CPU_1_MAP Need add description 0 5 read-write CPU_INTR_FROM_CPU_2_MAP register description 0x98 0x20 CPU_INTR_FROM_CPU_2_MAP Need add description 0 5 read-write CPU_INTR_FROM_CPU_3_MAP register description 0x9C 0x20 CPU_INTR_FROM_CPU_3_MAP Need add description 0 5 read-write ASSIST_DEBUG_INTR_MAP register description 0xA0 0x20 ASSIST_DEBUG_INTR_MAP Need add description 0 5 read-write CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP register description 0xA4 0x20 CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP Need add description 0 5 read-write CACHE_CORE0_ACS_INT_MAP register description 0xA8 0x20 CACHE_CORE0_ACS_INT_MAP Need add description 0 5 read-write INTR_STATUS_REG_0 register description 0xAC 0x20 INTR_STATUS_0 Need add description 0 32 read-only INTR_STATUS_REG_1 register description 0xB0 0x20 INTR_STATUS_1 Need add description 0 32 read-only CLOCK_GATE register description 0xB4 0x20 0x00000001 REG_CLK_EN Need add description 0 1 read-write CPU_INT_ENABLE register description 0xB8 0x20 CPU_INT_ENABLE Need add description 0 32 read-write CPU_INT_TYPE register description 0xBC 0x20 CPU_INT_TYPE Need add description 0 32 read-write CPU_INT_CLEAR register description 0xC0 0x20 CPU_INT_CLEAR Need add description 0 32 read-write CPU_INT_EIP_STATUS register description 0xC4 0x20 CPU_INT_EIP_STATUS Need add description 0 32 read-only CPU_INT_PRI_0 register description 0xC8 0x20 CPU_PRI_0_MAP Need add description 0 4 read-write CPU_INT_PRI_1 register description 0xCC 0x20 CPU_PRI_1_MAP Need add description 0 4 read-write CPU_INT_PRI_2 register description 0xD0 0x20 CPU_PRI_2_MAP Need add description 0 4 read-write CPU_INT_PRI_3 register description 0xD4 0x20 CPU_PRI_3_MAP Need add description 0 4 read-write CPU_INT_PRI_4 register description 0xD8 0x20 CPU_PRI_4_MAP Need add description 0 4 read-write CPU_INT_PRI_5 register description 0xDC 0x20 CPU_PRI_5_MAP Need add description 0 4 read-write CPU_INT_PRI_6 register description 0xE0 0x20 CPU_PRI_6_MAP Need add description 0 4 read-write CPU_INT_PRI_7 register description 0xE4 0x20 CPU_PRI_7_MAP Need add description 0 4 read-write CPU_INT_PRI_8 register description 0xE8 0x20 CPU_PRI_8_MAP Need add description 0 4 read-write CPU_INT_PRI_9 register description 0xEC 0x20 CPU_PRI_9_MAP Need add description 0 4 read-write CPU_INT_PRI_10 register description 0xF0 0x20 CPU_PRI_10_MAP Need add description 0 4 read-write CPU_INT_PRI_11 register description 0xF4 0x20 CPU_PRI_11_MAP Need add description 0 4 read-write CPU_INT_PRI_12 register description 0xF8 0x20 CPU_PRI_12_MAP Need add description 0 4 read-write CPU_INT_PRI_13 register description 0xFC 0x20 CPU_PRI_13_MAP Need add description 0 4 read-write CPU_INT_PRI_14 register description 0x100 0x20 CPU_PRI_14_MAP Need add description 0 4 read-write CPU_INT_PRI_15 register description 0x104 0x20 CPU_PRI_15_MAP Need add description 0 4 read-write CPU_INT_PRI_16 register description 0x108 0x20 CPU_PRI_16_MAP Need add description 0 4 read-write CPU_INT_PRI_17 register description 0x10C 0x20 CPU_PRI_17_MAP Need add description 0 4 read-write CPU_INT_PRI_18 register description 0x110 0x20 CPU_PRI_18_MAP Need add description 0 4 read-write CPU_INT_PRI_19 register description 0x114 0x20 CPU_PRI_19_MAP Need add description 0 4 read-write CPU_INT_PRI_20 register description 0x118 0x20 CPU_PRI_20_MAP Need add description 0 4 read-write CPU_INT_PRI_21 register description 0x11C 0x20 CPU_PRI_21_MAP Need add description 0 4 read-write CPU_INT_PRI_22 register description 0x120 0x20 CPU_PRI_22_MAP Need add description 0 4 read-write CPU_INT_PRI_23 register description 0x124 0x20 CPU_PRI_23_MAP Need add description 0 4 read-write CPU_INT_PRI_24 register description 0x128 0x20 CPU_PRI_24_MAP Need add description 0 4 read-write CPU_INT_PRI_25 register description 0x12C 0x20 CPU_PRI_25_MAP Need add description 0 4 read-write CPU_INT_PRI_26 register description 0x130 0x20 CPU_PRI_26_MAP Need add description 0 4 read-write CPU_INT_PRI_27 register description 0x134 0x20 CPU_PRI_27_MAP Need add description 0 4 read-write CPU_INT_PRI_28 register description 0x138 0x20 CPU_PRI_28_MAP Need add description 0 4 read-write CPU_INT_PRI_29 register description 0x13C 0x20 CPU_PRI_29_MAP Need add description 0 4 read-write CPU_INT_PRI_30 register description 0x140 0x20 CPU_PRI_30_MAP Need add description 0 4 read-write CPU_INT_PRI_31 register description 0x144 0x20 CPU_PRI_31_MAP Need add description 0 4 read-write CPU_INT_THRESH register description 0x148 0x20 CPU_INT_THRESH Need add description 0 4 read-write INTERRUPT_REG_DATE register description 0x7FC 0x20 0x02108190 INTERRUPT_REG_DATE Need add description 0 28 read-write IO_MUX Input/Output Multiplexer IO_MUX 0x60009000 0x0 0x5C registers PIN_CTRL Clock Output Configuration Register 0x0 0x20 0x000007FF CLK_OUT1 If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals. 0 4 read-write CLK_OUT2 If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals. 4 4 read-write CLK_OUT3 If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals. 8 4 read-write 21 0x4 GPIO%s IO MUX Configure Register for pad XTAL_32K_P 0x4 0x20 0x00000B00 MCU_OE Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. 1 1 read-write MCU_WPD Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled. 15 1 read-write DATE IO MUX Version Control Register 0xFC 0x20 0x02106190 REG_DATE Version control register 0 28 read-write LEDC LED Control PWM (Pulse Width Modulation) LEDC 0x60019000 0x0 0xB0 registers LEDC 19 6 0x14 CH%s_CONF0 Configuration register 0 for channel %s 0x0 0x20 TIMER_SEL This field is used to select one of timers for channel %s. 0: select timer0; 1: select timer1; 2: select timer2; 3: select timer3 0 2 read-write SIG_OUT_EN Set this bit to enable signal output on channel %s. 2 1 read-write IDLE_LV This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0). 3 1 read-write PARA_UP This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware. 4 1 write-only OVF_NUM This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. 5 10 read-write OVF_CNT_EN This bit is used to enable the ovf_cnt of channel %s. 15 1 read-write OVF_CNT_RESET Set this bit to reset the ovf_cnt of channel %s. 16 1 write-only 6 0x14 CH%s_HPOINT High point register for channel %s 0x4 0x20 HPOINT The output value changes to high when the selected timers has reached the value specified by this register. 0 14 read-write 6 0x14 CH%s_DUTY Initial duty cycle for channel %s 0x8 0x20 DUTY This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint. 0 19 read-write 6 0x14 CH%s_CONF1 Configuration register 1 for channel %s 0xC 0x20 0x40000000 DUTY_SCALE This register is used to configure the changing step scale of duty on channel %s. 0 10 read-write DUTY_CYCLE The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s. 10 10 read-write DUTY_NUM This register is used to control the number of times the duty cycle will be changed. 20 10 read-write DUTY_INC This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase; 0: Decrease. 30 1 read-write DUTY_START Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. 31 1 read-write 6 0x14 CH%s_DUTY_R Current duty cycle for channel %s 0x10 0x20 DUTY_CH0_R This register stores the current duty of output signal on channel %s. 0 19 read-only 4 0x8 TIMER%s_CONF Timer %s configuration 0xA0 0x20 0x00800000 DUTY_RES This register is used to control the range of the counter in timer %s. 0 4 read-write CLK_DIV This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part. 4 18 read-write PAUSE This bit is used to suspend the counter in timer %s. 22 1 read-write RST This bit is used to reset timer %s. The counter will show 0 after reset. 23 1 read-write TICK_SEL This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK 24 1 read-write PARA_UP Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. 25 1 write-only 4 0x8 TIMER%s_VALUE Timer %s current counter value 0xA4 0x20 CNT This register stores the current counter value of timer %s. 0 14 read-only INT_RAW Raw interrupt status 0xC0 0x20 OVF_INT_RAW Triggered when the timer0 has reached its maximum counter value. 0 1 read-write TIMER1_OVF_INT_RAW Triggered when the timer1 has reached its maximum counter value. 1 1 read-write TIMER2_OVF_INT_RAW Triggered when the timer2 has reached its maximum counter value. 2 1 read-write TIMER3_OVF_INT_RAW Triggered when the timer3 has reached its maximum counter value. 3 1 read-write DUTY_CHNG_END_CH0_INT_RAW Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. 4 1 read-write DUTY_CHNG_END_CH1_INT_RAW Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. 5 1 read-write DUTY_CHNG_END_CH2_INT_RAW Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. 6 1 read-write DUTY_CHNG_END_CH3_INT_RAW Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. 7 1 read-write DUTY_CHNG_END_CH4_INT_RAW Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. 8 1 read-write DUTY_CHNG_END_CH5_INT_RAW Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. 9 1 read-write OVF_CNT_CH0_INT_RAW Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. 10 1 read-write OVF_CNT_CH1_INT_RAW Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. 11 1 read-write OVF_CNT_CH2_INT_RAW Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. 12 1 read-write OVF_CNT_CH3_INT_RAW Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. 13 1 read-write OVF_CNT_CH4_INT_RAW Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. 14 1 read-write OVF_CNT_CH5_INT_RAW Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. 15 1 read-write INT_ST Masked interrupt status 0xC4 0x20 OVF_INT_ST This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. 0 1 read-only TIMER1_OVF_INT_ST This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. 1 1 read-only TIMER2_OVF_INT_ST This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. 2 1 read-only TIMER3_OVF_INT_ST This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. 3 1 read-only DUTY_CHNG_END_CH0_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1. 4 1 read-only DUTY_CHNG_END_CH1_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1. 5 1 read-only DUTY_CHNG_END_CH2_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1. 6 1 read-only DUTY_CHNG_END_CH3_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1. 7 1 read-only DUTY_CHNG_END_CH4_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1. 8 1 read-only DUTY_CHNG_END_CH5_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1. 9 1 read-only OVF_CNT_CH0_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. 10 1 read-only OVF_CNT_CH1_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. 11 1 read-only OVF_CNT_CH2_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. 12 1 read-only OVF_CNT_CH3_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. 13 1 read-only OVF_CNT_CH4_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. 14 1 read-only OVF_CNT_CH5_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. 15 1 read-only INT_ENA Interrupt enable bits 0xC8 0x20 OVF_INT_ENA The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. 0 1 read-write TIMER1_OVF_INT_ENA The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. 1 1 read-write TIMER2_OVF_INT_ENA The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. 2 1 read-write TIMER3_OVF_INT_ENA The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. 3 1 read-write DUTY_CHNG_END_CH0_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. 4 1 read-write DUTY_CHNG_END_CH1_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. 5 1 read-write DUTY_CHNG_END_CH2_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. 6 1 read-write DUTY_CHNG_END_CH3_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. 7 1 read-write DUTY_CHNG_END_CH4_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. 8 1 read-write DUTY_CHNG_END_CH5_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. 9 1 read-write OVF_CNT_CH0_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. 10 1 read-write OVF_CNT_CH1_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. 11 1 read-write OVF_CNT_CH2_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. 12 1 read-write OVF_CNT_CH3_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. 13 1 read-write OVF_CNT_CH4_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. 14 1 read-write OVF_CNT_CH5_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. 15 1 read-write INT_CLR Interrupt clear bits 0xCC 0x20 OVF_INT_CLR Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. 0 1 write-only TIMER1_OVF_INT_CLR Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. 1 1 write-only TIMER2_OVF_INT_CLR Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. 2 1 write-only TIMER3_OVF_INT_CLR Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. 3 1 write-only DUTY_CHNG_END_CH0_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. 4 1 write-only DUTY_CHNG_END_CH1_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. 5 1 write-only DUTY_CHNG_END_CH2_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. 6 1 write-only DUTY_CHNG_END_CH3_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. 7 1 write-only DUTY_CHNG_END_CH4_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. 8 1 write-only DUTY_CHNG_END_CH5_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. 9 1 write-only OVF_CNT_CH0_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. 10 1 write-only OVF_CNT_CH1_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. 11 1 write-only OVF_CNT_CH2_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. 12 1 write-only OVF_CNT_CH3_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. 13 1 write-only OVF_CNT_CH4_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. 14 1 write-only OVF_CNT_CH5_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. 15 1 write-only CONF Global ledc configuration register 0xD0 0x20 APB_CLK_SEL This bit is used to select clock source for the 4 timers . 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK 0 2 read-write CLK_EN This bit is used to control clock. 1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers. 31 1 read-write DATE Version control register 0xFC 0x20 0x19061700 LEDC_DATE This is the version control register. 0 32 read-write MODEM_CLKRST MODEM_CLKRST Peripheral MODEM_CLKRST 0x6004D800 0x0 0x18 registers CLK_CONF 0x0 0x20 CLK_EN . 0 1 read-write MODEM_LP_TIMER_CONF 0x4 0x20 LP_TIMER_SEL_RTC_SLOW . 0 1 read-write LP_TIMER_SEL_8M . 1 1 read-write LP_TIMER_SEL_XTAL . 2 1 read-write LP_TIMER_SEL_XTAL32K . 3 1 read-write LP_TIMER_CLK_DIV_NUM . 4 8 read-write COEX_LP_CLK_CONF 0x8 0x20 COEX_LPCLK_SEL_RTC_SLOW . 0 1 read-write COEX_LPCLK_SEL_8M . 1 1 read-write COEX_LPCLK_SEL_XTAL . 2 1 read-write COEX_LPCLK_SEL_XTAL32K . 3 1 read-write COEX_LPCLK_DIV_NUM . 4 8 read-write BLE_TIMER_CLK_CONF 0xC 0x20 0x00000003 BLETIMER_USE_XTAL . 0 1 read-write BLETIMER_CLK_IS_ACTIVE . 1 1 read-write DATE 0xC 0x20 0x02107270 DATE . 0 28 read-write ETM_CLK_CONF 0x10 0x20 ETM_CLK_SEL . 0 1 read-write ETM_CLK_ACTIVE . 1 1 read-write RNG Hardware Random Number Generator RNG 0x60026000 0x0 0x4 registers DATA Random number data 0xB0 0x20 read-only RTC_CNTL Real-Time Clock Control RTC_CNTL 0x60008000 0x0 0x114 registers RTC_CORE 21 OPTIONS0 register description 0x0 0x20 0x1000A000 SW_STALL_PROCPU_C0 {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU 2 2 read-write SW_PROCPU_RST PRO CPU SW reset 5 1 read-write BB_I2C_FORCE_PD BB_I2C force power down 6 1 read-write BB_I2C_FORCE_PU BB_I2C force power up 7 1 read-write BBPLL_I2C_FORCE_PD BB_PLL _I2C force power down 8 1 read-write BBPLL_I2C_FORCE_PU BB_PLL_I2C force power up 9 1 read-write BBPLL_FORCE_PD BB_PLL force power down 10 1 read-write BBPLL_FORCE_PU BB_PLL force power up 11 1 read-write XTL_FORCE_PD crystall force power down 12 1 read-write XTL_FORCE_PU crystall force power up 13 1 read-write XTL_EN_WAIT wait bias_sleep and current source wakeup 14 4 read-write XTL_EXT_CTR_SEL Need add desc 20 3 read-write ANALOG_FORCE_ISO Need add desc 25 1 read-write ANALOG_FORCE_NOISO Need add desc 28 1 read-write DG_WRAP_FORCE_RST digital wrap force reset in deep sleep 29 1 read-write DG_WRAP_FORCE_NORST digital core force no reset in deep sleep 30 1 read-write SW_SYS_RST SW system reset 31 1 read-write SLP_TIMER0 register description 0x4 0x20 SLP_VAL_LO Need add desc 0 32 read-write SLP_TIMER1 register description 0x8 0x20 SLP_VAL_HI RTC sleep timer high 16 bits 0 16 read-write MAIN_TIMER_ALARM_EN timer alarm enable bit 16 1 read-write TIME_UPDATE register description 0xC 0x20 TIMER_SYS_STALL Enable to record system stall time 27 1 read-write TIMER_XTL_OFF Enable to record 40M XTAL OFF time 28 1 read-write TIMER_SYS_RST enable to record system reset time 29 1 read-write TIME_UPDATE Set 1: to update register with RTC timer 31 1 read-write TIME_LOW0 register description 0x10 0x20 TIMER_VALUE0_LOW RTC timer low 32 bits 0 32 read-write TIME_HIGH0 register description 0x14 0x20 TIMER_VALUE0_HIGH RTC timer high 16 bits 0 16 read-write STATE0 register description 0x18 0x20 SW_CPU_INT rtc software interrupt to main cpu 0 1 read-write SLP_REJECT_CAUSE_CLR clear rtc sleep reject cause 1 1 read-write APB2RTC_BRIDGE_SEL 1: APB to RTC using bridge 22 1 read-write SDIO_ACTIVE_IND SDIO active indication 28 1 read-write SLP_WAKEUP leep wakeup bit 29 1 read-write SLP_REJECT leep reject bit 30 1 read-write SLEEP_EN sleep enable bit 31 1 read-write TIMER1 register description 0x1C 0x20 0x28140403 CPU_STALL_EN CPU stall enable bit 0 1 read-write CPU_STALL_WAIT CPU stall wait cycles in fast_clk_rtc 1 5 read-write CK8M_WAIT CK8M wait cycles in slow_clk_rtc 6 8 read-write XTL_BUF_WAIT XTAL wait cycles in slow_clk_rtc 14 10 read-write PLL_BUF_WAIT PLL wait cycles in slow_clk_rtc 24 8 read-write TIMER2 register description 0x20 0x20 0x01000000 MIN_TIME_CK8M_OFF minimal cycles in slow_clk_rtc for CK8M in power down state 24 8 read-write TIMER4 register description 0x24 0x20 0x10200000 DG_WRAP_WAIT_TIMER Need add desc 16 9 read-write DG_WRAP_POWERUP_TIMER Need add desc 25 7 read-write TIMER5 register description 0x28 0x20 0x00008000 MIN_SLP_VAL minimal sleep cycles in slow_clk_rtc 8 8 read-write ANA_CONF register description 0x2C 0x20 0x00440000 I2C_RESET_POR_FORCE_PD Need add desc 18 1 read-write I2C_RESET_POR_FORCE_PU Need add desc 19 1 read-write SAR_I2C_PU PLLA force power up 22 1 read-write BBPLL_CAL_SLP_START start BBPLL calibration during sleep 25 1 read-write TXRF_I2C_PU 1: TXRF_I2C power up 27 1 read-write RFRX_PBUS_PU 1: RFRX_PBUS power up 28 1 read-write CKGEN_I2C_PU 1: CKGEN_I2C power up 30 1 read-write PLL_I2C_PU Need add desc 31 1 read-write PLLA_FORCE_PD PLLA force power down 23 1 read-write PLLA_FORCE_PU PLLA force power up 24 1 read-write RESET_STATE register description 0x30 0x20 0x00002000 RESET_CAUSE_PROCPU reset cause of PRO CPU 0 6 read-write STAT_VECTOR_SEL_PROCPU PRO CPU state vector sel 13 1 read-write OCD_HALT_ON_RESET_PROCPU PROCPU OcdHaltOnReset 19 1 read-write DRESET_MASK_PROCPU Need add desc 20 1 read-write WAKEUP_STATE register description 0x34 0x20 0x00060000 WAKEUP_ENA wakeup enable bitmap 15 17 read-write INT_ENA_RTC register description 0x38 0x20 SLP_WAKEUP_INT_ENA enable sleep wakeup interrupt 0 1 SLP_REJECT_INT_ENA enable sleep reject interrupt 1 1 WDT_INT_ENA enable RTC WDT interrupt 3 1 BROWN_OUT_INT_ENA enable brown out interrupt 9 1 MAIN_TIMER_INT_ENA enable RTC main timer interrupt 10 1 SWD_INT_ENA enable super watch dog interrupt 15 1 BBPLL_CAL_INT_ENA Need add desc 20 1 INT_RAW_RTC register description 0x3C 0x20 SLP_WAKEUP_INT_RAW sleep wakeup interrupt raw 0 1 read-write SLP_REJECT_INT_RAW sleep reject interrupt raw 1 1 read-write WDT_INT_RAW RTC WDT interrupt raw 3 1 read-write BROWN_OUT_INT_RAW brown out interrupt raw 9 1 read-write MAIN_TIMER_INT_RAW RTC main timer interrupt raw 10 1 read-write SWD_INT_RAW super watch dog interrupt raw 15 1 read-write BBPLL_CAL_INT_RAW Need add desc 20 1 read-write INT_ST_RTC register description 0x40 0x20 SLP_WAKEUP_INT_ST sleep wakeup interrupt state 0 1 read-write SLP_REJECT_INT_ST sleep reject interrupt state 1 1 read-write WDT_INT_ST RTC WDT interrupt state 3 1 read-write BROWN_OUT_INT_ST brown out interrupt state 9 1 read-write MAIN_TIMER_INT_ST RTC main timer interrupt state 10 1 read-write SWD_INT_ST super watch dog interrupt state 15 1 read-write BBPLL_CAL_INT_ST Need add desc 20 1 read-write INT_CLR_RTC register description 0x44 0x20 SLP_WAKEUP_INT_CLR Clear sleep wakeup interrupt state 0 1 read-write SLP_REJECT_INT_CLR Clear sleep reject interrupt state 1 1 read-write WDT_INT_CLR Clear RTC WDT interrupt state 3 1 read-write BROWN_OUT_INT_CLR Clear brown out interrupt state 9 1 read-write MAIN_TIMER_INT_CLR Clear RTC main timer interrupt state 10 1 read-write SWD_INT_CLR Clear super watch dog interrupt state 15 1 read-write BBPLL_CAL_INT_CLR Need add desc 20 1 read-write STORE0 register description 0x48 0x20 SCRATCH0 Need add desc 0 32 read-write STORE1 register description 0x4C 0x20 SCRATCH1 Need add desc 0 32 read-write STORE2 register description 0x50 0x20 SCRATCH2 Need add desc 0 32 read-write STORE3 register description 0x54 0x20 SCRATCH3 Need add desc 0 32 read-write EXT_XTL_CONF register description 0x58 0x20 XTL_EXT_CTR_LV 0: power down XTAL at high level 30 1 read-write XTL_EXT_CTR_EN Need add desc 31 1 read-write EXT_WAKEUP_CONF register description 0x5C 0x20 GPIO_WAKEUP_FILTER enable filter for gpio wakeup event 31 1 read-write SLP_REJECT_CONF register description 0x60 0x20 SLEEP_REJECT_ENA sleep reject enable 12 18 read-write LIGHT_SLP_REJECT_EN enable reject for light sleep 30 1 read-write DEEP_SLP_REJECT_EN enable reject for deep sleep 31 1 read-write CPU_PERIOD_CONF register description 0x64 0x20 CPUSEL_CONF CPU sel option 29 1 read-write CPUPERIOD_SEL Need add desc 30 2 read-write CLK_CONF register description 0x68 0x20 0x11583218 EFUSE_CLK_FORCE_GATING Need add desc 1 1 read-write EFUSE_CLK_FORCE_NOGATING Need add desc 2 1 read-write CK8M_DIV_SEL_VLD used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel 3 1 read-write CK8M_DIV CK8M_D256_OUT divider. 00: div128 4 2 read-write ENB_CK8M disable CK8M and CK8M_D256_OUT 6 1 read-write ENB_CK8M_DIV 1: CK8M_D256_OUT is actually CK8M 7 1 read-write DIG_XTAL32K_EN enable CK_XTAL_32K for digital core (no relationship with RTC core) 8 1 read-write DIG_CLK8M_D256_EN enable CK8M_D256_OUT for digital core (no relationship with RTC core) 9 1 read-write DIG_CLK8M_EN enable CK8M for digital core (no relationship with RTC core) 10 1 read-write CK8M_DIV_SEL divider = reg_ck8m_div_sel + 1 12 3 read-write XTAL_FORCE_NOGATING XTAL force no gating during sleep 15 1 read-write CK8M_FORCE_NOGATING CK8M force no gating during sleep 16 1 read-write CK8M_DFREQ CK8M_DFREQ 17 8 read-write CK8M_FORCE_PD CK8M force power down 25 1 read-write CK8M_FORCE_PU CK8M force power up 26 1 read-write XTAL_GLOBAL_FORCE_GATING Need add desc 27 1 read-write XTAL_GLOBAL_FORCE_NOGATING Need add desc 28 1 read-write FAST_CLK_RTC_SEL fast_clk_rtc sel. 0: XTAL div 4 29 1 read-write ANA_CLK_RTC_SEL Need add desc 30 2 read-write SLOW_CLK_CONF register description 0x6C 0x20 0x00400000 ANA_CLK_DIV_VLD used to sync div bus. clear vld before set reg_rtc_ana_clk_div 22 1 read-write ANA_CLK_DIV Need add desc 23 8 read-write SLOW_CLK_NEXT_EDGE Need add desc 31 1 read-write BIAS_CONF register description 0x70 0x20 0x00010800 DG_VDD_DRV_B_SLP Need add desc 0 8 read-write DG_VDD_DRV_B_SLP_EN Need add desc 8 1 read-write BIAS_BUF_IDLE Need add desc 10 1 read-write BIAS_BUF_WAKE Need add desc 11 1 read-write BIAS_BUF_DEEP_SLP Need add desc 12 1 read-write BIAS_BUF_MONITOR Need add desc 13 1 read-write PD_CUR_DEEP_SLP xpd cur when rtc in sleep_state 14 1 read-write PD_CUR_MONITOR xpd cur when rtc in monitor state 15 1 read-write BIAS_SLEEP_DEEP_SLP bias_sleep when rtc in sleep_state 16 1 read-write BIAS_SLEEP_MONITOR bias_sleep when rtc in monitor state 17 1 read-write DBG_ATTEN_DEEP_SLP DBG_ATTEN when rtc in sleep state 18 4 read-write DBG_ATTEN_MONITOR DBG_ATTEN when rtc in active state 22 4 read-write DBG_ATTEN_ACTIVE Need add desc 26 4 read-write RTC_CNTL register description 0x74 0x20 0x80000000 DIG_REG_CAL_EN Need add desc 7 1 read-write SCK_DCAP SCK_DCAP 14 8 read-write REGULATOR_FORCE_PD RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower ) 30 1 read-write REGULATOR_FORCE_PU Need add desc 31 1 read-write PWC register description 0x78 0x20 PAD_FORCE_HOLD rtc pad force hold 21 1 read-write DIG_PWC register description 0x7C 0x20 0x00100020 VDD_SPI_PWR_DRV Need add desc 0 2 read-write VDD_SPI_PWR_FORCE Need add desc 2 1 read-write VDD_SPI_PD_EN Need add desc 3 1 read-write LSLP_MEM_FORCE_PD memories in digital core force PD in sleep 4 1 read-write LSLP_MEM_FORCE_PU memories in digital core force no PD in sleep 5 1 read-write DG_WRAP_FORCE_PD digital core force power down 19 1 read-write DG_WRAP_FORCE_PU digital core force power up 20 1 read-write DG_WRAP_PD_EN Need add desc 31 1 read-write DIG_ISO register description 0x80 0x20 0x80005080 FORCE_OFF Need add desc 7 1 read-write FORCE_ON Need add desc 8 1 read-write DG_PAD_AUTOHOLD read only register to indicate digital pad auto-hold status 9 1 read-write CLR_DG_PAD_AUTOHOLD wtite only register to clear digital pad auto-hold 10 1 read-write DG_PAD_AUTOHOLD_EN digital pad enable auto-hold 11 1 read-write DG_PAD_FORCE_NOISO digital pad force no ISO 12 1 read-write DG_PAD_FORCE_ISO digital pad force ISO 13 1 read-write DG_PAD_FORCE_UNHOLD digital pad force un-hold 14 1 read-write DG_PAD_FORCE_HOLD digital pad force hold 15 1 read-write DG_WRAP_FORCE_ISO digital core force ISO 30 1 read-write DG_WRAP_FORCE_NOISO Need add desc 31 1 read-write WDTCONFIG0 register description 0x84 0x20 0x00013214 WDT_CHIP_RESET_WIDTH chip reset siginal pulse width 0 8 read-write WDT_CHIP_RESET_EN wdt reset whole chip enable 8 1 read-write WDT_PAUSE_IN_SLP pause WDT in sleep 9 1 read-write WDT_PROCPU_RESET_EN enable WDT reset PRO CPU 11 1 read-write WDT_FLASHBOOT_MOD_EN enable WDT in flash boot 12 1 read-write WDT_SYS_RESET_LENGTH system reset counter length 13 3 read-write WDT_CPU_RESET_LENGTH CPU reset counter length 16 3 read-write WDT_STG3 1: interrupt stage en 19 3 read-write WDT_STG2 1: interrupt stage en 22 3 read-write WDT_STG1 1: interrupt stage en 25 3 read-write WDT_STG0 1: interrupt stage en 28 3 read-write WDT_EN Need add desc 31 1 read-write WDTCONFIG1 register description 0x88 0x20 0x00030D40 WDT_STG0_HOLD Need add desc 0 32 read-write WDTCONFIG2 register description 0x8C 0x20 0x00013880 WDT_STG1_HOLD Need add desc 0 32 read-write WDTCONFIG3 register description 0x90 0x20 0x00000FFF WDT_STG2_HOLD Need add desc 0 32 read-write WDTCONFIG4 register description 0x94 0x20 0x00000FFF WDT_STG3_HOLD Need add desc 0 32 read-write WDTFEED register description 0x98 0x20 WDT_FEED Need add desc 31 1 read-write WDTWPROTECT register description 0x9C 0x20 WDT_WKEY Need add desc 0 32 read-write SWD_CONF register description 0xA0 0x20 0x04B00000 SWD_RESET_FLAG swd reset flag 0 1 read-write SWD_FEED_INT swd interrupt for feeding 1 1 read-write SWD_BYPASS_RST Need add desc 17 1 read-write SWD_SIGNAL_WIDTH adjust signal width send to swd 18 10 read-write SWD_RST_FLAG_CLR reset swd reset flag 28 1 read-write SWD_FEED Sw feed swd 29 1 read-write SWD_DISABLE disabel SWD 30 1 read-write SWD_AUTO_FEED_EN automatically feed swd when int comes 31 1 read-write SWD_WPROTECT register description 0xA4 0x20 SWD_WKEY Need add desc 0 32 read-write SW_CPU_STALL register description 0xA8 0x20 SW_STALL_PROCPU_C1 Need add desc 26 6 read-write STORE4 register description 0xAC 0x20 SCRATCH4 Need add desc 0 32 read-write STORE5 register description 0xB0 0x20 SCRATCH5 Need add desc 0 32 read-write STORE6 register description 0xB4 0x20 SCRATCH6 Need add desc 0 32 read-write STORE7 register description 0xB8 0x20 SCRATCH7 Need add desc 0 32 read-write LOW_POWER_ST register description 0xBC 0x20 XPD_DIG digital wrap power down 8 1 read-write TOUCH_STATE_START touch should start to work 9 1 read-write TOUCH_STATE_SWITCH touch is about to working. Switch rtc main state 10 1 read-write TOUCH_STATE_SLP touch is in sleep state 11 1 read-write TOUCH_STATE_DONE touch is done 12 1 read-write COCPU_STATE_START ulp/cocpu should start to work 13 1 read-write COCPU_STATE_SWITCH ulp/cocpu is about to working. Switch rtc main state 14 1 read-write COCPU_STATE_SLP ulp/cocpu is in sleep state 15 1 read-write COCPU_STATE_DONE ulp/cocpu is done 16 1 read-write MAIN_STATE_XTAL_ISO no use any more 17 1 read-write MAIN_STATE_PLL_ON rtc main state machine is in states that pll should be running 18 1 read-write RDY_FOR_WAKEUP rtc is ready to receive wake up trigger from wake up source 19 1 read-write MAIN_STATE_WAIT_END rtc main state machine has been waited for some cycles 20 1 read-write IN_WAKEUP_STATE rtc main state machine is in the states of wakeup process 21 1 read-write IN_LOW_POWER_STATE rtc main state machine is in the states of low power 22 1 read-write MAIN_STATE_IN_WAIT_8M rtc main state machine is in wait 8m state 23 1 read-write MAIN_STATE_IN_WAIT_PLL rtc main state machine is in wait pll state 24 1 read-write MAIN_STATE_IN_WAIT_XTL rtc main state machine is in wait xtal state 25 1 read-write MAIN_STATE_IN_SLP rtc main state machine is in sleep state 26 1 read-write MAIN_STATE_IN_IDLE rtc main state machine is in idle state 27 1 read-write MAIN_STATE rtc main state machine status 28 4 read-write DIAG0 register description 0xC0 0x20 LOW_POWER_DIAG1 Need add desc 0 32 read-write PAD_HOLD register description 0xC4 0x20 GPIO_PIN0_HOLD Need add desc 0 1 read-write GPIO_PIN1_HOLD Need add desc 1 1 read-write GPIO_PIN2_HOLD Need add desc 2 1 read-write GPIO_PIN3_HOLD Need add desc 3 1 read-write GPIO_PIN4_HOLD Need add desc 4 1 read-write GPIO_PIN5_HOLD Need add desc 5 1 read-write DIG_PAD_HOLD register description 0xC8 0x20 DIG_PAD_HOLD Need add desc 0 32 read-write BROWN_OUT register description 0xCC 0x20 0x43FF0010 BROWN_OUT_INT_WAIT brown out interrupt wait cycles 4 10 read-write BROWN_OUT_CLOSE_FLASH_ENA enable close flash when brown out happens 14 1 read-write BROWN_OUT_PD_RF_ENA enable power down RF when brown out happens 15 1 read-write BROWN_OUT_RST_WAIT brown out reset wait cycles 16 10 read-write BROWN_OUT_RST_ENA enable brown out reset 26 1 read-write BROWN_OUT_RST_SEL 1: 4-pos reset 27 1 read-write BROWN_OUT_ANA_RST_EN Need add desc 28 1 read-write BROWN_OUT_CNT_CLR clear brown out counter 29 1 read-write BROWN_OUT_ENA enable brown out 30 1 read-write DET Need add desc 31 1 read-write TIME_LOW1 register description 0xD0 0x20 TIMER_VALUE1_LOW RTC timer low 32 bits 0 32 read-write TIME_HIGH1 register description 0xD4 0x20 TIMER_VALUE1_HIGH RTC timer high 16 bits 0 16 read-write USB_CONF register description 0xD8 0x20 IO_MUX_RESET_DISABLE Need add desc 18 1 read-write SLP_REJECT_CAUSE register description 0xDC 0x20 REJECT_CAUSE sleep reject cause 0 18 read-write OPTION1 register description 0xE0 0x20 FORCE_DOWNLOAD_BOOT Need add desc 0 1 read-write SLP_WAKEUP_CAUSE register description 0xE4 0x20 WAKEUP_CAUSE sleep wakeup cause 0 17 read-write ULP_CP_TIMER_1 register description 0xE8 0x20 0x0000C800 ULP_CP_TIMER_SLP_CYCLE sleep cycles for ULP-coprocessor timer 8 24 read-write INT_ENA_RTC_W1TS register description 0xEC 0x20 SLP_WAKEUP_INT_ENA_W1TS enable sleep wakeup interrupt 0 1 read-write SLP_REJECT_INT_ENA_W1TS enable sleep reject interrupt 1 1 read-write WDT_INT_ENA_W1TS enable RTC WDT interrupt 3 1 read-write BROWN_OUT_INT_ENA_W1TS enable brown out interrupt 9 1 read-write MAIN_TIMER_INT_ENA_W1TS enable RTC main timer interrupt 10 1 read-write SWD_INT_ENA_W1TS enable super watch dog interrupt 15 1 read-write BBPLL_CAL_INT_ENA_W1TS Need add desc 20 1 read-write INT_ENA_RTC_W1TC register description 0xF0 0x20 SLP_WAKEUP_INT_ENA_W1TC enable sleep wakeup interrupt 0 1 read-write SLP_REJECT_INT_ENA_W1TC enable sleep reject interrupt 1 1 read-write WDT_INT_ENA_W1TC enable RTC WDT interrupt 3 1 read-write BROWN_OUT_INT_ENA_W1TC enable brown out interrupt 9 1 read-write MAIN_TIMER_INT_ENA_W1TC enable RTC main timer interrupt 10 1 read-write SWD_INT_ENA_W1TC enable super watch dog interrupt 15 1 read-write BBPLL_CAL_INT_ENA_W1TC Need add desc 20 1 read-write CNTL_RETENTION_CTRL register description 0xF4 0x20 0xA0D00000 RETENTION_CLK_SEL Need add desc 18 1 read-write RETENTION_DONE_WAIT Need add desc 19 3 read-write RETENTION_CLKOFF_WAIT Need add desc 22 4 read-write RETENTION_EN Need add desc 26 1 read-write RETENTION_WAIT wait cycles for rention operation 27 5 read-write FIB_SEL register description 0xF8 0x20 0x00000007 FIB_SEL select use analog fib signal 0 3 read-write CNTL_GPIO_WAKEUP register description 0xFC 0x20 GPIO_WAKEUP_STATUS Need add desc 0 6 read-write GPIO_WAKEUP_STATUS_CLR Need add desc 6 1 read-write GPIO_PIN_CLK_GATE Need add desc 7 1 read-write GPIO_PIN5_INT_TYPE Need add desc 8 3 read-write GPIO_PIN4_INT_TYPE Need add desc 11 3 read-write GPIO_PIN3_INT_TYPE Need add desc 14 3 read-write GPIO_PIN2_INT_TYPE Need add desc 17 3 read-write GPIO_PIN1_INT_TYPE Need add desc 20 3 read-write GPIO_PIN0_INT_TYPE Need add desc 23 3 read-write GPIO_PIN5_WAKEUP_ENABLE Need add desc 26 1 read-write GPIO_PIN4_WAKEUP_ENABLE Need add desc 27 1 read-write GPIO_PIN3_WAKEUP_ENABLE Need add desc 28 1 read-write GPIO_PIN2_WAKEUP_ENABLE Need add desc 29 1 read-write GPIO_PIN1_WAKEUP_ENABLE Need add desc 30 1 read-write GPIO_PIN0_WAKEUP_ENABLE Need add desc 31 1 read-write CNTL_DBG_SEL register description 0x100 0x20 DEBUG_12M_NO_GATING Need add desc 1 1 read-write DEBUG_BIT_SEL Need add desc 2 5 read-write DEBUG_SEL0 Need add desc 7 5 read-write DEBUG_SEL1 Need add desc 12 5 read-write DEBUG_SEL2 Need add desc 17 5 read-write DEBUG_SEL3 Need add desc 22 5 read-write DEBUG_SEL4 Need add desc 27 5 read-write CNTL_DBG_MAP register description 0x104 0x20 GPIO_PIN5_MUX_SEL Need add desc 2 1 read-write GPIO_PIN4_MUX_SEL Need add desc 3 1 read-write GPIO_PIN3_MUX_SEL Need add desc 4 1 read-write GPIO_PIN2_MUX_SEL Need add desc 5 1 read-write GPIO_PIN1_MUX_SEL Need add desc 6 1 read-write GPIO_PIN0_MUX_SEL Need add desc 7 1 read-write GPIO_PIN5_FUN_SEL Need add desc 8 4 read-write GPIO_PIN4_FUN_SEL Need add desc 12 4 read-write GPIO_PIN3_FUN_SEL Need add desc 16 4 read-write GPIO_PIN2_FUN_SEL Need add desc 20 4 read-write GPIO_PIN1_FUN_SEL Need add desc 24 4 read-write GPIO_PIN0_FUN_SEL Need add desc 28 4 read-write CNTL_SENSOR_CTRL register description 0x108 0x20 SAR2_PWDET_CCT Need add desc 27 3 read-write FORCE_XPD_SAR Need add desc 30 2 read-write CNTL_DBG_SAR_SEL register description 0x10C 0x20 SAR_DEBUG_SEL Need add desc 27 5 read-write CNTL_DATE register description 0x1FC 0x20 0x02107190 CNTL_DATE Need add desc 0 28 read-write SENSITIVE SENSITIVE Peripheral SENSITIVE 0x600C1000 0x0 0x48 registers ROM_TABLE_LOCK register description 0x0 0x20 ROM_TABLE_LOCK Need add description 0 1 read-write ROM_TABLE register description 0x4 0x20 ROM_TABLE Need add description 0 32 read-write APB_PERIPHERAL_ACCESS_0 register description 0x8 0x20 APB_PERIPHERAL_ACCESS_LOCK Need add description 0 1 read-write APB_PERIPHERAL_ACCESS_1 register description 0xC 0x20 0x00000001 APB_PERIPHERAL_ACCESS_SPLIT_BURST Need add description 0 1 read-write INTERNAL_SRAM_USAGE_0 register description 0x10 0x20 INTERNAL_SRAM_USAGE_LOCK Need add description 0 1 read-write INTERNAL_SRAM_USAGE_1 register description 0x14 0x20 0x0000000F INTERNAL_SRAM_USAGE_CPU_CACHE Need add description 0 1 read-write INTERNAL_SRAM_USAGE_CPU_SRAM Need add description 1 3 read-write INTERNAL_SRAM_USAGE_3 register description 0x18 0x20 INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM Need add description 0 3 read-write INTERNAL_SRAM_ALLOC_MAC_DUMP Need add description 3 1 read-write CACHE_TAG_ACCESS_0 register description 0x1C 0x20 CACHE_TAG_ACCESS_LOCK Need add description 0 1 read-write CACHE_TAG_ACCESS_1 register description 0x20 0x20 0x0000000F PRO_I_TAG_RD_ACS Need add description 0 1 read-write PRO_I_TAG_WR_ACS Need add description 1 1 read-write PRO_D_TAG_RD_ACS Need add description 2 1 read-write PRO_D_TAG_WR_ACS Need add description 3 1 read-write CACHE_MMU_ACCESS_0 register description 0x24 0x20 CACHE_MMU_ACCESS_LOCK Need add description 0 1 read-write CACHE_MMU_ACCESS_1 register description 0x28 0x20 0x00000003 PRO_MMU_RD_ACS Need add description 0 1 read-write PRO_MMU_WR_ACS Need add description 1 1 read-write PIF_ACCESS_MONITOR_0 register description 0x2C 0x20 PIF_ACCESS_MONITOR_LOCK Need add description 0 1 read-write PIF_ACCESS_MONITOR_1 register description 0x30 0x20 0x00000003 PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR Need add description 0 1 read-write PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN Need add description 1 1 read-write PIF_ACCESS_MONITOR_2 register description 0x34 0x20 PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR Need add description 0 1 read-only PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE Need add description 1 2 read-only PIF_ACCESS_MONITOR_3 register description 0x38 0x20 PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR Need add description 0 32 read-only XTS_AES_KEY_UPDATE register description 0x3C 0x20 XTS_AES_KEY_UPDATE Set this bit to update xts_aes key 0 1 read-write CLOCK_GATE register description 0x40 0x20 0x00000001 CLK_EN Need add description 0 1 read-write SENSITIVE_REG_DATE register description 0xFFC 0x20 0x02106301 SENSITIVE_REG_DATE Need add description 0 28 read-write SHA SHA (Secure Hash Algorithm) Accelerator SHA 0x6003B000 0x0 0xB0 registers SHA 34 MODE Initial configuration register. 0x0 0x20 MODE Sha mode. 0 3 read-write T_STRING SHA 512/t configuration register 0. 0x4 0x20 T_STRING Sha t_string (used if and only if mode == SHA_512/t). 0 32 read-write T_LENGTH SHA 512/t configuration register 1. 0x8 0x20 T_LENGTH Sha t_length (used if and only if mode == SHA_512/t). 0 6 read-write DMA_BLOCK_NUM DMA configuration register 0. 0xC 0x20 DMA_BLOCK_NUM Dma-sha block number. 0 6 read-write START Typical SHA configuration register 0. 0x10 0x20 START Reserved. 1 31 write-only CONTINUE Typical SHA configuration register 1. 0x14 0x20 CONTINUE Reserved. 1 31 write-only BUSY Busy register. 0x18 0x20 STATE Sha busy state. 1'b0: idle. 1'b1: busy. 0 1 read-only DMA_START DMA configuration register 1. 0x1C 0x20 DMA_START Start dma-sha. 0 1 write-only DMA_CONTINUE DMA configuration register 2. 0x20 0x20 DMA_CONTINUE Continue dma-sha. 0 1 write-only CLEAR_IRQ Interrupt clear register. 0x24 0x20 CLEAR_INTERRUPT Clear sha interrupt. 0 1 write-only IRQ_ENA Interrupt enable register. 0x28 0x20 INTERRUPT_ENA Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. 0 1 read-write DATE Date register. 0x2C 0x20 0x20200616 DATE Sha date information/ sha version information. 0 30 read-write 64 0x1 H_MEM[%s] Sha H memory which contains intermediate hash or finial hash. 0x40 0x8 64 0x1 M_MEM[%s] Sha M memory which contains message. 0x80 0x8 SPI0 SPI (Serial Peripheral Interface) Controller 0 SPI0 0x60003000 0x0 0x48 registers SPI_MEM_REJECT_CACHE 29 CTRL SPI0 control register. 0x8 0x20 0x002C2000 FDUMMY_OUT In the dummy phase the signal level of spi is output by the spi controller. 3 1 read-write FCMD_DUAL Apply 2 signals during command phase 1:enable 0: disable 7 1 read-write FCMD_QUAD Apply 4 signals during command phase 1:enable 0: disable 8 1 read-write FASTRD_MODE This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT AND SPI_MEM_FREAD_DOUT. 1: enable 0: disable. 13 1 read-write FREAD_DUAL In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. 14 1 read-write Q_POL The bit is used to set MISO line polarity, 1: high 0, low 18 1 read-write D_POL The bit is used to set MOSI line polarity, 1: high 0, low 19 1 read-write FREAD_QUAD In the read operations read-data phase apply 4 signals. 1: enable 0: disable. 20 1 read-write WP Write protect signal output when SPI is idle. 1: output high, 0: output low. 21 1 read-write FREAD_DIO In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. 23 1 read-write FREAD_QIO In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. 24 1 read-write CTRL1 SPI0 control1 register. 0xC 0x20 CLK_MODE SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. 0 2 read-write RXFIFO_RST SPI0 RX FIFO reset signal. 30 1 write-only CTRL2 SPI0 control2 register. 0x10 0x20 0x00000021 CS_SETUP_TIME (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit. 0 5 read-write CS_HOLD_TIME Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit. 5 5 read-write CS_HOLD_DELAY These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. 25 6 read-write SYNC_RESET The FSM will be reset. 31 1 write-only CLOCK SPI clock division control register. 0x14 0x20 0x00030103 CLKCNT_L In the master mode it must be equal to spi_mem_clkcnt_N. 0 8 read-write CLKCNT_H In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). 8 8 read-write CLKCNT_N In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) 16 8 read-write CLK_EQU_SYSCLK Set this bit in 1-division mode. 31 1 read-write USER SPI0 user register. 0x18 0x20 CS_HOLD spi cs keep low when spi is in done phase. 1: enable 0: disable. 6 1 read-write CS_SETUP spi cs is enable when spi is in prepare phase. 1: enable 0: disable. 7 1 read-write CK_OUT_EDGE the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. 9 1 read-write USR_DUMMY_IDLE spi clock is disable in dummy phase when the bit is enable. 26 1 read-write USR_DUMMY This bit enable the dummy phase of an operation. 29 1 read-write USER1 SPI0 user1 register. 0x1C 0x20 0x5C000007 USR_DUMMY_CYCLELEN The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). 0 6 read-write USR_ADDR_BITLEN The length in bits of address phase. The register value shall be (bit_num-1). 26 6 read-write USER2 SPI0 user2 register. 0x20 0x20 0x70000000 USR_COMMAND_VALUE The value of command. 0 16 read-write USR_COMMAND_BITLEN The length in bits of command phase. The register value shall be (bit_num-1) 28 4 read-write RD_STATUS SPI0 read control register. 0x2C 0x20 WB_MODE Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. 16 8 read-write MISC SPI0 misc register 0x34 0x20 TRANS_END The bit is used to indicate the spi0_mst_st controlled transmitting is done. 3 1 read-write TRANS_END_INT_ENA The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done. 4 1 read-write CSPI_ST_TRANS_END The bit is used to indicate the spi0_slv_st controlled transmitting is done. 5 1 read-write CSPI_ST_TRANS_END_INT_ENA The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done. 6 1 read-write CK_IDLE_EDGE 1: spi clk line is high when idle 0: spi clk line is low when idle 9 1 read-write CS_KEEP_ACTIVE spi cs line keep low when the bit is set. 10 1 read-write CACHE_FCTRL SPI0 bit mode control register. 0x3C 0x20 CACHE_REQ_EN For SPI0, Cache access enable, 1: enable, 0:disable. 0 1 read-write CACHE_USR_ADDR_4BYTE For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. 1 1 read-write CACHE_FLASH_USR_CMD For SPI0, cache read flash for user define command, 1: enable, 0:disable. 2 1 read-write FDIN_DUAL For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 3 1 read-write FDOUT_DUAL For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 4 1 read-write FADDR_DUAL For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 5 1 read-write FDIN_QUAD For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 6 1 read-write FDOUT_QUAD For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 7 1 read-write FADDR_QUAD For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 8 1 read-write FSM SPI0 FSM status register 0x54 0x20 0x00000200 CSPI_ST The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. 0 4 read-only EM_ST The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state. 4 3 read-only CSPI_LOCK_DELAY_TIME The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. 7 5 read-write TIMING_CALI SPI0 timing calibration register 0xA8 0x20 TIMING_CLK_ENA The bit is used to enable timing adjust clock for all reading operations. 0 1 read-only TIMING_CALI The bit is used to enable timing auto-calibration for all reading operations. 1 1 read-only EXTRA_DUMMY_CYCLELEN add extra dummy spi clock cycle length for spi clock calibration. 2 3 read-only DIN_MODE SPI0 input delay mode control register 0xAC 0x20 DIN0_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 0 2 read-only DIN1_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 2 2 read-only DIN2_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 4 2 read-only DIN3_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 6 2 read-only DIN_NUM SPI0 input delay number control register 0xB0 0x20 DIN0_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 0 1 read-only DIN1_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 1 1 read-only DIN2_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 2 1 read-only DIN3_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 3 1 read-only DOUT_MODE SPI0 output delay mode control register 0xB4 0x20 DOUT0_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 0 1 read-only DOUT1_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 1 1 read-only DOUT2_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 2 1 read-only DOUT3_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 3 1 read-only CLOCK_GATE SPI0 clk_gate register 0xDC 0x20 0x00000001 CLK_EN Register clock gate enable signal. 1: Enable. 0: Disable. 0 1 read-write CORE_CLK_SEL SPI0 module clock select register 0xE0 0x20 SPI01_CLK_SEL When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. 0 2 read-write DATE Version control register 0x3FC 0x20 0x02106191 DATE SPI register version. 0 28 read-write SPI1 SPI (Serial Peripheral Interface) Controller 1 SPI1 0x60002000 0x0 0xA8 registers CMD SPI1 memory command register 0x0 0x20 SPI1_MST_ST The current status of SPI1 master FSM. 0 4 read-only MSPI_ST The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. 4 4 read-only FLASH_PE In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. 17 1 read-write USR User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 18 1 read-write FLASH_HPM Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. 19 1 read-write FLASH_RES This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. 20 1 read-write FLASH_DP Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 21 1 read-write FLASH_CE Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 22 1 read-write FLASH_BE Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 23 1 read-write FLASH_SE Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 24 1 read-write FLASH_PP Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. 25 1 read-write FLASH_WRSR Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 26 1 read-write FLASH_RDSR Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 27 1 read-write FLASH_RDID Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 28 1 read-write FLASH_WRDI Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 29 1 read-write FLASH_WREN Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 30 1 read-write FLASH_READ Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 31 1 read-write ADDR SPI1 address register 0x4 0x20 USR_ADDR_VALUE In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer. 0 32 read-write CTRL SPI1 control register. 0x8 0x20 0x002CA000 FDUMMY_OUT In the dummy phase the signal level of spi is output by the spi controller. 3 1 read-write FCMD_DUAL Apply 2 signals during command phase 1:enable 0: disable 7 1 read-write FCMD_QUAD Apply 4 signals during command phase 1:enable 0: disable 8 1 read-write FCS_CRC_EN For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. 10 1 read-write TX_CRC_EN For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable 11 1 read-write FASTRD_MODE This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable. 13 1 read-write FREAD_DUAL In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. 14 1 read-write RESANDRES The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. 15 1 read-write Q_POL The bit is used to set MISO line polarity, 1: high 0, low 18 1 read-write D_POL The bit is used to set MOSI line polarity, 1: high 0, low 19 1 read-write FREAD_QUAD In the read operations read-data phase apply 4 signals. 1: enable 0: disable. 20 1 read-write WP Write protect signal output when SPI is idle. 1: output high, 0: output low. 21 1 read-write WRSR_2B two bytes data will be written to status register when it is set. 1: enable 0: disable. 22 1 read-write FREAD_DIO In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. 23 1 read-write FREAD_QIO In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. 24 1 read-write CTRL1 SPI1 control1 register. 0xC 0x20 0x00000FFC CLK_MODE SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. 0 2 read-write CS_HOLD_DLY_RES After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles. 2 10 read-write CTRL2 SPI1 control2 register. 0x10 0x20 SYNC_RESET The FSM will be reset. 31 1 write-only CLOCK SPI1 clock division control register. 0x14 0x20 0x00030103 CLKCNT_L In the master mode it must be equal to spi_mem_clkcnt_N. 0 8 read-write CLKCNT_H In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). 8 8 read-write CLKCNT_N In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) 16 8 read-write CLK_EQU_SYSCLK reserved 31 1 read-write USER SPI1 user register. 0x18 0x20 0x80000000 CK_OUT_EDGE the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. 9 1 read-write FWRITE_DUAL In the write operations read-data phase apply 2 signals 12 1 read-write FWRITE_QUAD In the write operations read-data phase apply 4 signals 13 1 read-write FWRITE_DIO In the write operations address phase and read-data phase apply 2 signals. 14 1 read-write FWRITE_QIO In the write operations address phase and read-data phase apply 4 signals. 15 1 read-write USR_MISO_HIGHPART read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. 24 1 read-write USR_MOSI_HIGHPART write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. 25 1 read-write USR_DUMMY_IDLE SPI clock is disable in dummy phase when the bit is enable. 26 1 read-write USR_MOSI This bit enable the write-data phase of an operation. 27 1 read-write USR_MISO This bit enable the read-data phase of an operation. 28 1 read-write USR_DUMMY This bit enable the dummy phase of an operation. 29 1 read-write USR_ADDR This bit enable the address phase of an operation. 30 1 read-write USR_COMMAND This bit enable the command phase of an operation. 31 1 read-write USER1 SPI1 user1 register. 0x1C 0x20 0x5C000007 USR_DUMMY_CYCLELEN The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). 0 6 read-write USR_ADDR_BITLEN The length in bits of address phase. The register value shall be (bit_num-1). 26 6 read-write USER2 SPI1 user2 register. 0x20 0x20 0x70000000 USR_COMMAND_VALUE The value of command. 0 16 read-write USR_COMMAND_BITLEN The length in bits of command phase. The register value shall be (bit_num-1) 28 4 read-write MOSI_DLEN SPI1 send data bit length control register. 0x24 0x20 USR_MOSI_DBITLEN The length in bits of write-data. The register value shall be (bit_num-1). 0 10 read-write MISO_DLEN SPI1 receive data bit length control register. 0x28 0x20 USR_MISO_DBITLEN The length in bits of read-data. The register value shall be (bit_num-1). 0 10 read-write RD_STATUS SPI1 status register. 0x2C 0x20 STATUS The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. 0 16 read-write WB_MODE Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. 16 8 read-write MISC SPI1 misc register 0x34 0x20 0x00000002 CS0_DIS SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on. 0 1 read-write CS1_DIS SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on. 1 1 read-write CK_IDLE_EDGE 1: spi clk line is high when idle 0: spi clk line is low when idle 9 1 read-write CS_KEEP_ACTIVE spi cs line keep low when the bit is set. 10 1 read-write TX_CRC SPI1 TX CRC data register. 0x38 0x20 0xFFFFFFFF DATA For SPI1, the value of crc32. 0 32 read-only CACHE_FCTRL SPI1 bit mode control register. 0x3C 0x20 CACHE_USR_ADDR_4BYTE For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. 1 1 read-write FDIN_DUAL For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 3 1 read-write FDOUT_DUAL For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 4 1 read-write FADDR_DUAL For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 5 1 read-write FDIN_QUAD For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 6 1 read-write FDOUT_QUAD For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 7 1 read-write FADDR_QUAD For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 8 1 read-write W0 SPI1 memory data buffer0 0x58 0x20 BUF0 data buffer 0 32 read-write W1 SPI1 memory data buffer1 0x5C 0x20 BUF1 data buffer 0 32 read-write W2 SPI1 memory data buffer2 0x60 0x20 BUF2 data buffer 0 32 read-write W3 SPI1 memory data buffer3 0x64 0x20 BUF3 data buffer 0 32 read-write W4 SPI1 memory data buffer4 0x68 0x20 BUF4 data buffer 0 32 read-write W5 SPI1 memory data buffer5 0x6C 0x20 BUF5 data buffer 0 32 read-write W6 SPI1 memory data buffer6 0x70 0x20 BUF6 data buffer 0 32 read-write W7 SPI1 memory data buffer7 0x74 0x20 BUF7 data buffer 0 32 read-write W8 SPI1 memory data buffer8 0x78 0x20 BUF8 data buffer 0 32 read-write W9 SPI1 memory data buffer9 0x7C 0x20 BUF9 data buffer 0 32 read-write W10 SPI1 memory data buffer10 0x80 0x20 BUF10 data buffer 0 32 read-write W11 SPI1 memory data buffer11 0x84 0x20 BUF11 data buffer 0 32 read-write W12 SPI1 memory data buffer12 0x88 0x20 BUF12 data buffer 0 32 read-write W13 SPI1 memory data buffer13 0x8C 0x20 BUF13 data buffer 0 32 read-write W14 SPI1 memory data buffer14 0x90 0x20 BUF14 data buffer 0 32 read-write W15 SPI1 memory data buffer15 0x94 0x20 BUF15 data buffer 0 32 read-write FLASH_WAITI_CTRL SPI1 wait idle control register 0x98 0x20 0x00000014 WAITI_DUMMY The dummy phase enable when wait flash idle (RDSR) 1 1 read-write WAITI_CMD The command to wait flash idle(RDSR). 2 8 read-write WAITI_DUMMY_CYCLELEN The dummy cycle length when wait flash idle(RDSR). 10 6 read-write FLASH_SUS_CTRL SPI1 flash suspend control register 0x9C 0x20 0x08002000 FLASH_PER program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 0 1 read-write FLASH_PES program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 1 1 read-write FLASH_PER_WAIT_EN 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. 2 1 read-write FLASH_PES_WAIT_EN 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. 3 1 read-write PES_PER_EN Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done. 4 1 read-write FLASH_PES_EN Set this bit to enable Auto-suspending function. 5 1 read-write PESR_END_MSK The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]. 6 16 read-write SPI_FMEM_RD_SUS_2B 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit 22 1 read-write PER_END_EN 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0. 23 1 read-write PES_END_EN 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0. 24 1 read-write SUS_TIMEOUT_CNT When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass. 25 7 read-write FLASH_SUS_CMD SPI1 flash suspend command register 0xA0 0x20 0x0005757A FLASH_PER_COMMAND Program/Erase resume command. 0 8 read-write FLASH_PES_COMMAND Program/Erase suspend command. 8 8 read-write WAIT_PESR_COMMAND Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. 16 16 read-write SUS_STATUS SPI1 flash suspend status register 0xA4 0x20 FLASH_SUS The status of flash suspend, only used in SPI1. 0 1 read-write WAIT_PESR_CMD_2B 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. 1 1 read-write FLASH_HPM_DLY_128 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent. 2 1 read-write FLASH_RES_DLY_128 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent. 3 1 read-write FLASH_DP_DLY_128 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent. 4 1 read-write FLASH_PER_DLY_128 Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent. 5 1 read-write FLASH_PES_DLY_128 Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent. 6 1 read-write SPI0_LOCK_EN 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. 7 1 read-write TIMING_CALI SPI1 timing control register 0xA8 0x20 TIMING_CALI The bit is used to enable timing auto-calibration for all reading operations. 1 1 read-only EXTRA_DUMMY_CYCLELEN add extra dummy spi clock cycle length for spi clock calibration. 2 3 read-only INT_ENA SPI1 interrupt enable register 0xC0 0x20 PER_END_INT_ENA The enable bit for SPI_MEM_PER_END_INT interrupt. 0 1 read-write PES_END_INT_ENA The enable bit for SPI_MEM_PES_END_INT interrupt. 1 1 read-write WPE_END_INT_ENA The enable bit for SPI_MEM_WPE_END_INT interrupt. 2 1 read-write SLV_ST_END_INT_ENA The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. 3 1 read-write MST_ST_END_INT_ENA The enable bit for SPI_MEM_MST_ST_END_INT interrupt. 4 1 read-write BROWN_OUT_INT_ENA The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. 5 1 read-write INT_CLR SPI1 interrupt clear register 0xC4 0x20 PER_END_INT_CLR The clear bit for SPI_MEM_PER_END_INT interrupt. 0 1 write-only PES_END_INT_CLR The clear bit for SPI_MEM_PES_END_INT interrupt. 1 1 write-only WPE_END_INT_CLR The clear bit for SPI_MEM_WPE_END_INT interrupt. 2 1 write-only SLV_ST_END_INT_CLR The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. 3 1 write-only MST_ST_END_INT_CLR The clear bit for SPI_MEM_MST_ST_END_INT interrupt. 4 1 write-only BROWN_OUT_INT_CLR The status bit for SPI_MEM_BROWN_OUT_INT interrupt. 5 1 write-only INT_RAW SPI1 interrupt raw register 0xC8 0x20 PER_END_INT_RAW The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others. 0 1 read-write PES_END_INT_RAW The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others. 1 1 read-write WPE_END_INT_RAW The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. 2 1 read-write SLV_ST_END_INT_RAW The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others 3 1 read-write MST_ST_END_INT_RAW The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others. 4 1 read-write BROWN_OUT_INT_RAW The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others. 5 1 read-write INT_ST SPI1 interrupt status register 0xCC 0x20 PER_END_INT_ST The status bit for SPI_MEM_PER_END_INT interrupt. 0 1 read-only PES_END_INT_ST The status bit for SPI_MEM_PES_END_INT interrupt. 1 1 read-only WPE_END_INT_ST The status bit for SPI_MEM_WPE_END_INT interrupt. 2 1 read-only SLV_ST_END_INT_ST The status bit for SPI_MEM_SLV_ST_END_INT interrupt. 3 1 read-only MST_ST_END_INT_ST The status bit for SPI_MEM_MST_ST_END_INT interrupt. 4 1 read-only BROWN_OUT_INT_ST The status bit for SPI_MEM_BROWN_OUT_INT interrupt. 5 1 read-only CLOCK_GATE SPI1 clk_gate register 0xDC 0x20 0x00000001 CLK_EN Register clock gate enable signal. 1: Enable. 0: Disable. 0 1 read-write DATE Version control register 0x3FC 0x20 0x02107013 DATE Version control register 0 28 read-write SPI2 SPI (Serial Peripheral Interface) Controller 2 SPI2 0x60024000 0x0 0x98 registers SPI_INTR_1 15 SPI_INTR_2 16 CMD Command control register 0x0 0x20 CONF_BITLEN Define the APB cycles of SPI_CONF state. Can be configured in CONF state. 0 18 read-write UPDATE Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. 23 1 read-write USR User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. 24 1 read-write ADDR Address value register 0x4 0x20 USR_ADDR_VALUE Address to slave. Can be configured in CONF state. 0 32 read-write CTRL SPI control register 0x8 0x20 0x003C0000 DUMMY_OUT 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. 3 1 read-write FADDR_DUAL Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. 5 1 read-write FADDR_QUAD Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. 6 1 read-write FADDR_OCT Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. 7 1 read-only FCMD_DUAL Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. 8 1 read-write FCMD_QUAD Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. 9 1 read-write FCMD_OCT Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state. 10 1 read-only FREAD_DUAL In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. 14 1 read-write FREAD_QUAD In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. 15 1 read-write FREAD_OCT In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state. 16 1 read-only Q_POL The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. 18 1 read-write D_POL The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. 19 1 read-write HOLD_POL SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. 20 1 read-write WP_POL Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. 21 1 read-write RD_BIT_ORDER In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. 23 2 read-write WR_BIT_ORDER In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. 25 2 read-write CLOCK SPI clock control register 0xC 0x20 0x80003043 CLKCNT_L In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. 0 6 read-write CLKCNT_H In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. 6 6 read-write CLKCNT_N In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. 12 6 read-write CLKDIV_PRE In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. 18 4 read-write CLK_EQU_SYSCLK In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. 31 1 read-write USER SPI USER control register 0x10 0x20 0x800000C0 DOUTDIN Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. 0 1 read-write QPI_MODE Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. 3 1 read-write OPI_MODE Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state. 4 1 read-only TSCK_I_EDGE In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. 5 1 read-write CS_HOLD spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. 6 1 read-write CS_SETUP spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. 7 1 read-write RSCK_I_EDGE In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. 8 1 read-write CK_OUT_EDGE the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. 9 1 read-write FWRITE_DUAL In the write operations read-data phase apply 2 signals. Can be configured in CONF state. 12 1 read-write FWRITE_QUAD In the write operations read-data phase apply 4 signals. Can be configured in CONF state. 13 1 read-write FWRITE_OCT In the write operations read-data phase apply 8 signals. Can be configured in CONF state. 14 1 read-only USR_CONF_NXT 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. 15 1 read-write SIO Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. 17 1 read-write USR_MISO_HIGHPART read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. 24 1 read-write USR_MOSI_HIGHPART write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. 25 1 read-write USR_DUMMY_IDLE spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. 26 1 read-write USR_MOSI This bit enable the write-data phase of an operation. Can be configured in CONF state. 27 1 read-write USR_MISO This bit enable the read-data phase of an operation. Can be configured in CONF state. 28 1 read-write USR_DUMMY This bit enable the dummy phase of an operation. Can be configured in CONF state. 29 1 read-write USR_ADDR This bit enable the address phase of an operation. Can be configured in CONF state. 30 1 read-write USR_COMMAND This bit enable the command phase of an operation. Can be configured in CONF state. 31 1 read-write USER1 SPI USER control register 1 0x14 0x20 0xB8410007 USR_DUMMY_CYCLELEN The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. 0 8 read-write MST_WFULL_ERR_END_EN 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 16 1 read-write CS_SETUP_TIME (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. 17 5 read-write CS_HOLD_TIME delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. 22 5 read-write USR_ADDR_BITLEN The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. 27 5 read-write USER2 SPI USER control register 2 0x18 0x20 0x78000000 USR_COMMAND_VALUE The value of command. Can be configured in CONF state. 0 16 read-write MST_REMPTY_ERR_END_EN 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 27 1 read-write USR_COMMAND_BITLEN The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. 28 4 read-write MS_DLEN SPI data bit length control register 0x1C 0x20 MS_DATA_BITLEN The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. 0 18 read-write MISC SPI misc register 0x20 0x20 0x0000003E CS0_DIS SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. 0 1 read-write CS1_DIS SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. 1 1 read-write CS2_DIS SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. 2 1 read-write CS3_DIS SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. 3 1 read-write CS4_DIS SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. 4 1 read-write CS5_DIS SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. 5 1 read-write CK_DIS 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. 6 1 read-write MASTER_CS_POL In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. 7 6 read-write CLK_DATA_DTR_EN 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. 16 1 read-only DATA_DTR_EN 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. 17 1 read-only ADDR_DTR_EN 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. 18 1 read-only CMD_DTR_EN 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. 19 1 read-only SLAVE_CS_POL spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. 23 1 read-write DQS_IDLE_EDGE The default value of spi_dqs. Can be configured in CONF state. 24 1 read-only CK_IDLE_EDGE 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. 29 1 read-write CS_KEEP_ACTIVE spi cs line keep low when the bit is set. Can be configured in CONF state. 30 1 read-write QUAD_DIN_PIN_SWAP 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state. 31 1 read-write DIN_MODE SPI input delay mode configuration 0x24 0x20 DIN0_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 0 2 read-only DIN1_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 2 2 read-only DIN2_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 4 2 read-only DIN3_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 6 2 read-only DIN4_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 8 2 read-only DIN5_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 10 2 read-only DIN6_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 12 2 read-only DIN7_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 14 2 read-only TIMING_HCLK_ACTIVE 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. 16 1 read-only DIN_NUM SPI input delay number configuration 0x28 0x20 DIN0_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 0 2 read-only DIN1_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 2 2 read-only DIN2_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 4 2 read-only DIN3_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 6 2 read-only DIN4_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 8 2 read-only DIN5_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 10 2 read-only DIN6_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 12 2 read-only DIN7_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 14 2 read-only DOUT_MODE SPI output delay mode configuration 0x2C 0x20 DOUT0_MODE The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 0 1 read-only DOUT1_MODE The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 1 1 read-only DOUT2_MODE The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 2 1 read-only DOUT3_MODE The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 3 1 read-only DOUT4_MODE The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 4 1 read-only DOUT5_MODE The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 5 1 read-only DOUT6_MODE The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 6 1 read-only DOUT7_MODE The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 7 1 read-only D_DQS_MODE The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 8 1 read-only DMA_CONF SPI DMA control register 0x30 0x20 0x00000003 DMA_OUTFIFO_EMPTY Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. 0 1 read-only DMA_INFIFO_FULL Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. 1 1 read-only DMA_SLV_SEG_TRANS_EN Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. 18 1 read-write SLV_RX_SEG_TRANS_CLR_EN 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. 19 1 read-write SLV_TX_SEG_TRANS_CLR_EN 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. 20 1 read-write RX_EOF_EN 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. 21 1 read-write DMA_RX_ENA Set this bit to enable SPI DMA controlled receive data mode. 27 1 read-write DMA_TX_ENA Set this bit to enable SPI DMA controlled send data mode. 28 1 read-write RX_AFIFO_RST Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. 29 1 write-only BUF_AFIFO_RST Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. 30 1 write-only DMA_AFIFO_RST Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. 31 1 write-only DMA_INT_ENA SPI interrupt enable register 0x34 0x20 DMA_INFIFO_FULL_ERR_INT_ENA The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. 0 1 read-write DMA_OUTFIFO_EMPTY_ERR_INT_ENA The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. 1 1 read-write SLV_EX_QPI_INT_ENA The enable bit for SPI slave Ex_QPI interrupt. 2 1 read-write SLV_EN_QPI_INT_ENA The enable bit for SPI slave En_QPI interrupt. 3 1 read-write SLV_CMD7_INT_ENA The enable bit for SPI slave CMD7 interrupt. 4 1 read-write SLV_CMD8_INT_ENA The enable bit for SPI slave CMD8 interrupt. 5 1 read-write SLV_CMD9_INT_ENA The enable bit for SPI slave CMD9 interrupt. 6 1 read-write SLV_CMDA_INT_ENA The enable bit for SPI slave CMDA interrupt. 7 1 read-write SLV_RD_DMA_DONE_INT_ENA The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 8 1 read-write SLV_WR_DMA_DONE_INT_ENA The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 9 1 read-write SLV_RD_BUF_DONE_INT_ENA The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 10 1 read-write SLV_WR_BUF_DONE_INT_ENA The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 11 1 read-write TRANS_DONE_INT_ENA The enable bit for SPI_TRANS_DONE_INT interrupt. 12 1 read-write DMA_SEG_TRANS_DONE_INT_ENA The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 13 1 read-write SEG_MAGIC_ERR_INT_ENA The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. 14 1 read-write SLV_BUF_ADDR_ERR_INT_ENA The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 15 1 read-write SLV_CMD_ERR_INT_ENA The enable bit for SPI_SLV_CMD_ERR_INT interrupt. 16 1 read-write MST_RX_AFIFO_WFULL_ERR_INT_ENA The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 17 1 read-write MST_TX_AFIFO_REMPTY_ERR_INT_ENA The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 18 1 read-write APP2_INT_ENA The enable bit for SPI_APP2_INT interrupt. 19 1 read-write APP1_INT_ENA The enable bit for SPI_APP1_INT interrupt. 20 1 read-write DMA_INT_CLR SPI interrupt clear register 0x38 0x20 DMA_INFIFO_FULL_ERR_INT_CLR The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. 0 1 write-only DMA_OUTFIFO_EMPTY_ERR_INT_CLR The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. 1 1 write-only SLV_EX_QPI_INT_CLR The clear bit for SPI slave Ex_QPI interrupt. 2 1 write-only SLV_EN_QPI_INT_CLR The clear bit for SPI slave En_QPI interrupt. 3 1 write-only SLV_CMD7_INT_CLR The clear bit for SPI slave CMD7 interrupt. 4 1 write-only SLV_CMD8_INT_CLR The clear bit for SPI slave CMD8 interrupt. 5 1 write-only SLV_CMD9_INT_CLR The clear bit for SPI slave CMD9 interrupt. 6 1 write-only SLV_CMDA_INT_CLR The clear bit for SPI slave CMDA interrupt. 7 1 write-only SLV_RD_DMA_DONE_INT_CLR The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 8 1 write-only SLV_WR_DMA_DONE_INT_CLR The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 9 1 write-only SLV_RD_BUF_DONE_INT_CLR The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 10 1 write-only SLV_WR_BUF_DONE_INT_CLR The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 11 1 write-only TRANS_DONE_INT_CLR The clear bit for SPI_TRANS_DONE_INT interrupt. 12 1 write-only DMA_SEG_TRANS_DONE_INT_CLR The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 13 1 write-only SEG_MAGIC_ERR_INT_CLR The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. 14 1 write-only SLV_BUF_ADDR_ERR_INT_CLR The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 15 1 write-only SLV_CMD_ERR_INT_CLR The clear bit for SPI_SLV_CMD_ERR_INT interrupt. 16 1 write-only MST_RX_AFIFO_WFULL_ERR_INT_CLR The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 17 1 write-only MST_TX_AFIFO_REMPTY_ERR_INT_CLR The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 18 1 write-only APP2_INT_CLR The clear bit for SPI_APP2_INT interrupt. 19 1 write-only APP1_INT_CLR The clear bit for SPI_APP1_INT interrupt. 20 1 write-only DMA_INT_RAW SPI interrupt raw register 0x3C 0x20 DMA_INFIFO_FULL_ERR_INT_RAW 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. 0 1 read-write DMA_OUTFIFO_EMPTY_ERR_INT_RAW 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. 1 1 read-write SLV_EX_QPI_INT_RAW The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. 2 1 read-write SLV_EN_QPI_INT_RAW The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. 3 1 read-write SLV_CMD7_INT_RAW The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. 4 1 read-write SLV_CMD8_INT_RAW The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. 5 1 read-write SLV_CMD9_INT_RAW The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. 6 1 read-write SLV_CMDA_INT_RAW The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. 7 1 read-write SLV_RD_DMA_DONE_INT_RAW The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. 8 1 read-write SLV_WR_DMA_DONE_INT_RAW The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. 9 1 read-write SLV_RD_BUF_DONE_INT_RAW The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. 10 1 read-write SLV_WR_BUF_DONE_INT_RAW The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. 11 1 read-write TRANS_DONE_INT_RAW The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. 12 1 read-write DMA_SEG_TRANS_DONE_INT_RAW The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. 13 1 read-write SEG_MAGIC_ERR_INT_RAW The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others. 14 1 read-write SLV_BUF_ADDR_ERR_INT_RAW The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. 15 1 read-write SLV_CMD_ERR_INT_RAW The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. 16 1 read-write MST_RX_AFIFO_WFULL_ERR_INT_RAW The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. 17 1 read-write MST_TX_AFIFO_REMPTY_ERR_INT_RAW The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. 18 1 read-write APP2_INT_RAW The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. 19 1 read-write APP1_INT_RAW The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. 20 1 read-write DMA_INT_ST SPI interrupt status register 0x40 0x20 DMA_INFIFO_FULL_ERR_INT_ST The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. 0 1 read-only DMA_OUTFIFO_EMPTY_ERR_INT_ST The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. 1 1 read-only SLV_EX_QPI_INT_ST The status bit for SPI slave Ex_QPI interrupt. 2 1 read-only SLV_EN_QPI_INT_ST The status bit for SPI slave En_QPI interrupt. 3 1 read-only SLV_CMD7_INT_ST The status bit for SPI slave CMD7 interrupt. 4 1 read-only SLV_CMD8_INT_ST The status bit for SPI slave CMD8 interrupt. 5 1 read-only SLV_CMD9_INT_ST The status bit for SPI slave CMD9 interrupt. 6 1 read-only SLV_CMDA_INT_ST The status bit for SPI slave CMDA interrupt. 7 1 read-only SLV_RD_DMA_DONE_INT_ST The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 8 1 read-only SLV_WR_DMA_DONE_INT_ST The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 9 1 read-only SLV_RD_BUF_DONE_INT_ST The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 10 1 read-only SLV_WR_BUF_DONE_INT_ST The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 11 1 read-only TRANS_DONE_INT_ST The status bit for SPI_TRANS_DONE_INT interrupt. 12 1 read-only DMA_SEG_TRANS_DONE_INT_ST The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 13 1 read-only SEG_MAGIC_ERR_INT_ST The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. 14 1 read-only SLV_BUF_ADDR_ERR_INT_ST The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 15 1 read-only SLV_CMD_ERR_INT_ST The status bit for SPI_SLV_CMD_ERR_INT interrupt. 16 1 read-only MST_RX_AFIFO_WFULL_ERR_INT_ST The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 17 1 read-only MST_TX_AFIFO_REMPTY_ERR_INT_ST The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 18 1 read-only APP2_INT_ST The status bit for SPI_APP2_INT interrupt. 19 1 read-only APP1_INT_ST The status bit for SPI_APP1_INT interrupt. 20 1 read-only DMA_INT_SET SPI interrupt software set register 0x44 0x20 DMA_INFIFO_FULL_ERR_INT_SET The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. 0 1 write-only DMA_OUTFIFO_EMPTY_ERR_INT_SET The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. 1 1 write-only SLV_EX_QPI_INT_SET The software set bit for SPI slave Ex_QPI interrupt. 2 1 write-only SLV_EN_QPI_INT_SET The software set bit for SPI slave En_QPI interrupt. 3 1 write-only SLV_CMD7_INT_SET The software set bit for SPI slave CMD7 interrupt. 4 1 write-only SLV_CMD8_INT_SET The software set bit for SPI slave CMD8 interrupt. 5 1 write-only SLV_CMD9_INT_SET The software set bit for SPI slave CMD9 interrupt. 6 1 write-only SLV_CMDA_INT_SET The software set bit for SPI slave CMDA interrupt. 7 1 write-only SLV_RD_DMA_DONE_INT_SET The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 8 1 write-only SLV_WR_DMA_DONE_INT_SET The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 9 1 write-only SLV_RD_BUF_DONE_INT_SET The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 10 1 write-only SLV_WR_BUF_DONE_INT_SET The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 11 1 write-only TRANS_DONE_INT_SET The software set bit for SPI_TRANS_DONE_INT interrupt. 12 1 write-only DMA_SEG_TRANS_DONE_INT_SET The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 13 1 write-only SEG_MAGIC_ERR_INT_SET The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. 14 1 write-only SLV_BUF_ADDR_ERR_INT_SET The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 15 1 write-only SLV_CMD_ERR_INT_SET The software set bit for SPI_SLV_CMD_ERR_INT interrupt. 16 1 write-only MST_RX_AFIFO_WFULL_ERR_INT_SET The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 17 1 write-only MST_TX_AFIFO_REMPTY_ERR_INT_SET The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 18 1 write-only APP2_INT_SET The software set bit for SPI_APP2_INT interrupt. 19 1 write-only APP1_INT_SET The software set bit for SPI_APP1_INT interrupt. 20 1 write-only W0 SPI CPU-controlled buffer0 0x98 0x20 BUF0 data buffer 0 32 read-write W1 SPI CPU-controlled buffer1 0x9C 0x20 BUF1 data buffer 0 32 read-write W2 SPI CPU-controlled buffer2 0xA0 0x20 BUF2 data buffer 0 32 read-write W3 SPI CPU-controlled buffer3 0xA4 0x20 BUF3 data buffer 0 32 read-write W4 SPI CPU-controlled buffer4 0xA8 0x20 BUF4 data buffer 0 32 read-write W5 SPI CPU-controlled buffer5 0xAC 0x20 BUF5 data buffer 0 32 read-write W6 SPI CPU-controlled buffer6 0xB0 0x20 BUF6 data buffer 0 32 read-write W7 SPI CPU-controlled buffer7 0xB4 0x20 BUF7 data buffer 0 32 read-write W8 SPI CPU-controlled buffer8 0xB8 0x20 BUF8 data buffer 0 32 read-write W9 SPI CPU-controlled buffer9 0xBC 0x20 BUF9 data buffer 0 32 read-write W10 SPI CPU-controlled buffer10 0xC0 0x20 BUF10 data buffer 0 32 read-write W11 SPI CPU-controlled buffer11 0xC4 0x20 BUF11 data buffer 0 32 read-write W12 SPI CPU-controlled buffer12 0xC8 0x20 BUF12 data buffer 0 32 read-write W13 SPI CPU-controlled buffer13 0xCC 0x20 BUF13 data buffer 0 32 read-write W14 SPI CPU-controlled buffer14 0xD0 0x20 BUF14 data buffer 0 32 read-write W15 SPI CPU-controlled buffer15 0xD4 0x20 BUF15 data buffer 0 32 read-write SLAVE SPI slave control register 0xE0 0x20 0x02800000 CLK_MODE SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. 0 2 read-write CLK_MODE_13 {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. 2 1 read-write RSCK_DATA_OUT It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge 3 1 read-write SLV_RDDMA_BITLEN_EN 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others 8 1 read-write SLV_WRDMA_BITLEN_EN 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others 9 1 read-write SLV_RDBUF_BITLEN_EN 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others 10 1 read-write SLV_WRBUF_BITLEN_EN 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others 11 1 read-write DMA_SEG_MAGIC_VALUE The magic value of BM table in master DMA seg-trans. 22 4 read-write MODE Set SPI work mode. 1: slave mode 0: master mode. 26 1 read-write SOFT_RESET Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. 27 1 write-only USR_CONF 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. 28 1 read-write SLAVE1 SPI slave control register 1 0xE4 0x20 SLV_DATA_BITLEN The transferred data bit length in SPI slave FD and HD mode. 0 18 read-write SLV_LAST_COMMAND In the slave mode it is the value of command. 18 8 read-write SLV_LAST_ADDR In the slave mode it is the value of address. 26 6 read-write CLK_GATE SPI module clock and register clock control 0xE8 0x20 CLK_EN Set this bit to enable clk gate 0 1 read-write MST_CLK_ACTIVE Set this bit to power on the SPI module clock. 1 1 read-write MST_CLK_SEL This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. 2 1 read-write DATE Version control 0xF0 0x20 0x02106070 DATE SPI register version. 0 28 read-write SYSTEM System Configuration Registers SYSTEM 0x600C0000 0x0 0xA0 registers CPU_PERI_CLK_EN cpu_peripheral clock gating register 0x0 0x20 CLK_EN_ASSIST_DEBUG Set 1 to open assist_debug module clock 6 1 read-write CLK_EN_DEDICATED_GPIO Set 1 to open dedicated_gpio module clk 7 1 read-write CPU_PERI_RST_EN cpu_peripheral reset register 0x4 0x20 0x000000C0 RST_EN_ASSIST_DEBUG Set 1 to let assist_debug module reset 6 1 read-write RST_EN_DEDICATED_GPIO Set 1 to let dedicated_gpio module reset 7 1 read-write CPU_PER_CONF cpu clock config register 0x8 0x20 0x0000000C CPUPERIOD_SEL This field used to sel cpu clock frequent. 0 2 read-write PLL_FREQ_SEL This field used to sel pll frequent. 2 1 read-write CPU_WAIT_MODE_FORCE_ON Set 1 to force cpu_waiti_clk enable. 3 1 read-write CPU_WAITI_DELAY_NUM This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close 4 4 read-write MEM_PD_MASK memory power down mask register 0xC 0x20 0x00000001 LSLP_MEM_PD_MASK Set 1 to mask memory power down. 0 1 read-write PERIP_CLK_EN0 peripheral clock gating register 0x10 0x20 0x71002066 SPI01_CLK_EN Set 1 to enable SPI01 clock 1 1 read-write UART_CLK_EN Set 1 to enable UART clock 2 1 read-write UART1_CLK_EN Set 1 to enable UART1 clock 5 1 read-write SPI2_CLK_EN Set 1 to enable SPI2 clock 6 1 read-write I2C_EXT0_CLK_EN Set 1 to enable I2C_EXT0 clock 7 1 read-write LEDC_CLK_EN Set 1 to enable LEDC clock 11 1 read-write TIMERGROUP_CLK_EN Set 1 to enable TIMERGROUP clock 13 1 read-write UART_MEM_CLK_EN Set 1 to enable UART_MEM clock 24 1 read-write APB_SARADC_CLK_EN Set 1 to enable APB_SARADC clock 28 1 read-write SYSTIMER_CLK_EN Set 1 to enable SYSTEMTIMER clock 29 1 read-write ADC2_ARB_CLK_EN Set 1 to enable ADC2_ARB clock 30 1 read-write PERIP_CLK_EN1 peripheral clock gating register 0x14 0x20 CRYPTO_ECC_CLK_EN Set 1 to enable ECC clock 1 1 read-write CRYPTO_SHA_CLK_EN Set 1 to enable SHA clock 2 1 read-write DMA_CLK_EN Set 1 to enable DMA clock 6 1 read-write TSENS_CLK_EN Set 1 to enable TSENS clock 10 1 read-write PERIP_RST_EN0 reserved 0x18 0x20 SPI01_RST Set 1 to let SPI01 reset 1 1 read-write UART_RST Set 1 to let UART reset 2 1 read-write UART1_RST Set 1 to let UART1 reset 5 1 read-write SPI2_RST Set 1 to let SPI2 reset 6 1 read-write I2C_EXT0_RST Set 1 to let I2C_EXT0 reset 7 1 read-write LEDC_RST Set 1 to let LEDC reset 11 1 read-write TIMERGROUP_RST Set 1 to let TIMERGROUP reset 13 1 read-write UART_MEM_RST Set 1 to let UART_MEM reset 24 1 read-write APB_SARADC_RST Set 1 to let APB_SARADC reset 28 1 read-write SYSTIMER_RST Set 1 to let SYSTIMER reset 29 1 read-write ADC2_ARB_RST Set 1 to let ADC2_ARB reset 30 1 read-write PERIP_RST_EN1 peripheral reset register 0x1C 0x20 0x00000046 CRYPTO_ECC_RST Set 1 to let CRYPTO_ECC reset 1 1 read-write CRYPTO_SHA_RST Set 1 to let CRYPTO_SHA reset 2 1 read-write DMA_RST Set 1 to let DMA reset 6 1 read-write TSENS_RST Set 1 to let TSENS reset 10 1 read-write BT_LPCK_DIV_INT clock config register 0x20 0x20 0x000000FF BT_LPCK_DIV_NUM This field is lower power clock frequent division factor 0 12 read-write BT_LPCK_DIV_FRAC low power clock configuration register 0x24 0x20 0x02001001 BT_LPCK_DIV_B This field is lower power clock frequent division factor b 0 12 read-write BT_LPCK_DIV_A This field is lower power clock frequent division factor a 12 12 read-write LPCLK_SEL_RTC_SLOW Set 1 to select rtc-slow clock as rtc low power clock 24 1 read-write LPCLK_SEL_8M Set 1 to select 8m clock as rtc low power clock 25 1 read-write LPCLK_SEL_XTAL Set 1 to select xtal clock as rtc low power clock 26 1 read-write LPCLK_SEL_XTAL32K Set 1 to select xtal32k clock as low power clock 27 1 read-write LPCLK_RTC_EN Set 1 to enable RTC low power clock 28 1 read-write CPU_INTR_FROM_CPU_0 interrupt generate register 0x28 0x20 CPU_INTR_FROM_CPU_0 Set 1 to generate cpu interrupt 0 0 1 read-write CPU_INTR_FROM_CPU_1 interrupt generate register 0x2C 0x20 CPU_INTR_FROM_CPU_1 Set 1 to generate cpu interrupt 1 0 1 read-write CPU_INTR_FROM_CPU_2 interrupt generate register 0x30 0x20 CPU_INTR_FROM_CPU_2 Set 1 to generate cpu interrupt 2 0 1 read-write CPU_INTR_FROM_CPU_3 interrupt generate register 0x34 0x20 CPU_INTR_FROM_CPU_3 Set 1 to generate cpu interrupt 3 0 1 read-write RSA_PD_CTRL rsa memory power control register 0x38 0x20 0x00000001 RSA_MEM_PD Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA. This bit is invalid. 0 1 read-write RSA_MEM_FORCE_PU Set 1 to force power up RSA memory. This bit has the second highest priority. 1 1 read-write RSA_MEM_FORCE_PD Set 1 to force power down RSA memory. This bit has the highest priority. 2 1 read-write EDMA_CTRL edma clcok and reset register 0x3C 0x20 0x00000001 EDMA_CLK_ON Set 1 to enable EDMA clock. 0 1 read-write EDMA_RESET Set 1 to let EDMA reset 1 1 read-write CACHE_CONTROL cache control register 0x40 0x20 0x00000005 ICACHE_CLK_ON Set 1 to enable icache clock 0 1 read-write ICACHE_RESET Set 1 to let icache reset 1 1 read-write DCACHE_CLK_ON Set 1 to enable dcache clock 2 1 read-write DCACHE_RESET Set 1 to let dcache reset 3 1 read-write EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG 0x44 0x20 ENABLE_SPI_MANUAL_ENCRYPT Set 1 to enable the SPI manual encrypt. 0 1 read-write ENABLE_DOWNLOAD_DB_ENCRYPT Set 1 to enable download DB encrypt. 1 1 read-write ENABLE_DOWNLOAD_G0CB_DECRYPT Set 1 to enable download G0CB decrypt 2 1 read-write ENABLE_DOWNLOAD_MANUAL_ENCRYPT Set 1 to enable download manual encrypt 3 1 read-write RTC_FASTMEM_CONFIG fast memory config register 0x48 0x20 0x7FF00000 RTC_MEM_CRC_START Set 1 to start the CRC of RTC memory 8 1 read-write RTC_MEM_CRC_ADDR This field is used to set address of RTC memory for CRC. 9 11 read-write RTC_MEM_CRC_LEN This field is used to set length of RTC memory for CRC based on start address. 20 11 read-write RTC_MEM_CRC_FINISH This bit stores the status of RTC memory CRC.1 means finished. 31 1 read-only RTC_FASTMEM_CRC reserved 0x4C 0x20 RTC_MEM_CRC_RES This field stores the CRC result of RTC memory. 0 32 read-only REDUNDANT_ECO_CTRL eco register 0x50 0x20 REDUNDANT_ECO_DRIVE reg_redundant_eco_drive 0 1 read-write REDUNDANT_ECO_RESULT reg_redundant_eco_result 1 1 read-only CLOCK_GATE clock gating register 0x54 0x20 0x00000001 CLK_EN reg_clk_en 0 1 read-write SYSCLK_CONF system clock config register 0x58 0x20 0x00000001 PRE_DIV_CNT This field is used to set the count of prescaler of XTAL_CLK. 0 10 read-write SOC_CLK_SEL This field is used to select soc clock. 10 2 read-write CLK_XTAL_FREQ This field is used to read xtal frequency in MHz. 12 7 read-only CLK_DIV_EN reg_clk_div_en 19 1 read-only MEM_PVT mem pvt register 0x5C 0x20 0x00000003 MEM_PATH_LEN reg_mem_path_len 0 4 read-write MEM_ERR_CNT_CLR reg_mem_err_cnt_clr 4 1 write-only MONITOR_EN reg_mem_pvt_monitor_en 5 1 read-write MEM_TIMING_ERR_CNT reg_mem_timing_err_cnt 6 16 read-only MEM_VT_SEL reg_mem_vt_sel 22 2 read-write COMB_PVT_LVT_CONF mem pvt register 0x60 0x20 0x00000003 COMB_PATH_LEN_LVT reg_comb_path_len_lvt 0 6 read-write COMB_ERR_CNT_CLR_LVT reg_comb_err_cnt_clr_lvt 6 1 write-only COMB_PVT_MONITOR_EN_LVT reg_comb_pvt_monitor_en_lvt 7 1 read-write COMB_PVT_NVT_CONF mem pvt register 0x64 0x20 0x00000003 COMB_PATH_LEN_NVT reg_comb_path_len_nvt 0 6 read-write COMB_ERR_CNT_CLR_NVT reg_comb_err_cnt_clr_nvt 6 1 write-only COMB_PVT_MONITOR_EN_NVT reg_comb_pvt_monitor_en_nvt 7 1 read-write COMB_PVT_HVT_CONF mem pvt register 0x68 0x20 0x00000003 COMB_PATH_LEN_HVT reg_comb_path_len_hvt 0 6 read-write COMB_ERR_CNT_CLR_HVT reg_comb_err_cnt_clr_hvt 6 1 write-only COMB_PVT_MONITOR_EN_HVT reg_comb_pvt_monitor_en_hvt 7 1 read-write COMB_PVT_ERR_LVT_SITE0 mem pvt register 0x6C 0x20 COMB_TIMING_ERR_CNT_LVT_SITE0 reg_comb_timing_err_cnt_lvt_site0 0 16 read-only COMB_PVT_ERR_NVT_SITE0 mem pvt register 0x70 0x20 COMB_TIMING_ERR_CNT_NVT_SITE0 reg_comb_timing_err_cnt_nvt_site0 0 16 read-only COMB_PVT_ERR_HVT_SITE0 mem pvt register 0x74 0x20 COMB_TIMING_ERR_CNT_HVT_SITE0 reg_comb_timing_err_cnt_hvt_site0 0 16 read-only COMB_PVT_ERR_LVT_SITE1 mem pvt register 0x78 0x20 COMB_TIMING_ERR_CNT_LVT_SITE1 reg_comb_timing_err_cnt_lvt_site1 0 16 read-only COMB_PVT_ERR_NVT_SITE1 mem pvt register 0x7C 0x20 COMB_TIMING_ERR_CNT_NVT_SITE1 reg_comb_timing_err_cnt_nvt_site1 0 16 read-only COMB_PVT_ERR_HVT_SITE1 mem pvt register 0x80 0x20 COMB_TIMING_ERR_CNT_HVT_SITE1 reg_comb_timing_err_cnt_hvt_site1 0 16 read-only COMB_PVT_ERR_LVT_SITE2 mem pvt register 0x84 0x20 COMB_TIMING_ERR_CNT_LVT_SITE2 reg_comb_timing_err_cnt_lvt_site2 0 16 read-only COMB_PVT_ERR_NVT_SITE2 mem pvt register 0x88 0x20 COMB_TIMING_ERR_CNT_NVT_SITE2 reg_comb_timing_err_cnt_nvt_site2 0 16 read-only COMB_PVT_ERR_HVT_SITE2 mem pvt register 0x8C 0x20 COMB_TIMING_ERR_CNT_HVT_SITE2 reg_comb_timing_err_cnt_hvt_site2 0 16 read-only COMB_PVT_ERR_LVT_SITE3 mem pvt register 0x90 0x20 COMB_TIMING_ERR_CNT_LVT_SITE3 reg_comb_timing_err_cnt_lvt_site3 0 16 read-only COMB_PVT_ERR_NVT_SITE3 mem pvt register 0x94 0x20 COMB_TIMING_ERR_CNT_NVT_SITE3 reg_comb_timing_err_cnt_nvt_site3 0 16 read-only COMB_PVT_ERR_HVT_SITE3 mem pvt register 0x98 0x20 COMB_TIMING_ERR_CNT_HVT_SITE3 reg_comb_timing_err_cnt_hvt_site3 0 16 read-only REG_DATE Version register 0xFFC 0x20 0x02108190 SYSTEM_REG_DATE reg_system_reg_date 0 28 read-write SYSTIMER System Timer SYSTIMER 0x60023000 0x0 0x78 registers SYSTIMER_TARGET0 26 SYSTIMER_TARGET1 27 SYSTIMER_TARGET2 28 CONF Configure system timer clock 0x0 0x20 0x46000000 SYSTIMER_CLK_FO systimer clock force on 0 1 read-write TARGET2_WORK_EN target2 work enable 22 1 read-write TARGET1_WORK_EN target1 work enable 23 1 read-write TARGET0_WORK_EN target0 work enable 24 1 read-write TIMER_UNIT1_CORE1_STALL_EN If timer unit1 is stalled when core1 stalled 25 1 read-write TIMER_UNIT1_CORE0_STALL_EN If timer unit1 is stalled when core0 stalled 26 1 read-write TIMER_UNIT0_CORE1_STALL_EN If timer unit0 is stalled when core1 stalled 27 1 read-write TIMER_UNIT0_CORE0_STALL_EN If timer unit0 is stalled when core0 stalled 28 1 read-write TIMER_UNIT1_WORK_EN timer unit1 work enable 29 1 read-write TIMER_UNIT0_WORK_EN timer unit0 work enable 30 1 read-write CLK_EN register file clk gating 31 1 read-write UNIT0_OP system timer unit0 value update register 0x4 0x20 TIMER_UNIT0_VALUE_VALID timer value is sync and valid 29 1 read-only TIMER_UNIT0_UPDATE update timer_unit0 30 1 write-only UNIT1_OP system timer unit1 value update register 0x8 0x20 TIMER_UNIT1_VALUE_VALID timer value is sync and valid 29 1 read-only TIMER_UNIT1_UPDATE update timer unit1 30 1 write-only UNIT0_LOAD_HI system timer unit0 value high load register 0xC 0x20 TIMER_UNIT0_LOAD_HI timer unit0 load high 20 bits 0 20 read-write UNIT0_LOAD_LO system timer unit0 value low load register 0x10 0x20 TIMER_UNIT0_LOAD_LO timer unit0 load low 32 bits 0 32 read-write UNIT1_LOAD_HI system timer unit1 value high load register 0x14 0x20 TIMER_UNIT1_LOAD_HI timer unit1 load high 20 bits 0 20 read-write UNIT1_LOAD_LO system timer unit1 value low load register 0x18 0x20 TIMER_UNIT1_LOAD_LO timer unit1 load low 32 bits 0 32 read-write TARGET0_HI system timer comp0 value high register 0x1C 0x20 TIMER_TARGET0_HI timer taget0 high 20 bits 0 20 read-write TARGET0_LO system timer comp0 value low register 0x20 0x20 TIMER_TARGET0_LO timer taget0 low 32 bits 0 32 read-write TARGET1_HI system timer comp1 value high register 0x24 0x20 TIMER_TARGET1_HI timer taget1 high 20 bits 0 20 read-write TARGET1_LO system timer comp1 value low register 0x28 0x20 TIMER_TARGET1_LO timer taget1 low 32 bits 0 32 read-write TARGET2_HI system timer comp2 value high register 0x2C 0x20 TIMER_TARGET2_HI timer taget2 high 20 bits 0 20 read-write TARGET2_LO system timer comp2 value low register 0x30 0x20 TIMER_TARGET2_LO timer taget2 low 32 bits 0 32 read-write TARGET0_CONF system timer comp0 target mode register 0x34 0x20 TARGET0_PERIOD target0 period 0 26 read-write TARGET0_PERIOD_MODE Set target0 to period mode 30 1 read-write TARGET0_TIMER_UNIT_SEL select which unit to compare 31 1 read-write TARGET1_CONF system timer comp1 target mode register 0x38 0x20 TARGET1_PERIOD target1 period 0 26 read-write TARGET1_PERIOD_MODE Set target1 to period mode 30 1 read-write TARGET1_TIMER_UNIT_SEL select which unit to compare 31 1 read-write TARGET2_CONF system timer comp2 target mode register 0x3C 0x20 TARGET2_PERIOD target2 period 0 26 read-write TARGET2_PERIOD_MODE Set target2 to period mode 30 1 read-write TARGET2_TIMER_UNIT_SEL select which unit to compare 31 1 read-write UNIT0_VALUE_HI system timer unit0 value high register 0x40 0x20 TIMER_UNIT0_VALUE_HI timer read value high 20bits 0 20 read-only UNIT0_VALUE_LO system timer unit0 value low register 0x44 0x20 TIMER_UNIT0_VALUE_LO timer read value low 32bits 0 32 read-only UNIT1_VALUE_HI system timer unit1 value high register 0x48 0x20 TIMER_UNIT1_VALUE_HI timer read value high 20bits 0 20 read-only UNIT1_VALUE_LO system timer unit1 value low register 0x4C 0x20 TIMER_UNIT1_VALUE_LO timer read value low 32bits 0 32 read-only COMP0_LOAD system timer comp0 conf sync register 0x50 0x20 TIMER_COMP0_LOAD timer comp0 sync enable signal 0 1 write-only COMP1_LOAD system timer comp1 conf sync register 0x54 0x20 TIMER_COMP1_LOAD timer comp1 sync enable signal 0 1 write-only COMP2_LOAD system timer comp2 conf sync register 0x58 0x20 TIMER_COMP2_LOAD timer comp2 sync enable signal 0 1 write-only UNIT0_LOAD system timer unit0 conf sync register 0x5C 0x20 TIMER_UNIT0_LOAD timer unit0 sync enable signal 0 1 write-only UNIT1_LOAD system timer unit1 conf sync register 0x60 0x20 TIMER_UNIT1_LOAD timer unit1 sync enable signal 0 1 write-only INT_ENA systimer interrupt enable register 0x64 0x20 TARGET0_INT_ENA interupt0 enable 0 1 read-write TARGET1_INT_ENA interupt1 enable 1 1 read-write TARGET2_INT_ENA interupt2 enable 2 1 read-write INT_RAW systimer interrupt raw register 0x68 0x20 TARGET0_INT_RAW interupt0 raw 0 1 read-write TARGET1_INT_RAW interupt1 raw 1 1 read-write TARGET2_INT_RAW interupt2 raw 2 1 read-write INT_CLR systimer interrupt clear register 0x6C 0x20 TARGET0_INT_CLR interupt0 clear 0 1 write-only TARGET1_INT_CLR interupt1 clear 1 1 write-only TARGET2_INT_CLR interupt2 clear 2 1 write-only INT_ST systimer interrupt status register 0x70 0x20 TARGET0_INT_ST interupt0 status 0 1 read-only TARGET1_INT_ST interupt1 status 1 1 read-only TARGET2_INT_ST interupt2 status 2 1 read-only DATE system timer version control register 0xFC 0x20 0x02012251 DATE systimer register version 0 32 read-write TIMG0 Timer Group 0 TIMG 0x6001F000 0x0 0x68 registers TG0_T0_LEVEL 23 TG0_WDT_LEVEL 24 T0CONFIG Timer %s configuration register 0x0 0x20 0x60002000 USE_XTAL 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group. 9 1 read-write ALARM_EN When set, the alarm is enabled. This bit is automatically cleared once an alarm occurs. 10 1 read-write DIVCNT_RST When set, Timer %s 's clock divider counter will be reset. 12 1 write-only DIVIDER Timer %s clock (T%s_clk) prescaler value. 13 16 read-write AUTORELOAD When set, timer %s auto-reload at alarm is enabled. 29 1 read-write INCREASE When set, the timer %s time-base counter will increment every clock tick. When cleared, the timer %s time-base counter will decrement. 30 1 read-write EN When set, the timer %s time-base counter is enabled. 31 1 read-write T0LO Timer %s current value, low 32 bits 0x4 0x20 LO After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter of timer %s can be read here. 0 32 read-only T0HI Timer %s current value, high 22 bits 0x8 0x20 T0_HI After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter of timer %s can be read here. 0 22 read-only T0UPDATE Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG 0xC 0x20 T0_UPDATE After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched. 31 1 read-write T0ALARMLO Timer %s alarm value, low 32 bits 0x10 0x20 ALARM_LO Timer %s alarm trigger time-base counter value, low 32 bits. 0 32 read-write T0ALARMHI Timer %s alarm value, high bits 0x14 0x20 ALARM_HI Timer %s alarm trigger time-base counter value, high 22 bits. 0 22 read-write T0LOADLO Timer %s reload value, low 32 bits 0x18 0x20 LOAD_LO Low 32 bits of the value that a reload will load onto timer %s time-base Counter. 0 32 read-write T0LOADHI Timer %s reload value, high 22 bits 0x1C 0x20 LOAD_HI High 22 bits of the value that a reload will load onto timer %s time-base counter. 0 22 read-write T0LOAD Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG 0x20 0x20 LOAD Write any value to trigger a timer %s time-base counter reload. 0 32 write-only WDTCONFIG0 Watchdog timer configuration register 0x48 0x20 0x0004C000 WDT_APPCPU_RESET_EN WDT reset CPU enable. 12 1 read-write WDT_PROCPU_RESET_EN WDT reset CPU enable. 13 1 read-write WDT_FLASHBOOT_MOD_EN When set, Flash boot protection is enabled. 14 1 read-write WDT_SYS_RESET_LENGTH System reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. 15 3 read-write WDT_CPU_RESET_LENGTH CPU reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. 18 3 read-write WDT_USE_XTAL choose WDT clock:0-apb_clk; 1-xtal_clk. 21 1 read-write WDT_CONF_UPDATE_EN update the WDT configuration registers 22 1 write-only WDT_STG3 Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 23 2 read-write WDT_STG2 Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 25 2 read-write WDT_STG1 Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 27 2 read-write WDT_STG0 Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 29 2 read-write WDT_EN When set, MWDT is enabled. 31 1 read-write WDTCONFIG1 Watchdog timer prescaler register 0x4C 0x20 0x00010000 WDT_DIVCNT_RST When set, WDT 's clock divider counter will be reset. 0 1 write-only WDT_CLK_PRESCALE MWDT clock prescaler value. MWDT clock period = 12.5 ns * TIMG_WDT_CLK_PRESCALE. 16 16 read-write WDTCONFIG2 Watchdog timer stage 0 timeout value 0x50 0x20 0x018CBA80 WDT_STG0_HOLD Stage 0 timeout value, in MWDT clock cycles. 0 32 read-write WDTCONFIG3 Watchdog timer stage 1 timeout value 0x54 0x20 0x07FFFFFF WDT_STG1_HOLD Stage 1 timeout value, in MWDT clock cycles. 0 32 read-write WDTCONFIG4 Watchdog timer stage 2 timeout value 0x58 0x20 0x000FFFFF WDT_STG2_HOLD Stage 2 timeout value, in MWDT clock cycles. 0 32 read-write WDTCONFIG5 Watchdog timer stage 3 timeout value 0x5C 0x20 0x000FFFFF WDT_STG3_HOLD Stage 3 timeout value, in MWDT clock cycles. 0 32 read-write WDTFEED Write to feed the watchdog timer 0x60 0x20 WDT_FEED Write any value to feed the MWDT. (WO) 0 32 write-only WDTWPROTECT Watchdog write protect register 0x64 0x20 0x50D83AA1 WDT_WKEY If the register contains a different value than its reset value, write protection is enabled. 0 32 read-write RTCCALICFG RTC calibration configure register 0x68 0x20 0x00013000 RTC_CALI_START_CYCLING Reserved 12 1 read-write RTC_CALI_CLK_SEL 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. 13 2 read-write RTC_CALI_RDY Reserved 15 1 read-only RTC_CALI_MAX Reserved 16 15 read-write RTC_CALI_START Reserved 31 1 read-write RTCCALICFG1 RTC calibration configure1 register 0x6C 0x20 RTC_CALI_CYCLING_DATA_VLD Reserved 0 1 read-only RTC_CALI_VALUE Reserved 7 25 read-only INT_ENA_TIMERS Interrupt enable bits 0x70 0x20 T0_INT_ENA The interrupt enable bit for the TIMG_T0_INT interrupt. 0 1 read-write WDT_INT_ENA The interrupt enable bit for the TIMG_WDT_INT interrupt. 1 1 read-write INT_RAW_TIMERS Raw interrupt status 0x74 0x20 T0_INT_RAW The raw interrupt status bit for the TIMG_T0_INT interrupt. 0 1 read-only WDT_INT_RAW The raw interrupt status bit for the TIMG_WDT_INT interrupt. 1 1 read-only INT_ST_TIMERS Masked interrupt status 0x78 0x20 T0_INT_ST The masked interrupt status bit for the TIMG_T0_INT interrupt. 0 1 read-only WDT_INT_ST The masked interrupt status bit for the TIMG_WDT_INT interrupt. 1 1 read-only INT_CLR_TIMERS Interrupt clear bits 0x7C 0x20 T0_INT_CLR Set this bit to clear the TIMG_T0_INT interrupt. 0 1 write-only WDT_INT_CLR Set this bit to clear the TIMG_WDT_INT interrupt. 1 1 write-only RTCCALICFG2 Timer group calibration register 0x80 0x20 0xFFFFFF98 RTC_CALI_TIMEOUT RTC calibration timeout indicator 0 1 read-only RTC_CALI_TIMEOUT_RST_CNT Cycles that release calibration timeout reset 3 4 read-write RTC_CALI_TIMEOUT_THRES Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered. 7 25 read-write NTIMERS_DATE Timer version control register 0xF8 0x20 0x02006191 NTIMGS_DATE Timer version control register 0 28 read-write REGCLK Timer group clock gate register 0xFC 0x20 0x60000000 WDT_CLK_IS_ACTIVE enable WDT's clock 29 1 read-write TIMER_CLK_IS_ACTIVE enable Timer 30's clock 30 1 read-write CLK_EN Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software. 31 1 read-write UART0 UART (Universal Asynchronous Receiver-Transmitter) Controller 0 UART 0x60000000 0x0 0x84 registers UART0 17 FIFO FIFO data register 0x0 0x20 RXFIFO_RD_BYTE UART 0 accesses FIFO via this register. 0 8 read-write INT_RAW Raw interrupt status 0x4 0x20 0x00000002 RXFIFO_FULL_INT_RAW This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. 0 1 read-write TXFIFO_EMPTY_INT_RAW This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . 1 1 read-write PARITY_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a parity error in the data. 2 1 read-write FRM_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a data frame error . 3 1 read-write RXFIFO_OVF_INT_RAW This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. 4 1 read-write DSR_CHG_INT_RAW This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. 5 1 read-write CTS_CHG_INT_RAW This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. 6 1 read-write BRK_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. 7 1 read-write RXFIFO_TOUT_INT_RAW This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. 8 1 read-write SW_XON_INT_RAW This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. 9 1 read-write SW_XOFF_INT_RAW This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. 10 1 read-write GLITCH_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. 11 1 read-write TX_BRK_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent. 12 1 read-write TX_BRK_IDLE_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. 13 1 read-write TX_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. 14 1 read-write RS485_PARITY_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. 15 1 read-write RS485_FRM_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. 16 1 read-write RS485_CLASH_INT_RAW This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. 17 1 read-write AT_CMD_CHAR_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. 18 1 read-write WAKEUP_INT_RAW This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. 19 1 read-write INT_ST Masked interrupt status 0x8 0x20 RXFIFO_FULL_INT_ST This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. 0 1 read-only TXFIFO_EMPTY_INT_ST This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. 1 1 read-only PARITY_ERR_INT_ST This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. 2 1 read-only FRM_ERR_INT_ST This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. 3 1 read-only RXFIFO_OVF_INT_ST This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. 4 1 read-only DSR_CHG_INT_ST This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. 5 1 read-only CTS_CHG_INT_ST This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. 6 1 read-only BRK_DET_INT_ST This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. 7 1 read-only RXFIFO_TOUT_INT_ST This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. 8 1 read-only SW_XON_INT_ST This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. 9 1 read-only SW_XOFF_INT_ST This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. 10 1 read-only GLITCH_DET_INT_ST This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. 11 1 read-only TX_BRK_DONE_INT_ST This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. 12 1 read-only TX_BRK_IDLE_DONE_INT_ST This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. 13 1 read-only TX_DONE_INT_ST This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. 14 1 read-only RS485_PARITY_ERR_INT_ST This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. 15 1 read-only RS485_FRM_ERR_INT_ST This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. 16 1 read-only RS485_CLASH_INT_ST This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. 17 1 read-only AT_CMD_CHAR_DET_INT_ST This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. 18 1 read-only WAKEUP_INT_ST This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. 19 1 read-only INT_ENA Interrupt enable bits 0xC 0x20 RXFIFO_FULL_INT_ENA This is the enable bit for rxfifo_full_int_st register. 0 1 read-write TXFIFO_EMPTY_INT_ENA This is the enable bit for txfifo_empty_int_st register. 1 1 read-write PARITY_ERR_INT_ENA This is the enable bit for parity_err_int_st register. 2 1 read-write FRM_ERR_INT_ENA This is the enable bit for frm_err_int_st register. 3 1 read-write RXFIFO_OVF_INT_ENA This is the enable bit for rxfifo_ovf_int_st register. 4 1 read-write DSR_CHG_INT_ENA This is the enable bit for dsr_chg_int_st register. 5 1 read-write CTS_CHG_INT_ENA This is the enable bit for cts_chg_int_st register. 6 1 read-write BRK_DET_INT_ENA This is the enable bit for brk_det_int_st register. 7 1 read-write RXFIFO_TOUT_INT_ENA This is the enable bit for rxfifo_tout_int_st register. 8 1 read-write SW_XON_INT_ENA This is the enable bit for sw_xon_int_st register. 9 1 read-write SW_XOFF_INT_ENA This is the enable bit for sw_xoff_int_st register. 10 1 read-write GLITCH_DET_INT_ENA This is the enable bit for glitch_det_int_st register. 11 1 read-write TX_BRK_DONE_INT_ENA This is the enable bit for tx_brk_done_int_st register. 12 1 read-write TX_BRK_IDLE_DONE_INT_ENA This is the enable bit for tx_brk_idle_done_int_st register. 13 1 read-write TX_DONE_INT_ENA This is the enable bit for tx_done_int_st register. 14 1 read-write RS485_PARITY_ERR_INT_ENA This is the enable bit for rs485_parity_err_int_st register. 15 1 read-write RS485_FRM_ERR_INT_ENA This is the enable bit for rs485_parity_err_int_st register. 16 1 read-write RS485_CLASH_INT_ENA This is the enable bit for rs485_clash_int_st register. 17 1 read-write AT_CMD_CHAR_DET_INT_ENA This is the enable bit for at_cmd_char_det_int_st register. 18 1 read-write WAKEUP_INT_ENA This is the enable bit for uart_wakeup_int_st register. 19 1 read-write INT_CLR Interrupt clear bits 0x10 0x20 RXFIFO_FULL_INT_CLR Set this bit to clear the rxfifo_full_int_raw interrupt. 0 1 write-only TXFIFO_EMPTY_INT_CLR Set this bit to clear txfifo_empty_int_raw interrupt. 1 1 write-only PARITY_ERR_INT_CLR Set this bit to clear parity_err_int_raw interrupt. 2 1 write-only FRM_ERR_INT_CLR Set this bit to clear frm_err_int_raw interrupt. 3 1 write-only RXFIFO_OVF_INT_CLR Set this bit to clear rxfifo_ovf_int_raw interrupt. 4 1 write-only DSR_CHG_INT_CLR Set this bit to clear the dsr_chg_int_raw interrupt. 5 1 write-only CTS_CHG_INT_CLR Set this bit to clear the cts_chg_int_raw interrupt. 6 1 write-only BRK_DET_INT_CLR Set this bit to clear the brk_det_int_raw interrupt. 7 1 write-only RXFIFO_TOUT_INT_CLR Set this bit to clear the rxfifo_tout_int_raw interrupt. 8 1 write-only SW_XON_INT_CLR Set this bit to clear the sw_xon_int_raw interrupt. 9 1 write-only SW_XOFF_INT_CLR Set this bit to clear the sw_xoff_int_raw interrupt. 10 1 write-only GLITCH_DET_INT_CLR Set this bit to clear the glitch_det_int_raw interrupt. 11 1 write-only TX_BRK_DONE_INT_CLR Set this bit to clear the tx_brk_done_int_raw interrupt.. 12 1 write-only TX_BRK_IDLE_DONE_INT_CLR Set this bit to clear the tx_brk_idle_done_int_raw interrupt. 13 1 write-only TX_DONE_INT_CLR Set this bit to clear the tx_done_int_raw interrupt. 14 1 write-only RS485_PARITY_ERR_INT_CLR Set this bit to clear the rs485_parity_err_int_raw interrupt. 15 1 write-only RS485_FRM_ERR_INT_CLR Set this bit to clear the rs485_frm_err_int_raw interrupt. 16 1 write-only RS485_CLASH_INT_CLR Set this bit to clear the rs485_clash_int_raw interrupt. 17 1 write-only AT_CMD_CHAR_DET_INT_CLR Set this bit to clear the at_cmd_char_det_int_raw interrupt. 18 1 write-only WAKEUP_INT_CLR Set this bit to clear the uart_wakeup_int_raw interrupt. 19 1 write-only CLKDIV Clock divider configuration 0x14 0x20 0x000002B6 CLKDIV The integral part of the frequency divider factor. 0 12 read-write FRAG The decimal part of the frequency divider factor. 20 4 read-write RX_FILT Rx Filter configuration 0x18 0x20 0x00000008 GLITCH_FILT when input pulse width is lower than this value, the pulse is ignored. 0 8 read-write GLITCH_FILT_EN Set this bit to enable Rx signal filter. 8 1 read-write STATUS UART status register 0x1C 0x20 0xE000C000 RXFIFO_CNT Stores the byte number of valid data in Rx-FIFO. 0 10 read-only DSRN The register represent the level value of the internal uart dsr signal. 13 1 read-only CTSN This register represent the level value of the internal uart cts signal. 14 1 read-only RXD This register represent the level value of the internal uart rxd signal. 15 1 read-only TXFIFO_CNT Stores the byte number of data in Tx-FIFO. 16 10 read-only DTRN This bit represents the level of the internal uart dtr signal. 29 1 read-only RTSN This bit represents the level of the internal uart rts signal. 30 1 read-only TXD This bit represents the level of the internal uart txd signal. 31 1 read-only CONF0 a 0x20 0x20 0x1000001C PARITY This register is used to configure the parity check mode. 0 1 read-write PARITY_EN Set this bit to enable uart parity check. 1 1 read-write BIT_NUM This register is used to set the length of data. 2 2 read-write STOP_BIT_NUM This register is used to set the length of stop bit. 4 2 read-write SW_RTS This register is used to configure the software rts signal which is used in software flow control. 6 1 read-write SW_DTR This register is used to configure the software dtr signal which is used in software flow control. 7 1 read-write TXD_BRK Set this bit to enbale transmitter to send NULL when the process of sending data is done. 8 1 read-write IRDA_DPLX Set this bit to enable IrDA loopback mode. 9 1 read-write IRDA_TX_EN This is the start enable bit for IrDA transmitter. 10 1 read-write IRDA_WCTL 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0. 11 1 read-write IRDA_TX_INV Set this bit to invert the level of IrDA transmitter. 12 1 read-write IRDA_RX_INV Set this bit to invert the level of IrDA receiver. 13 1 read-write LOOPBACK Set this bit to enable uart loopback test mode. 14 1 read-write TX_FLOW_EN Set this bit to enable flow control function for transmitter. 15 1 read-write IRDA_EN Set this bit to enable IrDA protocol. 16 1 read-write RXFIFO_RST Set this bit to reset the uart receive-FIFO. 17 1 read-write TXFIFO_RST Set this bit to reset the uart transmit-FIFO. 18 1 read-write RXD_INV Set this bit to inverse the level value of uart rxd signal. 19 1 read-write CTS_INV Set this bit to inverse the level value of uart cts signal. 20 1 read-write DSR_INV Set this bit to inverse the level value of uart dsr signal. 21 1 read-write TXD_INV Set this bit to inverse the level value of uart txd signal. 22 1 read-write RTS_INV Set this bit to inverse the level value of uart rts signal. 23 1 read-write DTR_INV Set this bit to inverse the level value of uart dtr signal. 24 1 read-write CLK_EN 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. 25 1 read-write ERR_WR_MASK 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. 26 1 read-write AUTOBAUD_EN This is the enable bit for detecting baudrate. 27 1 read-write MEM_CLK_EN UART memory clock gate enable signal. 28 1 read-write CONF1 Configuration register 1 0x24 0x20 0x0000C060 RXFIFO_FULL_THRHD It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. 0 9 read-write TXFIFO_EMPTY_THRHD It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. 9 9 read-write DIS_RX_DAT_OVF Disable UART Rx data overflow detect. 18 1 read-write RX_TOUT_FLOW_DIS Set this bit to stop accumulating idle_cnt when hardware flow control works. 19 1 read-write RX_FLOW_EN This is the flow enable bit for UART receiver. 20 1 read-write RX_TOUT_EN This is the enble bit for uart receiver's timeout function. 21 1 read-write LOWPULSE Autobaud minimum low pulse duration register 0x28 0x20 0x00000FFF MIN_CNT This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. 0 12 read-only HIGHPULSE Autobaud minimum high pulse duration register 0x2C 0x20 0x00000FFF MIN_CNT This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. 0 12 read-only RXD_CNT Autobaud edge change count register 0x30 0x20 RXD_EDGE_CNT This register stores the count of rxd edge change. It is used in baud rate-detect process. 0 10 read-only FLOW_CONF Software flow-control configuration 0x34 0x20 SW_FLOW_CON_EN Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. 0 1 read-write XONOFF_DEL Set this bit to remove flow control char from the received data. 1 1 read-write FORCE_XON Set this bit to enable the transmitter to go on sending data. 2 1 read-write FORCE_XOFF Set this bit to stop the transmitter from sending data. 3 1 read-write SEND_XON Set this bit to send Xon char. It is cleared by hardware automatically. 4 1 read-write SEND_XOFF Set this bit to send Xoff char. It is cleared by hardware automatically. 5 1 read-write SLEEP_CONF Sleep-mode configuration 0x38 0x20 0x000000F0 ACTIVE_THRESHOLD The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. 0 10 read-write SWFC_CONF0 Software flow-control character configuration 0x3C 0x20 0x000026E0 XOFF_THRESHOLD When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char. 0 9 read-write XOFF_CHAR This register stores the Xoff flow control char. 9 8 read-write SWFC_CONF1 Software flow-control character configuration 0x40 0x20 0x00002200 XON_THRESHOLD When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char. 0 9 read-write XON_CHAR This register stores the Xon flow control char. 9 8 read-write TXBRK_CONF Tx Break character configuration 0x44 0x20 0x0000000A TX_BRK_NUM This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. 0 8 read-write IDLE_CONF Frame-end idle configuration 0x48 0x20 0x00040100 RX_IDLE_THRHD It will produce frame end signal when receiver takes more time to receive one byte data than this register value. 0 10 read-write TX_IDLE_NUM This register is used to configure the duration time between transfers. 10 10 read-write RS485_CONF RS485 mode configuration 0x4C 0x20 RS485_EN Set this bit to choose the rs485 mode. 0 1 read-write DL0_EN Set this bit to delay the stop bit by 1 bit. 1 1 read-write DL1_EN Set this bit to delay the stop bit by 1 bit. 2 1 read-write RS485TX_RX_EN Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. 3 1 read-write RS485RXBY_TX_EN 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. 4 1 read-write RS485_RX_DLY_NUM This register is used to delay the receiver's internal data signal. 5 1 read-write RS485_TX_DLY_NUM This register is used to delay the transmitter's internal data signal. 6 4 read-write AT_CMD_PRECNT Pre-sequence timing configuration 0x50 0x20 0x00000901 PRE_IDLE_NUM This register is used to configure the idle duration time before the first at_cmd is received by receiver. 0 16 read-write AT_CMD_POSTCNT Post-sequence timing configuration 0x54 0x20 0x00000901 POST_IDLE_NUM This register is used to configure the duration time between the last at_cmd and the next data. 0 16 read-write AT_CMD_GAPTOUT Timeout configuration 0x58 0x20 0x0000000B RX_GAP_TOUT This register is used to configure the duration time between the at_cmd chars. 0 16 read-write AT_CMD_CHAR AT escape sequence detection configuration 0x5C 0x20 0x0000032B AT_CMD_CHAR This register is used to configure the content of at_cmd char. 0 8 read-write CHAR_NUM This register is used to configure the num of continuous at_cmd chars received by receiver. 8 8 read-write MEM_CONF UART threshold and allocation configuration 0x60 0x20 0x000A0012 RX_SIZE This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes. 1 3 read-write TX_SIZE This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes. 4 3 read-write RX_FLOW_THRHD This register is used to configure the maximum amount of data that can be received when hardware flow control works. 7 9 read-write RX_TOUT_THRHD This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. 16 10 read-write MEM_FORCE_PD Set this bit to force power down UART memory. 26 1 read-write MEM_FORCE_PU Set this bit to force power up UART memory. 27 1 read-write MEM_TX_STATUS Tx-FIFO write and read offset address. 0x64 0x20 APB_TX_WADDR This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB. 0 10 read-only TX_RADDR This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl. 11 10 read-only MEM_RX_STATUS Rx-FIFO write and read offset address. 0x68 0x20 0x00080100 APB_RX_RADDR This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180. 0 10 read-only RX_WADDR This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180. 11 10 read-only FSM_STATUS UART transmit and receive status. 0x6C 0x20 ST_URX_OUT This is the status register of receiver. 0 4 read-only ST_UTX_OUT This is the status register of transmitter. 4 4 read-only POSPULSE Autobaud high pulse register 0x70 0x20 0x00000FFF POSEDGE_MIN_CNT This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. 0 12 read-only NEGPULSE Autobaud low pulse register 0x74 0x20 0x00000FFF NEGEDGE_MIN_CNT This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. 0 12 read-only CLK_CONF UART core clock configuration 0x78 0x20 0x03701000 SCLK_DIV_B The denominator of the frequency divider factor. 0 6 read-write SCLK_DIV_A The numerator of the frequency divider factor. 6 6 read-write SCLK_DIV_NUM The integral part of the frequency divider factor. 12 8 read-write SCLK_SEL UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL. 20 2 read-write SCLK_EN Set this bit to enable UART Tx/Rx clock. 22 1 read-write RST_CORE Write 1 then write 0 to this bit, reset UART Tx/Rx. 23 1 read-write TX_SCLK_EN Set this bit to enable UART Tx clock. 24 1 read-write RX_SCLK_EN Set this bit to enable UART Rx clock. 25 1 read-write TX_RST_CORE Write 1 then write 0 to this bit, reset UART Tx. 26 1 read-write RX_RST_CORE Write 1 then write 0 to this bit, reset UART Rx. 27 1 read-write DATE UART Version register 0x7C 0x20 0x02008270 DATE This is the version register. 0 32 read-write ID UART ID register 0x80 0x20 0x40000500 ID This register is used to configure the uart_id. 0 30 read-write HIGH_SPEED This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. 30 1 read-write REG_UPDATE Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. 31 1 read-write UART1 UART (Universal Asynchronous Receiver-Transmitter) Controller 1 0x60010000 UART1 18 XTS_AES XTS-AES-128 Flash Encryption XTS_AES 0x600CC000 0x0 0x30 registers 16 0x1 PLAIN_MEM[%s] The memory that stores plaintext 0x0 0x8 LINESIZE XTS-AES line-size register 0x40 0x20 LINESIZE This bit stores the line size parameter. 0: 16Byte, 1: 32Byte. 0 1 read-write DESTINATION XTS-AES destination register 0x44 0x20 DESTINATION This bit stores the destination. 0: flash(default). 1: reserved. 0 1 read-write PHYSICAL_ADDRESS XTS-AES physical address register 0x48 0x20 PHYSICAL_ADDRESS Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes. 0 30 read-write TRIGGER XTS-AES trigger register 0x4C 0x20 TRIGGER Set this bit to start manual encryption calculation 0 1 write-only RELEASE XTS-AES release register 0x50 0x20 RELEASE Set this bit to release the manual encrypted result, after that the result will be visible to spi 0 1 write-only DESTROY XTS-AES destroy register 0x54 0x20 DESTROY Set this bit to destroy XTS-AES result. 0 1 write-only STATE XTS-AES status register 0x58 0x20 STATE Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means the encrypted result is generated but not visible to mspi. USE means that the encrypted result is visible to mspi. 0 2 read-only DATE XTS-AES version control register 0x5C 0x20 0x20200623 DATE Those bits stores the version information of XTS-AES. 0 30 read-write