Cypress Semiconductor Cypress psoc63 psoc63 1.0 PSoC 63 (Connectivity Line): Dual-core Cortex-M4/M0+ MCU series with programmable digital and analog peripherals, advanced graphics, CapSense, crypto and secure boot security, with integrated high-speed wired and wireless connectivity. Copyright 2016-2018 Cypress Semiconductor Corporation \n \n Licensed under the Apache License, Version 2.0 (the "License"); \n you may not use this file except in compliance with the License. \n You may obtain a copy of the License at \n \n http://www.apache.org/licenses/LICENSE-2.0 \n Unless required by applicable law or agreed to in writing, software \n distributed under the License is distributed on an "AS IS" BASIS, \n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. \n See the License for the specific language governing permissions and \n limitations under the License. CM4 r0p1 little true true 1 3 0 8 32 0x00000000 0xFFFFFFFF PERI Peripheral interconnect 0x40010000 0 65536 registers 11 64 GR[%s] Peripheral group structure 0x00000000 CLOCK_CTL Clock control 0x0 32 read-write 0x0 0xFF00 INT8_DIV Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write SL_CTL Slave control 0x20 32 read-write 0xFFFF 0xFFFF ENABLED_0 Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled. [0:0] read-only ENABLED_1 Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. [1:1] read-write ENABLED_2 Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. [2:2] read-write ENABLED_3 N/A [3:3] read-write ENABLED_4 N/A [4:4] read-write ENABLED_5 N/A [5:5] read-write ENABLED_6 N/A [6:6] read-write ENABLED_7 N/A [7:7] read-write ENABLED_8 N/A [8:8] read-write ENABLED_9 N/A [9:9] read-write ENABLED_10 N/A [10:10] read-write ENABLED_11 N/A [11:11] read-write ENABLED_12 N/A [12:12] read-write ENABLED_13 N/A [13:13] read-write ENABLED_14 N/A [14:14] read-write ENABLED_15 N/A [15:15] read-write TIMEOUT_CTL Timeout control 0x24 32 read-write 0xFFFF 0xFFFF TIMEOUT This field specifies a number of peripheral group (clk_group) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). '0x0000'-'0xfffe': Number of peripheral group clock cycles. '0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated. [15:0] read-write DIV_CMD Divider command register 0x400 32 read-write 0xFFFF 0xC000FFFF DIV_SEL (TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated. [5:0] read-write TYPE_SEL Specifies the divider type of the divider on which the command is performed: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. [7:6] read-write PA_DIV_SEL (PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times. If PA_DIV_SEL is '63' and PA_TYPE_SEL is '3', 'clk_peri' is used as reference. [13:8] read-write PA_TYPE_SEL Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. [15:14] read-write DISABLE Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled. The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately. [30:30] read-write ENABLE Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: 0: Disable the divider using the DIV_CMD.DISABLE field. 1: Configure the divider's DIV_XXX_CTL register. 2: Enable the divider using the DIV_CMD_ENABLE field. The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_peri' (typical usage) or to ANY enabled divider. The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider. The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_peri'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_peri' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process. [31:31] read-write 64 4 DIV_8_CTL[%s] Divider control register (for 8.0 divider) 0x800 32 read-write 0x0 0xFF01 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write 64 4 DIV_16_CTL[%s] Divider control register (for 16.0 divider) 0x900 32 read-write 0x0 0xFFFF01 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [23:8] read-write 64 4 DIV_16_5_CTL[%s] Divider control register (for 16.5 divider) 0xA00 32 read-write 0x0 0xFFFFF9 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [7:3] read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [23:8] read-write 63 4 DIV_24_5_CTL[%s] Divider control register (for 24.5 divider) 0xB00 32 read-write 0x0 0xFFFFFFF9 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [7:3] read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [31:8] read-write 128 4 CLOCK_CTL[%s] Clock control register 0xC00 32 read-write 0xFF 0xFF DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. [5:0] read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. [7:6] read-write TR_CMD Trigger command register 0x1000 32 read-write 0x0 0xC0FF0FFF TR_SEL Specifies the activated trigger when ACTIVATE is '1'. OUT_SEL specifies whether the activated trigger is an input trigger or output trigger to the trigger multiplexer. During activation (ACTIVATE is '1'), SW should not modify this register field. If the specified trigger is not present, the trigger activation has no effect. [7:0] read-write GROUP_SEL Specifies the trigger group. [11:8] read-write COUNT Amount of 'clk_peri' cycles a specific trigger is activated. During activation (ACTIVATE is '1'), HW decrements this field to '0' using a cycle counter. During activation, SW should not modify this register field. A value of 255 is a special case: HW does NOT decrement this field to '0' and trigger activation is under direct control of ACTIVATE when ACTIVATE is '1' the trigger is activated and when ACTIVATE is '0' the trigger is deactivated. [23:16] read-write OUT_SEL Specifies whether trigger activation is for a specific input or ouput trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only. '0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer. '1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer. [30:30] read-write ACTIVATE SW sets this field to '1' by to activate (set to '1') a trigger as identified by TR_SEL and OUT_SEL for COUNT cycles. HW sets this field to '0' when the cycle counter is decremented to '0'. Note: a COUNT value of 255 is a special case and trigger activation is under direct control of the ACTIVATE field (the counter is not decremented). [31:31] read-write 15 512 TR_GR[%s] Trigger group 0x00002000 128 4 TR_OUT_CTL[%s] Trigger control register 0x0 32 read-write 0x0 0x3FF TR_SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. [7:0] read-write TR_INV Specifies if the output trigger is inverted. [8:8] read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. [9:9] read-write 16 64 PPU_PR[%s] PPU structure with programmable address 0x00004000 ADDR0 PPU region address 0 (slave structure) 0x0 32 read-write 0x0 0x0 SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. [7:0] read-write ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. [31:8] read-write ATT0 PPU region attributes 0 (slave structure) 0x4 32 read-write 0x124 0x80000124 UR User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed). [0:0] read-write UW User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed). [1:1] read-write UX User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed). [2:2] read-only PR Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed). [3:3] read-write PW Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed). [4:4] read-write PX Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed). [5:5] read-only NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [6:6] read-write PC_MASK_0 This field specifies protection context identifier based access control for protection context '0'. [8:8] read-only PC_MASK_15_TO_1 This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. [23:9] read-write REGION_SIZE This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-write PC_MATCH This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. [30:30] read-write ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption. [31:31] read-write ADDR1 PPU region address 1 (master structure) 0x20 32 read-only 0x0 0xFFFFFFFF SUBREGION_DISABLE See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. [7:0] read-only ADDR24 See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only. [31:8] read-only ATT1 PPU region attributes 1 (master structure) 0x24 32 read-write 0x7000109 0x9F00012D UR See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. [0:0] read-only UW See corresponding field for PPU structure with programmable address. [1:1] read-write UX See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. [2:2] read-only PR See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. [3:3] read-only PW See corresponding field for PPU structure with programmable address. [4:4] read-write PX See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. [5:5] read-only NS See corresponding field for PPU structure with programmable address. [6:6] read-write PC_MASK_0 See corresponding field for PPU structure with programmable address. [8:8] read-only PC_MASK_15_TO_1 See corresponding field for PPU structure with programmable address. [23:9] read-write REGION_SIZE See corresponding field for PPU structure with programmable address. '7': 256 B region [28:24] read-only PC_MATCH See corresponding field for PPU structure with programmable address. [30:30] read-write ENABLED See corresponding field for PPU structure with programmable address. [31:31] read-write 11 64 PPU_GR[%s] PPU structure with fixed/constant address for a peripheral group 0x00005000 ADDR0 PPU region address 0 (slave structure) 0x0 32 read-only 0x0 0xFFFFFFFF SUBREGION_DISABLE See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific. [7:0] read-only ADDR24 See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': address of protected region. Note: this field is read-only. Its value is chip specific. [31:8] read-only ATT0 PPU region attributes 0 (slave structure) 0x4 32 read-write 0x124 0x9F000124 UR See corresponding field for PPU structure with programmable address. [0:0] read-write UW See corresponding field for PPU structure with programmable address. [1:1] read-write UX See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. [2:2] read-only PR See corresponding field for PPU structure with programmable address. [3:3] read-write PW See corresponding field for PPU structure with programmable address. [4:4] read-write PX See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. [5:5] read-only NS See corresponding field for PPU structure with programmable address. [6:6] read-write PC_MASK_0 See corresponding field for PPU structure with programmable address. [8:8] read-only PC_MASK_15_TO_1 See corresponding field for PPU structure with programmable address. [23:9] read-write REGION_SIZE See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific. [28:24] read-only PC_MATCH See corresponding field for PPU structure with programmable address. [30:30] read-write ENABLED See corresponding field for PPU structure with programmable address. [31:31] read-write ADDR1 PPU region address 1 (master structure) 0x20 32 read-only 0x0 0xFFFFFFFF SUBREGION_DISABLE See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. [7:0] read-only ADDR24 See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only. [31:8] read-only ATT1 PPU region attributes 1 (master structure) 0x24 32 read-write 0x7000109 0x9F00012D UR See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. [0:0] read-only UW See corresponding field for PPU structure with programmable address. [1:1] read-write UX See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. [2:2] read-only PR See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. [3:3] read-only PW See corresponding field for PPU structure with programmable address. [4:4] read-write PX See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. [5:5] read-only NS See corresponding field for PPU structure with programmable address. [6:6] read-write PC_MASK_0 See corresponding field for PPU structure with programmable address. [8:8] read-only PC_MASK_15_TO_1 See corresponding field for PPU structure with programmable address. [23:9] read-write REGION_SIZE See corresponding field for PPU structure with programmable address. '7': 256 B region [28:24] read-only PC_MATCH See corresponding field for PPU structure with programmable address. [30:30] read-write ENABLED See corresponding field for PPU structure with programmable address. [31:31] read-write CPUSS CPU subsystem (CPUSS) 0x40210000 0 65536 registers ioss_interrupts_gpio_0 GPIO Port Interrupt #0 0 ioss_interrupts_gpio_1 GPIO Port Interrupt #1 1 ioss_interrupts_gpio_2 GPIO Port Interrupt #2 2 ioss_interrupts_gpio_3 GPIO Port Interrupt #3 3 ioss_interrupts_gpio_4 GPIO Port Interrupt #4 4 ioss_interrupts_gpio_5 GPIO Port Interrupt #5 5 ioss_interrupts_gpio_6 GPIO Port Interrupt #6 6 ioss_interrupts_gpio_7 GPIO Port Interrupt #7 7 ioss_interrupts_gpio_8 GPIO Port Interrupt #8 8 ioss_interrupts_gpio_9 GPIO Port Interrupt #9 9 ioss_interrupts_gpio_10 GPIO Port Interrupt #10 10 ioss_interrupts_gpio_11 GPIO Port Interrupt #11 11 ioss_interrupts_gpio_12 GPIO Port Interrupt #12 12 ioss_interrupts_gpio_13 GPIO Port Interrupt #13 13 ioss_interrupts_gpio_14 GPIO Port Interrupt #14 14 ioss_interrupt_gpio GPIO All Ports 15 ioss_interrupt_vdd GPIO Supply Detect Interrupt 16 lpcomp_interrupt Low Power Comparator Interrupt 17 scb_8_interrupt Serial Communication Block #8 (DeepSleep capable) 18 srss_interrupt_mcwdt_0 Multi Counter Watchdog Timer interrupt 19 srss_interrupt_mcwdt_1 Multi Counter Watchdog Timer interrupt 20 srss_interrupt_backup Backup domain interrupt 21 srss_interrupt Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) 22 pass_interrupt_ctbs CTBm Interrupt (all CTBms) 23 bless_interrupt Bluetooth Radio interrupt 24 cpuss_interrupts_ipc_0 CPUSS Inter Process Communication Interrupt #0 25 cpuss_interrupts_ipc_1 CPUSS Inter Process Communication Interrupt #1 26 cpuss_interrupts_ipc_2 CPUSS Inter Process Communication Interrupt #2 27 cpuss_interrupts_ipc_3 CPUSS Inter Process Communication Interrupt #3 28 cpuss_interrupts_ipc_4 CPUSS Inter Process Communication Interrupt #4 29 cpuss_interrupts_ipc_5 CPUSS Inter Process Communication Interrupt #5 30 cpuss_interrupts_ipc_6 CPUSS Inter Process Communication Interrupt #6 31 cpuss_interrupts_ipc_7 CPUSS Inter Process Communication Interrupt #7 32 cpuss_interrupts_ipc_8 CPUSS Inter Process Communication Interrupt #8 33 cpuss_interrupts_ipc_9 CPUSS Inter Process Communication Interrupt #9 34 cpuss_interrupts_ipc_10 CPUSS Inter Process Communication Interrupt #10 35 cpuss_interrupts_ipc_11 CPUSS Inter Process Communication Interrupt #11 36 cpuss_interrupts_ipc_12 CPUSS Inter Process Communication Interrupt #12 37 cpuss_interrupts_ipc_13 CPUSS Inter Process Communication Interrupt #13 38 cpuss_interrupts_ipc_14 CPUSS Inter Process Communication Interrupt #14 39 cpuss_interrupts_ipc_15 CPUSS Inter Process Communication Interrupt #15 40 scb_0_interrupt Serial Communication Block #0 41 scb_1_interrupt Serial Communication Block #1 42 scb_2_interrupt Serial Communication Block #2 43 scb_3_interrupt Serial Communication Block #3 44 scb_4_interrupt Serial Communication Block #4 45 scb_5_interrupt Serial Communication Block #5 46 scb_6_interrupt Serial Communication Block #6 47 scb_7_interrupt Serial Communication Block #7 48 csd_interrupt CSD (Capsense) interrupt 49 cpuss_interrupts_dw0_0 CPUSS DataWire #0, Channel #0 50 cpuss_interrupts_dw0_1 CPUSS DataWire #0, Channel #1 51 cpuss_interrupts_dw0_2 CPUSS DataWire #0, Channel #2 52 cpuss_interrupts_dw0_3 CPUSS DataWire #0, Channel #3 53 cpuss_interrupts_dw0_4 CPUSS DataWire #0, Channel #4 54 cpuss_interrupts_dw0_5 CPUSS DataWire #0, Channel #5 55 cpuss_interrupts_dw0_6 CPUSS DataWire #0, Channel #6 56 cpuss_interrupts_dw0_7 CPUSS DataWire #0, Channel #7 57 cpuss_interrupts_dw0_8 CPUSS DataWire #0, Channel #8 58 cpuss_interrupts_dw0_9 CPUSS DataWire #0, Channel #9 59 cpuss_interrupts_dw0_10 CPUSS DataWire #0, Channel #10 60 cpuss_interrupts_dw0_11 CPUSS DataWire #0, Channel #11 61 cpuss_interrupts_dw0_12 CPUSS DataWire #0, Channel #12 62 cpuss_interrupts_dw0_13 CPUSS DataWire #0, Channel #13 63 cpuss_interrupts_dw0_14 CPUSS DataWire #0, Channel #14 64 cpuss_interrupts_dw0_15 CPUSS DataWire #0, Channel #15 65 cpuss_interrupts_dw1_0 CPUSS DataWire #1, Channel #0 66 cpuss_interrupts_dw1_1 CPUSS DataWire #1, Channel #1 67 cpuss_interrupts_dw1_2 CPUSS DataWire #1, Channel #2 68 cpuss_interrupts_dw1_3 CPUSS DataWire #1, Channel #3 69 cpuss_interrupts_dw1_4 CPUSS DataWire #1, Channel #4 70 cpuss_interrupts_dw1_5 CPUSS DataWire #1, Channel #5 71 cpuss_interrupts_dw1_6 CPUSS DataWire #1, Channel #6 72 cpuss_interrupts_dw1_7 CPUSS DataWire #1, Channel #7 73 cpuss_interrupts_dw1_8 CPUSS DataWire #1, Channel #8 74 cpuss_interrupts_dw1_9 CPUSS DataWire #1, Channel #9 75 cpuss_interrupts_dw1_10 CPUSS DataWire #1, Channel #10 76 cpuss_interrupts_dw1_11 CPUSS DataWire #1, Channel #11 77 cpuss_interrupts_dw1_12 CPUSS DataWire #1, Channel #12 78 cpuss_interrupts_dw1_13 CPUSS DataWire #1, Channel #13 79 cpuss_interrupts_dw1_14 CPUSS DataWire #1, Channel #14 80 cpuss_interrupts_dw1_15 CPUSS DataWire #1, Channel #15 81 cpuss_interrupts_fault_0 CPUSS Fault Structure Interrupt #0 82 cpuss_interrupts_fault_1 CPUSS Fault Structure Interrupt #1 83 cpuss_interrupt_crypto CRYPTO Accelerator Interrupt 84 cpuss_interrupt_fm FLASH Macro Interrupt 85 cpuss_interrupts_cm0_cti_0 CM0+ CTI #0 86 cpuss_interrupts_cm0_cti_1 CM0+ CTI #1 87 cpuss_interrupts_cm4_cti_0 CM4 CTI #0 88 cpuss_interrupts_cm4_cti_1 CM4 CTI #1 89 tcpwm_0_interrupts_0 TCPWM #0, Counter #0 90 tcpwm_0_interrupts_1 TCPWM #0, Counter #1 91 tcpwm_0_interrupts_2 TCPWM #0, Counter #2 92 tcpwm_0_interrupts_3 TCPWM #0, Counter #3 93 tcpwm_0_interrupts_4 TCPWM #0, Counter #4 94 tcpwm_0_interrupts_5 TCPWM #0, Counter #5 95 tcpwm_0_interrupts_6 TCPWM #0, Counter #6 96 tcpwm_0_interrupts_7 TCPWM #0, Counter #7 97 tcpwm_1_interrupts_0 TCPWM #1, Counter #0 98 tcpwm_1_interrupts_1 TCPWM #1, Counter #1 99 tcpwm_1_interrupts_2 TCPWM #1, Counter #2 100 tcpwm_1_interrupts_3 TCPWM #1, Counter #3 101 tcpwm_1_interrupts_4 TCPWM #1, Counter #4 102 tcpwm_1_interrupts_5 TCPWM #1, Counter #5 103 tcpwm_1_interrupts_6 TCPWM #1, Counter #6 104 tcpwm_1_interrupts_7 TCPWM #1, Counter #7 105 tcpwm_1_interrupts_8 TCPWM #1, Counter #8 106 tcpwm_1_interrupts_9 TCPWM #1, Counter #9 107 tcpwm_1_interrupts_10 TCPWM #1, Counter #10 108 tcpwm_1_interrupts_11 TCPWM #1, Counter #11 109 tcpwm_1_interrupts_12 TCPWM #1, Counter #12 110 tcpwm_1_interrupts_13 TCPWM #1, Counter #13 111 tcpwm_1_interrupts_14 TCPWM #1, Counter #14 112 tcpwm_1_interrupts_15 TCPWM #1, Counter #15 113 tcpwm_1_interrupts_16 TCPWM #1, Counter #16 114 tcpwm_1_interrupts_17 TCPWM #1, Counter #17 115 tcpwm_1_interrupts_18 TCPWM #1, Counter #18 116 tcpwm_1_interrupts_19 TCPWM #1, Counter #19 117 tcpwm_1_interrupts_20 TCPWM #1, Counter #20 118 tcpwm_1_interrupts_21 TCPWM #1, Counter #21 119 tcpwm_1_interrupts_22 TCPWM #1, Counter #22 120 tcpwm_1_interrupts_23 TCPWM #1, Counter #23 121 udb_interrupts_0 UDB Interrupt #0 122 udb_interrupts_1 UDB Interrupt #1 123 udb_interrupts_2 UDB Interrupt #2 124 udb_interrupts_3 UDB Interrupt #3 125 udb_interrupts_4 UDB Interrupt #4 126 udb_interrupts_5 UDB Interrupt #5 127 udb_interrupts_6 UDB Interrupt #6 128 udb_interrupts_7 UDB Interrupt #7 129 udb_interrupts_8 UDB Interrupt #8 130 udb_interrupts_9 UDB Interrupt #9 131 udb_interrupts_10 UDB Interrupt #10 132 udb_interrupts_11 UDB Interrupt #11 133 udb_interrupts_12 UDB Interrupt #12 134 udb_interrupts_13 UDB Interrupt #13 135 udb_interrupts_14 UDB Interrupt #14 136 udb_interrupts_15 UDB Interrupt #15 137 pass_interrupt_sar SAR ADC interrupt 138 audioss_interrupt_i2s I2S Audio interrupt 139 audioss_interrupt_pdm PDM/PCM Audio interrupt 140 profile_interrupt Energy Profiler interrupt 141 smif_interrupt Serial Memory Interface interrupt 142 usb_interrupt_hi USB Interrupt 143 usb_interrupt_med USB Interrupt 144 usb_interrupt_lo USB Interrupt 145 pass_interrupt_dacs Consolidated interrrupt for all DACs 146 CM0_CTL CM0+ control 0x0 32 read-write 0xFA050002 0xFFFF0003 SLV_STALL Processor debug access control: '0': Access. '1': Stall access. This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses. [0:0] read-write ENABLED Processor enable: '0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot. '1': Enabled. Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented). Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details). [1:1] read-write VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. [31:16] read-only CM0_STATUS CM0+ status 0x8 32 read-only 0x0 0x3 SLEEPING Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. [0:0] read-only SLEEPDEEP Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. [1:1] read-only CM0_CLOCK_CTL CM0+ clock control 0x10 32 read-write 0x1000000 0xFF00FF00 SLOW_INT_DIV Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write PERI_INT_DIV Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. Note that Fperi <= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to '0'. [31:24] read-write CM0_INT_CTL0 CM0+ interrupt control 0 0x20 32 read-write 0xF0F0F0F0 0xFFFFFFFF MUX0_SEL System interrupt select for CPU interrupt source 0. If the field value is 240, no system interrupt is connected and the CPU interrupt source is always '0'/de-activated. [7:0] read-write MUX1_SEL System interrupt select for CPU interrupt source 1. [15:8] read-write MUX2_SEL System interrupt select for CPU interrupt source 2. [23:16] read-write MUX3_SEL System interrupt select for CPU interrupt source 3. [31:24] read-write CM0_INT_CTL1 CM0+ interrupt control 1 0x24 32 read-write 0xF0F0F0F0 0xFFFFFFFF MUX0_SEL System interrupt select for CPU interrupt source 4. [7:0] read-write MUX1_SEL System interrupt select for CPU interrupt source 5. [15:8] read-write MUX2_SEL System interrupt select for CPU interrupt source 6. [23:16] read-write MUX3_SEL System interrupt select for CPU interrupt source 7. [31:24] read-write CM0_INT_CTL2 CM0+ interrupt control 2 0x28 32 read-write 0xF0F0F0F0 0xFFFFFFFF MUX0_SEL System interrupt select for CPU interrupt source 8. [7:0] read-write MUX1_SEL System interrupt select for CPU interrupt source 9. [15:8] read-write MUX2_SEL System interrupt select for CPU interrupt source 10. [23:16] read-write MUX3_SEL System interrupt select for CPU interrupt source 11. [31:24] read-write CM0_INT_CTL3 CM0+ interrupt control 3 0x2C 32 read-write 0xF0F0F0F0 0xFFFFFFFF MUX0_SEL System interrupt select for CPU interrupt source 12. [7:0] read-write MUX1_SEL System interrupt select for CPU interrupt source 13. [15:8] read-write MUX2_SEL System interrupt select for CPU interrupt source 14. [23:16] read-write MUX3_SEL System interrupt select for CPU interrupt source 15. [31:24] read-write CM0_INT_CTL4 CM0+ interrupt control 4 0x30 32 read-write 0xF0F0F0F0 0xFFFFFFFF MUX0_SEL System interrupt select for CPU interrupt source 16. [7:0] read-write MUX1_SEL System interrupt select for CPU interrupt source 17. [15:8] read-write MUX2_SEL System interrupt select for CPU interrupt source 18. [23:16] read-write MUX3_SEL System interrupt select for CPU interrupt source 19. [31:24] read-write CM0_INT_CTL5 CM0+ interrupt control 5 0x34 32 read-write 0xF0F0F0F0 0xFFFFFFFF MUX0_SEL System interrupt select for CPU interrupt source 20. [7:0] read-write MUX1_SEL System interrupt select for CPU interrupt source 21. [15:8] read-write MUX2_SEL System interrupt select for CPU interrupt source 22. [23:16] read-write MUX3_SEL System interrupt select for CPU interrupt source 23. [31:24] read-write CM0_INT_CTL6 CM0+ interrupt control 6 0x38 32 read-write 0xF0F0F0F0 0xFFFFFFFF MUX0_SEL System interrupt select for CPU interrupt source 24. [7:0] read-write MUX1_SEL System interrupt select for CPU interrupt source 25. [15:8] read-write MUX2_SEL System interrupt select for CPU interrupt source 26. [23:16] read-write MUX3_SEL System interrupt select for CPU interrupt source 27. [31:24] read-write CM0_INT_CTL7 CM0+ interrupt control 7 0x3C 32 read-write 0xF0F0F0F0 0xFFFFFFFF MUX0_SEL System interrupt select for CPU interrupt source 28. [7:0] read-write MUX1_SEL System interrupt select for CPU interrupt source 29. [15:8] read-write MUX2_SEL System interrupt select for CPU interrupt source 30. [23:16] read-write MUX3_SEL System interrupt select for CPU interrupt source 31. [31:24] read-write CM4_PWR_CTL CM4 power control 0x80 32 read-write 0xFA050001 0xFFFF0003 PWR_MODE Set Power mode for CM4 [1:0] read-write OFF Switch CM4 off Power off, clock off, isolate, reset and no retain. 0 RESET Reset CM4 Clock off, no isolated, no retain and reset. Note: The CM4 CPU has a AIRCR.SYSRESETREQ register field that allows the CM4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot. 1 RETAINED Put CM4 in Retained mode This can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached. Power off, clock off, isolate, no reset and retain. 2 ENABLED Switch CM4 on. Power on, clock on, no isolate, no reset and no retain. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. [31:16] read-only CM4_PWR_DELAY_CTL CM4 power control 0x84 32 read-write 0x12C 0x3FF UP Number clock cycles delay needed after power domain power up [9:0] read-write CM4_STATUS CM4 status 0x88 32 read-only 0x13 0x13 SLEEPING Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. [0:0] read-only SLEEPDEEP Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. [1:1] read-only PWR_DONE After a PWR_MODE change this flag indicates if the new power mode has taken effect or not. Note: this flag can also change as a result of a change in debug power up req [4:4] read-only CM4_CLOCK_CTL CM4 clock control 0x90 32 read-write 0x0 0xFF00 FAST_INT_DIV Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1, 256] (FAST_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write CM4_NMI_CTL CM4 NMI control 0xA0 32 read-write 0xF0 0xFF MUX0_SEL System interrupt select for CPU NMI. The reset value ensure that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. [7:0] read-write RAM0_CTL0 RAM 0 control 0 0x100 32 read-write 0x1 0x303 SLOW_WS Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. [1:0] read-write FAST_WS Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. [9:8] read-write 16 4 RAM0_PWR_MACRO_CTL[%s] RAM 0 power control 0x140 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Set Power mode for 1 SRAM0 Macro [1:0] read-write OFF See CM4_PWR_CTL 0 RSVD undefined 1 RETAINED See CM4_PWR_CTL 2 ENABLED See CM4_PWR_CTL 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. [31:16] read-only RAM1_CTL0 RAM 1 control 0 0x180 32 read-write 0x1 0x303 SLOW_WS Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. [1:0] read-write FAST_WS Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. [9:8] read-write RAM1_PWR_CTL RAM1 power control 0x190 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Set Power mode for SRAM1 [1:0] read-write OFF See CM4_PWR_CTL 0 RSVD undefined 1 RETAINED See CM4_PWR_CTL 2 ENABLED See CM4_PWR_CTL 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. [31:16] read-only RAM2_CTL0 RAM 2 control 0 0x1A0 32 read-write 0x1 0x303 SLOW_WS Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. [1:0] read-write FAST_WS Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. [9:8] read-write RAM2_PWR_CTL RAM2 power control 0x1B0 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Set Power mode for SRAM2 [1:0] read-write OFF See CM4_PWR_CTL 0 RSVD undefined 1 RETAINED See CM4_PWR_CTL 2 ENABLED See CM4_PWR_CTL 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. [31:16] read-only RAM_PWR_DELAY_CTL Power up delay used for all SRAM power domains 0x1C0 32 read-write 0x96 0x3FF UP Number clock cycles delay needed after power domain power up [9:0] read-write ROM_CTL ROM control 0x1D0 32 read-write 0x1 0x303 SLOW_WS Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. Timing paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The 'clk_hf' clock domain frequency determines this field's value such that the timing paths minimum duration is met. A table/formula will be provided for this field's values for different 'clk_hf' frequencies. [1:0] read-write FAST_WS Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. [9:8] read-write UDB_PWR_CTL UDB power control 0x1F0 32 read-write 0xFA050001 0xFFFF0003 PWR_MODE Set Power mode for UDBs [1:0] read-write OFF See CM4_PWR_CTL 0 RESET See CM4_PWR_CTL 1 RETAINED See CM4_PWR_CTL 2 ENABLED See CM4_PWR_CTL 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. [31:16] read-only UDB_PWR_DELAY_CTL UDB power control 0x1F4 32 read-write 0x12C 0x3FF UP Number clock cycles delay needed after power domain power up [9:0] read-write DP_STATUS Debug port status 0x208 32 read-only 0x4 0x7 SWJ_CONNECTED Specifies if the SWJ debug port is connected; i.e. debug host interface is active: '0': Not connected/not active. '1': Connected/active. [0:0] read-only SWJ_DEBUG_EN Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on: '0': Disabled. '1': Enabled. [1:1] read-only SWJ_JTAG_SEL Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected). '0': SWD selected. '1': JTAG selected. [2:2] read-only BUFF_CTL Buffer control 0x220 32 read-write 0x1 0x1 WRITE_BUFF Specifies if write transfer can be buffered in the bus infrastructure bridges: '0': Write transfers are not buffered, independent of the transfer's bufferable attribute. '1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write. [0:0] read-write DDFT_CTL DDFT control 0x230 32 read-write 0x0 0x1F1F DDFT_OUT0_SEL Select signal for CPUSS DDFT[0] 0: clk_r of the Main flash (which is clk_hf for SONOS Flash) 1: Flash data output bit '0' (r_q[0]) 2: Flash data output bit '32' (r_q[32]) 3: Flash data output bit '64' (r_q[64]) 4: Flash data output bit '127' (r_q[127]) 5: bist_fm_enabled 6: bist_fail 7: cm0_sleeping 8: cm0_sleepdeep 9: cm0_sleep_hold_ack_n 10: cm4_sleeping 11: cm4_sleepdeep 12: cm4_sleep_hold_ack_n 13: cm4_power 14: cm4_act_retain_n 15: cm4_act_isolate_n 16: cm4_enabled 17: cm4_reset_n 18: cm4_pwr_done 19: mmio_ram0_ctl1_power[0] (Power control for SRAM0 macro0) 20: mmio_ram0_ctl1_retain_n[0] (Retention control for SRAM0 macro0) 21: mmio_ram0_ctl1_isolate_n[0] (Isolation control for SRAM0 macro0) [4:0] read-write DDFT_OUT1_SEL Select signal for CPUSS DDFT[0] 0: clk_r of the Main flash (which is clk_hf for SONOS Flash) 1: Flash data output bit '0' (r_q[0]) 2: Flash data output bit '32' (r_q[32]) 3: Flash data output bit '64' (r_q[64]) 4: Flash data output bit '127' (r_q[127]) 5: bist_fm_enabled 6: bist_fail 7: cm0_sleeping 8: cm0_sleepdeep 9: cm0_sleep_hold_ack_n 10: cm4_sleeping 11: cm4_sleepdeep 12: cm4_sleep_hold_ack_n 13: cm4_power 14: cm4_act_retain_n 15: cm4_act_isolate_n 16: cm4_enabled 17: cm4_reset_n 18: cm4_pwr_done 19: mmio_ram0_ctl1_power[0] (Power control for SRAM0 macro0) 20: mmio_ram0_ctl1_retain_n[0] (Retention control for SRAM0 macro0) 21: mmio_ram0_ctl1_isolate_n[0] (Isolation control for SRAM0 macro0) [12:8] read-write SYSTICK_CTL SysTick timer control 0x240 32 read-write 0x40000147 0xC3FFFFFF TENMS Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327. [23:0] read-write CLOCK_SOURCE Specifies an external clock source: '0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise). '1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock. o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected. '3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo'). Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used. Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source. [25:24] read-write SKEW Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock: '0': Precise. '1': Imprecise. [30:30] read-write NOREF Specifies if an external clock source is provided: '0': An external clock source is provided. '1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source. [31:31] read-write CM0_VECTOR_TABLE_BASE CM0+ vector table base 0x2B0 32 read-write 0x0 0xFFFFFF00 ADDR24 Address of CM0+ vector table. Note: the CM0+ vector table is at an address that is a 256 B multiple. [31:8] read-write CM4_VECTOR_TABLE_BASE CM4 vector table base 0x2C0 32 read-write 0x0 0xFFFFFC00 ADDR22 Address of CM4 vector table. Note: the CM4 vector table is at an address that is a 1024 B multiple. [31:10] read-write CM0_PC0_HANDLER CM0+ protection context 0 handler 0x320 32 read-write 0x0 0xFFFFFFFF ADDR Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt. [31:0] read-write IDENTITY Identity 0x400 32 read-only 0x0 0x0 P This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register. [0:0] read-only NS This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register. [1:1] read-only PC This field specifies the protection context of the transfer that reads the register. [7:4] read-only MS This field specifies the bus master identifier of the transfer that reads the register. [11:8] read-only PROTECTION Protection status 0x500 32 read-write 0x0 0x7 STATE Protection state: '0': UNKNOWN. '1': VIRGIN. '2': NORMAL. '3': SECURE. '4': DEAD. The following state transistions are allowed (and enforced by HW): - UNKNOWN => VIRGIN/NORMAL/SECURE/DEAD - NORMAL => DEAD - SECURE => DEAD An attempt to make a NOT allowed state transition will NOT affect this register field. [2:0] read-write CM0_NMI_CTL CM0+ NMI control 0x520 32 read-write 0xF0 0xFF MUX0_SEL System interrupt select for CPU NMI. The reset value ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. [7:0] read-write MBIST_STAT Memory BIST status 0x5A0 32 read-only 0x0 0x3 SFP_READY Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0. [0:0] read-only SFP_FAIL Report status of the BIST run, only valid if SFP_READY=1 [1:1] read-only TRIM_ROM_CTL ROM trim control 0xF000 32 read-write 0x2 0x1F RM N/A [3:0] read-write RME Read-Write margin enable control. This selects between the default Read-Write margin setting, and the external pin Read-Write margin settting. [4:4] read-write TRIM_RAM_CTL RAM trim control 0xF004 32 read-write 0x6002 0x73FF RM N/A [3:0] read-write RME Read-Write margin enable control. This selects between the default Read-Write margin setting, and the external RM[3:0] Read-Write margin settting. [4:4] read-write WPULSE Write Assist Pulse to control pulse width of negative voltage on SRAM bitline. [7:5] read-write RA Read Assist control for WL under-drive. [9:8] read-write WA Write assist enable control (Active High). - WA[1:0] Write Assist pins to control negative voltage on SRAM bitline. [14:12] read-write FAULT Fault structures 0x40220000 0 65536 registers 2 256 STRUCT[%s] Fault structure 0x00000000 CTL Fault control 0x0 32 read-write 0x0 0x7 TR_EN Trigger output enable: '0': Disabled. The trigger output 'tr_fault' is '0'. '1': Enabled. The trigger output 'tr_fault' reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3). [0:0] read-write OUT_EN IO output signal enable: '0': Disabled. The IO output signal 'fault_out' is '0'. The IO output enable signal 'fault_out_en' is '0'. '1': Enabled. The IO output signal 'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'. [1:1] read-write RESET_REQ_EN Reset request enable: '0': Disabled. '1': Enabled. The output reset request signal 'fault_reset_req' reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis). The 'fault_reset_req' signals of the individual fault report structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal. [2:2] read-write STATUS Fault status 0xC 32 read-write 0x0 0x80000000 IDX The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below. Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'. [6:0] read-only MPU_0 Bus master 0 MPU/SMPU. DATA0[31:0]: Violating address. DATA1[0]: User read. DATA1[1]: User write. DATA1[2]: User execute. DATA1[3]: Privileged read. DATA1[4]: Privileged write. DATA1[5]: Privileged execute. DATA1[6]: Non-secure. DATA1[11:8]: Master identifier. DATA1[15:12]: Protection context identifier. DATA1[31]: '0' MPU violation; '1': SMPU violation. 0 MPU_1 Bus master 1 MPU. See MPU_0 description. 1 MPU_2 Bus master 2 MPU. See MPU_0 description. 2 MPU_3 Bus master 3 MPU. See MPU_0 description. 3 MPU_4 Bus master 4 MPU. See MPU_0 description. 4 MPU_5 Bus master 5 MPU. See MPU_0 description. 5 MPU_6 Bus master 6 MPU. See MPU_0 description. 6 MPU_7 Bus master 7 MPU. See MPU_0 description. 7 MPU_8 Bus master 8 MPU. See MPU_0 description. 8 MPU_9 Bus master 9 MPU. See MPU_0 description. 9 MPU_10 Bus master 10 MPU. See MPU_0 description. 10 MPU_11 Bus master 11 MPU. See MPU_0 description. 11 MPU_12 Bus master 12 MPU. See MPU_0 description. 12 MPU_13 Bus master 13 MPU. See MPU_0 description. 13 MPU_14 Bus master 14 MPU. See MPU_0 description. 14 MPU_15 Bus master 15 MPU. See MPU_0 description. 15 CM4_SYS_MPU CM4 system bus AHB-Lite interface MPU. See MPU_0 description. 16 MS_PPU_0 Peripheral master interface 0 PPU. DATA0[31:0]: Violating address. DATA1[0]: User read. DATA1[1]: User write. DATA1[2]: User execute. DATA1[3]: Privileged read. DATA1[4]: Privileged write. DATA1[5]: Privileged execute. DATA1[6]: Non-secure. DATA1[11:8]: Master identifier. DATA1[15:12]: Protection context identifier. DATA1[31]: '0': PPU violation, '1': peripheral bus error. 28 MS_PPU_1 Peripheral master interface 0 PPU. See MS_PPU_0 description. 29 MS_PPU_2 Peripheral master interface 1 PPU. See MS_PPU_0 description. 30 MS_PPU_3 Peripheral master interface 2 PPU. See MS_PPU_0 description. 31 GROUP_PPU_0 Peripheral group 0 PPU. DATA0[31:0]: Violating address. DATA1[0]: User read. DATA1[1]: User write. DATA1[2]: User execute. DATA1[3]: Privileged read. DATA1[4]: Privileged write. DATA1[5]: Privileged execute. DATA1[6]: Non-secure. DATA1[11:8]: Master identifier. DATA1[15:12]: Protection context identifier. DATA1[31:30]: '0': PPU violation, '1': timeout detected, '2': peripheral bus error. 32 GROUP_PPU_1 Peripheral group 1 PPU. See GROUP_PPU_0 description. 33 GROUP_PPU_2 Peripheral group 2 PPU. See GROUP_PPU_0 description. 34 GROUP_PPU_3 Peripheral group 3 PPU. See GROUP_PPU_0 description. 35 GROUP_PPU_4 Peripheral group 4 PPU. See GROUP_PPU_0 description. 36 GROUP_PPU_5 Peripheral group 5 PPU. See GROUP_PPU_0 description. 37 GROUP_PPU_6 Peripheral group 6 PPU. See GROUP_PPU_0 description. 38 GROUP_PPU_7 Peripheral group 7 PPU. See GROUP_PPU_0 description. 39 GROUP_PPU_8 Peripheral group 8 PPU. See GROUP_PPU_0 description. 40 GROUP_PPU_9 Peripheral group 9 PPU. See GROUP_PPU_0 description. 41 GROUP_PPU_10 Peripheral group 10 PPU. See GROUP_PPU_0 description. 42 GROUP_PPU_11 Peripheral group 11 PPU. See GROUP_PPU_0 description. 43 GROUP_PPU_12 Peripheral group 12 PPU. See GROUP_PPU_0 description. 44 GROUP_PPU_13 Peripheral group 13 PPU. See GROUP_PPU_0 description. 45 GROUP_PPU_14 Peripheral group 14 PPU. See GROUP_PPU_0 description. 46 GROUP_PPU_15 Peripheral group 15 PPU. See GROUP_PPU_0 description. 47 FLASHC_MAIN_BUS_ERROR Flash controller, main interface, bus error: FAULT_DATA0[31:0]: Violating address. FAULT_DATA1[31]: '0': FLASH macro interface bus error; '1': memory hole. FAULT_DATA1[15:12]: Protection context identifier. FAULT_DATA1[11:8]: Master identifier. 50 VALID Valid indication: '0': Invalid. '1': Valid. HW sets this field to '1' when new fault source data is captured. New fault source data is ONLY captured when VALID is '0'. SW can clear this field to '0' when the fault is handled (by SW). [31:31] read-write 4 4 DATA[%s] Fault data 0x10 32 read-only 0x0 0x0 DATA Captured fault source data. Note: the fault source index STATUS.IDX specifies the format of the DATA registers. [31:0] read-only PENDING0 Fault pending 0 0x40 32 read-only 0x0 0x0 SOURCE This field specifies the following sources: Bit 0: CM0 MPU. Bit 1: CRYPTO MPU. Bit 2: DW 0 MPU. Bit 3: DW 1 MPU. ... Bit 14: CM4 code bus MPU. Bit 15: DAP MPU. Bit 16: CM4 s+G92ystem bus MPU. Bit 28: Peripheral master interface 0 PPU. Bit 29: Peripheral master interface 1 PPU. Bit 30: Peripheral master interface 2 PPU. Bit 31: Peripheral master interface 3 PPU. [31:0] read-only PENDING1 Fault pending 1 0x44 32 read-only 0x0 0x0 SOURCE This field specifies the following sources: Bit 0: Peripheral group 0 PPU. Bit 1: Peripheral group 1 PPU. Bit 2: Peripheral group 2 PPU. Bit 3: Peripheral group 3 PPU. Bit 4: Peripheral group 4 PPU. Bit 5: Peripheral group 5 PPU. Bit 6: Peripheral group 6 PPU. Bit 7: Peripheral group 7 PPU. ... Bit 15: Peripheral group 15 PPU. Bit 18: Flash controller, main interface, bus error. [31:0] read-only PENDING2 Fault pending 2 0x48 32 read-only 0x0 0x0 SOURCE This field specifies the following sources: Bit 0 - 31: TBD. [31:0] read-only MASK0 Fault mask 0 0x50 32 read-write 0x0 0xFFFFFFFF SOURCE Fault source enables: Bits 31-0: Fault sources 31 to 0. [31:0] read-write MASK1 Fault mask 1 0x54 32 read-write 0x0 0xFFFFFFFF SOURCE Fault source enables: Bits 31-0: Fault sources 63 to 32. [31:0] read-write MASK2 Fault mask 2 0x58 32 read-write 0x0 0xFFFFFFFF SOURCE Fault source enables: Bits 31-0: Fault sources 95 to 64. [31:0] read-write INTR Interrupt 0xC0 32 read-write 0x0 0x1 FAULT This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured: - STATUS.VALID is set to '1'. - STATUS.IDX specifies the fault source index. - DATA0 through DATA3 captures the fault source dara. SW writes a '1' to these field to clear the interrupt cause to '0'. [0:0] read-write INTR_SET Interrupt set 0xC4 32 read-write 0x0 0x1 FAULT SW writes a '1' to this field to set the corresponding field in the INTR register. [0:0] read-write INTR_MASK Interrupt mask 0xC8 32 read-write 0x0 0x1 FAULT Mask bit for corresponding field in the INTR register. [0:0] read-write INTR_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x1 FAULT Logical and of corresponding INTR and INTR_MASK fields. [0:0] read-only IPC IPC 0x40230000 0 65536 registers 16 32 STRUCT[%s] IPC structure 0x00000000 ACQUIRE IPC acquire 0x0 32 read-only 0x0 0x80000000 P User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock. [0:0] read-only NS Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock. [1:1] read-only PC This field specifies the protection context that successfully acquired the lock. [7:4] read-only MS This field specifies the bus master identifier that successfully acquired the lock. [11:8] read-only SUCCESS Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value). [31:31] read-only RELEASE IPC release 0x4 32 write-only 0x0 0xFFFF INTR_RELEASE This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field. [15:0] write-only NOTIFY IPC notification 0x8 32 write-only 0x0 0xFFFF INTR_NOTIFY This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field. [15:0] write-only DATA IPC data 0xC 32 read-write 0x0 0x0 DATA This field holds a 32-bit data element that is associated with the IPC structure. [31:0] read-write LOCK_STATUS IPC lock status 0x10 32 read-only 0x0 0x80000000 P This field specifies the user/privileged access control: '0': user mode. '1': privileged mode. [0:0] read-only NS This field specifies the cecure/on-secure access control: '0': secure. '1': non-secure. [1:1] read-only PC This field specifies the protection context that successfully acquired the lock. [7:4] read-only MS This field specifies the bus master identifier that successfully acquired the lock. [11:8] read-only ACQUIRED Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). [31:31] read-only 16 32 INTR_STRUCT[%s] IPC interrupt structure 0x00001000 INTR Interrupt 0x0 32 read-write 0x0 0xFFFFFFFF RELEASE These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. [15:0] read-write NOTIFY These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. [31:16] read-write INTR_SET Interrupt set 0x4 32 read-write 0x0 0xFFFFFFFF RELEASE SW writes a '1' to this field to set the corresponding field in the INTR register. [15:0] read-write NOTIFY SW writes a '1' to this field to set the corresponding field in the INTR register. [31:16] read-write INTR_MASK Interrupt mask 0x8 32 read-write 0x0 0xFFFFFFFF RELEASE Mask bit for corresponding field in the INTR register. [15:0] read-write NOTIFY Mask bit for corresponding field in the INTR register. [31:16] read-write INTR_MASKED Interrupt masked 0xC 32 read-only 0x0 0xFFFFFFFF RELEASE Logical and of corresponding request and mask bits. [15:0] read-only NOTIFY Logical and of corresponding INTR and INTR_MASK fields. [31:16] read-only PROT Protection 0x40240000 0 65536 registers SMPU SMPU 0x00000000 MS0_CTL Master 0 protection context control 0x0 32 read-write 0x303 0xFFFF0303 P Privileged setting ('0': user mode; '1': privileged mode). Notes: This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute. The default/reset field value provides privileged mode access capabilities. [0:0] read-write NS Security setting ('0': secure mode; '1': non-secure mode). Notes: This field is ONLY used for masters that do NOT provide their own secure/non-escure access control attribute. Note that the default/reset field value provides non-secure mode access capabilities to all masters. [1:1] read-write PRIO Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority). Notes: The AHB-Lite interconnect performs arbitration on the individual beats/transfers of a burst (this optimizes latency over locality/bandwidth). The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency). Masters with the same priority setting form a 'priority group'. Within a 'priority group', roundrobin arbitration is performed. [9:8] read-write PC_MASK_0 Protection context mask for protection context '0'. This field is a constant '0': - PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to '0' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. [16:16] read-only PC_MASK_15_TO_1 Protection context mask for protection contexts '15' downto '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1': - PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to 'i+1'; and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. - PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to 'i+1'. Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]). [31:17] read-write MS1_CTL Master 1 protection context control 0x4 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS2_CTL Master 2 protection context control 0x8 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS3_CTL Master 3 protection context control 0xC 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS4_CTL Master 4 protection context control 0x10 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS5_CTL Master 5 protection context control 0x14 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS6_CTL Master 6 protection context control 0x18 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS7_CTL Master 7 protection context control 0x1C 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS8_CTL Master 8 protection context control 0x20 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS9_CTL Master 9 protection context control 0x24 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS10_CTL Master 10 protection context control 0x28 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS11_CTL Master 11 protection context control 0x2C 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS12_CTL Master 12 protection context control 0x30 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS13_CTL Master 13 protection context control 0x34 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS14_CTL Master 14 protection context control 0x38 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS15_CTL Master 15 protection context control 0x3C 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write 16 64 SMPU_STRUCT[%s] SMPU structure 0x00002000 ADDR0 SMPU region address 0 (slave structure) 0x0 32 read-write 0x0 0x0 SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. [7:0] read-write ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. [31:8] read-write ATT0 SMPU region attributes 0 (slave structure) 0x4 32 read-write 0x100 0x80000100 UR User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed). [0:0] read-write UW User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed). [1:1] read-write UX User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed). [2:2] read-write PR Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed). [3:3] read-write PW Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed). [4:4] read-write PX Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed). [5:5] read-write NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [6:6] read-write PC_MASK_0 This field specifies protection context identifier based access control for protection context '0'. [8:8] read-only PC_MASK_15_TO_1 This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. [23:9] read-write REGION_SIZE This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-write PC_MATCH This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. [30:30] read-write ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption. [31:31] read-write ADDR1 SMPU region address 1 (master structure) 0x20 32 read-only 0x0 0xFFFFFFFF SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. [7:0] read-only ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. 'ADDR_DEF1': base address of structure. Note: this field is read-only. [31:8] read-only ATT1 SMPU region attributes 1 (master structure) 0x24 32 read-write 0x7000109 0x9F00012D UR User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed). Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. [0:0] read-only UW User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed). [1:1] read-write UX User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed). Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. [2:2] read-only PR Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed). Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. [3:3] read-only PW Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed). [4:4] read-write PX Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed). Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. [5:5] read-only NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [6:6] read-write PC_MASK_0 This field specifies protection context identifier based access control for protection context '0'. [8:8] read-only PC_MASK_15_TO_1 This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. [23:9] read-write REGION_SIZE This field specifies the region size: '7': 256 B region (8 32 B subregions) Note: this field is read-only. [28:24] read-only PC_MATCH This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. [30:30] read-write ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. [31:31] read-write 16 1024 MPU[%s] MPU 0x00004000 MS_CTL Master control 0x0 32 read-write 0x0 0xF000F PC N/A [3:0] read-write PC_SAVED Saved protection context. Modifications to this field are constrained by the associated MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. [19:16] read-write 8 32 MPU_STRUCT[%s] MPU structure 0x00000200 ADDR MPU region address 0x0 32 read-write 0x0 0x0 SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. [7:0] read-write ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. [31:8] read-write ATT MPU region attrributes 0x4 32 read-write 0x0 0x80000000 UR User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed). [0:0] read-write UW User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed). [1:1] read-write UX User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed). [2:2] read-write PR Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed). [3:3] read-write PW Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed). [4:4] read-write PX Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed). [5:5] read-write NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [6:6] read-write REGION_SIZE This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-write ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption. [31:31] read-write FLASHC Flash controller 0x40250000 0 65536 registers FLASH_CTL Control 0x0 32 read-write 0x0 0x10F MAIN_WS FLASH macro main interface wait states: '0': 0 wait states. ... '15': 15 wait states [3:0] read-write REMAP Specifies remapping of FLASH macro main region. '0': No remapping. '1': Remapping. The highest address bit of the FLASH main region is inverted. This effectively remaps the location of FLASH main region physical sectors in the logical address space. In other words, the higher half physical sectors are swapped with the lower half physical sectors. Note: remapping only affects reading of the FLASH main region (over the R interface). It does NOT affect programming/erasing of the FLASH memory region (over the C interface). E.g., for a 512 KB / 4 Mb main region, the logical address space ranges from [0x1000:0000, 0x1007:ffff] (the highest bit if the FLASH main region is bit 18). The memory has four physical sectors: sectors 0, 1, 2 and 3. If REMAP is '0', the physical regions logical addresses are as follows: - The physical region 0: [0x1000:0000, 0x1001:ffff]. - The physical region 1: [0x1002:0000, 0x1003:ffff]. - The physical region 2: [0x1004:0000, 0x1005:ffff]. - The physical region 3: [0x1006:0000, 0x1007:ffff]. If REMAP is '1', the physical regions logical addresses are as follows: - The physical region 0: [0x1004:0000, 0x1005:ffff]. - The physical region 1: [0x1006:0000, 0x1007:ffff]. - The physical region 2: [0x1000:0000, 0x1001:ffff]. - The physical region 3: [0x1002:0000, 0x1003:ffff]. Note: when the REMAP is changed, SW should invalidate the caches and buffers. [8:8] read-write FLASH_PWR_CTL Flash power control 0x4 32 read-write 0x3 0x3 ENABLE Controls 'enable' pin of the Flash memory. [0:0] read-write ENABLE_HV Controls 'enable_hv' pin of the Flash memory. [1:1] read-write FLASH_CMD Command 0x8 32 read-write 0x0 0x1 INV FLASH cache and buffer invalidation for ALL cache and buffers. SW writes a '1' to clear the cache and buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches' LRU structures are also reset to their default state. [0:0] read-write BIST_CTL BIST control 0x100 32 read-write 0x0 0xFF OPCODE This field specifies how the data check should be performed after reading the data from Flash memory. '0': Read the Flash and compare the output to BIST_DATA (R0). '1': Read the Flash and compare the output to the binary complement of BIST_DATA (R1). '2': Read the Flash and compare with BIST_DATA[] and compliment of BIST_DATA alternately (R01). The expected data of the first read is BIST_DATA, expected data of the second read is binary compliment of BIST_DATA, third read expected data is BIST_DATA, fourth read expected data is binary compliment of BIST_DATA and so on. [1:0] read-write UP Specifies direction in which Flash BIST steps through addresses: ''0': BIST steps through the Flash from the maximum row and column addresses (as specified by a design time configurtion parameter when ADDR_START_ENABLED is '0' and as specified by BIST_ADDR_START when ADDR_START_ENABLED is '1') to the minimum row and column addresses. '1': BIST steps through the Flash from the minimum row and column addresses ('0' when ADDR_START_ENABLED is '0' and as specified by BIST_ADDR_START when ADDR_START_ENABLED is '1') to the maximum row and column addresses. [2:2] read-write ROW_FIRST Specifies how the Flash BIST addresses are generated: '0': Column address is incremented/decremented till it reaches its maximum/minimum value. Once it reach its maximum/minimum value, it is set to its mimimum/maximum value and only then is the row address incremented/decremented. '1': Row address is incremented/decremented till it reaches its maximum/minimum value. Once it reach its maximum/minimum value, it is set to its mimimum/maximum value and only then is the column address incremented/decremented. [3:3] read-write ADDR_START_ENABLED Specifies Flash BIST start addresses: '0': Row and column addresses start with their maximum/minimum values. '1': Row and column addresses start with their values as specified by BIST_ADDR_START. This feature is supported only for simple increment/decrement patterns. It is not supported with address compliment pattern (BIST_CTL.ADDR_COMPLIMENT_ENABLED) or address pattern which increments/decrements both row address and column address (BIST_CTL.INCR_DECR_BOTH) for every read. [4:4] read-write ADDR_COMPLIMENT_ENABLED Specifies to generate address compliment patterns. '0': Generate normal increment/decrement patterns. '1': Generate address patterns which interleaves compliment of previous address in between. Example: The following is an exaple pattern, With UP=1 and ROW_FIRST =0 00_00 11_11 00_01 11_10 00_10 11_01 ... [5:5] read-write INCR_DECR_BOTH Specifies to generate patterns where both column address and row address are incremented/decremented simultaneously. '0': Generate normal increment/decrement patterns. '1': Generate address patterns with both row and column address changing. Example: With UP = 1 and ROW_FIRST = 0 00_00 01_01 10_10 11_11 00_01 01_10 10_11 11_00 00_10 ... [6:6] read-write STOP_ON_ERROR Specifies the BIST to continue indefinitely, regardless of occurrence of errors or not. '0': BIST controller doesn't stop on the data failures, it continues regardless of the errors. '1': BIST controller stops on when the first data failure is encounted. [7:7] read-write BIST_CMD BIST command 0x104 32 read-write 0x0 0x1 START 1': Start FLASH BIST. Hardware set this field to '0' when BIST is completed. [0:0] read-write BIST_ADDR_START BIST address start register 0x108 32 read-write 0x0 0xFFFFFFFF COL_ADDR_START Column start address. Useful to apply BIST to a part of an Flash. The value of this field should be in a legal range (a value outside of the legal range has an undefined result, and may lock up the BIST state machine). This legal range is dependent on the number of columns of the SRAM the BIST is applied to (as specified by BIST_CTL.SRAMS_ENABLED). E.g. for a Flash with n columns, the legal range is [0, n-1]. [15:0] read-write ROW_ADDR_START Row start address. Useful to apply BIST to a part of an Flash. The value of this field should be in a legal range (a value outside of the legal range has an undefined result, and may lock up the BIST state machine). This legal range is dependent on the number of rows of the SRAM the BIST is applied to (as specified by BIST_CTL.SRAMS_ENABLED). E.g. for a Flash with m columns, the legal range is [0, m-1]. [31:16] read-write 8 4 BIST_DATA[%s] BIST data register(s) 0x10C 32 read-write 0x0 0xFFFFFFFF DATA BIST data register to store the expected value for data comparison. For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value. [31:0] read-write 8 4 BIST_DATA_ACT[%s] BIST data actual register(s) 0x12C 32 read-only 0x0 0x0 DATA This field specified the actual Flash data output that caused the BIST failure. [31:0] read-only 8 4 BIST_DATA_EXP[%s] BIST data expected register(s) 0x14C 32 read-only 0x0 0x0 DATA This field specified the expected Flash data output. [31:0] read-only BIST_ADDR BIST address register 0x16C 32 read-only 0x0 0x0 COL_ADDR Current column address. [15:0] read-only ROW_ADDR Current row address. [31:16] read-only BIST_STATUS BIST status register 0x170 32 read-write 0x0 0x1 FAIL 0': BIST passed. '1': BIST failed. [0:0] read-write CM0_CA_CTL0 CM0+ cache control 0x400 32 read-write 0xC0000000 0xC7030000 WAY Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2. [17:16] read-write SET_ADDR Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2. [26:24] read-write PREF_EN Prefetch enable: '0': Disabled. '1': Enabled. Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. [30:30] read-write ENABLED Cache enable: '0': Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way). '1': Enabled. [31:31] read-write CM0_CA_CTL1 CM0+ cache control 0x404 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Set Power mode for CM0 cache [1:0] read-write OFF See CM4_PWR_CTL 0 RSVD undefined 1 RETAINED See CM4_PWR_CTL 2 ENABLED See CM4_PWR_CTL 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. [31:16] read-only CM0_CA_CTL2 CM0+ cache control 0x408 32 read-write 0x12C 0x3FF PWRUP_DELAY Number clock cycles delay needed after power domain power up [9:0] read-write CM0_CA_CMD CM0+ cache command 0x40C 32 read-write 0x0 0x1 INV FLASH cache invalidation. SW writes a '1' to clear the cache. W sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The cache's LRU structure is also reset to its default state. [0:0] read-write CM0_CA_STATUS0 CM0+ cache status 0 0x440 32 read-only 0x0 0xFFFF VALID16 Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. [15:0] read-only CM0_CA_STATUS1 CM0+ cache status 1 0x444 32 read-only 0x0 0x0 TAG Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. [31:0] read-only CM0_CA_STATUS2 CM0+ cache status 2 0x448 32 read-only 0x0 0x0 LRU Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y): Bit 5: 0_LRU_1: way 0 less recently used than way 1. Bit 4: 0_LRU_2. Bit 3: 0_LRU_3. Bit 2: 1_LRU_2. Bit 1: 1_LRU_3. Bit 0: 2_LRU_3. [5:0] read-only CM4_CA_CTL0 CM4 cache control 0x480 32 read-write 0xC0000000 0xC7030000 WAY See CM0_CA_CTL. [17:16] read-write SET_ADDR See CM0_CA_CTL. [26:24] read-write PREF_EN See CM0_CA_CTL. [30:30] read-write ENABLED See CM0_CA_CTL. [31:31] read-write CM4_CA_CTL1 CM4 cache control 0x484 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Set Power mode for CM4 cache [1:0] read-write OFF See CM4_PWR_CTL 0 RSVD undefined 1 RETAINED See CM4_PWR_CTL 2 ENABLED See CM4_PWR_CTL 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. [31:16] read-only CM4_CA_CTL2 CM4 cache control 0x488 32 read-write 0x12C 0x3FF PWRUP_DELAY Number clock cycles delay needed after power domain power up [9:0] read-write CM4_CA_CMD CM4 cache command 0x48C 32 read-write 0x0 0x1 INV See CM0_CA_CMD. [0:0] read-write CM4_CA_STATUS0 CM4 cache status 0 0x4C0 32 read-only 0x0 0xFFFF VALID16 See CM0_CA_STATUS0. [15:0] read-only CM4_CA_STATUS1 CM4 cache status 1 0x4C4 32 read-only 0x0 0x0 TAG See CM0_CA_STATUS1. [31:0] read-only CM4_CA_STATUS2 CM4 cache status 2 0x4C8 32 read-only 0x0 0x0 LRU See CM0_CA_STATUS2. [5:0] read-only CRYPTO_BUFF_CTL Cryptography buffer control 0x500 32 read-write 0xC0000000 0xC0000000 PREF_EN Prefetch enable: '0': Disabled. '1': Enabled. Prefetching requires the buffer to be enabled; i.e. ENABLED is '1'. [30:30] read-write ENABLED Cache enable: '0': Disabled. '1': Enabled. [31:31] read-write CRYPTO_BUFF_CMD Cryptography buffer command 0x508 32 read-write 0x0 0x1 INV FLASH buffer invalidation. SW writes a '1' to clear the buffer. HW sets this field to '0' when the operation is completed. [0:0] read-write DW0_BUFF_CTL Datawire 0 buffer control 0x580 32 read-write 0xC0000000 0xC0000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write ENABLED See CRYPTO_BUFF_CTL. [31:31] read-write DW0_BUFF_CMD Datawire 0 buffer command 0x588 32 read-write 0x0 0x1 INV See CRYPTO_BUFF_CMD. [0:0] read-write DW1_BUFF_CTL Datawire 1 buffer control 0x600 32 read-write 0xC0000000 0xC0000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write ENABLED See CRYPTO_BUFF_CTL. [31:31] read-write DW1_BUFF_CMD Datawire 1 buffer command 0x608 32 read-write 0x0 0x1 INV See CRYPTO_BUFF_CMD. [0:0] read-write DAP_BUFF_CTL Debug access port buffer control 0x680 32 read-write 0xC0000000 0xC0000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write ENABLED See CRYPTO_BUFF_CTL. [31:31] read-write DAP_BUFF_CMD Debug access port buffer command 0x688 32 read-write 0x0 0x1 INV See CRYPTO_BUFF_CMD. [0:0] read-write EXT_MS0_BUFF_CTL External master 0 buffer control 0x700 32 read-write 0xC0000000 0xC0000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write ENABLED See CRYPTO_BUFF_CTL. [31:31] read-write EXT_MS0_BUFF_CMD External master 0 buffer command 0x708 32 read-write 0x0 0x1 INV See CRYPTO_BUFF_CMD. [0:0] read-write EXT_MS1_BUFF_CTL External master 1 buffer control 0x780 32 read-write 0xC0000000 0xC0000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write ENABLED See CRYPTO_BUFF_CTL. [31:31] read-write EXT_MS1_BUFF_CMD External master 1 buffer command 0x788 32 read-write 0x0 0x1 INV See CRYPTO_BUFF_CMD. [0:0] read-write FM_CTL Flash Macro Registers 0x0000F000 FM_CTL Flash macro control 0x0 32 read-write 0x0 0x37F030F FM_MODE Flash macro mode selection: '0': Normal functional mode. '1': Sets 'pre-program control bit' for soft pre-program operation of all selected SONOS cells. the control bit is cleared by the HW after any program operation. '2': Sets ... '15': TBD [3:0] read-write FM_SEQ Flash macro sequence select: '0': TBD '1': TBD '2': TBD '3': TBD [9:8] read-write DAA_MUX_SEL Direct memory cell access address. [22:16] read-write IF_SEL Interface selection. Specifies the interface that is used for flash memory read operations: '0': R interface is used (default value). In this case, the flash memory address is provided as part of the R signal interface. '1': C interface is used. In this case, the flash memory address is provided by FM_MEM_ADDR (the page address) and by the C interface access offset in the FM_MEM_DATA structure. [24:24] read-write WR_EN '0': normal mode '1': Fm Write Enable [25:25] read-write STATUS Status 0x4 32 read-only 0x0 0x3F HV_TIMER_RUNNING Indicates if the high voltage timer is running: '0': not running '1': running [0:0] read-only HV_REGS_ISOLATED Indicates the isolation status at HV trim and redundancy registers inputs '0' - Not isolated, writing permitted '1' - isolated writing disabled [1:1] read-only ILLEGAL_HVOP Indicates a bulk,sector erase, program has been requested when axa=1 '0' - no error '1' - illegal HV operation error [2:2] read-only TURBO_N After FM power up indicates the analog blocks currents are boosted to faster reach their functional state.. Used in the testchip boot only as an 'FM READY' flag. '0' - turbo mode '1' - normal mode [3:3] read-only WR_EN_MON FM_CTL.WR_EN bit after being synchronized in clk_r domain [4:4] read-only IF_SEL_MON FM_CTL.IF_SEL bit after being synchronized in clk_r domain [5:5] read-only FM_ADDR Flash macro address 0x8 32 read-write 0x0 0x1FFFFFF RA Row address. [15:0] read-write BA Bank address. [23:16] read-write AXA Auxiliairy address field: '0': regular flash memory. '1': supervisory flash memory. [24:24] read-write GEOMETRY Regular flash geometry 0xC 32 read-only 0x0 0xFFFFFFFF WORD_SIZE_LOG2 Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access: '0': 1 Byte '1': 2 Bytes '2': 4 Bytes ... '7': 128 Bytes The currently planned flash macros have a word size of either 32-bit, 64-bit or 128-bit, resulting in WORD_SIZE_LOG2 settings of 2, 3 and 4 respectively. [3:0] read-only PAGE_SIZE_LOG2 Number of Bytes per page (log 2): '0': 1 Byte '1': 2 Bytes '2': 4 Bytes ... '15': 32768 Bytes The currently planned flash macros have a page size of either 256 Byte or 512 Byte, resulting in PAGE_SIZE_LOG2 settings of 8 and 9 respectively. [7:4] read-only ROW_COUNT Number of rows (minus 1): '0': 1 row '1': 2 rows '2': 3 rows ... '65535': 65536 rows [23:8] read-only BANK_COUNT Number of banks (minus 1): '0': 1 bank '1': 2 banks ... '255': 256 banks [31:24] read-only GEOMETRY_SUPERVISORY Supervisory flash geometry 0x10 32 read-only 0x0 0xFFFFFFFF WORD_SIZE_LOG2 Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically, WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2. [3:0] read-only PAGE_SIZE_LOG2 Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically, PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2. [7:4] read-only ROW_COUNT Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT [23:8] read-only BANK_COUNT Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT. [31:24] read-only TIMER_CTL Timer control 0x14 32 read-write 0x4000000 0xE701FFFF PERIOD Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples. [15:0] read-write SCALE Timer tick scale: '0': 1 microsecond. '1': 100 microseconds. [16:16] read-write PUMP_CLOCK_SEL Pump clock select: '0': internal clock. '1': external clock. [24:24] read-write PRE_PROG '1' during pre-program operation [25:25] read-write PRE_PROG_CSL '0' CSL lines driven by CSL_DAC '1' CSL lines driven by VNEG_G [26:26] read-write PUMP_EN Pump enable: '0': disabled '1': enabled (also requires FM_CTL.IF_SEL to be '1', this additional restriction is reuired to prevent non intential clearing of the FM). SW sets this field to '1' to generate a single PE pulse. HW clears this field when timer is expired. [29:29] read-write ACLK_EN ACLK enable (generates a single cycle pulse for the FM): '0': disabled '1': enabled. SW set this field to '1' to generate a single cycle pulse. HW sets this field to '0' when the pulse is generated. [30:30] read-write TIMER_EN Timer enable: '0': disabled '1': enabled. SW sets this field to '1' to start the timer. HW sets this field to '0' when the timer is expired. [31:31] read-write ANA_CTL0 Analog control 0 0x18 32 read-write 0x400 0x9000700 CSLDAC Trimming of common source line DAC. [10:8] read-write VCC_SEL Vcc select: '0': 1.2 V : LP reset value '1': 0.95 V: ULP reset value Note: the flash macro compiler has a configuration option that specifies the default/reset value of this field. [24:24] read-write FLIP_AMUXBUS_AB Flips amuxbusa and amuxbusb '0': amuxbusa, amuxbusb '1': amuxbusb, amuxbusb [27:27] read-write ANA_CTL1 Analog control 1 0x1C 32 read-write 0x6060000 0x7F0F00FF MDAC Trimming of the output margin Voltage as a function of Vpos and Vneg. [7:0] read-write PDAC Trimming of positive pump output Voltage: [19:16] read-write NDAC Trimming of negative pump output Voltage: [27:24] read-write VPROT_OVERRIDE '0': vprot = BG.vprot. '1': vprot = vcc [28:28] read-write R_GRANT_CTL r_grant control: '0': r_grant normal functionality '1': forces r_grant LO synchronized on clk_r [29:29] read-write RST_SFT_HVPL '1': Page Latches Soft Reset [30:30] read-write GEOMETRY_GEN N/A, DNU 0x20 32 read-only 0x0 0xE DNU_0X20_1 N/A [1:1] read-only DNU_0X20_2 N/A [2:2] read-only DNU_0X20_3 N/A [3:3] read-only TEST_CTL Test mode control 0x24 32 read-write 0x0 0x80070F1F TEST_MODE Test mode control: '0'-'31': TBD [4:0] read-write PN_CTL Postive/negative margin mode control: '0': negative margin control '1': positive margin control [8:8] read-write TM_PE PUMP_EN override: Pump Enable =PUMP_EN | PE_TM [9:9] read-write TM_DISPOS Test mode positive pump disable [10:10] read-write TM_DISNEG Test mode negative pump disable [11:11] read-write EN_CLK_MON 1: enables the oscillator output monitor [16:16] read-write CSL_DEBUG Engineering Debug Register [17:17] read-write ENABLE_OSC 0': the oscillator enable logic has control over the internal oscillator '1': forces oscillator enable HI [18:18] read-write UNSCRAMBLE_WA See BSN-242 memo '0': normal '1': disables the Word Address scrambling [31:31] read-write WAIT_CTL Wiat State control 0x28 32 read-write 0x30B09 0x70F0F WAIT_FM_MEM_RD Number of C interface wait cycles (on 'clk_c') for a read from the memory [3:0] read-write WAIT_FM_HV_RD Number of C interface wait cycles (on 'clk_c') for a read from the high Voltage page latches. Common for reading HV Page Latches and the DATA_COMP_RESULT bit [11:8] read-write WAIT_FM_HV_WR Number of C interface wait cycles (on 'clk_c') for a write to the high Voltage page latches. [18:16] read-write MONITOR_STATUS Monitor Status 0x2C 32 read-only 0x4 0x6 POS_PUMP_VLO POS pump VLO [1:1] read-only NEG_PUMP_VHI NEG pump VHI [2:2] read-only SCRATCH_CTL Scratch Control 0x30 32 read-write 0x0 0xFFFFFFFF DUMMY32 Scratchpad register fields. Provided for test purposes. [31:0] read-write HV_CTL High voltage control 0x34 32 read-write 0x32 0xFF TIMER_CLOCK_FREQ Specifies the frequency in MHz of the timer clock 'clk_t' as provide to the flash macro. E.g., if '4', the timer clock 'clk_t' has a frequency of 4 MHz. [7:0] read-write ACLK_CTL Aclk control 0x38 32 write-only 0x0 0x1 ACLK_GEN A write to this register generates a ACLK pulse for the flash macro (also requires FM_CTL.IF_SEL to be '1'). [0:0] write-only INTR Interrupt 0x3C 32 read-write 0x0 0x1 TIMER_EXPIRED Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit. [0:0] read-write INTR_SET Interrupt set 0x40 32 read-write 0x0 0x1 TIMER_EXPIRED Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [0:0] read-write INTR_MASK Interrupt mask 0x44 32 read-write 0x0 0x1 TIMER_EXPIRED Mask for corresponding field in INTR register. [0:0] read-write INTR_MASKED Interrupt masked 0x48 32 read-only 0x0 0x1 TIMER_EXPIRED Logical and of corresponding request and mask fields. [0:0] read-only FM_HV_DATA_ALL Flash macro high Voltage page latches data (for all page latches) 0x4C 32 write-only 0x0 0xFFFFFFFF DATA32 Write all high Voltage page latches with the same 32-bit data in a single write cycle [31:0] write-only CAL_CTL0 Cal control BG LO trim bits 0x50 32 read-write 0x88F8F 0xFFFFF VCT_TRIM_LO_HV LO Bandgap Voltage Temperature Compensation trim control. [4:0] read-write CDAC_LO_HV LO Temperature compensated trim DAC. To control Vcstat slope for Vpos. [7:5] read-write VBG_TRIM_LO_HV LO Bandgap Voltage trim control. [12:8] read-write VBG_TC_TRIM_LO_HV LO Bandgap Voltage Temperature Compensation trim control [15:13] read-write IPREF_TRIM_LO_HV LO Bandgap IPTAT trim control. [19:16] read-write CAL_CTL1 Cal control BG HI trim bits 0x54 32 read-write 0x88F8F 0xFFFFF VCT_TRIM_HI_HV HI Bandgap Voltage Temperature Compensation trim control. [4:0] read-write CDAC_HI_HV HI Temperature compensated trim DAC. To control Vcstat slope for Vpos. [7:5] read-write VBG_TRIM_HI_HV HI Bandgap Voltage trim control. [12:8] read-write VBG_TC_TRIM_HI_HV HI Bandgap Voltage Temperature Compensation trim control. [15:13] read-write IPREF_TRIM_HI_HV HI Bandgap IPTAT trim control. [19:16] read-write CAL_CTL2 Cal control BG LO&HI ipref trim, ref sel, fm_active, turbo_ext 0x58 32 read-write 0x7070 0xFFFFF ICREF_TRIM_LO_HV LO Bandgap Current trim control. [4:0] read-write ICREF_TC_TRIM_LO_HV LO Bandgap Current Temperature Compensation trim control [7:5] read-write ICREF_TRIM_HI_HV HI Bandgap Current trim control. [12:8] read-write ICREF_TC_TRIM_HI_HV HI Bandgap Current Temperature Compensation trim control. [15:13] read-write VREF_SEL_HV Voltage reference: '0': internal bandgap reference '1': external voltage reference [16:16] read-write IREF_SEL_HV Current reference: '0': internal current reference '1': external current reference [17:17] read-write FM_ACTIVE_HV 0: No Action 1: Forces FM SYS in active mode [18:18] read-write TURBO_EXT_HV 0: turbo signal generated internally 1: turbo cleared by clk_pump_ext HI [19:19] read-write CAL_CTL3 Cal control osc trim bits, idac, sdac, itim, bdac. 0x5C 32 read-write 0xA504 0xFFFFF OSC_TRIM_HV Flash macro pump clock trim control. [3:0] read-write OSC_RANGE_TRIM_HV 0: Oscillator High Frequency Range 1: Oscillator Low Frequency range [4:4] read-write IDAC_HV N/A [8:5] read-write SDAC_HV N/A [10:9] read-write ITIM_HV Trimming of timing current [14:11] read-write VDDHI_HV 0': vdd<2.3V '1': vdd>=2.3V [15:15] read-write TURBO_PULSEW_HV Turbo pulse width trim [17:16] read-write BGLO_EN_HV LO Bandgap Enable [18:18] read-write BGHI_EN_HV HI Bandgap Enable [19:19] read-write BOOKMARK Bookmark register - keeps the current FW HV seq 0x60 32 write-only 0x0 0xFFFFFFFF BOOKMARK Used by FW. Keeps the Current HV cycle sequence [31:0] write-only RED_CTL01 Redundancy Control normal sectors 0,1 0x80 32 read-write 0x0 0x1FF01FF RED_ADDR_0 Bad Row Pair Address for Sector 0 [7:0] read-write RED_EN_0 '1': Redundancy Enable for Sector 0 [8:8] read-write RED_ADDR_1 Bad Row Pair Address for Sector 1 [23:16] read-write RED_EN_1 '1': Redundancy Enable for Sector 1 [24:24] read-write RED_CTL23 Redundancy Controll normal sectors 2,3 0x84 32 read-write 0x0 0x1FF01FF RED_ADDR_2 Bad Row Pair Address for Sector 2 [7:0] read-write RED_EN_2 1': Redundancy Enable for Sector 2 [8:8] read-write RED_ADDR_3 Bad Row Pair Address for Sector 3 [23:16] read-write RED_EN_3 1': Redundancy Enable for Sector 3 [24:24] read-write RED_CTL45 Redundancy Controll normal sectors 4,5 0x88 32 read-write 0x0 0xFF01FF DNU_45_1 Not Used [0:0] read-write REG_ACT_HV Forces the VBST regulator in active mode all the time [1:1] read-write DNU_45_3 Not Used [2:2] read-write FDIV_TRIM_HV_0 '2b00' F = 1MHz see fdiv_trim_hv<1> value as well '2b01' F = 0.5MHz '2b10' F = 2MHz '2b11' F = 4Mhz [3:3] read-write DNU_45_5 Not Used [4:4] read-write FDIV_TRIM_HV_1 '2b00' F = 1MHz see fdiv_trim_hv<0> value as well '2b01' F = 0.5MHz '2b10' F = 2MHz '2b11' F = 4Mhz [5:5] read-write DNU_45_6 Not Used [6:6] read-write VLIM_TRIM_HV_0 '2b00' V2 = 650mV see vlim_trim_hv<1> value as well '2b01' V2 = 600mV '2b10' V2 = 750mV '2b11' V2 = 700mV [7:7] read-write DNU_45_8 Not Used [8:8] read-write DNU_45_23_16 Not Used [23:16] read-write RED_CTL67 Redundancy Controll normal sectors 6,7 0x8C 32 read-write 0x0 0xFF01FF VLIM_TRIM_HV_1 '2b00' V2 = 650mV see vlim_trim_hv<0> value as well '2b01' V2 = 600mV '2b10' V2 = 750mV '2b11' V2 = 700mV [0:0] read-write DNU_67_1 Not Used [1:1] read-write VPROT_ACT_HV Forces VPROT in active mode all the time [2:2] read-write DNU_67_3 Not Used [3:3] read-write IPREF_TC_HV Reduces the IPREF Tempco by not subtracting ICREF form IPREF - IPREF will be 1uA [4:4] read-write DNU_67_5 Not Used [5:5] read-write IPREF_TRIMA_HI_HV Adds 200-300nA boost on IPREF_HI [6:6] read-write DNU_67_7 Not Used [7:7] read-write IPREF_TRIMA_LO_HV Adds 200-300nA boost on IPREF_LO [8:8] read-write DNU_67_23_16 Not Used [23:16] read-write RED_CTL_SM01 Redundancy Controll special sectors 0,1 0x90 32 read-write 0x0 0xC1FF01FF RED_ADDR_SM0 Bad Row Pair Address for Special Sector 0 [7:0] read-write RED_EN_SM0 Redundancy Enable for Special Sector 0 [8:8] read-write RED_ADDR_SM1 Bad Row Pair Address for Special Sector 1 [23:16] read-write RED_EN_SM1 Redundancy Enable for Special Sector 1 [24:24] read-write TRKD Sense Amp Control tracking delay [30:30] read-write R_GRANT_EN '0': r_grant handshake disabled, r_grant always 1. '1': r_grand handshake enabled [31:31] read-write 32 4 TM_CMPR[%s] Do Not Use 0x100 32 read-only 0x0 0x1 DATA_COMP_RESULT The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal) [0:0] read-only 256 4 FM_HV_DATA[%s] Flash macro high Voltage page latches data 0x800 32 read-write 0x0 0xFFFFFFFF DATA32 Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality. [31:0] read-write 256 4 FM_MEM_DATA[%s] Flash macro memory sense amplifier and column decoder data 0xC00 32 read-only 0x0 0xFFFFFFFF DATA32 Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. [31:0] read-only SRSS SRSS Core Registers 0x40260000 0 65536 registers PWR_CTL Power Mode Control 0x0 32 read-write 0x0 0xFFFC0033 POWER_MODE Current power mode of the device. LPACTIVE/LPSLEEP are implemented as firmware configuration of multiple registers and are reported here as ACTIVE/SLEEP, respectively. Note that this field cannot be read in all power modes on actual silicon. [1:0] read-only RESET System is resetting. 0 ACTIVE At least one CPU is running. 1 SLEEP No CPUs are running. Peripherals may be running. 2 DEEPSLEEP Main high-frequency clock is off; low speed clocks are available. Communication interface clocks may be present. 3 DEBUG_SESSION Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1) [4:4] read-only NO_SESSION No debug session active 0 SESSION_ACTIVE Debug session is active. Power modes behave differently to keep the debug session active. 1 LPM_READY Indicates whether certain low power functions are ready. The low current circuits take longer to startup after POR/XRES/BOD/HIBERNATE wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless of this bit. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready. If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP. When low power circuits are ready, device will automatically enter the originally requested mode. 1: Normal operation. DEEPSLEEP and low power circuits operate as requested in other registers. [5:5] read-only IREF_LPMODE Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: Current reference generator operates in normal mode. It works for vddd ramp rates of 100mV/us or less. 1: Current reference generator operates in low power mode. Response time is reduced to save current, and it works for vddd ramp rates of 10mV/us or less. [18:18] read-write VREFBUF_OK Indicates that the voltage reference buffer is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting VREFBUF_DIS=1. [19:19] read-only DPSLP_REG_DIS Disable the DeepSleep regulator. For ULP products, this is only legal when the ULP SISO-LC/SIMO-LC Buck supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: DeepSleep Regulator is on. 1: DeepSleep Regulator is off. [20:20] read-write RET_REG_DIS Disable the Retention regulator. For ULP products, this is only legal when the ULP SISO-LC/SIMO-LC Buck supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: Retention Regulator is on. 1: Retention Regulator is off. [21:21] read-write NWELL_REG_DIS Disable the Nwell regulator. For ULP products, this is only legal when the ULP SISO-LC/SIMO-LC Buck supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: Nwell Regulator is on. 1: Nwell Regulator is off. [22:22] read-write LINREG_DIS Disable the linear Core Regulator. For ULP products, this is only legal when the ULP SISO-LC/SIMO-LC Buck supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: Linear regulator is on. 1: Linear regulator is off. [23:23] read-write LINREG_LPMODE Control the power mode of the ULP Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: ULP Linear Regulator operates in normal mode. Internal current consumption is 50uA and load current capability is 50mA to 300mA, depending on the number of regulator modules present in the product. 1: ULP Linear Regulator operates in low power mode. Internal current consumption is 5uA and load current capability is 25mA. Firmware must ensure the current is kept within the limit. [24:24] read-write PORBOD_LPMODE Control the power mode of the ULP POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: ULP POR/BOD circuits operate in normal mode. They work for vddd ramp rates of 100mV/us or less. 1: ULP POR/BOD circuits operate in low power mode. Response time is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. [25:25] read-write BGREF_LPMODE Control the power mode of the ULP Bandgap Voltage and Current References. This applies to voltage and current generation and is different than the reference voltage buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. When lower power mode is used, the Active Reference circuit can be disabled to reduce current. Firmware is responsible to ensure ACT_REF_OK==1 before changing back to normal mode. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: ULP Active Bandgap Voltage and Current Reference operates in normal mode. They work for vddd ramp rates of 100mV/us or less. 1: ULP Active Bandgap Voltage and Current Reference operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. The Active Reference may be disabled using ACT_REF_DIS=0. [26:26] read-write PLL_LS_BYPASS Bypass level shifter inside the PLL. 0: Do not bypass the level shifter. This setting is ok for all operational modes and vccd target voltage. 1: Bypass the level shifter. This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal. Otherwise, it can result in clock degradation and static current. [27:27] read-write VREFBUF_LPMODE Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. 0: ULP Voltage Reference Buffer operates in normal mode. They work for vddd ramp rates of 100mV/us or less. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 1: ULP Voltage Reference Buffer operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. [28:28] read-write VREFBUF_DIS Disable the 800mV voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS that use the buffer. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. [29:29] read-write ACT_REF_DIS Disables the Active Reference. Firmware must ensure that LPM_READY==1 and BGREF_LPMODE==1 for at least 1us before disabling the Active Reference. When enabling the Active Reference, use ACT_REF_OK indicator to know when it is ready. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: Active Reference is enabled 1: Active Reference is disabled [30:30] read-write ACT_REF_OK Indicates that the normal mode of the Active Reference is ready. [31:31] read-only PWR_HIBERNATE HIBERNATE Mode Register 0x4 32 read-write 0x0 0xCFFEFFFF TOKEN Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register. [7:0] read-write UNLOCK This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description. [15:8] read-write FREEZE Firmware sets this bit to freeze the configuration, mode and state of all GPIOs and SIOs in the system. When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This occurs even in the illegal condition where UNLOCK is not set. If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write. [17:17] read-write MASK_HIBALARM When set, HIBERNATE will wakeup for a RTC interrupt [18:18] read-write MASK_HIBWDT When set, HIBERNATE will wakeup if WDT matches [19:19] read-write POLARITY_HIBPIN Each bit sets the active polarity of the corresponding wakeup pin. 0: Pin input of 0 will wakeup the part from HIBERNATE 1: Pin input of 1 will wakeup the part from HIBERNATE [23:20] read-write MASK_HIBPIN When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting. Each bit corresponds to one of the wakeup pins. [27:24] read-write HIBERNATE_DISABLE Hibernate disable bit. 0: Normal operation, HIBERNATE works as described 1: Further writes to this register are ignored Note: This bit is a write-once bit until the next reset. Avoid changing any other bits in this register while disabling HIBERNATE mode. Also, it is recommended to clear the UNLOCK code, if it was previously written.. [30:30] read-write HIBERNATE Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event. Both UNLOCK and FREEZE must have been set correctly in a previous write operations. Otherwise, it will not enter HIBERNATE. External supplies must have been stable for 250us before entering HIBERNATE mode. [31:31] read-write PWR_LVD_CTL Low Voltage Detector (LVD) Configuration Register 0x8 32 read-write 0x0 0xFF HVLVD1_TRIPSEL Threshold selection for HVLVD1. Disable the LVD (HVLVD1_EN=0) before changing the threshold. 0: rise=1.225V (nom), fall=1.2V (nom) 1: rise=1.425V (nom), fall=1.4V (nom) 2: rise=1.625V (nom), fall=1.6V (nom) 3: rise=1.825V (nom), fall=1.8V (nom) 4: rise=2.025V (nom), fall=2V (nom) 5: rise=2.125V (nom), fall=2.1V (nom) 6: rise=2.225V (nom), fall=2.2V (nom) 7: rise=2.325V (nom), fall=2.3V (nom) 8: rise=2.425V (nom), fall=2.4V (nom) 9: rise=2.525V (nom), fall=2.5V (nom) 10: rise=2.625V (nom), fall=2.6V (nom) 11: rise=2.725V (nom), fall=2.7V (nom) 12: rise=2.825V (nom), fall=2.8V (nom) 13: rise=2.925V (nom), fall=2.9V (nom) 14: rise=3.025V (nom), fall=3.0V (nom) 15: rise=3.125V (nom), fall=3.1V (nom) [3:0] read-write HVLVD1_SRCSEL Source selection for HVLVD1 [6:4] read-write VDDD Select VDDD 0 AMUXBUSA Select AMUXBUSA (VDDD branch) 1 RSVD N/A 2 VDDIO N/A 3 AMUXBUSB Select AMUXBUSB (VDDD branch) 4 HVLVD1_EN Enable HVLVD1 voltage monitor. When the LVD is enabled, it takes 20us for it to settle. There is no hardware stabilization counter, and it may falsely trigger during settling. It is recommended that firmware keep the interrupt masked for at least 8us, write a 1'b1 to the corresponding SRSS_INTR field to any falsely pended interrupt, and then optionally unmask the interrupt. After enabling, it further recommended to read the realted PWR_LVD_STATUS field, since the interrupt only triggers on edges. This bit is cleared (LVD is disabled) when entering DEEPSLEEP to prevent false interrupts during wakeup. [7:7] read-write PWR_BUCK_CTL Buck Control Register 0x14 32 read-write 0x5 0xC0000007 BUCK_OUT1_SEL Voltage output selection for vccbuck1 output. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. 0: 0.85V 1: 0.875V 2: 0.90V 3: 0.95V 4: 1.05V 5: 1.10V 6: 1.15V 7: 1.20V [2:0] read-write BUCK_EN Master enable for buck converter. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. [30:30] read-write BUCK_OUT1_EN Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. The SAS specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1. [31:31] read-write PWR_BUCK_CTL2 Buck Control Register 2 0x18 32 read-write 0x0 0xC0000007 BUCK_OUT2_SEL Voltage output selection for vccbuck2 output. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. 0: 1.15V 1: 1.20V 2: 1.25V 3: 1.30V 4: 1.35V 5: 1.40V 6: 1.45V 7: 1.50V [2:0] read-write BUCK_OUT2_HW_SEL Hardware control for vccbuck2 output. When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware, it can directly control the enable signal for vccbuck2. The same charging time in BUCK_OUT2_EN applies. [30:30] read-write BUCK_OUT2_EN Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. [31:31] read-write PWR_LVD_STATUS Low Voltage Detector (LVD) Status Register 0x1C 32 read-only 0x0 0x1 HVLVD1_OK HVLVD1 output. 0: below voltage threshold 1: above voltage threshold [0:0] read-only 16 4 PWR_HIB_DATA[%s] HIBERNATE Data Register 0x80 32 read-write 0x0 0xFFFFFFFF HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. [31:0] read-write WDT_CTL Watchdog Counter Control Register 0x180 32 read-write 0xC0000001 0xC0000001 WDT_EN Enable this watchdog timer. This field is retained during DEEPSLEEP and HIBERNATE modes. [0:0] read-write WDT_LOCK Prohibits writing to WDT_*, CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers when not equal 0. Requires at least two different writes to unlock. A change in WDT_LOCK takes effect beginning with the next write cycle. Note that this field is 2 bits to force multiple writes only. It represents only a single write protect signal protecting all those registers at the same time. WDT will lock on any reset. This field is not retained during DEEPSLEEP or HIBERNATE mode, so the WDT will be locked after wakeup from these modes. [31:30] read-write NO_CHG No effect 0 CLR0 Clears bit 0 1 CLR1 Clears bit 1 2 SET01 Sets both bits 0 and 1 3 WDT_CNT Watchdog Counter Count Register 0x184 32 read-write 0x0 0xFFFF COUNTER Current value of WDT Counter. The write feature of this register is for engineering use (DfV), have no synchronization, and can only be applied when the WDT is fully off. When writing, the value is updated immediately in the WDT counter, but it will read back as the old value until this register resynchronizes just after the negedge of ILO. Writes will be ignored if they occur when the WDT is enabled. [15:0] read-write WDT_MATCH Watchdog Counter Match Register 0x188 32 read-write 0x1000 0xFFFFF MATCH Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match). [15:0] read-write IGNORE_BITS The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). Up to 12 MSB can be ignored. Settings >12 behave like a setting of 12. [19:16] read-write 2 64 MCWDT_STRUCT[%s] Multi-Counter Watchdog Timer MCWDT_STRUCT 0x00000200 MCWDT_CNTLOW Multi-Counter Watchdog Sub-counters 0/1 0x4 32 read-write 0x0 0xFFFFFFFF WDT_CTR0 Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled. [15:0] read-write WDT_CTR1 Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled [31:16] read-write MCWDT_CNTHIGH Multi-Counter Watchdog Sub-counter 2 0x8 32 read-write 0x0 0xFFFFFFFF WDT_CTR2 Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled [31:0] read-write MCWDT_MATCH Multi-Counter Watchdog Counter Match Register 0xC 32 read-write 0x0 0xFFFFFFFF WDT_MATCH0 Match value for sub-counter 0 of this MCWDT [15:0] read-write WDT_MATCH1 Match value for sub-counter 1 of this MCWDT [31:16] read-write MCWDT_CONFIG Multi-Counter Watchdog Counter Configuration 0x10 32 read-write 0x0 0x1F010F0F WDT_MODE0 Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0). [1:0] read-write NOTHING Do nothing 0 INT Assert WDT_INTx 1 RESET Assert WDT Reset 2 INT_THEN_RESET Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt 3 WDT_CLEAR0 Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1). 0: Free running counter 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH0 is 1. [2:2] read-write WDT_CASCADE0_1 Cascade Watchdog Counters 0,1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0. 0: Independent counters 1: Cascaded counters [3:3] read-write WDT_MODE1 Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1). [9:8] read-write NOTHING Do nothing 0 INT Assert WDT_INTx 1 RESET Assert WDT Reset 2 INT_THEN_RESET Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt 3 WDT_CLEAR1 Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1). 0: Free running counter 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH1 is 1. [10:10] read-write WDT_CASCADE1_2 Cascade Watchdog Counters 1,2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters. 0: Independent counters 1: Cascaded counters. When cascading all three counters, WDT_CLEAR1 must be 1. [11:11] read-write WDT_MODE2 Watchdog Counter 2 Mode. [16:16] read-write NOTHING Free running counter with no interrupt requests 0 INT Free running counter with interrupt request that occurs one LFCLK cycle after the specified bit in CTR2 toggles (see WDT_BITS2). 1 WDT_BITS2 Bit to observe for WDT_INT2: 0: Assert after bit0 of WDT_CTR2 toggles (one int every tick) .. 31: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks) [28:24] read-write MCWDT_CTL Multi-Counter Watchdog Counter Control 0x14 32 read-write 0x0 0xB0B0B WDT_ENABLE0 Enable subcounter 0. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) [0:0] read-write WDT_ENABLED0 Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles. [1:1] read-only WDT_RESET0 Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. [3:3] read-write WDT_ENABLE1 Enable subcounter 1. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) [8:8] read-write WDT_ENABLED1 Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles. [9:9] read-only WDT_RESET1 Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. [11:11] read-write WDT_ENABLE2 Enable subcounter 2. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) [16:16] read-write WDT_ENABLED2 Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles. [17:17] read-only WDT_RESET2 Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. [19:19] read-write MCWDT_INTR Multi-Counter Watchdog Counter Interrupt Register 0x18 32 read-write 0x0 0x7 MCWDT_INT0 MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3. [0:0] read-write MCWDT_INT1 MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3. [1:1] read-write MCWDT_INT2 MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3. [2:2] read-write MCWDT_INTR_SET Multi-Counter Watchdog Counter Interrupt Set Register 0x1C 32 read-write 0x0 0x7 MCWDT_INT0 Set interrupt for MCWDT_INT0 [0:0] read-write MCWDT_INT1 Set interrupt for MCWDT_INT1 [1:1] read-write MCWDT_INT2 Set interrupt for MCWDT_INT2 [2:2] read-write MCWDT_INTR_MASK Multi-Counter Watchdog Counter Interrupt Mask Register 0x20 32 read-write 0x0 0x7 MCWDT_INT0 Mask for sub-counter 0 [0:0] read-write MCWDT_INT1 Mask for sub-counter 1 [1:1] read-write MCWDT_INT2 Mask for sub-counter 2 [2:2] read-write MCWDT_INTR_MASKED Multi-Counter Watchdog Counter Interrupt Masked Register 0x24 32 read-only 0x0 0x7 MCWDT_INT0 Logical and of corresponding request and mask bits. [0:0] read-only MCWDT_INT1 Logical and of corresponding request and mask bits. [1:1] read-only MCWDT_INT2 Logical and of corresponding request and mask bits. [2:2] read-only MCWDT_LOCK Multi-Counter Watchdog Counter Lock Register 0x28 32 read-write 0x0 0xC0000000 MCWDT_LOCK Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. Note that this field is 2 bits to force multiple writes only. Each MCWDT has a separate local lock. LFCLK settings are locked by the global WDT_LOCK register, and this register has no effect on that. [31:30] read-write NO_CHG No effect 0 CLR0 Clears bit 0 1 CLR1 Clears bit 1 2 SET01 Sets both bits 0 and 1 3 16 4 CLK_DSI_SELECT[%s] Clock DSI Select Register 0x300 32 read-write 0x0 0x1F DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH<i> using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. [4:0] read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO ILO - Internal Low-speed Oscillator 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 16 4 CLK_PATH_SELECT[%s] Clock Path Select Register 0x340 32 read-write 0x0 0x7 PATH_MUX Selects a source for clock PATH<i>. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. [2:0] read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 16 4 CLK_ROOT_SELECT[%s] Clock Root Select Register 0x380 32 read-write 0x0 0x8000003F ROOT_MUX Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>. Use CLK_SELECT_PATH[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. [3:0] read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 ROOT_DIV Selects predivider value for this clock root and DSI input. [5:4] read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. [31:31] read-write CLK_SELECT Clock selection register 0x500 32 read-write 0x0 0xFF03 LFCLK_SEL Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. [1:0] read-write ILO ILO - Internal Low-speed Oscillator 0 WCO WCO - Watch-Crystal Oscillator. Requires Backup domain to be present and properly configured (including external watch crystal, if used). 1 ALTLF ALTLF - Alternate Low-Frequency Clock. Capability is product-specific 2 PILO PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes. Does not work in HIBERNATE mode. 3 PUMP_SEL Selects clock PATH<k>, where k=PUMP_SEL. The output of this mux goes to the PUMP_DIV to make PUMPCLK Each product has a specific number of available clock paths. Selecting a path that is not implemented on a product will result in undefined behavior. Note that this is not a glitch free mux. [11:8] read-write PUMP_DIV Division ratio for PUMPCLK. Uses selected PUMP_SEL clock as the source. [14:12] read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 DIV_BY_16 Divide selected clock source by 16 4 PUMP_ENABLE Enable the pump clock. PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects, avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE. To change the settings, do the following: 1) If the pump clock is enabled, write PUMP_ENABLE=0 without changing PUMP_SEL and PUMP_DIV. 2) Change PUMP_SEL and PUMP_DIV to desired settings with PUMP_ENABLE=0. 3) Write PUMP_ENABLE=1 without changing PUMP_SEL and PUMP_DIV. [15:15] read-write CLK_TIMER_CTL Timer Clock Control Register 0x504 32 read-write 0x70000 0x80FF0301 TIMER_SEL Select source for TIMERCLK. The output of this mux can be further divided using TIMER_DIV. [0:0] read-write IMO IMO - Internal Main Oscillator 0 HF0_DIV Select the output of the predivider configured by TIMER_HF0_DIV. 1 TIMER_HF0_DIV Predivider used when HF0_DIV is selected in TIMER_SEL. If HFCLK0 frequency is less than 100MHz and has approximately 50 percent duty cycle, then no division is required (NO_DIV). Otherwise, select a divide ratio of 2, 4, or 8 before selected HF0_DIV as the timer clock. [9:8] read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing or correcting duty cycle. 0 DIV_BY_2 Divide HFCLK0 by 2. 1 DIV_BY_4 Divide HFCLK0 by 4. 2 DIV_BY_8 Divide HFCLK0 by 8. 3 TIMER_DIV Divide selected timer clock source by (1+TIMER_DIV). The output of this divider is TIMERCLK Allows for integer divisions in the range [1, 256]. Do not change this setting while the timer is enabled. [23:16] read-write ENABLE Enable for TIMERCLK. 0: TIMERCLK is off 1: TIMERCLK is enabled [31:31] read-write CLK_ILO_CONFIG ILO Configuration 0x50C 32 read-write 0x80000000 0x80000001 ILO_BACKUP If backup domain is present, this register indicates that ILO should stay enabled for use by backup domain during XRES, HIBERNATE mode, and through power-related resets like BOD. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. 0: ILO turns off at XRES/BOD event or HIBERNATE entry. 1: ILO remains on if backup domain is present and powered even for XRES/BOD or HIBERNATE entry. [0:0] read-write ENABLE Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. [31:31] read-write CLK_IMO_CONFIG IMO Configuration 0x510 32 read-write 0x80000000 0x80000000 ENABLE Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during DEEPSLEEP, HIBERNATE, and XRES. [31:31] read-write CLK_OUTPUT_FAST Fast Clock Output Select Register 0x514 32 read-write 0x0 0xFFF0FFF FAST_SEL0 Select signal for fast clock output #0 [3:0] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0. 0 ECO External Crystal Oscillator (ECO) 1 EXTCLK External clock input (EXTCLK) 2 ALTHF Alternate High-Frequency (ALTHF) clock input to SRSS 3 TIMERCLK Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. 4 PATH_SEL0 Selects the clock path chosen by PATH_SEL0 field 5 HFCLK_SEL0 Selects the output of the HFCLK_SEL0 mux 6 SLOW_SEL0 Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0 7 PATH_SEL0 Selects a clock path to use in fast clock output #0 logic. For FLL path, it connects after the bypass mux. For PLL path(s), it connects after the CLK_PLL_DDFT mux. 0: FLL output 1-15: PLL output on path1-path15 (if available) [7:4] read-write HFCLK_SEL0 Selects a HFCLK tree for use in fast clock output #0 [11:8] read-write FAST_SEL1 Select signal for fast clock output #1 [19:16] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1. 0 ECO External Crystal Oscillator (ECO) 1 EXTCLK External clock input (EXTCLK) 2 ALTHF Alternate High-Frequency (ALTHF) clock input to SRSS 3 TIMERCLK Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. 4 PATH_SEL1 Selects the clock path chosen by PATH_SEL1 field 5 HFCLK_SEL1 Selects the output of the HFCLK_SEL1 mux 6 SLOW_SEL1 Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1 7 PATH_SEL1 Selects a clock path to use in fast clock output #1 logic. For FLL path, it connects after the bypass mux. For PLL path(s), it connects after the CLK_PLL_DDFT mux. 1-15: PLL output on path1-path15 (if available) [23:20] read-write HFCLK_SEL1 Selects a HFCLK tree for use in fast clock output #1 logic [27:24] read-write CLK_OUTPUT_SLOW Slow Clock Output Select Register 0x518 32 read-write 0x0 0xFF SLOW_SEL0 Select signal for slow clock output #0 [3:0] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. 0 ILO Internal Low Speed Oscillator (ILO) 1 WCO Watch-Crystal Oscillator (WCO) 2 BAK Root of the Backup domain clock tree (BAK) 3 ALTLF Alternate low-frequency clock input to SRSS (ALTLF) 4 LFCLK Root of the low-speed clock tree (LFCLK) 5 IMO Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 6 SLPCTRL Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 7 PILO Precision Internal Low Speed Oscillator (PILO) 8 SLOW_SEL1 Select signal for slow clock output #1 [7:4] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. 0 ILO Internal Low Speed Oscillator (ILO) 1 WCO Watch-Crystal Oscillator (WCO) 2 BAK Root of the Backup domain clock tree (BAK) 3 ALTLF Alternate low-frequency clock input to SRSS (ALTLF) 4 LFCLK Root of the low-speed clock tree (LFCLK) 5 IMO Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 6 SLPCTRL Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 7 PILO Precision Internal Low Speed Oscillator (PILO) 8 CLK_CAL_CNT1 Clock Calibration Counter 1 0x51C 32 read-write 0x80000000 0x80FFFFFF CAL_COUNTER1 Down-counter clocked on fast DDFT output #0 (see TST_DDFT_FAST_CTL). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done. Do not write this field unless CAL_COUNTER_DONE==1. [23:0] read-write CAL_COUNTER_DONE Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up [31:31] read-only CLK_CAL_CNT2 Clock Calibration Counter 2 0x520 32 read-only 0x0 0xFFFFFF CAL_COUNTER2 Up-counter clocked on fast DDFT output #1 (see TST_DDFT_FAST_CTL). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER) [23:0] read-only CLK_ECO_CONFIG ECO Configuration Register 0x52C 32 read-write 0x2 0x80000002 AGC_EN Automatic Gain Control (AGC) enable. When set, the oscillation amplitude is controlled to the level selected by ECO_TRIM0.ATRIM. When low, the amplitude is not explicitly controlled and will grow until it saturates to the supply rail (1.8V nom). WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal. [1:1] read-write ECO_EN Master enable for ECO oscillator. [31:31] read-write CLK_ECO_STATUS ECO Status Register 0x530 32 read-only 0x0 0x3 ECO_OK Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec. [0:0] read-only ECO_READY Indicates the ECO internal oscillator circuit has fully stabilized. [1:1] read-only CLK_PILO_CONFIG Precision ILO Configuration Register 0x53C 32 read-write 0x80 0xE00003FF PILO_FFREQ Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz. [9:0] read-write PILO_CLK_EN Enable the PILO clock output. See PILO_EN field for required sequencing. [29:29] read-write PILO_RESET_N Reset the PILO. See PILO_EN field for required sequencing. [30:30] read-write PILO_EN Enable PILO. When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle. [31:31] read-write CLK_FLL_CONFIG FLL Configuration Register 0x580 32 read-write 0x1000000 0x8103FFFF FLL_MULT Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref). Ffll = (FLL_MULT) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1) [17:0] read-write FLL_OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. 0: no division 1: divide by 2 [24:24] read-write FLL_ENABLE Master enable for FLL. Do not enable until the reference clock has stabilized. 0: Block is powered off 1: Block is powered on [31:31] read-write CLK_FLL_CONFIG2 FLL Configuration Register 2 0x584 32 read-write 0x20001 0x1FF1FFF FLL_REF_DIV Control bits for reference divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 8191: divide by 8191 [12:0] read-write LOCK_TOL Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or to track a less accurate source. The tolerance should be set so that the FLL does not unlock under normal conditions. The tolerance is the allowed difference between the count value for the ideal formula and the measured value. 0: tolerate error of 1 count value 1: tolerate error of 2 count values ... 511: tolerate error of 512 count values [24:16] read-write CLK_FLL_CONFIG3 FLL Configuration Register 3 0x588 32 read-write 0x2800 0x301FFFFF FLL_LF_IGAIN FLL Loop Filter Integral Gain Setting 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 >=12: illegal [3:0] read-write FLL_LF_PGAIN FLL Loop Filter Proportional Gain Setting 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 >=12: illegal [7:4] read-write SETTLING_COUNT Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case. 0: no settling time 1: wait one reference clock cycle ... 8191: wait 8191 reference clock cycles [20:8] read-write BYPASS_SEL Bypass mux located just after FLL output. [29:28] read-write AUTO Automatic using lock indicator. When unlocked, automatically selects FLL reference input (bypass mode). When locked, automatically selects FLL output. 0 AUTO1 Same as AUTO 1 FLL_REF Select FLL reference input (bypass mode). Ignores lock indicator 2 FLL_OUT Select FLL output. Ignores lock indicator. 3 CLK_FLL_CONFIG4 FLL Configuration Register 4 0x58C 32 read-write 0xFF 0xC1FF07FF CCO_LIMIT Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support) [7:0] read-write CCO_RANGE Frequency range of CCO [10:8] read-write RANGE0 Target frequency is in range [48, 64) MHz 0 RANGE1 Target frequency is in range [64, 85) MHz 1 RANGE2 Target frequency is in range [85, 113) MHz 2 RANGE3 Target frequency is in range [113, 150) MHz 3 RANGE4 Target frequency is in range [150, 200] MHz 4 CCO_FREQ CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range. [24:16] read-write CCO_HW_UPDATE_DIS Disable CCO frequency update by FLL hardware 0: Hardware update of CCO settings is allowed. Use this setting for normal FLL operation. 1: Hardware update of CCO settings is disabled. Use this setting for open-loop FLL operation. [30:30] read-write CCO_ENABLE Enable the CCO. It is required to enable the CCO before using the FLL. 0: Block is powered off 1: Block is powered on [31:31] read-write CLK_FLL_STATUS FLL Status Register 0x590 32 read-write 0x0 0x7 LOCKED FLL Lock Indicator [0:0] read-only UNLOCK_OCCURRED N/A [1:1] read-write CCO_READY This indicates that the CCO is internally settled and ready to use. [2:2] read-only 15 4 CLK_PLL_CONFIG[%s] PLL Configuration Register 0x600 32 read-write 0x20116 0xB81F1F7F FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) [6:0] read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) [12:8] read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) [20:16] read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) [27:27] read-write BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. [29:28] read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. 0 AUTO1 Same as AUTO 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled [31:31] read-write 15 4 CLK_PLL_STATUS[%s] PLL Status Register 0x640 32 read-write 0x0 0x3 LOCKED PLL Lock Indicator [0:0] read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. [1:1] read-write SRSS_INTR SRSS Interrupt Register 0x700 32 read-write 0x0 0x23 WDT_MATCH WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. W1C also feeds the watch dog. Missing 2 interrupts in a row will generate a reset. Due to internal synchronization, it takes 2 SYSCLK cycles to update after a W1C. [0:0] read-write HVLVD1 Interrupt for low voltage detector HVLVD1 [1:1] read-write CLK_CAL Clock calibration counter is done [5:5] read-write SRSS_INTR_SET SRSS Interrupt Set Register 0x704 32 read-write 0x0 0x23 WDT_MATCH Set interrupt for low voltage detector WDT_MATCH [0:0] read-write HVLVD1 Set interrupt for low voltage detector HVLVD1 [1:1] read-write CLK_CAL Set interrupt for clock calibration counter done [5:5] read-write SRSS_INTR_MASK SRSS Interrupt Mask Register 0x708 32 read-write 0x0 0x23 WDT_MATCH Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU. It will not, however, disable the WDT reset generation on 2 missed interrupts. [0:0] read-write HVLVD1 Mask for low voltage detector HVLVD1 [1:1] read-write CLK_CAL Mask for clock calibration done [5:5] read-write SRSS_INTR_MASKED SRSS Interrupt Masked Register 0x70C 32 read-only 0x0 0x23 WDT_MATCH Logical and of corresponding request and mask bits. [0:0] read-only HVLVD1 Logical and of corresponding request and mask bits. [1:1] read-only CLK_CAL Logical and of corresponding request and mask bits. [5:5] read-only SRSS_INTR_CFG SRSS Interrupt Configuration Register 0x710 32 read-write 0x0 0x3 HVLVD1_EDGE_SEL Sets which edge(s) will trigger an IRQ for HVLVD1 [1:0] read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 RES_CAUSE Reset Cause Observation Register 0x800 32 read-write 0x0 0x1FF RESET_WDT A basic WatchDog Timer (WDT) reset has occurred since last power cycle. [0:0] read-write RESET_ACT_FAULT Fault logging system requested a reset from its Active logic. [1:1] read-write RESET_DPSLP_FAULT Fault logging system requested a reset from its DeepSleep logic. [2:2] read-write RESET_CSV_WCO_LOSS Clock supervision logic requested a reset due to loss of a watch-crystal clock. [3:3] read-write RESET_SOFT A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. [4:4] read-write RESET_MCWDT0 Multi-Counter Watchdog timer reset #0 has occurred since last power cycle. [5:5] read-write RESET_MCWDT1 Multi-Counter Watchdog timer reset #1 has occurred since last power cycle. [6:6] read-write RESET_MCWDT2 Multi-Counter Watchdog timer reset #2 has occurred since last power cycle. [7:7] read-write RESET_MCWDT3 Multi-Counter Watchdog timer reset #3 has occurred since last power cycle. [8:8] read-write RES_CAUSE2 Reset Cause Observation Register 2 0x804 32 read-write 0x0 0xFFFFFFFF RESET_CSV_HF_LOSS Clock supervision logic requested a reset due to loss of a high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. [15:0] read-write RESET_CSV_HF_FREQ Clock supervision logic requested a reset due to frequency error of high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. [31:16] read-write PWR_TRIM_REF_CTL Reference Trim Register 0x7F00 32 read-write 0x70F00000 0xF1FF5FFF ACT_REF_TCTRIM Active-Reference temperature trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range [3:0] read-write ACT_REF_ITRIM Active-Reference current trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range [7:4] read-write ACT_REF_ABSTRIM Active-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range [12:8] read-write ACT_REF_IBOOST Active-Reference current boost. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: normal operation others: risk mitigation [14:14] read-write DPSLP_REF_TCTRIM DeepSleep-Reference temperature trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range [19:16] read-write DPSLP_REF_ABSTRIM DeepSleep-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. [24:20] read-write DPSLP_REF_ITRIM DeepSleep current reference trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. [31:28] read-write PWR_TRIM_BODOVP_CTL BOD/OVP Trim Register 0x7F04 32 read-write 0x40D04 0xFDFF7 HVPORBOD_TRIPSEL HVPORBOD trip point selection. Monitors vddd. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. [2:0] read-write HVPORBOD_OFSTRIM HVPORBOD offset trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. [6:4] read-write HVPORBOD_ITRIM HVPORBOD current trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. [9:7] read-write LVPORBOD_TRIPSEL LVPORBOD trip point selection. Monitors vccd. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. [12:10] read-write LVPORBOD_OFSTRIM LVPORBOD offset trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. [16:14] read-write LVPORBOD_ITRIM LVPORBOD current trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. [19:17] read-write CLK_TRIM_CCO_CTL CCO Trim Register 0x7F08 32 read-write 0xA7000020 0xBF00003F CCO_RCSTRIM CCO reference current source trim. [5:0] read-write CCO_STABLE_CNT Terminal count for the stabilization counter from CCO_ENABLE until stable. [29:24] read-write ENABLE_CNT Enables the automatic stabilization counter. [31:31] read-write CLK_TRIM_CCO_CTL2 CCO Trim Register 2 0x7F0C 32 read-write 0x884110 0x1FFFFFF CCO_FCTRIM1 CCO frequency 1st range calibration [4:0] read-write CCO_FCTRIM2 CCO frequency 2nd range calibration [9:5] read-write CCO_FCTRIM3 CCO frequency 3rd range calibration [14:10] read-write CCO_FCTRIM4 CCO frequency 4th range calibration [19:15] read-write CCO_FCTRIM5 CCO frequency 5th range calibration [24:20] read-write PWR_TRIM_WAKE_CTL Wakeup Trim Register 0x7F30 32 read-write 0x0 0xFF WAKE_DELAY Wakeup holdoff. Spec (fastest) wake time is achieve with a setting of 0. Additional delay can be added for debugging or workaround. The delay is counted by the IMO. [7:0] read-write PWR_TRIM_LVD_CTL LVD Trim Register 0xFF10 32 read-write 0x20 0x77 HVLVD1_OFSTRIM HVLVD1 offset trim [2:0] read-write HVLVD1_ITRIM HVLVD1 current trim [6:4] read-write CLK_TRIM_ILO_CTL ILO Trim Register 0xFF18 32 read-write 0x2C 0x3F ILO_FTRIM ILO frequency trims. LSB step size is 1.5 percent (typical) of the frequency. [5:0] read-write PWR_TRIM_PWRSYS_CTL Power System Trim Register 0xFF1C 32 read-write 0x17 0x1F ACT_REG_TRIM Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. The nominal output voltage is vccd=812.5mV + ACT_REG_TRIM*12.5mV. The actual output voltage will vary depending on conditions and load. The following settings are explicitly shown for convenience, and other values may be calculated using the formula: 5'h07: 900mV (nominal) 5'h17: 1100mV (nominal) [4:0] read-write ACT_REG_BOOST Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that. This may allow a reduction in the internal operating current of the regulator. The regulator internal operating current depends on the boost setting: 2'b00: 50uA 2'b01: 100uA 2'b10: 150uA 2'b11: 200uA The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer). The defaults are set assuming the application consumes the maximum allowed by the chip. 50mA chip: 2'b00 (default); 100mA chip: 2'b00 (default); 150mA chip: 50..100mA app => 2'b00, 150mA app => 2'b01 (default); 200mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200mA app => 2'b10 (default); 250mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10 (default); 300mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10, 300mA app => 2'b11 (default); This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. [31:30] read-write CLK_TRIM_ECO_CTL ECO Trim Register 0xFF20 32 read-write 0x1F0003 0x3F3FF7 WDTRIM Watch Dog Trim - Delta voltage below stead state level 0x0 - 50mV 0x1 - 75mV 0x2 - 100mV 0x3 - 125mV 0x4 - 150mV 0x5 - 175mV 0x6 - 200mV 0x7 - 225mV [2:0] read-write ATRIM Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal. 0x0 - 150mV 0x1 - 175mV 0x2 - 200mV 0x3 - 225mV 0x4 - 250mV 0x5 - 275mV 0x6 - 300mV 0x7 - 325mV 0x8 - 350mV 0x9 - 375mV 0xA - 400mV 0xB - 425mV 0xC - 450mV 0xD - 475mV 0xE - 500mV 0xF - 525mV [7:4] read-write FTRIM Filter Trim - 3rd harmonic oscillation [9:8] read-write RTRIM Feedback resistor Trim [11:10] read-write GTRIM Gain Trim - Startup time [13:12] read-write ITRIM Current Trim [21:16] read-write CLK_TRIM_PILO_CTL PILO Trim Register 0xFF24 32 read-write 0x108500F 0x7DFF703F PILO_CFREQ Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz. [5:0] read-write PILO_OSC_TRIM Trim for current in oscillator block. [14:12] read-write PILO_COMP_TRIM Trim for comparator bias current. [17:16] read-write PILO_NBIAS_TRIM Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier [19:18] read-write PILO_RES_TRIM Trim for beta-multiplier branch current [24:20] read-write PILO_ISLOPE_TRIM Trim for beta-multiplier current slope [27:26] read-write PILO_VTDIFF_TRIM Trim for VT-DIFF output (internal power supply) [30:28] read-write CLK_TRIM_PILO_CTL2 PILO Trim Register 2 0xFF28 32 read-write 0xDA10E0 0xFF1FFF PILO_VREF_TRIM Trim for voltage reference [7:0] read-write PILO_IREFBM_TRIM Trim for beta-multiplier current reference [12:8] read-write PILO_IREF_TRIM Trim for current reference [23:16] read-write CLK_TRIM_PILO_CTL3 PILO Trim Register 3 0xFF2C 32 read-write 0x4800 0xFFFF PILO_ENGOPT Engineering options for PILO circuits 0: Short vdda to vpwr 1: Beta:mult current change 2: Iref generation Ptat current addition 3: Disable current path in secondary Beta:mult startup circuit 4: Double oscillator current 5: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block 6: Spare 7: Ptat component increase in Iref 8: vpwr_rc and vpwr_dig_rc shorting testmode 9: Switch b/w psub connection for cascode nfet for vref generation 10: Switch between sub:threshold and deep:sub:threshold stacks in comparator. 15-11: Frequency fine trim. See AKK-444 for an overview of the trim strategy. [15:0] read-write BACKUP SRSS Backup Domain 0x40270000 0 65536 registers CTL Control 0x0 32 read-write 0x0 0xFF0F3308 WCO_EN Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes. After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs. [3:3] read-write CLK_SEL Clock select for BAK clock [9:8] read-write WCO Watch-crystal oscillator input. 0 ALTBAK This allows to use the LFCLK selection as an alternate backup domain clock. Note that LFCLK is not available in all power modes, and clock glitches can propagate into the backup logic when the clock is stopped. For this reason, if the WCO is intended as the clock source then choose it directly instead of routing through LFCLK. 1 PRESCALER N/A [13:12] read-write WCO_BYPASS Configures the WCO for different board-level connections to the WCO pins. For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1. 0: Watch crystal. Connect a 32.768 kHz watch crystal between WCO input and output pins. 1: Clock signal, either a square wave or sine wave. See PRESCALER field for connection information. [16:16] read-write VDDBAK_CTL Controls the behavior of the switch that generates vddbak from vbackup or vddd. 0: automatically select vddd if its brownout detector says it is valid. If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup. 1,2,3: force vddbak and vmax to select vbackup, regardless of its voltage. [18:17] read-write VBACKUP_MEAS Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled by 40 percent so it is within the supply range of the ADC. [19:19] read-write EN_CHARGE_KEY When set to 3C, the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY. [31:24] read-write RTC_RW RTC Read Write register 0x8 32 read-write 0x0 0x3 READ Read bit When this bit is set the RTC registers will be copied to user registers and frozen so that a coherent RTC value can safely be read. The RTC will keep on running. Do not set the read bit if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Write bit is set. Do not set the Read bit at the same time that the Write bit is cleared. [0:0] read-write WRITE Write bit Only when this bit is set can the RTC registers be written to (otherwise writes are ignored). This bit cannot be set if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Read bit is set or getting set. The user writes to the RTC user registers, when the Write bit is cleared by the user then the user registers content is copied to the actual RTC registers. Only user RTC registers that were written to will get copied, others will not be affected. When the SECONDS field is updated then TICKS will also be reset (WDT is not affected). When the Write bit is cleared by a reset (brown out/DeepSleep) then the RTC update will be ignored/lost. Do not set the Write bit if the RTC if the RTC is still busy with a previous update (see RTC_BUSY). Do not set the Write bit at the same time that the Read bit is cleared. [1:1] read-write CAL_CTL Oscillator calibration for absolute frequency 0xC 32 read-write 0x0 0x8000007F CALIB_VAL Calibration value for absolute frequency (at a fixed temperature). Each step causes 128 ticks to be added or removed each hour. Effectively that means that each step is 1.085ppm (= 128/(60*60*32,768)). Positive values 0x01-0x3c (1..60) add pulses, negative values remove pulses, thus giving a range of +/-65.1 ppm (limited by 60 minutes per hour, not the range of this field) Calibration is performed hourly, starting at 59 minutes and 59 seconds, and applied as 64 ticks every 30 seconds until there have been 2*CALIB_VAL adjustments. [5:0] read-write CALIB_SIGN Calibration sign: 0= Negative sign: remove pulses (it takes more clock ticks to count one second) 1= Positive sign: add pulses (it takes less clock ticks to count one second) [6:6] read-write CAL_OUT Output enable for 512Hz signal for calibration and allow CALIB_VAL to be written. Note that calibration does not affect the 512Hz output signal. [31:31] read-write STATUS Status 0x10 32 read-only 0x0 0x5 RTC_BUSY pending RTC write [0:0] read-only WCO_OK Indicates that output has transitioned. [2:2] read-only RTC_TIME Calendar Seconds, Minutes, Hours, Day of Week 0x14 32 read-write 0x1000000 0x77F7F7F RTC_SEC Calendar seconds in BCD, 0-59 [6:0] read-write RTC_MIN Calendar minutes in BCD, 0-59 [14:8] read-write RTC_HOUR Calendar hours in BCD, value depending on 12/24HR mode 0=24HR: [21:16]=0-23 1=12HR: [21]:0=AM, 1=PM, [20:16]=1-12 [21:16] read-write CTRL_12HR Select 12/24HR mode: 1=12HR, 0=24HR [22:22] read-write RTC_DAY Calendar Day of the week in BCD, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended [26:24] read-write RTC_DATE Calendar Day of Month, Month, Year 0x18 32 read-write 0x101 0xFF1F3F RTC_DATE Calendar Day of the Month in BCD, 1-31 Automatic Leap Year Correction [5:0] read-write RTC_MON Calendar Month in BCD, 1-12 [12:8] read-write RTC_YEAR Calendar year in BCD, 0-99 [23:16] read-write ALM1_TIME Alarm 1 Seconds, Minute, Hours, Day of Week 0x1C 32 read-write 0x1000000 0x87BFFFFF ALM_SEC Alarm seconds in BCD, 0-59 [6:0] read-write ALM_SEC_EN Alarm second enable: 0=ignore, 1=match [7:7] read-write ALM_MIN Alarm minutes in BCD, 0-59 [14:8] read-write ALM_MIN_EN Alarm minutes enable: 0=ignore, 1=match [15:15] read-write ALM_HOUR Alarm hours in BCD, value depending on 12/24HR mode 12HR: [5]:0=AM, 1=PM, [4:0]=1-12 24HR: [5:0]=0-23 [21:16] read-write ALM_HOUR_EN Alarm hour enable: 0=ignore, 1=match [23:23] read-write ALM_DAY Alarm Day of the week in BCD, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended [26:24] read-write ALM_DAY_EN Alarm Day of the Week enable: 0=ignore, 1=match [31:31] read-write ALM1_DATE Alarm 1 Day of Month, Month 0x20 32 read-write 0x101 0x80009FBF ALM_DATE Alarm Day of the Month in BCD, 1-31 Leap Year corrected [5:0] read-write ALM_DATE_EN Alarm Day of the Month enable: 0=ignore, 1=match [7:7] read-write ALM_MON Alarm Month in BCD, 1-12 [12:8] read-write ALM_MON_EN Alarm Month enable: 0=ignore, 1=match [15:15] read-write ALM_EN Master enable for alarm 1. 0: Alarm 1 is disabled. Fields for date and time are ignored. 1: Alarm 1 is enabled. If none of the date and time fields are enabled, then this alarm triggers once every second. [31:31] read-write ALM2_TIME Alarm 2 Seconds, Minute, Hours, Day of Week 0x24 32 read-write 0x1000000 0x87BFFFFF ALM_SEC Alarm seconds in BCD, 0-59 [6:0] read-write ALM_SEC_EN Alarm second enable: 0=ignore, 1=match [7:7] read-write ALM_MIN Alarm minutes in BCD, 0-59 [14:8] read-write ALM_MIN_EN Alarm minutes enable: 0=ignore, 1=match [15:15] read-write ALM_HOUR Alarm hours in BCD, value depending on 12/24HR mode 12HR: [5]:0=AM, 1=PM, [4:0]=1-12 24HR: [5:0]=0-23 [21:16] read-write ALM_HOUR_EN Alarm hour enable: 0=ignore, 1=match [23:23] read-write ALM_DAY Alarm Day of the week in BCD, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended [26:24] read-write ALM_DAY_EN Alarm Day of the Week enable: 0=ignore, 1=match [31:31] read-write ALM2_DATE Alarm 2 Day of Month, Month 0x28 32 read-write 0x101 0x80009FBF ALM_DATE Alarm Day of the Month in BCD, 1-31 Leap Year corrected [5:0] read-write ALM_DATE_EN Alarm Day of the Month enable: 0=ignore, 1=match [7:7] read-write ALM_MON Alarm Month in BCD, 1-12 [12:8] read-write ALM_MON_EN Alarm Month enable: 0=ignore, 1=match [15:15] read-write ALM_EN Master enable for alarm 2. 0: Alarm 2 is disabled. Fields for date and time are ignored. 1: Alarm 2 is enabled. If none of the date and time fields are enabled, then this alarm triggers once every second. [31:31] read-write INTR Interrupt request register 0x2C 32 read-write 0x0 0x7 ALARM1 Alarm 1 Interrupt [0:0] read-write ALARM2 Alarm 2 Interrupt [1:1] read-write CENTURY Century overflow interrupt [2:2] read-write INTR_SET Interrupt set request register 0x30 32 read-write 0x0 0x7 ALARM1 Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write ALARM2 Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write CENTURY Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write INTR_MASK Interrupt mask register 0x34 32 read-write 0x0 0x7 ALARM1 Mask bit for corresponding bit in interrupt request register. [0:0] read-write ALARM2 Mask bit for corresponding bit in interrupt request register. [1:1] read-write CENTURY Mask bit for corresponding bit in interrupt request register. [2:2] read-write INTR_MASKED Interrupt masked request register 0x38 32 read-only 0x0 0x7 ALARM1 Logical and of corresponding request and mask bits. [0:0] read-only ALARM2 Logical and of corresponding request and mask bits. [1:1] read-only CENTURY Logical and of corresponding request and mask bits. [2:2] read-only OSCCNT 32kHz oscillator counter 0x3C 32 read-only 0x0 0xFF CNT32KHZ 32kHz oscillator count (msb=128Hz), calibration can cause bit 6 to skip. Reset when RTC_TIME.RTC_SEC fields is written. [7:0] read-only TICKS 128Hz tick counter 0x40 32 read-only 0x0 0x3F CNT128HZ 128Hz counter (msb=2Hz) When SECONDS is written this field will be reset. [5:0] read-only PMIC_CTL PMIC control register 0x44 32 read-write 0xA0000000 0xE001FF00 UNLOCK This byte must be set to 0x3A for PMIC to be disabled. When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN. Do not change PMIC_EN in the same write cycle as setting/clearing the UNLOCK code; do these in separate write cycles. [15:8] read-write POLARITY 0: Pin input of 0 will set PMIC_EN. 1: Pin input of 1 will set PMIC_EN. [16:16] read-write PMIC_EN_OUTEN Output enable for the output driver in the PMIC_EN pad. 0: Output pad is tristate for PMIC_EN pin. This can allow this pin to be used for another purpose. Tristate condition is kept only if the UNLOCK key (0x3A) is present 1: Output pad is enabled for PMIC_EN pin. [29:29] read-write PMIC_ALWAYSEN Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware. 0: Normal operation, PMIC_EN and PMIC_OUTEN work as described 1: PMIC_EN and PMIC_OUTEN are ignored and the output pad is forced enabled. Note: This bit is a write-once bit until the next backup reset. [30:30] read-write PMIC_EN Enable for external PMIC that supplies vddd (if present). This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0. When PMIC_EN=0, the system functions normally until vddd is no longer present (OFF w/Backup mode). Firmware can set this bit, if it does so before vddd is actually removed. This bit is also set by any RTC alarm or PMIC pin wakeup event regardless of UNLOCK setting. [31:31] read-write RESET Backup reset register 0x48 32 read-write 0x0 0x80000000 RESET Writing 1 to this register resets the backup logic. Hardware clears it when the reset is complete. After setting this register, firmware should confirm it reads as 0 before attempting to write other backup registers. [31:31] read-write 64 4 BREG[%s] Backup register region 0x1000 32 read-write 0x0 0xFFFFFFFF BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. [31:0] read-write TRIM Trim Register 0xFF00 32 read-write 0x0 0x3F TRIM WCO trim [5:0] read-write DW0 Datawire Controller DW 0x40280000 0 4096 registers CTL Control 0x0 32 read-write 0x0 0x80000000 ENABLED IP enable: '0': Disabled. Disabling the IP activates the IP's Active logic reset: Active logic and non-retention MMIO registers are reset (retention MMIO registers are not affected). '1': Enabled. [31:31] read-write STATUS Status 0x4 32 read-only 0x0 0x80700000 P Active channel, user/privileged access control: '0': user mode. '1': privileged mode. [0:0] read-only NS Active channel, secure/non-secure access control: '0': secure. '1': non-secure. [1:1] read-only B Active channel, non-bufferable/bufferable access control: '0': non-bufferable '1': bufferable. [2:2] read-only PC Active channel protection context. [7:4] read-only CH_IDX Active channel index. [12:8] read-only PRIO Active channel priority. [17:16] read-only PREEMPTABLE Active channel preemptable. [18:18] read-only STATE State of the DW controller. '0': Default/inactive state. '1': Loading descriptor. '2': Loading data element from source location. '3': Storing data element to destination location. '4': Update of active control information (e.g. source and destination addresses). '5': Wait for trigger de-activation. [22:20] read-only ACTIVE Active channel present: '0': No. '1': Yes. [31:31] read-only PENDING Pending channels 0x8 32 read-only 0x0 0xFFFFFFFF CH_PENDING Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s)). [31:0] read-only STATUS_INTR System interrupt control 0x10 32 read-only 0x0 0xFFFFFFFF CH Reflects the INTR.CH bit fields of all channels. [31:0] read-only STATUS_INTR_MASKED Status of interrupts masked 0x14 32 read-only 0x0 0xFFFFFFFF CH Reflects the INTR_MASKED.CH bit fields of all channels. [31:0] read-only ACT_DESCR_CTL Active descriptor control 0x20 32 read-only 0x0 0x0 DATA Copy of DESCR_CTL of the currently active descriptor. [31:0] read-only ACT_DESCR_SRC Active descriptor source 0x24 32 read-only 0x0 0x0 DATA Copy of DESCR_SRC of the currently active descriptor. [31:0] read-only ACT_DESCR_DST Active descriptor destination 0x28 32 read-only 0x0 0x0 DATA Copy of DESCR_DST of the currently active descriptor. [31:0] read-only ACT_DESCR_X_CTL Active descriptor X loop control 0x30 32 read-only 0x0 0x0 DATA Copy of DESCR_X_CTL of the currently active descriptor. [31:0] read-only ACT_DESCR_Y_CTL Active descriptor Y loop control 0x34 32 read-only 0x0 0x0 DATA Copy of DESCR_Y_CTL of the currently active descriptor. [31:0] read-only ACT_DESCR_NEXT_PTR Active descriptor next pointer 0x38 32 read-only 0x0 0x0 ADDR Copy of DESCR_NEXT_PTR of the currently active descriptor. [31:2] read-only ACT_SRC Active source 0x40 32 read-only 0x0 0x0 SRC_ADDR Current address of source location. [31:0] read-only ACT_DST Active destination 0x44 32 read-only 0x0 0x0 DST_ADDR Current address of destination location. [31:0] read-only 16 32 CH_STRUCT[%s] DW channel structure 0x00000800 CH_CTL Channel control 0x0 32 read-write 0x2 0x800700F7 P User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). [0:0] read-write NS Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). [1:1] read-write B Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). [2:2] read-write PC Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context. [7:4] read-write PRIO Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, roundrobin arbitration is applied. Roundrobin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group). [17:16] read-write PREEMPTABLE Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higer priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated. [18:18] read-write ENABLED Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pensding channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE). [31:31] read-write CH_STATUS Channel status 0x4 32 read-only 0x0 0x0 INTR_CAUSE Specifies the source of the interrupt cause: '0': NO_INTR '1': COMPLETION '2': SRC_BUS_ERROR '3': DST_BUS_ERROR '4': SRC_MISAL '5': DST_MISAL '6': CURR_PTR_NULL '7': ACTIVE_CH_DISABLED '8': DESCR_BUS_ERROR '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '1', '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0'). [3:0] read-only CH_IDX Channel current indices 0x8 32 read-write 0x0 0x0 X_IDX Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR. [7:0] read-write Y_IDX Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR. [15:8] read-write CH_CURR_PTR Channel current descriptor pointer 0xC 32 read-write 0x0 0x0 ADDR Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'. [31:2] read-write INTR Interrupt 0x10 32 read-write 0x0 0x1 CH Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit. [0:0] read-write INTR_SET Interrupt set 0x14 32 read-write 0x0 0x1 CH Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect). [0:0] read-write INTR_MASK Interrupt mask 0x18 32 read-write 0x0 0x1 CH Mask for corresponding field in INTR register. [0:0] read-write INTR_MASKED Interrupt masked 0x1C 32 read-only 0x0 0x1 CH Logical and of corresponding INTR and INTR_MASK fields. [0:0] read-only DW1 0x40281000 EFUSE EFUSE MXS40 registers 0x402C0000 0 128 registers CTL Control 0x0 32 read-write 0x0 0x80000000 ENABLED IP enable: '0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. '1': Enabled. [31:31] read-write CMD Command 0x10 32 read-write 0x1 0x800F1F71 BIT_DATA Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR, BYTE_ADDR, and MACRO_ADDR fields. This bit is a don't care for the MXS40 Macro. [0:0] read-write BIT_ADDR Bit address. This field specifies a bit within a Byte. [6:4] read-write BYTE_ADDR Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B). [12:8] read-write MACRO_ADDR Macro address. This field specifies an eFUSE macro. [19:16] read-write START FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed. Note: it is good practice to verify the result of a program operation by reading back a programmed eFUSE memory location. Programming can only change an eFUSE memory bit from '0' to '1'; i.e. a programming operation is a 'one-off' operation for each eFUSE memory bit: once a bit is changed to '1', it can NEVER be changed back to '0' as a hardware fuse is blown. Programming a memory bit to '1' requires blowing a fuse and requires an eFUSE macro operation. Therefore, this programmiong operation takes time (as specified by the SEQ_PROGRAM_CTL reguisters). Programming amemory bit to '0' does not require an eFUSE macro operation (it is the default eFUSE macro state). Therefore, this programming operation is almost instantaneous. Note: during a program operation, a read operation can not be performed. An AHB-Lite read transfer to the eFUSE memory during a program operation results in an AHB-Lite bus error. [31:31] read-write SEQ_DEFAULT Sequencer Default value 0x20 32 read-write 0x1D0000 0x7F0000 STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write SEQ_READ_CTL_0 Sequencer read control 0 0x40 32 read-write 0x80560001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_1 Sequencer read control 1 0x44 32 read-write 0x540004 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_2 Sequencer read control 2 0x48 32 read-write 0x560001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_3 Sequencer read control 3 0x4C 32 read-write 0x540003 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_4 Sequencer read control 4 0x50 32 read-write 0x80150001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_5 Sequencer read control 5 0x54 32 read-write 0x310004 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_0 Sequencer program control 0 0x60 32 read-write 0x200001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_1 Sequencer program control 1 0x64 32 read-write 0x220020 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_2 Sequencer program control 2 0x68 32 read-write 0x200001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_3 Sequencer program control 3 0x6C 32 read-write 0x310005 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_4 Sequencer program control 4 0x70 32 read-write 0x80350006 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_5 Sequencer program control 5 0x74 32 read-write 0x803D0019 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write PROFILE Energy Profiler IP 0x402D0000 0 65536 registers CTL Profile control 0x0 32 read-write 0x0 0x80000001 WIN_MODE Specifies the profiling time window mode: '0': Start / stop mode. The profiling time window is started when a rising edge of the start trigger signal occurs and stopped when a rising edge of the stop trigger signal occurs. In case both rising edges (of start and stop trigger signals) occur in the same cycle, the profiling time window is stopped. '1': Enable mode. The profiling time window is active as long as the start 'trigger' signal is active. The stop trigger signal has no effect. [0:0] read-write ENABLED Enables the profiling block: '0': Disabled. '1': Enabled. [31:31] read-write STATUS Profile status 0x4 32 read-only 0x0 0x1 WIN_ACTIVE Indicates if the profiling time window is active. '0': Not active. '1': Active. [0:0] read-only CMD Profile command 0x10 32 read-write 0x0 0x103 START_TR Software start trigger for the profiling time window. When written with '1', the profiling time window is started. Can only be used in start / stop mode (PROFILE_WIN_MODE=0). Has no effect in enable mode (PROFILE_WIN_MODE=1). [0:0] read-write STOP_TR Software stop trigger for the profiling time window. When written with '1', the profiling time window is stopped. Can only be used in start / stop mode (PROFILE_WIN_MODE=0). Has no effect in enable mode (PROFILE_WIN_MODE=1). [1:1] read-write CLR_ALL_CNT Counter clear. When written with '1', all profiling counter registers are cleared to 0x00. [8:8] read-write INTR Profile interrupt 0x7C0 32 read-write 0x0 0xFFFFFFFF CNT_OVFLW This interrupt cause field is activated (HW sets the field to '1') when an profiling counter overflow (from 0xFFFFFFFF to 0x00000000) is captured. There is one bit per profling counter. SW writes a '1' to a bit of this field to clear this bit to '0' (writing 0xFFFFFFFF clears all interrupt causes to '0'). [31:0] read-write INTR_SET Profile interrupt set 0x7C4 32 read-write 0x0 0xFFFFFFFF CNT_OVFLW SW writes a '1' to a bit of this field to set the corresponding bit in the INTR register. [31:0] read-write INTR_MASK Profile interrupt mask 0x7C8 32 read-write 0x0 0xFFFFFFFF CNT_OVFLW Mask bit for corresponding field in the INTR register. [31:0] read-write INTR_MASKED Profile interrupt masked 0x7CC 32 read-only 0x0 0xFFFFFFFF CNT_OVFLW Logical and of corresponding INTR and INTR_MASK fields. [31:0] read-only 8 16 CNT_STRUCT[%s] Profile counter structure 0x00000800 CTL Profile counter configuration 0x0 32 read-write 0x0 0x807F0071 CNT_DURATION This field specifies if events (edges) or a duration of the monitor signal is counted. '0': Events are monitored. An edge detection is done. All edges of the selected monitor signal are counted. '1': A duration is monitored. No edge detection is done. The monitored signal is taken as a (high active) level signal for enabling the profiling counter. Note: All monitor signals which only can represent events are edge encoded in hardware, therefore a selection of CTL.CNT_DURATION=1 will not produce meaningful results. [0:0] read-write REF_CLK_SEL This field specifies the reference clock used for a counting time base when counting durations. Has no effect when CTL.CNT_DURATION=0. [6:4] read-write CLK_TIMER Timer clock (divided or undivided high frequency clock, e.g. from IMO). Selection is done in SRSS register CLK_TIMER_CTL.TIMER_SEL. 0 CLK_IMO IMO - Internal Main Oscillator 1 CLK_ECO ECO - External-Crystal Oscillator 2 CLK_LF Low frequency clock (ILO, WCO or ALTLF). Selection is done in SRSS register CLK_SELECT.LFCLK_SEL. 3 CLK_HF High frequuency clock ('clk_hfx'). 4 CLK_PERI Peripheral clock ('clk_peri'). 5 RSVD_6 N/A 6 RSVD_7 N/A 7 MON_SEL This field specifies the montior input signal to be observed by the profiling counter. The monitor signals are product specific, see product definition spreadsheet tab 'Monitor' for details. [22:16] read-write ENABLED Enables the profiling counter: '0': Disabled. '1': Enabled. [31:31] read-write CNT Profile counter value 0x8 32 read-write 0x0 0xFFFFFFFF CNT This field shows / specifies the actual value of the profiling counter. It allows reading as well as writing the profiling counter. [31:0] read-write HSIOM High Speed IO Matrix (HSIOM) 0x40310000 0 16384 registers 15 16 PRT[%s] HSIOM port registers 0x00000000 PORT_SEL0 Port selection 0 0x0 32 read-write 0x0 0x1F1F1F1F IO0_SEL Selects connection for IO pin 0 route. [4:0] read-write GPIO GPIO controls 'out' 0 GPIO_DSI GPIO controls 'out', DSI controls 'output enable' 1 DSI_DSI DSI controls 'out' and 'output enable' 2 DSI_GPIO DSI controls 'out', GPIO controls 'output enable' 3 AMUXA Analog mux bus A 4 AMUXB Analog mux bus B 5 AMUXA_DSI Analog mux bus A, DSI control 6 AMUXB_DSI Analog mux bus B, DSI control 7 ACT_0 Active functionality 0 8 ACT_1 Active functionality 1 9 ACT_2 Active functionality 2 10 ACT_3 Active functionality 3 11 DS_0 DeepSleep functionality 0 12 DS_1 DeepSleep functionality 1 13 DS_2 DeepSleep functionality 2 14 DS_3 DeepSleep functionality 3 15 ACT_4 Active functionality 4 16 ACT_5 Active functionality 5 17 ACT_6 Active functionality 6 18 ACT_7 Active functionality 7 19 ACT_8 Active functionality 8 20 ACT_9 Active functionality 9 21 ACT_10 Active functionality 10 22 ACT_11 Active functionality 11 23 ACT_12 Active functionality 12 24 ACT_13 Active functionality 13 25 ACT_14 Active functionality 14 26 ACT_15 Active functionality 15 27 DS_4 DeepSleep functionality 4 28 DS_5 DeepSleep functionality 5 29 DS_6 DeepSleep functionality 6 30 DS_7 DeepSleep functionality 7 31 IO1_SEL Selects connection for IO pin 1 route. [12:8] read-write IO2_SEL Selects connection for IO pin 2 route. [20:16] read-write IO3_SEL Selects connection for IO pin 3 route. [28:24] read-write PORT_SEL1 Port selection 1 0x4 32 read-write 0x0 0x1F1F1F1F IO4_SEL Selects connection for IO pin 4 route. See PORT_SEL0 for connection details. [4:0] read-write IO5_SEL Selects connection for IO pin 5 route. [12:8] read-write IO6_SEL Selects connection for IO pin 6 route. [20:16] read-write IO7_SEL Selects connection for IO pin 7 route. [28:24] read-write 64 4 AMUX_SPLIT_CTL[%s] AMUX splitter cell control 0x2000 32 read-write 0x0 0x77 SWITCH_AA_SL T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed. [0:0] read-write SWITCH_AA_SR T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed. [1:1] read-write SWITCH_AA_S0 T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed. [2:2] read-write SWITCH_BB_SL T-switch control for Left AMUXBUSB switch. [4:4] read-write SWITCH_BB_SR T-switch control for Right AMUXBUSB switch. [5:5] read-write SWITCH_BB_S0 T-switch control for AMUXBUSB vssa/ground switch. [6:6] read-write GPIO GPIO port control/configuration 0x40320000 0 65536 registers 15 128 PRT[%s] GPIO port registers 0x00000000 OUT Port output data register 0x0 32 read-write 0x0 0xFF OUT0 IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1' [0:0] read-write OUT1 IO output data for pin 1 [1:1] read-write OUT2 IO output data for pin 2 [2:2] read-write OUT3 IO output data for pin 3 [3:3] read-write OUT4 IO output data for pin 4 [4:4] read-write OUT5 IO output data for pin 5 [5:5] read-write OUT6 IO output data for pin 6 [6:6] read-write OUT7 IO output data for pin 7 [7:7] read-write OUT_CLR Port output data set register 0x4 32 read-write 0x0 0xFF OUT0 IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'. [0:0] read-write OUT1 IO clear output for pin 1 [1:1] read-write OUT2 IO clear output for pin 2 [2:2] read-write OUT3 IO clear output for pin 3 [3:3] read-write OUT4 IO clear output for pin 4 [4:4] read-write OUT5 IO clear output for pin 5 [5:5] read-write OUT6 IO clear output for pin 6 [6:6] read-write OUT7 IO clear output for pin 7 [7:7] read-write OUT_SET Port output data clear register 0x8 32 read-write 0x0 0xFF OUT0 IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'. [0:0] read-write OUT1 IO set output for pin 1 [1:1] read-write OUT2 IO set output for pin 2 [2:2] read-write OUT3 IO set output for pin 3 [3:3] read-write OUT4 IO set output for pin 4 [4:4] read-write OUT5 IO set output for pin 5 [5:5] read-write OUT6 IO set output for pin 6 [6:6] read-write OUT7 IO set output for pin 7 [7:7] read-write OUT_INV Port output data invert register 0xC 32 read-write 0x0 0xFF OUT0 IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0'). [0:0] read-write OUT1 IO invert output for pin 1 [1:1] read-write OUT2 IO invert output for pin 2 [2:2] read-write OUT3 IO invert output for pin 3 [3:3] read-write OUT4 IO invert output for pin 4 [4:4] read-write OUT5 IO invert output for pin 5 [5:5] read-write OUT6 IO invert output for pin 6 [6:6] read-write OUT7 IO invert output for pin 7 [7:7] read-write IN Port input state register 0x10 32 read-only 0x0 0x1FF IN0 IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin. [0:0] read-only IN1 IO pin state for pin 1 [1:1] read-only IN2 IO pin state for pin 2 [2:2] read-only IN3 IO pin state for pin 3 [3:3] read-only IN4 IO pin state for pin 4 [4:4] read-only IN5 IO pin state for pin 5 [5:5] read-only IN6 IO pin state for pin 6 [6:6] read-only IN7 IO pin state for pin 7 [7:7] read-only FLT_IN Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register. [8:8] read-only INTR Port interrupt status register 0x14 32 read-write 0x0 0x1FF01FF EDGE0 Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin. [0:0] read-write EDGE1 Edge detect for IO pin 1 [1:1] read-write EDGE2 Edge detect for IO pin 2 [2:2] read-write EDGE3 Edge detect for IO pin 3 [3:3] read-write EDGE4 Edge detect for IO pin 4 [4:4] read-write EDGE5 Edge detect for IO pin 5 [5:5] read-write EDGE6 Edge detect for IO pin 6 [6:6] read-write EDGE7 Edge detect for IO pin 7 [7:7] read-write FLT_EDGE Edge detected on filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-write IN_IN0 IO pin state for pin 0 [16:16] read-only IN_IN1 IO pin state for pin 1 [17:17] read-only IN_IN2 IO pin state for pin 2 [18:18] read-only IN_IN3 IO pin state for pin 3 [19:19] read-only IN_IN4 IO pin state for pin 4 [20:20] read-only IN_IN5 IO pin state for pin 5 [21:21] read-only IN_IN6 IO pin state for pin 6 [22:22] read-only IN_IN7 IO pin state for pin 7 [23:23] read-only FLT_IN_IN Filtered pin state for pin selected by INTR_CFG.FLT_SEL [24:24] read-only INTR_MASK Port interrupt mask register 0x18 32 read-write 0x0 0x1FF EDGE0 Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled [0:0] read-write EDGE1 Masks edge interrupt on IO pin 1 [1:1] read-write EDGE2 Masks edge interrupt on IO pin 2 [2:2] read-write EDGE3 Masks edge interrupt on IO pin 3 [3:3] read-write EDGE4 Masks edge interrupt on IO pin 4 [4:4] read-write EDGE5 Masks edge interrupt on IO pin 5 [5:5] read-write EDGE6 Masks edge interrupt on IO pin 6 [6:6] read-write EDGE7 Masks edge interrupt on IO pin 7 [7:7] read-write FLT_EDGE Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-write INTR_MASKED Port interrupt masked status register 0x1C 32 read-only 0x0 0x1FF EDGE0 Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU [0:0] read-only EDGE1 Edge detected and masked on IO pin 1 [1:1] read-only EDGE2 Edge detected and masked on IO pin 2 [2:2] read-only EDGE3 Edge detected and masked on IO pin 3 [3:3] read-only EDGE4 Edge detected and masked on IO pin 4 [4:4] read-only EDGE5 Edge detected and masked on IO pin 5 [5:5] read-only EDGE6 Edge detected and masked on IO pin 6 [6:6] read-only EDGE7 Edge detected and masked on IO pin 7 [7:7] read-only FLT_EDGE Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-only INTR_SET Port interrupt set register 0x20 32 read-write 0x0 0x1FF EDGE0 Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set [0:0] read-write EDGE1 Sets edge detect interrupt for IO pin 1 [1:1] read-write EDGE2 Sets edge detect interrupt for IO pin 2 [2:2] read-write EDGE3 Sets edge detect interrupt for IO pin 3 [3:3] read-write EDGE4 Sets edge detect interrupt for IO pin 4 [4:4] read-write EDGE5 Sets edge detect interrupt for IO pin 5 [5:5] read-write EDGE6 Sets edge detect interrupt for IO pin 6 [6:6] read-write EDGE7 Sets edge detect interrupt for IO pin 7 [7:7] read-write FLT_EDGE Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-write INTR_CFG Port interrupt configuration register 0x24 32 read-write 0x0 0x1FFFFF EDGE0_SEL Sets which edge will trigger an IRQ for IO pin 0 [1:0] read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 EDGE1_SEL Sets which edge will trigger an IRQ for IO pin 1 [3:2] read-write EDGE2_SEL Sets which edge will trigger an IRQ for IO pin 2 [5:4] read-write EDGE3_SEL Sets which edge will trigger an IRQ for IO pin 3 [7:6] read-write EDGE4_SEL Sets which edge will trigger an IRQ for IO pin 4 [9:8] read-write EDGE5_SEL Sets which edge will trigger an IRQ for IO pin 5 [11:10] read-write EDGE6_SEL Sets which edge will trigger an IRQ for IO pin 6 [13:12] read-write EDGE7_SEL Sets which edge will trigger an IRQ for IO pin 7 [15:14] read-write FLT_EDGE_SEL Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL [17:16] read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 FLT_SEL Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt. [20:18] read-write CFG Port configuration register 0x28 32 read-write 0x0 0xFFFFFFFF DRIVE_MODE0 The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell. [2:0] read-write HIGHZ Output buffer is off creating a high impedance input D_OUT = '0': High Impedance D_OUT = '1': High Impedance 0 RSVD N/A 1 PULLUP Resistive pull up For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Weak/resistive pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull up D_OUT = '1': Weak/resistive pull up 2 PULLDOWN Resistive pull down For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Weak/resistive pull down 3 OD_DRIVESLOW Open drain, drives low For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': High Impedance When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance 4 OD_DRIVESHIGH Open drain, drives high For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': High Impedance D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance 5 STRONG Strong D_OUTput buffer For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance 6 PULLUP_DOWN Pull up or pull down For GPIO & UDB/DSI peripherals: When D_OUT_EN = '0': GPIO_DSI_OUT = '0': Weak/resistive pull down GPIO_DSI_OUT = '1': Weak/resistive pull up where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT. For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Weak/resistive pull up 7 IN_EN0 Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled [3:3] read-write DRIVE_MODE1 The GPIO drive mode for IO pin 1 [6:4] read-write IN_EN1 Enables the input buffer for IO pin 1 [7:7] read-write DRIVE_MODE2 The GPIO drive mode for IO pin 2 [10:8] read-write IN_EN2 Enables the input buffer for IO pin 2 [11:11] read-write DRIVE_MODE3 The GPIO drive mode for IO pin 3 [14:12] read-write IN_EN3 Enables the input buffer for IO pin 3 [15:15] read-write DRIVE_MODE4 The GPIO drive mode for IO pin4 [18:16] read-write IN_EN4 Enables the input buffer for IO pin 4 [19:19] read-write DRIVE_MODE5 The GPIO drive mode for IO pin 5 [22:20] read-write IN_EN5 Enables the input buffer for IO pin 5 [23:23] read-write DRIVE_MODE6 The GPIO drive mode for IO pin 6 [26:24] read-write IN_EN6 Enables the input buffer for IO pin 6 [27:27] read-write DRIVE_MODE7 The GPIO drive mode for IO pin 7 [30:28] read-write IN_EN7 Enables the input buffer for IO pin 7 [31:31] read-write CFG_IN Port input buffer configuration register 0x2C 32 read-write 0x0 0xFF VTRIP_SEL0_0 Configures the pin 0 input buffer mode (trip points and hysteresis) [0:0] read-write CMOS Input buffer compatible with CMOS and I2C interfaces 0 TTL Input buffer compatible with TTL and MediaLB interfaces 1 VTRIP_SEL1_0 Configures the pin 1 input buffer mode (trip points and hysteresis) [1:1] read-write VTRIP_SEL2_0 Configures the pin 2 input buffer mode (trip points and hysteresis) [2:2] read-write VTRIP_SEL3_0 Configures the pin 3 input buffer mode (trip points and hysteresis) [3:3] read-write VTRIP_SEL4_0 Configures the pin 4 input buffer mode (trip points and hysteresis) [4:4] read-write VTRIP_SEL5_0 Configures the pin 5 input buffer mode (trip points and hysteresis) [5:5] read-write VTRIP_SEL6_0 Configures the pin 6 input buffer mode (trip points and hysteresis) [6:6] read-write VTRIP_SEL7_0 Configures the pin 7 input buffer mode (trip points and hysteresis) [7:7] read-write CFG_OUT Port output buffer configuration register 0x30 32 read-write 0x0 0xFFFF00FF SLOW0 Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate [0:0] read-write SLOW1 Enables slow slew rate for IO pin 1 [1:1] read-write SLOW2 Enables slow slew rate for IO pin 2 [2:2] read-write SLOW3 Enables slow slew rate for IO pin 3 [3:3] read-write SLOW4 Enables slow slew rate for IO pin 4 [4:4] read-write SLOW5 Enables slow slew rate for IO pin 5 [5:5] read-write SLOW6 Enables slow slew rate for IO pin 6 [6:6] read-write SLOW7 Enables slow slew rate for IO pin 7 [7:7] read-write DRIVE_SEL0 Sets the GPIO drive strength for IO pin 0 [17:16] read-write FULL_DRIVE Full drive strength: GPIO drives current at its max rated spec. 0 ONE_HALF_DRIVE 1/2 drive strength: GPIO drives current at 1/2 of its max rated spec 1 ONE_QUARTER_DRIVE 1/4 drive strength: GPIO drives current at 1/4 of its max rated spec. 2 ONE_EIGHTH_DRIVE 1/8 drive strength: GPIO drives current at 1/8 of its max rated spec. 3 DRIVE_SEL1 Sets the GPIO drive strength for IO pin 1 [19:18] read-write DRIVE_SEL2 Sets the GPIO drive strength for IO pin 2 [21:20] read-write DRIVE_SEL3 Sets the GPIO drive strength for IO pin 3 [23:22] read-write DRIVE_SEL4 Sets the GPIO drive strength for IO pin 4 [25:24] read-write DRIVE_SEL5 Sets the GPIO drive strength for IO pin 5 [27:26] read-write DRIVE_SEL6 Sets the GPIO drive strength for IO pin 6 [29:28] read-write DRIVE_SEL7 Sets the GPIO drive strength for IO pin 7 [31:30] read-write CFG_SIO Port SIO configuration register 0x34 32 read-write 0x0 0xFFFFFFFF VREG_EN01 The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used. [0:0] read-write IBUF_SEL01 N/A [1:1] read-write VTRIP_SEL01 N/A [2:2] read-write VREF_SEL01 N/A [4:3] read-write VOH_SEL01 Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. In differential input buffer mode (IBUF01_SEL = '1'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -> Trip point=50 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=Vohref (buffered) c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -> Trip point=40 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=0.5*Vohref c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=0.5*Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. [7:5] read-write VREG_EN23 N/A [8:8] read-write IBUF_SEL23 N/A [9:9] read-write VTRIP_SEL23 N/A [10:10] read-write VREF_SEL23 N/A [12:11] read-write VOH_SEL23 N/A [15:13] read-write VREG_EN45 N/A [16:16] read-write IBUF_SEL45 N/A [17:17] read-write VTRIP_SEL45 N/A [18:18] read-write VREF_SEL45 N/A [20:19] read-write VOH_SEL45 N/A [23:21] read-write VREG_EN67 N/A [24:24] read-write IBUF_SEL67 N/A [25:25] read-write VTRIP_SEL67 N/A [26:26] read-write VREF_SEL67 N/A [28:27] read-write VOH_SEL67 N/A [31:29] read-write CFG_IN_GPIO5V Port GPIO5V input buffer configuration register 0x3C 32 read-write 0x0 0xFF VTRIP_SEL0_1 Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. 0: input buffer is not compatible with automative. 1: input buffer is compatible with automative. Use CFG_IN.VTRIP_SEL0_0 fieds set as CMOS only when this bit needs to be set. [0:0] read-write DISABLE Input buffer not compatible with automotive (elevated Vil) interfaces. 0 AUTO Input buffer compatible with automotive (elevated Vil) interfaces. 1 VTRIP_SEL1_1 Input buffer compatible with automotive (elevated Vil) interfaces. [1:1] read-write VTRIP_SEL2_1 Input buffer compatible with automotive (elevated Vil) interfaces. [2:2] read-write VTRIP_SEL3_1 Input buffer compatible with automotive (elevated Vil) interfaces. [3:3] read-write VTRIP_SEL4_1 Input buffer compatible with automotive (elevated Vil) interfaces. [4:4] read-write VTRIP_SEL5_1 Input buffer compatible with automotive (elevated Vil) interfaces. [5:5] read-write VTRIP_SEL6_1 Input buffer compatible with automotive (elevated Vil) interfaces. [6:6] read-write VTRIP_SEL7_1 Input buffer compatible with automotive (elevated Vil) interfaces. [7:7] read-write INTR_CAUSE0 Interrupt port cause register 0 0x4000 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PRT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only INTR_CAUSE1 Interrupt port cause register 1 0x4004 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to deternine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only INTR_CAUSE2 Interrupt port cause register 2 0x4008 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to deternine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only INTR_CAUSE3 Interrupt port cause register 3 0x400C 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to deternine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only VDD_ACTIVE Extern power supply detection register 0x4010 32 read-only 0x0 0xC000FFFF VDDIO_ACTIVE Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the device (supplies are numbered 0..n-1). Note that VDDIO supplies have basic (crude) supply detectors only. If separate, robust, brown-out detection is desired on IO supplies, on-chip or off-chip analog resources need to provide it. For these bits to work reliable, the supply must be within valid spec range (per datasheet) or held at ground. Any in-between voltage has an undefined result. '0': Supply is not present '1': Supply is present When multiple VDDIO supplies are present, they will be assigned in alphanumeric ascending order to these bits during implementation. For example 'vddusb, vddio_0, vddio_a, vbackup, vddio_r, vddio_1' are present then they will be assigned to these bits as below: 0: vbackup, 1: vddio_0, 2: vddio_1, 3: vddio_a, 4: vddio_r, 5: vddusb' [15:0] read-only VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-only VDDD_ACTIVE This bit indicates presence of the VDDD supply. This bit will always read-back 1. The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in certain test-modes to observe the brown-out detector status.) [31:31] read-only VDD_INTR Supply detection interrupt register 0x4014 32 read-write 0x0 0xC000FFFF VDDIO_ACTIVE Supply state change detected. '0': No change to supply detected '1': Change to supply detected [15:0] read-write VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-write VDDD_ACTIVE The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'. [31:31] read-write VDD_INTR_MASK Supply detection interrupt mask register 0x4018 32 read-write 0x0 0xC000FFFF VDDIO_ACTIVE Masks supply interrupt on VDDIO. '0': VDDIO interrupt forwarding disabled '1': VDDIO interrupt forwarding enabled [15:0] read-write VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-write VDDD_ACTIVE Same as VDDIO_ACTIVE for the digital supply VDDD. [31:31] read-write VDD_INTR_MASKED Supply detection interrupt masked register 0x401C 32 read-only 0x0 0xC000FFFF VDDIO_ACTIVE Supply transistion detected AND masked '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU [15:0] read-only VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-only VDDD_ACTIVE Same as VDDIO_ACTIVE for the digital supply VDDD. [31:31] read-only VDD_INTR_SET Supply detection interrupt set register 0x4020 32 read-write 0x0 0xC000FFFF VDDIO_ACTIVE Sets supply interrupt. '0': Interrupt state not affected '1': Interrupt set [15:0] read-write VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-write VDDD_ACTIVE Same as VDDIO_ACTIVE for the digital supply VDDD. [31:31] read-write SMARTIO Programmable IO configuration 0x40330000 0 65536 registers 10 256 PRT[%s] Programmable IO port registers 0x00000000 CTL Control register 0x0 32 read-write 0x2001400 0x82001F00 BYPASS Bypass of the programmable IO, one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1', this field is used. When ENABLED is '0', this field is NOT used and SMARTIO fabric is always bypassed. '0': No bypass (programmable SMARTIO fabric is exposed). '1': Bypass (programmable SMARTIOIO fabric is hidden). [7:0] read-write CLOCK_SRC Clock ('clk_fabric') and reset ('rst_fabric_n') source selection: '0': io_data_in[0]/'1'. ... '7': io_data_in[7]/'1'. '8': chip_data[0]/'1'. ... '15': chip_data[7]/'1'. '16': clk_smartio/rst_sys_act_n. Used for both Active functionality synchronous logic on 'clk_smartio'. This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. '17': clk_smartio/rst_sys_dpslp_n. Used for both DeepSleep functionality synchronous logic on 'clk_smartio' (note that 'clk_smartio' is NOT available in DeepSleep and Hibernate power modes). This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. '18': Same as '17'. Note that the M0S8 SMARTIO version used the Hibernate reset for this value, but the MXS40 SMARTIO version does not support Hibernate functionality. '19': clk_lf/rst_lf_dpslp_n (note that 'clk_lf' is available in DeepSleep power mode). This selection is intended for synchronous operation on'clk_lf'. Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to other 'clk_lf' clocked elements. '20'-'30': Clock source is constant '0'. Any of these clock sources should be selected when the IP is disabled to ensure low power consumption. '31': asynchronous mode/'1'. Select this when clockless operation is configured. NOTE: Two positive edges of the selected clock are required for the block to be enabled (to deactivate reset). In asynchronous (clockless) mode clk_sys is used to enable the block, but is not available for clocking. [12:8] read-write HLD_OVR IO cell hold override functionality. In DeepSleep power mode, the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep output functionality on these IO pads. This field is used to control the hold override functionality from the SMARTIO: '0': The HSIOM controls the IO cell hold override functionality ('hsiom_hld_ovr'). '1': The SMARTIO controls the IO cel hold override functionality: - In bypass mode (ENABLED is '0' or BYPASS[i] is '1'), the HSIOM control is used. - In NON bypass mode (ENABLED is '1' and BYPASS[i] is '0'), the SMARTIO sets hold override to 'pwr_hld_ovr_hib' to enable SMARTIO functionality in DeepSleep power mode (but disables it in Hibernate or Stop power mode). [24:24] read-write PIPELINE_EN Enable for pipeline register: '0': Disabled (register is bypassed). '1': Enabled. [25:25] read-write ENABLED Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured: '0': Disabled (signals are bypassed; behavior as if BYPASS is 0xFF). When disabled, the fabric (data unit and LUTs) reset is activated. If the IP is disabled: - The PIPELINE_EN register field should be set to '1', to ensure low power consumption by preventing combinatorial loops. - The CLOCK_SRC register field should be set to '20'-'30' (clock is constant '0'), to ensure low power consumption. '1': Enabled. Once enabled, it takes 3 'clk_fabric' clock cycles till the fabric reset is de-activated and the fabric becomes fully functional. This ensures that the IO pins' input synchronizer states are flushed when the fabric is fully functional. [31:31] read-write SYNC_CTL Synchronization control register 0x10 32 read-write 0x0 0x0 IO_SYNC_EN Synchronization of the IO pin input signals to 'clk_fabric', one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i. '0': No synchronization. '1': Synchronization. [7:0] read-write CHIP_SYNC_EN Synchronization of the chip input signals to 'clk_fabric', one bit for each input: CHIP_SYNC_EN[i] is for input i. '0': No synchronization. '1': Synchronization. [15:8] read-write 8 4 LUT_SEL[%s] LUT component input selection 0x20 32 read-write 0x0 0x0 LUT_TR0_SEL LUT input signal 'tr0_in' source selection: '0': Data unit output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). [3:0] read-write LUT_TR1_SEL LUT input signal 'tr1_in' source selection: '0': LUT 0 output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). [11:8] read-write LUT_TR2_SEL LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL. [19:16] read-write 8 4 LUT_CTL[%s] LUT component control register 0x40 32 read-write 0x0 0x0 LUT LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg). [7:0] read-write LUT_OPC LUT opcode specifies the LUT operation: '0': Combinatoral output, no feedback. tr_out = LUT[{tr2_in, tr1_in, tr0_in}]. '1': Combinatorial output, feedback. tr_out = LUT[{lut_reg, tr1_in, tr0_in}]. On clock: lut_reg <= tr_in2. '2': Sequential output, no feedback. temp = LUT[{tr2_in, tr1_in, tr0_in}]. tr_out = lut_reg. On clock: lut_reg <= temp. '3': Register with asynchronous set and reset. tr_out = lut_reg. enable = (tr2_in ^ LUT[4]) | LUT[5]. set = enable & (tr1_in ^ LUT[2]) & LUT[3]. clr = enable & (tr0_in ^ LUT[0]) & LUT[1]. Asynchronously (no clock required): lut_reg <= if (clr) '0' else if (set) '1' [9:8] read-write DU_SEL Data unit component input selection 0xC0 32 read-write 0x0 0x0 DU_TR0_SEL Data unit input signal 'tr0_in' source selection: '0': Constant '0'. '1': Constant '1'. '2': Data unit output. '10-3': LUT 7 - 0 outputs. Otherwise: Undefined. [3:0] read-write DU_TR1_SEL Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL. [11:8] read-write DU_TR2_SEL Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL. [19:16] read-write DU_DATA0_SEL Data unit input data 'data0_in' source selection: '0': Constant '0'. '1': chip_data[7:0]. '2': io_data_in[7:0]. '3': DATA.DATA MMIO register field. [25:24] read-write DU_DATA1_SEL Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL. [29:28] read-write DU_CTL Data unit component control register 0xC4 32 read-write 0x0 0x0 DU_SIZE Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g., if DU_SIZE is 7, the width is 8 bits. [2:0] read-write DU_OPC Data unit opcode specifies the data unit operation: '1': INCR '2': DECR '3': INCR_WRAP '4': DECR_WRAP '5': INCR_DECR '6': INCR_DECR_WRAP '7': ROR '8': SHR '9': AND_OR '10': SHR_MAJ3 '11': SHR_EQL. Otherwise: Undefined. [11:8] read-write DATA Data register 0xF0 32 read-write 0x0 0x0 DATA Data unit input data source. [7:0] read-write LPCOMP Low Power Comparators 0x40350000 0 65536 registers CONFIG LPCOMP Configuration Register 0x0 32 read-write 0x0 0xC0000000 LPREF_EN Enable the local reference generator circuit to generate the local Vref and ibias. This bit must be set for DeepSleep or Hibernate operation. [30:30] read-write ENABLED - 0: IP disabled (put analog in power down, open all switches, all clocks off, leakage power only) - 1: IP enabled [31:31] read-write STATUS LPCOMP Status Register 0x4 32 read-only 0x0 0x10001 OUT0 Current output value of the comparator 0. [0:0] read-only OUT1 Current output value of the comparator 1. [16:16] read-only INTR LPCOMP Interrupt request register 0x10 32 read-write 0x0 0x3 COMP0 Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit. [0:0] read-write COMP1 Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit. [1:1] read-write INTR_SET LPCOMP Interrupt set register 0x14 32 read-write 0x0 0x3 COMP0 Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write COMP1 Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write INTR_MASK LPCOMP Interrupt request mask 0x18 32 read-write 0x0 0x3 COMP0_MASK Mask bit for corresponding bit in interrupt request register. [0:0] read-write COMP1_MASK Mask bit for corresponding bit in interrupt request register. [1:1] read-write INTR_MASKED LPCOMP Interrupt request masked 0x1C 32 read-only 0x0 0x3 COMP0_MASKED Logical and of corresponding request and mask bits. [0:0] read-only COMP1_MASKED Logical and of corresponding request and mask bits. [1:1] read-only CMP0_CTRL Comparator 0 control Register 0x40 32 read-write 0x0 0xCE3 MODE0 Operating mode for the comparator [1:0] read-write OFF Off 0 ULP Ultra lowpower operating mode (uses less power, < 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used. 1 LP Low Power operating mode (uses more power, <10uA @@@ TBD). In this mode the iref from SRSS will be used. 2 NORMAL Normal, full speed power operating mode (uses <150uA). In this mode the iref from SRSS will be used. 3 HYST0 Add 30mV hysteresis to the comparator 0= Disable Hysteresis 1= Enable Hysteresis [5:5] read-write INTTYPE0 Sets which edge will trigger an IRQ [7:6] read-write DISABLE Disabled, no interrupts will be detected 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 DSI_BYPASS0 Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async). Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin. [10:10] read-write DSI_LEVEL0 Synchronous comparator DSI (trigger) output : 0=pulse, 1=level [11:11] read-write CMP0_SW Comparator 0 switch control 0x50 32 read-write 0x0 0xF7 CMP0_IP0 Comparator 0 positive terminal isolation switch to GPIO [0:0] read-write CMP0_AP0 Comparator 0 positive terminal switch to amuxbusA [1:1] read-write CMP0_BP0 Comparator 0 positive terminal switch to amuxbusB [2:2] read-write CMP0_IN0 Comparator 0 negative terminal isolation switch to GPIO [4:4] read-write CMP0_AN0 Comparator 0 negative terminal switch to amuxbusA [5:5] read-write CMP0_BN0 Comparator 0 negative terminal switch to amuxbusB [6:6] read-write CMP0_VN0 Comparator 0 negative terminal switch to local Vref (LPREF_EN must be set) [7:7] read-write CMP0_SW_CLEAR Comparator 0 switch control clear 0x54 32 read-write 0x0 0xF7 CMP0_IP0 see corresponding bit in CMP0_SW [0:0] read-write CMP0_AP0 see corresponding bit in CMP0_SW [1:1] read-write CMP0_BP0 see corresponding bit in CMP0_SW [2:2] read-write CMP0_IN0 see corresponding bit in CMP0_SW [4:4] read-write CMP0_AN0 see corresponding bit in CMP0_SW [5:5] read-write CMP0_BN0 see corresponding bit in CMP0_SW [6:6] read-write CMP0_VN0 see corresponding bit in CMP0_SW [7:7] read-write CMP1_CTRL Comparator 1 control Register 0x80 32 read-write 0x0 0xCE3 MODE1 Operating mode for the comparator [1:0] read-write OFF Off 0 ULP Ultra lowpower operating mode (uses less power, < 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used. 1 LP Low Power operating mode (uses more power, <10uA @@@ TBD). In this mode the iref from SRSS will be used. 2 NORMAL Normal, full speed power operating mode (uses <150uA). In this mode the iref from SRSS will be used. 3 HYST1 Add 30mV hysteresis to the comparator 0= Disable Hysteresis 1= Enable Hysteresis [5:5] read-write INTTYPE1 Sets which edge will trigger an IRQ [7:6] read-write DISABLE Disabled, no interrupts will be detected 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 DSI_BYPASS1 Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async). Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin. [10:10] read-write DSI_LEVEL1 Synchronous comparator DSI (trigger) output : 0=pulse, 1=level [11:11] read-write CMP1_SW Comparator 1 switch control 0x90 32 read-write 0x0 0xF7 CMP1_IP1 Comparator 1 positive terminal isolation switch to GPIO [0:0] read-write CMP1_AP1 Comparator 1 positive terminal switch to amuxbusA [1:1] read-write CMP1_BP1 Comparator 1 positive terminal switch to amuxbusB [2:2] read-write CMP1_IN1 Comparator 1 negative terminal isolation switch to GPIO [4:4] read-write CMP1_AN1 Comparator 1 negative terminal switch to amuxbusA [5:5] read-write CMP1_BN1 Comparator 1 negative terminal switch to amuxbusB [6:6] read-write CMP1_VN1 Comparator 1 negative terminal switch to local Vref (LPREF_EN must be set) [7:7] read-write CMP1_SW_CLEAR Comparator 1 switch control clear 0x94 32 read-write 0x0 0xF7 CMP1_IP1 see corresponding bit in CMP1_SW [0:0] read-write CMP1_AP1 see corresponding bit in CMP1_SW [1:1] read-write CMP1_BP1 see corresponding bit in CMP1_SW [2:2] read-write CMP1_IN1 see corresponding bit in CMP1_SW [4:4] read-write CMP1_AN1 see corresponding bit in CMP1_SW [5:5] read-write CMP1_BN1 see corresponding bit in CMP1_SW [6:6] read-write CMP1_VN1 see corresponding bit in CMP1_SW [7:7] read-write CSD0 Capsense Controller CSD 0x40360000 0 4096 registers CONFIG Configuration and Control 0x0 32 read-write 0x4000000 0xCF0E1DF1 IREF_SEL N/A [0:0] read-write IREF_SRSS N/A 0 IREF_PASS N/A 1 FILTER_DELAY Enables the digital filtering on the CSD comparator [8:4] read-write SHIELD_DELAY Configures the delay between shield clock and sensor clock [11:10] read-write OFF Delay line is off; sensor clock = shield clock 0 D5NS shield clock is delayed by 5ns delay w.r.t sensor clock 1 D10NS shield clock is delayed by 10ns delay w.r.t sensor clock 2 D20NS shield clock is delayed by 20ns delay w.r.t sensor clock 3 SENSE_EN Enables the sensor and shield clocks, CSD modulator output and turns on the IDAC compensation current as selected by CSD_IDAC. [12:12] read-write FULL_WAVE N/A [17:17] read-write HALFWAVE Half Wave mode 0 FULLWAVE Full Wave mode 1 MUTUAL_CAP N/A [18:18] read-write SELFCAP Self-cap mode 0 MUTUALCAP Mutual-cap mode 1 CSX_DUAL_CNT N/A [19:19] read-write ONE N/A 0 TWO N/A 1 DSI_COUNT_SEL N/A [24:24] read-write CSD_RESULT N/A 0 ADC_RESULT N/A 1 DSI_SAMPLE_EN DSI_SAMPLE_EN = 1 -> COUNTER will count the samples generated by DSI DSI_SAMPLE_EN = 0 -> COUNTER will count the samples generated by CSD modulator [25:25] read-write SAMPLE_SYNC N/A [26:26] read-write DSI_SENSE_EN DSI_SENSE_EN = 1-> sensor clock is driven directly by DSI DSI_SENSE_EN = 0-> sensor clock is driven by PRS/divide-by-2/DIRECT_CLOCK [27:27] read-write LP_MODE N/A [30:30] read-write ENABLE N/A [31:31] read-write SPARE Spare MMIO 0x4 32 read-write 0x0 0xF SPARE Spare MMIO [3:0] read-write STATUS Status Register 0x80 32 read-only 0x0 0xE CSD_SENSE Only for Debug/test purpose this internal signal (sensor clock) status can be read by CPU [1:1] read-only HSCMP_OUT Only for Debug/test purpose the output status of CSD comparator can be read by CPU [2:2] read-only C_LT_VREF N/A 0 C_GT_VREF N/A 1 CSDCMP_OUT Only for Debug/test purpose the output status of CSD modulator can be read by CPU [3:3] read-only STAT_SEQ Current Sequencer status 0x84 32 read-only 0x0 0x70007 SEQ_STATE CSD sequencer state [2:0] read-only ADC_STATE ADC sequencer state (only relevant after SEQ_STATE has reached SAMPLE_NORM and ADC sequencer has started) [18:16] read-only STAT_CNTS Current status counts 0x88 32 read-only 0x0 0xFFFF NUM_CONV Current number of conversions remaining when in Sample_* states (note that in AutoZero* states the same down counter is reused to count the cycles) [15:0] read-only STAT_HCNT Current count of the HSCMP counter 0x8C 32 read-only 0x0 0xFFFF CNT Current value of HSCMP counter [15:0] read-only RESULT_VAL1 Result CSD/CSX accumulation counter value 1 0xD0 32 read-only 0x0 0xFFFFFF VALUE Accumulated counter value for this result. In case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt) this counter counts when csd_sense is high. [15:0] read-only BAD_CONVS Number of 'bad' conversion for which the CSD comparator did not trigger within the normal time window, either because Vref was not crossed at all, or if the Vref was already crossed before the window started. This counter is reset when the sequencer is started and will saturate at 255 when more than 255 conversions are bad. [23:16] read-only RESULT_VAL2 Result CSX accumulation counter value 2 0xD4 32 read-only 0x0 0xFFFF VALUE Only used in case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt), this counter counts when csd_sense is low. [15:0] read-only ADC_RES ADC measurement 0xE0 32 read-only 0x0 0xC001FFFF VIN_CNT Count to source/sink Cref1 + Cref2 from Vin to Vrefhi. [15:0] read-only HSCMP_POL Polarity used for IDACB for this last ADC result, 0= source, 1= sink [16:16] read-only ADC_OVERFLOW This flag is set when the ADC counter overflows. This is an indication to the firmware that the IDACB current level is too low. [30:30] read-only ADC_ABORT This flag is set when the ADC sequencer was aborted before tripping HSCMP. [31:31] read-only INTR CSD Interrupt Request Register 0xF0 32 read-write 0x0 0x106 SAMPLE A normal sample is complete [1:1] read-write INIT Coarse initialization complete or Sample initialization complete (the latter is typically ignored) [2:2] read-write ADC_RES ADC Result ready [8:8] read-write INTR_SET CSD Interrupt set register 0xF4 32 read-write 0x0 0x106 SAMPLE Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write INIT Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write ADC_RES Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write INTR_MASK CSD Interrupt mask register 0xF8 32 read-write 0x0 0x106 SAMPLE Mask bit for corresponding bit in interrupt request register. [1:1] read-write INIT Mask bit for corresponding bit in interrupt request register. [2:2] read-write ADC_RES Mask bit for corresponding bit in interrupt request register. [8:8] read-write INTR_MASKED CSD Interrupt masked register 0xFC 32 read-only 0x0 0x106 SAMPLE Logical and of corresponding request and mask bits. [1:1] read-only INIT Logical and of corresponding request and mask bits. [2:2] read-only ADC_RES Logical and of corresponding request and mask bits. [8:8] read-only HSCMP High Speed Comparator configuration 0x180 32 read-write 0x0 0x80000011 HSCMP_EN High Speed Comparator enable [0:0] read-write OFF Disable comparator, output is zero 0 ON On, regular operation. Note that CONFIG.LP_MODE determines the power mode level 1 HSCMP_INVERT Invert the HSCMP output before it is used to control switches and the CSD sequencer. This bit does not affect the ADC sequencer or the STATUS.HSCMP_OUT [4:4] read-write AZ_EN Auto-Zero enable, allow the Sequencer to Auto-Zero this component [31:31] read-write AMBUF Reference Generator configuration 0x184 32 read-write 0x0 0x3 PWR_MODE Amux buffer power level [1:0] read-write OFF Disable buffer 0 NORM On, normal or low power level depending on CONFIG.LP_MODE. 1 HI On, high or low power level depending on CONFIG.LP_MODE. 2 REFGEN Reference Generator configuration 0x188 32 read-write 0x0 0x9F1F71 REFGEN_EN Reference Generator Enable [0:0] read-write OFF Disable Reference Generator 0 ON On, regular operation. Note that CONFIG.LP_MODE determines the power mode level 1 BYPASS Bypass selected input reference unbuffered to Vrefhi [4:4] read-write VDDA_EN Close Vdda switch to top of resistor string (or Vrefhi?) [5:5] read-write RES_EN Resistor string enable; 0= open switch on top of the resistor string (Vreflo=Vssa) [6:6] read-write GAIN Select resistor string tap for feedback, 0= minimum vout, 31= maximum vout = vrefhi -> gain=1 (only works if the resistor string is enabled; RES_EN=1) [12:8] read-write VREFLO_SEL Select resistor string tap for Vreflo/Vreflo_int, 0= minimum vout, 31= maximum vout = vrefhi (only works if the resistor string is enabled; RES_EN=1) [20:16] read-write VREFLO_INT Ouput the resistor string tap either to Vreflo (0) or Vreflo_int (1). [23:23] read-write CSDCMP CSD Comparator configuration 0x18C 32 read-write 0x0 0xB0000331 CSDCMP_EN CSD Comparator Enable [0:0] read-write OFF Disable comparator, output is zero 0 ON On, regular operation. Note that CONFIG.LP_MODE determines the power mode level 1 POLARITY_SEL Select which IDAC polarity to use to detect CSDCMP triggering [5:4] read-write IDACA_POL Use idaca_pol (firmware setting with CSX and optionally DSI mixed in) to determine the direction, this is the most common use-case, used for normal CSD and normal CSX 0 IDACB_POL Use idacb_pol (firmware setting with optional DSI mixed in) to determine the direction, this is only used for normal CSD if IDACB is used i.s.o. IDACA (not common) 1 DUAL_POL Use the expression (csd_sense ? idaca_pol : idacb_pol) to determine the direction, this is only useful for the CSX with DUAL_IDAC use-case 2 CMP_PHASE Select in what phase(s) the comparator is active, typically set to match the BAL_MODE of the used IDAC. Note, this also determines when a bad conversion is detected, namely at the beginning and end of the comparator active phase (also taking into account FILTER_DELAY and non-overlap). [9:8] read-write FULL Comparator is active from start of Phi2 and kept active into Phi1. Intended usage: legacy CSD for balancing over a full csd_sense period (non-overlap should be turned off) 0 PHI1 Comparator is active during Phi1 only. Currently no known use-case. 1 PHI2 Comparator is active during Phi2 only. Intended usage: CSD Low EMI. 2 PHI1_2 Comparator is activated at the start of both Phi1 and Phi2 (non-overlap should be enabled). Intended usage: CSX, or Full-Wave. 3 CMP_MODE Select which signal to output on dsi_sample_out. [28:28] read-write CSD CSD mode: output the filtered sample signal on dsi_sample_out 0 GP General Purpose mode: output the unfiltered sample unfiltered comparator output, either asynchronous or flopped. 1 FEEDBACK_MODE This bit controls whether the output directly from the comparator (csdcmp_out) or the flopped version (csdcmp_out_ff) is used. For CSD operation, the selected signal controls the IDAC(s), in GP mode the signal goes out on dsi_sample_out. [29:29] read-write FLOP Use feedback from sampling flip-flop (used in most modes). 0 COMP Use feedback from comparator directly (used in single Cmod mutual cap sensing only) 1 AZ_EN Auto-Zero enable, allow the Sequencer to Auto-Zero this component [31:31] read-write SW_RES Switch Resistance configuration 0x1F0 32 read-write 0x0 0xF00FF RES_HCAV Select resistance or low EMI (slow ramp) for the HCAV switch [1:0] read-write LOW Low 0 MED Medium 1 HIGH High 2 LOWEMI Low EMI (slow ramp: 3 switches closed by fixed delay line) 3 RES_HCAG Select resistance or low EMI for the corresponding switch [3:2] read-write RES_HCBV Select resistance or low EMI for the corresponding switch [5:4] read-write RES_HCBG Select resistance or low EMI for the corresponding switch [7:6] read-write RES_F1PM Select resistance for the corresponding switch [17:16] read-write LOW Low 0 MED Medium 1 HIGH High 2 RSVD N/A 3 RES_F2PT Select resistance for the corresponding switch [19:18] read-write SENSE_PERIOD Sense clock period 0x200 32 read-write 0xC000000 0xFF70FFF SENSE_DIV The length-1 of the Sense modulation 'clock' period in clk_csd cycles. For regular CSD one sense clock cycle = one conversion (=phi1+phi2) . Note this is the base divider, clock dithering may change the actual period length. Note that SENSE_DIV must be at least 1 and additionally also allow for one clk_hf of non overlap (if OVERLAP_HI1/2 is set) on both phases, i.e. if clk_csd=clk_hf then SENSE_DIV must be >=3. In addition the FILTER_DELAY needs to be added to the minimum allowed SENSE_DIV value. [11:0] read-write LFSR_SIZE Selects the length of the LFSR which determines the LFSR repeat period. LFSR_BITS LSB of the LFSR are used for the clock dithering variation on the base period (was PRS in CSDv1). Whenever the LFSR is used (non zero value in this field) the LFSR_CLEAR bit should also be set. [18:16] read-write OFF Don't use clock dithering (=spreadspectrum) (LFSR output value is zero) 0 6B 6-bit LFSR (G(x)=X^6 +X^4+X^3+ X+1, period= 63) 1 7B 7-bit LFSR (G(x)=X^7 +X^4+X^3+X^2+1, period= 127) 2 9B 9-bit LFSR (G(x)=X^9 +X^4+X^3+ X+1, period= 511) 3 10B 10-bit LFSR (G(x)=X^10+X^4+X^3+ X+1, period= 1023) 4 8B 8-bit LFSR (G(x)=X^8+X^4+X^3+X^2+1, period= 255) 5 12B 12-bit LFSR (G(x)=X^12+X^7+X^4+X^3+1, period= 4095) 6 LFSR_SCALE Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV. This dithering is disabled when SEL_LSFR_MSB is set. The clock divider to be used = (SENSE_DIV+1) + (SEL_LSFR_MSB ? 0 : (LFSR_OUT<<LFSR_SCALE)). Note that the clock divider including the dithering term must fit in 12 bits, otherwise the result is undefined. [23:20] read-write LFSR_CLEAR When set, forces the LFSR to it's initial state (all ones). This bit is automatically cleared by hardware after the LFSR is cleared, which is at the next clk_csd positive edge. This bit should be set whenever this register is written and the LFSR is used. Note that the LFSR will also get reset to all ones during the AutoZero_1/2 states. [24:24] read-write SEL_LFSR_MSB Use the MSB of configured LSFR size as csd_sense signal. Intended to be used only with bit 8 or 12-bit LFSR size for CSDv1 backward compatibility (PRS). When this bit is set then clock divider dithering is disabled and SENSE_WIDTH is disabled. [25:25] read-write LFSR_BITS Selects the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period. Caveat make sure that SENSE_DIV > the maximum absolute range (e.g. for 4B SENSE_DIV > 8), otherwise results are undefined. [27:26] read-write 2B use 2 bits: range = [-2,1] 0 3B use 3 bits: range = [-4,3] 1 4B use 4 bits: range = [-8,7] 2 5B use 5 bits: range = [-16,15] (default) 3 SENSE_DUTY Sense clock duty cycle 0x204 32 read-write 0x0 0xD0FFF SENSE_WIDTH Defines the length of the first phase of the sense clock in clk_csd cycles. A value of 0 disables this feature and the duty cycle of csd_sense will be 50 percent, which is equal to SENSE_WIDTH = (SENSE_DIV+1)/2, or when clock dithering is used that becomes [(SENSE_DIV+1) + (LFSR_OUT << LSFR_SCALE)]/2. At all times it must be assured that the phases are at least 2 clk_csd cycles (1 for non overlap, if used), if this rule is violated the result is undefined. Note that this feature is not available when SEL_LFSR_MSB (PRS) is selected. [11:0] read-write SENSE_POL Polarity of the sense clock 0 = start with low phase (typical for regular negative transfer CSD) 1 = start with high phase [16:16] read-write OVERLAP_PHI1 NonOverlap or not for Phi1 (csd_sense=0). 0 = Non-overlap for Phi1, the Phi1 signal is csd_sense inverted except that the signal goes low 1 clk_sample before csd_sense goes high. Intended usage: new low EMI CSD/CSX with static GPIO. 1 = 'Overlap' (= not non-overlap) for Phi1, the Phi1 signal is csd_sense inverted. Intended usage: legacy CSD with GPIO switching, the GPIO internal circuit ensures that the switches are non-overlapping. [18:18] read-write OVERLAP_PHI2 Same as OVERLAP_PHI1 but for Phi2 (csd_sense=1). [19:19] read-write SW_HS_P_SEL HSCMP Pos input switch Waveform selection 0x280 32 read-write 0x0 0x11111111 SW_HMPM Set HMPM switch 0: static open 1: static closed [0:0] read-write SW_HMPT Set corresponding switch [4:4] read-write SW_HMPS Set corresponding switch [8:8] read-write SW_HMMA Set corresponding switch [12:12] read-write SW_HMMB Set corresponding switch [16:16] read-write SW_HMCA Set corresponding switch [20:20] read-write SW_HMCB Set corresponding switch [24:24] read-write SW_HMRH Set corresponding switch [28:28] read-write SW_HS_N_SEL HSCMP Neg input switch Waveform selection 0x284 32 read-write 0x0 0x77110000 SW_HCCC Set corresponding switch [16:16] read-write SW_HCCD Set corresponding switch [20:20] read-write SW_HCRH Select waveform for corresponding switch [26:24] read-write SW_HCRL Select waveform for corresponding switch [30:28] read-write SW_SHIELD_SEL Shielding switches Waveform selection 0x288 32 read-write 0x0 0x117777 SW_HCAV N/A [2:0] read-write SW_HCAG Select waveform for corresponding switch [6:4] read-write SW_HCBV N/A [10:8] read-write SW_HCBG Select waveform for corresponding switch, using csd_shield as base [14:12] read-write SW_HCCV Set corresponding switch [16:16] read-write SW_HCCG Set corresponding switch If the ADC is enabled then this switch is directly controlled by the ADC sequencer. [20:20] read-write SW_AMUXBUF_SEL Amuxbuffer switches Waveform selection 0x290 32 read-write 0x0 0x11171110 SW_IRBY Set corresponding switch [4:4] read-write SW_IRLB Set corresponding switch [8:8] read-write SW_ICA Set corresponding switch [12:12] read-write SW_ICB Select waveform for corresponding switch [18:16] read-write SW_IRLI Set corresponding switch [20:20] read-write SW_IRH Set corresponding switch [24:24] read-write SW_IRL Set corresponding switch [28:28] read-write SW_BYP_SEL AMUXBUS bypass switches Waveform selection 0x294 32 read-write 0x0 0x111000 SW_BYA Set corresponding switch [12:12] read-write SW_BYB Set corresponding switch [16:16] read-write SW_CBCC Set corresponding switch If the ADC is enabled then this switch is directly controlled by the ADC sequencer. [20:20] read-write SW_CMP_P_SEL CSDCMP Pos Switch Waveform selection 0x2A0 32 read-write 0x0 0x1111777 SW_SFPM Select waveform for corresponding switch [2:0] read-write SW_SFPT Select waveform for corresponding switch [6:4] read-write SW_SFPS Select waveform for corresponding switch [10:8] read-write SW_SFMA Set corresponding switch [12:12] read-write SW_SFMB Set corresponding switch [16:16] read-write SW_SFCA Set corresponding switch [20:20] read-write SW_SFCB Set corresponding switch [24:24] read-write SW_CMP_N_SEL CSDCMP Neg Switch Waveform selection 0x2A4 32 read-write 0x0 0x77000000 SW_SCRH Select waveform for corresponding switch [26:24] read-write SW_SCRL Select waveform for corresponding switch [30:28] read-write SW_REFGEN_SEL Reference Generator Switch Waveform selection 0x2A8 32 read-write 0x0 0x11110011 SW_IAIB Set corresponding switch [0:0] read-write SW_IBCB Set corresponding switch [4:4] read-write SW_SGMB Set corresponding switch [16:16] read-write SW_SGRP Set corresponding switch [20:20] read-write SW_SGRE Set corresponding switch [24:24] read-write SW_SGR Set corresponding switch [28:28] read-write SW_FW_MOD_SEL Full Wave Cmod Switch Waveform selection 0x2B0 32 read-write 0x0 0x11170701 SW_F1PM Set corresponding switch [0:0] read-write SW_F1MA Select waveform for corresponding switch [10:8] read-write SW_F1CA Select waveform for corresponding switch [18:16] read-write SW_C1CC Set corresponding switch [20:20] read-write SW_C1CD Set corresponding switch [24:24] read-write SW_C1F1 Set corresponding switch [28:28] read-write SW_FW_TANK_SEL Full Wave Csh_tank Switch Waveform selection 0x2B4 32 read-write 0x0 0x11177710 SW_F2PT Set corresponding switch [4:4] read-write SW_F2MA Select waveform for corresponding switch [10:8] read-write SW_F2CA Select waveform for corresponding switch [14:12] read-write SW_F2CB Select waveform for corresponding switch [18:16] read-write SW_C2CC Set corresponding switch [20:20] read-write SW_C2CD Set corresponding switch [24:24] read-write SW_C2F2 Set corresponding switch [28:28] read-write SW_DSI_SEL DSI output switch control Waveform selection 0x2C0 32 read-write 0x0 0xFF DSI_CSH_TANK Select waveform for dsi_csh_tank output signal 0: static open 1: static closed 2: phi1 3: phi2 4: phi1 & HSCMP 5: phi2 & HSCMP 6: HSCMP // ignores phi1/2 7: !sense // = phi1 but ignores OVERLAP_PHI1 8: phi1_delay // phi1 delayed with shield delay 9: phi2_delay // phi2 delayed with shield delay 10: !phi1 11: !phi2 12: !(phi1 & HSCMP) 13: !(phi2 & HSCMP) 14: !HSCMP // ignores phi1/2 15: sense // = phi2 but ignores OVERLAP_PHI2 [3:0] read-write DSI_CMOD Select waveform for dsi_cmod output signal [7:4] read-write IO_SEL IO output control Waveform selection 0x2D0 32 read-write 0x0 0xFFFF0FF CSD_TX_OUT Select waveform for csd_tx_out output signal [3:0] read-write CSD_TX_OUT_EN Select waveform for csd_tx_out_en output signal [7:4] read-write CSD_TX_AMUXB_EN Select waveform for csd_tx_amuxb_en output signal [15:12] read-write CSD_TX_N_OUT Select waveform for csd_tx_n_out output signal [19:16] read-write CSD_TX_N_OUT_EN Select waveform for csd_tx_n_out_en output signal [23:20] read-write CSD_TX_N_AMUXA_EN Select waveform for csd_tx_n_amuxa_en output signal [27:24] read-write SEQ_TIME Sequencer Timing 0x300 32 read-write 0x0 0xFF AZ_TIME Define Auto-Zero time in csd_sense cycles -1. [7:0] read-write SEQ_INIT_CNT Sequencer Initial conversion and sample counts 0x310 32 read-write 0x0 0xFFFF CONV_CNT Number of conversion per Initialization sample, if set to 0 the Sample_init state will be skipped. [15:0] read-write SEQ_NORM_CNT Sequencer Normal conversion and sample counts 0x314 32 read-write 0x0 0xFFFF CONV_CNT Number of conversion per sample, if set to 0 the Sample_norm state will be skipped. Sample window size = SEQ_NORM_CNT.CONV_CNT * (SENSE_PERIOD.SENSE_DIV+1). Note for CSDv1 Sample window size = PERIOD [15:0] read-write ADC_CTL ADC Control 0x320 32 read-write 0x0 0x300FF ADC_TIME ADC timing -1 in csd_sense clock cycles (actual time is ADC_TIME+1 cycles), either used to discharge Cref1&2, or as the aperture to capture the input voltage on Cref1&2 [7:0] read-write ADC_MODE Enable ADC measurement. When enabled the ADC sequencer will be started when the main sequencer goes to the SAMPLE_NORM state [17:16] read-write OFF No ADC measurement 0 VREF_CNT Count time A to bring Cref1 + Cref2 up from Vssa to Vrefhi with IDACB 1 VREF_BY2_CNT Count time B to bring Cref1 + Cref2 back up to Vrefhi with IDACB (after bringing them down for time A/2 cycles with IDACB sinking) 2 VIN_CNT Determine HSCMP polarity and count time C to source/sink Cref1 + Cref2 from Vin to Vrefhi. 3 SEQ_START Sequencer start 0x340 32 read-write 0x0 0x31B START Start the CSD sequencer. The sequencer will clear this bit when it is done. Depending on the mode the sequencer is done when a sample has been accumulated, when the high speed comparator trips or if the sequencer is aborted. When the ADC is enabled the ADC sequencer will start when the CSD sequencer reaches the Sample_norm state (only with the regular CSD scan mode). [0:0] read-write SEQ_MODE 0 = regular CSD scan + optional ADC 1 = coarse initialization, the Sequencer will go to the INIT_COARSE state. [1:1] read-write ABORT When a 1 is written the CSD and ADC sequencers will be aborted (if they are running) and the START bit will be cleared. This bit always read as 0. [3:3] read-write DSI_START_EN When this bit is set a positive edge on dsi_start will start the CSD sequencer and if enabled also the ADC sequencer. [4:4] read-write AZ0_SKIP When set the AutoZero_0 state will be skipped [8:8] read-write AZ1_SKIP When set the AutoZero_1 state will be skipped [9:9] read-write IDACA IDACA Configuration 0x400 32 read-write 0x0 0x3EF0FFF VAL N/A [6:0] read-write POL_DYN N/A [7:7] read-write STATIC N/A 0 DYNAMIC N/A 1 POLARITY N/A [9:8] read-write VSSA_SRC Normal: sensor switching between Vssio and Cmod. For non-CSD application, IDAC1 will source current. 0 VDDA_SNK Inverted: sensor switch between Vddio and Cmod. For non-CSD application, IDAC1 will sink current. 1 SENSE N/A 2 SENSE_INV N/A 3 BAL_MODE N/A [11:10] read-write FULL N/A 0 PHI1 N/A 1 PHI2 N/A 2 PHI1_2 N/A 3 LEG1_MODE N/A [17:16] read-write GP_STATIC N/A 0 GP N/A 1 CSD_STATIC N/A 2 CSD N/A 3 LEG2_MODE N/A [19:18] read-write GP_STATIC N/A 0 GP N/A 1 CSD_STATIC N/A 2 CSD N/A 3 DSI_CTRL_EN N/A [21:21] read-write RANGE N/A [23:22] read-write IDAC_LO N/A 0 IDAC_MED N/A 1 IDAC_HI N/A 2 LEG1_EN N/A [24:24] read-write LEG2_EN N/A [25:25] read-write IDACB IDACB Configuration 0x500 32 read-write 0x0 0x7EF0FFF VAL N/A [6:0] read-write POL_DYN N/A [7:7] read-write STATIC N/A 0 DYNAMIC N/A 1 POLARITY N/A [9:8] read-write VSSA_SRC Normal: sensor switching between Vssio and Cmod. For non-CSD application, IDAC1 will source current. 0 VDDA_SNK Inverted: sensor switch between Vddio and Cmod. For non-CSD application, IDAC1 will sink current. 1 SENSE N/A 2 SENSE_INV N/A 3 BAL_MODE N/A [11:10] read-write FULL N/A 0 PHI1 N/A 1 PHI2 N/A 2 PHI1_2 N/A 3 LEG1_MODE N/A [17:16] read-write GP_STATIC N/A 0 GP N/A 1 CSD_STATIC N/A 2 CSD N/A 3 LEG2_MODE N/A [19:18] read-write GP_STATIC N/A 0 GP N/A 1 CSD_STATIC N/A 2 CSD N/A 3 DSI_CTRL_EN N/A [21:21] read-write RANGE N/A [23:22] read-write IDAC_LO N/A 0 IDAC_MED N/A 1 IDAC_HI N/A 2 LEG1_EN N/A [24:24] read-write LEG2_EN N/A [25:25] read-write LEG3_EN N/A [26:26] read-write TCPWM0 Timer/Counter/PWM TCPWM 0x40380000 0 65536 registers CTRL TCPWM control register 0x0 32 read-write 0x0 0xFFFFFFFF COUNTER_ENABLED Counter enables for counters 0 up to CNT_NR-1. '0': counter disabled. '1': counter enabled. Counter static configuration information (e.g. CTRL.MODE, all TR_CTRL0, TR_CTRL1, and TR_CTRL2 register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes: - the associated counter triggers in the CMD register are set to '0'. - the counter's interrupt cause fields in counter's INTR register. - the counter's status fields in counter's STATUS register.. - the counter's trigger outputs ('tr_overflow', 'tr_underflow' and 'tr_compare_match'). - the counter's line outputs ('line_out' and 'line_compl_out'). In multi-core environments, use the CTRL_SET/CTRL_CLR registers to avoid race-conditions on read-modify-write attempts to this register. [31:0] read-write CTRL_CLR TCPWM control clear register 0x4 32 read-write 0x0 0xFFFFFFFF COUNTER_ENABLED Alias of CTRL that only allows disabling of counters. A write access: '0': Does nothing. '1': Clears respective COUNTER_ENABLED field. A read access returns CTRL.COUNTER_ENABLED. [31:0] read-write CTRL_SET TCPWM control set register 0x8 32 read-write 0x0 0xFFFFFFFF COUNTER_ENABLED Alias of CTRL that only allows enabling of counters. A write access: '0': Does nothing. '1': Sets respective COUNTER_ENABLED field. A read access returns CTRL.COUNTER_ENABLED. [31:0] read-write CMD_CAPTURE TCPWM capture command register 0xC 32 read-write 0x0 0xFFFFFFFF COUNTER_CAPTURE Counters SW capture trigger. When written with '1', a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.COUNTER_ENABLED, the field is immediately set to '0'. [31:0] read-write CMD_RELOAD TCPWM reload command register 0x10 32 read-write 0x0 0xFFFFFFFF COUNTER_RELOAD Counters SW reload trigger. For HW behavior, see COUNTER_CAPTURE field. [31:0] read-write CMD_STOP TCPWM stop command register 0x14 32 read-write 0x0 0xFFFFFFFF COUNTER_STOP Counters SW stop trigger. For HW behavior, see COUNTER_CAPTURE field. [31:0] read-write CMD_START TCPWM start command register 0x18 32 read-write 0x0 0xFFFFFFFF COUNTER_START Counters SW start trigger. For HW behavior, see COUNTER_CAPTURE field. [31:0] read-write INTR_CAUSE TCPWM Counter interrupt cause register 0x1C 32 read-only 0x0 0xFFFFFFFF COUNTER_INT Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED, the associated interrupt field is immediately set to '0'. [31:0] read-only 24 64 CNT[%s] Timer/Counter/PWM Counter Module 0x00000100 CTRL Counter control register 0x0 32 read-write 0x0 0x737FF0F AUTO_RELOAD_CC Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event. [0:0] read-write AUTO_RELOAD_PERIOD Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event. [1:1] read-write PWM_SYNC_KILL Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'. [2:2] read-write PWM_STOP_ON_KILL Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only. [3:3] read-write GENERIC Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock. [15:8] read-write DIVBY1 Divide by 1 (other-than-PWM_DT mode) 0 DIVBY2 Divide by 2 (other-than-PWM_DT mode) 1 DIVBY4 Divide by 4 (other-than-PWM_DT mode) 2 DIVBY8 Divide by 8 (other-than-PWM_DT mode) 3 DIVBY16 Divide by 16 (other-than-PWM_DT mode) 4 DIVBY32 Divide by 32 (other-than-PWM_DT mode) 5 DIVBY64 Divide by 64 (other-than-PWM_DT mode) 6 DIVBY128 Divide by 128 (other-than-PWM_DT mode) 7 UP_DOWN_MODE Determines counter direction. [17:16] read-write COUNT_UP Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD. 0 COUNT_DOWN Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. 1 COUNT_UPDN1 Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. 2 COUNT_UPDN2 Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates). 3 ONE_SHOT When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated. [18:18] read-write QUADRATURE_MODE In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1]. [21:20] read-write X1 X1 encoding (QUAD mode) 0 X2 X2 encoding (QUAD mode) 1 X4 X4 encoding (QUAD mode) 2 MODE Counter mode. [26:24] read-write TIMER Timer mode 0 CAPTURE Capture mode 2 QUAD Quadrature encoding mode 3 PWM Pulse width modulation (PWM) mode 4 PWM_DT PWM with deadtime insertion mode 5 PWM_PR Pseudo random pulse width modulation 6 STATUS Counter status register 0x4 32 read-only 0x0 0x8000FF01 DOWN When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented. [0:0] read-only GENERIC Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality. [15:8] read-only RUNNING When '0', the counter is NOT running. When '1', the counter is running. [31:31] read-only COUNTER Counter count register 0x8 32 read-write 0x0 0xFFFFFFFF COUNTER 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running. [31:0] read-write CC Counter compare/capture register 0xC 32 read-write 0xFFFFFFFF 0xFFFFFFFF CC In CAPTURE mode, captures the counter value. In other modes, compared to counter value. [31:0] read-write CC_BUFF Counter buffered compare/capture register 0x10 32 read-write 0xFFFFFFFF 0xFFFFFFFF CC Additional buffer for counter CC register. [31:0] read-write PERIOD Counter period register 0x14 32 read-write 0xFFFFFFFF 0xFFFFFFFF PERIOD Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1. [31:0] read-write PERIOD_BUFF Counter buffered period register 0x18 32 read-write 0xFFFFFFFF 0xFFFFFFFF PERIOD Additional buffer for counter PERIOD register. [31:0] read-write TR_CTRL0 Counter trigger control register 0 0x20 32 read-write 0x10 0xFFFFF CAPTURE_SEL Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts. [3:0] read-write COUNT_SEL Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'. [7:4] read-write RELOAD_SEL Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint). [11:8] read-write STOP_SEL Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event. [15:12] read-write START_SEL Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B). [19:16] read-write TR_CTRL1 Counter trigger control register 1 0x24 32 read-write 0x3FF 0x3FF CAPTURE_EDGE A capture event will copy the counter value into the CC register. [1:0] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 BOTH_EDGES Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 COUNT_EDGE A counter event will increase or decrease the counter by '1'. [3:2] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 BOTH_EDGES Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 RELOAD_EDGE A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD. [5:4] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 BOTH_EDGES Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 STOP_EDGE A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter. [7:6] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 BOTH_EDGES Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 START_EDGE A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does. [9:8] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 BOTH_EDGES Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 TR_CTRL2 Counter trigger control register 2 0x28 32 read-write 0x3F 0x3F CC_MATCH_MODE Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register. [1:0] read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 OVERFLOW_MODE Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals. [3:2] read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 UNDERFLOW_MODE Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals. [5:4] read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 INTR Interrupt request register 0x30 32 read-write 0x0 0x3 TC Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit. [0:0] read-write CC_MATCH Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit. [1:1] read-write INTR_SET Interrupt set request register 0x34 32 read-write 0x0 0x3 TC Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write CC_MATCH Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write INTR_MASK Interrupt mask register 0x38 32 read-write 0x0 0x3 TC Mask bit for corresponding bit in interrupt request register. [0:0] read-write CC_MATCH Mask bit for corresponding bit in interrupt request register. [1:1] read-write INTR_MASKED Interrupt masked request register 0x3C 32 read-only 0x0 0x3 TC Logical and of corresponding request and mask bits. [0:0] read-only CC_MATCH Logical and of corresponding request and mask bits. [1:1] read-only TCPWM1 0x40390000 LCD0 LCD Controller Block LCD 0x403B0000 0 65536 registers ID ID & Revision 0x0 32 read-only 0x1F0F0 0xFFFFFFFF ID the ID of LCD controller peripheral is 0xF0F0 [15:0] read-only REVISION the version number is 0x0001 [31:16] read-only DIVIDER LCD Divider Register 0x4 32 read-write 0x0 0xFFFFFFFF SUBFR_DIV Input clock frequency divide value, to generate the 1/4 sub-frame period. The sub-frame period is 4*(SUBFR_DIV+1) cycles long. [15:0] read-write DEAD_DIV Length of the dead time period in cycles. When set to zero, no dead time period exists. [31:16] read-write CONTROL LCD Configuration Register 0x8 32 read-write 0x0 0x80000F7F LS_EN Low speed (LS) generator enable 1: enable 0: disable [0:0] read-write HS_EN High speed (HS) generator enable 1: enable 0: disable [1:1] read-write LCD_MODE HS/LS Mode selection [2:2] read-write LS Select Low Speed (32kHz) Generator (Works in Active, Sleep and DeepSleep power modes). 0 HS Select High Speed (system clock) Generator (Works in Active and Sleep power modes only). 1 TYPE LCD driving waveform type configuration. [3:3] read-write TYPE_A Type A - Each frame addresses each COM pin only once with a balanced (DC=0) waveform. 0 TYPE_B Type B - Each frame addresses each COM pin twice in sequence with a positive and negative waveform that together are balanced (DC=0). 1 OP_MODE Driving mode configuration [4:4] read-write PWM PWM Mode 0 CORRELATION Digital Correlation Mode 1 BIAS PWM bias selection [6:5] read-write HALF 1/2 Bias 0 THIRD 1/3 Bias 1 FOURTH 1/4 Bias (not supported by LS generator) 2 FIFTH 1/5 Bias (not supported by LS generator) 3 COM_NUM The number of COM connections minus 2. So: 0: 2 COM's 1: 3 COM's ... 13: 15 COM's 14: 16 COM's 15: undefined [11:8] read-write LS_EN_STAT LS enable status bit. This bit is a copy of LS_EN that is synchronized to the low speed clock domain and back to the system clock domain. Firmware can use this bit to observe whether LS_EN has taken effect in the low speed clock domain. Firmware should never change the configuration for the LS generator without ensuring this bit is 0. The following procedure should be followed to disable the LS generator: 1. If LS_EN=0 we are done. Exit the procedure. 2. Check that LS_EN_STAT=1. If not, wait until it is. This will catch the case of a recent enable (LS_EN=1) that has not taken effect yet. 3. Set LS_EN=0. 4. Wait until LS_EN_STAT=0. [31:31] read-only 8 4 DATA0[%s] LCD Pin Data Registers 0x100 32 read-write 0x0 0xFFFFFFFF DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb). [31:0] read-write 8 4 DATA1[%s] LCD Pin Data Registers 0x200 32 read-write 0x0 0xFFFFFFFF DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb). [31:0] read-write 8 4 DATA2[%s] LCD Pin Data Registers 0x300 32 read-write 0x0 0xFFFFFFFF DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb). [31:0] read-write 8 4 DATA3[%s] LCD Pin Data Registers 0x400 32 read-write 0x0 0xFFFFFFFF DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb). [31:0] read-write BLE Bluetooth Low Energy Subsystem 0x403C0000 0 131072 registers RCB Radio Control Bus (RCB) controller 0x00000000 CTRL RCB control register. 0x0 32 read-write 0xF80000 0x80FFFF3E TX_CLK_EDGE N/A [1:1] read-write RX_CLK_EDGE N/A [2:2] read-write RX_CLK_SRC N/A [3:3] read-write SCLK_CONTINUOUS N/A [4:4] read-write SSEL_POLARITY N/A [5:5] read-write LEAD N/A [9:8] read-write LAG N/A [11:10] read-write DIV_ENABLED N/A [12:12] read-write DIV N/A [18:13] read-write ADDR_WIDTH N/A [22:19] read-write DATA_WIDTH N/A [23:23] read-write ENABLED N/A [31:31] read-write STATUS RCB status register. 0x4 32 read-only 0x0 0x0 BUS_BUSY RCB bus is busy. The bus is considered busy ('1') during an ongoing transaction. [0:0] read-only TX_CTRL Transmitter control register. 0x10 32 read-write 0x21 0x7F MSB_FIRST Least significant bit first ('0') or most significant bit first ('1'). This field also affects the Address field When MSB_FIRST = 1, then [15:0] is data and [(ADDR_WIDTH+15):16] is used for address When MSB_FIRST = 0, then [15:0] is for data. No address field [0:0] read-write FIFO_RECONFIG Setting this bit, clears the FIFO and resets the pointer [1:1] read-write TX_ENTRIES This field determines the depth of the TX_FIFO. Allowed legal values are 8 and 16 only [6:2] read-write TX_FIFO_CTRL Transmitter FIFO control register. 0x14 32 read-write 0x0 0x1001F TX_TRIGGER_LEVEL Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event is generated. [4:0] read-write CLEAR When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. [16:16] read-write TX_FIFO_STATUS Transmitter FIFO status register. 0x18 32 read-only 0x0 0xF0F801F USED Amount of enties in the transmitter FIFO. The value of this field ranges from 0 to 16 [4:0] read-only SR_VALID Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is tranmitted next (when the protocol state machine is not transmitting a data frame). [15:15] read-only RD_PTR FIFO read pointer: FIFO location from which a data frame is read by the hardware. [19:16] read-only WR_PTR FIFO write pointer: FIFO location at which a new data frame is written. [27:24] read-only TX_FIFO_WR Transmitter FIFO write register. 0x1C 32 write-only 0x0 0xFFFFFFFF DATA Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'. [31:0] write-only RX_CTRL Receiver control register. 0x20 32 read-write 0x1 0x1 MSB_FIRST Least significant bit first ('0') or most significant bit first ('1'). This field also affects the Address field When MSB_FIRST = 1, then [15:0] is data and [(ADDR_WIDTH+15):16] is used for address When MSB_FIRST = 0, then [15:0] is for data. No address field [0:0] read-write RX_FIFO_CTRL Receiver FIFO control register. 0x24 32 read-write 0x0 0x1000F TRIGGER_LEVEL Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event is generated. [3:0] read-write CLEAR When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. [16:16] read-write RX_FIFO_STATUS Receiver FIFO status register. 0x28 32 read-only 0x0 0xF0F801F USED Amount of enties in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR. [4:0] read-only SR_VALID Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame). [15:15] read-only RD_PTR FIFO read pointer: FIFO location from which a data frame is read. [19:16] read-only WR_PTR FIFO write pointer: FIFO location at which a new data frame is written by the hardware. [27:24] read-only RX_FIFO_RD Receiver FIFO read register. 0x2C 32 read-only 0x0 0x0 DATA N/A [31:0] read-only RX_FIFO_RD_SILENT Receiver FIFO read register. 0x30 32 read-only 0x0 0x0 DATA Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. [31:0] read-only INTR Master interrupt request register. 0x40 32 read-write 0x600 0x1F1F01 RCB_DONE N/A [0:0] read-write TX_FIFO_TRIGGER N/A [8:8] read-write TX_FIFO_NOT_FULL N/A [9:9] read-write TX_FIFO_EMPTY N/A [10:10] read-write TX_FIFO_OVERFLOW N/A [11:11] read-write TX_FIFO_UNDERFLOW Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'. Only used in FIFO mode. [12:12] read-write RX_FIFO_TRIGGER N/A [16:16] read-write RX_FIFO_NOT_EMPTY N/A [17:17] read-write RX_FIFO_FULL N/A [18:18] read-write RX_FIFO_OVERFLOW N/A [19:19] read-write RX_FIFO_UNDERFLOW N/A [20:20] read-write INTR_SET Master interrupt set request register 0x44 32 read-write 0x600 0x1F1F01 RCB_DONE Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write TX_FIFO_TRIGGER Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write TX_FIFO_NOT_FULL Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write TX_FIFO_EMPTY Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write TX_FIFO_OVERFLOW Write with '1' to set corresponding bit in interrupt request register. [11:11] read-write TX_FIFO_UNDERFLOW Write with '1' to set corresponding bit in interrupt request register. [12:12] read-write RX_FIFO_TRIGGER Write with '1' to set corresponding bit in interrupt request register. [16:16] read-write RX_FIFO_NOT_EMPTY Write with '1' to set corresponding bit in interrupt request register. [17:17] read-write RX_FIFO_FULL Write with '1' to set corresponding bit in interrupt request register. [18:18] read-write RX_FIFO_OVERFLOW Write with '1' to set corresponding bit in interrupt request register. [19:19] read-write RX_FIFO_UNDERFLOW Write with '1' to set corresponding bit in interrupt request register. [20:20] read-write INTR_MASK Master interrupt mask register. 0x48 32 read-write 0x0 0x1F1F01 RCB_DONE Mask bit for corresponding bit in interrupt request register. [0:0] read-write TX_FIFO_TRIGGER Mask bit for corresponding bit in interrupt request register. [8:8] read-write TX_FIFO_NOT_FULL Mask bit for corresponding bit in interrupt request register. [9:9] read-write TX_FIFO_EMPTY Mask bit for corresponding bit in interrupt request register. [10:10] read-write TX_FIFO_OVERFLOW Mask bit for corresponding bit in interrupt request register. [11:11] read-write TX_FIFO_UNDERFLOW Mask bit for corresponding bit in interrupt request register. [12:12] read-write RX_FIFO_TRIGGER Mask bit for corresponding bit in interrupt request register. [16:16] read-write RX_FIFO_NOT_EMPTY Mask bit for corresponding bit in interrupt request register. [17:17] read-write RX_FIFO_FULL Mask bit for corresponding bit in interrupt request register. [18:18] read-write RX_FIFO_OVERFLOW Mask bit for corresponding bit in interrupt request register. [19:19] read-write RX_FIFO_UNDERFLOW Mask bit for corresponding bit in interrupt request register. [20:20] read-write INTR_MASKED Master interrupt masked request register 0x4C 32 read-only 0x0 0x1F1F01 RCB_DONE Logical and of corresponding request and mask bits. [0:0] read-only TX_FIFO_TRIGGER Logical and of corresponding request and mask bits. [8:8] read-only TX_FIFO_NOT_FULL Logical and of corresponding request and mask bits. [9:9] read-only TX_FIFO_EMPTY Logical and of corresponding request and mask bits. [10:10] read-only TX_FIFO_OVERFLOW Logical and of corresponding request and mask bits. [11:11] read-only TX_FIFO_UNDERFLOW Logical and of corresponding request and mask bits. [12:12] read-only RX_FIFO_TRIGGER Logical and of corresponding request and mask bits. [16:16] read-only RX_FIFO_NOT_EMPTY Logical and of corresponding request and mask bits. [17:17] read-only RX_FIFO_FULL Logical and of corresponding request and mask bits. [18:18] read-only RX_FIFO_OVERFLOW Logical and of corresponding request and mask bits. [19:19] read-only RX_FIFO_UNDERFLOW Logical and of corresponding request and mask bits. [20:20] read-only RCBLL Radio Control Bus (RCB) & Link Layer controller 0x00000100 CTRL RCB LL control register. 0x0 32 read-write 0x0 0x3F RCBLL_CTRL N/A [0:0] read-write RCBLL_CPU_REQ N/A [1:1] read-write CPU_SINGLE_WRITE N/A [2:2] read-write CPU_SINGLE_READ N/A [3:3] read-write ALLOW_CPU_ACCESS_TX_RX N/A [4:4] read-write ENABLE_RADIO_BOD N/A [5:5] read-write INTR Master interrupt request register. 0x10 32 read-write 0x0 0xD RCB_LL_DONE RCB_LL is done and the access is given back to CPU [0:0] read-write SINGLE_WRITE_DONE N/A [2:2] read-write SINGLE_READ_DONE N/A [3:3] read-write INTR_SET Master interrupt set request register 0x14 32 read-write 0x0 0xD RCB_LL_DONE Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write SINGLE_WRITE_DONE N/A [2:2] read-write SINGLE_READ_DONE N/A [3:3] read-write INTR_MASK Master interrupt mask register. 0x18 32 read-write 0x0 0xD RCB_LL_DONE Mask bit for corresponding bit in interrupt request register. [0:0] read-write SINGLE_WRITE_DONE N/A [2:2] read-write SINGLE_READ_DONE N/A [3:3] read-write INTR_MASKED Master interrupt masked request register 0x1C 32 read-only 0x0 0xD RCB_LL_DONE Logical and of corresponding request and mask bits. [0:0] read-only SINGLE_WRITE_DONE N/A [2:2] read-only SINGLE_READ_DONE N/A [3:3] read-only RADIO_REG1_ADDR Address of Register#1 in Radio (MDON) 0x20 32 read-write 0x1E02 0xFFFF REG_ADDR N/A [15:0] read-write RADIO_REG2_ADDR Address of Register#2 in Radio (RSSI) 0x24 32 read-write 0xA03 0xFFFF REG_ADDR N/A [15:0] read-write RADIO_REG3_ADDR Address of Register#3 in Radio (ACCL) 0x28 32 read-write 0x824 0xFFFF REG_ADDR N/A [15:0] read-write RADIO_REG4_ADDR Address of Register#4 in Radio (ACCH) 0x2C 32 read-write 0x823 0xFFFF REG_ADDR N/A [15:0] read-write RADIO_REG5_ADDR Address of Register#5 in Radio (RSSI ENERGY) 0x30 32 read-write 0xA03 0xFFFF REG_ADDR N/A [15:0] read-write CPU_WRITE_REG N/A 0x40 32 read-write 0x0 0xFFFFFFFF ADDR N/A [15:0] read-write WRITE_DATA N/A [31:16] read-write CPU_READ_REG N/A 0x44 32 read-write 0x0 0xFFFFFFFF ADDR N/A [15:0] read-write READ_DATA N/A [31:16] read-only BLELL Bluetooth Low Energy Link Layer 0x00001000 COMMAND_REGISTER Instruction Register 0x0 32 write-only 0x0 0xFF COMMAND N/A [7:0] write-only EVENT_INTR Event(Interrupt) status and Clear register 0x8 32 read-write 0x0 0xFF ADV_INTR Advertiser interrupt. If bit is set to 1, it indicates an event occurred in the advertising procedure. The source of the event needs to be read from the ADV_INTR register. This bit is cleared, when firmware clears ALL interrupts by writing to the ADV_INTR register. [0:0] read-only SCAN_INTR Scanner interrupt. If bit is set to 1, it indicates an event occurred in the scanning procedure. The source of the event needs to be read from the SCAN_INTR register. This bit is cleared, when firmware clears ALL interrupts by writing to the SCAN_INTR register. [1:1] read-only INIT_INTR Initiator interrupt. If bit is set to 1, it indicates an event occurred in the initiating procedure. The source of the event needs to be read from the INIT_INTR register. This bit is cleared, when firmware clears ALL interrupts by writing to the INIT_INTR register. [2:2] read-only CONN_INTR Connection interrupt. If bit is set to 1, it indicates an event occurred in the connection operation. This interrupt is aggregation of interrupts for all the connections. The source of the event for the specific connection, needs to be read from the CONN_INTR register specific to the connection. This bit is cleared, when firmware clears ALL interrupts by writing to the CONN_INTR register. [3:3] read-only SM_INTR Read: Sleep-mode-exit interrupt. This bit is set, when link layer hardware exits from sleep mode. Write: Clear sleep-mode-exit interrupt. Write to the register with this bit set to 1, clears the interrupt source. This interrupt is deprecated and should not be used. [4:4] read-write DSM_INTR Read: Deep sleep mode exit interrupt. This bit is set, when link layer hardware exits from deep sleep mode. Write: Clear deep sleep mode exit interrupt. Write to the register with this bit set to 1, clears the interrupt source. [5:5] read-write ENC_INTR Encryption module interrupt. This interrupt id deprecated and should not be used [6:6] read-only RSSI_RX_DONE_INTR RSSI RX done interrupt. [7:7] read-only EVENT_ENABLE Event indications enable. 0x10 32 read-write 0x0 0xFF ADV_INT_EN Advertiser interrupt enable. 1 - enable advertiser procedure to interrupt the firmware. 0 - disable advertiser procedure interrupt to firmware. [0:0] read-write SCN_INT_EN Scanner interrupt enable. 1 - enable scan procedure to interrupt the firmware. 0 - disable scan procedure interrupt to firmware. [1:1] read-write INIT_INT_EN Initiator interrupt enable. 1 - enable initiator procedure to interrupt the firmware. 0 - disable initiator procedure interrupt to firmware. [2:2] read-write CONN_INT_EN Connection interrupt enable. 1 - enable connection procedure to interrupt the firmware. 0 - disable connection procedure interrupt to firmware. [3:3] read-write SM_INT_EN Sleep-mode-exit interrupt enable. 1 - enable sleep mode exit event to interrupt the firmware. 0 - disable sleep mode exit interrupt to firmware. This interrupt is deprecated and should not be used. [4:4] read-write DSM_INT_EN Deep Sleep-mode-exit interrupt enable. 1 - enable deep sleep mode exit event to interrupt the firmware. 0 - disable deep sleep mode exit interrupt to firmware. [5:5] read-write ENC_INT_EN Encryption module interrupt enable. 1 - Enable encryption module interrupt to firmware. 0 - disable encryption module interrupt to firmware. This interrupt is deprecated and should not be used [6:6] read-write RSSI_RX_DONE_INT_EN RSSI Rx interrupt enable. 1 - Enable RSSI Rx done interrupt to firmware. 0 - Disable RSSI Rx done interrupt to firmware. [7:7] read-write ADV_PARAMS Advertising parameters register. 0x18 32 read-write 0xE0 0xFFFF TX_ADDR Device own address type. 1 - Address type is random. 0 - Address type is public. [0:0] read-write ADV_TYPE The Advertising type is used to determine the packet type that is used for advertising when advertising is enabled. 0x0 - Connectable undirected advertising. (adv_ind) 0x1 - Connectable directed advertising (adv_direct_ind). 0x2 - Discoverable undirected advertising (adv_discover_ind) 0x3 - Non connectable undirected advertising (adv_nonconn_ind). [2:1] read-write ADV_FILT_POLICY Advertising filter policy. The set of devices that the advertising procedure uses for device filtering is called the White List. 0x0 - Allow scan request from any device, allow connect request from any device. 0x1 - Allow scan request from devices in white list only, allow connect request from any device. 0x2 - Allow scan request from any device, allow connect request from devices in white list only. 0x3 - Allow scan request from devices in white list only, allow connect request from devices in white list only. [4:3] read-write ADV_CHANNEL_MAP Advertising channel map indicates the advertising channels used for advertising. By setting the bit, corresponding channel is enabled for use. Atleast one channel bit should be set. 7 - enable channel 39. 6 - enable channel 38. 5 - enable channel 37. [7:5] read-write RX_ADDR Peer addresses type. This is the Direct_Address_type field programmed, only if ADV_DIRECT_IND type is sent. 1 - Rx addr type is random. 0 - Rx addr type is public [8:8] read-write RX_SEC_ADDR Peer secondary addresses type. This is the Direct_Address_type field programmed, only if ADV_DIRECT_IND type is sent. This address type corresponds to the PEER_SERC_ADDR register. Valid only if PRIV_1_2_ADV is set. 1 - Rx secondary addr type is random. 0 - Rx secondary addr type is public [9:9] read-write ADV_LOW_DUTY_CYCLE This bit field is used to specify to the Controller the Low Duty Cycle connectable directed advertising variant being used. 1 - Low Duty Cycle Connectable Directed Advertising. 0 - High Duty Cycle Connectable Directed Advertising. [10:10] read-write INITA_RPA_CHECK This bit field is used to specify the Advertiser behavior on receiving the same INITA in the connect_req as in the ADV_DIRECT_IND packet it sent. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. 0 - Accept the connect_req packet 1 - Reject the connect_req packet [11:11] read-write TX_ADDR_PRIV Device own address type subtype when Address type is random. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. 1 - Random Address type is private. 0 - Random Address type is static. [12:12] read-write ADV_RCV_IA_IN_PRIV Advertiser behavior when a peer Identity address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. 1 - Accept packets with peer identity address not in the Resolving list in privacy mode 0 - Reject packets with peer identity address not in the Resolving list in privacy mode [13:13] read-write ADV_RPT_PEER_NRPA_ADDR_IN_PRIV Advertiser behavior when a peer Non Resolvable Private Address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. This is applicable when whitelist is disabled. 1 - Only report the packets with peer NRPA address in privacy mode 0 - Respond to packets with peer NRPA address in privacy mode [14:14] read-write RCV_TX_ADDR Transmit address field of the received packet extracted from the receive packet. This field is used by firmware to report peer_addr_type parameter in the connection complete event. [15:15] read-only ADV_INTERVAL_TIMEOUT Advertising interval register. 0x1C 32 read-write 0x20 0x7FFF ADV_INTERVAL Range: 0x0020 to 0x4000 (For ADV_IND) 0x00A0 to 0x4000 (For ADV_SCAN_IND and NONCONN_IND) Invalid for ADV_DIRECT_IND Time = N * 0.625 msec Time Range: 20 ms to 10.24 sec. For directed advertising, firmware programs the default value of 1.28 seconds. In MMMS mode, this register is used as ADV_NI_TIMER when the ADV_NI_VALID is set by firmware [14:0] read-write ADV_INTR Advertising interrupt status and Clear register 0x20 32 read-write 0x0 0x1FFF ADV_STRT_INTR If this bit is set it indicates a new advertising event started after interval expiry. Write to the register with this bit set to 1, clears the interrupt source. [0:0] read-write ADV_CLOSE_INTR If this bit is set it indicates current advertising event is closed. Write to the register with this bit set to 1, clears the interrupt source. [1:1] read-write ADV_TX_INTR If this bit is set it indicates ADV packet is transmitted. Write to the register with this bit set to 1, clears the interrupt source. [2:2] read-write SCAN_RSP_TX_INTR If this bit is set it indicates scan response packet transmitted in response to previous scan request packet received. Write to the register with this bit set to 1, clears the interrupt source. [3:3] read-write SCAN_REQ_RX_INTR If this bit is set it indicates scan request packet received. Write to the register with this bit set to 1, clears the interrupt source. [4:4] read-write CONN_REQ_RX_INTR If this bit is set it indicates connect request packet is received. Write to the register with this bit set to 1, clears the interrupt source. [5:5] read-write SLV_CONNECTED If this bit is set it indicates that connection is created as slave. Write to the register with this bit set to 1, clears the interrupt source. Note: On a slave connection creation, the link layer cannot enter deepsleep mode in the same slot . It can enter deepsleep mode only in the subsequent slots. [6:6] read-write ADV_TIMEOUT If this bit is set it indicates that the directed advertising event has timed out after 1.28 seconds. Applicable in adv_direct_ind advertising. Write to the register with this bit set to 1, clears the interrupt source. [7:7] read-write ADV_ON Advertiser procedure is ON in hardware. Indicates that advertiser procedure is ON in hardware. 1 - ON 0 - OFF [8:8] read-only SLV_CONN_PEER_RPA_UNMCH_INTR If this bit is set it indicates that connection is created as slave, but the peer device Resolvable Private Address is not resolved/ ID or NRPA are not matched yet. If the address is not resolved prior to connection establishment, the connection will be terminated. Write to the register with this bit set to 1, clears the interrupt source. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. [9:9] read-write SCAN_REQ_RX_PEER_RPA_UNMCH_INTR If this bit is set it indicates scan request packet received, but the peer device Resolvable Private Address is not resolved/ ID or NRPA are not matched yet. Write to the register with this bit set to 1, clears the interrupt source. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. [10:10] read-write INIT_ADDR_MATCH_PRIV_MISMATCH_INTR If this bit is set it indicates that an Identity address is received from a Scanner and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the Scanner Write to the register with this bit set to 1, clears the interrupt source. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. [11:11] read-write SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR If this bit is set it indicates that an Identity address is received from an initiator and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the initiator Write to the register with this bit set to 1, clears the interrupt source. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. [12:12] read-write ADV_NEXT_INSTANT Advertising next instant. 0x24 32 read-only 0x0 0xFFFF ADV_NEXT_INSTANT Shows the next start of advertising event with reference to the internal reference clock. [15:0] read-only SCAN_INTERVAL Scan Interval Register 0x28 32 read-write 0x10 0xFFFF SCAN_INTERVAL Scan interval register. Interval between two consecutive scanning events. Firmware sets the scanning interval value to this register before issuing start scan command. Range: 0x0004 to 0x4000 Default: 0x0010 (10 ms) Time = N * 0.625 msec Time Range: 2.5 msec to 10.24 sec. In MMMS mode, this register is used as SCAN_NI_TIMER when the SCAN_NI_VALID is set by firmware [15:0] read-write SCAN_WINDOW Scan window Register 0x2C 32 read-write 0x10 0xFFFF SCAN_WINDOW Duration of scan in a scanning event, which should be less than or equal to scan interval value. Firmware sets the scan window value to this register before issuing start scan command. Range: 0x0004 to 0x4000 Default: 0x0010 (10 ms) Time = N * 0.625 msec Time Range: 2.5 msec to 10.24 sec. (To prevent ADV RX - SCAN REQ TX - SCAN RSP RX spilling over across the scan window, when not in continuous scan, the scan window must be 2 slots less that the scan interval. [15:0] read-write SCAN_PARAM Scanning parameters register 0x30 32 read-write 0x0 0x3FF TX_ADDR Device's own address type. 1 - addr type is random. 0 - addr type is public. [0:0] read-write SCAN_TYPE 0x00 - passive scanning.(default) 0x01 - active scanning. 0x10 - RFU 0x11 - RFU [2:1] read-write SCAN_FILT_POLICY The scanner filter policy determines how the scanner processes advertising packets. 0x00 - Accept advertising packets from any device. 0x01 - Accept advertising packets from only devices in the whitelist. In the above 2 policies, the directed advertising packets which are not addressed to this device are ignored. 0x10 - Accept all undirected advertising packets and directed advertising packet addressed to this device. 0x11 - Accept undirected advertising packets from devices in the whitelist and directed advertising packet addressed to this device In the above 2 policies, the directed advertising packets where the initiator address is a resolvable private address are accepted. The above 2 policies are extended scanner filter policies. [4:3] read-write DUP_FILT_EN Filter duplicate packets. 1- Duplicate filtering enabled. 0- Duplicate filtering not enabled. This field is derived from the LE_set_scan_enable command. [5:5] read-write DUP_FILT_CHK_ADV_DIR This bit field is used to specify the Scanner duplicate filter behavior for ADV_DIRECT_IND packet when duplicate DUP_FILT_EN is set. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. 0 - Do not filter ADV_DIRECT_IND duplicate packets. 1 - Filter ADV_DIRECT_IND duplicate packets [6:6] read-write SCAN_RSP_ADVA_CHECK This bit field is used to specify the Scanner behavior with respect to ADVA while receiving a SCAN_RSP packet. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. 0 - The ADVA in SCAN_RSP packets are not verified 1 - The ADVA in SCAN_RSP packets are verified against ADVA received in ADV packet . If it fails, then abort the packet. [7:7] read-write SCAN_RCV_IA_IN_PRIV Scanner behavior when a peer Identity address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. 1 - Accept packets with peer identity address not in the Resolving list in privacy mode 0 - Reject packets with peer identity address not in the Resolving list in privacy mode [8:8] read-write SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV Scanner behavior when a peer Non Resolvable Private Address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. This is applicable when whitelist is disabled. 1 - Only report packets with peer NRPA address in privacy mode 0 - Respond packets with peer NRPA address in privacy mode [9:9] read-write SCAN_INTR Scan interrupt status and Clear register 0x38 32 read-write 0x0 0x7FF SCAN_STRT_INTR If this bit is set it indicates scan window is opened. Write to the register with this bit set to 1, clears the interrupt source. [0:0] read-write SCAN_CLOSE_INTR If this bit is set it indicates scan window is closed. Write to the register with this bit set to 1, clears the interrupt source. [1:1] read-write SCAN_TX_INTR If this bit is set it indicates scan request packet is transmitted. Write to the register with this bit set to 1, clears the interrupt source. [2:2] read-write ADV_RX_INTR If this bit is set it indicates ADV packet received. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. Write to the register with this bit set to 1, clears the interrupt source. This interrupt is generated while active/passive scanning upon receiving adv packets. Note: Any ADV RX interrupt received after issuing SCAN_STOP command must be ignored and the ADVCH FIFO flushed. [3:3] read-write SCAN_RSP_RX_INTR If this bit is set it indicates SCAN_RSP packet is received. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. Write to the register with this bit set to 1, clears the interrupt source. NOTE: This interrupt is generated while active scanning upon receiving scan response packet. [4:4] read-write ADV_RX_PEER_RPA_UNMCH_INTR If this bit is set it indicates ADV packet received but the peer device Address is not match yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. Write to the register with this bit set to 1, clears the interrupt source. This interrupt is generated while active/passive scanning upon receiving adv packets. [5:5] read-write ADV_RX_SELF_RPA_UNMCH_INTR If this bit is set it indicates ADV_DIRECT packet received but the self device Resolvable Private Address is not resolved yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. Write to the register with this bit set to 1, clears the interrupt source. This interrupt is generated while active/passive scanning upon receiving adv_direct packets. [6:6] read-write SCANA_TX_ADDR_NOT_SET_INTR If this bit is set it indicates that a valid ScanA RPA to be transmitted in SCAN_REQ packet in response to an ADV packet is not present in the resolving list Write to the register with this bit set to 1, clears the interrupt source. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. [7:7] read-write SCAN_ON Scan procedure status. 1 - scan procedure is active. 0 - scan procedure is not active. [8:8] read-only PEER_ADDR_MATCH_PRIV_MISMATCH_INTR If this bit is set it indicates that an Identity address is received from an initiator and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the initiator Write to the register with this bit set to 1, clears the interrupt source. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. [9:9] read-write SELF_ADDR_MATCH_PRIV_MISMATCH_INTR If this bit is set it indicates that the self Identity address is received from an initiator and matches, but self IRK is set and hence a corresponding RPA is expected from the initiator Write to the register with this bit set to 1, clears the interrupt source. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. [10:10] read-write SCAN_NEXT_INSTANT Advertising next instant. 0x3C 32 read-only 0x0 0xFFFF NEXT_SCAN_INSTANT Shows the instant with respect to internal reference clock of resolution 625 us at which next scanning event begins. [15:0] read-only INIT_INTERVAL Initiator Interval Register 0x40 32 read-write 0x0 0xFFFF INIT_SCAN_INTERVAL Initiator interval register. Firmware sets the initiator's scanning interval value to this regis-ter before issuing create connection command. Interval between two consecutive scanning events. Range: 0x0004 to 0x4000 Time = N * 0.625 msec Time Range: 2.5 msec to 10.24 sec. In MMMS mode, this register is used as INIT_NI_TIMER when the INIT_NI_VALID is set by firmware [15:0] read-write INIT_WINDOW Initiator window Register 0x44 32 read-write 0x0 0xFFFF INIT_SCAN_WINDOW Duration of scan in a scanning event, which should be less than or equal to scan interval value. Firmware sets the scan window value to this register before issuing create connection command. Range: 0x0004 to 0x4000 Time = N * 0.625 msec Time Range: 2.5 msec to 10.24 sec. In MMMS mode, this register is used as INIT_NI_TIMER when the INIT_NI_VALID is set by firmware [15:0] read-write INIT_PARAM Initiator parameters register 0x48 32 read-write 0x0 0x1B TX_ADDR Device' own address type. 1 - addr type is random. 0 - addr type is public. [0:0] read-write RX_ADDR__RX_TX_ADDR Peer address type. The rx_addr field is updated by the receiver with the address type of the received connectable advertising packet. 1 - addr type is random. 0 - addr type is public. [1:1] read-write INIT_FILT_POLICY The Initiator_Filter_Policy is used to determine whether the White List is used or not. 0 - White list is not used to determine which advertiser to connect to. Instead the Peer_Address_Type and Peer Address fields are used to specify the address type and address of the advertising device to connect to. 1 - White list is used to determine the advertising device to connect to. Peer_Address_Type and Peer_Address fields are ignored when whitelist is used. [3:3] read-write INIT_RCV_IA_IN_PRIV Init behavior when a peer Identity address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set. 1 - Accept packets with peer identity address not in the Resolving list in privacy mode 0 - Reject packets with peer identity address not in the Resolving list in privacy mode & HW_RSLV_LIST_FULL is not set [4:4] read-write INIT_INTR Scan interrupt status and Clear register 0x50 32 read-write 0x0 0x3F7 INIT_INTERVAL_EXPIRE_INTR If this bit is set it indicates initiator scan window has started. Write to the register with this bit set to 1, clears the interrupt source. [0:0] read-write INIT_CLOSE_WINDOW_INR If this bit is set it indicates initiator scan window has finished. Write to the register with this bit set to 1, clears the interrupt source. [1:1] read-write INIT_TX_START_INTR If this bit is set it indicates initiator packet (CONREQ) transmission has started. Write to the register with this bit set to 1, clears the interrupt source. [2:2] read-write MASTER_CONN_CREATED If this bit is set it indicates connection is created as master. Write to the register with this bit set to 1, clears the interrupt source. [4:4] read-write ADV_RX_SELF_ADDR_UNMCH_INTR If this bit is set it indicates ADV_DIRECT packet received but the self device Resolvable Private Address is not resolved yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set. Write to the register with this bit set to 1, clears the interrupt source. This interrupt is generated while active/passive scanning upon receiving adv packets. [5:5] read-write ADV_RX_PEER_ADDR_UNMCH_INTR If this bit is set it indicates ADV packet received but the peer device Address is not matched yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set. Write to the register with this bit set to 1, clears the interrupt source. This interrupt is generated while active/passive scanning upon receiving adv packets. [6:6] read-write INITA_TX_ADDR_NOT_SET_INTR If this bit is set it indicates that a valid INITA RPA to be transmitted in CONN_REQ packet in response to an ADV packet is not present in the resolving list Write to the register with this bit set to 1, clears the interrupt source. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set. [7:7] read-write INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR If this bit is set it indicates that an Identity address is received from an initiator and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the initiator Write to the register with this bit set to 1, clears the interrupt source. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set. [8:8] read-write INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR If this bit is set it indicates that - an Identity address is received from an initiator and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the initiator - or an RPA is received from an initiator and matches an entry in the resolving list, but peer IRK is not set and hence a corresponding Identity address is expected from the initiator Write to the register with this bit set to 1, clears the interrupt source. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set. [9:9] read-write INIT_NEXT_INSTANT Initiator next instant. 0x54 32 read-only 0x0 0xFFFF INIT_NEXT_INSTANT Shows the instant with respect to internal reference clock of resolution 625 us at which next initiator scanning event begins. [15:0] read-only DEVICE_RAND_ADDR_L Lower 16 bit random address of the device. 0x58 32 read-write 0x0 0xFFFF DEVICE_RAND_ADDR_L Lower 16 bit of 48-bit random address of the device. [15:0] read-write DEVICE_RAND_ADDR_M Middle 16 bit random address of the device. 0x5C 32 read-write 0x0 0xFFFF DEVICE_RAND_ADDR_M Middle 16 bit of 48-bit random address of the device. [15:0] read-write DEVICE_RAND_ADDR_H Higher 16 bit random address of the device. 0x60 32 read-write 0x0 0xFFFF DEVICE_RAND_ADDR_H Higher 16 bit of 48-bit random address of the device. [15:0] read-write PEER_ADDR_L Lower 16 bit address of the peer device. 0x68 32 read-write 0x0 0xFFFF PEER_ADDR_L Lower 16 bit of 48-bit address of the peer device. [15:0] read-write PEER_ADDR_M Middle 16 bit address of the peer device. 0x6C 32 read-write 0x0 0xFFFF PEER_ADDR_M Middle 16 bit of 48-bit address of the peer device. [15:0] read-write PEER_ADDR_H Higher 16 bit address of the peer device. 0x70 32 read-write 0x0 0xFFFF PEER_ADDR_H Higher 16 bit of 48-bit address of the peer device. The peer address registers are used for multiple purposes. The register is written by firmware to provide the peer address to be used for a hardware procedure. When firmware reads the register, it reads back peer address values updated by hardware. While doing directed Advertising, the firmware writes the peer address of the device specified by the Di-rect_Address parameter of the LE_Set_Advertising_Parameters command. In non MMMS mode, While device is configured as an initiator without white list filtering, the peer address specified in the peer_address field of the create connection command is programmed into this register, which is used by hard-ware procedures. In non MMMS mode, While device is configured as an initiator and white list is enabled, firmware can read this register to get the address of the peer device from which connectable ADV packet was received and to which the connection is created. When a connection is created as a slave, the firmware can read this register to get the address of the peer de-vice to which connection is created. [15:0] read-write WL_ADDR_TYPE whitelist address type 0x78 32 read-write 0x0 0xFFFF WL_ADDR_TYPE 8 address type bits corresponding to the device address stored. 1 - Address type is random. 0 - Address type is public. [15:0] read-write WL_ENABLE whitelist valid entry bit 0x7C 32 read-write 0x0 0xFFFF WL_ENABLE Stores the valid entry bit corresponding to each of the eight device address stored in the whitelist. 1 - White list entry is Valid 0 - White list entry is Invalid [15:0] read-write TRANSMIT_WINDOW_OFFSET Transmit window offset 0x80 32 read-write 0x0 0xFFFF TX_WINDOW_OFFSET This is used to determine the first anchor point for the master transmission, from the time of connection creation. Range: This shall be a multiple of 1.25 ms in the range of 0 ms to connInterval value. [15:0] read-write TRANSMIT_WINDOW_SIZE Transmit window size 0x84 32 read-write 0x0 0xFF TX_WINDOW_SIZE window_size along with the window_offset is used to calculate the first connection point anchor point for the master. This shall be a multiple of 1.25 ms in the range of 1.25 ms to the lesser of 10 ms and (connInterval - 1.25 ms). Values range from 0 to 10 ms. [7:0] read-write DATA_CHANNELS_L0 Data channel map 0 (lower word) 0x88 32 read-write 0x0 0xFFFF DATA_CHANNELS_L0 This register field indicates which of the data channels are in use. This stores the information for the lower 16 (15:0) data channel indices. '1' indicates the corresponding data channel is used and '0' indicates the channel is unused. [15:0] read-write DATA_CHANNELS_M0 Data channel map 0 (middle word) 0x8C 32 read-write 0x0 0xFFFF DATA_CHANNELS_M0 This register field indicates which of the data channels are in use. This stores the information for the middle 16 (32:16) data channel indices. '1' indicates the corresponding data channel is used and '0' indicates the channel is unused. [15:0] read-write DATA_CHANNELS_H0 Data channel map 0 (upper word) 0x90 32 read-write 0x0 0x1F DATA_CHANNELS_H0 This register field indicates which of the data channels are in use. This stores the information for the upper 5 (36:32) data channel indices. '1' indicates the corresponding data channel is used and '0' indicates the channel is unused. Note: The Data channel map 0 and data channel map 1 are two sets of channel maps stored, common for all the connections. At any given time, only two maps can be maintained and the connections will use one of the two sets as indicated by the channel map index field in the CE_CNFG_STS registers specific to the link. Firmware must also manage to update this field along with the map. [4:0] read-write DATA_CHANNELS_L1 Data channel map 1 (lower word) 0x98 32 read-write 0x0 0xFFFF DATA_CHANNELS_L1 This register field indicates which of the data channels are in use. This stores the information for the lower 16 (15:0) data channel indices. '1' indicates the corresponding data channel is used and '0' indicates the channel is unused. [15:0] read-write DATA_CHANNELS_M1 Data channel map 1 (middle word) 0x9C 32 read-write 0x0 0xFFFF DATA_CHANNELS_M1 This register field indicates which of the data channels are in use. This stores the information for the middle 16 (32:16) data channel indices. '1' indicates the corresponding data channel is used and '0' indicates the channel is unused. [15:0] read-write DATA_CHANNELS_H1 Data channel map 1 (upper word) 0xA0 32 read-write 0x0 0x1F DATA_CHANNELS_H1 This register field indicates which of the data channels are in use. This stores the information for the upper 5 data channel indices. '1' indicates the corresponding data channel is used and '0' indicates the channel is unused. Note: The Data channel map 0 and data channel map 1 are two sets of channel maps stored, common for all the connections. At any given time, only two maps can be maintained and the connections will use one of the two sets as indicated by the channel map index field in the CE_CNFG_STS registers specific to the link. Firmware must also manage to update this field along with the map. [4:0] read-write CONN_INTR Connection interrupt status and Clear register 0xA8 32 read-write 0x0 0xFFFF CONN_CLOSED If this bit is set it indicates that the link is disconnected. If this bit is written with 1, it clears the connection updated interrupt. [0:0] read-write CONN_ESTB If this bit is set it indicates that the connection has been established. The bit is also set when a connection update procedure is complet-ed, at the start of the first anchor point with the updated parameters. If this bit is written with 1, it clears the connection established interrupt. [1:1] read-write MAP_UPDT_DONE If this bit is set it indicates that the channel map update is completed at the instant specified by the firmware. If this bit is written with 1, it clears the map update done interrupt. [2:2] read-write START_CE If this bit is set it indicates that the connection event started interrupt has happened. If this bit is written with 1, it clears the connection event started interrupt. [3:3] read-write CLOSE_CE If this bit is set it indicates that the connection event closed interrupt has happened. If this bit is written with 1, it clears the connection event closed interrupt. [4:4] read-write CE_TX_ACK If this bit is set it indicates that the connection event transmission acknowledgement is received for the previous non-empty packet transmitted. If this bit is written with 1, it clears the ce transmission acknowledgement interrupt. [5:5] read-write CE_RX If this bit is set it indicates that a packet is received in the connection event. If this bit is written with 1, it clears the connection event received interrupt. [6:6] read-write CON_UPDT_DONE This bit is set when the last connection event with previous connec-tion parameters is reached. The bit is set immediately after the re-ceive operation at the anchor point of the last connection event. If this bit is written with 1, it clears the connection updated interrupt. [7:7] read-write DISCON_STATUS Reason for disconnect - indicates the reason the link is disconnected by hardware. 001 - connection failed to be established 010 - supervision timeout 011 - kill connection by host 100 - kill connection after ACK transmitted 101 - PDU response timer expired [10:8] read-only RX_PDU_STATUS Status of PDU received. This information is valid along with receive interrupt. xx1 - Bad Packet (packet with CRC error) 000 - empty PDU 010 - new data (non-empty) PDU 110 - Duplicate Packet [13:11] read-only PING_TIMER_EXPIRD_INTR If this is set, it indicates that ping timer has expired. If this bit is written with 1, it clears the interrupt. [14:14] read-write PING_NEARLY_EXPIRD_INTR If this is set, it indicates that ping timer has nearly expired. If this bit is written with 1, it clears the interrupt. [15:15] read-write CONN_STATUS Connection channel status 0xAC 32 read-only 0x0 0xF000 RECEIVE_PACKET_COUNT This field stores the count for the number of receive packets in the receive FIFO that are still not ready by firmware. The counter value is incremented by hardware for every good packet it stores in the FIFO. After firmware reads a packet, it decrements the counter by issuing the PACKET_RECEIVED command from the commander. [15:12] read-only CONN_INDEX Connection Index register 0xB0 32 read-write 0x0 0xFFFF CONN_INDEX This field is used to index the multiple connections existing. Range is 0 to maximum number of connections supported. For a single connection device, conn_index is 0. [15:0] read-write WAKEUP_CONFIG Wakeup configuration 0xB8 32 read-write 0x0 0xFCFF OSC_STARTUP_DELAY Oscillator stabilization/startup delay. This is in X.Y for-mat where X is in terms of number of BT slots (625 us) and Y is in terms of number of clock periods of 16KHz clock input, required for RF oscillator to stabilize the clock output to the controller on its output pin, after oscillator is turned ON. In this period the clock is as-sumed to be unstable, and so the controller does not turn on the clock to internal logic till this period is over. This means, the wake up from deep sleep mode must account for this delay before the wakeup instant. Osc_startup_delay[7:5] is number of slots(625us) Osc_startup_delay[4:0 is number of clock periods of 16KHz clock (Warning: Min. value of Osc_startup_delay [4:0] sup-ported is 1 and Max. value is 9. Therefore programma-ble range is 1 to 9) [7:0] read-write DSM_OFFSET_TO_WAKEUP_INSTANT Number of 'slots' before the wake up instant before which the hardware needs to exit from deep sleep mode. The slot is of 0.625ms period. This is a onetime configuration field, which is used every time hardware does an auto-wakeup before the next wakeup instant. [15:10] read-write WAKEUP_CONTROL Wakeup control 0xC0 32 read-write 0x0 0xFFFF WAKEUP_INSTANT Instant, with reference to the internal 16-bit clock reference, at which the hardware must wakeup from deep sleep mode. This is calculated by firmware based on the next closest instant where a controller operation is required (like advertiser/scanner). Firmware reads the next instant of the procedures in the corresponding *_NEXT_INSTANT registers. This value is used only when hardware auto wakeup from deep sleep mode is enabled in the clock control register. Note: it is recommended to program wakeup_instant such a way that the actual instant to wakeup shall be at least two counts (two slots of 625 us) ahead of reference clock when entering DSM. The actual instant to wakeup is 'wakeup_instant - dsm_offset_to_wakeup_instant - osc_startup_delay, and it shall be greater than 'reference clock + 2' [15:0] read-write CLOCK_CONFIG Clock control 0xC4 32 read-write 0x80 0xF7FF ADV_CLK_GATE_EN Advertiser block clock gate enable. 1 - enable, 0 - disable. Enables gating of clock to the advertiser module (llh_adv) in hardware. If 1, the sleep mode logic can control the clock gate to shutdown/wakeup the clock to the module. If 0, the logic has no control and clock to the module is always turned ON. [0:0] read-write SCAN_CLK_GATE_EN Scan block clock gate enable. 1 - enable, 0 - disable. Enables gating of clock to the scanner module (llh_scan) in hardware. If 1, the sleep mode logic can control the clock gate to shutdown/wakeup the clock to the module. If 0, the logic has no control and clock to the module is always turned ON. [1:1] read-write INIT_CLK_GATE_EN Initiator block clock gate enable. 1 - enable, 0 - disable. Enables gating of clock to the initiator module (llh_init). If 1, the sleep mode logic can control the clock gate to shutdown/wakeup the clock to the module. If 0, the logic has no control and clock to the module is always turned ON. [2:2] read-write CONN_CLK_GATE_EN Connection block clock gate enable. 1 - enable, 0 - disable. Enables gating of clock to the connection module (llh_connch_top) in hardware. If 1, the sleep mode logic can control the clock gate to shutdown/wakeup the clock to the engine. If 0, the logic has no control and clock to the module is always turned ON. [3:3] read-write CORECLK_GATE_EN Core clock gate enable. 1 - enable, 0 - disable. Enables gating of clock to the llh_core module in hard-ware. If 1, the sleep mode/deep sleep mode logic can control the clock gate to shutdown/wakeup the clock to the module. If 0, the logic has no control and clock is always turned ON. [4:4] read-write SYSCLK_GATE_EN Sysclk gate enable. 1- enable, 0 - disable. Enables clock gating of system clock input to the link layer. If 1, it enables the DSM logic to control the clock gate for system clock input from pin. If 0, the DSM logic has no control and the system clock is always ON. [5:5] read-write PHY_CLK_GATE_EN Digital PHY clock enable. 1- enable, 0-disable. Enable the Digital PHY to shutdown the clock. When 1, it indicates that controller has an upcoming activity so PHY clock must be turned ON. When 0, it indicates inactivity in the controller. [6:6] read-write LLH_IDLE Indicates if hardware is doing any transmit/receive operation. This information is used by firmware to decide to program the hardware into deep sleep mode. 1 - LL hardware is idle. 0 - LL hardware is busy. In this case LL hardware will not enter deep sleep mode, even if firmware gives an enter DSM command. (In this situation hardware generates dsm exit interrupt to inform firmware that DSM entry was not successful). [7:7] read-only LPO_CLK_FREQ_SEL Clock frequency select. 0 - 32KHz, 1 - 32.768KHz. Base frequency of the sleep_clk input used for generat-ing the internal reference clock of approximate 16Khz frequency. [8:8] read-write LPO_SEL_EXTERNAL Select external sleep clock. 1 - External clock, 0 - inter-nal generated clock. The field is used to select either the low power clock in-put on sleep_clk input pin(of frequency 16.384KHz) di-rectly to run the DSM logic or to use the internal gener-ated reference clock(of 16KHz) for the same. [9:9] read-write SM_AUTO_WKUP_EN Enable sleep mode auto wakeup enable. 1- enable, 0 - disable. Enables hardware to automatically wakeup from sleep mode at the instant = wakeup_instant - sm_offset_to_wakeup_instant. The wakeup_insant is the field in the wakeup control register described earlier. The sm_offset_to_wakeup_instant value is the field described in the wakeup configuration register. [10:10] read-write SM_INTR_EN Enable SM exit interrupt. 1 - enable, 0 - disable. Enables hardware to generate an interrupt while exiting sleep mode - irrespective of whether it is initiated by hardware or firmware. The interrupt is captured and stored till it gets cleared. Disabling this bit mask the sleep mode exit event from hardware & firmware. This feature is not available. FW should never set this bit [12:12] read-write DEEP_SLEEP_AUTO_WKUP_DISABLE Disable Auto Wakeup in DEEP_SLEEP mode. 1 - Disable Auto Wakeup 0 - Auto Wakeup enabled [13:13] read-write SLEEP_MODE_EN Enable sleep mode. 1 - enable, 0 - disable. Enables hardware to control sleep mode operation. This feature is not available. FW should never set this bit [14:14] read-write DEEP_SLEEP_MODE_EN Enable deep sleep mode. 1 - enable, 0 - disable. Enables hardware logic related to deep sleep mode to control the deep sleep mode operation. If disabled, the related logic is not executed and hardware cannot enter deep sleep mode. [15:15] read-write TIM_COUNTER_L Reference Clock 0xC8 32 read-only 0x0 0xFFFF TIM_REF_CLOCK 16-bit internal reference clock. The clock is a free run-ning clock, incremented by a 0.625ms periodic pulse. It is used as a reference clock to derive all the timing required as per protocol. [15:0] read-only WAKEUP_CONFIG_EXTD Wakeup configuration extended 0xCC 32 read-write 0x0 0x1F DSM_LF_OFFSET Number of 'LF slots' before the wake up instant before which the hardware needs to exit from deep sleep mode. The LF slot is of 62.5us period. This is a onetime configuration field, which is used every time hardware does an auto-wakeup before the next wakeup instant. This is in addition to the LF slots calculated by HW window widening logic. [4:0] read-write POC_REG__TIM_CONTROL BLE Time Control 0xD8 32 read-write 0x0 0xFF8 BB_CLK_FREQ_MINUS_1 LLH clock configuration. The clock frequency of the clock input to this design is configured in this register. This is used to derive a 1MHz clock. [7:3] read-write START_SLOT_OFFSET LLH clock configuration. The start of slot signal is offset by this value. If value is 0, the start of slot signal is generated at the 625us. The offset value is in terms of us. [11:8] read-write ADV_TX_DATA_FIFO Advertising data transmit FIFO. Access ADVCH_TX_FIFO. 0xE0 32 read-write 0x0 0xFFFF ADV_TX_DATA IO mapped FIFO of depth 16 (2 byte wide), to store ADV data of maximum length 31 bytes for transmitting. Firmware writes consecutive words by writing to the same address location. Note: ADV_TX_DATA_FIFO and ADV_SCN_RSP_TX_FIFO shares same physical FIFO of depth 32. 16 locations for each FIFO are allocated. Reading this location resets the FIFO pointer. [15:0] read-write ADV_SCN_RSP_TX_FIFO Advertising scan response data transmit FIFO. Access ADVCH_TX_FIFO. 0xE8 32 read-write 0x0 0xFFFF SCAN_RSP_DATA IO mapped FIFO of depth 16 (2 byte wide), to store scan response data of maximum length 31 bytes for transmitting. Firmware writes consecutive words by writing to the same location. Note: ADV_TX_DATA_FIFO and ADV_SCN_RSP_TX_FIFO shares same physical FIFO of depth 32. 16 locations for each FIFO are allocated. Reading this location resets the FIFO pointer. [15:0] read-write INIT_SCN_ADV_RX_FIFO advertising scan response data receive data FIFO. Access ADVRX_FIFO. 0xF8 32 read-only 0x0 0xFFFF ADV_SCAN_RSP_RX_DATA IO mapped FIFO of depth 64, to store ADV and SCAN_RSP header and payload received by the scanner. The RSSI value at the time of reception of this packet is also stored. Firmware reads from the same address to read out consecutive words of data. Note: The 16 bit header is first loaded to the advertise channel data receive FIFO followed by the payload data and then 16 bit RSSI. [15:0] read-only CONN_INTERVAL Connection Interval 0x100 32 read-write 0x0 0xFFFF CONNECTION_INTERVAL The value configured in this register determines the spacing be-tween the connection events. This shall be a multiple of 1.25 ms in the range of 7.5 ms to 4.0 s. [15:0] read-write SUP_TIMEOUT Supervision timeout 0x104 32 read-write 0x0 0xFFFF SUPERVISION_TIMEOUT This field defines the maximum time between two received Data packet PDUs before the connection is considered lost. This shall be a multiple of 10 ms in the range of 100 ms to 32.0 s and it shall be larger than (1+connSlaveLatency)*connInterval. [15:0] read-write SLAVE_LATENCY Slave Latency 0x108 32 read-write 0x0 0xFFFF SLAVE_LATENCY The value configured in this field defines the number of consecutive connection events that the slave device is not required to listen for master. The value of connSlaveLatency should not cause a Supervision Timeout. This shall be an integer in the range of 0 to ((connSupervision Timeout/connInterval)-1). connSlaveLatency shall also be less than 500. [15:0] read-write CE_LENGTH Connection event length 0x10C 32 read-write 0x0 0xFFFF CONNECTION_EVENT_LENGTH This field defines the length of Connection event. This value is derived from the CE length HCI parameters received from the host. This determines the number of master transmit slots in a connection event, subject to either of the MD bits being set. If both MD bits are set to 0, this has no effect. Units: 625us Note: The connection event length as specified by the CE_LENGTH shall not exceed CONN_INTERVAL - 1.25 ms. The CE-length parameter, according to the Bluetooth specification, is the length of the connection event. Take an example to illustrate this scenario: Assume a connection with interval = 100ms. that the application has put allowed 20ms of CE-length. Here, the CE-length can be upto 100ms (100ms - 150us to be exact). If the connection is maintained for 5 minutes, there could be 10*60*5 = 3000 connection-intervals. The CE-length need not be maintained constant during all the 3000 connection events. Here are the typical cases that determine the value of CE-length: (1) No data packets exchanged. we are just maintaining time and frequency synchronization. In this case, only a packet pair will be exchanged every connection interval. Here, CE-length = 1. (2) Average of 10 packets to be sent per connection event. We can pump data in multiple ways here: 2.1: Send data at uniform rate : In this case, the CE-length will be enough to accommodate 10 packets, which will take about 7ms. As this is less than application enforced limit of 20ms, we can comfortably push all the 10 data packets in this connection interval. So data will be pumped to the other BT device at the same rate as is received from my application. 2.2: Can send data in bursts. Assume that we accumulate data for 1 second and pump out at the end of 1 second(this is not done by our Bluetooth stack, the application needs to buffer the data). So, at 10th connection interval, we have 100 packets accumulated. We are now ready to pump this data. 100 packets take about 70 ms. This is above the application enforced 20ms. So, the hardware can pump data that can fill up 20ms. The remaining data will be deferred to the next connection interval. So, in this case, you would see a CE-length spread over time like this (Per connection interval): 0,0,0,0,0,0,0,0,0,0, 20,20,20,10,0,0,0,0,0,0, 20,20,20,10,0,0,0,0,0,0, 20,20,20,10,0,0,0,0,0,0, and so on. (3) We are receiving data at the same rate as in (2). This case is to honor data sent by the other BT-device by giving it more time in the current connection interval. In (2) and (3) you will see non-empty packets either transmitted or received. We can also utilize the CE-length for different reasons: (4) A transaction is in progress, and we are expecting a response packet very soon. In this case, we may be exchanging only empty packets now, and in the next few packet-pairs. In this case, you will the CE-length to be large, and a non-empty packet may not be exchanged in all the slots. [15:0] read-write PDU_ACCESS_ADDR_L_REGISTER Access address (lower) 0x110 32 read-write 0x0 0xFFFF PDU_ACCESS_ADDRESS_LOWER_BITS This field defines the lower 16 bits of the access address for each Link layer connection between any two devices. [15:0] read-write PDU_ACCESS_ADDR_H_REGISTER Access address (upper) 0x114 32 read-write 0x0 0xFFFF PDU_ACCESS_ADDRESS_HIGHER_BITS This field defines the higher 16 bits of the access address for each Link layer connection between any two devices. [15:0] read-write CONN_CE_INSTANT Connection event instant 0x118 32 read-write 0x0 0xFFFF CE_INSTANT This is the value of the free running Connection Event counter when the new parameters of 'connection update' and/or 'Channel map update' will be effective. Range : 0x0000 to 0xFFFF [15:0] read-write CE_CNFG_STS_REGISTER connection configuration & status register 0x11C 32 read-write 0x0 0xF5FF DATA_LIST_INDEX_LAST_ACK_INDEX Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded. The default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4. Hardware will start the next data transmission from the index indicated by this field. [3:0] read-write DATA_LIST_HEAD_UP Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause. The bit must be toggled every time the firmware needs to indicate the start/resume. This requires a read modify write operation. [4:4] read-write SPARE This bit is unused [5:5] read-write MD MD bit set to '1' indicates device has more data to be sent. [6:6] read-write MAP_INDEX__CURR_INDEX Written by firmware to select the map index to be used by hardware for this connection. 1 - use channel map register set 1. 0 - use channel map register set 0. When firmware reads this field, it returns the current map index being used in hardware. [7:7] read-write PAUSE_DATA Pause data. 1 - pause data, 0 - do not pause. The current_pdu_index in hardware does not move to next in-dex until pause_data is cleared. But if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out [8:8] read-write CONN_ACTIVE This bit is '1' whenever the connection is active. [10:10] read-only CURRENT_PDU_INDEX The index of the transmit packet buffer that is currently in transmission/waiting for transmission. [15:12] read-only NEXT_CE_INSTANT Next connection event instant 0x120 32 read-only 0xFFFF 0xFFFF NEXT_CE_INSTANT 16-bit internal reference clock value at which the next connection event will occur on a connection. The connection index register must be programmed with index of the connection, before reading the register. The reset value is 0x0000. After reset deassertion, then the very next clock, the value assigned to the registers is 0xFFFF. [15:0] read-only CONN_CE_COUNTER connection event counter 0x124 32 read-only 0x0 0xFFFF CONNECTION_EVENT_COUNTER This is the free running counter, connEventCounter as defined by Bluetooth spec. Firmware will read the instantaneous Event counter from this register, during connection update and channel map update procedure. Firmware will use this value to calculate the instant from which the new parameters (for connection update and channel map update) will be effective. [15:0] read-only DATA_LIST_SENT_UPDATE__STATUS data list sent update and status 0x128 32 read-write 0x0 0x8F LIST_INDEX__TX_SENT_3_0 Write:Indicates the buffer index for which the SENT bit is being updated by firmware. The default number of buffers in the IP is 4. The index range is 0-3. Read: Reads TX_SENT[3:0]. The bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are 1 - queued 0 - no packet / packet ack received by hardware Example1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement. NOTE: The SENT status bit and ACK status bit have to be taken together to understand the meaning of packet status. The table below describes how the two bits are sequentially updated by either hardware/firmware to complete one data transmission. SENT ACK Description 0 0 Buffer is empty. No packet is queued in the buffer 1 0 Packet is queued by firmware. 1 1 Packet is transmitted by hardware. Hardware is waiting for acknowledgement. 0 1 Hardware has received ACK. Firmware has not yet processed the ACK. 0 0 Firmware has processed the ack. The buffer is again empty. [3:0] read-write SET_CLEAR Write: Used to set the SENT bit in hardware for the selected packet buffer. 1 - packet queued When firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted. The SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device. Firmware typically does not clear the bit. However, It only clears the bit on its own if it needs to 'flush' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified. [7:7] write-only DATA_LIST_ACK_UPDATE__STATUS data list ack update and status 0x12C 32 read-write 0x0 0x8F LIST_INDEX__TX_ACK_3_0 Write: Indicates the buffer index for which the ACK bit is being updated by firmware. The default number of buffers in the IP is 5. The index range is 0-4. Read: Reads TX_ACK[3:0] If a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement. Example1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware. Example2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware. NOTE: The SENT status bit and ACK status bit have to be taken together to understand the meaning of packet status. The table below describes how the two bits are sequentially updated by either hardware/firmware to complete one data transmission. SENT ACK Description 0 0 Buffer is empty. No packet is queued in the buffer 1 0 Packet is queued by firmware. 1 1 Packet is transmitted by hardware. Hardware is waiting for acknowledgement. 0 1 Hardware has received ACK. Firmware has not yet processed the ACK. 0 0 Firmware has processed the ack. The buffer is again empty. [3:0] read-write SET_CLEAR Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware. Firmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware. For clearing ack for a packet transmitted in fifo-index : '3', firm-ware will write '3' in the 'list-index' field and set this bit (BIT7) to 0. This is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on. The ACK bit in hardware is set by hardware when it has success-fully transmitted a packet. [7:7] write-only CE_CNFG_STS_REGISTER_EXT connection configuration & status register 0x130 32 read-write 0x0 0x3F0F TX_2M transmittion on 2M [0:0] read-write RX_2M receiving on 2M [1:1] read-write SN Sequence number for next scheduled connection index [2:2] read-write NESN Next Sequence number for next scheduled connection index [3:3] read-write LAST_UNMAPPED_CHANNEL Last unmapped channel for next scheduled connection index [13:8] read-write CONN_EXT_INTR Connection extended interrupt status and Clear register 0x134 32 read-write 0x0 0x7 DATARATE_UPDATE If this bit is set it indicates that the data rate is updated If this bit is written with 1, it clears the interrupt status bit [0:0] read-write EARLY_INTR For master this bit is set on start_ce For Slave this bit is set on slave_timer_adj [1:1] read-write GEN_TIMER_INTR If this bit is set it indicates that the generic timer (PDU response timer reconfigured in MMMS mode) has expired If this bit is written with 1, it clears the interrupt status bit [2:2] read-write CONN_EXT_INTR_MASK Connection Extended Interrupt mask 0x138 32 read-write 0x0 0x7 DATARATE_UPDATE If this bit is set connection data rate update interrupt is enabled. [0:0] read-write EARLY_INTR If this bit is set connection early interrupt is enabled. [1:1] read-write GEN_TIMER_INTR Generic timer (PDU response timer reconfigured in MMMS mode) expiry interrupt [2:2] read-write 5 4 DATA_MEM_DESCRIPTOR[%s] Data buffer descriptor 0 to 4 0x140 32 read-write 0x0 0x3FF LLID N/A [1:0] read-write DATA_LENGTH This field indicates the length of the data packet. Bits [9:7] are valid only if DLE is set. Range 0x00 to 0xFF. [9:2] read-write WINDOW_WIDEN_INTVL Window widen for interval 0x160 32 read-write 0xA 0xFFF WINDOW_WIDEN_INTVL This value defines the increased listening time for the slave. The window widening shall be smaller than ((connInterval/2)-T_IFS us) This value is calculated by firmware based on the drift, the connec-tion interval value. The value is the unit widening value for one con-nection interval duration. In case of slave latency, this value is accu-mulated till the next anchor point at which the slave will listen. [11:0] read-write WINDOW_WIDEN_WINOFF Window widen for offset 0x164 32 read-write 0xA 0xFFF WINDOW_WIDEN_WINOFF This field stores the additional number of microseconds the slave must extend its listening window to listen for a master packet. This value is calculated based on the window offset value. This is used at connection setup directly. During connection setup, this value is added with window_widen_intvl register value to calculate the win-dow widening size. [11:0] read-write LE_RF_TEST_MODE Direct Test Mode control 0x170 32 read-write 0x0 0xA3FF TEST_FREQUENCY N = (F - 2402) / 2 Range: 0x00 - 0x27. Frequency Range : 2402 MHz to 2480 MHz [5:0] read-write DTM_STATUS__DTM_CONT_RXEN This bit is overloaded. The read operation returns the staus of the DTM 1 - DTM test ON 0 - DTM test OFF The write operation contrls the DTM RX mode 0: DTM run at normal DTMRX burst mode 1: DTM run at continuous RX DTM mode [6:6] read-write PKT_PAYLOAD N/A [9:7] read-write DTM_CONT_TXEN 0: DTM run at normal DTMTX burst mode 1: DTM run at continuous TX DTM mode [13:13] read-write DTM_DATA_2MBPS 0: DTM run at 1M bps data rate 1: DTM run at 2M bps data rate [15:15] read-write DTM_RX_PKT_COUNT Direct Test Mode receive packet count 0x174 32 read-only 0x0 0xFFFF RX_PACKET_COUNT Number of packets received in receive test mode. [15:0] read-only LE_RF_TEST_MODE_EXT Direct Test Mode control 0x178 32 read-write 0x0 0xFF DTM_PACKET_LENGTH DTM TX packet length. Bits [7:6] are accessible onle when DLE is enabled [7:0] read-write TXRX_HOP Channel Address register 0x188 32 read-only 0x0 0x7F7F HOP_CH_TX Transmit channel index. Channel index on which previous packet is transmitted. [6:0] read-only HOP_CH_RX Receive channel index. Channel index on which previous packet is received. [14:8] read-only TX_RX_ON_DELAY Transmit/Receive data delay 0x190 32 read-write 0x0 0xFFFF RXON_DELAY Receive delay - Delay from start of receive to expected first bit of receive packet at the controller. Used to control the turn on time of radio to optimize on power. The delay is in resolution of 1 microsecond. [7:0] read-write TXON_DELAY Transmit delay - Delay from start of transmit to transmission of first bit on air. It is used to control the T_IFS. The delay is in resolution of 1 microsecond. [15:8] read-write ADV_ACCADDR_L ADV packet access code low word 0x1A8 32 read-write 0xBED6 0xFFFF ADV_ACCADDR_L Lower 16 bit of ADV packet access code [15:0] read-write ADV_ACCADDR_H ADV packet access code high word 0x1AC 32 read-write 0x8E89 0xFFFF ADV_ACCADDR_H higher 16 bit of ADV packet access code [15:0] read-write ADV_CH_TX_POWER_LVL_LS Advertising channel transmit power setting 0x1B0 32 read-write 0x0 0xFFFF ADV_TRANSMIT_POWER_LVL_LS When LL_CONFIG.TX_PA_PWR_LVL_TYPE is 1, this field represents the Advertising channel transmit power setting Least Significant 16 bits. When LL_CONFIG.TX_PA_PWR_LVL_TYPE is 0, the LS 4 bits represents the Advertising channel transmit power code 4 bits. [15:0] read-write ADV_CH_TX_POWER_LVL_MS Advertising channel transmit power setting extension 0x1B4 32 read-write 0x0 0x3 ADV_TRANSMIT_POWER_LVL_MS Advertising channel transmit power setting Most Significant 2 bits. [1:0] read-write CONN_CH_TX_POWER_LVL_LS Connection channel transmit power setting 0x1B8 32 read-write 0x0 0xFFFF CONNCH_TRANSMIT_POWER_LVL_LS When LL_CONFIG.TX_PA_PWR_LVL_TYPE is 1, this field represents the Connection channel transmit power setting Least Significant 16 bits. When LL_CONFIG.TX_PA_PWR_LVL_TYPE is 0, the LS 4 bits represents the Connection channel transmit power code 4 bits. [15:0] read-write CONN_CH_TX_POWER_LVL_MS Connection channel transmit power setting extension 0x1BC 32 read-write 0x0 0x3 CONNCH_TRANSMIT_POWER_LVL_MS Connection channel transmit power setting Most Significant 2 bits. [1:0] read-write DEV_PUB_ADDR_L Device public address lower register 0x1C0 32 read-write 0x3412 0xFFFF DEV_PUB_ADDR_L Lower 16 bit of 48-bit public address of the device. [15:0] read-write DEV_PUB_ADDR_M Device public address middle register 0x1C4 32 read-write 0x56 0xFFFF DEV_PUB_ADDR_M Middle 16 bit of 48-bit public address of the device. [15:0] read-write DEV_PUB_ADDR_H Device public address higher register 0x1C8 32 read-write 0x0 0xFFFF DEV_PUB_ADDR_H Higher 16 bit of 48-bit public address of the device. [15:0] read-write OFFSET_TO_FIRST_INSTANT Offset to first instant 0x1D0 32 read-write 0x6 0xFFFF OFFSET_TO_FIRST_EVENT The offset w.r.t the internal reference clock at which instant the first event occurs. This register will give flexibility to the firmware to position the con-nection at a desired point with respect to the internal free running clock. It is optional to be updated by firmware. This is not updated in the current firmware. [15:0] read-write ADV_CONFIG Advertiser configuration register 0x1D4 32 read-write 0x20FF 0xFFFF ADV_STRT_EN Enable advertising event start interrupt. [0:0] read-write ADV_CLS_EN Enable advertising event stop interrupt. [1:1] read-write ADV_TX_EN Enable adv packet transmitted interrupt. [2:2] read-write SCN_RSP_TX_EN Enable scan response packet transmitted interrupt. [3:3] read-write ADV_SCN_REQ_RX_EN Enable scan request packet received interrupt. [4:4] read-write ADV_CONN_REQ_RX_EN Enable connect request packet received interrupt. [5:5] read-write SLV_CONNECTED_EN Enable slave connected interrupt. [6:6] read-write ADV_TIMEOUT_EN Enable adv_timeout interrupt. Applicable in adv_direct_ind advertising. [7:7] read-write ADV_RAND_DISABLE Disable randomization of adv interval. When disabled, interval is same as programmed in adv_interval register. [8:8] read-write ADV_SCN_PEER_RPA_UNMCH_EN Enable scan request packet received with peer device address unmatched interrupt. This bit is valid only if PRIV_1_2 PRIV_1_2 and PRIV_1_2_ADV are set. [9:9] read-write ADV_CONN_PEER_RPA_UNMCH_EN Enable connect request packet received with peer device address unmatched interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. [10:10] read-write ADV_PKT_INTERVAL Time between the beginning of two consecutive advertising PDU's. Time = N * 0.625 msec Time Range: <=10msec. [15:11] read-write SCAN_CONFIG Scan configuration register 0x1D8 32 read-write 0xE01F 0xE9FF SCN_STRT_EN Enable scan event start interrupt. [0:0] read-write SCN_CLOSE_EN Enable scan event close interrupt. [1:1] read-write SCN_TX_EN Enable scan request packet transmitted interrupt. [2:2] read-write ADV_RX_EN Enable adv packet received interrupt . [3:3] read-write SCN_RSP_RX_EN Enable scan_rsp packet received interrupt . [4:4] read-write SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN Enable ADV peer address unmatched interrupt. This bit is valid only if PRIV_1_2 PRIV_1_2 and PRIV_1_2_SCAN are set. [5:5] read-write SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN Enable ADV self address unmatched interrupt. This bit is valid only if PRIV_1_2 PRIV_1_2 and PRIV_1_2_SCAN are set. [6:6] read-write SCANA_TX_ADDR_NOT_SET_INTR_EN Enable SCANA RPA TX not set interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. [7:7] read-write RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN This bit controls the SCAN engine behavior when an self address match occurs but a privacy mismatch occurs 0 - The packet is aborted 1 - The packet is received and reported to the Link Layer firmware This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. [8:8] read-write BACKOFF_ENABLE Enable random backoff feature in scanner. 1 - enable 0 - disable [11:11] read-write SCAN_CHANNEL_MAP Advertising channels that are enabled for scanning operation. Bit 15: setting 1 - enables channel 39 for use. Bit 14: setting 1 - enables channel 38 for use. Bit 13: setting 1 - enables channel 37 for use. [15:13] read-write INIT_CONFIG Initiator configuration register 0x1DC 32 read-write 0x0 0xE0F7 INIT_STRT_EN Enable Initiator event start interrupt. [0:0] read-write INIT_CLOSE_EN Enable Initiator event close interrupt. [1:1] read-write CONN_REQ_TX_EN Enables connection request packet transmission start interrupt. [2:2] read-write CONN_CREATED Enable master connection created interrupt [4:4] read-write INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN Enable ADV self address RPA unresolved interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set. [5:5] read-write INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN Enable ADV peer address RPA unresolved interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set. [6:6] read-write INITA_TX_ADDR_NOT_SET_INTR_EN Enable INITA RPA TX not set interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set. [7:7] read-write INIT_CHANNEL_MAP Advertising channels that are enabled for initiator scanning operation. Bit 15: setting 1 - enables channel 39 for use. Bit 14: setting 1 - enables channel 38 for use. Bit 13: setting 1 - enables channel 37 for use. [15:13] read-write CONN_CONFIG Connection configuration register 0x1E0 32 read-write 0xE11F 0xF9FF RX_PKT_LIMIT Defines a limit for the number of Rx packets that can be re-ceived by the LLH. Default maximum value is 0xF.Minimum value shall be '1' or no packet will be stored in the Rx FIFO. [3:0] read-write RX_INTR_THRESHOLD This register field allows setting a threshold for the packet received interrupt to the firmware. For example if the value programmed is 0x2 - then HW will generate interrupt only on receiving the second packet. In any case if the received number of packets in a conn event is less than the threshold or there are still packets (less than threshold) pending in the Rx FIFO, HW will generate the interrupt at the ce_close. Min value possible is 1. Max value depends on the Rx FIFO capacity. [7:4] read-write MD_BIT_CLEAR This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or, 'hardware and soft-ware logic combined'. 1 - MD bit is exclusively controlled by software, ie based on status of CE_CNFG_STS_REGISTER[6] - md bit. 0 - MD Bit in the transmitted pdu is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the md bit in CE_CNFG_STS_REGISTER[6] and either of the following conditions is true, a) If there are packets queued for transmission. b) If there is an acknowledgement awaited from the remote side for the packet transmitted. [8:8] read-write DSM_SLOT_VARIANCE This bit configures the DSM slot counting mode. 0 - The DSM slot count variance with respect to actual time is less than 1 slot 1 - The DSM slot count variance with respect to actual time is more than 1 slot &less that 2 slots [11:11] read-write SLV_MD_CONFIG This bit is set to configure the MD bit control when IUT is in slave role. 1 - MD bit will be decided on packet pending status 0 - MD bit will be decided on packet queued in next buffer status This bit has effect only when 'CONN_CONFIG.md_bit_ctr' bit is not set . [12:12] read-write EXTEND_CU_TX_WIN This bit is used to enable/disable extending the additional rx window on slave side during connection update in event of packet miss at the update instant. 1 - Enable 0 - Disable [13:13] read-write MASK_SUTO_AT_UPDT This bit is used to enable/disable masking of internal hardware supervision timeout trigger when switching from old connection parameters to new parameters. 1 - Enable 0 - Disable [14:14] read-write CONN_REQ_1SLOT_EARLY This bit is used to enable extension of the Conn Request to arbiter to 1 slot early. When enabled the request length is 2 slots. 1 - Enable 0 - Disable [15:15] read-write CONN_PARAM1 Connection parameter 1 0x1E8 32 read-write 0x0 0xFFFF SCA_PARAM Sleep Clock Accuracy [2:0] read-write HOP_INCREMENT_PARAM Hop increment for connection channel. [7:3] read-write CRC_INIT_L This field defines the lower byte (7:0) of the CRC initialization vector. [15:8] read-write CONN_PARAM2 Connection parameter 2 0x1EC 32 read-write 0x0 0xFFFF CRC_INIT_H This field defines the upper two bytes (23:8) of the CRC initialization vector. [15:0] read-write CONN_INTR_MASK Connection Interrupt mask 0x1F0 32 read-write 0x2000 0xE3FF CONN_CL_INT_EN If this bit is set connection closed interrupt is enabled. [0:0] read-write CONN_ESTB_INT_EN If this bit is set connection establishment interrupt is enabled. [1:1] read-write MAP_UPDT_INT_EN If this bit is set, channel map update interrupt is enabled. [2:2] read-write START_CE_INT_EN If this bit is set connection event start interrupt is enabled [3:3] read-write CLOSE_CE_INT_EN If this bit is set connection event closed interrupt is enabled. [4:4] read-write CE_TX_ACK_INT_EN If this bit is set transmission acknowledgement interrupt is enabled: This interrupt is generated to indicate to the firmware that a non-empty packet transmitted is successfully acknowledged by the remote device. For negative acknowledgements from remote device, this interrupt indication is not generated. [5:5] read-write CE_RX_INT_EN If this bit is set interrupt is enabled for reception of packet in a connection event. [6:6] read-write CONN_UPDATE_INTR_EN If this bit is set connection update interrupt is enabled. [7:7] read-write RX_GOOD_PDU_INT_EN If this bit is set packet receive good pdu interrupt is enabled. Effective only when bit 6 is set. [8:8] read-write RX_BAD_PDU_INT_EN If this bit is set packet receive bad pdu interrupt is enabled. Effective only when bit 6 is set. [9:9] read-write CE_CLOSE_NULL_RX_INT_EN If this but us set, the RX interrupt is triggerred for an end of connection event with a null packet [13:13] read-write PING_TIMER_EXPIRD_INTR If this bit is set ping timer expired interrupt is enabled. [14:14] read-write PING_NEARLY_EXPIRD_INTR If this bit is set ping timer nearly expired interrupt is enabled [15:15] read-write SLAVE_TIMING_CONTROL slave timing control 0x1F4 32 read-write 0xBE96 0xFFFF SLAVE_TIME_SET_VAL Programmable adjust value to the clock counter when slave is connected [7:0] read-write SLAVE_TIME_ADJ_VAL Timing adjust value. The internal micro second counter is adjusted to this value whenever slave receives a good access address match at connection anchor point. This will ensure the slave gets synchronized to master timing. [15:8] read-write RECEIVE_TRIG_CTRL Receive trigger control 0x1F8 32 read-write 0x0 0xFF3F ACC_TRIGGER_THRESHOLD Access address match threshold value. Number of bits of ac-cess address that should match with the expected access ad-dress to trigger an access code match. Max value : 32 (for 32-bit access address) Lower values may be programmed for bad radios or channels but care must be taken to ensure there are no 'false' matches due to reduced number of bits required to match. [5:0] read-write ACC_TRIGGER_TIMEOUT If access address match does not occur then within this time from the start of receive operation, the receive operation times out and stops. An internal counter value of 1usec resolution is continuously compared with the value programmed. Max value :0xFF [15:8] read-write LL_DBG_1 LL debug register 1 0x200 32 read-only 0x0 0x3FF CONN_RX_WR_PTR Connection receive FIFO write pointer [9:0] read-only LL_DBG_2 LL debug register 2 0x204 32 read-only 0x0 0x3FF CONN_RX_RD_PTR Connection receive FIFO read pointer [9:0] read-only LL_DBG_3 LL debug register 3 0x208 32 read-only 0x0 0x3FF CONN_RX_WR_PTR_STORE Connection receive FIFO stored write pointer for pointer restore [9:0] read-only LL_DBG_4 LL debug register 4 0x20C 32 read-only 0x0 0x7FF CONNECTION_FSM_STATE Connection FSM state [3:0] read-only SLAVE_LATENCY_FSM_STATE Slave Latency FSM state [5:4] read-only ADVERTISER_FSM_STATE Advertiser FSM state [10:6] read-only LL_DBG_5 LL debug register 5 0x210 32 read-only 0x0 0x3FF INIT_FSM_STATE Initiator FSM state [4:0] read-only SCAN_FSM_STATE Scanner FSM state [9:5] read-only LL_DBG_6 LL debug register 6 0x214 32 read-only 0x0 0x3FFF ADV_TX_WR_PTR Advertiser Transmit FIFO write pointer [3:0] read-only SCAN_RSP_TX_WR_PTR Scan Response Transmit FIFO write pointer [7:4] read-only ADV_TX_RD_PTR Advertiser/ Scan Response FIFO read pointer [13:8] read-only LL_DBG_7 LL debug register 7 0x218 32 read-only 0x0 0x3FFF ADV_RX_WR_PTR Advertiser Receive FIFO write pointer [6:0] read-only ADV_RX_RD_PTR Advertiser Receive FIFO read pointer [13:7] read-only LL_DBG_8 LL debug register 8 0x21C 32 read-only 0x0 0x3FFF ADV_RX_WR_PTR_STORE Advertiser Receive FIFO stored write pointer for pointer restore [6:0] read-only WLF_PTR Whitelist FIFO pointer [13:7] read-only LL_DBG_9 LL debug register 9 0x220 32 read-only 0x10 0xFFFF WINDOW_WIDEN Window Widening value in us. The reset value of this register is 0x0000. After reset de-assertion, at the first clock cycle, the value 0x0010 is assigned to the register. [15:0] read-only LL_DBG_10 LL debug register 10 0x224 32 read-only 0x0 0x3F RF_CHANNEL_NUM Active channel number [5:0] read-only PEER_ADDR_INIT_L Lower 16 bit address of the peer device for INIT. 0x230 32 read-write 0x0 0xFFFF PEER_ADDR_L Lower 16 bit of 48-bit address of the peer device. This is used only in MMMS mode The peer address registers are used for multiple purposes. The register is written by firmware to provide the peer address to be used for a hardware procedure. When firmware reads the register, it reads back peer address values updated by hardware. While device is configured as an initiator without white list filtering, the peer address specified in the peer_address field of the create connection command is programmed into this register, which is used by hard-ware procedures. While device is configured as an initiator and white list is enabled, firmware can read this register to get the address of the peer device from which connectable ADV packet was received and to which the connection is created. [15:0] read-write PEER_ADDR_INIT_M Middle 16 bit address of the peer device for INIT. 0x234 32 read-write 0x0 0xFFFF PEER_ADDR_M Middle 16 bit of 48-bit address of the peer device. This is used only in MMMS mode The peer address registers are used for multiple purposes. The register is written by firmware to provide the peer address to be used for a hardware procedure. When firmware reads the register, it reads back peer address values updated by hardware. While device is configured as an initiator without white list filtering, the peer address specified in the peer_address field of the create connection command is programmed into this register, which is used by hard-ware procedures. While device is configured as an initiator and white list is enabled, firmware can read this register to get the address of the peer device from which connectable ADV packet was received and to which the connection is created. [15:0] read-write PEER_ADDR_INIT_H Higher 16 bit address of the peer device for INIT. 0x238 32 read-write 0x0 0xFFFF PEER_ADDR_H Higher 16 bit of 48-bit address of the peer device. This is used only in MMMS mode The peer address registers are used for multiple purposes. The register is written by firmware to provide the peer address to be used for a hardware procedure. When firmware reads the register, it reads back peer address values updated by hardware. While device is configured as an initiator without white list filtering, the peer address specified in the peer_address field of the create connection command is programmed into this register, which is used by hard-ware procedures. While device is configured as an initiator and white list is enabled, firmware can read this register to get the address of the peer device from which connectable ADV packet was received and to which the connection is created. [15:0] read-write PEER_SEC_ADDR_ADV_L Lower 16 bits of the secondary address of the peer device for ADV_DIR. 0x23C 32 read-write 0x0 0xFFFF PEER_SEC_ADDR_L Lower 16 bit of 48-bit secondary address of the peer device for ADV_DIR. [15:0] read-write PEER_SEC_ADDR_ADV_M Middle 16 bits of the secondary address of the peer device for ADV_DIR. 0x240 32 read-write 0x0 0xFFFF PEER_SEC_ADDR_M Middle 16 bit of 48-bit secondary address of the peer device for ADV_DIR. [15:0] read-write PEER_SEC_ADDR_ADV_H Higher 16 bits of the secondary address of the peer device for ADV_DIR. 0x244 32 read-write 0x0 0xFFFF PEER_SEC_ADDR_H Higher 16 bit of 48-bit secondary address of the peer device for ADV_DIR. While doing directed Advertising in device privacy mode, if the peer device has shared its IRK, then the peer device RPA is written into the PEER_ADDR registers and the peer device identity address is written into this register. If the peer device has not shared its IRK, then the peer identity address is written into the PEER_ADDR registers and this register must be cleared. [15:0] read-write INIT_WINDOW_TIMER_CTRL Initiator Window NI timer control 0x248 32 read-write 0x0 0x1 INIT_WINDOW_OFFSET_SEL Controls the INIT Window offset source 1 - Pick INIT Window Offset from HW calculated INIT_WINDOW_OFFSET 0 - Pick INIT Window Offset from FW loaded register [0:0] read-write CONN_CONFIG_EXT Connection extended configuration register 0x24C 32 read-write 0xA000 0xFF7F CONN_REQ_2SLOT_EARLY This bit is used to enable extension of the Conn Request to arbiter to 2 slot early. When enabled the request length is 3 slots, irrespective of the status of CONN_REQ_1SLOT_EARLY bit. 1 - Enable 0 - Disable [0:0] read-write CONN_REQ_3SLOT_EARLY This bit is used to enable extension of the Conn Request to arbiter to 3 slot early. When enabled the request length is 4 slots, irrespective of the status of CONN_REQ_1SLOT_EARLY & CONN_REQ_2SLOT_EARLY bits. 1 - Enable 0 - Disable [1:1] read-write FW_PKT_RCV_CONN_INDEX Connection Index for which the FW generates Packet Received Command. In MMMS mode, FW should write this field before giving PKT_RECEIVE_COMMAND to HW. [6:2] read-write MMMS_RX_PKT_LIMIT Receive Packet Limit for MMMS mode. This is the RX_FIFO Limit and applies to all connections together [13:8] read-write DEBUG_CE_EXPIRE MMMS CE expire control bit [14:14] read-write MT_PDU_CE_EXPIRE MMMS empty PDU CE expire handling control bit [15:15] read-write DPLL_CONFIG DPLL & CY Correlator configuration register 0x258 32 read-write 0x0 0xFFFF DPLL_CORREL_CONFIG If MXD_IF_OPTION is 0: Not used If CY_CORREL_EN is 1: [11:0] CY correl Access address compare mask for LSB 12 bits. Ideal value is 0xFFF [15:12] CY correl maximum number of allowed mismatched bits in access address. Ideal value is 0x0. [15:0] read-write INIT_NI_VAL Initiator Window NI instant 0x260 32 read-write 0x0 0xFFFF INIT_NI_VAL Initiator window Next Instant value used for spacing Master connections in time, to minimize connection contention. This value is in 625us slots. The read value corresponds to the hardware updated Interval value [15:0] read-write INIT_WINDOW_OFFSET Initiator Window offset captured at conn request 0x264 32 read-only 0x0 0xFFFF INIT_WINDOW_NI Initiator Window offset captured at conn request. This value is in 1.25ms slots [15:0] read-only INIT_WINDOW_NI_ANCHOR_PT Initiator Window NI anchor point captured at conn request 0x268 32 read-only 0x0 0xFFFF INIT_INT_OFF_CAPT Initiator interval offset captured at conn request. The value indicates the master connection anchor point. This value is in 625us slots [15:0] read-only CONN_UPDATE_NEW_INTERVAL Connection update new interval 0x3A4 32 read-write 0x0 0xFFFF CONN_UPDT_INTERVAL This register will have the new connection interval that the hardware will use after the connection update instant. Before the instant, the connection interval in the register CONN_INTERVAL will be used by hardware. [15:0] read-write CONN_UPDATE_NEW_LATENCY Connection update new latency 0x3A8 32 read-write 0x0 0xFFFF CONN_UPDT_SLV_LATENCY This register will have the new slave latency parameter that the hardware will use after the connection update instant. Before the instant, the connection interval in the register SLAVE_LATENCY will be used by hardware. [15:0] read-write CONN_UPDATE_NEW_SUP_TO Connection update new supervision timeout 0x3AC 32 read-write 0x0 0xFFFF CONN_UPDT_SUP_TO This register will have the new supervision timeout that the hardware will use after the connection update instant. Before the instant, the connection interval in the register SUP_TIMEOUT will be used by hardware. [15:0] read-write CONN_UPDATE_NEW_SL_INTERVAL Connection update new Slave Latency X Conn interval Value 0x3B0 32 read-write 0x0 0xFFFF SL_CONN_INTERVAL_VAL This register will have the new Slave Latency * Conn Interval value that the hardware will use after the connection update instant. Before the instant, the connection interval in the register SL_CONN_INTERVAL will be used by hardware. [15:0] read-write CONN_REQ_WORD0 Connection request address word 0 0x3C0 32 read-write 0x0 0xFFFF ACCESS_ADDR_LOWER This field defines the lower 16 bits of the access address that is to be sent in the connect request packet of the initiator. [15:0] read-write CONN_REQ_WORD1 Connection request address word 1 0x3C4 32 read-write 0x0 0xFFFF ACCESS_ADDR_UPPER This field defines the upper16 bits of the access address that is to be sent in the connect request packet of the initiator. [15:0] read-write CONN_REQ_WORD2 Connection request address word 2 0x3C8 32 read-write 0x0 0xFFFF TX_WINDOW_SIZE_VAL window_size along with the window_offset is used to calculate the first connection point anchor point for the master. This shall be a multiple of 1.25 ms in the range of 1.25 ms to the lesser of 10 ms and (connInterval - 1.25 ms). Values range from 0 to 10 ms. [7:0] read-write CRC_INIT_LOWER This field defines the lower byte [7:0] of the CRC initialization value. [15:8] read-write CONN_REQ_WORD3 Connection request address word 3 0x3CC 32 read-write 0x0 0xFFFF CRC_INIT_UPPER This field defines the upper byte [23:8] of the CRC initialization value that is to be sent in the connect request packet of the initiator. [15:0] read-write CONN_REQ_WORD4 Connection request address word 4 0x3D0 32 read-write 0x0 0xFFFF TX_WINDOW_OFFSET This is used to determine the anchor point for the master transmission. Range: This shall be a multiple of 1.25 ms in the range of 0 ms to connInterval value. [15:0] read-write CONN_REQ_WORD5 Connection request address word 5 0x3D4 32 read-write 0x0 0xFFFF CONNECTION_INTERVAL_VAL The value configured in this register determines the spacing between the connection events. This shall be a multiple of 1.25 ms in the range of 7.5 ms to 4.0 s. [15:0] read-write CONN_REQ_WORD6 Connection request address word 6 0x3D8 32 read-write 0x0 0xFFFF SLAVE_LATENCY_VAL The value configured in this field defines the number of consecutive connection events that the slave device is not required to listen for master. The value of connSlaveLatency should not cause a Supervision Timeout. This shall be an integer in the range of 0 to ((connSupervision Timeout/connInterval)-1). connSlaveLatency shall also be less than 500. [15:0] read-write CONN_REQ_WORD7 Connection request address word 7 0x3DC 32 read-write 0x0 0xFFFF SUPERVISION_TIMEOUT_VAL This field defines the maximum time between two received Data packet PDUs before the connection is considered lost. This shall be a multiple of 10 ms in the range of 100 ms to 32.0 s and it shall be larger than (1+connSlaveLatency)*connInterval. [15:0] read-write CONN_REQ_WORD8 Connection request address word 8 0x3E0 32 read-write 0x0 0xFFFF DATA_CHANNELS_LOWER This register field indicates which of the data channels are in use. This stores the information for the lower 16 (15:0) data channel indices. 1' indicates the corresponding data channel is used and '0' indicates the channel is unused. [15:0] read-write CONN_REQ_WORD9 Connection request address word 9 0x3E4 32 read-write 0x0 0xFFFF DATA_CHANNELS_MID This register field indicates which of the data channels are in use. This stores the information for the middle 16 (31:16) data channel indices. '1' indicates the corresponding data channel is used and '0' indicates the channel is unused. [15:0] read-write CONN_REQ_WORD10 Connection request address word 10 0x3E8 32 read-write 0x0 0x1F DATA_CHANNELS_UPPER This register field indicates which of the data channels are in use. This stores the information for the upper 5 (36:32) data channel indices. '1' indicates the corresponding data channel is used and '0' indicates the channel is unused. [4:0] read-write CONN_REQ_WORD11 Connection request address word 11 0x3EC 32 read-write 0x0 0xFF HOP_INCREMENT_2 This field is used for the data channel selection process. [4:0] read-write SCA_2 This field defines the sleep clock accuracies given in ppm. [7:5] read-write PDU_RESP_TIMER PDU response timer/Generic Timer (MMMS mode) 0xA04 32 read-write 0x0 0xFFFF PDU_RESP_TIME_VAL Non MMMS mode: This register is loaded with the count value to monitor the time to get a response for a PDU from peer device. Firmware starts the timer by issuing the command, RESP_TIMER_ON, after it has queued a PDU for transmission, that requires a response. If a response is received, firmware stops and clears the timer by issuing the command RESP_TIMER_OFF. If this timer expires, it results in hardware closing the connection and triggering a conn_closed interrupt. The discon_status field in the Connection status register is set with the appropriate reason. Units : Milliseconds. Resolution : 1.25 ms MMMS mode: This register is loaded with a count value, which when matched by the internal timer, triggers the GEN_TIMER_INTR. This is recommended to be used as a one shot timer and not as a periodic timer. Firmware starts the timer by loading the expiry time and issuing the command, RESP_TIMER_ON. Once the timer expiry is triggered with the interrupt GEN_TIMER_INTR, the firmware stops the timer by issuing the command RESP_TIMER_OFF. Resolution : 625 us [15:0] read-write NEXT_RESP_TIMER_EXP Next response timeout instant 0xA08 32 read-only 0x0 0xFFFF NEXT_RESPONSE_INSTANT This field defines the clock instant at which the next PDU response timeout event will occur on a connection. This is with reference to the 16-bit internal reference clock. [15:0] read-only NEXT_SUP_TO Next supervision timeout instant 0xA0C 32 read-only 0x0 0xFFFF NEXT_TIMEOUT_INSTANT This field defines the clock instant at which the next connection supervision timeout event will occur on a connection This is with reference to the 16-bit internal reference clock. [15:0] read-only LLH_FEATURE_CONFIG Feature enable 0xA10 32 read-write 0x6 0x7 QUICK_TRANSMIT Quick transmit feature in slave latency is enabled by setting this bit. When slave latency is enabled, this feature enables the slave to transmit in the immediate connection interval, in case required, instead of waiting till the end of slave latency [0:0] read-write SL_DSM_EN Enable/Disable Slave Latency Period DSM. [1:1] read-write US_COUNTER_OFFSET_ADJ Enable/Disable the connection US counter offset adjust. For non-MMMS mode, this bit must be tied to 1. [2:2] read-write WIN_MIN_STEP_SIZE Window minimum step size 0xA14 32 read-write 0x2064 0xFFFF STEPDN After receiving 2 consecutive good packets the reference window is gradually decremented by step down size until it reaches window minimum. The unit is in microseconds [3:0] read-write STEPUP If packets are missed, the reference window is gradually increased by step up size, until it receives 2 consecutive good packets. The unit is in microseconds [7:4] read-write WINDOW_MIN_FW Minimum window interval value programmed by firmware. While the slave receive window is decremented, the windows_min_fw sets the lowest value of the window widen value to ensure packets are not missed. The unit is in microseconds. [15:8] read-write SLV_WIN_ADJ Slave window adjustment 0xA18 32 read-write 0x10 0x7FF SLV_WIN_ADJ Window Adjust value. This value is added to the calculated slave window widening value to be used as final window widen value. [10:0] read-write SL_CONN_INTERVAL Slave Latency X Conn Interval Value 0xA1C 32 read-write 0x0 0xFFFF SL_CONN_INTERVAL_VAL This field defines the (SL*CI) product for the ongoing connection. This value is used in calculation of next connection instant during slave latency. [15:0] read-write LE_PING_TIMER_ADDR LE Ping connection timer address 0xA20 32 read-write 0x0 0xFFFF CONN_PING_TIMER_ADDR The register used to configure the LE Au-thenticated payload Timeout (LE APTO) which is the Maximum amount of time specified between packets authenticated by a MIC. This value of ping timer is in the order of 10ms, valid range 0x1 ~ 0xFFFF [15:0] read-write LE_PING_TIMER_OFFSET LE Ping connection timer offset 0xA24 32 read-write 0x0 0xFFFF CONN_PING_TIMER_OFFSET The value of ping timer nearly expired offset in the order of 10ms, valid range 0x0 ~ 0xFFFF. This is the time period after which the ping timer nearly expired interrupt is generated. [15:0] read-write LE_PING_TIMER_NEXT_EXP LE Ping timer next expiry instant 0xA28 32 read-only 0x0 0xFFFF CONN_PING_TIMER_NEXT_EXP The value of ping timer next expiry instant in the terms of native clock value (least 16 bit value of the 17 bit ping counter). This together with CONN_PING_TIMER_NEXT_EXP_WRAP will provide the correct status of ping timer duration. [15:0] read-only LE_PING_TIMER_WRAP_COUNT LE Ping Timer wrap count 0xA2C 32 read-only 0x0 0xFFFF CONN_SEC_CURRENT_WRAP This register holds the current position of the Ping timer. [15:0] read-only TX_EN_EXT_DELAY Transmit enable extension delay 0xE00 32 read-write 0x1345 0xFFFF TXEN_EXT_DELAY Transmit enable extension delay. This is to extend the active state (high) of rif_tx_en signal after the last bit is sent out from LLH. The unit is in microsecond and the supported range is 00 - 31 us. [3:0] read-write RXEN_EXT_DELAY receiver enable extension delay. This is to extend the active state (high) of dbus_rx_en signal after the last bit is received from demod. The unit is in microsecond and the supported range is 00 - 31 us. [7:4] read-write DEMOD_2M_COMP_DLY 2Mbps demod delay delta compare to 1Mbps demod delay. This data is 2's comp data. [11:8] read-write MOD_2M_COMP_DLY 2Mbps modulation delay delta compare to 1Mbps demod delay. This data is 2's comp data. [15:12] read-write TX_RX_SYNTH_DELAY Transmit/Receive enable delay 0xE04 32 read-write 0x0 0xFFFF RX_EN_DELAY The delay used to assert rif_rx_en, Rx_tRamp micro-seconds, ahead of first bit of the expected rx_data, which can be used to turn on the Radio receiver. The value to be programmed to the Rx_en_delay [7:0] = rx_on_delay - Rx_tRamp rx_on_delay[7:0] = TX_RX_ON_DELAY[7:0]) Rx_tRamp = Radio receiver rampup time [7:0] read-write TX_EN_DELAY The delay used to assert rif_tx_en exactly Tx_tRamp micro-seconds ahead of the first bit of the tx_data, which can be used to turn on the Radio transmitter. The value to be programmed to the Tx_en_delay [7:0] = tx_on_delay - Tx_tRamp tx_on_delay[7:0] = TX_RX_ON_DELAY[15:8]) Tx_tRamp = Radio transmitter ramp_up [15:8] read-write EXT_PA_LNA_DLY_CNFG External TX PA and RX LNA delay configuration 0xE08 32 read-write 0x0 0xFFFF LNA_CTL_DELAY The delay used to assert LNA_CTL, LNA_tRamp micro-seconds, ahead of first bit of the expected rx_data, which can be used to turn on the external Low Noise Amplifier. The value to be programmed to the lna_ctl_delay [7:0] = rx_on_delay - LNA_tRamp rx_on_delay[7:0] = TX_RX_ON_DELAY[7:0]) LNA_tRamp = External Low Noise Amplifier startup time [7:0] read-write PA_CTL_DELAY The delay used to assert PA_CTL exactly PA_tRamp micro-seconds ahead of the first bit of the tx_data, which can be used to turn on the external power amplifier. The value to be programmed to the pa_ctl_delay [7:0] = tx_on_delay - PA_tRamp tx_on_delay[7:0] = TX_RX_ON_DELAY[15:8]) PA_tRamp = External Power Amplifier ramp time [15:8] read-write LL_CONFIG Link Layer additional configuration 0xE10 32 read-write 0x4C00 0x7FEF RSSI_SEL Controls the RSSI reads. When this bit is 1, the bit RSSI_INTR_SEL is don't care. 0 - RSSI read is initiated after the the packet is received 1 - RSSI read is completed before the packet is received. When RCB Interface is operating 4Mhz are lower this bit should be set to 1'b0. [0:0] read-write TX_RX_CTRL_SEL Controls the mode of issueing TX_EN & RX_EN to the Radio 1 - TX_EN and RX_EN are issued through direct pins 0 - TX_EN and RX_EN are issued through RCB writes [1:1] read-write TIFS_ENABLE Setting this bit enables the tx 1MHz pulse to match the received bpktctl from CYBLERD55. This will result is reduced TIFS variation [2:2] read-write TIMER_LF_SLOT_ENABLE Controls the wakeup timer configuration 1 - Wakeup time is compensated with the LF_OFFSET 0 - Wakeup time is not compensated with the LF_OFFSET as in legacy mode [3:3] read-write RSSI_INTR_SEL Controls the engine interrupt generation based on RSSI reads. This is valid only if RSSI_SEL is 0. 0 - Receive interrupts are triggerred after the RSSI read is complete 1 - Receive interrupts are triggerred after the last bit of CRC [5:5] read-write RSSI_EARLY_CNFG Controls the early RSSI reads. This is applicable only when RSSI_SEL is 1. 1 - RSSI read is initiated during the first CRC byte reception. 0 - RSSI read is initiated during the third CRC byte reception. [6:6] read-write TX_RX_PIN_DLY Controls the delay from DBUS_TX, DBUS_RX assertion to the assertion on the pins. This is applicable only when TX_RX_CTRL_SEL is set. 0 - The pin assertion is delayed by 4 cycles. 1 - The pin assertion is delayed by 8 cycles. [7:7] read-write TX_PA_PWR_LVL_TYPE Controls the TX power level format given to the CYBLERD55 chip. 0 - The power level given to CYBLERD55 is in 4 bit code format from ADV_CH_TX_POWER for advertising channel and DTM packets & from CONN_CH_TX_POWER for connection channel packets. The power level setting is decoded and given to the PA. 1 - The power level given to CYBLERD55 is in 18 bit power level setting format from {ADV_CH_TX_POWER_LVL_MS, ADV_CH_TX_POWER_LVL_LS} channel and DTM packets & from {CONN_CH_TX_POWER_LVL_MS, CONN_CH_TX_POWER_LVL_LS} for connection channel packets. This setting is directly given to the PA. [8:8] read-write RSSI_ENERGY_RD Controls the RSSI reads. 0 - Channel Energy read is not initiated if no packet is received during a receive cycle 1 - Channel Energy read is initiated at the end of the receive cycle if no packet is received [9:9] read-write RSSI_EACH_PKT Controls the RSSI reads. 0 - RSSI read is not initiated for zero length and aborted packets 1 - RSSI read is initiated for zero length and aborted packets [10:10] read-write FORCE_TRIG_RCB_UPDATE Controls the RCB update to radio on TX/RX enable. Applicable only when TX_RX_CTRL_SEL is 1'b1 0 - RCB update is triggerred only when the fields change on rising edge of TX/RX enable 1 - RCB update is force triggerred on rising edge of TX/RX enable If TX_RX_CTRL_SEL is 1'b1 and ENABLE_RADIO_BOD is 1'b1, this bit needs to be set to 1'b1 [11:11] read-write CHECK_DUP_CONN Controls the duplicate connection checkin ADV and INIT 0 - Does not check if the peer is already connection before a new connection is created 1 - Checks if the peer is already connection before a new connection is created and aborts a duplicate connection creation [12:12] read-write MULTI_ENGINE_LPM Controls the LPM entry condition 0 - Legacy mode LPM entry check 1 - MMMS mode LPM entry check [13:13] read-write ADV_DIR_DEVICE_PRIV_EN Controls the ADV behavior while advertising ADV_DIR and only device privacy is set. When the ADV is transmitting INITA RPA, the bahavior when an Identity address in received from the Initiator in the CONN_REQ is given below 0 - Abort the CONN_REQ and continue with advertisement 1 - Check the address against PEER_SEC_ADDR_ADV and create connection on a match. [14:14] read-write LL_CONTROL LL Backward compatibility 0xF00 32 read-write 0x2 0xFFFF PRIV_1_2 Enables Privacy 1.2 Feature. [0:0] read-write DLE Enables Data Length extension feature in DTM, connection and encryption modules. This bit should always be set to 1'b1. 1'b0 is not supported. [1:1] read-write WL_READ_AS_MEM The Whilelist read logic is controlled using this bit. 0 - The reads to the whitelist address range is treated as FIFO reads and the pointers are reset by issueing the RESET_READ_PTR command. 1 - The reads to the whitelist address range is treated an memory reads. Any whilelist entry can be read. [2:2] read-write ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL Controls the ADVCH FIFO flushing when PRIV_1_2 is enabled. 0 - Flushes all ADV & INIT packets, as in non privacy 1.2 mode, except those with unresolved peer or self RPA. 1 - Does not flush any CRC good packets [3:3] read-write HW_RSLV_LIST_FULL This bit indicates that the resolving list in the hardware is full and the list is extended in the FW. This will affect the behavior of address resolution. 0 - The resolving list in the hardware is not fully filled. When Whitelist is disabled and a peer identity address not in the resolving list is received, the packet is responded to by the hardware. 1 - The resolving list in the hardware is fully filled. All address comparisons must be extended to the Firmware list as well, Any match in the Firmware list should be followed by copying the matching entry into the hardware resolving list. [4:4] read-write RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV This bit controls the ADV engine behavior when an initiator address match occurs but a privacy mismatch occurs 0 - The packet is aborted 1 - The packet is received and reported to the Link Layer firmware [5:5] read-write RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV This bit controls the ADV engine behavior when a scanner address match occurs but a privacy mismatch occurs 0 - The packet is aborted 1 - The packet is received and reported to the Link Layer firmware [6:6] read-write RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN This bit controls the SCAN engine behavior when an peer address match occurs but a privacy mismatch occurs 0 - The packet is aborted 1 - The packet is received and reported to the Link Layer firmware [7:7] read-write RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI This bit controls the INIT engine behavior when an peer address match occurs but a privacy mismatch occurs 0 - The packet is aborted 1 - The packet is received and reported to the Link Layer firmware [8:8] read-write RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI This bit controls the INIT engine behavior when a self address match occurs but a privacy mismatch occurs 0 - The packet is aborted 1 - The packet is received and reported to the Link Layer firmware [9:9] read-write PRIV_1_2_ADV Enables Privacy 1.2 for ADV engine [10:10] read-write PRIV_1_2_SCAN Enables Privacy 1.2 for SCAN engine [11:11] read-write PRIV_1_2_INIT Enables Privacy 1.2 for INIT engine [12:12] read-write EN_CONN_RX_EN_MOD This bit controls the Connection RX enable modification mode when SLV_CONN_PEER_RPA_NOT_RSLVD is set. 1'b0 - The Connection RX enable is unmodified 1'b1 - The Connection RX enable is during the Peer INIT RPA unresolved state is modified, until it is resolved. [13:13] read-write SLV_CONN_PEER_RPA_NOT_RSLVD This bit is asserted when SLV_CONN_PEER_RPA_UNMCH_INTR is set. The device does not enter into Connection established state until this bit is cleared after the RPA is resoved by the firmware. If the firmware is not able to resolve the RPA within the supervision timeout, the device aborts the connection establishement and this bit is cleared by the hardware. This bit is valid only if PRIV_1_2 is set. [14:14] read-write ADVCH_FIFO_FLUSH When set, flushes the ADVCH FIFO. The bit is auto cleared. Note that this should be used only when the FIFO is not read by the firmware. If firmware has started reading the FIFO, then the FIFO must be emptied exclusively by firmware reads [15:15] write-only DEV_PA_ADDR_L Device Resolvable/Non-Resolvable Private address lower register 0xF04 32 read-write 0x3412 0xFFFF DEV_PA_ADDR_L Lower 16 bit of 48-bit Random Private address of the device. [15:0] read-write DEV_PA_ADDR_M Device Resolvable/Non-Resolvable Private address middle register 0xF08 32 read-write 0x56 0xFFFF DEV_PA_ADDR_M Middle 16 bit of 48-bit Random Private address of the device. [15:0] read-write DEV_PA_ADDR_H Device Resolvable/Non-Resolvable Private address higher register 0xF0C 32 read-write 0x0 0xFFFF DEV_PA_ADDR_H Higher 16 bit of 48-bit Random Private address of the device. [15:0] read-write 16 4 RSLV_LIST_ENABLE[%s] Resolving list entry control bit 0xF10 32 read-write 0x0 0x7FF VALID_ENTRY Indicates if the index is valid [0:0] read-write PEER_ADDR_IRK_SET Indicates if the listed peer device has shared its IRK. 0 - Identity address in a received packet is accepted. If a valid peer device RPA is available in the list, then the RPA in a received packet is accepted. 1 - Only the peer device RPA, if available in the list, in a received packet is accepted. An Identity address in the received packet is reported as a privacy mismatch. [1:1] read-write SELF_ADDR_IRK_SET_RX Indicates if the local IRK has been shared with the listed peer device 0 - Self Identity address in a received packet is accepted. If a valid self RPA is available in the list, then the RPA in a received packet is accepted. 1 - Only the self device RPA, if available in the list, in a received packet is accepted. A Self Identity address in the received packet is reported as a privacy mismatch. [2:2] read-write WHITELISTED_PEER Indicates if the listed peer device is in the whitelist [3:3] read-write PEER_ADDR_TYPE Indicates the address type of the listed peer device [4:4] read-write PEER_ADDR_RPA_VAL Indicates that the peer device RPA in the list is valid [5:5] read-write SELF_ADDR_RXD_RPA_VAL Indicates that the received self RPA in the list is valid [6:6] read-write SELF_ADDR_TX_RPA_VAL Indicates that the self RPA in the list to be transmitted is valid [7:7] read-write SELF_ADDR_INIT_RPA_SEL When Initiator whitelist is disabled, this bit indicates the specific device to from which ADV packets will be accepted. [8:8] read-write SELF_ADDR_TYPE_TX Indicates the TX addr type to be used for SCANA and INITA 0 - Self Identity address is used in SCANA/INITA in SCAN_REQ/CONN_REQ packets 1 - Self RPA address provided in RSLV_LIST_TX_INIT_RPA field in the resolving list with the associated valid bit in SELF_ADDR_TX_RPA_VAL above is used in SCANA/INITA in SCAN_REQ/CONN_REQ packets [9:9] read-write ENTRY_CONNECTED Indicates if the entry is already in connection with our device [10:10] read-write WL_CONNECTION_STATUS whitelist valid entry bit 0xFA0 32 read-write 0x0 0xFFFF WL_ENTRY_CONNECTED Stores the connection status of each of the sixteen device address stored in the whitelist. 1 - White list entry is already in a connection 0 - White list entry is not in a connection [15:0] read-write CONN_RXMEM_BASE_ADDR_DLE DLE Connection RX memory base address 0x1800 32 read-write 0x0 0xFFFFFFFF CONN_RX_MEM_BASE_ADDR_DLE Data from Rx memory are read as 32-bit wide data. This memory is valid only if DLE is set. [31:0] read-write CONN_TXMEM_BASE_ADDR_DLE DLE Connection TX memory base address 0x2800 32 read-write 0x0 0xFFFFFFFF CONN_TX_MEM_BASE_ADDR_DLE Data to Tx memory are written as 32-bit wide data. This memory is valid only if DLE is set. [31:0] read-write CONN_1_PARAM_MEM_BASE_ADDR Connection Parameter memory base address for connection 1 0x12800 32 read-write 0x0 0xFFFF CONN_1_PARAM N/A [15:0] read-write CONN_2_PARAM_MEM_BASE_ADDR Connection Parameter memory base address for connection 2 0x12880 32 read-write 0x0 0xFFFF CONN_2_PARAM N/A [15:0] read-write CONN_3_PARAM_MEM_BASE_ADDR Connection Parameter memory base address for connection 3 0x12900 32 read-write 0x0 0xFFFF CONN_3_PARAM N/A [15:0] read-write CONN_4_PARAM_MEM_BASE_ADDR Connection Parameter memory base address for connection 4 0x12980 32 read-write 0x0 0xFFFF CONN_4_PARAM N/A [15:0] read-write NI_TIMER Next Instant Timer 0x14000 32 read-write 0x0 0xFFFF NI_TIMER BT Slot at which the next connection has to be serviced, granularity is 625us. The NI timer has to be programmed 1.25ms before the connection event [15:0] read-write US_OFFSET Micro-second Offset 0x14004 32 read-write 0x0 0x3FF US_OFFSET_SLOT_BOUNDARY Micro Second Offset from the Slot Bounday at which the connection programmed in NEXT_CONN has to be serviced. This register along with NI_TIMER has to be programmed 1.25ms before the connection event. The granularity is 1us [9:0] read-write NEXT_CONN Next Connection 0x14008 32 read-write 0x0 0x7F NEXT_CONN_INDEX Connection Index to be serviced. Allowed values are 0,1,2,3. [4:0] read-write NEXT_CONN_TYPE Connection type 1 - Master Connection 0 - Slave Connection [5:5] read-write NI_VALID Flag indication if programmed NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the connection of if NI_TIMER is pointing to past value [6:6] read-write NI_ABORT Abort next scheduled connection 0x1400C 32 read-write 0x0 0x3 NI_ABORT Setting this bit clears the schedule NI [0:0] read-write ABORT_ACK This bit will set if the scheduled NI is aborted [1:1] read-write CONN_NI_STATUS Connection NI Status 0x14020 32 read-only 0xFFFF 0xFFFF CONN_NI HW updates this register with the next Connection Instant for current serviced connection, granularity is 625us. The reset value is 0x0000. After reset deassertion, then the very next clock, the value assigned to the registers is 0xFFFF. [15:0] read-only NEXT_SUP_TO_STATUS Next Supervision timeout Status 0x14024 32 read-only 0x0 0xFFFF NEXT_SUP_TO HW updates this register for the SuperVision timeout next instant, granularity is 625us [15:0] read-only MMMS_CONN_STATUS Connection Status 0x14028 32 read-only 0x0 0xFFFF CURR_CONN_INDEX Connection Index that was serviced. Legal values are 0,1,2,3. [4:0] read-only CURR_CONN_TYPE Connection type 1 - Master Connection 0 - Slave Connection [5:5] read-only SN_CURR Sequence Number of Packets exchanged [6:6] read-only NESN_CURR Next Sequence Number [7:7] read-only LAST_UNMAPPED_CHANNEL Last Unmapped Channel [13:8] read-only PKT_MISS 1 - Packet Missed 0 - Connection exchanged packets [14:14] read-only ANCHOR_PT_STATE Anchor Point State 0 - Anchor point missed 1 - Anchor point established [15:15] read-only BT_SLOT_CAPT_STATUS BT Slot Captured Status 0x1402C 32 read-only 0x0 0xFFFF BT_SLOT During slave connection event, HW updates this register with the captured BT_SLOT at anchor point, granularity is 625us [15:0] read-only US_CAPT_STATUS Micro-second Capture Status 0x14030 32 read-only 0x0 0x3FF US_CAPT During slave connection event, HW updates this register with the captured microsecond at anchor point, granularity is 1us [9:0] read-only US_OFFSET_STATUS Micro-second Offset Status 0x14034 32 read-only 0xD5 0xFFFF US_OFFSET During slave connection event, HW updates this register with the calculated us_offset at anchor point, granularity is 1us. The reset value is 0x0000. After reset deassertion, then the very next clock, the value assigned to the registers is 0x00D5. [15:0] read-only ACCU_WINDOW_WIDEN_STATUS Accumulated Window Widen Status 0x14038 32 read-only 0x0 0xFFFF ACCU_WINDOW_WIDEN Accumulated Window Widen Value. HW updates this register at the close of slave connection event [15:0] read-only EARLY_INTR_STATUS Status when early interrupt is raised 0x1403C 32 read-only 0x0 0xFFFF CONN_INDEX_FOR_EARLY_INTR Connection Index for which early interrupt is raised [4:0] read-only CONN_TYPE_FOR_EARLY_INTR Connection type for which early interrupt is raised. [5:5] read-only US_FOR_EARLY_INTR US offset when early interrupt is raised [15:6] read-only MMMS_CONFIG Multi-Master Multi-Slave Config 0x14040 32 read-write 0x0 0x7FF MMMS_ENABLE Configuration bit to enable MMMS functionality [0:0] read-write DISABLE_CONN_REQ_PARAM_IN_MEM If set to 1'b1 and MMMS enabled, then the parameters received in connection request are not stored in CONN_REQ_PARAM memory. By default this bit is 1'b0 and the connection request parameters are stored in connection memory. This bit is intended as a fail-safe. Should not be changed dynamically during runtime [1:1] read-write DISABLE_CONN_PARAM_MEM_WR By default on end_ce, the connection parameters memory is loaded with the updated connection parameters. Setting this bit prevent's this update. This bit is intended as a fail-safe. Should not be changed dynamically during runtime [2:2] read-write CONN_PARAM_FROM_REG By default the parameters for the connection are picked up from the connection parameters memory. Setting this bit disables this and the parameters are picked up from registers 0 - HW loads the parameters from connection memory 1 - Firmware should program the paramters for the connection event This bit is intended as a fail-safe. Should not be changed dynamically during runtime [3:3] read-write ADV_CONN_INDEX This field specifies the connection index for which ADV is enabled [8:4] read-write CE_LEN_IMMEDIATE_EXPIRE Enable for CE length immediate expiry [9:9] read-write RESET_RX_FIFO_PTR Setting this bit resets the receive FIFO pointers [10:10] read-write US_COUNTER Running US of the current BT Slot 0x14044 32 read-only 0x0 0x3FF US_COUNTER Current value of the US Counter [9:0] read-only US_CAPT_PREV Previous captured US of the BT Slot 0x14048 32 read-write 0x0 0x3FF US_CAPT_LOAD HW uses this register to load the us_offset from connection parameter memory. This can be used by firmware as a fail safe option if the HW load from memory is disabled. In alll other conditions firmware should not use this register. [9:0] read-write EARLY_INTR_NI NI at early interrupt 0x1404C 32 read-only 0x0 0xFFFF EARLY_INTR_NI Connection Next instant when the early interrupt is triggered [15:0] read-only MMMS_MASTER_CREATE_BT_CAPT BT slot capture for master connection creation 0x14080 32 read-only 0x0 0xFFFF BT_SLOT This register captures the BT_SLOT when master connection is created, granularity is 625us [15:0] read-only MMMS_SLAVE_CREATE_BT_CAPT BT slot capture for slave connection creation 0x14084 32 read-only 0x0 0x3FF US_CAPT This register captures the BT_SLOT when slave connection is created, granularity is 625us [9:0] read-only MMMS_SLAVE_CREATE_US_CAPT Micro second capture for slave connection creation 0x14088 32 read-only 0x0 0xFFFF US_OFFSET_SLAVE_CREATED This register captures the us when slave connection is created, granularity is 1us [15:0] read-only 16 4 MMMS_DATA_MEM_DESCRIPTOR[%s] Data buffer descriptor 0 to 15 0x14100 32 read-write 0x0 0x3FF LLID_C1 N/A [1:0] read-write DATA_LENGTH_C1 This field indicates the length of the data packet. Bits [9:7] are valid only if DLE is set. Range 0x00 to 0xFF. [9:2] read-write CONN_1_DATA_LIST_SENT data list sent update and status for connection 1 0x14200 32 read-write 0x0 0xF8F LIST_INDEX__TX_SENT_3_0_C1 Write:Indicates the buffer index for which the SENT bit is being updated by firmware. The default number of buffers in the IP is 5. The index range is 0-3. Read: Reads TX_SENT[3:0]. The bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are 1 - queued 0 - no packet / packet ack received by hardware Example1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement. [3:0] read-write SET_CLEAR_C1 Write: Used to set the SENT bit in hardware for the selected packet buffer. 1 - packet queued When firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted. The SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device. Firmware typically does not clear the bit. However, It only clears the bit on its own if it needs to 'flush' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified. [7:7] write-only BUFFER_NUM_TX_SENT_3_0_C1 Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16, can be shared with up to 8 connections [11:8] read-write CONN_1_DATA_LIST_ACK data list ack update and status for connection 1 0x14204 32 read-write 0x0 0x8F LIST_INDEX__TX_ACK_3_0_C1 Write: Indicates the buffer index for which the ACK bit is being updated by firmware. The default number of buffers in the IP is 5. The index range is 0-3. Read: Reads TX_ACK[3:0] If a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement. Example1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware. Example2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware. [3:0] read-write SET_CLEAR_C1 Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware. Firmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware. For clearing ack for a packet transmitted in fifo-index : '3', firm-ware will write '3' in the 'list-index' field and set this bit (BIT7) to 0. This is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on. The ACK bit in hardware is set by hardware when it has success-fully transmitted a packet. [7:7] write-only CONN_1_CE_DATA_LIST_CFG Connection specific pause resume for connection 1 0x14208 32 read-write 0x0 0xFFFF DATA_LIST_INDEX_LAST_ACK_INDEX_C1 Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded. The default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4. Hardware will start the next data transmission from the index indicated by this field. [3:0] read-write DATA_LIST_HEAD_UP_C1 Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause. The bit must be set every time the firmware needs to indicate the start/resume. [4:4] read-write SLV_MD_CONFIG_C1 This bit is set to configure the MD bit control when the design is in slave mode. 1 - MD bit will be decided on packet pending status 0 - MD bit will be decided on packet queued in next buffer status This bit has valid only when MD_BIT_CLEAR bit is not set [5:5] read-write MD_C1 MD bit set to '1' indicates device has more data to be sent. [6:6] read-write MD_BIT_CLEAR_C1 This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or, 'hardware and software logic combined' 1 - MD bit is exclusively controlled by software, based on status of bit [6]. 0 - MD Bit in the transmitted PDU is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the MD in bit [6] and either of the following conditions is true, a) If there are packets queued for transmission. b) If there is an acknowledgement awaited from the remote side for the packet transmitted. [7:7] read-write PAUSE_DATA_C1 Pause data. 1 - pause data, 0 - do not pause. The current_pdu_index in hardware does not move to next in-dex until pause_data is cleared. But if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out [8:8] read-write KILL_CONN Kills the connection immediately when the connection event is active [9:9] read-write KILL_CONN_AFTER_TX Kills the connection when the connection event is active and a TX is completed [10:10] read-write EMPTYPDU_SENT This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW [11:11] read-write CURRENT_PDU_INDEX_C1 The index of the transmit packet buffer that is currently in transmission/waiting for transmission. [15:12] read-only CONN_2_DATA_LIST_SENT data list sent update and status for connection 2 0x14210 32 read-write 0x0 0xF8F LIST_INDEX__TX_SENT_3_0_C1 Write:Indicates the buffer index for which the SENT bit is being updated by firmware. The default number of buffers in the IP is 5. The index range is 0-3. Read: Reads TX_SENT[3:0]. The bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are 1 - queued 0 - no packet / packet ack received by hardware Example1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement. [3:0] read-write SET_CLEAR_C1 Write: Used to set the SENT bit in hardware for the selected packet buffer. 1 - packet queued When firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted. The SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device. Firmware typically does not clear the bit. However, It only clears the bit on its own if it needs to 'flush' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified. [7:7] write-only BUFFER_NUM_TX_SENT_3_0_C1 Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16, can be shared with up to 8 connections [11:8] read-write CONN_2_DATA_LIST_ACK data list ack update and status for connection 2 0x14214 32 read-write 0x0 0x8F LIST_INDEX__TX_ACK_3_0_C1 Write: Indicates the buffer index for which the ACK bit is being updated by firmware. The default number of buffers in the IP is 5. The index range is 0-3. Read: Reads TX_ACK[3:0] If a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement. Example1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware. Example2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware. [3:0] read-write SET_CLEAR_C1 Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware. Firmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware. For clearing ack for a packet transmitted in fifo-index : '3', firm-ware will write '3' in the 'list-index' field and set this bit (BIT7) to 0. This is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on. The ACK bit in hardware is set by hardware when it has success-fully transmitted a packet. [7:7] write-only CONN_2_CE_DATA_LIST_CFG Connection specific pause resume for connection 2 0x14218 32 read-write 0x0 0xFFFF DATA_LIST_INDEX_LAST_ACK_INDEX_C1 Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded. The default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4. Hardware will start the next data transmission from the index indicated by this field. [3:0] read-write DATA_LIST_HEAD_UP_C1 Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause. The bit must be set every time the firmware needs to indicate the start/resume. [4:4] read-write SLV_MD_CONFIG_C1 This bit is set to configure the MD bit control when the design is in slave mode. 1 - MD bit will be decided on packet pending status 0 - MD bit will be decided on packet queued in next buffer status This bit has valid only when MD_BIT_CLEAR bit is not set [5:5] read-write MD_C1 MD bit set to '1' indicates device has more data to be sent. [6:6] read-write MD_BIT_CLEAR_C1 This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or, 'hardware and software logic combined' 1 - MD bit is exclusively controlled by software, based on status of bit [6]. 0 - MD Bit in the transmitted PDU is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the MD in bit [6] and either of the following conditions is true, a) If there are packets queued for transmission. b) If there is an acknowledgement awaited from the remote side for the packet transmitted. [7:7] read-write PAUSE_DATA_C1 Pause data. 1 - pause data, 0 - do not pause. The current_pdu_index in hardware does not move to next in-dex until pause_data is cleared. But if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out [8:8] read-write KILL_CONN Kills the connection immediately when the connection event is active [9:9] read-write KILL_CONN_AFTER_TX Kills the connection when the connection event is active and a TX is completed [10:10] read-write EMPTYPDU_SENT This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW [11:11] read-write CURRENT_PDU_INDEX_C1 The index of the transmit packet buffer that is currently in transmission/waiting for transmission. [15:12] read-only CONN_3_DATA_LIST_SENT data list sent update and status for connection 3 0x14220 32 read-write 0x0 0xF8F LIST_INDEX__TX_SENT_3_0_C1 Write:Indicates the buffer index for which the SENT bit is being updated by firmware. The default number of buffers in the IP is 5. The index range is 0-3. Read: Reads TX_SENT[3:0]. The bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are 1 - queued 0 - no packet / packet ack received by hardware Example1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement. [3:0] read-write SET_CLEAR_C1 Write: Used to set the SENT bit in hardware for the selected packet buffer. 1 - packet queued When firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted. The SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device. Firmware typically does not clear the bit. However, It only clears the bit on its own if it needs to 'flush' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified. [7:7] write-only BUFFER_NUM_TX_SENT_3_0_C1 Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16, can be shared with up to 8 connections [11:8] read-write CONN_3_DATA_LIST_ACK data list ack update and status for connection 3 0x14224 32 read-write 0x0 0x8F LIST_INDEX__TX_ACK_3_0_C1 Write: Indicates the buffer index for which the ACK bit is being updated by firmware. The default number of buffers in the IP is 5. The index range is 0-3. Read: Reads TX_ACK[3:0] If a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement. Example1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware. Example2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware. [3:0] read-write SET_CLEAR_C1 Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware. Firmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware. For clearing ack for a packet transmitted in fifo-index : '3', firm-ware will write '3' in the 'list-index' field and set this bit (BIT7) to 0. This is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on. The ACK bit in hardware is set by hardware when it has success-fully transmitted a packet. [7:7] write-only CONN_3_CE_DATA_LIST_CFG Connection specific pause resume for connection 3 0x14228 32 read-write 0x0 0xFFFF DATA_LIST_INDEX_LAST_ACK_INDEX_C1 Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded. The default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4. Hardware will start the next data transmission from the index indicated by this field. [3:0] read-write DATA_LIST_HEAD_UP_C1 Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause. The bit must be set every time the firmware needs to indicate the start/resume. [4:4] read-write SLV_MD_CONFIG_C1 This bit is set to configure the MD bit control when the design is in slave mode. 1 - MD bit will be decided on packet pending status 0 - MD bit will be decided on packet queued in next buffer status This bit has valid only when MD_BIT_CLEAR bit is not set [5:5] read-write MD_C1 MD bit set to '1' indicates device has more data to be sent. [6:6] read-write MD_BIT_CLEAR_C1 This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or, 'hardware and software logic combined' 1 - MD bit is exclusively controlled by software, based on status of bit [6]. 0 - MD Bit in the transmitted PDU is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the MD in bit [6] and either of the following conditions is true, a) If there are packets queued for transmission. b) If there is an acknowledgement awaited from the remote side for the packet transmitted. [7:7] read-write PAUSE_DATA_C1 Pause data. 1 - pause data, 0 - do not pause. The current_pdu_index in hardware does not move to next in-dex until pause_data is cleared. But if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out [8:8] read-write KILL_CONN Kills the connection immediately when the connection event is active [9:9] read-write KILL_CONN_AFTER_TX Kills the connection when the connection event is active and a TX is completed [10:10] read-write EMPTYPDU_SENT This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW [11:11] read-write CURRENT_PDU_INDEX_C1 The index of the transmit packet buffer that is currently in transmission/waiting for transmission. [15:12] read-only CONN_4_DATA_LIST_SENT data list sent update and status for connection 4 0x14230 32 read-write 0x0 0xF8F LIST_INDEX__TX_SENT_3_0_C1 Write:Indicates the buffer index for which the SENT bit is being updated by firmware. The default number of buffers in the IP is 5. The index range is 0-3. Read: Reads TX_SENT[3:0]. The bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are 1 - queued 0 - no packet / packet ack received by hardware Example1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement. [3:0] read-write SET_CLEAR_C1 Write: Used to set the SENT bit in hardware for the selected packet buffer. 1 - packet queued When firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted. The SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device. Firmware typically does not clear the bit. However, It only clears the bit on its own if it needs to 'flush' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified. [7:7] write-only BUFFER_NUM_TX_SENT_3_0_C1 Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16, can be shared with up to 8 connections [11:8] read-write CONN_4_DATA_LIST_ACK data list ack update and status for connection 4 0x14234 32 read-write 0x0 0x8F LIST_INDEX__TX_ACK_3_0_C1 Write: Indicates the buffer index for which the ACK bit is being updated by firmware. The default number of buffers in the IP is 5. The index range is 0-3. Read: Reads TX_ACK[3:0] If a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement. Example1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware. Example2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware. [3:0] read-write SET_CLEAR_C1 Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware. Firmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware. For clearing ack for a packet transmitted in fifo-index : '3', firm-ware will write '3' in the 'list-index' field and set this bit (BIT7) to 0. This is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on. The ACK bit in hardware is set by hardware when it has success-fully transmitted a packet. [7:7] write-only CONN_4_CE_DATA_LIST_CFG Connection specific pause resume for connection 4 0x14238 32 read-write 0x0 0xFFFF DATA_LIST_INDEX_LAST_ACK_INDEX_C1 Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded. The default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4. Hardware will start the next data transmission from the index indicated by this field. [3:0] read-write DATA_LIST_HEAD_UP_C1 Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause. The bit must be set every time the firmware needs to indicate the start/resume. [4:4] read-write SLV_MD_CONFIG_C1 This bit is set to configure the MD bit control when the design is in slave mode. 1 - MD bit will be decided on packet pending status 0 - MD bit will be decided on packet queued in next buffer status This bit has valid only when MD_BIT_CLEAR bit is not set [5:5] read-write MD_C1 MD bit set to '1' indicates device has more data to be sent. [6:6] read-write MD_BIT_CLEAR_C1 This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or, 'hardware and software logic combined' 1 - MD bit is exclusively controlled by software, based on status of bit [6]. 0 - MD Bit in the transmitted PDU is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the MD in bit [6] and either of the following conditions is true, a) If there are packets queued for transmission. b) If there is an acknowledgement awaited from the remote side for the packet transmitted. [7:7] read-write PAUSE_DATA_C1 Pause data. 1 - pause data, 0 - do not pause. The current_pdu_index in hardware does not move to next in-dex until pause_data is cleared. But if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out [8:8] read-write KILL_CONN Kills the connection immediately when the connection event is active [9:9] read-write KILL_CONN_AFTER_TX Kills the connection when the connection event is active and a TX is completed [10:10] read-write EMPTYPDU_SENT This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW [11:11] read-write CURRENT_PDU_INDEX_C1 The index of the transmit packet buffer that is currently in transmission/waiting for transmission. [15:12] read-only MMMS_ADVCH_NI_ENABLE Enable bits for ADV_NI, SCAN_NI and INIT_NI 0x14400 32 read-write 0x0 0x7 ADV_NI_ENABLE This bit is used to enable the Advertisement NI timer and is valid when MMMS_ENABLE=1. 0 - ADV_NI timer is disabled 1 - ADV_NI timer is enabled In this mode, the adv engine next instant is scheduled by firmware [0:0] read-write SCAN_NI_ENABLE This bit is used to enable the SCAN NI timer and is valid when MMMS_ENABLE=1. 0 - SCAN_NI timer is disabled 1 - SCAN_NI timer is enabled In this mode, the scan engine next instant is scheduled by firmware [1:1] read-write INIT_NI_ENABLE This bit is used to enable the INIT NI timer and is valid when MMMS_ENABLE=1. 0 - INIT_NI timer is disabled 1 - INIT_NI timer is enabled In this mode, the init engine next instant is scheduled by firmware [2:2] read-write MMMS_ADVCH_NI_VALID Next instant valid for ADV, SCAN, INIT 0x14404 32 read-write 0x0 0x7 ADV_NI_VALID This bit indicates if the programmed advertisement NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the advertisment event 0 - ADV_NI timer is not valid 1 - ADV_NI timer is valid [0:0] read-write SCAN_NI_VALID This bit indicates if the programmed scan NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the scanner event 0 - SCAN_NI timer is not valid 1 - SCAN_NI timer is valid [1:1] read-write INIT_NI_VALID This bit indicates if the programmed initiator NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the initiator event 0 - INIT_NI timer is not valid 1 - INIT_NI timer is valid [2:2] read-write MMMS_ADVCH_NI_ABORT Abort the next instant of ADV, SCAN, INIT 0x14408 32 read-write 0x0 0x3 ADVCH_NI_ABORT FW can use this bit to clear an unserviced NI_VALID for Advertisement or scanner or initiator. HW will clear NI_VALID for ADV/SCAN/INIT if the event has not yet started [0:0] write-only ADVCH_ABORT_STATUS The link layer hardware logic will set this bit when the NI_TIMER is aborted. Firmware to clear this by writing 1'b1 to this register bit [1:1] read-write CONN_PARAM_NEXT_SUP_TO Register to configure the supervision timeout for next scheduled connection 0x14410 32 read-write 0x0 0xFFFF NEXT_SUP_TO_LOAD HW uses this register to load the Supervision timeout Next instant from the connection memory. This can be used by firmware as a failsafe option when the hardware load is disabled. In all other conditions, this register should not be updated by firmware. [15:0] read-write CONN_PARAM_ACC_WIN_WIDEN Register to configure Accumulated window widening for next scheduled connection 0x14414 32 read-write 0x0 0x3FF ACC_WINDOW_WIDEN HW uses this register to load the accumulated window windeing value from the connection memory. This can be used by firmware as a failsafe option when the hardware load is disabled. In all other conditions, this register should not be updated by firmware. [9:0] read-write HW_LOAD_OFFSET Register to configure offset from connection anchor point at which connection parameter memory should be read 0x14420 32 read-write 0x4 0x1F LOAD_OFFSET Load Offset in us before connection event at which the connection parameters are loaded from memory, granularity is in 1us [4:0] read-write ADV_RAND Random number generated by Hardware for ADV NI calculation 0x14424 32 read-only 0x7 0xF ADV_RAND Random ADV delay, to be used for ADV next instant calculation. The granularity is in BT slot [3:0] read-only MMMS_RX_PKT_CNTR Packet Counter of packets in RX FIFO in MMMS mode 0x14428 32 read-only 0x0 0x3F MMMS_RX_PKT_CNT Count of all packets in the RX FIFO in MMMS mode [5:0] read-only 8 4 CONN_RX_PKT_CNTR[%s] Packet Counter for Individual connection index 0x14430 32 read-only 0x0 0x3F RX_PKT_CNT Number of packets received for the connection. Incremented when the packet is received during the connection event and decremented when firmware has processed the packet. The register field FW_PKT_RCV_CONN_INDEX should be programmed before firmware issues the packet received command [5:0] read-only WHITELIST_BASE_ADDR Whitelist base address 0x14800 32 read-write 0x0 0xFFFF WL_BASE_ADDR Device address values written to white list memory are written as 16-bit wide address. [15:0] read-write RSLV_LIST_PEER_IDNTT_BASE_ADDR Resolving list base address for storing Peer Identity address 0x148C0 32 read-write 0x0 0xFFFF RSLV_LIST_PEER_IDNTT_BASE_ADDR Device address values written to the list are written as 16-bit wide address. [15:0] read-write RSLV_LIST_PEER_RPA_BASE_ADDR Resolving list base address for storing resolved Peer RPA address 0x14980 32 read-write 0x0 0xFFFF RSLV_LIST_PEER_RPA_BASE_ADDR Device address values written to the list are written as 16-bit wide address. [15:0] read-write RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR Resolving list base address for storing Resolved received INITA RPA 0x14A40 32 read-write 0x0 0xFFFF RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR Device address values written to the list are written as 16-bit wide address. [15:0] read-write RSLV_LIST_TX_INIT_RPA_BASE_ADDR Resolving list base address for storing generated TX INITA RPA 0x14B00 32 read-write 0x0 0xFFFF RSLV_LIST_TX_INIT_RPA_BASE_ADDR Device address values written to the list are written as 16-bit wide address. [15:0] read-write BLESS Bluetooth Low Energy Subsystem Miscellaneous 0x0001F000 DDFT_CONFIG BLESS DDFT configuration register 0x60 32 read-write 0x0 0x1F1F03 DDFT_ENABLE Enables the DDFT output from BLESS 1: DDFT is enabled 0: DDFT is disabled [0:0] read-write BLERD_DDFT_EN Enables the DDFT inputs from CYBLERD55 chip 1: DDFT inputs are enabled 0: DDFT inputs are disabled [1:1] read-write DDFT_MUX_CFG1 dbg_mux_pin1 selection, combine with BLERD and BLESS 5'h00 blerd_ddft_out[0] 5'h01 rcb_tx_fifo_empty 5'h02 hv_ldo_lv_detect_raw 5'h03 dbus_rx_en 5'h04 1'b0 5'h05 clk_switch_to_sysclk 5'h06 ll_clk_en_sync 5'h07 dsm_entry_stat 5'h08 proc_tx_en 5'h09 rssi_read_start 5'h0A tx_2mbps 5'h0B rcb_bus_busy 5'h0C hv_ldo_en_mt (act_stdbyb) 5'h0D ll_eco_clk_en 5'h0E blerd_reset_assert 5'h0F hv_ldo_byp_n 5'h10 hv_ldo_lv_detect_mt 5'h11 enable_ldo 5'h12 enable_ldo_dly 5'h13 bless_rcb_le_out 5'h14 bless_rcb_clk_out 5'h15 bless_dig_ldo_on_out 5'h16 bless_act_ldo_en_out 5'h17 bless_clk_en_out 5'h18 bless_buck_en_out 5'h19 bless_ret_switch_hv_out 5'h1A efuse_rw_out 5'h1B efuse_avdd_out 5'h1C efuse_config_efuse_mode 5'h1D bless_dbus_tx_en_pad 5'h1E bless_bpktctl_rd 5'h1F 1'b0 [12:8] read-write DDFT_MUX_CFG2 dbg_mux_pin2 selection, combine with BLERD and BLESS 5'h00 blerd_ddft_out[1] 5'h01 rcb_rx_fifo_empty 5'h02 ll_decode_rxdata 5'h03 dbus_tx_en 5'h04 fw_clk_en 5'h05 interrupt_ll_n 5'h06 llh_st_sm 5'h07 llh_st_dsm 5'h08 proc_rx_en 5'h09 rssi_rx_done 5'h0A rx_2mbps 5'h0B rcb_ll_ctrl 5'h0C hv_ldo_byp_n 5'h0D reset_deassert 5'h0E rcb_intr 5'h0F rcb_ll_intr 5'h10 hv_ldo_en_mt (act_stdbyb) 5'h11 hv_ldo_lv_detect_raw 5'h12 bless_rcb_data_in 5'h13 bless_xtal_en_out 5'h14 bless_isolate_n_out 5'h15 bless_reset_n_out 5'h16 bless_ret_ldo_ol_hv_out 5'h17 bless_txd_rxd_out 5'h18 tx_rx_ctrl_sel 5'h19 bless_bpktctl_cy 5'h1A efuse_cs_out 5'h1B efuse_pgm_out 5'h1C efuse_sclk_out 5'h1D hv_ldo_lv_detect_mt 5'h1E enable_ldo 5'h1F enable_ldo_dly [20:16] read-write XTAL_CLK_DIV_CONFIG Crystal clock divider configuration register 0x64 32 read-write 0x0 0xF SYSCLK_DIV System clock pre-divider value. The 24 MHz crystal clock is divided to generate the system clock. 0: NO_DIV: SYSCLK= XTALCLK/1 1: DIV_BY_2: SYSCLK= XTALCLK/2 2: DIV_BY_4: SYSCLK= XTALCLK/4 3: DIV_BY_8: SYSCLK= XTALCLK/8 [1:0] read-write LLCLK_DIV Link Layer clock pre-divider value. The 24 MHz crystal clock is divided to generate the Link Layer clock. 0: NO_DIV: LLCLK= XTALCLK/1 1: DIV_BY_2: LLCLK= XTALCLK/2 2: DIV_BY_4: LLCLK= XTALCLK/4 3: DIV_BY_8: LLCLK= XTALCLK/8 [3:2] read-write INTR_STAT Link Layer interrupt status register 0x68 32 read-write 0x0 0xFFF DSM_ENTERED_INTR On a firmware request to LL to enter into state machine, working on LF clock, LL transitions into Deep Sleep Mode and asserts this interrupt. The interrupt can be cleared by writing one into this location. [0:0] read-write DSM_EXITED_INTR On a firmware request to LL to exit from Deep Sleep Mode, working on LF clock, LL transitions from Deep Sleep Mode and asserts this interrupt when the Deep Sleep clock gater is turned ON. The interrupt can be cleared by writing one into this location. [1:1] read-write RCBLL_DONE_INTR RCB transaction Complete [2:2] read-only BLERD_ACTIVE_INTR CYBLERD55 is in active mode. RF is active [3:3] read-write RCB_INTR RCB controller Interrupt - Refer to RCB_INTR_STAT register [4:4] read-only LL_INTR LL controller interrupt - Refer to EVENT_INTR register [5:5] read-only GPIO_INTR GPIO interrupt [6:6] read-write EFUSE_INTR This bit when set by efuse controller logic when the efuse read/write is completed [7:7] read-write XTAL_ON_INTR enabled crystal stable signal rising edge interrupt. The interrupt can be cleared by writing one into this location. [8:8] read-write ENC_INTR Encryption Interrupt Triggered [9:9] read-only HVLDO_LV_DETECT_POS This interrupt is set on HVLDO LV Detector Rise edge. There is a 1cycle AHB clock glitch filter on the HVLDO LV Detector output [10:10] read-write HVLDO_LV_DETECT_NEG This interrupt is set on HVLDO LV Detector Fall edge. There is a 1cycle AHB clock glitch filter on the HVLDO LV Detector output [11:11] read-write INTR_MASK Link Layer interrupt mask register 0x6C 32 read-write 0x0 0x1FFF DSM_EXIT When the Link Layer is in Deep Sleep Mode, firmware can set this bit to wake the Link Layer. [0:0] read-write DSM_ENTERED_INTR_MASK Masks the DSM Entered Interrupt, when disabled. [1:1] read-write DSM_EXITED_INTR_MASK Masks the DSM Exited Interrupt, when disabled. [2:2] read-write XTAL_ON_INTR_MASK Masks the Crystal Stable Interrupt, when disabled. [3:3] read-write RCBLL_INTR_MASK Mask for RCBLL interrupt [4:4] read-write BLERD_ACTIVE_INTR_MASK Mask for CYBLERD55 Active Interrupt [5:5] read-write RCB_INTR_MASK Mask for RCB interrupt [6:6] read-write LL_INTR_MASK Mask for LL interrupt [7:7] read-write GPIO_INTR_MASK Mask for GPIO interrupt [8:8] read-write EFUSE_INTR_MASK This bit enables the efuse interrupt to firmware [9:9] read-write ENC_INTR_MASK Mask for Encryption interrupt [10:10] read-write HVLDO_LV_DETECT_POS_MASK Mask for HVLDO LV Detector Rise edge interrupt [11:11] read-write HVLDO_LV_DETECT_NEG_MASK Mask for HVLDO LV Detector Fall edge interrupt [12:12] read-write LL_CLK_EN Link Layer primary clock enable 0x70 32 read-write 0x26 0x3F CLK_EN Set this bit 1 to enable the clock to Link Layer. [0:0] read-write CY_CORREL_EN If MXD_IF option is 1, this bit needs to be set to enable configuring the correlator through BLELL.DPLL_CONFIG register [1:1] read-write MXD_IF_OPTION 1: MXD IF option 0: CYBLERD55 correlates Access Code 0: MXD IF option 1: LL correlates Access Code [2:2] read-write SEL_RCB_CLK 0: AHB clock (clk_sys) is used as the clock for RCB access 1: LL clock (clk_eco) is used as the clock for RCB access [3:3] read-write BLESS_RESET 0: No Soft Reset 1: Initiate Soft Reset Setting this bit will reset entire BLESS_VER3 [4:4] read-write DPSLP_HWRCB_EN Controls the DPSLP entry and exit writes to RD and controls the active domain reset and clock. 1 - LL HW controls the RD active domain reset and clock. 0 - The RD active domain reset and clock. Must be controlled by the FW [5:5] read-write LF_CLK_CTRL BLESS LF clock control and BLESS revision ID indicator 0x74 32 read-write 0x40000000 0xE0000003 DISABLE_LF_CLK When set to 1, gates the LF clock input to the Link Layer. Ths is done for extended DSM mode where the DSM state machine needs to be forzen to prevent a default auto exit. [0:0] read-write ENABLE_ENC_CLK This bit is used to enable the clock to the encryption engine 0 - Disable the clock to ENC engine 1 - Enable the clock to ENC engine [1:1] read-write M0S8BLESS_REV_ID Indicates the m0s8bless IP revision. [31:29] read-only EXT_PA_LNA_CTRL External TX PA and RX LNA control 0x78 32 read-write 0x0 0x3E ENABLE_EXT_PA_LNA When set to 1, enables the external PA & LNA [1:1] read-write CHIP_EN_POL Controls the polarity of the chip enable control signal 0 - High enable, low disable 1 - Low enable, High disable [2:2] read-write PA_CTRL_POL Controls the polarity of the PA control signal 0 - High enable, low disable 1 - Low enable, High disable [3:3] read-write LNA_CTRL_POL Controls the polarity of the LNA control signal 0 - High enable, low disable 1 - Low enable, High disable [4:4] read-write OUT_EN_DRIVE_VAL Configures the drive value on the output enables of PA, LNA and CHI_EN signals 0 - drive 0 on the output enable signals 1 - drive 1 on the output enable signals [5:5] read-write LL_PKT_RSSI_CH_ENERGY Link Layer Last Received packet RSSI/Channel energy and channel number 0x80 32 read-only 0x0 0x7FFFFF RSSI This field captures the RSSI of the packet when a packet reception is complete or gives the Channel energy when a Receive cycle is over without packet reception. [15:0] read-only RX_CHANNEL This field indicates the last channel for which the RSSI is captured [21:16] read-only PKT_RSSI_OR_CH_ENERGY This field indicates if the captured RSSI is for a received packet or is the channel energy [22:22] read-only BT_CLOCK_CAPT BT clock captured on an LL DSM exit 0x84 32 read-only 0x0 0xFFFF BT_CLOCK This field captures the LF BT clock captured on an LL DSM exit. This register is valid only when MT_STATUS.LL_CLK_STATE is set. This value may be used to manage the low power entry. [15:0] read-only MT_CFG MT Configuration Register 0xA0 32 read-write 0x8100000 0xFFFFFFF ENABLE_BLERD This register bit needs to be set to enable CYBLERD55 1'b1 - CYBLERD55 enabled 1'b0 - CYBLERD55 disabled On power up this bit needs to be set to make CYBLERD55 active. [0:0] read-write DEEPSLEEP_EXIT_CFG This register bit indicates the source for PSoC DeepSleep exit to BLESS 1'b0 - act_power_good from SRSS indicates PSoC DeepSleep exit 1'b1 - MT_CFG.DEEPSLEEP_EXITED indicates PSoC DeepSleep exit [1:1] read-write DEEPSLEEP_EXITED This register bit is used by FW to indicate that PSoC is out of DeepSleep 1'b0 - PSoC in DeepSleep 1'b1 - PSoC out of DeepSleep This bit is cleared by HW on exit from DPSLP [2:2] read-write ACT_LDO_NOT_BUCK This register bit specifies whether the Active LDO or BUCK in CYBLERD55 is used in active mode [3:3] read-write OVERRIDE_HVLDO_BYPASS This register should be set to override the HW generated signal to HVLDO. When set HVLDO_BYPASS is driven to the IP [4:4] read-write HVLDO_BYPASS Override value for HVLDO BYPASS 1'b0: bypass the HVLDO 1'b1: Do not bypass the HVLDO [5:5] read-write OVERRIDE_ACT_REGULATOR This register should be set to override the HW generated signal to enable ACTIVE_LDO/BUCK. When set ACT_REGULATOR_EN is driven to CYBLERD55 [6:6] read-write ACT_REGULATOR_EN Override value for ACT_LDO_EN/BUCK_EN [7:7] read-write OVERRIDE_DIG_REGULATOR This register should be set to override the HW generated signal to Digital regulator of CYBLERD55. When set DIG_REGULATOR_EN is driven to CYBLERD55 [8:8] read-write DIG_REGULATOR_EN Override value for digital regulator of CYBLERD55 [9:9] read-write OVERRIDE_RET_SWITCH This register should be set to override the HW generated signal to the retention switch of CYBLERD55. When set OVERRIDE_RET_SWITCH is driven to the IP [10:10] read-write RET_SWITCH Override value for RET_SWITCH [11:11] read-write OVERRIDE_ISOLATE This register should be set to override the HW generated isolation signal to CYBLERD55. When set ISOLATE_N is driven to the IP [12:12] read-write ISOLATE_N Override value for isolation to CYBLERD55 [13:13] read-write OVERRIDE_LL_CLK_EN This register should be set to override the HW generated ECO Clock gate. When set LL_CLK_EN is used to gate the clock [14:14] read-write LL_CLK_EN Override value for LL Clock gate [15:15] read-write OVERRIDE_HVLDO_EN This register should be set to override the HW generated enable to HVLSO. When set HVLDO_EN is used. [16:16] read-write HVLDO_EN Overrie value for HVLDO enable 1'b1: switch to Active LDO 1'b0: switch to standby LDO [17:17] read-write DPSLP_ECO_ON This bit when set indicates that ECO clock should be kept on even in BLESS DPSLP. This bit must be toggled only when the Link Layer is active. [18:18] read-write OVERRIDE_RESET_N This register should be set to override the HW generated reset to CYBLERD55. When set RESET_N is used. [19:19] read-write RESET_N Overrie value for CYBLERD55 RESET_N [20:20] read-write OVERRIDE_XTAL_EN This register should be set to override the HW generated XTAL_EN to CYBLERD55. When set XTAL_EN is used. [21:21] read-write XTAL_EN Overrie value for CYBLERD55 XTAL_EN [22:22] read-write OVERRIDE_CLK_EN This register should be set to override the HW generated CLK_EN to CYBLERD55. When set CLK_EN is used. [23:23] read-write BLERD_CLK_EN Overrie value for CYBLERD55 CLK_EN [24:24] read-write OVERRIDE_RET_LDO_OL This register should be set to override the HW generated RET_LDO_OL_HV to CYBLERD55. When set CLK_EN is used. [25:25] read-write RET_LDO_OL Overrie value for CYBLERD55 RET_LDO_OL_HV [26:26] read-write HVLDO_POR_HV Reset for HVLDO 1'b1 - HVLDO Disabled 1'b0 - HVLDO Enabled [27:27] read-write MT_DELAY_CFG MT Delay configuration for state transitions 0xA4 32 read-write 0x0 0xFFFFFFFF HVLDO_STARTUP_DELAY This register specifies the startup delay for the HVLDO interms of number of LF Clock cycles. FW has to program this register based on the selected LF clock frequency [7:0] read-write ISOLATE_DEASSERT_DELAY This register specifies the time from switching the CYBLERD55 logic to Active regulator to removal of ISOLATE_N [15:8] read-write ACT_TO_SWITCH_DELAY This register specifies the time from assertion of ISOLATE_N to switching the CYBLERD55 logic to Retention LDO [23:16] read-write HVLDO_DISABLE_DELAY This register specifies the time from disabling XTAL to switching of the HVLDO. [31:24] read-write MT_DELAY_CFG2 MT Delay configuration for state transitions 0xA8 32 read-write 0x0 0xFFFFFFFF OSC_STARTUP_DELAY_LF This register specifies the time for OSC Startup. After this delay, clock is enabled to the link layer. Clock is enabled after OSC_STARTUP_DELAY + 1 LF clock cycles. If PSoC was in DPSLP when XTAL is enabled, then the wakeup delay will be OSC_STARTUP_DELAY + 1 + PSoC Wakeup time. Minimum value to be programmed in 1. This is equivalent to Link Layer register WAKEUP_CONFIG.OSC_STARTUP_DELAY, but is specified in LF cycles [7:0] read-write DSM_OFFSET_TO_WAKEUP_INSTANT_LF This register specifies the pre-processing time required in Link Layer. This is esentially the time from CLK_EN (ungating clock in CYBLERD55) to the time when logic in CYBLERD55 is switched to Active mode Regulator.The delay is in terms of LF Clock cycles. FW has to program this register based on the selected LF clock frequency. This is equivalent to Link Layer register WAKEUP_CONFIG.DSM_OFFSET_TO_WAKEUP_INSTANT_LF, but is specified in LF cycles. [15:8] read-write ACT_STARTUP_DELAY This register specifes the Active Regulator startup time in CYBLERD55. The delay is in terms of LF Clock cycles. FW has to program this register based on the selected LF clock frequency. The digital LDO will be turned on after this time elapses [23:16] read-write DIG_LDO_STARTUP_DELAY This register specifes the Digital LDO startup time in CYBLERD55.The delay is in terms of LF Clock cycles. FW has to program this register based on the selected LF clock frequency. The logic in CYBLERD55 is switched to Active mode Regulator after this (ACT_STARTUP_DELAY + DIG_LDO_STARTUP_DELAY) [31:24] read-write MT_DELAY_CFG3 MT Delay configuration for state transitions 0xAC 32 read-write 0x0 0xFFFFFF XTAL_DISABLE_DELAY This register specifies the time from switching of logic to Retention LDO in CYBLERD55 to XTAL Disable. This should include the post processing time The delay is in terms of LF Clock cycles. FW has to program this register based on the selected LF clock frequency. At the minimum XTAL_DISABLE_DELAY should be the sum of DIG_LDO_DISABLE_DELAY and the powerdown time of ACTIVE_LDO [7:0] read-write DIG_LDO_DISABLE_DELAY This field holds the delay from the time of diabling Digital LDO to the time at which ACTIVE regulator is disabled [15:8] read-write VDDR_STABLE_DELAY This field holds the delay after HVLDO Startup to VDDR Stable. Refer to memo AKK-410 [23:16] read-write MT_VIO_CTRL MT Configuration Register to control VIO switches 0xB0 32 read-write 0x0 0x3 SRSS_SWITCH_EN Enable to turn on HVLDO (One leg) 1'b0 - Switch is turned off 1'b1 - Switch is turned on [0:0] read-write SRSS_SWITCH_EN_DLY Enable to turn on HVLDO (All legs). This must be enabled 64us after enabling SRSS_SWITCH_EN 1'b0 - Switch is turned off 1'b1 - Switch is turned on [1:1] read-write MT_STATUS MT Status Register 0xB4 32 read-only 0x0 0x1FF BLESS_STATE 1'b0 - BLESS in DPSLP state 1'b1 - BLESS in ACTIVE state [0:0] read-only MT_CURR_STATE This register reflects the current state of the MT FSM 4'h0 - IDLE 4'h1 - BLERD_DEEPSLEEP 4'h2 - HVLDO_STARTUP 4'h3 - WAIT_CLK 4'h4 - BLERD_IDLE 4'h5 - SWITCH_EN 4'h6 - ACTIVE 4'h7 - ISOLATE 4'h8 - WAIT_IDLE 4'h9 - XTAL_DISABLE 4'hA - HVLDO_DISABLE [4:1] read-only HVLDO_STARTUP_CURR_STATE This register reflects the current state of the HVLDO Startup FSM 3'h0 - HVLDO_OFF 3'h1 - HVLDO_WAIT 3'h2 - HVLDO_SAMPLE 3'h3 - HVLDO_ENABLED 3'h4 - HVLDO_SET_BYPASS [7:5] read-only LL_CLK_STATE This bit indicates when the Link Layer registers are accessible upon a DSM exit. This bit should not be used after a DSM entry command has been issued. 1'b0 - Link Layer clock is not available 1'b1 - Link Layer clock is active [8:8] read-only PWR_CTRL_SM_ST Link Layer Power Control FSM Status Register 0xB8 32 read-only 0x0 0xF PWR_CTRL_SM_CURR_STATE This register reflects the current state of the LL Power Control FSM 4'h0 - IDLE 4'h1 - SLEEP 4'h2 - DEEP_SLEEP 4'h4 - WAIT_OSC_STABLE 4'h5 - INTR_GEN 4'h6 - ACTIVE 4'h7 - REQ_RF_OFF [3:0] read-only HVLDO_CTRL HVLDO Configuration register 0xC0 32 read-write 0x0 0x8000005F ADFT_EN ADFT enable [0:0] read-write ADFT_CTRL ADFT select [4:1] read-write VREF_EXT_EN Vref ext input enable. [6:6] read-write STATUS hvldo LV detect status [31:31] read-only MISC_EN_CTRL Radio Buck and Active regulator enable control 0xC4 32 read-write 0x8 0x1F BUCK_EN_CTRL Buck enable control. This must be programmed before enabling the Radio. 1'b1 - Buck enable output to radio is tied to 0 1'b0 - Buck enable output to radio is controlled from Mode transition FSM [0:0] read-write ACT_REG_EN_CTRL Active regulator enable control. This must be programmed before enabling the Radio. 1'b0 - Active regulator enable output to radio is tied to 0 1'b1 - Active regulator enable output to radio is controlled from Mode transition FSM [1:1] read-write LPM_DRIFT_EN Controls the LPM drift calculation. 1 - Enables the LPM drift mod 0 - Disables the LPM drift mod [2:2] read-write LPM_DRIFT_MULTI Controls the LPM drift multi level compensation. 1 - Enables the LPM drift multi comp 0 - Disables the LPM drift multi comp [3:3] read-write LPM_ENTRY_CTRL_MODE Controls the LPM entry control mode 1 - LPM can be entered in the same slot as the previous LPM exit 0 - LPM must not be entered in the same slot or the subsequent slot as the last LPM exit [4:4] read-write EFUSE_CONFIG EFUSE mode configuration register 0xD0 32 read-write 0x0 0x7 EFUSE_MODE This register enables the efuse mode in m0s8bless_ver3 [0:0] read-write EFUSE_READ This bit when set by firmware enables the read from EFUSE macro. It is cleared when the efuse read is completed [1:1] read-write EFUSE_WRITE This bit when set by firmware enables the write to EFUSE macro. It is cleared when the efuse write is completed [2:2] read-write EFUSE_TIM_CTRL1 EFUSE timing control register (common for Program and Read modes) 0xD4 32 read-write 0x111201C0 0xFFFFFFFF SCLK_HIGH Decides the duration of TPGM (in Program mode) or TCKHP (in Read mode) TPGM: Burning Time TCKHP : SCLK high Period [7:0] read-write SCLK_LOW Duration of SCLK LOW (TCLKP_R) or TCKLP_P [15:8] read-write CS_SCLK_SETUP_TIME This register specifies the setup time between CS and SCLK (TSR_CLK) [19:16] read-write CS_SCLK_HOLD_TIME This register specifies the hold time between CS and SCLK (THR_CLK) [23:20] read-write RW_CS_SETUP_TIME This field decides setup time between RW & CS (TSR_RW: in read mode) or RW & AVDD (TSP_RW: in Program mode). TSR_RW: RW to CS setup time into Read mode TSP_RW: RW to AVDD setup time into program mode [27:24] read-write RW_CS_HOLD_TIME This field decides hold time between RW & CS (THR_RW: in read mode) or RW & AVDD (THP_RW: in Program mode). THR_RW: RW to CS hold time out of Read mode THP_RW: RW to AVDD hold time out of program mode [31:28] read-write EFUSE_TIM_CTRL2 EFUSE timing control Register (for Read) 0xD8 32 read-write 0x102 0xFFF DATA_SAMPLE_TIME This register specifies the time for data sampling from SCLK HIGH (TCKDQ_H) [7:0] read-write DOUT_CS_HOLD_TIME Wait time DOUT to CS hold time out of read mode (TDQH) [11:8] read-write EFUSE_TIM_CTRL3 EFUSE timing control Register (for Program) 0xDC 32 read-write 0x3A3A11 0xFFFFFF PGM_SCLK_SETUP_TIME PGM to SCLK setup time (TS_PGM) PGM_SCLK_SETUP_TIME <CS_SCLK_SETUP_TIME [3:0] read-write PGM_SCLK_HOLD_TIME PGM to SCLK hold time (TH_PGM) [7:4] read-write AVDD_CS_SETUP_TIME AVDD to CS setup time into program mode (TSP_AVDD_CS) [15:8] read-write AVDD_CS_HOLD_TIME AVDD to CS hold time out of program mode (THP_AVDD_CS) [23:16] read-write EFUSE_RDATA_L EFUSE Lower read data 0xE0 32 read-only 0x0 0xFFFFFFFF DATA This register has the read value from the Efuse macro, fuse bits[31:0] [31:0] read-only EFUSE_RDATA_H EFUSE higher read data 0xE4 32 read-only 0x0 0xFFFFFFFF DATA This register has the read value from the Efuse macro, fuse bits[63:32] [31:0] read-only EFUSE_WDATA_L EFUSE lower write word 0xE8 32 read-write 0x0 0xFFFFFFFF DATA This register has the write value to the Efuse macro, fuse bits[31:0] [31:0] read-write EFUSE_WDATA_H EFUSE higher write word 0xEC 32 read-write 0x0 0xFFFFFFFF DATA This register has the write value to the Efuse macro, fuse bits[63:32] [31:0] read-write DIV_BY_625_CFG Divide by 625 for FW Use 0xF0 32 read-write 0x0 0xFFFF02 ENABLE This bit enables the divider for use by FW 1'b0 - divider used by LL 1'b1 - divider can be used by FW This divider can only be used in MMMS mode. Do not enable for legacy operation [1:1] read-write DIVIDEND This field holds the dividend [23:8] read-write DIV_BY_625_STS Output of divide by 625 divider 0xF4 32 read-only 0x100 0x3FF3F QUOTIENT Quotient value from the divider. Available 1 cycle after dividend is programmed. [5:0] read-only REMAINDER Remainder value from the divider. Available 1 cycle after dividend is programmed. [17:8] read-only PACKET_COUNTER0 Packet counter 0 0x100 32 read-write 0x0 0xFFFFFFFF PACKET_COUNTER_LOWER Lower 32-bits of the packet counter value passed as part of Nonce for the packet to be encrypted. [31:0] read-write PACKET_COUNTER2 Packet counter 2 0x104 32 read-write 0x0 0xFF PACKET_COUNTER_UPPER Upper 8 bits of the packet counter value passed as part of Nonce for the packet to be encrypted. [7:0] read-write IV_MASTER0 Master Initialization Vector 0 0x108 32 read-write 0x0 0xFFFFFFFF IV_MASTER This is the IVm field, which contains the master's portion of the initialization vector. [31:0] read-write IV_SLAVE0 Slave Initialization Vector 0 0x10C 32 read-write 0x0 0xFFFFFFFF IV_SLAVE This is the IVs field, which contains the slave's portion of the initialization vector. [31:0] read-write 4 4 ENC_KEY[%s] Encryption Key register 0-3 0x110 32 write-only 0x0 0xFFFFFFFF ENC_KEY The encryption key / session key which is used in ECB encryption, CCM encryption and CCM decryption. [31:0] write-only MIC_IN0 MIC input register 0x120 32 read-write 0x0 0xFFFFFFFF MIC_IN This is the MIC field used for CCM decryption. [31:0] read-write MIC_OUT0 MIC output register 0x124 32 read-only 0x0 0xFFFFFFFF MIC_OUT This is the MIC generated during CCM encryption. [31:0] read-only ENC_PARAMS Encryption Parameter register 0x128 32 read-write 0x0 0xFFF DATA_PDU_HEADER LLID of the packet. [1:0] read-write PAYLOAD_LENGTH_LSB Length of the input data. [6:2] read-write DIRECTION The directionBit shall be set to '1' for Data Channel PDUs sent by the master and set to '0' for Data Channel PDUs sent by the slave. [7:7] read-write PAYLOAD_LENGTH_LSB_EXT 3 Most significant bits of the LS byte of the length of the input data. Valid only when DLE is enabled. When DLE is enabled total ENC payload length = {PAYLOAD_LENGTH_LSB_EXT, PAYLOAD_LENGTH_LSB} [10:8] read-write MEM_LATENCY_HIDE Controls the encryption memory access mode. Valid only when DLE is enabled. 0 - The AES is idle while memory fetch/store in progress. 1- The AES is pipelined while memory fetch/store in progress. [11:11] read-write ENC_CONFIG Encryption Configuration 0x12C 32 read-write 0x0 0x1FFFF07 START_PROC 1 Start the AES processing [0:0] read-write ECB_CCM 0 - CCM 1 - ECB [1:1] read-write DEC_ENC Decryption/Encryption 0 - Encrypt 1 - Decrypt [2:2] read-write PAYLOAD_LENGTH_MSB MS byte of the length of the input data when B0 needs to be completely configurable. Valid only when AES_B0_DATA_OVERRIDE is enabled. When AES_B0_DATA_OVERRIDE is enabled total ENC payload length = {PAYLOAD_LENGTH_MSB, PAYLOAD_LENGTH_MSB, PAYLOAD_LENGTH} [15:8] read-write B0_FLAGS LS byte of the input data when B0 needs to be completely configurable. Valid only when AES_B0_DATA_OVERRIDE is enabled. [23:16] read-write AES_B0_DATA_OVERRIDE Configuration to use B0 DATA provided by FW for CCM computation [24:24] read-write ENC_INTR_EN Encryption Interrupt enable 0x130 32 read-write 0x0 0x7 AUTH_PASS_INTR_EN Authentication interrupt enable 0 - Disable 1 - Enable [0:0] read-write ECB_PROC_INTR_EN ECB processed interrupt enable 0 - Disable 1 - Enable [1:1] read-write CCM_PROC_INTR_EN CCM processed interupt enable 0 - Disable 1 - Enable [2:2] read-write ENC_INTR Encryption Interrupt status and clear register 0x134 32 read-write 0x0 0xF AUTH_PASS_INTR Authentication interrupt. 0x1- indicates MIC matched 0x0 -indicated MIC mismatched Writing 1 to this register clears the interrupt. [0:0] read-write ECB_PROC_INTR ECB processed interrupt. Writing 1 to this register clears the interrupt. [1:1] read-write CCM_PROC_INTR CCM processed interrupt. Writing 1 to this register clears the interrupt [2:2] read-write IN_DATA_CLEAR Clears the input data. Used for Zero padding of encryption for less than block sized data. [3:3] read-write 4 4 B1_DATA_REG[%s] Programmable B1 Data register (0-3) 0x140 32 read-write 0x0 0xFFFFFFFF B1_DATA Programmable B1 Data register [31:0] read-write ENC_MEM_BASE_ADDR Encryption memory base address 0x150 32 read-write 0x0 0xFFFFFFFF ENC_MEM Data values written to Enc memory are written as 16-bit wide data. This memory is valid only if DLE is set. [31:0] read-write TRIM_LDO_0 LDO Trim register 0 0xF00 32 read-write 0x58 0xFF ACT_LDO_VREG To trim the regulated voltage in steps of 25mV typically [3:0] read-write ACT_LDO_ITAIL To trim the bias currents for all the active mode blocks [7:4] read-write TRIM_LDO_1 LDO Trim register 1 0xF04 32 read-write 0x8 0xFF ACT_REF_BGR To trim active regulator reference voltage [3:0] read-write SB_BGRES To trim standby regulator reference voltage [7:4] read-write TRIM_LDO_2 LDO Trim register 2 0xF08 32 read-write 0x60 0x7F SB_BMULT_RES To trim standby regulator beta-multiplier current [4:0] read-write SB_BMULT_NBIAS To trim standby regulator beta-multiplier current [6:5] read-write TRIM_LDO_3 LDO Trim register 3 0xF0C 32 read-write 0x10 0x7F LVDET To trim the trip points of the LV-Detect block [4:0] read-write SLOPE_SB_BMULT To trim standby regulator beta-multiplier temp-co slope [6:5] read-write 4 4 TRIM_MXD[%s] MXD die Trim registers 0xF10 32 read-write 0x0 0xFF MXD_TRIM_BITS MXD trim bits [7:0] read-write TRIM_LDO_4 LDO Trim register 4 0xF30 32 read-write 0x0 0xFF T_LDO To debug post layout or post silicon [7:0] read-write TRIM_LDO_5 LDO Trim register 5 0xF34 32 read-write 0x0 0xFF RSVD N/A [7:0] read-write USBFS0 USB Host and Device Controller USBFS 0x403F0000 0 65536 registers USBDEV USB Device 0x00000000 8 4 EP0_DR[%s] Control End point EP0 Data Register 0x0 32 read-write 0x0 0xFF DATA_BYTE This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred. [7:0] read-write CR0 USB control 0 Register 0x20 32 read-write 0x0 0xFF DEVICE_ADDRESS These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware. If USB bus reset is detected, these bits are initialized. Refer to CDT#293217. [6:0] read-write USB_ENABLE This bit enables the device to respond to USB traffic. If USB bus reset is detected, this bit is cleared. Note: When USB PHY is GPIO mode(USBIO_CR1.IOMODE=0), USB bus reset is detected. Therefore, when USB PHY is GPIO mode, this bit is cleared even if this bit is set to 1. If this bit is set to 1, write this bit upon USB bus reset interrupt, and do not write to this bit during initialization steps. Refer to CDT#293217. [7:7] read-write CR1 USB control 1 Register 0x24 32 read-write 0x0 0xF REG_ENABLE This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply. [0:0] read-write ENABLE_LOCK This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation. [1:1] read-write BUS_ACTIVITY The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High value until firmware clears it. [2:2] read-write RSVD_3 N/A [3:3] read-write SIE_EP_INT_EN USB SIE Data Endpoints Interrupt Enable Register 0x28 32 read-write 0x0 0xFF EP1_INTR_EN Enables interrupt for EP1 [0:0] read-write EP2_INTR_EN Enables interrupt for EP2 [1:1] read-write EP3_INTR_EN Enables interrupt for EP3 [2:2] read-write EP4_INTR_EN Enables interrupt for EP4 [3:3] read-write EP5_INTR_EN Enables interrupt for EP5 [4:4] read-write EP6_INTR_EN Enables interrupt for EP6 [5:5] read-write EP7_INTR_EN Enables interrupt for EP7 [6:6] read-write EP8_INTR_EN Enables interrupt for EP8 [7:7] read-write SIE_EP_INT_SR USB SIE Data Endpoint Interrupt Status 0x2C 32 read-write 0x0 0xFF EP1_INTR Interrupt status for EP1 [0:0] read-write EP2_INTR Interrupt status for EP2 [1:1] read-write EP3_INTR Interrupt status for EP3 [2:2] read-write EP4_INTR Interrupt status for EP4 [3:3] read-write EP5_INTR Interrupt status for EP5 [4:4] read-write EP6_INTR Interrupt status for EP6 [5:5] read-write EP7_INTR Interrupt status for EP7 [6:6] read-write EP8_INTR Interrupt status for EP8 [7:7] read-write SIE_EP1_CNT0 Non-control endpoint count register 0x30 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP1_CNT1 Non-control endpoint count register 0x34 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP1_CR0 Non-control endpoint's control Register 0x38 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write USBIO_CR0 USBIO Control 0 Register 0x40 32 read-write 0x0 0xE0 RD Received Data. This read only bit gives the state of the USB differential receiver when IOMODE bit is '0' and USB doesn't transmit. This bit is valid if USB Device. If D+=D- (SE0), this value is undefined. [0:0] read-only DIFF_LOW D+ < D- (K state) 0 DIFF_HIGH D+ > D- (J state) 1 TD Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1. [5:5] read-write DIFF_K Force USB K state (D+ is low D- is high). 0 DIFF_J Force USB J state (D+ is high D- is low). 1 TSE0 Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0. [6:6] read-write TEN USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually transmitting is to force a resume state on the bus. [7:7] read-write USBIO_CR2 USBIO control 2 Register 0x44 32 read-write 0x0 0xFF RSVD_5_0 N/A [5:0] read-only TEST_PKT This bit enables the device to transmit a packet in response to an internally generated IN packet. When set, one packet will be generated. [6:6] read-write RSVD_7 N/A [7:7] read-write USBIO_CR1 USBIO control 1 Register 0x48 32 read-write 0x20 0x20 DMO This read only bit gives the state of the D- pin when IOMODE bit is '0' and USB doesn't transmit. This bit is '0' when USB transmits SE0, and this bit is '1' when USB transmits other than SE0. This bit is valid if USB Device. [0:0] read-only DPO This read only bit gives the state of the D+ pin when IOMODE bit is '0' and USB doesn't transmit. This bit displays the output value of D+ pin when USB transmits SE0 or data. This bit is valid if USB Device. [1:1] read-only RSVD_2 N/A [2:2] read-write IOMODE This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins. [5:5] read-write DYN_RECONFIG USB Dynamic reconfiguration register 0x50 32 read-write 0x0 0x1F DYN_CONFIG_EN This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1, indicates the reconfiguration required for selected EP. Use 0 for EP1, 1 for EP2, etc. [0:0] read-write DYN_RECONFIG_EPNO These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1. [3:1] read-write DYN_RECONFIG_RDY_STS This bit indicates the ready status for the dynamic reconfiguration, when set to 1, indicates the block is ready for reconfiguration. [4:4] read-only SOF0 Start Of Frame Register 0x60 32 read-only 0x0 0xFF FRAME_NUMBER It has the lower 8 bits [7:0] of the SOF frame number. [7:0] read-only SOF1 Start Of Frame Register 0x64 32 read-only 0x0 0x7 FRAME_NUMBER_MSB It has the upper 3 bits [10:8] of the SOF frame number. [2:0] read-only SIE_EP2_CNT0 Non-control endpoint count register 0x70 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP2_CNT1 Non-control endpoint count register 0x74 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP2_CR0 Non-control endpoint's control Register 0x78 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write OSCLK_DR0 Oscillator lock data register 0 0x80 32 read-only 0x0 0x0 ADDER These bits return the lower 8 bits of the oscillator locking circuits adder output. [7:0] read-only OSCLK_DR1 Oscillator lock data register 1 0x84 32 read-only 0x0 0x0 ADDER_MSB These bits return the upper 7 bits of the oscillator locking circuits adder output. [6:0] read-only EP0_CR Endpoint0 control Register 0xA0 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 OUT_RCVD When set this bit indicates a valid OUT packet has been received and ACKed. This bit is updated to '1' after the last received packet in an OUT transaction. When clear this bit indicates no OUT received. It is cleared by any writes to the register. [5:5] read-write IN_RCVD When set this bit indicates a valid IN packet has been received. This bit is updated to '1' after the host acknowledges an IN data packet. When clear this bit indicates either no IN has been received or that the host did not acknowledge the IN data by sending ACK handshake. It is cleared by any writes to the register. [6:6] read-write SETUP_RCVD When set this bit indicates a valid SETUP packet was received and ACKed. This bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval. After this interval the bit will remain set until cleared by firmware. While this bit is set to '1' the CPU cannot write to the EP0_DRx registers. This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data. This bit is cleared by any non-locked writes to the register. [7:7] read-write EP0_CNT Endpoint0 count Register 0xA4 32 read-write 0x0 0xCF BYTE_COUNT These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10. [3:0] read-write DATA_VALID This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP3_CNT0 Non-control endpoint count register 0xB0 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP3_CNT1 Non-control endpoint count register 0xB4 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP3_CR0 Non-control endpoint's control Register 0xB8 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write SIE_EP4_CNT0 Non-control endpoint count register 0xF0 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP4_CNT1 Non-control endpoint count register 0xF4 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP4_CR0 Non-control endpoint's control Register 0xF8 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write SIE_EP5_CNT0 Non-control endpoint count register 0x130 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP5_CNT1 Non-control endpoint count register 0x134 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP5_CR0 Non-control endpoint's control Register 0x138 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write SIE_EP6_CNT0 Non-control endpoint count register 0x170 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP6_CNT1 Non-control endpoint count register 0x174 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP6_CR0 Non-control endpoint's control Register 0x178 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write SIE_EP7_CNT0 Non-control endpoint count register 0x1B0 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP7_CNT1 Non-control endpoint count register 0x1B4 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP7_CR0 Non-control endpoint's control Register 0x1B8 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write SIE_EP8_CNT0 Non-control endpoint count register 0x1F0 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP8_CNT1 Non-control endpoint count register 0x1F4 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP8_CR0 Non-control endpoint's control Register 0x1F8 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write ARB_EP1_CFG Endpoint Configuration Register *1 0x200 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP1_INT_EN Endpoint Interrupt Enable Register *1 0x204 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP1_SR Endpoint Interrupt Enable Register *1 0x208 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW1_WA Endpoint Write Address value *1 0x210 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW1_WA_MSB Endpoint Write Address value *1 0x214 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW1_RA Endpoint Read Address value *1 0x218 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW1_RA_MSB Endpoint Read Address value *1 0x21C 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW1_DR Endpoint Data Register 0x220 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write BUF_SIZE Dedicated Endpoint Buffer Size Register *1 0x230 32 read-write 0x0 0xFF IN_BUF Buffer size for IN Endpoints. [3:0] read-write OUT_BUF Buffer size for OUT Endpoints. [7:4] read-write EP_ACTIVE Endpoint Active Indication Register *1 0x238 32 read-write 0x0 0xFF EP1_ACT Indicates that Endpoint is currently active. [0:0] read-write EP2_ACT Indicates that Endpoint is currently active. [1:1] read-write EP3_ACT Indicates that Endpoint is currently active. [2:2] read-write EP4_ACT Indicates that Endpoint is currently active. [3:3] read-write EP5_ACT Indicates that Endpoint is currently active. [4:4] read-write EP6_ACT Indicates that Endpoint is currently active. [5:5] read-write EP7_ACT Indicates that Endpoint is currently active. [6:6] read-write EP8_ACT Indicates that Endpoint is currently active. [7:7] read-write EP_TYPE Endpoint Type (IN/OUT) Indication *1 0x23C 32 read-write 0x0 0xFF EP1_TYP Endpoint Type Indication. [0:0] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP2_TYP Endpoint Type Indication. [1:1] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP3_TYP Endpoint Type Indication. [2:2] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP4_TYP Endpoint Type Indication. [3:3] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP5_TYP Endpoint Type Indication. [4:4] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP6_TYP Endpoint Type Indication. [5:5] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP7_TYP Endpoint Type Indication. [6:6] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP8_TYP Endpoint Type Indication. [7:7] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 ARB_EP2_CFG Endpoint Configuration Register *1 0x240 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP2_INT_EN Endpoint Interrupt Enable Register *1 0x244 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP2_SR Endpoint Interrupt Enable Register *1 0x248 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW2_WA Endpoint Write Address value *1 0x250 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW2_WA_MSB Endpoint Write Address value *1 0x254 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW2_RA Endpoint Read Address value *1 0x258 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW2_RA_MSB Endpoint Read Address value *1 0x25C 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW2_DR Endpoint Data Register 0x260 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write ARB_CFG Arbiter Configuration Register *1 0x270 32 read-write 0x0 0xF0 AUTO_MEM Enables Auto Memory Configuration. Manual memory configuration by default. [4:4] read-write DMA_CFG DMA Access Configuration. [6:5] read-write DMA_NONE No DMA 0 DMA_MANUAL Manual DMA 1 DMA_AUTO Auto DMA 2 CFG_CMP Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required. [7:7] read-write USB_CLK_EN USB Block Clock Enable Register 0x274 32 read-write 0x0 0x1 CSR_CLK_EN Clock Enable for Core Logic clocked by AHB bus clock [0:0] read-write ARB_INT_EN Arbiter Interrupt Enable *1 0x278 32 read-write 0x0 0xFF EP1_INTR_EN Enables interrupt for EP1 [0:0] read-write EP2_INTR_EN Enables interrupt for EP2 [1:1] read-write EP3_INTR_EN Enables interrupt for EP3 [2:2] read-write EP4_INTR_EN Enables interrupt for EP4 [3:3] read-write EP5_INTR_EN Enables interrupt for EP5 [4:4] read-write EP6_INTR_EN Enables interrupt for EP6 [5:5] read-write EP7_INTR_EN Enables interrupt for EP7 [6:6] read-write EP8_INTR_EN Enables interrupt for EP8 [7:7] read-write ARB_INT_SR Arbiter Interrupt Status *1 0x27C 32 read-only 0x0 0xFF EP1_INTR Interrupt status for EP1 [0:0] read-only EP2_INTR Interrupt status for EP2 [1:1] read-only EP3_INTR Interrupt status for EP3 [2:2] read-only EP4_INTR Interrupt status for EP4 [3:3] read-only EP5_INTR Interrupt status for EP5 [4:4] read-only EP6_INTR Interrupt status for EP6 [5:5] read-only EP7_INTR Interrupt status for EP7 [6:6] read-only EP8_INTR Interrupt status for EP8 [7:7] read-only ARB_EP3_CFG Endpoint Configuration Register *1 0x280 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP3_INT_EN Endpoint Interrupt Enable Register *1 0x284 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP3_SR Endpoint Interrupt Enable Register *1 0x288 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW3_WA Endpoint Write Address value *1 0x290 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW3_WA_MSB Endpoint Write Address value *1 0x294 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW3_RA Endpoint Read Address value *1 0x298 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW3_RA_MSB Endpoint Read Address value *1 0x29C 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW3_DR Endpoint Data Register 0x2A0 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write CWA Common Area Write Address *1 0x2B0 32 read-write 0x0 0xFF CWA Write Address for Common Area [7:0] read-write CWA_MSB Endpoint Read Address value *1 0x2B4 32 read-write 0x0 0x1 CWA_MSB Write Address for Common Area [0:0] read-write ARB_EP4_CFG Endpoint Configuration Register *1 0x2C0 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP4_INT_EN Endpoint Interrupt Enable Register *1 0x2C4 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP4_SR Endpoint Interrupt Enable Register *1 0x2C8 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW4_WA Endpoint Write Address value *1 0x2D0 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW4_WA_MSB Endpoint Write Address value *1 0x2D4 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW4_RA Endpoint Read Address value *1 0x2D8 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW4_RA_MSB Endpoint Read Address value *1 0x2DC 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW4_DR Endpoint Data Register 0x2E0 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write DMA_THRES DMA Burst / Threshold Configuration 0x2F0 32 read-write 0x0 0xFF DMA_THS DMA Threshold count [7:0] read-write DMA_THRES_MSB DMA Burst / Threshold Configuration 0x2F4 32 read-write 0x0 0x1 DMA_THS_MSB DMA Threshold count [0:0] read-write ARB_EP5_CFG Endpoint Configuration Register *1 0x300 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP5_INT_EN Endpoint Interrupt Enable Register *1 0x304 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP5_SR Endpoint Interrupt Enable Register *1 0x308 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW5_WA Endpoint Write Address value *1 0x310 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW5_WA_MSB Endpoint Write Address value *1 0x314 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW5_RA Endpoint Read Address value *1 0x318 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW5_RA_MSB Endpoint Read Address value *1 0x31C 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW5_DR Endpoint Data Register 0x320 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write BUS_RST_CNT Bus Reset Count Register 0x330 32 read-write 0xA 0xF BUS_RST_CNT Bus Reset Count Length [3:0] read-write ARB_EP6_CFG Endpoint Configuration Register *1 0x340 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP6_INT_EN Endpoint Interrupt Enable Register *1 0x344 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP6_SR Endpoint Interrupt Enable Register *1 0x348 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW6_WA Endpoint Write Address value *1 0x350 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW6_WA_MSB Endpoint Write Address value *1 0x354 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW6_RA Endpoint Read Address value *1 0x358 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW6_RA_MSB Endpoint Read Address value *1 0x35C 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW6_DR Endpoint Data Register 0x360 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write ARB_EP7_CFG Endpoint Configuration Register *1 0x380 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP7_INT_EN Endpoint Interrupt Enable Register *1 0x384 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP7_SR Endpoint Interrupt Enable Register *1 0x388 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW7_WA Endpoint Write Address value *1 0x390 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW7_WA_MSB Endpoint Write Address value *1 0x394 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW7_RA Endpoint Read Address value *1 0x398 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW7_RA_MSB Endpoint Read Address value *1 0x39C 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW7_DR Endpoint Data Register 0x3A0 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write ARB_EP8_CFG Endpoint Configuration Register *1 0x3C0 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP8_INT_EN Endpoint Interrupt Enable Register *1 0x3C4 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP8_SR Endpoint Interrupt Enable Register *1 0x3C8 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW8_WA Endpoint Write Address value *1 0x3D0 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW8_WA_MSB Endpoint Write Address value *1 0x3D4 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW8_RA Endpoint Read Address value *1 0x3D8 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW8_RA_MSB Endpoint Read Address value *1 0x3DC 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW8_DR Endpoint Data Register 0x3E0 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write 512 4 MEM_DATA[%s] DATA 0x400 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write SOF16 Start Of Frame Register 0x1060 32 read-only 0x0 0x7FF FRAME_NUMBER16 The frame number (11b) [10:0] read-only OSCLK_DR16 Oscillator lock data register 0x1080 32 read-only 0x0 0x0 ADDER16 These bits return the oscillator locking circuits adder output. [14:0] read-only ARB_RW1_WA16 Endpoint Write Address value 0x1210 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW1_RA16 Endpoint Read Address value 0x1218 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW1_DR16 Endpoint Data Register 0x1220 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write ARB_RW2_WA16 Endpoint Write Address value 0x1250 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW2_RA16 Endpoint Read Address value 0x1258 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW2_DR16 Endpoint Data Register 0x1260 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write ARB_RW3_WA16 Endpoint Write Address value 0x1290 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW3_RA16 Endpoint Read Address value 0x1298 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW3_DR16 Endpoint Data Register 0x12A0 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write CWA16 Common Area Write Address 0x12B0 32 read-write 0x0 0x1FF CWA16 Write Address for Common Area [8:0] read-write ARB_RW4_WA16 Endpoint Write Address value 0x12D0 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW4_RA16 Endpoint Read Address value 0x12D8 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW4_DR16 Endpoint Data Register 0x12E0 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write DMA_THRES16 DMA Burst / Threshold Configuration 0x12F0 32 read-write 0x0 0x1FF DMA_THS16 DMA Threshold count [8:0] read-write ARB_RW5_WA16 Endpoint Write Address value 0x1310 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW5_RA16 Endpoint Read Address value 0x1318 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW5_DR16 Endpoint Data Register 0x1320 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write ARB_RW6_WA16 Endpoint Write Address value 0x1350 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW6_RA16 Endpoint Read Address value 0x1358 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW6_DR16 Endpoint Data Register 0x1360 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write ARB_RW7_WA16 Endpoint Write Address value 0x1390 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW7_RA16 Endpoint Read Address value 0x1398 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW7_DR16 Endpoint Data Register 0x13A0 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write ARB_RW8_WA16 Endpoint Write Address value 0x13D0 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW8_RA16 Endpoint Read Address value 0x13D8 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW8_DR16 Endpoint Data Register 0x13E0 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write USBLPM USB Device LPM and PHY Test 0x00002000 POWER_CTL Power Control Register 0x0 32 read-write 0x0 0x303F0004 SUSPEND Put PHY into Suspend mode. If the PHY is enabled, this bit MUST be set before entering a low power mode (DeepSleep). Note: - This bit is invalid if the HOST bit of the Host Control 0 Register (HOST_CTL0) is '1'. [2:2] read-write DP_UP_EN Enables the pull up on the DP. '0' : Disable. '1' : Enable. [16:16] read-write DP_BIG Select the resister value if POWER_CTL.DP_EN='1'. This bit is valid in GPIO. '0' : The resister value is from 900 to1575Opull up on the DP. '1' : The resister value is from 1425 to 3090Opull up on the DP [17:17] read-write DP_DOWN_EN Enables the ~15k pull down on the DP. [18:18] read-write DM_UP_EN Enables the pull up on the DM. The bit is valid in GPIO. The pull up resistor is disabled in not GPIO. '0' : Disable. '1' : Enable. [19:19] read-write DM_BIG Select the resister value if POWER_CTL.DM_EN='1'. This bit is valid in GPIO. '0' : The resister value is from 900 to1575Opull up on the DM. '1' : The resister value is from 1425 to 3090Opull up on the DM [20:20] read-write DM_DOWN_EN Enables the ~15k pull down on the DP. [21:21] read-write ENABLE_DPO Enables the single ended receiver on D+. [28:28] read-write ENABLE_DMO Enables the signle ended receiver on D-. [29:29] read-write USBIO_CTL USB IO Control Register 0x8 32 read-write 0x0 0x3F DM_P The GPIO Drive Mode for DP IO pad. This field only applies if USBIO_CR1.IOMODE =1. Data comes from the corresponding GPIO.DR register. [2:0] read-write OFF Mode 0: Output buffer off (high Z). Input buffer off. 0 INPUT Mode 1: Output buffer off (high Z). Input buffer on. Other values, not supported. 1 DM_M The GPIO Drive Mode for DM IO pad. [5:3] read-write FLOW_CTL Flow Control Register 0xC 32 read-write 0x0 0xFF EP1_ERR_RESP End Point 1 error response 0: do nothing (backward compatibility mode) 1: if this is an IN EP and an underflow occurs then cause a CRC error, if this is an OUT EP and an overflow occurs then send a NAK [0:0] read-write EP2_ERR_RESP End Point 2 error response [1:1] read-write EP3_ERR_RESP End Point 3 error response [2:2] read-write EP4_ERR_RESP End Point 4 error response [3:3] read-write EP5_ERR_RESP End Point 5 error response [4:4] read-write EP6_ERR_RESP End Point 6 error response [5:5] read-write EP7_ERR_RESP End Point 7 error response [6:6] read-write EP8_ERR_RESP End Point 8 error response [7:7] read-write LPM_CTL LPM Control Register 0x10 32 read-write 0x0 0x17 LPM_EN LPM enable 0: Disabled, LPM token will not get a response (backward compatibility mode) 1: Enable, LPM token will get a handshake response (ACK, STALL, NYET or NAK) A STALL will be sent if the bLinkState is not 0001b A NYET, NAK or ACK response will be sent depending on the NYET_EN and LPM_ACK_RESP bits below [0:0] read-write LPM_ACK_RESP LPM ACK response enable (if LPM_EN=1), to allow firmware to refuse a low power request 0: a LPM token will get a NYET or NAK (depending on NYET_EN bit below) response and the device will NOT go to a low power mode 1: a LPM token will get an ACK response and the device will go to the requested low power mode [1:1] read-write NYET_EN Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the device is NOT ready to go to the requested low power mode (LPM_ACK_RESP=0). 0: a LPM token will get an NAK response (indicating a CRC error), the host is expected to repeat the LPM token. 1: a LPM token will get a NYET response [2:2] read-write SUB_RESP Enable a STALL response for all undefined SubPIDs, i.e. other than LPM (0011b). If not enabled then there will be no response (Error) for the undefined SubPIDs. [4:4] read-write LPM_STAT LPM Status register 0x14 32 read-only 0x0 0x1F LPM_BESL Best Effort Service Latency This value should match either the Baseline (DeepSleep) or Deep (Hibernate) BESL in the BOS descriptor. [3:0] read-only LPM_REMOTEWAKE 0: Device is prohibited from initiating a remote wake 1: Device is allow to wake the host [4:4] read-only INTR_SIE USB SOF, BUS RESET and EP0 Interrupt Status 0x20 32 read-write 0x0 0x1F SOF_INTR Interrupt status for USB SOF [0:0] read-write BUS_RESET_INTR Interrupt status for BUS RESET [1:1] read-write EP0_INTR Interrupt status for EP0 [2:2] read-write LPM_INTR Interrupt status for LPM (Link Power Management, L1 entry) [3:3] read-write RESUME_INTR Interrupt status for Resume [4:4] read-write INTR_SIE_SET USB SOF, BUS RESET and EP0 Interrupt Set 0x24 32 read-write 0x0 0x1F SOF_INTR_SET Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write BUS_RESET_INTR_SET Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write EP0_INTR_SET Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write LPM_INTR_SET Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write RESUME_INTR_SET Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write INTR_SIE_MASK USB SOF, BUS RESET and EP0 Interrupt Mask 0x28 32 read-write 0x0 0x1F SOF_INTR_MASK Set to 1 to enable interrupt corresponding to interrupt request register [0:0] read-write BUS_RESET_INTR_MASK Set to 1 to enable interrupt corresponding to interrupt request register [1:1] read-write EP0_INTR_MASK Set to 1 to enable interrupt corresponding to interrupt request register [2:2] read-write LPM_INTR_MASK Set to 1 to enable interrupt corresponding to interrupt request register [3:3] read-write RESUME_INTR_MASK Set to 1 to enable interrupt corresponding to interrupt request register [4:4] read-write INTR_SIE_MASKED USB SOF, BUS RESET and EP0 Interrupt Masked 0x2C 32 read-only 0x0 0x1F SOF_INTR_MASKED Logical and of corresponding request and mask bits. [0:0] read-only BUS_RESET_INTR_MASKED Logical and of corresponding request and mask bits. [1:1] read-only EP0_INTR_MASKED Logical and of corresponding request and mask bits. [2:2] read-only LPM_INTR_MASKED Logical and of corresponding request and mask bits. [3:3] read-only RESUME_INTR_MASKED Logical and of corresponding request and mask bits. [4:4] read-only INTR_LVL_SEL Select interrupt level for each interrupt source 0x30 32 read-write 0x0 0xFFFFC3FF SOF_LVL_SEL USB SOF Interrupt level select [1:0] read-write HI High priority interrupt 0 MED Medium priority interrupt 1 LO Low priority interrupt 2 RSVD illegal 3 BUS_RESET_LVL_SEL BUS RESET Interrupt level select [3:2] read-write EP0_LVL_SEL EP0 Interrupt level select [5:4] read-write LPM_LVL_SEL LPM Interrupt level select [7:6] read-write RESUME_LVL_SEL Resume Interrupt level select [9:8] read-write ARB_EP_LVL_SEL Arbiter Endpoint Interrupt level select [15:14] read-write EP1_LVL_SEL EP1 Interrupt level select [17:16] read-write EP2_LVL_SEL EP2 Interrupt level select [19:18] read-write EP3_LVL_SEL EP3 Interrupt level select [21:20] read-write EP4_LVL_SEL EP4 Interrupt level select [23:22] read-write EP5_LVL_SEL EP5 Interrupt level select [25:24] read-write EP6_LVL_SEL EP6 Interrupt level select [27:26] read-write EP7_LVL_SEL EP7 Interrupt level select [29:28] read-write EP8_LVL_SEL EP8 Interrupt level select [31:30] read-write INTR_CAUSE_HI High priority interrupt Cause register 0x34 32 read-only 0x0 0xFF9F SOF_INTR USB SOF Interrupt [0:0] read-only BUS_RESET_INTR BUS RESET Interrupt [1:1] read-only EP0_INTR EP0 Interrupt [2:2] read-only LPM_INTR LPM Interrupt [3:3] read-only RESUME_INTR Resume Interrupt [4:4] read-only ARB_EP_INTR Arbiter Endpoint Interrupt [7:7] read-only EP1_INTR EP1 Interrupt [8:8] read-only EP2_INTR EP2 Interrupt [9:9] read-only EP3_INTR EP3 Interrupt [10:10] read-only EP4_INTR EP4 Interrupt [11:11] read-only EP5_INTR EP5 Interrupt [12:12] read-only EP6_INTR EP6 Interrupt [13:13] read-only EP7_INTR EP7 Interrupt [14:14] read-only EP8_INTR EP8 Interrupt [15:15] read-only INTR_CAUSE_MED Medium priority interrupt Cause register 0x38 32 read-only 0x0 0xFF9F SOF_INTR USB SOF Interrupt [0:0] read-only BUS_RESET_INTR BUS RESET Interrupt [1:1] read-only EP0_INTR EP0 Interrupt [2:2] read-only LPM_INTR LPM Interrupt [3:3] read-only RESUME_INTR Resume Interrupt [4:4] read-only ARB_EP_INTR Arbiter Endpoint Interrupt [7:7] read-only EP1_INTR EP1 Interrupt [8:8] read-only EP2_INTR EP2 Interrupt [9:9] read-only EP3_INTR EP3 Interrupt [10:10] read-only EP4_INTR EP4 Interrupt [11:11] read-only EP5_INTR EP5 Interrupt [12:12] read-only EP6_INTR EP6 Interrupt [13:13] read-only EP7_INTR EP7 Interrupt [14:14] read-only EP8_INTR EP8 Interrupt [15:15] read-only INTR_CAUSE_LO Low priority interrupt Cause register 0x3C 32 read-only 0x0 0xFF9F SOF_INTR USB SOF Interrupt [0:0] read-only BUS_RESET_INTR BUS RESET Interrupt [1:1] read-only EP0_INTR EP0 Interrupt [2:2] read-only LPM_INTR LPM Interrupt [3:3] read-only RESUME_INTR Resume Interrupt [4:4] read-only ARB_EP_INTR Arbiter Endpoint Interrupt [7:7] read-only EP1_INTR EP1 Interrupt [8:8] read-only EP2_INTR EP2 Interrupt [9:9] read-only EP3_INTR EP3 Interrupt [10:10] read-only EP4_INTR EP4 Interrupt [11:11] read-only EP5_INTR EP5 Interrupt [12:12] read-only EP6_INTR EP6 Interrupt [13:13] read-only EP7_INTR EP7 Interrupt [14:14] read-only EP8_INTR EP8 Interrupt [15:15] read-only DFT_CTL DFT control 0x70 32 read-write 0x0 0x1F DDFT_OUT_SEL DDFT output select signal [2:0] read-write OFF Nothing connected, output 0 0 DP_SE Single Ended output of DP 1 DM_SE Single Ended output of DM 2 TXOE Output Enable 3 RCV_DF Differential Receiver output 4 GPIO_DP_OUT GPIO output of DP 5 GPIO_DM_OUT GPIO output of DM 6 DDFT_IN_SEL DDFT input select signal [4:3] read-write OFF Nothing connected, output 0 0 GPIO_DP_IN GPIO input of DP 1 GPIO_DM_IN GPIO input of DM 2 USBHOST USB Host Controller 0x00004000 HOST_CTL0 Host Control 0 Register. 0x0 32 read-write 0x0 0x80000001 HOST This bit selects an operating mode of this IP. '0' : USB Device '1' : USB Host Notes: - The operation mode does not transition to the required one immediately after it was changed using this bit. Read this bit to check that the operation mode has changed. - This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'.. - Before changing from the USB Host to the USB Device, check that the following conditions are satisfied and also set the RST bit of the Host Control 1 Register (HOST_CTL1). to '1'. * The SOFBUSY bit of the Host Status Register (HOST_STATUS) is set to '0'. * The TKNEN bits of the Host Token Endpoint Register (HOST_TOKEN) is set to '000'. * The SUSP bit of the Host Status Register (HOST_STATUS) is set to '0'. [0:0] read-write ENABLE This bit enables the operation of this IP. '0' : Disable USB Host '1' : Enable USB Host Note: - This bit doesn' affect the USB Device. [31:31] read-write HOST_CTL1 Host Control 1 Register. 0x10 32 read-write 0x83 0x83 CLKSEL This bit selects the operating clock of USB Host. '0' : Low-speed clock '1' : Full-speed clock Notes: - This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. - This bit must always be set to '1' in the USB Device mode. [0:0] read-write USTP This bit stops the clock for the USB Host operating unit. When this bit is '1', power consumption can be reduced by configuring this bit. '0' : Normal mode. '1' : Stops the clock for the USB Host operating unit. Notes: - If this bit is set to '1', the function of USB Host can't be used because internal clock is stopped. - This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. [1:1] read-write RST This bit resets this IP. '0' : Releases the reset for USB Host. '1' : Resets USB Host. Notes: - This bit is initialized if ENABLE bit of the Host Control 0 Register changes from '1' to '0'. - If this bit is set to '1', both the BFINI bits of the Host Endpoint 1 Control Register (HOST_EP1_CTL) and Host Endpoint 2 Control Register (HOST_EP2_CTL) are set to '1'. [7:7] read-write HOST_CTL2 Host Control 2 Register. 0x100 32 read-write 0x1 0xFF RETRY If this bit is set to '1', the target token is retried if a NAK or error* occurs. Retry processing is performed during the time that is specified in the Host Retry Timer Setup Register (HOST_RTIMER). * : HOST_ERR.RERR='1', HOST_ERR.TOUT='1', HOST_ERR.CRC='1', HOST_ERR.TGERR='1', HOST_ERR.STUFF='1' '0' : Doesn't retry token sending. '1' : Retries token sending Note: - This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [0:0] read-write CANCEL When this bit is set to '1', if the target token is written to the Host Token Endpoint Register (HOST_TOKEN) in the EOF area (specified in the Host EOF Setup Register), its sending is canceled. When this bit is set to '0', token sending is not canceled even if the target token is written to the register. The cancellation of token sending is detected by reading the TCAN bit of the Interrupt USB Host Register (INTR_USBHOST). '0' : Continues a token. '1' : Cancels a token. [1:1] read-write SOFSTEP If this bit is set to '1', the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1' each time SOF is sent. If this bit is set to '0', the set value of the Host SOF Interrupt Frame Compare Register (HOST_FCOMP) is compared with the low-order eight bits of the SOF frame number. If they match, the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1'. '0' : An interrupt occurred due to the HOST_HFCOMP setting. '1' : An interrupt occurred. Notes: - If a SOF token (TKNEN='001') is sent by the setting of the Host Token Endpoint Register (HOST_TOKEN), the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is not set to '1' regardless of the setting of this bit. [2:2] read-write ALIVE This bit is used to specify the keep-alive function in the low-speed mode. If this bit it set to '1' while the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is '0', SE0 is output instead of SOF. This bit is effective when the CLKSEL bit of the Host Conrtol 1 Register (HOST_CTL1) is '0'. If the CLKSEL bit is '1', SOF is output regardless of the setting of the ALIVE bit. '0' : SOF output. '1' : SE0 output (Keep alive) [3:3] read-write RSVD_4 N/A [4:4] read-write RSVD_5 N/A [5:5] read-write TTEST Timer Test. Set this bits to '00'. [7:6] read-write HOST_ERR Host Error Status Register. 0x104 32 read-write 0x3 0xFF HS These flags indicate the status of a handshake packet to be sent or received. These flags are set to 'NULL' when no handshake occurs due to an error or when a SOF token has been ended with the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). These bits are updated when sending or receiving has been ended. HS bits change values '11' under the following condition. However, if HS bits are written except the following conditions, the values are ignored. - HS bits indicate values except '11' and write the value '11' to HS bits. Note: This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [1:0] read-write ACK Acknowledge Packet 0 NAK Non-Acknowledge Packet 1 STALL Stall Packet 2 NULL Null Packet 3 STUFF If this bit is set to '1', it means that a bit stuffing error is detected. When this bit is '0', it means that no stuffing error is detected. If a stuffing error is detected, bit5 (Timeout) of this register is also set to '1'. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : No stuffing error. '1' : Stuffing error occurs. Note: - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [2:2] read-write TGERR If this bit is set to '1', it means that the data of this bit does not match the value of the received toggle data. When this bit is '0', it means that no toggle error is detected. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : No toggle error. '1' : Toggle error occurs. Note: - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [3:3] read-write CRC If this bit is set to '1', it means that a CRC error is detected in the USB Host. When this bit is '0', it means that no CRC error is detected. If a CRC error is detected, bit5 (Timeout) of this register is also set to '1'. When this bit is '0', it means that no CRC error is detected. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : No CRC error. '1' : CRC error occurs. Note: - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [4:4] read-write TOUT If this bit is set to '1', it means that no response is returned from the device within the specified time after a token has been sent in the USB Host. When this bit is '0', it means that no timeout is detected. When this bit is '0', it means that no error occurs. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : No timeout. '1' : Timeout occurs. Note: - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [5:5] read-write RERR When this bit is set to '1', it means that the received data exceeds the specified maximum number of packets in the USB Host. If a receive error is detected, bit5 (Timeout) of this register is also set to '1'. When this bit is '0', it means that no error occurs. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : No receive error. '1' : Maximum packet receive error. - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [6:6] read-write LSTSOF If this bit is set to '1', it means that the SOF token can't be sent in the USB Host because other token is in process. When this bit is '0', it means that no lost SOF error is detected. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : Sends SOF. '1' : SOF sending error. Note: - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [7:7] read-write HOST_STATUS Host Status Register. 0x108 32 read-write 0xC2 0x1FF CSTAT When this bit is '1', it means that the device is connected. When this bit is '0', it means that the device is disconnected. '0' : Device is disconnected. '1' : Device is connected. Notes: - This bit is initialized if the RST bit of the Host Control 1 Register (Host_CTL1) is set to '1'. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). [0:0] read-only TMODE If this bit is '1', it means that the device is connected in the full-speed mode. When this bit is '0', it means that the device is connected in the low-speed mode. This bit is valid when the CSTAT bit of the Host Status Register (HOST_STATUS) is '1'. '0' : Low-speed. '1' : Full-speed. Notes: - This bit is initialized if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). [1:1] read-only SUSP If this bit is set to '1', the USB Host is placed into the suspend state. If this bit is set to '0' while it is '1' or the USB bus is placed into the k-state mode, the suspend state is released, and the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. Set to '1' : Suspend. Set '0' while this bit is '1' : Resume. Others : Holds the status. Notes: - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). - If this bit is set to '1', this bit must not be set to '1' until the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. - Do not set this bit to '1' while the USB is active (during USB bus resetting, data transfer, or SOF timer running). - If the value of this bit is changed, it is not immediately reflected on the state of the USB bus. To check whether or not the state is updated, read this bit. [2:2] read-write SOFBUSY When a SOF token is sent using the Host Token Endpoint Register (HOST_TOKEN), this bit is set to '1', which means that the SOF timer is active. When this bit is '0', it means that the SOF timer is under suspension. To stop the active SOF timer, write '0' to this bit. However, if this bit is written with '1', its value is ignored. '0' : The SOF timer is stopped. '1' : The SOF timer is active. Notes: - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). - The SOF timer does not stop immediately after this bit has been set to '0' to stop the SOF timer. To check whether or not the SOF timer is stopped, read this bit. [3:3] read-write URST When this bit is set to '1', the USB bus is reset. This bit continues set to '1' during USB bus resetting, and changes to '0' when USB bus resetting is ended. If this bit is set to '0', no processing is performed. [4:4] read-write RSVD_5 N/A [5:5] read-only RSTBUSY This bit shows that USB Host is being reset internally. If the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. If the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0', this bit is set to '0'. '0' : USB Host isn't being reset. '1' : USB Host is being reset. Notes: - If this bit is '1', the token must't be executed. - This bit isn't set to '0' or '1' immediately evne if the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0' or '1'. [6:6] read-only CLKSEL_ST This bit shows whether it is full-speed or not. If the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. '0' : Low speed '1' : Full speed Note: - If this bit is different from the CLKSEL bit, The execution of the token and bus reset must be waited until the match. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). [7:7] read-only HOST_ST This bit shows whether it is USB Host mode. If the HOST bit of the Host Control Register (HOST_CTL0) is set to '1', this bit is set to '1'. '0' : USB Device '1' : USB Host Notes: - If this bit is different from the CLKSEL bit, The execution of the token must be waited until the match. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). [8:8] read-only HOST_FCOMP Host SOF Interrupt Frame Compare Register 0x10C 32 read-write 0x0 0xFF FRAMECOMP These bits are used to specify the data to be compared with the low-order eight bits of a frame number when sending a SOF token. If the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '0', the frame number of SOF is compared with the value of this register when sending a SOF token. If they match, the SOFIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. The setting of this register is invalid when the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '1'. Note: - This bit is not initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [7:0] read-write HOST_RTIMER Host Retry Timer Setup Register 0x110 32 read-write 0x0 0x3FFFF RTIMER These bits are used to specify the retry time in this register. The retry timer is activated when token sending starts while the RETRY bit of Host Control 2 Register (HOST_CTL2) is '1'. The retry time is then decremented by one when a 1-bit transfer clock (12 MHz in the full-speed mode) is output. When the retry timer reaches 0, the target token is sent, and processing is ended. If a token retry occurs in the EOF area, the retry timer is stopped until SOF sending is ended. After SOF sending has been completed, the retry timer restarts with the value that is set when the timer stopped. [17:0] read-write HOST_ADDR Host Address Register 0x114 32 read-write 0x0 0x7F ADDRESS These bits are used to specify a token address. Note: - This bit is not initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [6:0] read-write HOST_EOF Host EOF Setup Register 0x118 32 read-write 0x0 0x3FFF EOF These bits are used to specify the time to disable token sending before transferring SOF. Specify the time with a margin, which is longer than the one-packet length. The time unit is the 1-bit transfer time. Setting example: MAXPKT = 64 bytes, full-speed mode (Token_length + packet_length + header + CRC)*7/6 + Turn_around_time =(34 bit + 546 bit)*7/6 + 36 bit = 712.7 bit Therefore, set 0x2C9. Note: - This bit is not initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [13:0] read-write HOST_FRAME Host Frame Setup Register 0x11C 32 read-write 0x0 0x7FF FRAME These bits are used to specify a frame number of SOF. Notes: - This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - Specify a frame number in this register before setting SOF in the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). - This register cannot be written while the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' and a SOF token is in process. [10:0] read-write HOST_TOKEN Host Token Endpoint Register 0x120 32 read-write 0x0 0x17F ENDPT These bits are used to specify an endpoint to send or receive data to or from the device. Note: - This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [3:0] read-write TKNEN These bits send a token according to the settings. After operation has been ended, the TKNEN bit is set to '000', and the CMPIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. The settings of the TGGL and ENDPT bits are ignored when sending a SOF token. Notes: - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - The PRE packet isn't supported. - Do not set '100' to the TKNEN bit when the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' - Change the USB to the USB Host before writing data to this bit. - When issuing a token again after the token interrupt flag (CMPIRQ) has been set to '1', wait for 3 cycles or more after a USB transfer clock (12 MHz in the full-speed mode, 1.5 MHz in the low-speed mode) was output, then write data to this bit. - Read the value of TKNEN bit if a new value is written in it .Continue writing in this bit until a retrieved value equals a new value written in. During this checking process, it is needed to prevent any interrupt. - Take the following steps when CMPIRQ bit of Interrupt USB Host Register (INTR_USBHOST) is set to '1' by finishing IN token or Isochronous IN token. 1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. 2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. 3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'. [6:4] read-write NONE Sends no data. 0 SETUP Sends SETUP token. 1 IN Sends IN token. 2 OUT Sends OUT token. 3 SOF Sends SOF token. 4 ISO_IN Sends Isochronous IN. 5 ISO_OUT Sends Isochronous OUT. 6 RSV N/A 7 TGGL This bit is used to set toggle data. Toggle data is sent depending on the setting of this bit. When receiving toggle data, received toggle data is compared with the toggle data of this bit to verify whether or not an error occurs. '0' : DATA0 '1' : DATA1 Notes: - This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - Set this bit when the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN) is '000'. [8:8] read-write HOST_EP1_CTL Host Endpoint 1 Control Register 0x400 32 read-write 0x8100 0x9DFF PKS1 This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x100. - If automatic buffer transfer mode (DMEA='1') is used, this Endpoint must not set from 0 to 2. [8:0] read-write NULLE When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. '0' : Releases the NULL automatic transfer mode. '1' : Sets the NULL automatic transfer mode. Note : - For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication. [10:10] read-write DMAE This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. '0' : Releases the automatic buffer transfer mode. '1' : Sets the automatic buffer transfer mode. Note : - The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR). [11:11] read-write DIR This bit specifies the transfer direction the Endpoint support. '0' : IN Endpoint. '1' : OUT Endpoint Note: - This bit must be changed when INI_ST bit of the Host Endpoint 1 Status Register (HOST_EP1_STATUS) is '1'. [12:12] read-write BFINI This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit. '0' : Clears the initialization. '1' : Initializes the send/receive buffer Note : - The EP1 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP1DRQ and EP1SPK bits. [15:15] read-write HOST_EP1_STATUS Host Endpoint 1 Status Register 0x404 32 read-only 0x60000 0x70000 SIZE1 These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP1 has finished. The indication range is from 0x000 to 0x100. Note : - These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect. [8:0] read-only VAL_DATA This bit shows that there is valid data in the EP1 buffer. '0' : Invalid data in the buffer '1' : Valid data in the buffer [16:16] read-only INI_ST This bit shows that EP1 is initialized. If the init bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' and EP1 is initialized, this bit is to '1'. '0' : Release of the initialization '1' : Initialization Note: - This bit isn't set to '0' or '1' immediately evne if BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '0' or '1'. [17:17] read-only RSVD_18 N/A [18:18] read-only HOST_EP1_RW1_DR Host Endpoint 1 Data 1-Byte Register 0x408 32 read-write 0x0 0xFF BFDT8 Data Register for EP1. The 1-Byte data is valid. [7:0] read-write HOST_EP1_RW2_DR Host Endpoint 1 Data 2-Byte Register 0x40C 32 read-write 0x0 0xFFFF BFDT16 Data Register for EP1. The 2-Byte data is valid. [15:0] read-write HOST_EP2_CTL Host Endpoint 2 Control Register 0x500 32 read-write 0x8040 0x9C7F PKS2 This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x40. - If automatic buffer transfer mode (DMEA='1') is used, this Endpoint must not set from 0 to 2. [6:0] read-write NULLE When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. '0' : Releases the NULL automatic transfer mode. '1' : Sets the NULL automatic transfer mode. Note : - For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication. [10:10] read-write DMAE This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. '0' : Releases the automatic buffer transfer mode. '1' : Sets the automatic buffer transfer mode. Note : - The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR). [11:11] read-write DIR This bit specifies the transfer direction the Endpoint support. '0' : IN Endpoint. '1' : OUT Endpoint Note: - This bit must be changed when INI_ST bit of the Host Endpoint 2 Status Register (HOST_EP2_STATUS) is '1'. [12:12] read-write BFINI This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit. '0' : Clears the initialization. '1' : Initializes the send/receive buffer Note : - The EP2 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP2DRQ and EP2SPK bits. [15:15] read-write HOST_EP2_STATUS Host Endpoint 2 Status Register 0x504 32 read-only 0x60000 0x70000 SIZE2 These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP2 has finished. The indication range is from 0x000 to 0x40. Note : - These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect. [6:0] read-only VAL_DATA This bit shows that there is valid data in the EP2 buffer. '0' : Invalid data in the buffer '1' : Valid data in the buffer [16:16] read-only INI_ST This bit shows that EP2 is initialized. If the BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' and EP2 is initialized, this bit is to '1'. '0' : Release of the initialization '1' : Initialization Note: - This bit isn't set to '0' or '1' immediately evne if BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '0' or '1'. [17:17] read-only RSVD_18 N/A [18:18] read-only HOST_EP2_RW1_DR Host Endpoint 2 Data 1-Byte Register 0x508 32 read-write 0x0 0xFF BFDT8 Data Register for EP2. The 1-Byte data is valid. [7:0] read-write HOST_EP2_RW2_DR Host Endpoint 2 Data 2-Byte Register 0x50C 32 read-write 0x0 0xFFFF BFDT16 Data Register for EP2. The 2-Byte data is valid. [15:0] read-write HOST_LVL1_SEL Host Interrupt Level 1 Selection Register 0x800 32 read-write 0x0 0xFFFF SOFIRQ_SEL These bits assign SOFIRQ interrupt flag to any interrupt signals. [1:0] read-write HI High priority interrupt 0 MED Medium priority interrupt 1 LO Low priority interrupt 2 RSVD illegal 3 DIRQ_SEL These bits assign DIRQ interrupt flag to any interrupt signals. [3:2] read-write CNNIRQ_SEL These bits assign CNNIRQ interrupt flag to any interrupt signals. [5:4] read-write CMPIRQ_SEL These bits assign URIRQ interrupt flag to any interrupt signals. [7:6] read-write URIRQ_SEL These bits assign URIRQ interrupt flag to any interrupt signals. [9:8] read-write RWKIRQ_SEL These bits assign RWKIRQ interrupt flag to any interrupt signals. [11:10] read-write RSVD_13_12 N/A [13:12] read-write TCAN_SEL These bits assign TCAN interrupt flag to any interrupt signals. [15:14] read-write HOST_LVL2_SEL Host Interrupt Level 2 Selection Register 0x804 32 read-write 0x0 0xFF0 EP1_DRQ_SEL These bits assign EP1_DRQ interrupt flag to any interrupt signals. [5:4] read-write HI High priority interrupt 0 MED Medium priority interrupt 1 LO Low priority interrupt 2 RSVD illegal 3 EP1_SPK_SEL These bits assign EP1_SPK interrupt flag to any interrupt signals. [7:6] read-write EP2_DRQ_SEL These bits assign EP2_DRQ interrupt flag to any interrupt signals. [9:8] read-write EP2_SPK_SEL These bits assign EP2_SPK interrupt flag to any interrupt signals. [11:10] read-write INTR_USBHOST_CAUSE_HI Interrupt USB Host Cause High Register 0x900 32 read-only 0x0 0xFF SOFIRQ_INT SOFIRQ interrupt [0:0] read-only DIRQ_INT DIRQ interrupt [1:1] read-only CNNIRQ_INT CNNIRQ interrupt [2:2] read-only CMPIRQ_INT CMPIRQ interrupt [3:3] read-only URIRQ_INT URIRQ interrupt [4:4] read-only RWKIRQ_INT RWKIRQ interrupt [5:5] read-only RSVD_6 N/A [6:6] read-only TCAN_INT TCAN interrupt [7:7] read-only INTR_USBHOST_CAUSE_MED Interrupt USB Host Cause Medium Register 0x904 32 read-only 0x0 0xFF SOFIRQ_INT SOFIRQ interrupt [0:0] read-only DIRQ_INT DIRQ interrupt [1:1] read-only CNNIRQ_INT CNNIRQ interrupt [2:2] read-only CMPIRQ_INT CMPIRQ interrupt [3:3] read-only URIRQ_INT URIRQ interrupt [4:4] read-only RWKIRQ_INT RWKIRQ interrupt [5:5] read-only RSVD_6 N/A [6:6] read-only TCAN_INT TCAN interrupt [7:7] read-only INTR_USBHOST_CAUSE_LO Interrupt USB Host Cause Low Register 0x908 32 read-only 0x0 0xFF SOFIRQ_INT SOFIRQ interrupt [0:0] read-only DIRQ_INT DIRQ interrupt [1:1] read-only CNNIRQ_INT CNNIRQ interrupt [2:2] read-only CMPIRQ_INT CMPIRQ interrupt [3:3] read-only URIRQ_INT URIRQ interrupt [4:4] read-only RWKIRQ_INT RWKIRQ interrupt [5:5] read-only RSVD_6 N/A [6:6] read-only TCAN_INT TCAN interrupt [7:7] read-only INTR_HOST_EP_CAUSE_HI Interrupt USB Host Endpoint Cause High Register 0x920 32 read-only 0x0 0x3C EP1DRQ_INT EP1DRQ interrupt [2:2] read-only EP1SPK_INT EP1SPK interrupt [3:3] read-only EP2DRQ_INT EP2DRQ interrupt [4:4] read-only EP2SPK_INT EP2SPK interrupt [5:5] read-only INTR_HOST_EP_CAUSE_MED Interrupt USB Host Endpoint Cause Medium Register 0x924 32 read-only 0x0 0x3C EP1DRQ_INT EP1DRQ interrupt [2:2] read-only EP1SPK_INT EP1SPK interrupt [3:3] read-only EP2DRQ_INT EP2DRQ interrupt [4:4] read-only EP2SPK_INT EP2SPK interrupt [5:5] read-only INTR_HOST_EP_CAUSE_LO Interrupt USB Host Endpoint Cause Low Register 0x928 32 read-only 0x0 0x3C EP1DRQ_INT EP1DRQ interrupt [2:2] read-only EP1SPK_INT EP1SPK interrupt [3:3] read-only EP2DRQ_INT EP2DRQ interrupt [4:4] read-only EP2SPK_INT EP2SPK interrupt [5:5] read-only INTR_USBHOST Interrupt USB Host Register 0x940 32 read-write 0x0 0xFF SOFIRQ If this bit is set to '1', it means that SOF token sending is started. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : Does not issue an interrupt request by starting a SOF token. '1' : Issues an interrupt request by starting a SOF token. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [0:0] read-write DIRQ If this bit is set to '1', it means that a device disconnection is detected. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : Issues no interrupt request by detecting a device disconnection. '1' : Issues an interrupt request by detecting a device disconnection. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [1:1] read-write CNNIRQ If this bit is set to '1', it means that a device connection is detected. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : Issues no interrupt request by detecting a device connection. '1' : Issues an interrupt request by detecting a device connection. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [2:2] read-write CMPIRQ If this bit is set to '1', it means that a token is completed. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : Issues no interrupt request by token completion. '1' : Issues an interrupt request by token completion. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - This bit is not set to '1' even if the TCAN bit of the Interrupt USBHost Register (INTR_USBHOST) changes to '1'. - Take the following steps when this bit is set to '1' by finishing IN token or Isochronous IN token. 1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. 2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. 3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'. [3:3] read-write URIRQ If this bit is set to '1', it means that USB bus resetting is ended. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : Issues no interrupt request by USB bus resetting. '1' : Issues an interrupt request by USB bus resetting. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [4:4] read-write RWKIRQ If this bit is set to '1', it means that remote Wake-up is ended. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : Issues no interrupt request by restart. '1' : Issues an interrupt request by restart. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [5:5] read-write RSVD_6 N/A [6:6] read-write TCAN If this bit is set to '1', it means that token sending is canceled based on the setting of the CANCEL bit of Host Control 2 Register (HOST_CTL2). When this bit is '0', it means that token sending is not canceled. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : Does not cancel token sending. '1' : Cancels token sending. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [7:7] read-write INTR_USBHOST_SET Interrupt USB Host Set Register 0x944 32 read-write 0x0 0xFF SOFIRQS This bit sets SOFIRQ bit. If this bit is written to '1', SOFIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. [0:0] read-write DIRQS This bit sets DIRQ bit. If this bit is written to '1', DIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. [1:1] read-write CNNIRQS This bit sets CNNIRQ bit. If this bit is written to '1', CNNIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. [2:2] read-write CMPIRQS This bit sets CMPIRQ bit. If this bit is written to '1', CMPIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. [3:3] read-write URIRQS This bit sets URIRQ bit. If this bit is written to '1', URIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. [4:4] read-write RWKIRQS This bit sets RWKIRQ bit. If this bit is written to '1', RWKIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. [5:5] read-write RSVD_6 BCNFTEST interrupt. This bit is test bit [6:6] read-write TCANS This bit sets TCAN bit. If this bit is written to '1', TCAN is set to '1'. However, if this bit is written with '0', its value is ignored. [7:7] read-write INTR_USBHOST_MASK Interrupt USB Host Mask Register 0x948 32 read-write 0x0 0xFF SOFIRQM This bit masks the interrupt by SOF flag. '0' : Disables '1' : Enables [0:0] read-write DIRQM This bit masks the interrupt by DIRQ flag. '0' : Disables '1' : Enables [1:1] read-write CNNIRQM This bit masks the interrupt by CNNIRQ flag. '0' : Disables '1' : Enables [2:2] read-write CMPIRQM This bit masks the interrupt by CMPIRQ flag. '0' : Disables '1' : Enables [3:3] read-write URIRQM This bit masks the interrupt by URIRQ flag. '0' : Disables '1' : Enables [4:4] read-write RWKIRQM This bit masks the interrupt by RWKIRQ flag. '0' : Disables '1' : Enables [5:5] read-write RSVD_6 N/A [6:6] read-write TCANM This bit masks the interrupt by TCAN flag. '0' : Disables '1' : Enables [7:7] read-write INTR_USBHOST_MASKED Interrupt USB Host Masked Register 0x94C 32 read-only 0x0 0xFF SOFIRQED This bit indicates the interrupt by SOF flag. '0' : Doesn't request the interrupt by SOF '1' : Request the interrupt by SOF [0:0] read-only DIRQED This bit indicates the interrupt by DIRQ flag. '0' : Doesn't request the interrupt by DIRQ '1' : Request the interrupt by DIRQ [1:1] read-only CNNIRQED This bit indicates the interrupt by CNNIRQ flag. '0' : Doesn't request the interrupt by CNNIRQ '1' : Request the interrupt by CNNIRQ [2:2] read-only CMPIRQED This bit indicates the interrupt by CMPIRQ flag. '0' : Doesn't request the interrupt by CMPIRQ '1' : Request the interrupt by CMPIRQ [3:3] read-only URIRQED This bit indicates the interrupt by URIRQ flag. '0' : Doesn't request the interrupt by URIRQ '1' : Request the interrupt by URIRQ [4:4] read-only RWKIRQED This bit indicates the interrupt by RWKIRQ flag. '0' : Doesn't request the interrupt by RWKIRQ '1' : Request the interrupt by RWKIRQ [5:5] read-only RSVD_6 N/A [6:6] read-only TCANED This bit indicates the interrupt by TCAN flag. '0' : Doesn't request the interrupt by TCAN '1' : Request the interrupt by TCAN [7:7] read-only INTR_HOST_EP Interrupt USB Host Endpoint Register 0xA00 32 read-write 0x0 0x3C EP1DRQ This bit indicates that the EP1 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. '0' : Clears the interrupt cause '1' : Packet transfer normally ended Note : - If automatic buffer transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written. [2:2] read-write EP1SPK This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS in the Host Endpoint 1 Control Register (HOST_EP1_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. '0' : Received data size satisfies the maximum packet size '1' : Received data size does not satisfy the maximum packet size Note : - The SPK bit is not set during data transfer in the OUT direction. [3:3] read-write EP2DRQ This bit indicates that the EP2 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. '0' : Clears the interrupt cause '1' : Packet transfer normally ended Note : - If automatic buffer transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written. [4:4] read-write EP2SPK This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS in the Host Endpoint 2 Control Register (HOST_EP2_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. '0' : Received data size satisfies the maximum packet size '1' : Received data size does not satisfy the maximum packet size Note : - The SPK bit is not set during data transfer in the OUT direction. [5:5] read-write INTR_HOST_EP_SET Interrupt USB Host Endpoint Set Register 0xA04 32 read-write 0x0 0x3C EP1DRQS This bit sets EP1DRQ bit. If this bit is written to '1', EP1DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1DRQ can't be set to '1'. [2:2] read-write EP1SPKS This bit sets EP1SPK bit. If this bit is written to '1', EP1SPK is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1SPK can't be set to '1'. [3:3] read-write EP2DRQS This bit sets EP2DRQ bit. If this bit is written to '1', EP2DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2DRQ can't be set to '1'. [4:4] read-write EP2SPKS This bit sets EP2SPK bit. If this bit is written to '1', EP2SPK is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2SPK can't be set to '1'. [5:5] read-write INTR_HOST_EP_MASK Interrupt USB Host Endpoint Mask Register 0xA08 32 read-write 0x0 0x3C EP1DRQM This bit masks the interrupt by EP1DRQ flag. '0' : Disables '1' : Enables [2:2] read-write EP1SPKM This bit masks the interrupt by EP1SPK flag. '0' : Disables '1' : Enables [3:3] read-write EP2DRQM This bit masks the interrupt by EP2DRQ flag. '0' : Disables '1' : Enables [4:4] read-write EP2SPKM This bit masks the interrupt by EP2SPK flag. '0' : Disables '1' : Enables [5:5] read-write INTR_HOST_EP_MASKED Interrupt USB Host Endpoint Masked Register 0xA0C 32 read-only 0x0 0x3C EP1DRQED This bit indicates the interrupt by EP1DRQ flag. '0' : Doesn't request the interrupt by EP1DRQ '1' : Request the interrupt by EP1DRQ [2:2] read-only EP1SPKED This bit indicates the interrupt by EP1SPK flag. '0' : Doesn't request the interrupt by EP1SPK '1' : Request the interrupt by EP1SPK [3:3] read-only EP2DRQED This bit indicates the interrupt by EP2DRQ flag. '0' : Doesn't request the interrupt by EP2DRQ '1' : Request the interrupt by EP2DRQ [4:4] read-only EP2SPKED This bit indicates the interrupt by EP2SPK flag. '0' : Doesn't request the interrupt by EP2SPK '1' : Request the interrupt by EP2SPK [5:5] read-only HOST_DMA_ENBL Host DMA Enable Register 0xB00 32 read-write 0x0 0xC DM_EP1DRQE This bit enables DMA Request by EP1DRQ. '0' : Disable '1' : Enable [2:2] read-write DM_EP2DRQE This bit enables DMA Request by EP2DRQ. '0' : Disable '1' : Enable [3:3] read-write HOST_EP1_BLK Host Endpoint 1 Block Register 0xB20 32 read-write 0x0 0xFFFF0000 BLK_NUM Set the total byte number for DMA transfer. If HOST_EP1_RW1_DR or HOST_EP1_RW2_DR is written, the block number counter is decrement when DMAE='1'. - Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP1DRQE='1') [31:16] read-write HOST_EP2_BLK Host Endpoint 2 Block Register 0xB30 32 read-write 0x0 0xFFFF0000 BLK_NUM Set the total byte number for DMA transfer. If HOST_EP2_RW1_DR or HOST_EP2_RW2_DR is written, the block number counter is decrement when DMAE='1'. - Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP2DRQE='1') [31:16] read-write SMIF0 Serial Memory Interface SMIF 0x40420000 0 65536 registers CTL Control 0x0 32 read-write 0x3000 0x81073001 XIP_MODE Mode of operation. Note: this field should only be changed when the IP is disabled or when STATUS.BUSY is '0' and SW should not be executing from the XIP interface or MMIO interface. [0:0] read-write MMIO_MODE '0': MMIO mode. Individual MMIO accesses to TX and RX FIFOs are used to generate a sequence of SPI transfers. This mode of operation allows for large flexibility in terms of the SPI transfers that can be generated. 0 XIP_MODE 1': XIP mode. eXecute-In-Place mode: incoming read and write transfers over the AHB-Lite bus infrastructure are automatically translated in SPI transfers to read data from and write data to a device. This mode of operation allow for efficient device read and write operations. This mode is only supported in SPI_MODE. 1 CLOCK_IF_RX_SEL Specifies device interface receiver clock 'clk_if_rx' source. MISO data is captured on the rising edge of 'clk_if_rx'. '0': 'spi_clk_out' (internal clock) '1': !'spi_clk_out' (internal clock) '2': 'spi_clk_in' (feedback clock) '3': !'spi_clk_in' (feedback clock) Note: the device interface transmitter clock 'clk_if_tx' is fixed and is 'spi_clk_out' MOSI data is driven on the falling edge of 'clk_if_tx'. [13:12] read-write DESELECT_DELAY Specifies the minimum duration of SPI deselection ('spi_select_out[]' is high/'1') in between SPI transfers: '0': 1 interface clock cycle. '1': 2 interface clock cycles. '2': 3 interface clock cycles. '3': 4 interface clock cycles. '4': 5 interface clock cycles. '5': 6 interface clock cycles. '6': 7 interface clock cycles. '7': 8 interface clock cycles. During SPI deselection, 'spi_select_out[]' are '1'/inactive, 'spi_data_out[]' are '1' and 'spi_clk_out' is '0'/inactive. [18:16] read-write BLOCK Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO. Note: the FIFOs can only be accessed in MMIO_MODE. This field is not used for test controller accesses. [24:24] read-write BUS_ERROR 0': Generate an AHB-Lite bus error. This option is useful when SW decides to use polling on STATUS.TR_BUSY to determine if a interface transfer is no longer busy (transfer is completed). This option adds SW complexity, but limits the number of AHB-Lite wait states (and limits ISR latency). 0 WAIT_STATES 1': Introduce wait states. This setting potentially locks up the AHB-Lite infrastructure and may increase the CPU interrupt latency.This option is useful when SW performs TX/RX data FIFO accesses immediately after a command is setup using the TX format FIFO. This option has low SW complexity, but may result in a significant number of AHB-Lite wait states (and may increase ISR latency). 1 ENABLED IP enable: '0': Disabled. All non-retention registers are reset to their default value when the IP is disabled. When the IP is disabled, the XIP accesses produce AHB-Lite bus errors. '1': Enabled. Note: Before disabling the IP, SW should ensure that the IP is NOT busy (STATUS.BUSY is '0'), otherwise illegal interface transfers may occur. [31:31] read-write DISABLED N/A 0 ENABLED N/A 1 STATUS Status 0x4 32 read-only 0x0 0x80000000 BUSY Cache, cryptography, XIP, device interface or any other logic busy in the IP: '0': not busy '1': busy When BUSY is '0', the IP can be safely disabled without: - the potential loss of transient write data. - the potential risk of aborting an inflight SPI device interface transfer. When BUSY is '0', the mode of operation (XIP_MODE or MMIO_MODE) can be safely changed. [31:31] read-only TX_CMD_FIFO_STATUS Transmitter command FIFO status 0x44 32 read-only 0x0 0x7 USED3 Number of entries that are used in the TX command FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 4]. [2:0] read-only TX_CMD_FIFO_WR Transmitter command FIFO write 0x50 32 write-only 0x0 0xFFFFF DATA20 Command data. The higher two bits DATA[19:18] specify the specific command '0'/TX: A SPI transfer always start with a TX command FIFO entry of the 'TX' format. - DATA[17:16] specifies the width of the data transfer: - '0': 1 bit/cycle (single data transfer). - '1': 2 bits/cycle (dual data transfer). - '2': 4 bits/cycle (quad data transfer). - '3': 8 bits/cycle (octal data transfer). - DATA[15]: specifies whether this is the last TX Byte; i.e. whether the 'spi_select_out[3:0]' IO output signals are de-activated after the transfer. - DATA[11:8] specifies which of the four devices are selected. DATA[11:8] are directly mapped to 'spi_select_out[3:0]'. Two devices can be selected at the same time in dual-quad mode. - '0': device deselected - '1': device selected - DATA[7:0] specifies the transmitted Byte. '1'/TX_COUNT: The 'TX_COUNT' command relies on the TX data FIFO to provide the transmitted bytes. The 'TX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers. - DATA[17:16] specifies the width of the transfer. - DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) from the TX data FIFO. '2'/RX_COUNT: The 'RX_COUNT' command relies on the RX data FIFO to accept the received bytes. The 'RX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers. - DATA[17:16] specifies the width of the transfer. - DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) to the RX data FIFO. '3'/DUMMY_COUNT: The 'DUMMY_COUNT' command conveys dummy cycles. Dummy cycles are used to implement a Turn-Around time in which the SPI master changes from a transmitter driving the data lines to a receiver receiving on the same data lines. The 'DUMMY_COUNT' command is ALWAYS considered to be NOT the last command of a SPI data transfers; i.e. it needs to be followed by another command. - DATA[15:0] specifies the number of dummy cycles (minus 1). In dummy cycles, the data lines are not driven. [19:0] write-only TX_DATA_FIFO_CTL Transmitter data FIFO control 0x80 32 read-write 0x0 0x7 TRIGGER_LEVEL Determines when the TX data FIFO 'tr_tx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): - Trigger is active when TX_DATA_FIFO_STATUS.USED <= TRIGGER_LEVEL. [2:0] read-write TX_DATA_FIFO_STATUS Transmitter data FIFO status 0x84 32 read-only 0x0 0xF USED4 Number of entries that are used in the TX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. [3:0] read-only TX_DATA_FIFO_WR1 Transmitter data FIFO write 0x90 32 write-only 0x0 0xFF DATA0 TX data (written to TX data FIFO). [7:0] write-only TX_DATA_FIFO_WR2 Transmitter data FIFO write 0x94 32 write-only 0x0 0xFFFF DATA0 TX data (written to TX data FIFO, first byte). [7:0] write-only DATA1 TX data (written to TX data FIFO, second byte). [15:8] write-only TX_DATA_FIFO_WR4 Transmitter data FIFO write 0x98 32 write-only 0x0 0xFFFFFFFF DATA0 TX data (written to TX data FIFO, first byte). [7:0] write-only DATA1 TX data (written to TX data FIFO, second byte). [15:8] write-only DATA2 TX data (written to TX data FIFO, third byte). [23:16] write-only DATA3 TX data (written to TX data FIFO, fourth byte). [31:24] write-only RX_DATA_FIFO_CTL Receiver data FIFO control 0xC0 32 read-write 0x0 0x7 TRIGGER_LEVEL Determines when RX data FIFI 'tr_rx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): - Trigger is active when RX_DATA_FIFO_STATUS.USED > TRIGGER_LEVEL. [2:0] read-write RX_DATA_FIFO_STATUS Receiver data FIFO status 0xC4 32 read-only 0x0 0xF USED4 Number of entries that are used in the RX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. [3:0] read-only RX_DATA_FIFO_RD1 Receiver data FIFO read 0xD0 32 read-only 0x0 0xFF DATA0 RX data (read from RX data FIFO). [7:0] read-only RX_DATA_FIFO_RD2 Receiver data FIFO read 0xD4 32 read-only 0x0 0xFFFF DATA0 RX data (read from RX data FIFO, first byte). [7:0] read-only DATA1 RX data (read from RX data FIFO, second byte). [15:8] read-only RX_DATA_FIFO_RD4 Receiver data FIFO read 0xD8 32 read-only 0x0 0xFFFFFFFF DATA0 RX data (read from RX data FIFO, first byte). [7:0] read-only DATA1 RX data (read from RX data FIFO, second byte). [15:8] read-only DATA2 RX data (read from RX data FIFO, third byte). [23:16] read-only DATA3 RX data (read from RX data FIFO, fourth byte). [31:24] read-only RX_DATA_FIFO_RD1_SILENT Receiver data FIFO silent read 0xE0 32 read-only 0x0 0xFF DATA0 RX data (read from RX data FIFO). [7:0] read-only SLOW_CA_CTL Slow cache control 0x100 32 read-write 0xC0000000 0xC3030000 WAY this is for debug purpose only, and should be hidden to customers in technical document [17:16] read-write SET_ADDR this is for debug purpose only, and should be hidden to customers in technical document [25:24] read-write PREF_EN N/A [30:30] read-write ENABLED N/A [31:31] read-write SLOW_CA_CMD Slow cache command 0x108 32 read-write 0x0 0x1 INV Cache invalidation. SW writes a '1' to clear the cache. The cache's LRU structure is also reset to its default state. [0:0] read-write FAST_CA_CTL Fast cache control 0x180 32 read-write 0xC0000000 0xC3030000 WAY this is for debug purpose only, and should be hidden to customers in technical document [17:16] read-write SET_ADDR this is for debug purpose only, and should be hidden to customers in technical document [25:24] read-write PREF_EN N/A [30:30] read-write ENABLED N/A [31:31] read-write FAST_CA_CMD Fast cache command 0x188 32 read-write 0x0 0x1 INV See SLOW_CA_CMD.INV. [0:0] read-write CRYPTO_CMD Cryptography Command 0x200 32 read-write 0x0 0x1 START SW sets this field to '1' to start a AES-128 forward block cipher operation (on the address in CRYPTO_ADDR). HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRYPTO_RESULT0, ..., CRYPTO_RESULT3. The operation takes roughly 13 clk_hf clock cycles. Note: An operation can only be started in MMIO_MODE. [0:0] read-write CRYPTO_INPUT0 Cryptography input 0 0x220 32 read-write 0x0 0x0 INPUT Four Bytes of the plaintext PT[31:0] = CRYPTO_INPUT0.INPUT[31:0]. [31:0] read-write CRYPTO_INPUT1 Cryptography input 1 0x224 32 read-write 0x0 0x0 INPUT Four Bytes of the plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0]. [31:0] read-write CRYPTO_INPUT2 Cryptography input 2 0x228 32 read-write 0x0 0x0 INPUT Four Bytes of the plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0]. [31:0] read-write CRYPTO_INPUT3 Cryptography input 3 0x22C 32 read-write 0x0 0x0 INPUT Four Bytes of the plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0]. [31:0] read-write CRYPTO_KEY0 Cryptography key 0 0x240 32 write-only 0x0 0x0 KEY Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0]. [31:0] write-only CRYPTO_KEY1 Cryptography key 1 0x244 32 write-only 0x0 0x0 KEY Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0]. [31:0] write-only CRYPTO_KEY2 Cryptography key 2 0x248 32 write-only 0x0 0x0 KEY Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0]. [31:0] write-only CRYPTO_KEY3 Cryptography key 3 0x24C 32 write-only 0x0 0x0 KEY Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0]. [31:0] write-only CRYPTO_OUTPUT0 Cryptography output 0 0x260 32 read-write 0x0 0x0 OUTPUT Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0]. [31:0] read-write CRYPTO_OUTPUT1 Cryptography output 1 0x264 32 read-write 0x0 0x0 OUTPUT Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0]. [31:0] read-write CRYPTO_OUTPUT2 Cryptography output 2 0x268 32 read-write 0x0 0x0 OUTPUT Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0]. [31:0] read-write CRYPTO_OUTPUT3 Cryptography output 3 0x26C 32 read-write 0x0 0x0 OUTPUT Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0]. [31:0] read-write INTR Interrupt register 0x7C0 32 read-write 0x0 0x3F TR_TX_REQ Activated in MMIO mode, when a TX data FIFO trigger 'tr_tx_req' is activated. [0:0] read-write TR_RX_REQ Activated in MMIO mode, when a RX data FIFO trigger 'tr_rx_req' is activated. [1:1] read-write XIP_ALIGNMENT_ERROR Activated in XIP mode, if: - The selected device's ADDR_CTL.DIV2 is '1' and the AHB-Lite bus transfer address is not a multiple of 2. - The selected device's ADDR_CTL.DIV2 is '1' and the XIP transfer request is NOT for a multiple of 2 Bytes. Note: In dual-quad SPI mode (ADDR_CTL.DIV is '1'), each memory device contributes a 4-bit nibble for read data or write data. This is only possible if the request address is a multiple of 2 and the number of requested Bytes is a multiple of 2. [2:2] read-write TX_CMD_FIFO_OVERFLOW Activated in MMIO mode, on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_FIFO_WR) with not enough free entries available. [3:3] read-write TX_DATA_FIFO_OVERFLOW Activated in MMIO mode, on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FIFO_WR1, TX_DATA_FIFO_WR2, TX_DATA_FIFO_WR4) with not enough free entries available. [4:4] read-write RX_DATA_FIFO_UNDERFLOW Activated in MMIO mode, on an AHB-Lite read transfer from the RX data FIFO (RX_DATA_FIFO_RD1, RX_DATA_FIFO_RD2, RX_DATA_FIFO_RD4) with not enough entries available. Only activated for NON test bus controller transfers. [5:5] read-write INTR_SET Interrupt set register 0x7C4 32 read-write 0x0 0x3F TR_TX_REQ Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write TR_RX_REQ Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write XIP_ALIGNMENT_ERROR Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write TX_CMD_FIFO_OVERFLOW Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write TX_DATA_FIFO_OVERFLOW Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write RX_DATA_FIFO_UNDERFLOW Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write INTR_MASK Interrupt mask register 0x7C8 32 read-write 0x0 0x3F TR_TX_REQ Mask bit for corresponding bit in interrupt request register. [0:0] read-write TR_RX_REQ Mask bit for corresponding bit in interrupt request register. [1:1] read-write XIP_ALIGNMENT_ERROR Mask bit for corresponding bit in interrupt request register. [2:2] read-write TX_CMD_FIFO_OVERFLOW Mask bit for corresponding bit in interrupt request register. [3:3] read-write TX_DATA_FIFO_OVERFLOW Mask bit for corresponding bit in interrupt request register. [4:4] read-write RX_DATA_FIFO_UNDERFLOW Mask bit for corresponding bit in interrupt request register. [5:5] read-write INTR_MASKED Interrupt masked register 0x7CC 32 read-only 0x0 0x3F TR_TX_REQ Logical and of corresponding request and mask bits. [0:0] read-only TR_RX_REQ Logical and of corresponding request and mask bits. [1:1] read-only XIP_ALIGNMENT_ERROR Logical and of corresponding request and mask bits. [2:2] read-only TX_CMD_FIFO_OVERFLOW Logical and of corresponding request and mask bits. [3:3] read-only TX_DATA_FIFO_OVERFLOW Logical and of corresponding request and mask bits. [4:4] read-only RX_DATA_FIFO_UNDERFLOW Logical and of corresponding request and mask bits. [5:5] read-only 4 128 DEVICE[%s] Device (only used in XIP mode) 0x00000800 CTL Control 0x0 32 read-write 0x0 0x80030101 WR_EN Write enable: '0': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error. '1': write transfers are allowed to this device. [0:0] read-write CRYPTO_EN Cryptography on read/write accesses: '0': disabled. '1': enabled. [8:8] read-write DATA_SEL Specifies the connection of the IP's data lines (spi_data[0], ..., spi_data[7]) to the device's data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7): '0': spi_data[0] = IO0, spi_data[1] = IO1, ..., spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode. '1': spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes. '2': spi_data[4] = IO0, spi_data[5] = IO1, ..., spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad SPI modes. In dual quad SPI mode, this value must be used for the second device. '3': spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes. [17:16] read-write ENABLED Device enable: '0': Disabled. '1': Enabled. [31:31] read-write ADDR Device region base address 0x8 32 read-write 0x0 0x0 ADDR Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m. In dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index. The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24]. [31:8] read-write MASK Device region mask 0xC 32 read-write 0x0 0x0 MASK Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] & MASK[31:8]) == ADDR.ADDR[31:8]. The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff. Note: a transfer request that is not in any device region results in an AHB-Lite bus error. [31:8] read-write ADDR_CTL Address control 0x20 32 read-write 0x0 0x103 SIZE2 Specifies the size of the XIP device address in Bytes: '0': 1 Byte address. '1': 2 Byte address. '2': 3 Byte address. '3': 4 Byte address. The lower significant address Bytes of the transfer request are used as XIP address to the external device. Note that for dual quad SPI data transfer, the transfer request address is divided by 2. Therefore, the transfer request address needs to be a multiple of 2. If the trasnfer requestaddress is NOT a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. [1:0] read-write DIV2 Specifies if the AHB-Lite bus transfer address is divided by 2 or not: '0': No divide by 2. '1': Divide by 2. This functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to '1' in dual quad SPI mode. If the transfer request address is NOT a multiple of 2 or the requested number of Bytes is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. [8:8] read-write RD_CMD_CTL Read command control 0x40 32 read-write 0x0 0x800300FF CODE Command byte code. [7:0] read-write WIDTH Width of data transfer: '0': 1 bit/cycle (single data transfer). '1': 2 bits/cycle (dual data transfer). '2': 4 bits/cycle (quad data transfer). '3': 8 bits/cycle (octal data transfer). [17:16] read-write PRESENT Presence of command field: '0': not present '1': present [31:31] read-write RD_ADDR_CTL Read address control 0x44 32 read-write 0x0 0x30000 WIDTH Width of transfer. [17:16] read-write RD_MODE_CTL Read mode control 0x48 32 read-write 0x0 0x800300FF CODE Mode byte code. [7:0] read-write WIDTH Width of transfer. [17:16] read-write PRESENT Presence of mode field: '0': not present '1': present [31:31] read-write RD_DUMMY_CTL Read dummy control 0x4C 32 read-write 0x0 0x8000001F SIZE5 Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles. Note: this field specifies dummy cycles, not dummy Bytes! [4:0] read-write PRESENT Presence of dummy cycles: '0': not present '1': present [31:31] read-write RD_DATA_CTL Read data control 0x50 32 read-write 0x0 0x30000 WIDTH Width of transfer. [17:16] read-write WR_CMD_CTL Write command control 0x60 32 read-write 0x0 0x800300FF CODE Command byte code. [7:0] read-write WIDTH Width of transfer. [17:16] read-write PRESENT Presence of command field: '0': not present '1': present [31:31] read-write WR_ADDR_CTL Write address control 0x64 32 read-write 0x0 0x30000 WIDTH Width of transfer. [17:16] read-write WR_MODE_CTL Write mode control 0x68 32 read-write 0x0 0x800300FF CODE Mode byte code. [7:0] read-write WIDTH Width of transfer. [17:16] read-write PRESENT Presence of mode field: '0': not present '1': present [31:31] read-write WR_DUMMY_CTL Write dummy control 0x6C 32 read-write 0x0 0x8000001F SIZE5 Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles. [4:0] read-write PRESENT Presence of dummy cycles: '0': not present '1': present [31:31] read-write WR_DATA_CTL Write data control 0x70 32 read-write 0x0 0x30000 WIDTH Width of transfer. [17:16] read-write SCB0 Serial Communications Block (SPI/UART/I2C) SCB 0x40610000 0 65536 registers CTRL Generic control 0x0 32 read-write 0x300000F 0x83031F0F OVS N/A [3:0] read-write EC_AM_MODE This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI) '0': Internally clocked mode '1': Externally clocked mode In internally clocked mode, the serial interface protocols run off the SCB clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. The clocking for the rest of the logic is determined by CTRL.EC_OP_MODE. Externally clocked mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. In UART mode this field should be '0'. [8:8] read-write EC_OP_MODE This field specifies the clocking for the SCB block '0': Internally clocked mode '1': externally clocked mode In internally clocked mode, the serial interface protocols run off the SCB clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode AND EZ mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The maximum SPI slave, EZ mode bitrate is 48 Mbps (transmission and IO delays outside the IP will degrade the effective bitrate). In UART mode this field should be '0'. [9:9] read-write EZ_MODE Non EZ mode ('0') or EZ mode ('1'). In EZ mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory address, a write memory data element or a read memory data element. EZ mode is only used for synchronous serial interface protocols: SPI and I2C. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported and the transmitter should use continuous data frames; i.e. data frames not seperated by slave deselection. This mode is only applicable to slave functionality. In EZ mode, the slave can read from and write to an addressable memory structure of 32 bytes. In EZ mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first. In UART mode this field should be '0'. [10:10] read-write BYTE_MODE N/A [11:11] read-write CMD_RESP_MODE N/A [12:12] read-write ADDR_ACCEPT Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0'). In I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when this bit is '1' for both I2C read and write transfers. In multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. Note: non-matching addresses are never put in the RX FIFO. [16:16] read-write BLOCK Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide, this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0'). IF BLOCK is '0' and the accesses collide, CPU read operations return 0xffff:ffff and CPU write operations are ignored. Colliding accesses are registered as interrupt causes: INTR_TX.BLOCKED and INTR_RX.BLOCKED. [17:17] read-write MODE N/A [25:24] read-write I2C N/A 0 SPI N/A 1 UART N/A 2 ENABLED SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows: - Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL registers. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable. - Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality. - Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information. - Program CTRL register to enable SCB, select the specific operation mode and oversampling factor. When this block is enabled, no control information should be changed. Changes should be made AFTER disabling this block, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the block is re-enabled. Note that disabling the block will cause re-initialization of the design and associated state is lost (e.g. FIFO content). [31:31] read-write STATUS Generic status 0x4 32 read-only 0x0 0x0 EC_BUSY Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a blocked SW access) or bus errors being generated). Note that the INTR_TX.BLOCKED and INTR_RX.BLOCKED interrupt causes are used to indicate whether a SW access was actually blocked by externally clocked logic. [0:0] read-only CMD_RESP_CTRL Command/response control 0x8 32 read-write 0x0 0x1FF01FF BASE_RD_ADDR I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers. [8:0] read-write BASE_WR_ADDR I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers. [24:16] read-write CMD_RESP_STATUS Command/response status 0xC 32 read-only 0x0 0x0 CURR_RD_ADDR I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximim memory buffer address). The field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR - CMD_RESP_CTRL.BASE_RD_ADDR). This field is reliable when there is no bus transfer. This field is potentially unreliable when there is a ongoing bus transfer, i.e. when CMD_RESP_EC_BUSY is '0', the field is reliable. [8:0] read-only CURR_WR_ADDR I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximim memory buffer address). The field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR). This field is reliable when there is no bus transfer. This field is potentially unreliable when there is a ongoing bus transfer, i.e when CMD_RESP_EC_BUSY is '0', the field is reliable. [24:16] read-only CMD_RESP_EC_BUS_BUSY Indicates whether there is an ongoing bus transfer to the IP. '0': no ongoing bus transfer. '1': ongoing bus transfer. For SPI, the field is '1' when slave mode is selected. For I2C, the field is set to '1' at a I2C START/RESTART. In case of an address match, the field is set to '0' on a I2C STOP. In case of NO address match, the field is set to '0' after the failing address match. [30:30] read-only CMD_RESP_EC_BUSY N/A [31:31] read-only SPI_CTRL SPI control 0x20 32 read-write 0x3000000 0x8F010F3F SSEL_CONTINUOUS Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode, both continuous and non-continuous SPI data transfers are supported independent of this field. When continuous transfers are enabled individual data frame transfers are not necessarily seperated by slave deselection (as indicated by the level or pulse on the SELECT line): if the TX FIFO has multiple data frames, data frames are send out without slave deselection. When continuous transfers are not enabled individual data frame transfers are always seperated by slave deselection: independent of the availability of TX FIFO data frames, data frames are sent out with slave deselection. [0:0] read-write SELECT_PRECEDE Only used in SPI Texas Instruments' submode. When '1', the data frame start indication is a pulse on the Slave SELECT line that precedes the transfer of the first data frame bit. When '0', the data frame start indication is a pulse on the Slave SELECT line that coincides with the transfer of the first data frame bit. [1:1] read-write CPHA N/A [2:2] read-write CPOL N/A [3:3] read-write LATE_MISO_SAMPLE Changes the SCLK edge on which MISO is captured. Only used in master mode. When '0', the default applies ( for Motorola as determined by CPOL and CPHA, for Texas Instruments on the falling edge of SCLK and for National Semiconductors on the rising edge of SCLK). When '1', the alternate clock edge is used (which comes half a SPI SCLK period later). Late sampling addresses the round trip delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master. [4:4] read-write SCLK_CONTINUOUS N/A [5:5] read-write SSEL_POLARITY0 N/A [8:8] read-write SSEL_POLARITY1 N/A [9:9] read-write SSEL_POLARITY2 N/A [10:10] read-write SSEL_POLARITY3 N/A [11:11] read-write LOOPBACK Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode. '0': No local loopback '1': the SPI master MISO line is connected to the SPI master MOSI line. In other words, in loopback mode the SPI master receives on MISO what it transmits on MOSI. [16:16] read-write MODE N/A [25:24] read-write SPI_MOTOROLA SPI Motorola submode. In master mode, when not transmitting data (Slave SELECT is inactive), SCLK is stable at CPOL. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), Slave SELECT is inactive. 0 SPI_TI SPI Texas Instruments submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), Slave SELECT is inactive; i.e. no pulse is generated. 1 SPI_NS SPI National Semiconducturs submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), Slave SELECT is inactive. 2 SSEL Selects one of the four incoming/outgoing SPI slave select signals: - 0: Slave 0, SSEL[0]. - 1: Slave 1, SSEL[1]. - 2: Slave 2, SSEL[2]. - 3: Slave 3, SSEL[3]. SCB block should be disabled when changes are made to this field. [27:26] read-write MASTER_MODE N/A [31:31] read-write SPI_STATUS SPI status 0x24 32 read-only 0x0 0x0 BUS_BUSY SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted. [0:0] read-only SPI_EC_BUSY Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable. [1:1] read-only CURR_EZ_ADDR SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'), as clock domain synchronization is not performed in the design. [15:8] read-only BASE_EZ_ADDR SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design. [23:16] read-only UART_CTRL UART control 0x40 32 read-write 0x3000000 0x3010000 LOOPBACK Local loopback control (does NOT affect the information on the pins). 0: Loopback is not enabled 1: UART_TX is connected to UART_RX. UART_RTS is connected to UART_CTS. This allows a SCB UART transmitter to communicate with its receiver counterpart. [16:16] read-write MODE N/A [25:24] read-write UART_STD N/A 0 UART_SMARTCARD N/A 1 UART_IRDA Infrared Data Association (IrDA) submode. Return to Zero modulation scheme. In this mode, the oversampling factor should be 16, that is OVS should be set to 15. 2 UART_TX_CTRL UART transmitter control 0x44 32 read-write 0x2 0x137 STOP_BITS Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. [2:0] read-write PARITY Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes. [4:4] read-write PARITY_ENABLED Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware [5:5] read-write RETRY_ON_NACK When '1', a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode. [8:8] read-write UART_RX_CTRL UART receiver control 0x48 32 read-write 0xA0002 0xF3777 STOP_BITS N/A [2:0] read-write PARITY N/A [4:4] read-write PARITY_ENABLED N/A [5:5] read-write POLARITY Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality. [6:6] read-write DROP_ON_PARITY_ERROR Behaviour when a parity check fails. When '0', received data is sent to the RX FIFO. When '1', received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field). [8:8] read-write DROP_ON_FRAME_ERROR Behaviour when an error is detected in a start or stop period. When '0', received data is sent to the RX FIFO. When '1', received data is dropped and lost. [9:9] read-write MP_MODE N/A [10:10] read-write LIN_MODE Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. [12:12] read-write SKIP_START N/A [13:13] read-write BREAK_WIDTH N/A [19:16] read-write UART_RX_STATUS UART receiver status 0x4C 32 read-only 0x0 0x0 BR_COUNTER Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has valid data when INTR_RX.BAUD_DETECT is set to '1'. [11:0] read-only UART_FLOW_CTRL UART flow control 0x50 32 read-write 0x0 0x30100FF TRIGGER_LEVEL Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal is activated. By setting this field to '0', flow control is effectively disabled (may be useful for debug purposes). [7:0] read-write RTS_POLARITY Polarity of the RTS output signal: '0': RTS is active low; '1': RTS is active high; During SCB reset (Hibernate system power mode), RTS output signal is '1'. This represents an inactive state assuming an active low polarity. [16:16] read-write CTS_POLARITY Polarity of the CTS input signal '0': CTS is active low ; '1': CTS is active high; [24:24] read-write CTS_ENABLED Enable use of CTS input signal by the UART transmitter: '0': Disabled. The UART transmitter ignores the CTS input signal and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register. '1': Enabled. The UART transmitter uses CTS input signal to qualify the transmission of data. It transmits when CTS input signal is active and a data frame is available for transmission in the TX FIFO or the TX shift register. If UART_CTRL.LOOPBACK is '1', the CTS input signal is driven by the RTS output signal locally in SCB (both signals are subjected to signal polarity changes are indicated by RTS_POLARITY and CTS_POLARITY). [25:25] read-write I2C_CTRL I2C control 0x60 32 read-write 0xFB88 0xC001FBFF HIGH_PHASE_OVS Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5, 15] with input signal median filtering and [4, 15] without input signal median filtering. The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the SCB clock wrt. the regular interface (IF) high time to guarantee functional correct behavior. With input signal median filtering, the IF high time should be >= 6 SCB clock cycles and <= 16 SCB clock cycles. Without input signal median filtering, the IF high time should be >= 5 SCB clock cycles and <= 16 SCB clock cycles. [3:0] read-write LOW_PHASE_OVS Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering. The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the SCB clock wrt. the regular (no stretching) interface (IF) low time to guarantee functionally correct behavior. With input signal median filtering, the IF low time should be >= 8 SCB clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF low time should be >= 7 SCB clock cycles and <= 16 SCB clock cycles. [7:4] read-write M_READY_DATA_ACK N/A [8:8] read-write M_NOT_READY_DATA_NACK N/A [9:9] read-write S_GENERAL_IGNORE N/A [11:11] read-write S_READY_ADDR_ACK N/A [12:12] read-write S_READY_DATA_ACK N/A [13:13] read-write S_NOT_READY_ADDR_NACK This field is used during an address match or general call address in internally clocked mode Only used when: - EC_AM_MODE is '0', EC_OP_MODE is '0', S_GENERAL_IGNORE is '0] and non EZ mode. Functionality is as follows: - 1: a received (matching) slave address is immediately NACK'd when the receiver FIFO is full. - 0: clock stretching is performed (till the receiver FIFO is no longer full). For externally clocked logic (EC_AM is '1') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when (NOT used when EC_AM is '1' and EC_OP is '1' and address match and EZ mode): - EC_AM is '1' and EC_OP is '0'. - EC_AM is '1' and general call address match. - EC_AM is '1' and non EZ mode. Functionality is as follows: - 1: a received (matching or general) slave address is always immediately NACK'd. There are two possibilities: 1). the SCB clock is available (in Active system power mode) and it handles the rest of the current transfer. In this case the I2C master will not observe the NACK. 2).SCB clock is not present (in DeepSleep system power mode). In this case the I2C master will observe the NACK and may retry the transfer in the future (which gives the internally clocked logic the time to wake up from DeepSleep system power mode). - 0: clock stretching is performed (till the SCB clock is available). The logic will handle the ongoing transfer as soon as the clock is enabled. [14:14] read-write S_NOT_READY_DATA_NACK Only used when: - non EZ mode Functionality is as follows: - 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full. - 0: clock stretching is performed (till the receiver FIFO is no longer full). [15:15] read-write LOOPBACK Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0', no loopback When '1', loopback is enabled internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself. [16:16] read-write SLAVE_MODE N/A [30:30] read-write MASTER_MODE N/A [31:31] read-write I2C_STATUS I2C status 0x64 32 read-only 0x0 0x31 BUS_BUSY I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If SCB block is disabled, BUS_BUSY is '0'. After enabling the block, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period). For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions). For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions). [0:0] read-only I2C_EC_BUSY N/A [1:1] read-only S_READ N/A [4:4] read-only M_READ N/A [5:5] read-only CURR_EZ_ADDR N/A [15:8] read-only BASE_EZ_ADDR N/A [23:16] read-only I2C_M_CMD I2C master command 0x68 32 read-write 0x0 0x1F M_START When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START is transmitted when the master state machine is not in the default state, but is working on an ongoing transaction. The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a received data element. When this action is performed, the hardware sets this field to '0'. [0:0] read-write M_START_ON_IDLE When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is only functional after at least one I2C bus transfer has been detected on the bus (default/reset value of BUSY is '0') . A START is only transmitted when the master state machine is in the default state. When this action is performed, the hardware sets this field to '0'. [1:1] read-write M_ACK When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. [2:2] read-write M_NACK When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. [3:3] read-write M_STOP When '1', attempt to transmit a STOP. When this action is performed, the hardware sets this field to '0'. I2C_M_CMD.M_START has a higher priority than this command: in situations where both a STOP and a REPEATED START could be transmitted, M_START takes precedence over M_STOP. [4:4] read-write I2C_S_CMD I2C slave command 0x6C 32 read-write 0x0 0x3 S_ACK When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). [0:0] read-write S_NACK When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher priority than I2C_S_CMD.S_ACK, I2C_CTRL.S_READY_ADDR_ACK or I2C_CTRL.S_READY_DATA_ACK. [1:1] read-write I2C_CFG I2C configuration 0x70 32 read-write 0x2A1013 0x303F1313 SDA_IN_FILT_TRIM Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required [1:0] read-write SDA_IN_FILT_SEL Enable for 50ns glitch filter on SDA input '0': 0 ns. '1: 50 ns (filter enabled). [4:4] read-write SCL_IN_FILT_TRIM Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required [9:8] read-write SCL_IN_FILT_SEL Enable for 50ns glitch filter on SCL input '0': 0 ns. '1: 50 ns (filter enabled). [12:12] read-write SDA_OUT_FILT0_TRIM Trim settings for the 50ns delay filter on SDA output used to gurantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required [17:16] read-write SDA_OUT_FILT1_TRIM Trim settings for the 50ns delay filter on SDA output used to gurantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required [19:18] read-write SDA_OUT_FILT2_TRIM Trim settings for the 50ns delay filter on SDA output used to gurantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required [21:20] read-write SDA_OUT_FILT_SEL Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter '0': 0 ns. '1': 50 ns (filter 0 enabled). '2': 100 ns (filters 0 and 1 enabled). '3': 150 ns (filters 0, 1 and 2 enabled). [29:28] read-write DDFT_CTRL Digital DfT control 0x100 32 read-write 0x0 0x770011 DDFT_IN0_SEL Specifies signal that is connected to 'ddft_in[0]' (digital DfT input signal 0): '0': not used '1': used as 'i2c_scl_in' in I2C mode, as 'spi_clk_in' in SPI mode [0:0] read-write DDFT_IN1_SEL Specifies signal that is connected to 'ddft_in[1]' (digital DfT input signal 0): '0': not used '1': used as 'i2c_sda_in' in I2C mode, as 'spi_mosi_in' in SPI mode [4:4] read-write DDFT_OUT0_SEL Specifies signal that is connected to 'ddft_out[0]' (digital DfT output signal 0): In I2C mode (CTRL.MODE=0), '0': Constant '0'. '1': 'ec_busy_pp'. '2': 'rst_i2c_start_stop_n'. '3': 'rst_i2c_start_stop_n'. '4': 'i2c_scl_in_qual'. '5': 'i2c_sda_out_prel'. '6'-'7': Undefined. in SPI mode (CTRL.MODE=1), '0': Constant '0'. '1': 'rst_spi_n' '2': 'rst_spi_stop_n' '3'-'7': Undefined. [18:16] read-write DDFT_OUT1_SEL Specifies signal that is connected to 'ddft_out[1]' (digital DfT output signal 1): In I2C mode (CTRL.MODE=0), '0': Constant '0'. '1': 'clk_ff_sram'. '2': 'rst_i2c_n'. '3': 'rst_i2c_stop_n'. '4': 'i2c_sda_in_qual'. '5': 'i2c_sda_out'. '6': 'event_i2c_ec_wake_up_ddft' from I2CS_IC '7': Undefined. In SPI mode (CTRL.MODE=1), '0': Constant '0'. '1': 'spi_start_detect' '2': 'spi_stop_detect' '3'-'7': Undefined. [22:20] read-write TX_CTRL Transmitter control 0x200 32 read-write 0x107 0x1010F DATA_WIDTH Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. [3:0] read-write MSB_FIRST Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. [8:8] read-write OPEN_DRAIN Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'. '0': Normal operation mode. Typically, this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by a single IO cell. In this operation mode, for an IO cell 'xxx' that is used as an output, the 'xxx_out_en' output enable signal is typically constant '1' the 'xxx_out' output is the outputted value. In other words, in normal operation mode, the 'xxx_out' output is used to control the IO cell output value: 'xxx_out' is '0' to drive an IO cell output value of '0' and 'xxx_out' is '1' to drive an IO cell output value of '1'. '1': Open drain operation mode. Typically this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by multiple IO cells (possibly on multiple chips). In this operation mode, for and IO cell 'xxx' that is used as an output, the 'xxx_out_en' output controls the outputted value. Typically, open drain operation mode drives low/'0' and the 'xxx_out' output is constant '1'. In other words, in open drain operation mode, the 'xxx_out_en' output is used to control the IO cell output value: in drive low/'0' mode: 'xxx_out_en' is '1' (drive enabled) to drive an IO cell output value of '0' and 'xxx_out_en' is '1' (drive disabled) to not drive an IO cell output value (another IO cell can drive the wire/line or a pull up results in a wire/line value '1'). The open drain mode is supported for: - I2C mode, 'i2c_scl' and 'i2c_sda' IO cells. - UART mode, 'uart_tx' IO cell (SPI slave). - SPI mode, 'spi_miso' IO cell. [16:16] read-write TX_FIFO_CTRL Transmitter FIFO control 0x204 32 read-write 0x0 0x300FF TRIGGER_LEVEL Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event is generated. [7:0] read-write CLEAR When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. [16:16] read-write FREEZE When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. [17:17] read-write TX_FIFO_STATUS Transmitter FIFO status 0x208 32 read-only 0x0 0xFFFF81FF USED Amount of enties in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR. [8:0] read-only SR_VALID Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is tranmitted next (when the protocol state machine is not transmitting a data frame). [15:15] read-only RD_PTR FIFO read pointer: FIFO location from which a data frame is read by the hardware. [23:16] read-only WR_PTR FIFO write pointer: FIFO location at which a new data frame is written. [31:24] read-only TX_FIFO_WR Transmitter FIFO write 0x240 32 write-only 0x0 0xFFFF DATA Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'. [15:0] write-only RX_CTRL Receiver control 0x300 32 read-write 0x107 0x30F DATA_WIDTH Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. In EZ mode (for both SPI and I2C), the only valid value is 7. [3:0] read-write MSB_FIRST Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. [8:8] read-write MEDIAN Median filter. When '1', a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptability to errors. However, its requires higher oversampling values. For UART IrDA submode, this field should always be '1'. [9:9] read-write RX_FIFO_CTRL Receiver FIFO control 0x304 32 read-write 0x0 0x300FF TRIGGER_LEVEL Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event is generated. [7:0] read-write CLEAR When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. [16:16] read-write FREEZE When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer. [17:17] read-write RX_FIFO_STATUS Receiver FIFO status 0x308 32 read-only 0x0 0xFFFF81FF USED Amount of enties in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR. [8:0] read-only SR_VALID Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame). [15:15] read-only RD_PTR FIFO read pointer: FIFO location from which a data frame is read. [23:16] read-only WR_PTR FIFO write pointer: FIFO location at which a new data frame is written by the hardware. [31:24] read-only RX_MATCH Slave address and mask 0x310 32 read-write 0x0 0xFF00FF ADDR N/A [7:0] read-write MASK Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK)). [23:16] read-write RX_FIFO_RD Receiver FIFO read 0x340 32 read-only 0x0 0x0 DATA Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. When this register is read through the debugger, the data frame will not be removed from the FIFO. Similar in operation to RX_FIFO_RD_SILENT [15:0] read-only RX_FIFO_RD_SILENT Receiver FIFO read silent 0x344 32 read-only 0x0 0x0 DATA Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. [15:0] read-only INTR_CAUSE Active clocked interrupt signal 0xE00 32 read-only 0x0 0x3F M Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0. [0:0] read-only S Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0. [1:1] read-only TX Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0. [2:2] read-only RX Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0. [3:3] read-only I2C_EC Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0. [4:4] read-only SPI_EC Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0. [5:5] read-only INTR_I2C_EC Externally clocked I2C interrupt request 0xE80 32 read-write 0x0 0xF WAKE_UP Wake up request. Active on incoming slave request (with address match). Only used when CTRL.EC_AM_MODE is '1'. [0:0] read-write EZ_STOP STOP detection. Activated on the end of a every transfer (I2C STOP). Only available for a slave request with an address match, in EZ and CMD_RESP modes, when CTRL.EC_OP_MODE is '1'. [1:1] read-write EZ_WRITE_STOP STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. Only available for a slave request with an address match, in EZ and CMD_RESP modes, when CTRL.EC_OP_MODE is '1'. [2:2] read-write EZ_READ_STOP STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from. Only available for a slave request with an address match, in EZ and CMD_RESP modes, when CTRL.EC_OP_MODE is '1'. [3:3] read-write INTR_I2C_EC_MASK Externally clocked I2C interrupt mask 0xE88 32 read-write 0x0 0xF WAKE_UP Mask bit for corresponding bit in interrupt request register. [0:0] read-write EZ_STOP Mask bit for corresponding bit in interrupt request register. [1:1] read-write EZ_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [2:2] read-write EZ_READ_STOP Mask bit for corresponding bit in interrupt request register. [3:3] read-write INTR_I2C_EC_MASKED Externally clocked I2C interrupt masked 0xE8C 32 read-only 0x0 0xF WAKE_UP Logical and of corresponding request and mask bits. [0:0] read-only EZ_STOP Logical and of corresponding request and mask bits. [1:1] read-only EZ_WRITE_STOP Logical and of corresponding request and mask bits. [2:2] read-only EZ_READ_STOP Logical and of corresponding request and mask bits. [3:3] read-only INTR_SPI_EC Externally clocked SPI interrupt request 0xEC0 32 read-write 0x0 0xF WAKE_UP Wake up request. Active on incoming slave request when externally clocked selection is '1'. Only used when CTRL.EC_AM_MODE is '1'. [0:0] read-write EZ_STOP STOP detection. Activated on the end of a every transfer (SPI deselection). Only available in EZ and CMD_RESP mode and when CTRL.EC_OP_MODE is '1'. [1:1] read-write EZ_WRITE_STOP STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. Only used in EZ and CMD_RESP modes and when CTRL.EC_OP_MODE is '1'. [2:2] read-write EZ_READ_STOP STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from. Only used in EZ and CMD_RESP modes and when CTRL.EC_OP_MODE is '1'. [3:3] read-write INTR_SPI_EC_MASK Externally clocked SPI interrupt mask 0xEC8 32 read-write 0x0 0xF WAKE_UP Mask bit for corresponding bit in interrupt request register. [0:0] read-write EZ_STOP Mask bit for corresponding bit in interrupt request register. [1:1] read-write EZ_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [2:2] read-write EZ_READ_STOP Mask bit for corresponding bit in interrupt request register. [3:3] read-write INTR_SPI_EC_MASKED Externally clocked SPI interrupt masked 0xECC 32 read-only 0x0 0xF WAKE_UP Logical and of corresponding request and mask bits. [0:0] read-only EZ_STOP Logical and of corresponding request and mask bits. [1:1] read-only EZ_WRITE_STOP Logical and of corresponding request and mask bits. [2:2] read-only EZ_READ_STOP Logical and of corresponding request and mask bits. [3:3] read-only INTR_M Master interrupt request 0xF00 32 read-write 0x0 0x317 I2C_ARB_LOST I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line. [0:0] read-write I2C_NACK I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typically after the master transmitted the slave address or TX data). [1:1] read-write I2C_ACK I2C master acknowledgement. Set to '1', when the master receives a ACK (typically after the master transmitted the slave address or TX data). [2:2] read-write I2C_STOP I2C master STOP. Set to '1', when the master has transmitted a STOP. [4:4] read-write I2C_BUS_ERROR I2C master bus error (unexpected detection of START or STOP condition). [8:8] read-write SPI_DONE SPI master transfer done event: all data frames in the transmit FIFO are sent, the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty), and SPI select output pin is deselected. [9:9] read-write INTR_M_SET Master interrupt set request 0xF04 32 read-write 0x0 0x317 I2C_ARB_LOST Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write I2C_STOP Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write I2C_BUS_ERROR Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write SPI_DONE Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write INTR_M_MASK Master interrupt mask 0xF08 32 read-write 0x0 0x317 I2C_ARB_LOST Mask bit for corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Mask bit for corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Mask bit for corresponding bit in interrupt request register. [2:2] read-write I2C_STOP Mask bit for corresponding bit in interrupt request register. [4:4] read-write I2C_BUS_ERROR Mask bit for corresponding bit in interrupt request register. [8:8] read-write SPI_DONE Mask bit for corresponding bit in interrupt request register. [9:9] read-write INTR_M_MASKED Master interrupt masked request 0xF0C 32 read-only 0x0 0x317 I2C_ARB_LOST Logical and of corresponding request and mask bits. [0:0] read-only I2C_NACK Logical and of corresponding request and mask bits. [1:1] read-only I2C_ACK Logical and of corresponding request and mask bits. [2:2] read-only I2C_STOP Logical and of corresponding request and mask bits. [4:4] read-only I2C_BUS_ERROR Logical and of corresponding request and mask bits. [8:8] read-only SPI_DONE Logical and of corresponding request and mask bits. [9:9] read-only INTR_S Slave interrupt request 0xF40 32 read-write 0x0 0xFFF I2C_ARB_LOST I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine aborts the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. [0:0] read-write I2C_NACK N/A [1:1] read-write I2C_ACK N/A [2:2] read-write I2C_WRITE_STOP N/A [3:3] read-write I2C_STOP N/A [4:4] read-write I2C_START I2C slave START received. Set to '1', when START or REPEATED START event is detected. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL. [5:5] read-write I2C_ADDR_MATCH N/A [6:6] read-write I2C_GENERAL N/A [7:7] read-write I2C_BUS_ERROR N/A [8:8] read-write SPI_EZ_WRITE_STOP N/A [9:9] read-write SPI_EZ_STOP N/A [10:10] read-write SPI_BUS_ERROR N/A [11:11] read-write INTR_S_SET Slave interrupt set request 0xF44 32 read-write 0x0 0xFFF I2C_ARB_LOST Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write I2C_WRITE_STOP Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write I2C_STOP Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write I2C_START Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write I2C_ADDR_MATCH Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write I2C_GENERAL Write with '1' to set corresponding bit in interrupt request register. [7:7] read-write I2C_BUS_ERROR Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write SPI_EZ_WRITE_STOP Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write SPI_EZ_STOP Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write SPI_BUS_ERROR Write with '1' to set corresponding bit in interrupt request register. [11:11] read-write INTR_S_MASK Slave interrupt mask 0xF48 32 read-write 0x0 0xFFF I2C_ARB_LOST Mask bit for corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Mask bit for corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Mask bit for corresponding bit in interrupt request register. [2:2] read-write I2C_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [3:3] read-write I2C_STOP Mask bit for corresponding bit in interrupt request register. [4:4] read-write I2C_START Mask bit for corresponding bit in interrupt request register. [5:5] read-write I2C_ADDR_MATCH Mask bit for corresponding bit in interrupt request register. [6:6] read-write I2C_GENERAL Mask bit for corresponding bit in interrupt request register. [7:7] read-write I2C_BUS_ERROR Mask bit for corresponding bit in interrupt request register. [8:8] read-write SPI_EZ_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [9:9] read-write SPI_EZ_STOP Mask bit for corresponding bit in interrupt request register. [10:10] read-write SPI_BUS_ERROR Mask bit for corresponding bit in interrupt request register. [11:11] read-write INTR_S_MASKED Slave interrupt masked request 0xF4C 32 read-only 0x0 0xFFF I2C_ARB_LOST Logical and of corresponding request and mask bits. [0:0] read-only I2C_NACK Logical and of corresponding request and mask bits. [1:1] read-only I2C_ACK Logical and of corresponding request and mask bits. [2:2] read-only I2C_WRITE_STOP Logical and of corresponding request and mask bits. [3:3] read-only I2C_STOP Logical and of corresponding request and mask bits. [4:4] read-only I2C_START Logical and of corresponding request and mask bits. [5:5] read-only I2C_ADDR_MATCH Logical and of corresponding request and mask bits. [6:6] read-only I2C_GENERAL Logical and of corresponding request and mask bits. [7:7] read-only I2C_BUS_ERROR Logical and of corresponding request and mask bits. [8:8] read-only SPI_EZ_WRITE_STOP Logical and of corresponding request and mask bits. [9:9] read-only SPI_EZ_STOP Logical and of corresponding request and mask bits. [10:10] read-only SPI_BUS_ERROR Logical and of corresponding request and mask bits. [11:11] read-only INTR_TX Transmitter interrupt request 0xF80 32 read-write 0x0 0x7F3 TRIGGER N/A [0:0] read-write NOT_FULL N/A [1:1] read-write EMPTY N/A [4:4] read-write OVERFLOW N/A [5:5] read-write UNDERFLOW Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'. Only used in FIFO mode. [6:6] read-write BLOCKED SW cannot get access to the EZ memory (EZ data access), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. [7:7] read-write UART_NACK N/A [8:8] read-write UART_DONE N/A [9:9] read-write UART_ARB_LOST N/A [10:10] read-write INTR_TX_SET Transmitter interrupt set request 0xF84 32 read-write 0x0 0x7F3 TRIGGER Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write NOT_FULL Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write EMPTY Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write OVERFLOW Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write UNDERFLOW Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write BLOCKED Write with '1' to set corresponding bit in interrupt request register. [7:7] read-write UART_NACK Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write UART_DONE Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write UART_ARB_LOST Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write INTR_TX_MASK Transmitter interrupt mask 0xF88 32 read-write 0x0 0x7F3 TRIGGER Mask bit for corresponding bit in interrupt request register. [0:0] read-write NOT_FULL Mask bit for corresponding bit in interrupt request register. [1:1] read-write EMPTY Mask bit for corresponding bit in interrupt request register. [4:4] read-write OVERFLOW Mask bit for corresponding bit in interrupt request register. [5:5] read-write UNDERFLOW Mask bit for corresponding bit in interrupt request register. [6:6] read-write BLOCKED Mask bit for corresponding bit in interrupt request register. [7:7] read-write UART_NACK Mask bit for corresponding bit in interrupt request register. [8:8] read-write UART_DONE Mask bit for corresponding bit in interrupt request register. [9:9] read-write UART_ARB_LOST Mask bit for corresponding bit in interrupt request register. [10:10] read-write INTR_TX_MASKED Transmitter interrupt masked request 0xF8C 32 read-only 0x0 0x7F3 TRIGGER Logical and of corresponding request and mask bits. [0:0] read-only NOT_FULL Logical and of corresponding request and mask bits. [1:1] read-only EMPTY Logical and of corresponding request and mask bits. [4:4] read-only OVERFLOW Logical and of corresponding request and mask bits. [5:5] read-only UNDERFLOW Logical and of corresponding request and mask bits. [6:6] read-only BLOCKED Logical and of corresponding request and mask bits. [7:7] read-only UART_NACK Logical and of corresponding request and mask bits. [8:8] read-only UART_DONE Logical and of corresponding request and mask bits. [9:9] read-only UART_ARB_LOST Logical and of corresponding request and mask bits. [10:10] read-only INTR_RX Receiver interrupt request 0xFC0 32 read-write 0x0 0xFED TRIGGER N/A [0:0] read-write NOT_EMPTY N/A [2:2] read-write FULL N/A [3:3] read-write OVERFLOW N/A [5:5] read-write UNDERFLOW N/A [6:6] read-write BLOCKED SW cannot get access to the EZ memory (EZ_DATA accesses), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. [7:7] read-write FRAME_ERROR N/A [8:8] read-write PARITY_ERROR N/A [9:9] read-write BAUD_DETECT N/A [10:10] read-write BREAK_DETECT N/A [11:11] read-write INTR_RX_SET Receiver interrupt set request 0xFC4 32 read-write 0x0 0xFED TRIGGER Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write NOT_EMPTY Write with '1' to set corresponding bit in interrupt status register. [2:2] read-write FULL Write with '1' to set corresponding bit in interrupt status register. [3:3] read-write OVERFLOW Write with '1' to set corresponding bit in interrupt status register. [5:5] read-write UNDERFLOW Write with '1' to set corresponding bit in interrupt status register. [6:6] read-write BLOCKED Write with '1' to set corresponding bit in interrupt status register. [7:7] read-write FRAME_ERROR Write with '1' to set corresponding bit in interrupt status register. [8:8] read-write PARITY_ERROR Write with '1' to set corresponding bit in interrupt status register. [9:9] read-write BAUD_DETECT Write with '1' to set corresponding bit in interrupt status register. [10:10] read-write BREAK_DETECT Write with '1' to set corresponding bit in interrupt status register. [11:11] read-write INTR_RX_MASK Receiver interrupt mask 0xFC8 32 read-write 0x0 0xFED TRIGGER Mask bit for corresponding bit in interrupt request register. [0:0] read-write NOT_EMPTY Mask bit for corresponding bit in interrupt request register. [2:2] read-write FULL Mask bit for corresponding bit in interrupt request register. [3:3] read-write OVERFLOW Mask bit for corresponding bit in interrupt request register. [5:5] read-write UNDERFLOW Mask bit for corresponding bit in interrupt request register. [6:6] read-write BLOCKED Mask bit for corresponding bit in interrupt request register. [7:7] read-write FRAME_ERROR Mask bit for corresponding bit in interrupt request register. [8:8] read-write PARITY_ERROR Mask bit for corresponding bit in interrupt request register. [9:9] read-write BAUD_DETECT Mask bit for corresponding bit in interrupt request register. [10:10] read-write BREAK_DETECT Mask bit for corresponding bit in interrupt request register. [11:11] read-write INTR_RX_MASKED Receiver interrupt masked request 0xFCC 32 read-only 0x0 0xFED TRIGGER Logical and of corresponding request and mask bits. [0:0] read-only NOT_EMPTY Logical and of corresponding request and mask bits. [2:2] read-only FULL Logical and of corresponding request and mask bits. [3:3] read-only OVERFLOW Logical and of corresponding request and mask bits. [5:5] read-only UNDERFLOW Logical and of corresponding request and mask bits. [6:6] read-only BLOCKED Logical and of corresponding request and mask bits. [7:7] read-only FRAME_ERROR Logical and of corresponding request and mask bits. [8:8] read-only PARITY_ERROR Logical and of corresponding request and mask bits. [9:9] read-only BAUD_DETECT Logical and of corresponding request and mask bits. [10:10] read-only BREAK_DETECT Logical and of corresponding request and mask bits. [11:11] read-only SCB1 0x40620000 SCB2 0x40630000 SCB3 0x40640000 SCB4 0x40650000 SCB5 0x40660000 SCB6 0x40670000 SCB7 0x40680000 SCB8 0x40690000 CTBM0 Continuous Time Block Mini CTBM 0x41100000 0 65536 registers CTB_CTRL global CTB and power control 0x0 32 read-write 0x0 0xC0000000 DEEPSLEEP_ON - 0: CTB IP disabled off during DeepSleep power mode - 1: CTB IP remains enabled during DeepSleep power mode (if ENABLED=1) [30:30] read-write ENABLED - 0: CTB IP disabled (put analog in power down, open all switches) - 1: CTB IP enabled [31:31] read-write OA_RES0_CTRL Opamp0 and resistor0 control 0x4 32 read-write 0x0 0x1BFF OA0_PWR_MODE Opamp0 power level, assumes Cload=15pF for the (internal only) 1x driver or 50pF for the (external) 10x driver [2:0] read-write OFF Off 0 LOW Low power mode (IDD: 350uA, GBW: 1MHz for both 1x/10x) 1 MEDIUM Medium power mode (IDD: 600uA, GBW: 3MHz for 1x & 2.5MHz for 10x) 2 HIGH High power mode for highest GBW (IDD: 1500uA, GBW: 8MHz for 1x & 6MHz for 10x) 3 RSVD N/A 4 PS_LOW Power Saver Low power mode (IDD: ~20uA with 1uA bias from AREF, GBW: ~100kHz for 1x/10x, offset correcting IDAC is disabled) 5 PS_MEDIUM Power Saver Medium power mode (IDD: ~40uA with 1uA bias from AREF, GBW: ~100kHz for 1x/10x, offset correcting IDAC is enabled) 6 PS_HIGH Power Saver Medium power mode (IDD: ~60uA with 1uA bias from AREF, GBW: ~200kHz for 1x/10x, offset correcting IDAC is enabled) 7 OA0_DRIVE_STR_SEL Opamp0 output strength select 0=1x, 1=10x This setting sets specific requirements for OA0_BOOST_EN and OA0_COMP_TRIM [3:3] read-write OA0_COMP_EN Opamp0 comparator enable [4:4] read-write OA0_HYST_EN Opamp0 hysteresis enable (10mV) [5:5] read-write OA0_BYPASS_DSI_SYNC Opamp0 bypass comparator output synchronization for DSI (trigger) output: 0=synchronize (level or pulse), 1=bypass (output async) [6:6] read-write OA0_DSI_LEVEL Opamp0 comparator DSI (trigger) out level : 0=pulse, each time an edge is detected (see OA0_COMPINT) a pulse is sent out on DSI 1=level, DSI output is a synchronized version of the comparator output [7:7] read-write OA0_COMPINT Opamp0 comparator edge detect for interrupt and pulse mode of DSI (trigger) [9:8] read-write DISABLE Disabled, no interrupts will be detected 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 OA0_PUMP_EN Opamp0 pump enable [11:11] read-write OA0_BOOST_EN Opamp0 gain booster enable for class A output, for risk mitigation only, not user selectable. Value depends on the drive strength setting - 1x mode: set to 1; 10x mode: set to 0 [12:12] read-write OA_RES1_CTRL Opamp1 and resistor1 control 0x8 32 read-write 0x0 0x1BFF OA1_PWR_MODE Opamp1 power level: see description of OA0_PWR_MODE [2:0] read-write OA1_DRIVE_STR_SEL Opamp1 output strength select 0=1x, 1=10x This setting sets specific requirements for OA1_BOOST_EN and OA1_COMP_TRIM [3:3] read-write OA1_COMP_EN Opamp1 comparator enable [4:4] read-write OA1_HYST_EN Opamp1 hysteresis enable (10mV) [5:5] read-write OA1_BYPASS_DSI_SYNC Opamp1 bypass comparator output synchronization for DSI output: 0=synchronize, 1=bypass [6:6] read-write OA1_DSI_LEVEL Opamp1 comparator DSI (trigger) out level : 0=pulse, each time an edge is detected (see OA1_COMPINT) a pulse is sent out on DSI 1=level, DSI output is a synchronized version of the comparator output [7:7] read-write OA1_COMPINT Opamp1 comparator edge detect for interrupt and pulse mode of DSI (trigger) [9:8] read-write DISABLE Disabled, no interrupts will be detected 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 OA1_PUMP_EN Opamp1 pump enable [11:11] read-write OA1_BOOST_EN Opamp1 gain booster enable for class A output, for risk mitigation only, not user selectable. Value depends on the drive strength setting - 1x mode: set to 1; 10x mode: set to 0 [12:12] read-write COMP_STAT Comparator status 0xC 32 read-only 0x0 0x10001 OA0_COMP Opamp0 current comparator status [0:0] read-only OA1_COMP Opamp1 current comparator status [16:16] read-only INTR Interrupt request register 0x20 32 read-write 0x0 0x3 COMP0 Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit. [0:0] read-write COMP1 Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit. [1:1] read-write INTR_SET Interrupt request set register 0x24 32 read-write 0x0 0x3 COMP0_SET Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write COMP1_SET Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write INTR_MASK Interrupt request mask 0x28 32 read-write 0x0 0x3 COMP0_MASK Mask bit for corresponding bit in interrupt request register. [0:0] read-write COMP1_MASK Mask bit for corresponding bit in interrupt request register. [1:1] read-write INTR_MASKED Interrupt request masked 0x2C 32 read-only 0x0 0x3 COMP0_MASKED Logical and of corresponding request and mask bits. [0:0] read-only COMP1_MASKED Logical and of corresponding request and mask bits. [1:1] read-only OA0_SW Opamp0 switch control 0x80 32 read-write 0x0 0x24410D OA0P_A00 Opamp0 positive terminal amuxbusa [0:0] read-write OA0P_A20 Opamp0 positive terminal P0 [2:2] read-write OA0P_A30 Opamp0 positive terminal ctbbus0 [3:3] read-write OA0M_A11 Opamp0 negative terminal P1 [8:8] read-write OA0M_A81 Opamp0 negative terminal Opamp0 output [14:14] read-write OA0O_D51 Opamp0 output sarbus0 (ctbbus2 in CTB) [18:18] read-write OA0O_D81 Opamp0 output switch to short 1x with 10x drive [21:21] read-write OA0_SW_CLEAR Opamp0 switch control clear 0x84 32 read-write 0x0 0x24410D OA0P_A00 see corresponding bit in OA0_SW [0:0] read-write OA0P_A20 see corresponding bit in OA0_SW [2:2] read-write OA0P_A30 see corresponding bit in OA0_SW [3:3] read-write OA0M_A11 see corresponding bit in OA0_SW [8:8] read-write OA0M_A81 see corresponding bit in OA0_SW [14:14] read-write OA0O_D51 see corresponding bit in OA0_SW [18:18] read-write OA0O_D81 see corresponding bit in OA0_SW [21:21] read-write OA1_SW Opamp1 switch control 0x88 32 read-write 0x0 0x2C4193 OA1P_A03 Opamp1 positive terminal amuxbusb [0:0] read-write OA1P_A13 Opamp1 positive terminal P5 [1:1] read-write OA1P_A43 Opamp1 positive terminal ctbbus1 [4:4] read-write OA1P_A73 Opamp1 positive terminal to vref1 [7:7] read-write OA1M_A22 Opamp1 negative terminal P4 [8:8] read-write OA1M_A82 Opamp1 negative terminal Opamp1 output [14:14] read-write OA1O_D52 Opamp1 output sarbus0 (ctbbus2 in CTB) [18:18] read-write OA1O_D62 Opamp1 output sarbus1 (ctbbus3 in CTB) [19:19] read-write OA1O_D82 Opamp1 output switch to short 1x with 10x drive [21:21] read-write OA1_SW_CLEAR Opamp1 switch control clear 0x8C 32 read-write 0x0 0x2C4193 OA1P_A03 see corresponding bit in OA1_SW [0:0] read-write OA1P_A13 see corresponding bit in OA1_SW [1:1] read-write OA1P_A43 see corresponding bit in OA1_SW [4:4] read-write OA1P_A73 see corresponding bit in OA1_SW [7:7] read-write OA1M_A22 see corresponding bit in OA1_SW [8:8] read-write OA1M_A82 see corresponding bit in OA1_SW [14:14] read-write OA1O_D52 see corresponding bit in OA1_SW [18:18] read-write OA1O_D62 see corresponding bit in OA1_SW [19:19] read-write OA1O_D82 see corresponding bit in OA1_SW [21:21] read-write CTD_SW CTDAC connection switch control 0xA0 32 read-write 0x0 0xF732 CTDD_CRD CTDAC Reference opamp output to ctdrefdrive [1:1] read-write CTDS_CRS ctdrefsense to opamp input [4:4] read-write CTDS_COR ctdvout to opamp input [5:5] read-write CTDO_C6H P6 pin to Hold capacitor [8:8] read-write CTDO_COS ctdvout to Hold capacitor (Sample switch). Note this switch will temporarily be opened for deglitching if CTDAC.DEGLITCH_COS is set [9:9] read-write CTDH_COB Drive the CTDAC output with CTBM 1x output during hold mode in Sample and Hold operation [10:10] read-write CTDH_CHD Hold capacitor connect [12:12] read-write CTDH_CA0 Hold capacitor to opamp input [13:13] read-write CTDH_CIS Hold capacitor isolation (from all the other switches) [14:14] read-write CTDH_ILR Hold capacitor leakage reduction (drive other side of CIS to capacitor voltage) [15:15] read-write CTD_SW_CLEAR CTDAC connection switch control clear 0xA4 32 read-write 0x0 0xF732 CTDD_CRD see corresponding bit in CTD_SW [1:1] read-write CTDS_CRS see corresponding bit in CTD_SW [4:4] read-write CTDS_COR see corresponding bit in CTD_SW [5:5] read-write CTDO_C6H see corresponding bit in CTD_SW [8:8] read-write CTDO_COS see corresponding bit in CTD_SW [9:9] read-write CTDH_COB see corresponding bit in CTD_SW [10:10] read-write CTDH_CHD see corresponding bit in CTD_SW [12:12] read-write CTDH_CA0 see corresponding bit in CTD_SW [13:13] read-write CTDH_CIS see corresponding bit in CTD_SW [14:14] read-write CTDH_ILR see corresponding bit in CTD_SW [15:15] read-write CTB_SW_DS_CTRL CTB bus switch control 0xC0 32 read-write 0x0 0x80000C00 P2_DS_CTRL23 for P22, D51 (dsi_out[2]) [10:10] read-write P3_DS_CTRL23 for P33, D52, D62 (dsi_out[3]) [11:11] read-write CTD_COS_DS_CTRL Hold capacitor Sample switch (COS) [31:31] read-write CTB_SW_SQ_CTRL CTB bus switch Sar Sequencer control 0xC4 32 read-write 0x0 0xC00 P2_SQ_CTRL23 for D51 [10:10] read-write P3_SQ_CTRL23 for D52, D62 [11:11] read-write CTB_SW_STATUS CTB bus switch control status 0xC8 32 read-only 0x0 0xF0000000 OA0O_D51_STAT see OA0O_D51 bit in OA0_SW [28:28] read-only OA1O_D52_STAT see OA1O_D52 bit in OA1_SW [29:29] read-only OA1O_D62_STAT see OA1O_D62 bit in OA1_SW [30:30] read-only CTD_COS_STAT see COS bit in CTD_SW [31:31] read-only OA0_OFFSET_TRIM Opamp0 trim control 0xF00 32 read-write 0x0 0x3F OA0_OFFSET_TRIM Opamp0 offset trim [5:0] read-write OA0_SLOPE_OFFSET_TRIM Opamp0 trim control 0xF04 32 read-write 0x0 0x3F OA0_SLOPE_OFFSET_TRIM Opamp0 slope offset drift trim [5:0] read-write OA0_COMP_TRIM Opamp0 trim control 0xF08 32 read-write 0x0 0x3 OA0_COMP_TRIM Opamp0 Compensation Capacitor Trim. Value depends on the drive strength setting - 1x mode: set to 01; 10x mode: set to 11 [1:0] read-write OA1_OFFSET_TRIM Opamp1 trim control 0xF0C 32 read-write 0x0 0x3F OA1_OFFSET_TRIM Opamp1 offset trim [5:0] read-write OA1_SLOPE_OFFSET_TRIM Opamp1 trim control 0xF10 32 read-write 0x0 0x3F OA1_SLOPE_OFFSET_TRIM Opamp1 slope offset drift trim [5:0] read-write OA1_COMP_TRIM Opamp1 trim control 0xF14 32 read-write 0x0 0x3 OA1_COMP_TRIM Opamp1 Compensation Capacitor Trim. Value depends on the drive strength setting - 1x mode: set to 01; 10x mode: set to 11 [1:0] read-write CTDAC0 Continuous Time DAC CTDAC 0x41140000 0 65536 registers CTDAC_CTRL Global CTDAC control 0x0 32 read-write 0x0 0xFBC0033F DEGLITCH_CNT To prevent glitches after VALUE changes from propagating the output switch can be opened for DEGLITCH_CNT+1 clk_peri clock cycles. [5:0] read-write DEGLITCH_CO6 Force CTDAC.CO6 switch open after each VALUE change for the set number of clock cycles. [8:8] read-write DEGLITCH_COS Force CTB.COS switch open after each VALUE change for the set number of clock cycles. [9:9] read-write OUT_EN Output enable, intended to be used during the Hold phase of the Sample and Hold when power cycling : 0: output disabled, the output is either: - Tri-state (DISABLED_MODE=0) - or Vssa (DISABLED_MODE=1 && CTDAC_RANGE=0) - or Vref (DISABLED_MODE=1 && CTDAC_RANGE=1) 1: output enabled, CTDAC output drives the programmed VALUE [22:22] read-write CTDAC_RANGE By closing the bottom switch in the R2R network the output is lifted by one LSB, effectively adding 1 0: Range is [0, 4095] * Vref / 4096 1: Range is [1, 4096] * Vref / 4096 [23:23] read-write CTDAC_MODE DAC mode, this determines the Value decoding [25:24] read-write UNSIGNED12 Unsigned 12-bit VDAC, i.e. no value decoding. 0 VIRT_SIGNED12 Virtual signed 12-bits' VDAC. Value decoding: add 0x800 to the 12-bit Value (=invert MSB), to convert the lowest signed number 0x800 to the lowest unsigned number 0x000. This is the same as the SAR handles 12-bit 'virtual' signed numbers. 1 RSVD2 N/A 2 RSVD3 N/A 3 DISABLED_MODE Select the output value when the output is disabled (OUT_EN=0) (for risk mitigation) 0: Tri-state CTDAC output when disabled 1: output Vssa or Vref when disabled (see OUT_EN description) [27:27] read-write DSI_STROBE_EN DSI strobe input Enable. This enables CTDAC updates to be further throttled by DSI. 0: Ignore DSI strobe input 1: Only do a CTDAC update if alllowed by the DSI stobe (throttle), see below for level or edge [28:28] read-write DSI_STROBE_LEVEL Select level or edge detect for DSI strobe - 0: DSI strobe signal is a pulse input, after a positive edge is detected on the DSI strobe signal the next DAC value update is done on the next CTDAC clock - 1: DSI strobe signal is a level input, as long as the DSI strobe signal remains high the CTDAC will do a next DAC value update on each CTDAC clock. [29:29] read-write DEEPSLEEP_ON - 0: CTDAC IP disabled off during DeepSleep power mode - 1: CTDAC IP remains enabled during DeepSleep power mode (if ENABLED=1) [30:30] read-write ENABLED 0: CTDAC IP disabled (put analog in power down, open all switches) 1: CTDAC IP enabled [31:31] read-write INTR Interrupt request register 0x20 32 read-write 0x0 0x1 VDAC_EMPTY VDAC Interrupt: hardware sets this interrupt when VDAC next value field is empty, i.e. was copied to the current VALUE. Write with '1' to clear bit. [0:0] read-write INTR_SET Interrupt request set register 0x24 32 read-write 0x0 0x1 VDAC_EMPTY_SET Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write INTR_MASK Interrupt request mask 0x28 32 read-write 0x0 0x1 VDAC_EMPTY_MASK Mask bit for corresponding bit in interrupt request register. [0:0] read-write INTR_MASKED Interrupt request masked 0x2C 32 read-only 0x0 0x1 VDAC_EMPTY_MASKED Logical and of corresponding request and mask bits. [0:0] read-only CTDAC_SW CTDAC switch control 0xB0 32 read-write 0x0 0x101 CTDD_CVD VDDA supply to ctdrefdrive [0:0] read-write CTDO_CO6 ctdvout to P6 pin. Note this switch will temporarily be opened for deglitching if DEGLITCH_CO6 is set [8:8] read-write CTDAC_SW_CLEAR CTDAC switch control clear 0xB4 32 read-write 0x0 0x101 CTDD_CVD see corresponding bit in CTD_SW [0:0] read-write CTDO_CO6 see corresponding bit in CTD_SW [8:8] read-write CTDAC_VAL DAC Value 0x100 32 read-write 0x0 0xFFF VALUE Value, in CTDAC_MODE 1 this value is decoded [11:0] read-write CTDAC_VAL_NXT Next DAC value (double buffering) 0x104 32 read-write 0x0 0xFFF VALUE Next value fpr CTDAC_VAL.VALUE [11:0] read-write SAR SAR ADC with Sequencer 0x411D0000 0 65536 registers CTRL Analog control register. 0x0 32 read-write 0x10000000 0xFF3FEEF7 PWR_CTRL_VREF VREF buffer low power mode. [2:0] read-write PWR_100 full power (100 percent) (default), bypass cap, max clk_sar is 18MHz. 0 PWR_80 80 percent power 1 PWR_60 60 percent power 2 PWR_50 50 percent power 3 PWR_40 40 percent power 4 PWR_30 30 percent power 5 PWR_20 20 percent power 6 PWR_10 10 percent power 7 VREF_SEL SARADC internal VREF selection. [6:4] read-write VREF0 VREF0 from PRB (VREF buffer on) 0 VREF1 VREF1 from PRB (VREF buffer on) 1 VREF2 VREF2 from PRB (VREF buffer on) 2 VREF_AROUTE VREF from AROUTE (VREF buffer on) 3 VBGR 1.024V from BandGap (VREF buffer on) 4 VREF_EXT External precision Vref direct from a pin (low impedance path). 5 VDDA_DIV_2 Vdda/2 (VREF buffer on) 6 VDDA Vdda. 7 VREF_BYP_CAP_EN VREF bypass cap enable for when VREF buffer is on [7:7] read-write NEG_SEL SARADC internal NEG selection for Single ended conversion [11:9] read-write VSSA_KELVIN NEG input of SARADC is connected to 'vssa_kelvin', gives more precision around zero. Note this opens both SARADC internal switches, therefore use this value to insert a break-before-make cycle on those switches when SWITCH_DISABLE is high. 0 ART_VSSA NEG input of SARADC is connected to VSSA in AROUTE close to the SARADC 1 P1 NEG input of SARADC is connected to P1 pin of SARMUX 2 P3 NEG input of SARADC is connected to P3 pin of SARMUX 3 P5 NEG input of SARADC is connected to P5 pin of SARMUX 4 P7 NEG input of SARADC is connected to P7 pin of SARMUX 5 ACORE NEG input of SARADC is connected to an ACORE in AROUTE 6 VREF NEG input of SARADC is shorted with VREF input of SARADC. 7 SAR_HW_CTRL_NEGVREF Hardware control: 0=only firmware control, 1=hardware control masked by firmware setting for VREF to NEG switch. [13:13] read-write COMP_DLY Set the comparator latch delay in accordance with SAR conversion rate [15:14] read-write D2P5 2.5ns delay, use this for 2.5Msps 0 D4 4.0ns delay, use this for 2.0Msps 1 D10 10ns delay, use this for 1.5Msps 2 D12 12ns delay, use this for 1.0Msps or less 3 SPARE Spare controls, not yet designated, for late changes done with an ECO [19:16] read-write BOOSTPUMP_EN deprecated [20:20] read-write REFBUF_EN For normal ADC operation this bit must be set, for all reference choices - internal, external or vdda based reference. Setting this bit is critical to proper function of switches inside SARREF block. [21:21] read-write COMP_PWR Comparator power mode. (Sample rate TBD) [26:24] read-write P100 Power = 100 percent, use this for >2000Ksps 0 P80 Power = 80 percent, use this for 1500-2000Ksps 1 P60 Power = 60 percent, use this for 1000-1500Ksps 2 P50 Power = 50 percent, use this for 500-1000Ksps 3 P40 Power = 40 percent, use this for 250-500Ksps 4 P30 Power = 30 percent, use this for 100-250Ksps 5 P20 Power = 20 percent, use this for 100-250Ksps (TBD!) 6 P10 Power = 10 percent, use this for <100Ksps 7 DEEPSLEEP_ON - 0: SARMUX IP disabled off during DeepSleep power mode - 1: SARMUX IP remains enabled during DeepSleep power mode (if ENABLED=1) [27:27] read-write DSI_SYNC_CONFIG - 0: bypass clock domain synchronisation of the DSI config signals. - 1: synchronize the DSI config signals to peripheral clock domain. [28:28] read-write DSI_MODE SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1) - 0: Normal mode, SAR sequencer operates according to CHAN_EN enables and CHAN_CONFIG channel configurations - 1: CHAN_EN, INJ_START_EN and channel configurations in CHAN_CONFIG and INJ_CHAN_CONFIG are ignored [29:29] read-write SWITCH_DISABLE Disable SAR sequencer from enabling routing switches (note DSI and firmware can always close switches independent of this control) - 0: Normal mode, SAR sequencer changes switches according to pin address in channel configurations - 1: Switches disabled, SAR sequencer does not enable any switches, it is the responsibility of the firmware or UDBs (through DSI) to set the switches to route the signal to be converted through the SARMUX [30:30] read-write ENABLED - 0: SAR IP disabled (put analog in power down and stop clocks), also can clear FW_TRIGGER and INJ_START_EN (if not tailgaiting) on write. - 1: SAR IP enabled. [31:31] read-write SAMPLE_CTRL Sample control register. 0x4 32 read-write 0x80008 0xDFCF01FE LEFT_ALIGN Left align data in data[15:0], default data is right aligned in data[11:0], with sign extension to 16 bits if the channel is differential. [1:1] read-write SINGLE_ENDED_SIGNED Output data from a single ended conversion as a signed value [2:2] read-write UNSIGNED Default: result data is unsigned (zero extended if needed) 0 SIGNED result data is signed (sign extended if needed) 1 DIFFERENTIAL_SIGNED Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NEG_ADDR_EN is set to 1 [3:3] read-write UNSIGNED result data is unsigned (zero extended if needed) 0 SIGNED Default: result data is signed (sign extended if needed) 1 AVG_CNT Averaging Count for channels that have averaging enabled (AVG_EN). A channel will be sampled (1<<(AVG_CNT+1)) = [2..256] times. - In ACCUNDUMP mode (1st order accumulate and dump filter) a channel will be sampled back to back, the average result is calculated and stored and then the next enabled channel is sampled. If shifting is not enabled (AVG_SHIFT=0) then the result is forced to shift right so that is fits in 16 bits, so right shift is done by max(0,AVG_CNT-3). - In INTERLEAVED mode one sample is taken per triggered scan, only in the scan where the final averaging count is reached a valid average is calculated and stored in the RESULT register (by definition the same scan for all the channels that have averaging enabled). In all other scans the RESULT register for averaged channels will have an invalid result and the intermediate accumulated value is stored in the 16-bit WORK register. In this mode make sure that the averaging count is low enough to ensure that the intermediate value does not exceed 16-bits otherwise the MSBs will be lost. So for a 12-bit resolution the averaging count should be set to 16 or less (AVG_CNT=<3). [6:4] read-write AVG_SHIFT Averaging shifting: after averaging the result is shifted right to fit in 12 bits. [7:7] read-write AVG_MODE Averaging mode, in DSI mode this bit is ignored and only AccuNDump mode is available. [8:8] read-write ACCUNDUMP Accumulate and Dump (1st order accumulate and dump filter): a channel will be sampled back to back and averaged 0 INTERLEAVED Interleaved: Each scan (trigger) one sample is taken per channel and averaged over several scans. 1 CONTINUOUS - 0: Wait for next FW_TRIGGER (one shot) or hardware trigger (e.g. from TPWM for periodic triggering) before scanning enabled channels. - 1: Continuously scan enabled channels, ignore triggers. [16:16] read-write DSI_TRIGGER_EN - 0: firmware trigger only: disable hardware trigger tr_sar_in. - 1: enable hardware trigger tr_sar_in (e.g. from TCPWM, GPIO or UDB). [17:17] read-write DSI_TRIGGER_LEVEL - 0: trigger signal is a pulse input, a positive edge detected on the trigger signal triggers a new scan. - 1: trigger signal is a level input, as long as the trigger signal remains high the SAR will do continuous scans. [18:18] read-write DSI_SYNC_TRIGGER - 0: bypass clock domain synchronisation of the trigger signal. - 1: synchronize the trigger signal to the SAR clock domain, if needed an edge detect is done in the peripheral clock domain. [19:19] read-write UAB_SCAN_MODE Select whether UABs are scheduled or unscheduled. When no UAB is scanned this selection is ignored. [22:22] read-write UNSCHEDULED Unscheduled UABs: one or more of the UABs scanned by the SAR is not scheduled, for each channel that scans a UAB the SAR will wait for a positive edge on the trigger output of that UAB. Caveat: in this mode the length of SAR scan can be variable. 0 SCHEDULED Scheduled UABs: All UABs scanned by the SAR are assumed to be properly scheduled, i.e. their output is assumed to be valid when sampled by the SAR and the SAR does not wait. In this mode the length of the SAR scan is constant. This mode requires that the SAR scans strictly periodically, i.e. the SAR has to either run continuously or has to be triggered by a periodic hardware trigger (TCPWM or UDB timer). It also requires that the end of the UAB valid phase is precisely aligned with the end of the SAR sample period (using UAB.STARTUP_DELAY). Normally this scheduling is done by Creator. 1 REPEAT_INVALID For unscheduled UAB_SCAN_MODE only, do the following if an invalid sample is received: - 0: use the last known valid sample for that channel and clear the NEWVALUE flag - 1: repeat the conversions until a valid sample is received (caveat: could be never if the UAB valid window is incorrectly schedule w.r.t. SAR sampling) [23:23] read-write VALID_SEL Static UAB Valid select 0=UAB0 half 0 Valid output 1=UAB0 half 1 Valid output 2=UAB1 half 0 Valid output 3=UAB1 half 1 Valid output 4=UAB2 half 0 Valid output 5=UAB2 half 1 Valid output 6=UAB3 half 0 Valid output 7=UAB3 half 1 Valid output [26:24] read-write VALID_SEL_EN Enable static UAB Valid selection (override Hardware) [27:27] read-write VALID_IGNORE Ignore UAB valid signal, including the dynamic/Hardware from AROUTE and the static Valid selection from the VALID_SEL fields above [28:28] read-write TRIGGER_OUT_EN SAR output trigger enable (used for UAB synchronization). To ensure multiple UABs starting at the same trigger it is recommended to use this bit to temporarily disable the trigger output until all those UABs are set to run (UAB.SRAM_CTRL.RUN=1). [30:30] read-write EOS_DSI_OUT_EN Enable to output EOS_INTR to DSI. When enabled each time EOS_INTR is set by the hardware also a trigger pulse is send on the tr_sar_out signal. [31:31] read-write SAMPLE_TIME01 Sample time specification ST0 and ST1 0x10 32 read-write 0x30003 0x3FF03FF SAMPLE_TIME0 Sample time0 (aperture) in ADC clock cycles. Note that actual sample time is one clock less than specified here. The minimum sample time is 167ns, which is 3.0 cycles (4 in this field) with an 18MHz clock. Minimum legal value in this register is 2. [9:0] read-write SAMPLE_TIME1 Sample time1 [25:16] read-write SAMPLE_TIME23 Sample time specification ST2 and ST3 0x14 32 read-write 0x30003 0x3FF03FF SAMPLE_TIME2 Sample time2 [9:0] read-write SAMPLE_TIME3 Sample time3 [25:16] read-write RANGE_THRES Global range detect threshold register. 0x18 32 read-write 0x0 0xFFFFFFFF RANGE_LOW Low threshold for range detect. [15:0] read-write RANGE_HIGH High threshold for range detect. [31:16] read-write RANGE_COND Global range detect mode register. 0x1C 32 read-write 0x0 0xC0000000 RANGE_COND Range condition select. [31:30] read-write BELOW result < RANGE_LOW 0 INSIDE RANGE_LOW <= result < RANGE_HIGH 1 ABOVE RANGE_HIGH <= result 2 OUTSIDE result < RANGE_LOW || RANGE_HIGH <= result 3 CHAN_EN Enable bits for the channels 0x20 32 read-write 0x0 0xFFFF CHAN_EN Channel enable. - 0: the corresponding channel is disabled. - 1: the corresponding channel is enabled, it will be included in the next scan. [15:0] read-write START_CTRL Start control register (firmware trigger). 0x24 32 read-write 0x0 0x1 FW_TRIGGER When firmware writes a 1 here it will trigger the next scan of enabled channels, hardware clears this bit when the scan started with this trigger is completed. If scanning continuously the trigger is ignored and hardware clears this bit after the next scan is done. This bit is also cleared when the SAR is disabled. [0:0] read-write 16 4 CHAN_CONFIG[%s] Channel configuration register. 0x80 32 read-write 0x0 0x81773577 POS_PIN_ADDR Address of the pin to be sampled by this channel (connected to Vplus) [2:0] read-write POS_PORT_ADDR Address of the port that contains the pin to be sampled by this channel (connected to Vplus) [6:4] read-write SARMUX SARMUX pins. 0 CTB0 CTB0 1 CTB1 CTB1 2 CTB2 CTB2 3 CTB3 CTB3 4 AROUTE_VIRT2 AROUTE virtual port2 (VPORT2) 5 AROUTE_VIRT1 AROUTE virtual port1 (VPORT1) 6 SARMUX_VIRT SARMUX virtual port (VPORT0) 7 DIFFERENTIAL_EN Differential enable for this channel. If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored). [8:8] read-write AVG_EN Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s) [10:10] read-write SAMPLE_TIME_SEL Sample time select: select which of the 4 global sample times to use for this channel [13:12] read-write NEG_PIN_ADDR Address of the neg pin to be sampled by this channel. [18:16] read-write NEG_PORT_ADDR Address of the neg port that contains the pin to be sampled by this channel. [22:20] read-write SARMUX SARMUX pins. 0 AROUTE_VIRT2 AROUTE virtual port2 (VPORT2) 5 AROUTE_VIRT1 AROUTE virtual port1 (VPORT1) 6 SARMUX_VIRT SARMUX virtual port (VPORT0) 7 NEG_ADDR_EN 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin. [24:24] read-write DSI_OUT_EN DSI data output enable for this channel. - 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. - 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formating), together with the channel number, is sent out on the DSI communication channel for processing in UDBs. [31:31] read-write 16 4 CHAN_WORK[%s] Channel working data register 0x100 32 read-only 0x0 0x88000000 WORK SAR conversion working data of the channel. The data is written here right after sampling this channel. [15:0] read-only CHAN_WORK_NEWVALUE_MIR mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register [27:27] read-only CHAN_WORK_UPDATED_MIR mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register [31:31] read-only 16 4 CHAN_RESULT[%s] Channel result data register 0x180 32 read-only 0x0 0xE8000000 RESULT SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. [15:0] read-only CHAN_RESULT_NEWVALUE_MIR mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register [27:27] read-only SATURATE_INTR_MIR mirror bit of corresponding bit in SAR_SATURATE_INTR register [29:29] read-only RANGE_INTR_MIR mirror bit of corresponding bit in SAR_RANGE_INTR register [30:30] read-only CHAN_RESULT_UPDATED_MIR mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register [31:31] read-only CHAN_WORK_UPDATED Channel working data register 'updated' bits 0x200 32 read-only 0x0 0xFFFF CHAN_WORK_UPDATED If set the corresponding WORK register was updated, i.e. was already sampled during the current scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging. [15:0] read-only CHAN_RESULT_UPDATED Channel result data register 'updated' bits 0x204 32 read-only 0x0 0xFFFF CHAN_RESULT_UPDATED If set the corresponding RESULT register was updated, i.e. was sampled during the previous scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging. [15:0] read-only CHAN_WORK_NEWVALUE Channel working data register 'new value' bits 0x208 32 read-only 0x0 0xFFFF CHAN_WORK_NEWVALUE If set the corresponding WORK data received a new value, i.e. was already sampled during the current scan and data was valid. In case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid. In case of averaging this New Value bit is an OR of all the valid bits received by each conversion. [15:0] read-only CHAN_RESULT_NEWVALUE Channel result data register 'new value' bits 0x20C 32 read-only 0x0 0xFFFF CHAN_RESULT_NEWVALUE If set the corresponding RESULT data received a new value, i.e. was sampled during the last scan and data was valid. In case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid. In case of averaging this New Value bit is an OR of all the valid bits received by each conversion. [15:0] read-only INTR Interrupt request register. 0x210 32 read-write 0x0 0xFF EOS_INTR End Of Scan Interrupt: hardware sets this interrupt after completing a scan of all the enabled channels. Write with '1' to clear bit. [0:0] read-write OVERFLOW_INTR Overflow Interrupt: hardware sets this interrupt when it sets a new EOS_INTR while that bit was not yet cleared by the firmware. Write with '1' to clear bit. [1:1] read-write FW_COLLISION_INTR Firmware Collision Interrupt: hardware sets this interrupt when FW_TRIGGER is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the FW_TRIGGER has been completed, i.e. not when the preceeding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with '1' to clear bit. [2:2] read-write DSI_COLLISION_INTR DSI Collision Interrupt: hardware sets this interrupt when the DSI trigger signal is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the DSI trigger has been completed, i.e. not when the preceeding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with '1' to clear bit. [3:3] read-write INJ_EOC_INTR Injection End of Conversion Interrupt: hardware sets this interrupt after completing the conversion for the injection channel (irrespective of if tailgating was used). Write with '1' to clear bit. [4:4] read-write INJ_SATURATE_INTR Injection Saturation Interrupt: hardware sets this interrupt if an injection conversion result (before averaging) is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit. [5:5] read-write INJ_RANGE_INTR Injection Range detect Interrupt: hardware sets this interrupt if the injection conversion result (after averaging) met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit. [6:6] read-write INJ_COLLISION_INTR Injection Collision Interrupt: hardware sets this interrupt when the injection trigger signal is asserted (INJ_START_EN==1 && INJ_TAILGATING==0) while the SAR is BUSY. Raising this interrupt is delayed to when the sampling of the injection channel has been completed, i.e. not when the preceeding scan with which this trigger collided is completed. When this interrupt is set it implies that the injection channel was sampled later than was intended. Write with '1' to clear bit. [7:7] read-write INTR_SET Interrupt set request register 0x214 32 read-write 0x0 0xFF EOS_SET Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write OVERFLOW_SET Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write FW_COLLISION_SET Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write DSI_COLLISION_SET Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write INJ_EOC_SET Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write INJ_SATURATE_SET Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write INJ_RANGE_SET Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write INJ_COLLISION_SET Write with '1' to set corresponding bit in interrupt request register. [7:7] read-write INTR_MASK Interrupt mask register. 0x218 32 read-write 0x0 0xFF EOS_MASK Mask bit for corresponding bit in interrupt request register. [0:0] read-write OVERFLOW_MASK Mask bit for corresponding bit in interrupt request register. [1:1] read-write FW_COLLISION_MASK Mask bit for corresponding bit in interrupt request register. [2:2] read-write DSI_COLLISION_MASK Mask bit for corresponding bit in interrupt request register. [3:3] read-write INJ_EOC_MASK Mask bit for corresponding bit in interrupt request register. [4:4] read-write INJ_SATURATE_MASK Mask bit for corresponding bit in interrupt request register. [5:5] read-write INJ_RANGE_MASK Mask bit for corresponding bit in interrupt request register. [6:6] read-write INJ_COLLISION_MASK Mask bit for corresponding bit in interrupt request register. [7:7] read-write INTR_MASKED Interrupt masked request register 0x21C 32 read-only 0x0 0xFF EOS_MASKED Logical and of corresponding request and mask bits. [0:0] read-only OVERFLOW_MASKED Logical and of corresponding request and mask bits. [1:1] read-only FW_COLLISION_MASKED Logical and of corresponding request and mask bits. [2:2] read-only DSI_COLLISION_MASKED Logical and of corresponding request and mask bits. [3:3] read-only INJ_EOC_MASKED Logical and of corresponding request and mask bits. [4:4] read-only INJ_SATURATE_MASKED Logical and of corresponding request and mask bits. [5:5] read-only INJ_RANGE_MASKED Logical and of corresponding request and mask bits. [6:6] read-only INJ_COLLISION_MASKED Logical and of corresponding request and mask bits. [7:7] read-only SATURATE_INTR Saturate interrupt request register. 0x220 32 read-write 0x0 0xFFFF SATURATE_INTR Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit. [15:0] read-write SATURATE_INTR_SET Saturate interrupt set request register 0x224 32 read-write 0x0 0xFFFF SATURATE_SET Write with '1' to set corresponding bit in interrupt request register. [15:0] read-write SATURATE_INTR_MASK Saturate interrupt mask register. 0x228 32 read-write 0x0 0xFFFF SATURATE_MASK Mask bit for corresponding bit in interrupt request register. [15:0] read-write SATURATE_INTR_MASKED Saturate interrupt masked request register 0x22C 32 read-only 0x0 0xFFFF SATURATE_MASKED Logical and of corresponding request and mask bits. [15:0] read-only RANGE_INTR Range detect interrupt request register. 0x230 32 read-write 0x0 0xFFFF RANGE_INTR Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit. [15:0] read-write RANGE_INTR_SET Range detect interrupt set request register 0x234 32 read-write 0x0 0xFFFF RANGE_SET Write with '1' to set corresponding bit in interrupt request register. [15:0] read-write RANGE_INTR_MASK Range detect interrupt mask register. 0x238 32 read-write 0x0 0xFFFF RANGE_MASK Mask bit for corresponding bit in interrupt request register. [15:0] read-write RANGE_INTR_MASKED Range interrupt masked request register 0x23C 32 read-only 0x0 0xFFFF RANGE_MASKED Logical and of corresponding request and mask bits. [15:0] read-only INTR_CAUSE Interrupt cause register 0x240 32 read-only 0x0 0xC00000FF EOS_MASKED_MIR Mirror copy of corresponding bit in SAR_INTR_MASKED [0:0] read-only OVERFLOW_MASKED_MIR Mirror copy of corresponding bit in SAR_INTR_MASKED [1:1] read-only FW_COLLISION_MASKED_MIR Mirror copy of corresponding bit in SAR_INTR_MASKED [2:2] read-only DSI_COLLISION_MASKED_MIR Mirror copy of corresponding bit in SAR_INTR_MASKED [3:3] read-only INJ_EOC_MASKED_MIR Mirror copy of corresponding bit in SAR_INTR_MASKED [4:4] read-only INJ_SATURATE_MASKED_MIR Mirror copy of corresponding bit in SAR_INTR_MASKED [5:5] read-only INJ_RANGE_MASKED_MIR Mirror copy of corresponding bit in SAR_INTR_MASKED [6:6] read-only INJ_COLLISION_MASKED_MIR Mirror copy of corresponding bit in SAR_INTR_MASKED [7:7] read-only SATURATE_MASKED_RED Reduction OR of all SAR_SATURATION_INTR_MASKED bits [30:30] read-only RANGE_MASKED_RED Reduction OR of all SAR_RANGE_INTR_MASKED bits [31:31] read-only INJ_CHAN_CONFIG Injection channel configuration register. 0x280 32 read-write 0x0 0xC0003577 INJ_PIN_ADDR Address of the pin to be sampled by this injection channel. If differential is enabled then INJ_PIN_ADDR[0] is ignored and considered to be 0, i.e. INJ_PIN_ADDR points to the even pin of a pin pair. [2:0] read-write INJ_PORT_ADDR Address of the port that contains the pin to be sampled by this channel. [6:4] read-write SARMUX SARMUX pins. 0 CTB0 CTB0 1 CTB1 CTB1 2 CTB2 CTB2 3 CTB3 CTB3 4 AROUTE_VIRT AROUTE virtual port 6 SARMUX_VIRT SARMUX virtual port 7 INJ_DIFFERENTIAL_EN Differential enable for this channel. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (INJ_PIN_ADDR[0] is ignored). [8:8] read-write INJ_AVG_EN Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s) [10:10] read-write INJ_SAMPLE_TIME_SEL Injection sample time select: select which of the 4 global sample times to use for this channel [13:12] read-write INJ_TAILGATING Injection channel tailgating. - 0: no tailgating for this channel, SAR is immediately triggered when the INJ_START_EN bit is set. - 1: injection channel tailgating. The addressed pin is sampled after the next trigger and after all enabled channels have been scanned. [30:30] read-write INJ_START_EN Set by firmware to enable the injection channel. If INJ_TAILGATING is not set this bit also functions as trigger for this channel. Cleared by hardware after this channel has been sampled (i.e. this channel is always one shot even if CONTINUOUS is set). Also cleared if the SAR is disabled. [31:31] read-write INJ_RESULT Injection channel result register 0x290 32 read-only 0x0 0xF8000000 INJ_RESULT SAR conversion result of the channel. [15:0] read-only INJ_NEWVALUE The data in this register received a new value (only relevant for UAB, this bit shows the value of the UAB valid bit) [27:27] read-only INJ_COLLISION_INTR_MIR mirror bit of corresponding bit in SAR_INTR register [28:28] read-only INJ_SATURATE_INTR_MIR mirror bit of corresponding bit in SAR_INTR register [29:29] read-only INJ_RANGE_INTR_MIR mirror bit of corresponding bit in SAR_INTR register [30:30] read-only INJ_EOC_INTR_MIR mirror bit of corresponding bit in SAR_INTR register [31:31] read-only STATUS Current status of internal SAR registers (mostly for debug) 0x2A0 32 read-only 0x0 0xC000001F CUR_CHAN current channel being sampled (channel 16 indicates the injection channel), only valid if BUSY. [4:0] read-only SW_VREF_NEG the current switch status, including DSI and sequencer controls, of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL). [30:30] read-only BUSY If high then the SAR is busy with a conversion. This bit is always high when CONTINUOUS is set. Firmware should wait for this bit to be low before putting the SAR in power down. [31:31] read-only AVG_STAT Current averaging status (for debug) 0x2A4 32 read-only 0x0 0xFF8FFFFF CUR_AVG_ACCU the current value of the averaging accumulator [19:0] read-only INTRLV_BUSY If high then the SAR is in the middle of Interleaved averaging spanning several scans. While this bit is high the Firmware should not make any changes to the configuration registers otherwise some results may be incorrect. Note that the CUR_AVG_CNT status register below gives an indication how many more scans need to be done to complete the Interleaved averaging. This bit can be cleared by changing the averaging mode to ACCUNDUMP or by disabling the SAR. [23:23] read-only CUR_AVG_CNT the current value of the averaging counter. Note that the value shown is updated after the sampling time and therefore runs ahead of the accumulator update. [31:24] read-only MUX_SWITCH0 SARMUX Firmware switch controls 0x300 32 read-write 0x0 0x3FFFFFFF MUX_FW_P0_VPLUS Firmware control: 0=open, 1=close switch between pin P0 and vplus signal. Write with '1' to set bit. [0:0] read-write MUX_FW_P1_VPLUS Firmware control: 0=open, 1=close switch between pin P1 and vplus signal. Write with '1' to set bit. [1:1] read-write MUX_FW_P2_VPLUS Firmware control: 0=open, 1=close switch between pin P2 and vplus signal. Write with '1' to set bit. [2:2] read-write MUX_FW_P3_VPLUS Firmware control: 0=open, 1=close switch between pin P3 and vplus signal. Write with '1' to set bit. [3:3] read-write MUX_FW_P4_VPLUS Firmware control: 0=open, 1=close switch between pin P4 and vplus signal. Write with '1' to set bit. [4:4] read-write MUX_FW_P5_VPLUS Firmware control: 0=open, 1=close switch between pin P5 and vplus signal. Write with '1' to set bit. [5:5] read-write MUX_FW_P6_VPLUS Firmware control: 0=open, 1=close switch between pin P6 and vplus signal. Write with '1' to set bit. [6:6] read-write MUX_FW_P7_VPLUS Firmware control: 0=open, 1=close switch between pin P7 and vplus signal. Write with '1' to set bit. [7:7] read-write MUX_FW_P0_VMINUS Firmware control: 0=open, 1=close switch between pin P0 and vminus signal. Write with '1' to set bit. [8:8] read-write MUX_FW_P1_VMINUS Firmware control: 0=open, 1=close switch between pin P1 and vminus signal. Write with '1' to set bit. [9:9] read-write MUX_FW_P2_VMINUS Firmware control: 0=open, 1=close switch between pin P2 and vminus signal. Write with '1' to set bit. [10:10] read-write MUX_FW_P3_VMINUS Firmware control: 0=open, 1=close switch between pin P3 and vminus signal. Write with '1' to set bit. [11:11] read-write MUX_FW_P4_VMINUS Firmware control: 0=open, 1=close switch between pin P4 and vminus signal. Write with '1' to set bit. [12:12] read-write MUX_FW_P5_VMINUS Firmware control: 0=open, 1=close switch between pin P5 and vminus signal. Write with '1' to set bit. [13:13] read-write MUX_FW_P6_VMINUS Firmware control: 0=open, 1=close switch between pin P6 and vminus signal. Write with '1' to set bit. [14:14] read-write MUX_FW_P7_VMINUS Firmware control: 0=open, 1=close switch between pin P7 and vminus signal. Write with '1' to set bit. [15:15] read-write MUX_FW_VSSA_VMINUS Firmware control: 0=open, 1=close switch between vssa_kelvin and vminus signal. Write with '1' to set bit. [16:16] read-write MUX_FW_TEMP_VPLUS Firmware control: 0=open, 1=close switch between temperature sensor and vplus signal, also powers on the temperature sensor. Write with '1' to set bit. [17:17] read-write MUX_FW_AMUXBUSA_VPLUS Firmware control: 0=open, 1=close switch between amuxbusa and vplus signal. Write with '1' to set bit. [18:18] read-write MUX_FW_AMUXBUSB_VPLUS Firmware control: 0=open, 1=close switch between amuxbusb and vplus signal. Write with '1' to set bit. [19:19] read-write MUX_FW_AMUXBUSA_VMINUS Firmware control: 0=open, 1=close switch between amuxbusa and vminus signal. Write with '1' to set bit. [20:20] read-write MUX_FW_AMUXBUSB_VMINUS Firmware control: 0=open, 1=close switch between amuxbusb and vminus signal. Write with '1' to set bit. [21:21] read-write MUX_FW_SARBUS0_VPLUS Firmware control: 0=open, 1=close switch between sarbus0 and vplus signal. Write with '1' to set bit. [22:22] read-write MUX_FW_SARBUS1_VPLUS Firmware control: 0=open, 1=close switch between sarbus1 and vplus signal. Write with '1' to set bit. [23:23] read-write MUX_FW_SARBUS0_VMINUS Firmware control: 0=open, 1=close switch between sarbus0 and vminus signal. Write with '1' to set bit. [24:24] read-write MUX_FW_SARBUS1_VMINUS Firmware control: 0=open, 1=close switch between sarbus1 and vminus signal. Write with '1' to set bit. [25:25] read-write MUX_FW_P4_COREIO0 Firmware control: 0=open, 1=close switch between P4 and coreio0 signal. Write with '1' to set bit. [26:26] read-write MUX_FW_P5_COREIO1 Firmware control: 0=open, 1=close switch between P5 and coreio1 signal. Write with '1' to set bit. [27:27] read-write MUX_FW_P6_COREIO2 Firmware control: 0=open, 1=close switch between P6 and coreio2 signal. Write with '1' to set bit. [28:28] read-write MUX_FW_P7_COREIO3 Firmware control: 0=open, 1=close switch between P7 and coreio3 signal. Write with '1' to set bit. [29:29] read-write MUX_SWITCH_CLEAR0 SARMUX Firmware switch control clear 0x304 32 read-write 0x0 0x3FFFFFFF MUX_FW_P0_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [0:0] read-write MUX_FW_P1_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [1:1] read-write MUX_FW_P2_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [2:2] read-write MUX_FW_P3_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [3:3] read-write MUX_FW_P4_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [4:4] read-write MUX_FW_P5_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [5:5] read-write MUX_FW_P6_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [6:6] read-write MUX_FW_P7_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [7:7] read-write MUX_FW_P0_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [8:8] read-write MUX_FW_P1_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [9:9] read-write MUX_FW_P2_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [10:10] read-write MUX_FW_P3_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [11:11] read-write MUX_FW_P4_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [12:12] read-write MUX_FW_P5_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [13:13] read-write MUX_FW_P6_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [14:14] read-write MUX_FW_P7_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [15:15] read-write MUX_FW_VSSA_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [16:16] read-write MUX_FW_TEMP_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [17:17] read-write MUX_FW_AMUXBUSA_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [18:18] read-write MUX_FW_AMUXBUSB_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [19:19] read-write MUX_FW_AMUXBUSA_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [20:20] read-write MUX_FW_AMUXBUSB_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [21:21] read-write MUX_FW_SARBUS0_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [22:22] read-write MUX_FW_SARBUS1_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [23:23] read-write MUX_FW_SARBUS0_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [24:24] read-write MUX_FW_SARBUS1_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [25:25] read-write MUX_FW_P4_COREIO0 Write '1' to clear corresponding bit in MUX_SWITCH0 [26:26] read-write MUX_FW_P5_COREIO1 Write '1' to clear corresponding bit in MUX_SWITCH0 [27:27] read-write MUX_FW_P6_COREIO2 Write '1' to clear corresponding bit in MUX_SWITCH0 [28:28] read-write MUX_FW_P7_COREIO3 Write '1' to clear corresponding bit in MUX_SWITCH0 [29:29] read-write MUX_SWITCH_DS_CTRL SARMUX switch DSI control 0x340 32 read-write 0x0 0xCF00FF MUX_DS_CTRL_P0 for P0 switches [0:0] read-write MUX_DS_CTRL_P1 for P1 switches [1:1] read-write MUX_DS_CTRL_P2 for P2 switches [2:2] read-write MUX_DS_CTRL_P3 for P3 switches [3:3] read-write MUX_DS_CTRL_P4 for P4 switches [4:4] read-write MUX_DS_CTRL_P5 for P5 switches [5:5] read-write MUX_DS_CTRL_P6 for P6 switches [6:6] read-write MUX_DS_CTRL_P7 for P7 switches [7:7] read-write MUX_DS_CTRL_VSSA for vssa switch [16:16] read-write MUX_DS_CTRL_TEMP for temp switch [17:17] read-write MUX_DS_CTRL_AMUXBUSA for amuxbusa switch [18:18] read-write MUX_DS_CTRL_AMUXBUSB for amuxbusb switches [19:19] read-write MUX_DS_CTRL_SARBUS0 for sarbus0 switch [22:22] read-write MUX_DS_CTRL_SARBUS1 for sarbus1 switch [23:23] read-write MUX_SWITCH_SQ_CTRL SARMUX switch Sar Sequencer control 0x344 32 read-write 0x0 0xCF00FF MUX_SQ_CTRL_P0 for P0 switches [0:0] read-write MUX_SQ_CTRL_P1 for P1 switches [1:1] read-write MUX_SQ_CTRL_P2 for P2 switches [2:2] read-write MUX_SQ_CTRL_P3 for P3 switches [3:3] read-write MUX_SQ_CTRL_P4 for P4 switches [4:4] read-write MUX_SQ_CTRL_P5 for P5 switches [5:5] read-write MUX_SQ_CTRL_P6 for P6 switches [6:6] read-write MUX_SQ_CTRL_P7 for P7 switches [7:7] read-write MUX_SQ_CTRL_VSSA for vssa switch [16:16] read-write MUX_SQ_CTRL_TEMP for temp switch [17:17] read-write MUX_SQ_CTRL_AMUXBUSA for amuxbusa switch [18:18] read-write MUX_SQ_CTRL_AMUXBUSB for amuxbusb switches [19:19] read-write MUX_SQ_CTRL_SARBUS0 for sarbus0 switch [22:22] read-write MUX_SQ_CTRL_SARBUS1 for sarbus1 switch [23:23] read-write MUX_SWITCH_STATUS SARMUX switch status 0x348 32 read-only 0x0 0x3FFFFFF MUX_FW_P0_VPLUS switch status of corresponding bit in MUX_SWITCH0 [0:0] read-only MUX_FW_P1_VPLUS switch status of corresponding bit in MUX_SWITCH0 [1:1] read-only MUX_FW_P2_VPLUS switch status of corresponding bit in MUX_SWITCH0 [2:2] read-only MUX_FW_P3_VPLUS switch status of corresponding bit in MUX_SWITCH0 [3:3] read-only MUX_FW_P4_VPLUS switch status of corresponding bit in MUX_SWITCH0 [4:4] read-only MUX_FW_P5_VPLUS switch status of corresponding bit in MUX_SWITCH0 [5:5] read-only MUX_FW_P6_VPLUS switch status of corresponding bit in MUX_SWITCH0 [6:6] read-only MUX_FW_P7_VPLUS switch status of corresponding bit in MUX_SWITCH0 [7:7] read-only MUX_FW_P0_VMINUS switch status of corresponding bit in MUX_SWITCH0 [8:8] read-only MUX_FW_P1_VMINUS switch status of corresponding bit in MUX_SWITCH0 [9:9] read-only MUX_FW_P2_VMINUS switch status of corresponding bit in MUX_SWITCH0 [10:10] read-only MUX_FW_P3_VMINUS switch status of corresponding bit in MUX_SWITCH0 [11:11] read-only MUX_FW_P4_VMINUS switch status of corresponding bit in MUX_SWITCH0 [12:12] read-only MUX_FW_P5_VMINUS switch status of corresponding bit in MUX_SWITCH0 [13:13] read-only MUX_FW_P6_VMINUS switch status of corresponding bit in MUX_SWITCH0 [14:14] read-only MUX_FW_P7_VMINUS switch status of corresponding bit in MUX_SWITCH0 [15:15] read-only MUX_FW_VSSA_VMINUS switch status of corresponding bit in MUX_SWITCH0 [16:16] read-only MUX_FW_TEMP_VPLUS switch status of corresponding bit in MUX_SWITCH0 [17:17] read-only MUX_FW_AMUXBUSA_VPLUS switch status of corresponding bit in MUX_SWITCH0 [18:18] read-only MUX_FW_AMUXBUSB_VPLUS switch status of corresponding bit in MUX_SWITCH0 [19:19] read-only MUX_FW_AMUXBUSA_VMINUS switch status of corresponding bit in MUX_SWITCH0 [20:20] read-only MUX_FW_AMUXBUSB_VMINUS switch status of corresponding bit in MUX_SWITCH0 [21:21] read-only MUX_FW_SARBUS0_VPLUS switch status of corresponding bit in MUX_SWITCH0 [22:22] read-only MUX_FW_SARBUS1_VPLUS switch status of corresponding bit in MUX_SWITCH0 [23:23] read-only MUX_FW_SARBUS0_VMINUS switch status of corresponding bit in MUX_SWITCH0 [24:24] read-only MUX_FW_SARBUS1_VMINUS switch status of corresponding bit in MUX_SWITCH0 [25:25] read-only ANA_TRIM0 Analog trim register. 0xF00 32 read-write 0x0 0x3F CAP_TRIM Attenuation cap trimming [4:0] read-write TRIMUNIT Attenuation cap trimming [5:5] read-write ANA_TRIM1 Analog trim register. 0xF04 32 read-write 0x0 0x3F SAR_REF_BUF_TRIM SAR Reference buffer trim [5:0] read-write PASS PASS top-level MMIO (DSABv2, INTR) 0x411F0000 0 65536 registers INTR_CAUSE Interrupt cause register 0x0 32 read-only 0x0 0xFF CTB0_INT CTB0 interrupt pending [0:0] read-only CTB1_INT CTB1 interrupt pending [1:1] read-only CTB2_INT CTB2 interrupt pending [2:2] read-only CTB3_INT CTB3 interrupt pending [3:3] read-only CTDAC0_INT CTDAC0 interrupt pending [4:4] read-only CTDAC1_INT CTDAC1 interrupt pending [5:5] read-only CTDAC2_INT CTDAC2 interrupt pending [6:6] read-only CTDAC3_INT CTDAC3 interrupt pending [7:7] read-only AREF AREF configuration 0x00000E00 AREF_CTRL global AREF control 0x0 32 read-write 0x0 0xF039FFFD AREF_MODE Control bit to trade off AREF settling and noise performance [0:0] read-write NORMAL Nominal noise normal startup mode (meets normal mode settling and noise specifications) 0 FAST_START High noise fast startup mode (meets fast mode settling and noise specifications) 1 AREF_BIAS_SCALE BIAS Current Control for all AREF Amplifiers. (These are risk mitigation bits that should not be touched by the customer: the impact on IDDA/noise/startup still needs to be characterized) 0: 125nA (reduced bias: reduction in total AREF IDDA, higher noise and longer startup times) 1: 250nA ('default' setting to meet bandgap performance (noise/startup) and IDDA specifications) 2: 375nA (increased bias: increase in total AREF IDDA, lower noise and shorter startup times) 3: 500nA (further increased bias: increase in total AREF IDDA, lower noise and shorter startup times) [3:2] read-write AREF_RMB AREF control signals (RMB). Bit 0: Manual VBG startup circuit enable 0: normal VBG startup circuit operation 1: VBG startup circuit is forced 'always on' Bit 1: Manual disable of IPTAT2 DAC 0: normal IPTAT2 DAC operation 1: PTAT2 DAC is disabled while VBG startup is active Bit 2: Manual enable of VBG offset correction DAC 0: normal VBG offset correction DAC operation 1: VBG offset correction DAC is enabled while VBG startup is active [6:4] read-write CTB_IPTAT_SCALE CTB IPTAT current scaler. This bit must be set in order to operate the CTB amplifiers in the lowest power mode. This bit is chip-wide (controls all CTB amplifiers). 0: 1uA 1: 100nA [7:7] read-write CTB_IPTAT_REDIRECT Re-direct the CTB IPTAT output current. This can be used to reduce amplifier bias glitches during power mode transitions (for PSoC4A/B DSAB backwards compatibility). 0: Opamp<n>.IPTAT = AREF.IPTAT and Opamp<n>.IZTAT= AREF.IZTAT 1: Opamp<n>.IPTAT = HiZ and Opamp<n>.IZTAT= AREF.IPTAT *Note that in Deep Sleep, the AREF IZTAT and/or IPTAT currents can be disabled and therefore the corresponding Opamp<n>.IZTAT/IPTAT will be HiZ. [15:8] read-write IZTAT_SEL iztat current select control [16:16] read-write SRSS Use 250nA IZTAT from SRSS 0 LOCAL Use locally generated 250nA 1 CLOCK_PUMP_PERI_SEL CTBm charge pump clock source select. This field has nothing to do with the AREF. 0: Use the dedicated pump clock from SRSS (default) 1: Use one of the CLK_PERI dividers [19:19] read-write VREF_SEL bandgap voltage select control [21:20] read-write SRSS Use 0.8V Vref from SRSS 0 LOCAL Use locally generated Vref 1 EXTERNAL Use externally supplied Vref (aref_ext_vref) 2 DEEPSLEEP_MODE AREF DeepSleep Operation Modes (only applies if DEEPSLEEP_ON = 1) [29:28] read-write OFF All blocks 'OFF' in DeepSleep 0 IPTAT IPTAT bias generator 'ON' in DeepSleep (used for fast AREF wakeup only: IPTAT outputs not available) 1 IPTAT_IZTAT IPTAT bias generator and outputs 'ON' in DeepSleep (used for biasing the CTBm with a PTAT current only in deepsleep) *Note that this mode also requires that the CTB_IPTAT_REDIRECT be set if the CTBm opamp is to operate in DeepSleep 2 IPTAT_IZTAT_VREF IPTAT, VREF, and IZTAT generators 'ON' in DeepSleep. This mode provides identical AREF functionality in DeepSleep as in the Active mode. 3 DEEPSLEEP_ON - 0: AREF IP disabled/off during DeepSleep power mode - 1: AREF IP remains enabled during DeepSleep power mode (if ENABLED=1) [30:30] read-write ENABLED Disable AREF [31:31] read-write VREF_TRIM0 VREF Trim bits 0xF00 32 read-write 0x0 0xFF VREF_ABS_TRIM N/A [7:0] read-write VREF_TRIM1 VREF Trim bits 0xF04 32 read-write 0x0 0xFF VREF_TEMPCO_TRIM N/A [7:0] read-write VREF_TRIM2 VREF Trim bits 0xF08 32 read-write 0x0 0xFF VREF_CURV_TRIM N/A [7:0] read-write VREF_TRIM3 VREF Trim bits 0xF0C 32 read-write 0x0 0xF VREF_ATTEN_TRIM Obsolete [3:0] read-write IZTAT_TRIM0 IZTAT Trim bits 0xF10 32 read-write 0x0 0xFF IZTAT_ABS_TRIM N/A [7:0] read-write IZTAT_TRIM1 IZTAT Trim bits 0xF14 32 read-write 0x0 0xFF IZTAT_TC_TRIM IZTAT temperature correction trim (RMB) 0x00 : No IZTAT temperature correction 0xFF : Maximum IZTAT temperature correction As this is a Risk Mitigation Register, it should be loaded with 0x08. [7:0] read-write IPTAT_TRIM0 IPTAT Trim bits 0xF18 32 read-write 0x0 0xFF IPTAT_CORE_TRIM IPTAT trim 0x0 : Minimum IPTAT current (~150nA at room) 0xF : Maximum IPTAT current (~350nA at room) [3:0] read-write IPTAT_CTBM_TRIM CTMB PTAT Current Trim 0x0 : Minimum CTMB IPTAT Current (~875nA) 0xF : Maximum CTMB IPTAT Current (~1.1uA) [7:4] read-write ICTAT_TRIM0 ICTAT Trim bits 0xF1C 32 read-write 0x0 0xF ICTAT_TRIM ICTAT trim 0x00 : Minimum ICTAT current (~150nA at room) 0x0F : Maximum ICTAT current (~350nA at room) [3:0] read-write I2S0 I2S registers I2S 0x42A10000 0 4096 registers CTL Control 0x0 32 read-write 0x0 0xC0000000 TX_ENABLED Enables the I2S TX component: '0': Disabled. '1': Enabled. [30:30] read-write RX_ENABLED Enables the I2S RX component: '0': Disabled. '1': Enabled. [31:31] read-write CLOCK_CTL Clock control 0x10 32 read-write 0x0 0x13F CLOCK_DIV Frequency divisor for generating I2S clock frequency. The selected clock with CLOCK_SEL is divided by this. '0': Bypass '1': 2 x '2': 3 x '3': 4 x ... '62': 63 x '63': 64 x [5:0] read-write CLOCK_SEL Selects clock to be used by I2S: '0': Internal clock ('clk_audio_i2s') '1': External clock ('clk_i2s_if') [8:8] read-write CMD Command 0x20 32 read-write 0x0 0x10101 TX_START Transmitter enable: '0': Disabled. '1': Enabled. [0:0] read-write TX_PAUSE Pause enable: '0': Disabled (TX FIFO data is sent over I2S). '1': Enabled ('0' data is sent over I2S, instead of TX FIFO data). [8:8] read-write RX_START Receiver enable: '0': Disabled. '1': Enabled. [16:16] read-write TR_CTL Trigger control 0x40 32 read-write 0x0 0x10001 TX_REQ_EN Trigger output ('tr_i2s_tx_req') enable for requests of DMA transfer in transmission '0': Disabled. '1': Enabled. [0:0] read-write RX_REQ_EN Trigger output ('tr_i2s_rx_req') enable for requests of DMA transfer in reception '0': Disabled. '1': Enabled. [16:16] read-write TX_CTL Transmitter control 0x80 32 read-write 0x440510 0x37737F8 B_CLOCK_INV Serial data transmission is advanced by 0.5 SCK cycles. This bit is valid only in TX slave mode. When set to '1', the serial data will be transmitted 0.5 SCK cycles earlier than when set to '0'. 1) TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK falling edge 2) TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK rising edge that is 0.5 SCK cycles before the SCK falling edge in 1) 3) TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK rising edge 4) TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK falling edge that is 0.5 SCK cycles before the SCK rising edge in 3) (Note that this is only the appearance w.r.t. SCK edge, the actual timing is generated by an internal clock that runs 8x the SCK frequency). The word sync (TX_WS) signal is not affected by this bit setting. Note: When Master mode, must be '0'. (Note: This bit is connected to AR38U12.TX_CFG.TX_BCLKINV) [3:3] read-write FALLING_EDGE_TX SDO transmitted at SCK falling edge when TX_CTL.SCKI_POL=0 0 RISING_EDGE_TX SDO transmitted at SCK rising edge when TX_CTL.SCKI_POL=0 1 CH_NR Specifies number of channels per frame: Note: only '2channels' is supported during Left Justfied or I2S mode. Hence software must set '1' to this field in the modes. (Note: These bits are connected to AR38U12.TX_CFG.TX_CHSET) [6:4] read-write CH_NUM1 1 channel 0 CH_NUM2 2 channels 1 CH_NUM3 3 channels 2 CH_NUM4 4 channels 3 CH_NUM5 5 channels 4 CH_NUM6 6 channels 5 CH_NUM7 7 channels 6 CH_NUM8 8 channels 7 MS Set interface in master or slave mode: (Note: This bit is connected to AR38U12.TX_CFG.TX_MS) [7:7] read-write SLAVE Slave 0 MASTER Master 1 I2S_MODE Select I2S, left-justified or TDM: (Note: These bits are connected to AR38U12.TX_CFG.TX_I2S_MODE) [9:8] read-write LEFT_JUSTIFIED Left Justified 0 I2S I2S mode 1 TDM_A TDM mode A, the 1st Channel align to WSO Rising Edge 2 TDM_B TDM mode B, the 1st Channel align to WSO Rising edge with1 SCK Delay 3 WS_PULSE Set WS pulse width in TDM mode: (Note: This bit is connected to AR38U12.TX_CFG.TX_WS_PULSE) Note: When not TDM mode, must be '1'. [10:10] read-write SCK_PERIOD Pulse width is 1 SCK period 0 CH_LENGTH Pulse width is 1 channel length 1 OVHDATA Set overhead value: '0': Set to '0' '1': Set to '1' (Note: This bit is connected to AR38U12.TX_CFG.TX_OVHDATA) [12:12] read-write WD_EN Set watchdog for 'tx_ws_in': '0': Disabled. '1': Enabled. [13:13] read-write CH_LEN Channel length in number of bits: Note: - When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). - When TDM mode, must be 32-bit length to this field. (Note: These bits are connected to AR38U12.TX_CFG.TX_CHLEN) [18:16] read-write BIT_LEN8 8-bit 0 BIT_LEN16 16-bit 1 BIT_LEN18 18-bit 2 BIT_LEN20 20-bit 3 BIT_LEN24 24-bit 4 BIT_LEN32 32-bit 5 WORD_LEN Word length in number of bits: Note: - When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). - Don't configure this field as beyond Channel length. (Note: These bits are connected to AR38U12.TX_CFG.TX_IWL) [22:20] read-write BIT_LEN8 8-bit 0 BIT_LEN16 16-bit 1 BIT_LEN18 18-bit 2 BIT_LEN20 20-bit 3 BIT_LEN24 24-bit 4 BIT_LEN32 32-bit 5 SCKO_POL TX master bit clock polarity. When this bit is 1, the outgoing tx_sck signal is inverted after it has been transmitted from the I2S transceiver core. This bit does not affect the internal serial data transmission timing. The word sync (TX_WS) signal is not affected by this bit setting. '0': When transmitter is in master mode, serial data is transmitted from the falling bit clock edge '1': When transmitter is in master mode, serial data is transmitted from the rising bit clock edge [24:24] read-write SCKI_POL TX slave bit clock polarity. When this bit is 1, the incoming tx_sck signal is inverted before it is received by the I2S transceiver core. This bit does not affect the internal serial data transmission timing. The word sync (TX_WS) signal is not affected by this bit setting. See TX_CTL.B_CLOCK_INV for more details. [25:25] read-write TX_WATCHDOG Transmitter watchdog 0x84 32 read-write 0x0 0xFFFFFFFF WD_COUNTER Start value of the TX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'. [31:0] read-write RX_CTL Receiver control 0xA0 32 read-write 0x440510 0x3F727F8 B_CLOCK_INV Serial data capture is delayed by 0.5 SCK cycles. This bit is valid only in RX master mode. When set to '1', the serial data will be captured 0.5 SCK cycles later than when set to '0'. 1) RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK rising edge 2) RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK falling edge that is 0.5 SCK cycles after the SCK rising edge in 1) 3) RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK falling edge 4) RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK rising edge that is 0.5 SCK cycles after the SCK falling edge in 3) (Note that this is only the appearance w.r.t. SCK edge, the actual capture timing is derived from an internal clock that runs 8x the SCK frequency). The word sync (RX_WS) signal is not affected by this bit setting. Note: When Slave mode, must be '0'. (Note: This bit is connected to AR38U12.TX_CFG.RX_BCLKINV) [3:3] read-write RISING_EDGE_RX SDI received at SCK rising edge when RX_CTL.SCKO_POL=0 0 FALLING_EDGE_RX SDI received at SCK falling edge when RX_CTL.SCKO_POL=0 1 CH_NR Specifies number of channels per frame: Note: only '2channels' is supported during Left Justfied or I2S mode. Hence software must set '1' to this field in the modes. (Note: These bits are connected to AR38U12.RX_CFG.RX_CHSET) [6:4] read-write CH_NUM1 1 channel 0 CH_NUM2 2 channels 1 CH_NUM3 3 channels 2 CH_NUM4 4 channels 3 CH_NUM5 5 channels 4 CH_NUM6 6 channels 5 CH_NUM7 7 channels 6 CH_NUM8 8 channels 7 MS Set interface in master or slave mode: (Note: This bit is connected to AR38U12.TX_CFG.RX_MS) [7:7] read-write SLAVE Slave 0 MASTER Master 1 I2S_MODE Select I2S, left-justified or TDM: (Note: These bits are connected to AR38U12.RX_CFG.RX_I2S_MODE) [9:8] read-write LEFT_JUSTIFIED Left Justified 0 I2S I2S mode 1 TDM_A TDM mode A, the 1st Channel align to WSO Rising Edge 2 TDM_B TDM mode B, the 1st Channel align to WSO Rising edge with1 SCK Delay 3 WS_PULSE Set WS pulse width in TDM mode: (Note: This bit is connected to AR38U12.RX_CFG.RX_WS_PULSE) Note: When not TDM mode, must be '1'. [10:10] read-write SCK_PERIOD Pulse width is 1 SCK period 0 CH_LENGTH Pulse width is 1 channel length 1 WD_EN Set watchdog for 'rx_ws_in' '0': Disabled. '1': Enabled. [13:13] read-write CH_LEN Channel length in number of bits: Note: - When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). - When TDM mode, must be 32-bit length to this field. (Note: These bits are connected to AR38U12.RX_CFG.RX_CHLEN) [18:16] read-write BIT_LEN8 8-bit 0 BIT_LEN16 16-bit 1 BIT_LEN18 18-bit 2 BIT_LEN20 20-bit 3 BIT_LEN24 24-bit 4 BIT_LEN32 32-bit 5 WORD_LEN Word length in number of bits: Note: - When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). - Don't configure this field as beyond Channel length. (Note: These bits are connected to AR38U12.RX_CFG.RX_IWL) [22:20] read-write BIT_LEN8 8-bit 0 BIT_LEN16 16-bit 1 BIT_LEN18 18-bit 2 BIT_LEN20 20-bit 3 BIT_LEN24 24-bit 4 BIT_LEN32 32-bit 5 BIT_EXTENSION When reception word length is shorter than the word length of RX_FIFO_RD, extension mode of upper bit should be set. '0': Extended by '0' '1': Extended by sign bit (if MSB word is '1', then it is extended by '1', if MSB is '0' then it is extended by '0') [23:23] read-write SCKO_POL RX master bit clock polarity. When this bit is 1, the outgoing rx_sck signal is inverted after it has been transmitted from the I2S receiver core. This bit does not affect the internal serial data capture timing. The word sync (RX_WS) signal is not affected by this bit setting.See RX_CTL.B_CLOCK_INV for more details. [24:24] read-write SCKI_POL RX slave bit clock polarity. When this bit is 1, the incoming rx_sck signal is inverted before it is received by the I2S receiver core. This bit does not affect the internal serial data capture timing. The word sync (RX_WS) signal is not affected by this bit setting. '0': When receiver is in slave mode, serial data is sampled on the rising bit clock edge '1': When receiver is in slave mode, serial data is sampled on the falling bit clock edge [25:25] read-write RX_WATCHDOG Receiver watchdog 0xA4 32 read-write 0x0 0xFFFFFFFF WD_COUNTER Start value of the RX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'. [31:0] read-write TX_FIFO_CTL TX FIFO control 0x200 32 read-write 0x0 0x300FF TRIGGER_LEVEL Trigger level. When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated. [7:0] read-write CLEAR When '1', the TX FIFO and TX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. [16:16] read-write FREEZE When '1', hardware reads from the TX FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. This field is used only for debugging purposes. [17:17] read-write TX_FIFO_STATUS TX FIFO status 0x204 32 read-only 0x0 0xFFFF01FF USED Number of entries in the TX FIFO. The field value is in the range [0, 256]. [8:0] read-only RD_PTR TX FIFO read pointer: FIFO location from which a data frame is read by the hardware.This field is used only for debugging purposes. [23:16] read-only WR_PTR TX FIFO write pointer: FIFO location at which a new data frame is written by the host. This field is used only for debugging purposes. [31:24] read-only TX_FIFO_WR TX FIFO write 0x208 32 write-only 0x0 0xFFFFFFFF DATA Data written into the TX FIFO. Behavior is similar to that of a PUSH operation. Note: Don't access to this register while TX_FIFO_CTL.CLEAR is '1'. [31:0] write-only RX_FIFO_CTL RX FIFO control 0x300 32 read-write 0x0 0x300FF TRIGGER_LEVEL Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated. Note: software can configure up to 253 in I2S mode or Left Justified (RX_CTL.I2S_MODE = '0' or '1'). In TDM mode (RX_CTL.I2S_MODE = '2' or '3'), it can configure up to [256 - (RX_CTL.CH_NR+2)]. [7:0] read-write CLEAR When '1', the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. [16:16] read-write FREEZE When '1', hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer. This field is used only for debugging purposee. [17:17] read-write RX_FIFO_STATUS RX FIFO status 0x304 32 read-only 0x0 0xFFFF01FF USED Number of entries in the RX FIFO. The field value is in the range [0, 256]. [8:0] read-only RD_PTR RX FIFO read pointer: FIFO location from which a data frame is read by the host. This field is used only for debugging purposes. [23:16] read-only WR_PTR RX FIFO write pointer: FIFO location at which a new data frame is written by the hardware. This field is used only for debugging purposes. [31:24] read-only RX_FIFO_RD RX FIFO read 0x308 32 read-only 0x0 0xFFFFFFFF DATA Data read from the RX FIFO. Reading a data frame will remove the data frame from the RX FIFO; i.e. behavior is similar to that of a POP operation. Notes: - Don't access to this register while RX_FIFO_CTL.CLEAR is '1'. - Two stored data may be not valid after CMD.RX_START is set '1'. Therefore we recommend software discard those data. [31:0] read-only RX_FIFO_RD_SILENT RX FIFO silent read 0x30C 32 read-only 0x0 0xFFFFFFFF DATA Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes. Notes: - Don't access to this register while RX_FIFO_CTL.CLEAR is '1'. - Two stored data may be not valid after CMD.RX_START is set '1'. Therefore we recommend software discard those data. [31:0] read-only INTR Interrupt register 0xF00 32 read-write 0x0 0x16D0173 TX_TRIGGER Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL. [0:0] read-write TX_NOT_FULL TX FIFO is not full. [1:1] read-write TX_EMPTY TX FIFO is empty; i.e. it has 0 entries. [4:4] read-write TX_OVERFLOW Attempt to write to a full TX FIFO. [5:5] read-write TX_UNDERFLOW Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and TX_EMPTY is '1'. [6:6] read-write TX_WD Triggers (sets to '1') when the Tx watchdog event occurs. [8:8] read-write RX_TRIGGER More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL. [16:16] read-write RX_NOT_EMPTY RX FIFO is not empty. [18:18] read-write RX_FULL RX FIFO is full. [19:19] read-write RX_OVERFLOW Attempt to write to a full RX FIFO. [21:21] read-write RX_UNDERFLOW Attempt to read from an empty RX FIFO. [22:22] read-write RX_WD Triggers (sets to '1') when the Rx watchdog event occurs. [24:24] read-write INTR_SET Interrupt set register 0xF04 32 read-write 0x0 0x16D0173 TX_TRIGGER Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write TX_NOT_FULL Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write TX_EMPTY Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write TX_OVERFLOW Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write TX_UNDERFLOW Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write TX_WD Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write RX_TRIGGER Write with '1' to set corresponding bit in interrupt request register. [16:16] read-write RX_NOT_EMPTY Write with '1' to set corresponding bit in interrupt request register. [18:18] read-write RX_FULL Write with '1' to set corresponding bit in interrupt request register. [19:19] read-write RX_OVERFLOW Write with '1' to set corresponding bit in interrupt request register. [21:21] read-write RX_UNDERFLOW Write with '1' to set corresponding bit in interrupt request register. [22:22] read-write RX_WD Write with '1' to set corresponding bit in interrupt request register. [24:24] read-write INTR_MASK Interrupt mask register 0xF08 32 read-write 0x0 0x16D0173 TX_TRIGGER Mask bit for corresponding bit in interrupt request register. [0:0] read-write TX_NOT_FULL Mask bit for corresponding bit in interrupt request register. [1:1] read-write TX_EMPTY Mask bit for corresponding bit in interrupt request register. [4:4] read-write TX_OVERFLOW Mask bit for corresponding bit in interrupt request register. [5:5] read-write TX_UNDERFLOW Mask bit for corresponding bit in interrupt request register. [6:6] read-write TX_WD Mask bit for corresponding bit in interrupt request register. [8:8] read-write RX_TRIGGER Mask bit for corresponding bit in interrupt request register. [16:16] read-write RX_NOT_EMPTY Mask bit for corresponding bit in interrupt request register. [18:18] read-write RX_FULL Mask bit for corresponding bit in interrupt request register. [19:19] read-write RX_OVERFLOW Mask bit for corresponding bit in interrupt request register. [21:21] read-write RX_UNDERFLOW Mask bit for corresponding bit in interrupt request register. [22:22] read-write RX_WD Mask bit for corresponding bit in interrupt request register. [24:24] read-write INTR_MASKED Interrupt masked register 0xF0C 32 read-only 0x0 0x16D0173 TX_TRIGGER Logical and of corresponding request and mask bits. [0:0] read-only TX_NOT_FULL Logical and of corresponding request and mask bits. [1:1] read-only TX_EMPTY Logical and of corresponding request and mask bits. [4:4] read-only TX_OVERFLOW Logical and of corresponding request and mask bits. [5:5] read-only TX_UNDERFLOW Logical and of corresponding request and mask bits. [6:6] read-only TX_WD Logical and of corresponding request and mask bits. [8:8] read-only RX_TRIGGER Logical and of corresponding request and mask bits. [16:16] read-only RX_NOT_EMPTY Logical and of corresponding request and mask bits. [18:18] read-only RX_FULL Logical and of corresponding request and mask bits. [19:19] read-only RX_OVERFLOW Logical and of corresponding request and mask bits. [21:21] read-only RX_UNDERFLOW Logical and of corresponding request and mask bits. [22:22] read-only RX_WD Logical and of corresponding request and mask bits. [24:24] read-only PDM0 PDM registers PDM 0x42A20000 0 4096 registers CTL Control 0x0 32 read-write 0x20808 0x80030F0F PGA_R Right channel PGA gain: +1.5dB/step, -12dB ~ +10.5dB '0': -12 dB '1': -10.5 dB ... '15' +10.5 dB (Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_R) [3:0] read-write PGA_L Left channel PGA gain: +1.5dB/step, -12dB ~ +10.5dB '0': -12 dB '1': -10.5 dB ... '15': +10.5 dB (Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_L) [11:8] read-write SOFT_MUTE Soft mute function to mute the volume smoothly '0': Disabled. '1': Enabled. (Note: This bit is connected to AR36U12.PDM_CORE_CFG.SOFT_MUTE) [16:16] read-write STEP_SEL Set fine gain step for smooth PGA or Soft-Mute attenuation transition. '0': 0.13dB '1': 0.26dB (Note: This bit is connected to AR36U12.PDM_CORE2_CFG.SEL_STEP) [17:17] read-write ENABLED Enables the PDM component: '0': Disabled. '1': Enabled. [31:31] read-write CLOCK_CTL Clock control 0x10 32 read-write 0x200310 0x7F0F33 CLK_CLOCK_DIV PDM CLK (FPDM_CLK) (1st divider): This configures a frequency of PDM CLK. The configured frequency is used to operate PDM core. I.e. the frequency is input to MCLKQ_CLOCK_DIV register. Note: configure a frequency of PDM CLK as lower than or equal 50MHz with this divider. [1:0] read-write DIVBY1 Divide by 1 0 DIVBY2 Divide by 2 (no 50 percent duty cycle) 1 DIVBY3 Divide by 3 (no 50 percent duty cycle) 2 DIVBY4 Divide by 4 (no 50 percent duty cycle) 3 MCLKQ_CLOCK_DIV MCLKQ divider (2nd divider) (Note: These bits are connected to AR36U12.PDM_CORE2_CFG.DIV_MCLKQ) [5:4] read-write DIVBY1 Divide by 1 0 DIVBY2 Divide by 2 (no 50 percent duty cycle) 1 DIVBY3 Divide by 3 (no 50 percent duty cycle) 2 DIVBY4 Divide by 4 (no 50 percent duty cycle) 3 CKO_CLOCK_DIV PDM CKO (FPDM_CKO) clock divider (3rd divider): FPDM_CKO = MCLKQ / (CKO_CLOCK_DIV + 1) Note: To configure '0' to this field is prohibited. (Note: PDM_CKO is configured by MCLKQ_CLOCK_DIV, CLK_CLOCK_DIV and CKO_CLOCK_DIV. ) (Note: These bits are connected to AR36U12.PDM_CORE_CFG.MCLKDIV) [11:8] read-write SINC_RATE SINC Decimation Rate. For details, see the data sheet provided by Archband. Oversampling Ratio = Decimation Rate = 2 X SINC_RATE (Note: These bits are connected to AR36U12.PDM_CORE_CFG.SINC_RATE) [22:16] read-write MODE_CTL Mode control 0x14 32 read-write 0x1B000103 0x1F070707 PCM_CH_SET Specifies PCM output channels as mono or stereo: (Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_CHSET) [1:0] read-write DISABLED Channel disabled 0 MONO_L Mono left channel enable 1 MONO_R Mono right channel enable 2 STEREO Stereo channel enable 3 SWAP_LR Input data L/R channel swap: '1': Right/Left channel recording swap '0': No Swap (Note: This bit is connected to AR36U12.PDM_CORE_CFG.LRSWAP) [2:2] read-write S_CYCLES Set time step for gain change during PGA or soft mute operation in number of 1/a sampling rate. (Note: These bits are connected to AR36U12.PDM_CORE_CFG.S_CYCLES) [10:8] read-write STEP_NUM64 64steps 0 STEP_NUM96 96steps 1 STEP_NUM128 128steps 2 STEP_NUM160 160steps 3 STEP_NUM192 192steps 4 STEP_NUM256 256steps 5 STEP_NUM384 384steps 6 STEP_NUM512 512steps 7 CKO_DELAY Phase difference from the rising edge of internal sampler clock (CLK_IS) to that of PDM_CKO clock: (Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PDMCKO_DLY) [18:16] read-write ADV3 CLK_IS is 3*PDM_CLK period early 0 ADV2 CLK_IS is 2*PDM_CLK period early 1 ADV1 CLK_IS is 1*PDM_CLK period early 2 NO_DELAY CLK_IS is the same as PDM_CKO 3 DLY1 CLK_IS is 1*PDM_CLK period late 4 DLY2 CLK_IS is 2*PDM_CLK period late 5 DLY3 CLK_IS is 3*PDM_CLK period late 6 DLY4 CLK_IS is 4*PDM_CLK period late 7 HPF_GAIN Adjust high pass filter coefficients. H(Z) = (1 - Z-1 ) / [1 - (1- 2 -HPF_GAIN) Z-1 ] (Note: These bits are connected to AR36U12.PDM_CORE_CFG.HPGAIN) [27:24] read-write HPF_EN_N Enable high pass filter (active low) '1': Disabled. '0': Enabled. (Note: This bit is connected to AR36U12.PDM_CORE_CFG.ADCHPD) [28:28] read-write DATA_CTL Data control 0x18 32 read-write 0x0 0x103 WORD_LEN PCM Word Length in number of bits: (Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_IWL) [1:0] read-write BIT_LEN16 16-bit 0 BIT_LEN18 18-bit 1 BIT_LEN20 20-bit 2 BIT_LEN24 24-bit 3 BIT_EXTENSION When reception word length is shorter than the word length of RX_FIFO_RD, extension mode of upper bit should be set. '0': Extended by '0' '1': Extended by sign bit (if MSB word is '1', then it is extended by '1', if MSB is '0' then it is extended by '0') [8:8] read-write CMD Command 0x20 32 read-write 0x0 0x1 STREAM_EN Enable data streaming flow: '0': Disabled. '1': Enabled. (Note: This bit is connected to AR36U12.PDM_CORE_CFG.PDMA_EN) [0:0] read-write TR_CTL Trigger control 0x40 32 read-write 0x0 0x10000 RX_REQ_EN Trigger output ('tr_pdm_rx_req') enable for requests of DMA transfer '0': Disabled. '1': Enabled. [16:16] read-write RX_FIFO_CTL RX FIFO control 0x300 32 read-write 0x0 0x300FF TRIGGER_LEVEL Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated. Note: software can configure up to 254 in Mono channel enabled (MODE_CTL.PCM_CH_SET = '1' or '2'), up to 253 in Stereo channel enabled (MODE_CTL.PCM_CH_SET = '3'). [7:0] read-write CLEAR When '1', the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. [16:16] read-write FREEZE When '1', hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer.This field is used only for debugging purposes. [17:17] read-write RX_FIFO_STATUS RX FIFO status 0x304 32 read-only 0x0 0xFFFF00FF USED Number of entries in the RX FIFO. The field value is in the range [0, 255]. When this is zero, the RX FIFO is empty. [7:0] read-only RD_PTR RX FIFO read pointer: RX FIFO location from which a data frame is read by the host.This field is used only for debugging purposes. [23:16] read-only WR_PTR RX FIFO write pointer: RX FIFO location at which a new data frame is written by the hardware.This field is used only for debugging purposes. [31:24] read-only RX_FIFO_RD RX FIFO read 0x308 32 read-only 0x0 0xFFFFFFFF DATA Data read from the RX FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note: Don't access to this bit while RX_FIFO_CTL.CLEAR is '1'. [31:0] read-only RX_FIFO_RD_SILENT RX FIFO silent read 0x30C 32 read-only 0x0 0xFFFFFFFF DATA Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes. Note: Don't access to this bit while RX_FIFO_CTL.CLEAR is '1'. [31:0] read-only INTR Interrupt register 0xF00 32 read-write 0x0 0x650000 RX_TRIGGER More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTL. [16:16] read-write RX_NOT_EMPTY RX FIFO is not empty. [18:18] read-write RX_OVERFLOW Attempt to write to a full RX FIFO [21:21] read-write RX_UNDERFLOW Attempt to read from an empty RX FIFO [22:22] read-write INTR_SET Interrupt set register 0xF04 32 read-write 0x0 0x650000 RX_TRIGGER Write with '1' to set corresponding bit in interrupt request register. [16:16] read-write RX_NOT_EMPTY Write with '1' to set corresponding bit in interrupt request register. [18:18] read-write RX_OVERFLOW Write with '1' to set corresponding bit in interrupt request register. [21:21] read-write RX_UNDERFLOW Write with '1' to set corresponding bit in interrupt request register. [22:22] read-write INTR_MASK Interrupt mask register 0xF08 32 read-write 0x0 0x650000 RX_TRIGGER Mask bit for corresponding bit in interrupt request register. [16:16] read-write RX_NOT_EMPTY Mask bit for corresponding bit in interrupt request register. [18:18] read-write RX_OVERFLOW Mask bit for corresponding bit in interrupt request register. [21:21] read-write RX_UNDERFLOW Mask bit for corresponding bit in interrupt request register. [22:22] read-write INTR_MASKED Interrupt masked register 0xF0C 32 read-only 0x0 0x650000 RX_TRIGGER Logical and of corresponding request and mask bits. [16:16] read-only RX_NOT_EMPTY Logical and of corresponding request and mask bits. [18:18] read-only RX_OVERFLOW Logical and of corresponding request and mask bits. [21:21] read-only RX_UNDERFLOW Logical and of corresponding request and mask bits. [22:22] read-only