Microchip Technology MCHP ATSAML11E15A SAML11 0 Microchip ATSAML11E15A Microcontroller CM23 r0p0 selectable true false 2 false 8 32 32 read-write 0x00000000 0xFFFFFFFF AC U22451.0.2 Analog Comparators AC AC_ 0x40003400 0 0x24 registers AC 39 CTRLA Control A 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 CTRLB Control B 0x1 8 write-only 0x00 START0 Comparator 0 Start Comparison 0 1 START1 Comparator 1 Start Comparison 1 1 EVCTRL Event Control 0x2 16 0x0000 COMPEO0 Comparator 0 Event Output Enable 0 1 COMPEO1 Comparator 1 Event Output Enable 1 1 WINEO0 Window 0 Event Output Enable 4 1 COMPEI0 Comparator 0 Event Input Enable 8 1 COMPEI1 Comparator 1 Event Input Enable 9 1 INVEI0 Comparator 0 Input Event Invert Enable 12 1 INVEI1 Comparator 1 Input Event Invert Enable 13 1 INTENCLR Interrupt Enable Clear 0x4 8 0x00 COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 WIN0 Window 0 Interrupt Enable 4 1 INTENSET Interrupt Enable Set 0x5 8 0x00 COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 WIN0 Window 0 Interrupt Enable 4 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 0x00 COMP0 Comparator 0 0 1 COMP1 Comparator 1 1 1 WIN0 Window 0 4 1 STATUSA Status A 0x7 8 read-only 0x00 STATE0 Comparator 0 Current State 0 1 STATE1 Comparator 1 Current State 1 1 WSTATE0 Window 0 Current State 4 2 WSTATE0Select ABOVE Signal is above window 0 INSIDE Signal is inside window 1 BELOW Signal is below window 2 STATUSB Status B 0x8 8 read-only 0x00 READY0 Comparator 0 Ready 0 1 READY1 Comparator 1 Ready 1 1 DBGCTRL Debug Control 0x9 8 0x00 DBGRUN Debug Run 0 1 WINCTRL Window Control 0xA 8 0x00 WEN0 Window 0 Mode Enable 0 1 WINTSEL0 Window 0 Interrupt Selection 1 2 WINTSEL0Select ABOVE Interrupt on signal above window 0 INSIDE Interrupt on signal inside window 1 BELOW Interrupt on signal below window 2 OUTSIDE Interrupt on signal outside window 3 2 1 SCALER[%s] Scaler n 0xC 8 0x00 VALUE Scaler Value 0 6 2 4 COMPCTRL[%s] Comparator Control n 0x10 32 0x00000000 ENABLE Enable 1 1 SINGLE Single-Shot Mode 2 1 INTSEL Interrupt Selection 3 2 INTSELSelect TOGGLE Interrupt on comparator output toggle 0 RISING Interrupt on comparator output rising 1 FALLING Interrupt on comparator output falling 2 EOC Interrupt on end of comparison (single-shot mode only) 3 RUNSTDBY Run in Standby 6 1 MUXNEG Negative Input Mux Selection 8 3 MUXNEGSelect PIN0 I/O pin 0 0 PIN1 I/O pin 1 1 PIN2 I/O pin 2 2 PIN3 I/O pin 3 3 GND Ground 4 VSCALE VDD scaler 5 BANDGAP Internal bandgap voltage 6 OPAMP OPAMP output (on AC1) 7 DAC DAC output (on AC0) 7 MUXPOS Positive Input Mux Selection 12 3 MUXPOSSelect PIN0 I/O pin 0 0 PIN1 I/O pin 1 1 PIN2 I/O pin 2 2 PIN3 I/O pin 3 3 VSCALE VDD Scaler 4 SWAP Swap Inputs and Invert 15 1 SPEED Speed Selection 16 2 SPEEDSelect LOW Low speed 0 MEDLOW Medium low speed 1 MEDHIGH Medium high speed 2 HIGH High speed 3 HYSTEN Hysteresis Enable 19 1 HYST Hysteresis Level 20 2 HYSTSelect HYST50 50mV 0 HYST70 70mV 1 HYST90 90mV 2 HYST110 110mV 3 FLEN Filter Length 24 3 FLENSelect OFF No filtering 0 MAJ3 3-bit majority function (2 of 3) 1 MAJ5 5-bit majority function (3 of 5) 2 OUT Output 28 2 OUTSelect OFF The output of COMPn is not routed to the COMPn I/O port 0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 1 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port 2 SYNCBUSY Synchronization Busy 0x20 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE Enable Synchronization Busy 1 1 WINCTRL WINCTRL Synchronization Busy 2 1 COMPCTRL0 COMPCTRL 0 Synchronization Busy 3 1 COMPCTRL1 COMPCTRL 1 Synchronization Busy 4 1 ADC U22472.4.0 Analog Digital Converter ADC ADC_ 0x42001C00 0 0x2E registers ADC_OTHER 37 ADC_RESRDY 38 CTRLA Control A 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 SLAVEEN Slave Enable 5 1 RUNSTDBY Run During Standby 6 1 ONDEMAND On Demand Control 7 1 CTRLB Control B 0x1 8 0x00 PRESCALER Prescaler Configuration 0 3 PRESCALERSelect DIV2 Peripheral clock divided by 2 0x0 DIV4 Peripheral clock divided by 4 0x1 DIV8 Peripheral clock divided by 8 0x2 DIV16 Peripheral clock divided by 16 0x3 DIV32 Peripheral clock divided by 32 0x4 DIV64 Peripheral clock divided by 64 0x5 DIV128 Peripheral clock divided by 128 0x6 DIV256 Peripheral clock divided by 256 0x7 REFCTRL Reference Control 0x2 8 0x00 REFSEL Reference Selection 0 4 REFSELSelect INTREF Internal Bandgap Reference 0x0 INTVCC0 1/1.6 VDDANA 0x1 INTVCC1 1/2 VDDANA 0x2 AREFA External Reference 0x3 AREFB External Reference 0x4 INTVCC2 VCCANA 0x5 REFCOMP Reference Buffer Offset Compensation Enable 7 1 EVCTRL Event Control 0x3 8 0x00 FLUSHEI Flush Event Input Enable 0 1 STARTEI Start Conversion Event Input Enable 1 1 FLUSHINV Flush Event Invert Enable 2 1 STARTINV Satrt Event Invert Enable 3 1 RESRDYEO Result Ready Event Out 4 1 WINMONEO Window Monitor Event Out 5 1 INTENCLR Interrupt Enable Clear 0x4 8 0x00 RESRDY Result Ready Interrupt Disable 0 1 OVERRUN Overrun Interrupt Disable 1 1 WINMON Window Monitor Interrupt Disable 2 1 INTENSET Interrupt Enable Set 0x5 8 0x00 RESRDY Result Ready Interrupt Enable 0 1 OVERRUN Overrun Interrupt Enable 1 1 WINMON Window Monitor Interrupt Enable 2 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 0x00 RESRDY Result Ready Interrupt Flag 0 1 OVERRUN Overrun Interrupt Flag 1 1 WINMON Window Monitor Interrupt Flag 2 1 SEQSTATUS Sequence Status 0x7 8 read-only 0x00 SEQSTATE Sequence State 0 5 SEQBUSY Sequence Busy 7 1 INPUTCTRL Input Control 0x8 16 0x0000 MUXPOS Positive Mux Input Selection 0 5 MUXPOSSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 AIN6 ADC AIN6 Pin 0x6 AIN7 ADC AIN7 Pin 0x7 AIN8 ADC AIN8 Pin 0x8 AIN9 ADC AIN9 Pin 0x9 AIN10 ADC AIN10 Pin 0xA AIN11 ADC AIN11 Pin 0xB AIN12 ADC AIN12 Pin 0xC AIN13 ADC AIN13 Pin 0xD AIN14 ADC AIN14 Pin 0xE AIN15 ADC AIN15 Pin 0xF AIN16 ADC AIN16 Pin 0x10 AIN17 ADC AIN17 Pin 0x11 AIN18 ADC AIN18 Pin 0x12 AIN19 ADC AIN19 Pin 0x13 AIN20 ADC AIN20 Pin 0x14 AIN21 ADC AIN21 Pin 0x15 AIN22 ADC AIN22 Pin 0x16 AIN23 ADC AIN23 Pin 0x17 TEMP Temperature Sensor 0x18 BANDGAP Bandgap Voltage 0x19 SCALEDCOREVCC 1/4 Scaled Core Supply 0x1A SCALEDIOVCC 1/4 Scaled I/O Supply 0x1B DAC DAC Output 0x1C SCALEDVBAT 1/4 Scaled VBAT Supply 0x1D OPAMP01 OPAMP0 or OPAMP1 output 0x1E OPAMP2 OPAMP2 output 0x1F MUXNEG Negative Mux Input Selection 8 5 MUXNEGSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 AIN6 ADC AIN6 Pin 0x6 AIN7 ADC AIN7 Pin 0x7 CTRLC Control C 0xA 16 0x0000 DIFFMODE Differential Mode 0 1 LEFTADJ Left-Adjusted Result 1 1 FREERUN Free Running Mode 2 1 CORREN Digital Correction Logic Enable 3 1 RESSEL Conversion Result Resolution 4 2 RESSELSelect 12BIT 12-bit result 0x0 16BIT For averaging mode output 0x1 10BIT 10-bit result 0x2 8BIT 8-bit result 0x3 R2R Rail-to-Rail mode enable 7 1 WINMODE Window Monitor Mode 8 3 WINMODESelect DISABLE No window mode (default) 0 MODE1 RESULT > WINLT 1 MODE2 RESULT < WINUT 2 MODE3 WINLT < RESULT < WINUT 3 MODE4 !(WINLT < RESULT < WINUT) 4 DUALSEL Dual Mode Trigger Selection 12 2 DUALSELSelect BOTH Start event or software trigger will start a conversion on both ADCs 0 INTERLEAVE START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 1 AVGCTRL Average Control 0xC 8 0x00 SAMPLENUM Number of Samples to be Collected 0 4 SAMPLENUMSelect 1 1 sample 0x0 2 2 samples 0x1 4 4 samples 0x2 8 8 samples 0x3 16 16 samples 0x4 32 32 samples 0x5 64 64 samples 0x6 128 128 samples 0x7 256 256 samples 0x8 512 512 samples 0x9 1024 1024 samples 0xA ADJRES Adjusting Result / Division Coefficient 4 3 SAMPCTRL Sample Time Control 0xD 8 0x00 SAMPLEN Sampling Time Length 0 6 OFFCOMP Comparator Offset Compensation Enable 7 1 WINLT Window Monitor Lower Threshold 0xE 16 0x0000 WINLT Window Lower Threshold 0 16 WINUT Window Monitor Upper Threshold 0x10 16 0x0000 WINUT Window Upper Threshold 0 16 GAINCORR Gain Correction 0x12 16 0x0000 GAINCORR Gain Correction Value 0 12 OFFSETCORR Offset Correction 0x14 16 0x0000 OFFSETCORR Offset Correction Value 0 12 SWTRIG Software Trigger 0x18 8 0x00 FLUSH ADC Flush 0 1 START Start ADC Conversion 1 1 DBGCTRL Debug Control 0x1C 8 0x00 DBGRUN Debug Run 0 1 SYNCBUSY Synchronization Busy 0x20 16 read-only 0x0000 SWRST SWRST Synchronization Busy 0 1 ENABLE ENABLE Synchronization Busy 1 1 INPUTCTRL INPUTCTRL Synchronization Busy 2 1 CTRLC CTRLC Synchronization Busy 3 1 AVGCTRL AVGCTRL Synchronization Busy 4 1 SAMPCTRL SAMPCTRL Synchronization Busy 5 1 WINLT WINLT Synchronization Busy 6 1 WINUT WINUT Synchronization Busy 7 1 GAINCORR GAINCORR Synchronization Busy 8 1 OFFSETCORR OFFSETCTRL Synchronization Busy 9 1 SWTRIG SWTRG Synchronization Busy 10 1 RESULT Result 0x24 16 read-only 0x0000 RESULT Result Value 0 16 SEQCTRL Sequence Control 0x28 32 0x00000000 SEQEN Enable Positive Input in the Sequence 0 32 CALIB Calibration 0x2C 16 0x0000 BIASCOMP Bias Comparator Scaling 0 3 BIASREFBUF Bias Reference Buffer Scaling 8 3 CCL U22252.0.0 Configurable Custom Logic CCL CCL_ 0x42002C00 0 0x10 registers CTRL Control 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 RUNSTDBY Run in Standby 6 1 1 1 SEQCTRL[%s] SEQ Control x 0x4 8 0x00 SEQSEL Sequential Selection 0 4 SEQSELSelect DISABLE Sequential logic is disabled 0 DFF D flip flop 1 JK JK flip flop 2 LATCH D latch 3 RS RS latch 4 2 4 LUTCTRL[%s] LUT Control x 0x8 32 0x00000000 ENABLE LUT Enable 1 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0 SYNCH Synchronizer enabled 1 FILTER Filter enabled 2 EDGESEL Edge Selection 7 1 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 ALT2TC Alternate 2 TC input source 10 ASYNCEVENT Asynchronous event input source. The EVENT input will bypass edge detection logic. 11 INSEL1 Input Selection 1 12 4 INSEL1Select MASK Masked input 0x0 FEEDBACK Feedback input source 0x1 LINK Linked LUT input source 0x2 EVENT Event input source 0x3 IO I/O pin input source 0x4 AC AC input source 0x5 TC TC input source 0x6 ALTTC Alternate TC input source 0x7 TCC TCC input source 0x8 SERCOM SERCOM input source 0x9 ALT2TC Alternate 2 TC input source 0xA ASYNCEVENT Asynchronous event input source. The EVENT input will bypass edge detection logic. 0xB INSEL2 Input Selection 2 16 4 INSEL2Select MASK Masked input 0x0 FEEDBACK Feedback input source 0x1 LINK Linked LUT input source 0x2 EVENT Event input source 0x3 IO I/O pin input source 0x4 AC AC input source 0x5 TC TC input source 0x6 ALTTC Alternate TC input source 0x7 TCC TCC input source 0x8 SERCOM SERCOM input source 0x9 ALT2TC Alternate 2 TC input source 0xA ASYNCEVENT Asynchronous event input source. The EVENT input will bypass edge detection logic. 0xB INVEI Inverted Event Input Enable 20 1 LUTEI LUT Event Input Enable 21 1 LUTEO LUT Event Output Enable 22 1 TRUTH Truth Value 24 8 DAC U22142.1.0 Digital Analog Converter DAC DAC_ 0x42002000 0 0x15 registers DAC_UNDERRUN_A 40 DAC_EMPTY 41 CTRLA Control A 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 RUNSTDBY Run in Standby 6 1 CTRLB Control B 0x1 8 0x00 EOEN External Output Enable 0 1 IOEN Internal Output Enable 1 1 LEFTADJ Left Adjusted Data 2 1 VPD Voltage Pump Disable 3 1 DITHER Dither Enable 5 1 REFSEL Reference Selection 6 2 REFSELSelect INT1V Internal 1.0V reference 0 AVCC AVCC 1 VREFP External reference 2 EVCTRL Event Control 0x2 8 0x00 STARTEI Start Conversion Event Input 0 1 EMPTYEO Data Buffer Empty Event Output 1 1 INVEI Invert Event Input 2 1 INTENCLR Interrupt Enable Clear 0x4 8 0x00 UNDERRUN Underrun Interrupt Enable 0 1 EMPTY Data Buffer Empty Interrupt Enable 1 1 INTENSET Interrupt Enable Set 0x5 8 0x00 UNDERRUN Underrun Interrupt Enable 0 1 EMPTY Data Buffer Empty Interrupt Enable 1 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 0x00 UNDERRUN Underrun 0 1 EMPTY Data Buffer Empty 1 1 STATUS Status 0x7 8 read-only 0x00 READY Ready 0 1 DATA Data 0x8 16 write-only 0x0000 DATA Data value to be converted 0 16 DATABUF Data Buffer 0xC 16 write-only 0x0000 DATABUF Data Buffer 0 16 SYNCBUSY Synchronization Busy 0x10 32 read-only 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 DATA Data 2 1 DATABUF Data Buffer 3 1 DBGCTRL Debug Control 0x14 8 0x00 DBGRUN Debug Run 0 1 DMAC U22232.4.0 Direct Memory Access Controller DMAC DMAC_ 0x41006000 0 0x50 registers DMAC_0 11 DMAC_1 12 DMAC_2 13 DMAC_3 14 DMAC_OTHER 15 CTRL Control 0x0 16 0x0000 SWRST Software Reset 0 1 DMAENABLE DMA Enable 1 1 CRCENABLE CRC Enable 2 1 LVLEN0 Priority Level 0 Enable 8 1 LVLEN1 Priority Level 1 Enable 9 1 LVLEN2 Priority Level 2 Enable 10 1 LVLEN3 Priority Level 3 Enable 11 1 CRCCTRL CRC Control 0x2 16 0x0000 CRCBEATSIZE CRC Beat Size 0 2 CRCBEATSIZESelect BYTE 8-bit bus transfer 0x0 HWORD 16-bit bus transfer 0x1 WORD 32-bit bus transfer 0x2 CRCPOLY CRC Polynomial Type 2 2 CRCPOLYSelect CRC16 CRC-16 (CRC-CCITT) 0x0 CRC32 CRC32 (IEEE 802.3) 0x1 CRCSRC CRC Input Source 8 6 CRCSRCSelect NOACT No action 0x00 IO I/O interface 0x01 CRCDATAIN CRC Data Input 0x4 32 0x00000000 CRCDATAIN CRC Data Input 0 32 CRCCHKSUM CRC Checksum 0x8 32 0x00000000 CRCCHKSUM CRC Checksum 0 32 CRCSTATUS CRC Status 0xC 8 0x00 CRCBUSY CRC Module Busy 0 1 CRCZERO CRC Zero 1 1 DBGCTRL Debug Control 0xD 8 0x00 DBGRUN Debug Run 0 1 QOSCTRL QOS Control 0xE 8 0x2A WRBQOS Write-Back Quality of Service 0 2 WRBQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 FQOS Fetch Quality of Service 2 2 FQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 DQOS Data Transfer Quality of Service 4 2 DQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 SWTRIGCTRL Software Trigger Control 0x10 32 0x00000000 SWTRIG0 Channel 0 Software Trigger 0 1 SWTRIG1 Channel 1 Software Trigger 1 1 SWTRIG2 Channel 2 Software Trigger 2 1 SWTRIG3 Channel 3 Software Trigger 3 1 SWTRIG4 Channel 4 Software Trigger 4 1 SWTRIG5 Channel 5 Software Trigger 5 1 SWTRIG6 Channel 6 Software Trigger 6 1 SWTRIG7 Channel 7 Software Trigger 7 1 PRICTRL0 Priority Control 0 0x14 32 0x00000000 LVLPRI0 Level 0 Channel Priority Number 0 3 RRLVLEN0 Level 0 Round-Robin Scheduling Enable 7 1 LVLPRI1 Level 1 Channel Priority Number 8 3 RRLVLEN1 Level 1 Round-Robin Scheduling Enable 15 1 LVLPRI2 Level 2 Channel Priority Number 16 3 RRLVLEN2 Level 2 Round-Robin Scheduling Enable 23 1 LVLPRI3 Level 3 Channel Priority Number 24 3 RRLVLEN3 Level 3 Round-Robin Scheduling Enable 31 1 INTPEND Interrupt Pending 0x20 16 0x0000 ID Channel ID 0 3 TERR Transfer Error 8 1 TCMPL Transfer Complete 9 1 SUSP Channel Suspend 10 1 FERR Fetch Error 13 1 BUSY Busy 14 1 PEND Pending 15 1 INTSTATUS Interrupt Status 0x24 32 read-only 0x00000000 CHINT0 Channel 0 Pending Interrupt 0 1 CHINT1 Channel 1 Pending Interrupt 1 1 CHINT2 Channel 2 Pending Interrupt 2 1 CHINT3 Channel 3 Pending Interrupt 3 1 CHINT4 Channel 4 Pending Interrupt 4 1 CHINT5 Channel 5 Pending Interrupt 5 1 CHINT6 Channel 6 Pending Interrupt 6 1 CHINT7 Channel 7 Pending Interrupt 7 1 BUSYCH Busy Channels 0x28 32 read-only 0x00000000 BUSYCH0 Busy Channel 0 0 1 BUSYCH1 Busy Channel 1 1 1 BUSYCH2 Busy Channel 2 2 1 BUSYCH3 Busy Channel 3 3 1 BUSYCH4 Busy Channel 4 4 1 BUSYCH5 Busy Channel 5 5 1 BUSYCH6 Busy Channel 6 6 1 BUSYCH7 Busy Channel 7 7 1 PENDCH Pending Channels 0x2C 32 read-only 0x00000000 PENDCH0 Pending Channel 0 0 1 PENDCH1 Pending Channel 1 1 1 PENDCH2 Pending Channel 2 2 1 PENDCH3 Pending Channel 3 3 1 PENDCH4 Pending Channel 4 4 1 PENDCH5 Pending Channel 5 5 1 PENDCH6 Pending Channel 6 6 1 PENDCH7 Pending Channel 7 7 1 ACTIVE Active Channel and Levels 0x30 32 read-only 0x00000000 LVLEX0 Level 0 Channel Trigger Request Executing 0 1 LVLEX1 Level 1 Channel Trigger Request Executing 1 1 LVLEX2 Level 2 Channel Trigger Request Executing 2 1 LVLEX3 Level 3 Channel Trigger Request Executing 3 1 ID Active Channel ID 8 5 ABUSY Active Channel Busy 15 1 BTCNT Active Channel Block Transfer Count 16 16 BASEADDR Descriptor Memory Section Base Address 0x34 32 0x00000000 BASEADDR Descriptor Memory Base Address 0 32 WRBADDR Write-Back Memory Section Base Address 0x38 32 0x00000000 WRBADDR Write-Back Memory Base Address 0 32 CHID Channel ID 0x3F 8 0x00 ID Channel ID 0 3 CHCTRLA Channel Control A 0x40 8 0x00 SWRST Channel Software Reset 0 1 ENABLE Channel Enable 1 1 RUNSTDBY Channel run in standby 6 1 CHCTRLB Channel Control B 0x44 32 0x00000000 EVACT Event Input Action 0 3 EVACTSelect NOACT No action 0x0 TRIG Transfer and periodic transfer trigger 0x1 CTRIG Conditional transfer trigger 0x2 CBLOCK Conditional block transfer 0x3 SUSPEND Channel suspend operation 0x4 RESUME Channel resume operation 0x5 SSKIP Skip next block suspend action 0x6 EVIE Channel Event Input Enable 3 1 EVOE Channel Event Output Enable 4 1 LVL Channel Arbitration Level 5 2 TRIGSRC Trigger Source 8 5 TRIGSRCSelect DISABLE Only software/event triggers 0x00 TRIGACT Trigger Action 22 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0x0 BEAT One trigger required for each beat transfer 0x2 TRANSACTION One trigger required for each transaction 0x3 CMD Software Command 24 2 CMDSelect NOACT No action 0x0 SUSPEND Channel suspend operation 0x1 RESUME Channel resume operation 0x2 CHINTENCLR Channel Interrupt Enable Clear 0x4C 8 0x00 TERR Channel Transfer Error Interrupt Enable 0 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 SUSP Channel Suspend Interrupt Enable 2 1 CHINTENSET Channel Interrupt Enable Set 0x4D 8 0x00 TERR Channel Transfer Error Interrupt Enable 0 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 SUSP Channel Suspend Interrupt Enable 2 1 CHINTFLAG Channel Interrupt Flag Status and Clear 0x4E 8 0x00 TERR Channel Transfer Error 0 1 TCMPL Channel Transfer Complete 1 1 SUSP Channel Suspend 2 1 CHSTATUS Channel Status 0x4F 8 read-only 0x00 PEND Channel Pending 0 1 BUSY Channel Busy 1 1 FERR Channel Fetch Error 2 1 DSU U28101.0.0 Device Service Unit DSU DSU_ 0x41002000 0 0x2000 registers CTRL Control 0x0 8 write-only 0x00 SWRST Software Reset 0 1 CRC 32-bit Cyclic Redundancy Code 2 1 MBIST Memory built-in self-test 3 1 STATUSA Status A 0x1 8 0x00 DONE Done 0 1 CRSTEXT CPU Reset Phase Extension 1 1 BERR Bus Error 2 1 FAIL Failure 3 1 PERR Protection Error Detected by the State Machine 4 1 BREXT BootRom Phase Extension 5 1 STATUSB Status B 0x2 8 read-only 0x00 DAL Debugger Access Level 0 2 DALSelect SECURED 0x0 NS_DEBUG 0x1 FULL_DEBUG 0x2 DBGPRES Debugger Present 2 1 HPE Hot-Plugging Enable 3 1 DCCD0 Debug Communication Channel 0 Dirty 4 1 DCCD1 Debug Communication Channel 1 Dirty 5 1 BCCD0 Boot ROM Communication Channel 0 Dirty 6 1 BCCD1 Boot ROM Communication Channel 1 Dirty 7 1 STATUSC Status C 0x3 8 read-only 0x00 ADDR Address 0x4 32 0x00000000 AMOD Access Mode 0 2 ADDR Address 2 30 LENGTH Length 0x8 32 0x00000000 LENGTH Length 2 30 DATA Data 0xC 32 0x00000000 DATA Data 0 32 2 4 DCC[%s] Debug Communication Channel n 0x10 32 0x00000000 DATA Data 0 32 DID Device Identification 0x18 32 read-only 0x20830001 DEVSEL Device Select 0 8 REVISION Revision Number 8 4 DIE Die Number 12 4 SERIES Series 16 6 SERIESSelect 0 Cortex-M0+ processor, basic feature set 0 1 Cortex-M0+ processor, USB 1 FAMILY Family 23 5 FAMILYSelect 0 General purpose microcontroller 0 1 PicoPower 1 PROCESSOR Processor 28 4 PROCESSORSelect CM0P Cortex-M0+ 0x1 CM23 Cortex-M23 0x2 CM3 Cortex-M3 0x3 CM4 Cortex-M4 0x5 CM4F Cortex-M4 with FPU 0x6 CM33 Cortex-M33 0x7 CFG Configuration 0x1C 32 0x00000002 LQOS Latency Quality Of Service 0 2 DCCDMALEVEL DMA Trigger Level 2 2 DCCDMALEVELSelect EMPTY Trigger rises when DCC is empty 0 FULL Trigger rises when DCC is full 1 2 4 BCC[%s] Boot ROM Communication Channel n 0x20 32 0x00000000 DATA Data 0 32 2 4 DCFG[%s] Device Configuration 0xF0 32 0x00000000 DCFG Device Configuration 0 32 ENTRY0 CoreSight ROM Table Entry 0 0x1000 32 read-only 0x9F0FC002 EPRES Entry Present 0 1 FMT Format 1 1 ADDOFF Address Offset 12 20 ENTRY1 CoreSight ROM Table Entry 1 0x1004 32 read-only 0x00000000 END CoreSight ROM Table End 0x1008 32 read-only 0x00000000 END End Marker 0 32 MEMTYPE CoreSight ROM Table Memory Type 0x1FCC 32 read-only 0x00000000 SMEMP System Memory Present 0 1 PID4 Peripheral Identification 4 0x1FD0 32 read-only 0x00000000 JEPCC JEP-106 Continuation Code 0 4 FKBC 4KB count 4 4 PID5 Peripheral Identification 5 0x1FD4 32 read-only 0x00000000 PID6 Peripheral Identification 6 0x1FD8 32 read-only 0x00000000 PID7 Peripheral Identification 7 0x1FDC 32 read-only 0x00000000 PID0 Peripheral Identification 0 0x1FE0 32 read-only 0x000000D0 PARTNBL Part Number Low 0 8 PID1 Peripheral Identification 1 0x1FE4 32 read-only 0x000000FC PARTNBH Part Number High 0 4 JEPIDCL Low part of the JEP-106 Identity Code 4 4 PID2 Peripheral Identification 2 0x1FE8 32 read-only 0x00000009 JEPIDCH JEP-106 Identity Code High 0 3 JEPU JEP-106 Identity Code is used 3 1 REVISION Revision Number 4 4 PID3 Peripheral Identification 3 0x1FEC 32 read-only 0x00000000 CUSMOD ARM CUSMOD 0 4 REVAND Revision Number 4 4 CID0 Component Identification 0 0x1FF0 32 read-only 0x0000000D PREAMBLEB0 Preamble Byte 0 0 8 CID1 Component Identification 1 0x1FF4 32 read-only 0x00000010 PREAMBLE Preamble 0 4 CCLASS Component Class 4 4 CID2 Component Identification 2 0x1FF8 32 read-only 0x00000005 PREAMBLEB2 Preamble Byte 2 0 8 CID3 Component Identification 3 0x1FFC 32 read-only 0x000000B1 PREAMBLEB3 Preamble Byte 3 0 8 DSU_EXT DSU_EXT_ 0x41002100 EIC U28041.0.0 External Interrupt Controller EIC EIC_ 0x40002800 0 0x44 registers EIC_0 3 EIC_1 4 EIC_2 5 EIC_3 6 EIC_OTHER 7 CTRLA Control A 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 CKSEL Clock Selection 4 1 NMICTRL Non-Maskable Interrupt Control 0x1 8 0x00 NMISENSE Non-Maskable Interrupt Sense Configuration 0 3 NMISENSESelect NONE No detection 0 RISE Rising-edge detection 1 FALL Falling-edge detection 2 BOTH Both-edges detection 3 HIGH High-level detection 4 LOW Low-level detection 5 NMIFILTEN Non-Maskable Interrupt Filter Enable 3 1 NMIASYNCH Asynchronous Edge Detection Mode 4 1 NMIFLAG Non-Maskable Interrupt Flag Status and Clear 0x2 8 0x0000 NMI Non-Maskable Interrupt 0 1 SYNCBUSY Synchronization Busy 0x4 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy Status 0 1 ENABLE Enable Synchronization Busy Status 1 1 EVCTRL Event Control 0x8 32 0x00000000 EXTINTEO External Interrupt Event Output Enable 0 8 INTENCLR Interrupt Enable Clear 0xC 32 0x00000000 EXTINT External Interrupt Enable 0 8 NSCHK Non-secure Check Interrupt Enable 31 1 INTENSET Interrupt Enable Set 0x10 32 0x00000000 EXTINT External Interrupt Enable 0 8 NSCHK Non-secure Check Interrupt Enable 31 1 INTFLAG Interrupt Flag Status and Clear 0x14 32 0x00000000 EXTINT External Interrupt 0 8 NSCHK Non-secure Check Interrupt 31 1 ASYNCH External Interrupt Asynchronous Mode 0x18 32 0x00000000 ASYNCH Asynchronous Edge Detection Mode 0 8 1 4 CONFIG[%s] External Interrupt Sense Configuration 0x1C 32 0x00000000 SENSE0 Input Sense Configuration 0 0 3 SENSE0Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN0 Filter Enable 0 3 1 SENSE1 Input Sense Configuration 1 4 3 SENSE1Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN1 Filter Enable 1 7 1 SENSE2 Input Sense Configuration 2 8 3 SENSE2Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN2 Filter Enable 2 11 1 SENSE3 Input Sense Configuration 3 12 3 SENSE3Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN3 Filter Enable 3 15 1 SENSE4 Input Sense Configuration 4 16 3 SENSE4Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN4 Filter Enable 4 19 1 SENSE5 Input Sense Configuration 5 20 3 SENSE5Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN5 Filter Enable 5 23 1 SENSE6 Input Sense Configuration 6 24 3 SENSE6Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN6 Filter Enable 6 27 1 SENSE7 Input Sense Configuration 7 28 3 SENSE7Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN7 Filter Enable 7 31 1 DEBOUNCEN Debouncer Enable 0x30 32 0x00000000 DEBOUNCEN Debouncer Enable 0 8 DPRESCALER Debouncer Prescaler 0x34 32 0x00000000 PRESCALER0 Debouncer Prescaler 0 3 STATES0 Debouncer number of states 3 1 TICKON Pin Sampler frequency selection 16 1 PINSTATE Pin State 0x38 32 read-only 0x00000000 PINSTATE Pin State 0 8 NSCHK Non-secure Interrupt Check Enable 0x3C 32 0x00000000 EXTINT External Interrupt Nonsecure Check Enable 0 8 NMI Non-Maskable External Interrupt Nonsecure Check Enable 31 1 NONSEC Non-secure Interrupt 0x40 32 0x00000000 EXTINT External Interrupt Nonsecure Enable 0 8 NMI Non-Maskable Interrupt Nonsecure Enable 31 1 EIC_SEC EIC_SEC_ 0x40002A00 EVSYS U25042.0.0 Event System Interface EVSYS EVSYS_ 0x42000000 0 0x1F4 registers EVSYS_0 16 EVSYS_1 17 EVSYS_2 18 EVSYS_3 19 EVSYS_NSCHK 20 CTRLA Control 0x0 8 write-only 0x00 SWRST Software Reset 0 1 SWEVT Software Event 0x4 32 write-only 0x00000000 CHANNEL0 Channel 0 Software Selection 0 1 CHANNEL1 Channel 1 Software Selection 1 1 CHANNEL2 Channel 2 Software Selection 2 1 CHANNEL3 Channel 3 Software Selection 3 1 CHANNEL4 Channel 4 Software Selection 4 1 CHANNEL5 Channel 5 Software Selection 5 1 CHANNEL6 Channel 6 Software Selection 6 1 CHANNEL7 Channel 7 Software Selection 7 1 PRICTRL Priority Control 0x8 8 0x00 PRI Channel Priority Number 0 2 RREN Round-Robin Scheduling Enable 7 1 INTPEND Channel Pending Interrupt 0x10 16 0x4000 ID Channel ID 0 2 OVR Channel Overrun 8 1 EVD Channel Event Detected 9 1 READY Ready 14 1 BUSY Busy 15 1 INTSTATUS Interrupt Status 0x14 32 read-only 0x00000000 CHINT0 Channel 0 Pending Interrupt 0 1 CHINT1 Channel 1 Pending Interrupt 1 1 CHINT2 Channel 2 Pending Interrupt 2 1 CHINT3 Channel 3 Pending Interrupt 3 1 BUSYCH Busy Channels 0x18 32 read-only 0x00000000 BUSYCH0 Busy Channel 0 0 1 BUSYCH1 Busy Channel 1 1 1 BUSYCH2 Busy Channel 2 2 1 BUSYCH3 Busy Channel 3 3 1 READYUSR Ready Users 0x1C 32 read-only 0xFFFFFFFF READYUSR0 Ready User for Channel 0 0 1 READYUSR1 Ready User for Channel 1 1 1 READYUSR2 Ready User for Channel 2 2 1 READYUSR3 Ready User for Channel 3 3 1 8 0x8 CHANNEL[%s] 0x020 CHANNEL Channel n Control 0x0 32 0x00008000 EVGEN Event Generator Selection 0 6 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 RUNSTDBY Run in standby 14 1 ONDEMAND Generic Clock On Demand 15 1 CHINTENCLR Channel n Interrupt Enable Clear 0x4 8 0x00 OVR Channel Overrun Interrupt Disable 0 1 EVD Channel Event Detected Interrupt Disable 1 1 CHINTENSET Channel n Interrupt Enable Set 0x5 8 0x00 OVR Channel Overrun Interrupt Enable 0 1 EVD Channel Event Detected Interrupt Enable 1 1 CHINTFLAG Channel n Interrupt Flag Status and Clear 0x6 8 0x00 OVR Channel Overrun 0 1 EVD Channel Event Detected 1 1 CHSTATUS Channel n Status 0x7 8 read-only 0x01 RDYUSR Ready User 0 1 BUSYCH Busy Channel 1 1 23 1 USER[%s] User Multiplexer n 0x120 8 0x00 CHANNEL Channel Event Selection 0 4 INTENCLR Interrupt Enable Clear 0x1D4 8 0x00000000 NSCHK Non-Secure Check Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x1D5 8 0x00000000 NSCHK Non-Secure Check Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x1D6 8 0x00000000 NSCHK Non-Secure Check 0 1 NONSECCHAN Channels Security Attribution 0x1D8 32 0x00000000 CHANNEL0 Non-Secure for Channel 0 0 1 CHANNEL1 Non-Secure for Channel 1 1 1 CHANNEL2 Non-Secure for Channel 2 2 1 CHANNEL3 Non-Secure for Channel 3 3 1 CHANNEL4 Non-Secure for Channel 4 4 1 CHANNEL5 Non-Secure for Channel 5 5 1 CHANNEL6 Non-Secure for Channel 6 6 1 CHANNEL7 Non-Secure for Channel 7 7 1 NSCHKCHAN Non-Secure Channels Check 0x1DC 32 0x00000000 CHANNEL0 Channel 0 to be checked as non-secured 0 1 CHANNEL1 Channel 1 to be checked as non-secured 1 1 CHANNEL2 Channel 2 to be checked as non-secured 2 1 CHANNEL3 Channel 3 to be checked as non-secured 3 1 CHANNEL4 Channel 4 to be checked as non-secured 4 1 CHANNEL5 Channel 5 to be checked as non-secured 5 1 CHANNEL6 Channel 6 to be checked as non-secured 6 1 CHANNEL7 Channel 7 to be checked as non-secured 7 1 1 4 NONSECUSER[%s] Users Security Attribution 0x1E0 32 0x00000000 USER0 Non-Secure for User 0 0 1 USER1 Non-Secure for User 1 1 1 USER2 Non-Secure for User 2 2 1 USER3 Non-Secure for User 3 3 1 USER4 Non-Secure for User 4 4 1 USER5 Non-Secure for User 5 5 1 USER6 Non-Secure for User 6 6 1 USER7 Non-Secure for User 7 7 1 USER8 Non-Secure for User 8 8 1 USER9 Non-Secure for User 9 9 1 USER10 Non-Secure for User 10 10 1 USER11 Non-Secure for User 11 11 1 USER12 Non-Secure for User 12 12 1 USER13 Non-Secure for User 13 13 1 USER14 Non-Secure for User 14 14 1 USER15 Non-Secure for User 15 15 1 USER16 Non-Secure for User 16 16 1 USER17 Non-Secure for User 17 17 1 USER18 Non-Secure for User 18 18 1 USER19 Non-Secure for User 19 19 1 USER20 Non-Secure for User 20 20 1 USER21 Non-Secure for User 21 21 1 USER22 Non-Secure for User 22 22 1 1 4 NSCHKUSER[%s] Non-Secure Users Check 0x1F0 32 0x00000000 USER0 User 0 to be checked as non-secured 0 1 USER1 User 1 to be checked as non-secured 1 1 USER2 User 2 to be checked as non-secured 2 1 USER3 User 3 to be checked as non-secured 3 1 USER4 User 4 to be checked as non-secured 4 1 USER5 User 5 to be checked as non-secured 5 1 USER6 User 6 to be checked as non-secured 6 1 USER7 User 7 to be checked as non-secured 7 1 USER8 User 8 to be checked as non-secured 8 1 USER9 User 9 to be checked as non-secured 9 1 USER10 User 10 to be checked as non-secured 10 1 USER11 User 11 to be checked as non-secured 11 1 USER12 User 12 to be checked as non-secured 12 1 USER13 User 13 to be checked as non-secured 13 1 USER14 User 14 to be checked as non-secured 14 1 USER15 User 15 to be checked as non-secured 15 1 USER16 User 16 to be checked as non-secured 16 1 USER17 User 17 to be checked as non-secured 17 1 USER18 User 18 to be checked as non-secured 18 1 USER19 User 19 to be checked as non-secured 19 1 USER20 User 20 to be checked as non-secured 20 1 USER21 User 21 to be checked as non-secured 21 1 USER22 User 22 to be checked as non-secured 22 1 EVSYS_SEC EVSYS_SEC_ 0x42000200 FREQM U22572.1.0 Frequency Meter FREQM FREQM_ 0x40002C00 0 0x14 registers FREQM 8 CTRLA Control A Register 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 CTRLB Control B Register 0x1 8 write-only 0x00 START Start Measurement 0 1 CFGA Config A register 0x2 16 0x0000 REFNUM Number of Reference Clock Cycles 0 8 DIVREF Divide Reference Clock 15 1 INTENCLR Interrupt Enable Clear Register 0x8 8 0x00 DONE Measurement Done Interrupt Enable 0 1 INTENSET Interrupt Enable Set Register 0x9 8 0x00 DONE Measurement Done Interrupt Enable 0 1 INTFLAG Interrupt Flag Register 0xA 8 0x00 DONE Measurement Done 0 1 STATUS Status Register 0xB 8 0x00 BUSY FREQM Status 0 1 OVF Sticky Count Value Overflow 1 1 SYNCBUSY Synchronization Busy Register 0xC 32 read-only 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 VALUE Count Value Register 0x10 32 read-only 0x00000000 VALUE Measurement Value 0 24 GCLK U21221.1.2 Generic Clock Generator GCLK GCLK_ 0x40001C00 0 0x104 registers CTRLA Control 0x0 8 0x00 SWRST Software Reset 0 1 SYNCBUSY Synchronization Busy 0x4 32 read-only 0x00000000 SWRST Software Reset Synchroniation Busy bit 0 1 GENCTRL0 Generic Clock Generator Control 0 Synchronization Busy bit 2 1 GENCTRL1 Generic Clock Generator Control 1 Synchronization Busy bit 3 1 GENCTRL2 Generic Clock Generator Control 2 Synchronization Busy bit 4 1 GENCTRL3 Generic Clock Generator Control 3 Synchronization Busy bit 5 1 GENCTRL4 Generic Clock Generator Control 4 Synchronization Busy bit 6 1 5 4 GENCTRL[%s] Generic Clock Generator Control 0x20 32 0x00000000 SRC Source Select 0 3 SRCSelect XOSC XOSC oscillator output 0 GCLKIN Generator input pad 1 GCLKGEN1 Generic clock generator 1 output 2 OSCULP32K OSCULP32K oscillator output 3 XOSC32K XOSC32K oscillator output 4 OSC16M OSC16M oscillator output 5 DFLLULP DFLLULP output 6 FDPLL96M FDPLL output 7 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OOV Output Off Value 10 1 OE Output Enable 11 1 DIVSEL Divide Selection 12 1 RUNSTDBY Run in Standby 13 1 DIV Division Factor 16 16 21 4 PCHCTRL[%s] Peripheral Clock Control 0x80 32 0x00000000 GEN Generic Clock Generator 0 3 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 CHEN Channel Enable 6 1 WRTLOCK Write Lock 7 1 IDAU U28031.0.0 Implementation Defined Attribution Unit IDAU IDAU_ 0x41000000 0 0xD registers SECCTRL SECCTRL 0x1 8 0x03 RXN CPU RAM is eXecute Never 2 1 SCFGB SCFGB 0x4 32 0x00000000 BS Boot Secure 0 8 BNSC Boot Secure, Non-secure Callable 8 6 BOOTPROT Boot Protection 16 8 SCFGA SCFGA 0x8 32 0x00000000 AS Application Secure 0 8 ANSC Application Secure, Non-secure Callable 8 6 DS DATAFLASH Data Secure 16 4 SCFGR SCFGR 0xC 8 0x00 RS RAM Secure 0 7 MCLK U22343.0.0 Main Clock MCLK MCLK_ 0x40000800 0 0x20 registers CTRLA Control 0x0 8 0x00 CKSEL Clock Select 2 1 INTENCLR Interrupt Enable Clear 0x1 8 0x00 CKRDY Clock Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x2 8 0x00 CKRDY Clock Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x3 8 0x01 CKRDY Clock Ready 0 1 CPUDIV CPU Clock Division 0x4 8 0x01 CPUDIV CPU Clock Division Factor 0 8 CPUDIVSelect DIV1 Divide by 1 0x01 DIV2 Divide by 2 0x02 DIV4 Divide by 4 0x04 DIV8 Divide by 8 0x08 DIV16 Divide by 16 0x10 DIV32 Divide by 32 0x20 DIV64 Divide by 64 0x40 DIV128 Divide by 128 0x80 AHBMASK AHB Mask 0x10 32 0x00001FFF HPB0_ HPB0 AHB Clock Mask 0 1 HPB1_ HPB1 AHB Clock Mask 1 1 HPB2_ HPB2 AHB Clock Mask 2 1 DMAC_ DMAC AHB Clock Mask 3 1 DSU_ DSU AHB Clock Mask 4 1 PAC_ PAC AHB Clock Mask 6 1 NVMCTRL_ NVMCTRL AHB Clock Mask 7 1 TRAM_ TRAM AHB Clock Mask 12 1 APBAMASK APBA Mask 0x14 32 0x00007FFF PAC_ PAC APB Clock Enable 0 1 PM_ PM APB Clock Enable 1 1 MCLK_ MCLK APB Clock Enable 2 1 RSTC_ RSTC APB Clock Enable 3 1 OSCCTRL_ OSCCTRL APB Clock Enable 4 1 OSC32KCTRL_ OSC32KCTRL APB Clock Enable 5 1 SUPC_ SUPC APB Clock Enable 6 1 GCLK_ GCLK APB Clock Enable 7 1 WDT_ WDT APB Clock Enable 8 1 RTC_ RTC APB Clock Enable 9 1 EIC_ EIC APB Clock Enable 10 1 FREQM_ FREQM APB Clock Enable 11 1 PORT_ PORT APB Clock Enable 12 1 AC_ AC APB Clock Enable 13 1 APBBMASK APBB Mask 0x18 32 0x00000017 IDAU_ IDAU APB Clock Enable 0 1 DSU_ DSU APB Clock Enable 1 1 NVMCTRL_ NVMCTRL APB Clock Enable 2 1 APBCMASK APBC Mask 0x1C 32 0x00001FFF EVSYS_ EVSYS APB Clock Enable 0 1 SERCOM0_ SERCOM0 APB Clock Enable 1 1 SERCOM1_ SERCOM1 APB Clock Enable 2 1 SERCOM2_ SERCOM2 APB Clock Enable 3 1 TC0_ TC0 APB Clock Enable 4 1 TC1_ TC1 APB Clock Enable 5 1 TC2_ TC2 APB Clock Enable 6 1 ADC_ ADC APB Clock Enable 7 1 DAC_ DAC APB Clock Enable 8 1 PTC_ PTC APB Clock Enable 9 1 TRNG_ TRNG APB Clock Enable 10 1 CCL_ CCL APB Clock Enable 11 1 OPAMP_ OPAMP APB Clock Enable 12 1 NVMCTRL U28021.0.0 Non-Volatile Memory Controller NVMCTRL NVMCTRL_ 0x41004000 0 0x48 registers NVMCTRL 9 CTRLA Control A 0x0 16 write-only 0x0000 CMD Command 0 7 CMDSelect ER Erase Row - Erases the row addressed by the ADDR register. 0x02 WP Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. 0x04 SPRM Sets the power reduction mode. 0x42 CPRM Clears the power reduction mode. 0x43 PBC Page Buffer Clear - Clears the page buffer. 0x44 INVALL Invalidate all cache lines. 0x46 SDAL0 Set DAL=0 0x4B SDAL1 Set DAL=1 0x4C CMDEX Command Execution 8 8 CMDEXSelect KEY Execution Key 0xA5 CTRLB Control B 0x4 32 0x00000000 RWS NVM Read Wait States 1 4 SLEEPPRM Power Reduction Mode during Sleep 8 2 SLEEPPRMSelect WAKEONACCESS NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. 0 WAKEUPINSTANT NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. 1 DISABLED Auto power reduction disabled. 3 FWUP fast wake-up 11 1 READMODE NVMCTRL Read Mode 16 2 READMODESelect NO_MISS_PENALTY The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. 0x0 LOW_POWER Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. 0x1 DETERMINISTIC The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. 0x2 CACHEDIS Cache Disable 18 1 QWEN Quick Write Enable 19 1 CTRLC Control C 0x8 8 0x01 MANW Manual Write 0 1 EVCTRL Event Control 0xA 8 0x00 AUTOWEI Auto Write Event Enable 0 1 AUTOWINV Auto Write Event Polarity Inverted 1 1 INTENCLR Interrupt Enable Clear 0xC 8 0x00 DONE NVM Done Interrupt Clear 0 1 PROGE Programming Error Status Interrupt Clear 1 1 LOCKE Lock Error Status Interrupt Clear 2 1 NVME NVM Error Interrupt Clear 3 1 KEYE Key Write Error Interrupt Clear 4 1 NSCHK NS configuration change detected Interrupt Clear 5 1 INTENSET Interrupt Enable Set 0x10 8 0x00 DONE NVM Done Interrupt Enable 0 1 PROGE Programming Error Status Interrupt Enable 1 1 LOCKE Lock Error Status Interrupt Enable 2 1 NVME NVM Error Interrupt Enable 3 1 KEYE Key Write Error Interrupt Enable 4 1 NSCHK NS configuration change detected Interrupt Enable 5 1 INTFLAG Interrupt Flag Status and Clear 0x14 8 0x00 DONE NVM Done 0 1 PROGE Programming Error Status 1 1 LOCKE Lock Error Status 2 1 NVME NVM Error 3 1 KEYE KEY Write Error 4 1 NSCHK NS configuration change detected 5 1 STATUS Status 0x18 16 read-only 0x0000 PRM Power Reduction Mode 0 1 LOAD NVM Page Buffer Active Loading 1 1 READY NVM Ready 2 1 DALFUSE Debug Access Level Fuse 3 2 ADDR Address 0x1C 32 0x00000000 AOFFSET NVM Address Offset In The Selected Array 0 16 ARRAY Array Select 22 2 ARRAYSelect FLASH FLASH Array 0x0 DATAFLASH DATA FLASH Array 0x1 AUX Auxilliary Space 0x2 SULCK Secure Unlock Register 0x20 16 BS Secure Boot Region 0 1 AS Secure Application Region 1 1 DS Data Secure Region 2 1 SLKEY Write Key 8 8 SLKEYSelect KEY Write Key 0xA5 NSULCK Non-Secure Unlock Register 0x22 16 BNS Non-Secure Boot Region 0 1 ANS Non-Secure Application Region 1 1 DNS Non-Secure Data Region 2 1 NSLKEY Write Key 8 8 NSLKEYSelect KEY Write Key 0xA5 PARAM NVM Parameter 0x24 32 0x00000000 FLASHP FLASH Pages 0 16 PSZ Page Size 16 3 PSZSelect 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 DFLASHP DATAFLASH Pages 20 12 DSCC Data Scramble Configuration 0x30 32 write-only 0x00000000 DSCKEY Data Scramble Key 0 30 SECCTRL Security Control 0x34 32 0x00000030 TAMPEEN Tamper Erase Enable 0 1 SILACC Silent Access 2 1 DSCEN Data Scramble Enable 3 1 DXN Data Flash is eXecute Never 6 1 TEROW Tamper Rease Row 8 3 KEY Write Key 24 8 KEYSelect KEY Write Key 0xA5 SCFGB Secure Boot Configuration 0x38 32 0x00000003 BCREN Boot Configuration Row Read Enable 0 1 BCWEN Boot Configuration Row Write Enable 1 1 SCFGAD Secure Application and Data Configuration 0x3C 32 0x00000001 URWEN User Row Write Enable 0 1 NONSEC Non-secure Write Enable 0x40 32 0x00000001 WRITE Non-secure APB alias write enable, non-secure AHB writes to non-secure regions enable 0 1 NSCHK Non-secure Write Reference Value 0x44 32 0x00000001 WRITE Reference value to be checked against NONSEC.WRITE 0 1 NVMCTRL_SEC NVMCTRL_SEC_ 0x41005000 OPAMP U22372.0.0 Operational Amplifier OPAMP OPAMP_ 0x42003000 0 0x11 registers CTRLA Control A 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 LPMUX Low-Power Mux 7 1 STATUS Status 0x2 8 read-only 0x00 READY0 OPAMP 0 Ready 0 1 READY1 OPAMP 1 Ready 1 1 READY2 OPAMP 2 Ready 2 1 3 4 OPAMPCTRL[%s] OPAMP n Control 0x4 32 0x00000000 ENABLE Operational Amplifier Enable 1 1 ANAOUT Analog Output 2 1 BIAS Bias Selection 3 2 RES2VCC Resistor ladder To VCC 5 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 RES2OUT Resistor ladder To Output 8 1 RES1EN Resistor 1 Enable 9 1 RES1MUX Resistor 1 Mux 10 3 POTMUX Potentiometer Selection 13 3 MUXPOS Positive Input Mux Selection 16 4 MUXNEG Negative Input Mux Selection 20 4 RESCTRL Resister Control 0x10 8 0x00 RES2OUT Resistor ladder To Output 0 1 RES1EN Resistor 1 Enable 1 1 RES1MUX Resistor 1 Mux 2 1 POTMUX Potentiometer Selection 3 3 REFBUFLEVEL Reference output voltage level select 6 2 OSCCTRL U21194.0.0 Oscillators Control OSCCTRL OSCCTRL_ 0x40001000 0 0x41 registers EVCTRL Event Control 0x0 8 0x00 CFDEO Clock Failure Detector Event Output Enable 0 1 TUNEEI Tune Event Input Enable 1 1 TUNEINV Tune Event Input Invert 2 1 INTENCLR Interrupt Enable Clear 0x4 32 0x00000000 XOSCRDY XOSC Ready Interrupt Enable 0 1 XOSCFAIL XOSC Clock Failure Detector Interrupt Enable 1 1 OSC16MRDY OSC16M Ready Interrupt Enable 4 1 DFLLULPRDY DFLLULP Ready interrupt Enable 8 1 DFLLULPLOCK DFLLULP Lock Interrupt Enable 9 1 DFLLULPNOLOCK DFLLULP No Lock Interrupt Enable 10 1 DPLLLCKR DPLL Lock Rise Interrupt Enable 16 1 DPLLLCKF DPLL Lock Fall Interrupt Enable 17 1 DPLLLTO DPLL Lock Timeout Interrupt Enable 18 1 DPLLLDRTO DPLL Loop Divider Ratio Update Complete Interrupt Enable 19 1 INTENSET Interrupt Enable Set 0x8 32 0x00000000 XOSCRDY XOSC Ready Interrupt Enable 0 1 XOSCFAIL XOSC Clock Failure Detector Interrupt Enable 1 1 OSC16MRDY OSC16M Ready Interrupt Enable 4 1 DFLLULPRDY DFLLULP Ready interrupt Enable 8 1 DFLLULPLOCK DFLLULP Lock Interrupt Enable 9 1 DFLLULPNOLOCK DFLLULP No Lock Interrupt Enable 10 1 DPLLLCKR DPLL Lock Rise Interrupt Enable 16 1 DPLLLCKF DPLL Lock Fall Interrupt Enable 17 1 DPLLLTO DPLL Lock Timeout Interrupt Enable 18 1 DPLLLDRTO DPLL Loop Divider Ratio Update Complete Interrupt Enable 19 1 INTFLAG Interrupt Flag Status and Clear 0xC 32 0x00000000 XOSCRDY XOSC Ready 0 1 XOSCFAIL XOSC Clock Failure Detector 1 1 OSC16MRDY OSC16M Ready 4 1 DFLLULPRDY DFLLULP Ready 8 1 DFLLULPLOCK DFLLULP Lock 9 1 DFLLULPNOLOCK DFLLULP No Lock 10 1 DPLLLCKR DPLL Lock Rise 16 1 DPLLLCKF DPLL Lock Fall 17 1 DPLLLTO DPLL Lock Timeout 18 1 DPLLLDRTO DPLL Loop Divider Ratio Update Complete 19 1 STATUS Status 0x10 32 read-only 0x00000000 XOSCRDY XOSC Ready 0 1 XOSCFAIL XOSC Clock Failure Detector 1 1 XOSCCKSW XOSC Clock Switch 2 1 OSC16MRDY OSC16M Ready 4 1 DFLLULPRDY DFLLULP Ready 8 1 DFLLULPLOCK DFLLULP Lock 9 1 DFLLULPNOLOCK DFLLULP No Lock 10 1 DPLLLCKR DPLL Lock Rise 16 1 DPLLLCKF DPLL Lock Fall 17 1 DPLLTO DPLL Lock Timeout 18 1 DPLLLDRTO DPLL Loop Divider Ratio Update Complete 19 1 XOSCCTRL External Multipurpose Crystal Oscillator (XOSC) Control 0x14 16 0x0080 ENABLE Oscillator Enable 1 1 XTALEN Crystal Oscillator Enable 2 1 CFDEN Clock Failure Detector Enable 3 1 SWBEN Xosc Clock Switch Enable 4 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 GAIN Oscillator Gain 8 3 AMPGC Automatic Amplitude Gain Control 11 1 STARTUP Start-Up Time 12 4 CFDPRESC Clock Failure Detector Prescaler 0x16 8 0x00 CFDPRESC Clock Failure Detector Prescaler 0 3 OSC16MCTRL 16MHz Internal Oscillator (OSC16M) Control 0x18 8 0x82 ENABLE Oscillator Enable 1 1 FSEL Oscillator Frequency Selection 2 2 FSELSelect 4 4MHz 0x0 8 8MHz 0x1 12 12MHz 0x2 16 16MHz 0x3 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 DFLLULPCTRL DFLLULP Control 0x1C 16 0x0504 ENABLE Enable 1 1 BINSE Binary Search Enable 3 1 SAFE Tuner Safe Mode 4 1 DITHER Tuner Dither Mode 5 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand 7 1 DIV Division Factor 8 3 DIVSelect DIV1 Frequency Divided by 1 0x0 DIV2 Frequency Divided by 2 0x1 DIV4 Frequency Divided by 4 0x2 DIV8 Frequency Divided by 8 0x3 DIV16 Frequency Divided by 16 0x4 DIV32 Frequency Divided by 32 0x5 DFLLULPDITHER DFLLULP Dither Control 0x1E 8 0x00 STEP Dither Step 0 3 STEPSelect STEP1 Dither Step = 1 0x0 STEP2 Dither Step = 2 0x1 STEP4 Dither Step = 4 0x2 STEP8 Dither Step = 8 0x3 PER Dither Period 4 3 PERSelect PER1 Dither Over 1 Reference Clock Period 0x0 PER2 Dither Over 2 Reference Clock Period 0x1 PER4 Dither Over 4 Reference Clock Period 0x2 PER8 Dither Over 8 Reference Clock Period 0x3 PER16 Dither Over 16 Reference Clock Period 0x4 PER32 Dither Over 32 Reference Clock Period 0x5 DFLLULPRREQ DFLLULP Read Request 0x1F 8 0x00 RREQ Read Request 7 1 DFLLULPDLY DFLLULP Delay Value 0x20 32 0x00000080 DELAY Delay Value 0 8 DFLLULPRATIO DFLLULP Target Ratio 0x24 32 0x00000000 RATIO Target Tuner Ratio 0 11 DFLLULPSYNCBUSY DFLLULP Synchronization Busy 0x28 32 read-only 0x00000000 ENABLE Enable Bit Synchronization Busy 1 1 TUNE Tune Bit Synchronization Busy 2 1 DELAY Delay Register Synchronization Busy 3 1 DPLLCTRLA DPLL Control A 0x2C 8 0x80 ENABLE DPLL Enable 1 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Clock Activation 7 1 DPLLRATIO DPLL Ratio Control 0x30 32 0x00000000 LDR Loop Divider Ratio 0 12 LDRFRAC Loop Divider Ratio Fractional Part 16 4 DPLLCTRLB DPLL Control B 0x34 32 0x00000000 FILTER Proportional Integral Filter Selection 0 2 FILTERSelect Default Default Filter Mode 0 LBFILT Low Bandwidth Filter 1 HBFILT High Bandwidth Filter 2 HDFILT High Damping Filter 3 LPEN Low-Power Enable 2 1 WUF Wake Up Fast 3 1 REFCLK Reference Clock Selection 4 2 REFCLKSelect XOSC32K XOSC32K Clock Reference 0 XOSC XOSC Clock Reference 1 GCLK GCLK Clock Reference 2 LTIME Lock Time 8 3 LTIMESelect Default No time-out. Automatic lock 0 8MS Time-out if no lock within 8 ms 4 9MS Time-out if no lock within 9 ms 5 10MS Time-out if no lock within 10 ms 6 11MS Time-out if no lock within 11 ms 7 LBYPASS Lock Bypass 12 1 DIV Clock Divider 16 11 DPLLPRESC DPLL Prescaler 0x38 8 0x00 PRESC Output Clock Prescaler 0 2 PRESCSelect DIV1 DPLL output is divided by 1 0 DIV2 DPLL output is divided by 2 1 DIV4 DPLL output is divided by 4 2 DPLLSYNCBUSY DPLL Synchronization Busy 0x3C 8 read-only 0x00 ENABLE DPLL Enable Synchronization Status 1 1 DPLLRATIO DPLL Loop Divider Ratio Synchronization Status 2 1 DPLLPRESC DPLL Prescaler Synchronization Status 3 1 DPLLSTATUS DPLL Status 0x40 8 read-only 0x00 LOCK DPLL Lock 0 1 CLKRDY DPLL Clock Ready 1 1 OSC32KCTRL U22464.0.0 32k Oscillators Control OSC32KCTRL OSC32KCTRL_ 0x40001400 0 0x20 registers INTENCLR Interrupt Enable Clear 0x0 32 0x00000000 XOSC32KRDY XOSC32K Ready Interrupt Enable 0 1 CLKFAIL XOSC32K Clock Failure Detector Interrupt Enable 2 1 INTENSET Interrupt Enable Set 0x4 32 0x00000000 XOSC32KRDY XOSC32K Ready Interrupt Enable 0 1 CLKFAIL XOSC32K Clock Failure Detector Interrupt Enable 2 1 INTFLAG Interrupt Flag Status and Clear 0x8 32 0x00000000 XOSC32KRDY XOSC32K Ready 0 1 CLKFAIL XOSC32K Clock Failure Detector 2 1 STATUS Power and Clocks Status 0xC 32 read-only 0x00000000 XOSC32KRDY XOSC32K Ready 0 1 CLKFAIL XOSC32K Clock Failure Detector 2 1 CLKSW XOSC32K Clock switch 3 1 ULP32KSW OSCULP32K Clock Switch 4 1 RTCCTRL RTC Clock Selection 0x10 8 0x00 RTCSEL RTC Clock Selection 0 3 RTCSELSelect ULP1K 1.024kHz from 32kHz internal ULP oscillator 0 ULP32K 32.768kHz from 32kHz internal ULP oscillator 1 OSC1K 1.024kHz from 32.768kHz internal oscillator 2 OSC32K 32.768kHz from 32.768kHz internal oscillator 3 XOSC1K 1.024kHz from 32.768kHz internal oscillator 4 XOSC32K 32.768kHz from 32.768kHz external crystal oscillator 5 XOSC32K 32kHz External Crystal Oscillator (XOSC32K) Control 0x14 16 0x0080 ENABLE Oscillator Enable 1 1 XTALEN Crystal Oscillator Enable 2 1 EN32K 32kHz Output Enable 3 1 EN1K 1kHz Output Enable 4 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 STARTUP Oscillator Start-Up Time 8 3 WRTLOCK Write Lock 12 1 CFDCTRL Clock Failure Detector Control 0x16 8 0x00 CFDEN Clock Failure Detector Enable 0 1 SWBACK Clock Switch Back 1 1 CFDPRESC Clock Failure Detector Prescaler 2 1 EVCTRL Event Control 0x17 8 0x00 CFDEO Clock Failure Detector Event Output Enable 0 1 OSCULP32K 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control 0x1C 32 0x00000000 ULP32KSW OSCULP32K Clock Switch Enable 5 1 CALIB Oscillator Calibration 8 5 WRTLOCK Write Lock 15 1 PAC U21202.0.0 Peripheral Access Controller PAC PAC_ 0x40000000 0 0x80 registers PAC 21 WRCTRL Write control 0x0 32 0x00000000 PERID Peripheral identifier 0 16 KEY Peripheral access control key 16 8 KEYSelect OFF No action 0 CLR Clear protection 1 SET Set protection 2 SETLCK Set and lock protection 3 SETSEC Set IP secure 4 SETNONSEC Set IP non-secure 5 SECLOCK Lock IP security value 6 EVCTRL Event control 0x4 8 0x00 ERREO Peripheral acess error event output 0 1 INTENCLR Interrupt enable clear 0x8 8 0x00 ERR Peripheral access error interrupt disable 0 1 INTENSET Interrupt enable set 0x9 8 0x00 ERR Peripheral access error interrupt enable 0 1 INTFLAGAHB Bridge interrupt flag status 0x10 32 0x00000000 FLASH_ FLASH 0 1 HPB0_ HPB0 1 1 HPB1_ HPB1 2 1 HPB2_ HPB2 3 1 HSRAMCPU_ HSRAMCPU 4 1 HSRAMDMAC_ HSRAMDMAC 5 1 HSRAMDSU_ HSRAMDSU 6 1 INTFLAGA Peripheral interrupt flag status - Bridge A 0x14 32 0x00000000 PAC_ PAC 0 1 PM_ PM 1 1 MCLK_ MCLK 2 1 RSTC_ RSTC 3 1 OSCCTRL_ OSCCTRL 4 1 OSC32KCTRL_ OSC32KCTRL 5 1 SUPC_ SUPC 6 1 GCLK_ GCLK 7 1 WDT_ WDT 8 1 RTC_ RTC 9 1 EIC_ EIC 10 1 FREQM_ FREQM 11 1 PORT_ PORT 12 1 AC_ AC 13 1 INTFLAGB Peripheral interrupt flag status - Bridge B 0x18 32 0x00000000 IDAU_ IDAU 0 1 DSU_ DSU 1 1 NVMCTRL_ NVMCTRL 2 1 DMAC_ DMAC 3 1 INTFLAGC Peripheral interrupt flag status - Bridge C 0x1C 32 0x00000000 EVSYS_ EVSYS 0 1 SERCOM0_ SERCOM0 1 1 SERCOM1_ SERCOM1 2 1 SERCOM2_ SERCOM2 3 1 TC0_ TC0 4 1 TC1_ TC1 5 1 TC2_ TC2 6 1 ADC_ ADC 7 1 DAC_ DAC 8 1 PTC_ PTC 9 1 TRNG_ TRNG 10 1 CCL_ CCL 11 1 OPAMP_ OPAMP 12 1 TRAM_ TRAM 13 1 STATUSA Peripheral write protection status - Bridge A 0x34 32 read-only 0x0000C000 PAC_ PAC APB Protect Enable 0 1 PM_ PM APB Protect Enable 1 1 MCLK_ MCLK APB Protect Enable 2 1 RSTC_ RSTC APB Protect Enable 3 1 OSCCTRL_ OSCCTRL APB Protect Enable 4 1 OSC32KCTRL_ OSC32KCTRL APB Protect Enable 5 1 SUPC_ SUPC APB Protect Enable 6 1 GCLK_ GCLK APB Protect Enable 7 1 WDT_ WDT APB Protect Enable 8 1 RTC_ RTC APB Protect Enable 9 1 EIC_ EIC APB Protect Enable 10 1 FREQM_ FREQM APB Protect Enable 11 1 PORT_ PORT APB Protect Enable 12 1 AC_ AC APB Protect Enable 13 1 STATUSB Peripheral write protection status - Bridge B 0x38 32 read-only 0x00000002 IDAU_ IDAU APB Protect Enable 0 1 DSU_ DSU APB Protect Enable 1 1 NVMCTRL_ NVMCTRL APB Protect Enable 2 1 DMAC_ DMAC APB Protect Enable 3 1 STATUSC Peripheral write protection status - Bridge C 0x3C 32 read-only 0x00000000 EVSYS_ EVSYS APB Protect Enable 0 1 SERCOM0_ SERCOM0 APB Protect Enable 1 1 SERCOM1_ SERCOM1 APB Protect Enable 2 1 SERCOM2_ SERCOM2 APB Protect Enable 3 1 TC0_ TC0 APB Protect Enable 4 1 TC1_ TC1 APB Protect Enable 5 1 TC2_ TC2 APB Protect Enable 6 1 ADC_ ADC APB Protect Enable 7 1 DAC_ DAC APB Protect Enable 8 1 PTC_ PTC APB Protect Enable 9 1 TRNG_ TRNG APB Protect Enable 10 1 CCL_ CCL APB Protect Enable 11 1 OPAMP_ OPAMP APB Protect Enable 12 1 TRAM_ TRAM APB Protect Enable 13 1 NONSECA Peripheral non-secure status - Bridge A 0x54 32 read-only 0x00000000 PAC_ PAC Non-Secure 0 1 PM_ PM Non-Secure 1 1 MCLK_ MCLK Non-Secure 2 1 RSTC_ RSTC Non-Secure 3 1 OSCCTRL_ OSCCTRL Non-Secure 4 1 OSC32KCTRL_ OSC32KCTRL Non-Secure 5 1 SUPC_ SUPC Non-Secure 6 1 GCLK_ GCLK Non-Secure 7 1 WDT_ WDT Non-Secure 8 1 RTC_ RTC Non-Secure 9 1 EIC_ EIC Non-Secure 10 1 FREQM_ FREQM Non-Secure 11 1 PORT_ PORT Non-Secure 12 1 AC_ AC Non-Secure 13 1 NONSECB Peripheral non-secure status - Bridge B 0x58 32 read-only 0x00000002 IDAU_ IDAU Non-Secure 0 1 DSU_ DSU Non-Secure 1 1 NVMCTRL_ NVMCTRL Non-Secure 2 1 DMAC_ DMAC Non-Secure 3 1 NONSECC Peripheral non-secure status - Bridge C 0x5C 32 read-only 0x00000000 EVSYS_ EVSYS Non-Secure 0 1 SERCOM0_ SERCOM0 Non-Secure 1 1 SERCOM1_ SERCOM1 Non-Secure 2 1 SERCOM2_ SERCOM2 Non-Secure 3 1 TC0_ TC0 Non-Secure 4 1 TC1_ TC1 Non-Secure 5 1 TC2_ TC2 Non-Secure 6 1 ADC_ ADC Non-Secure 7 1 DAC_ DAC Non-Secure 8 1 PTC_ PTC Non-Secure 9 1 TRNG_ TRNG Non-Secure 10 1 CCL_ CCL Non-Secure 11 1 OPAMP_ OPAMP Non-Secure 12 1 TRAM_ TRAM Non-Secure 13 1 SECLOCKA Peripheral secure status locked - Bridge A 0x74 32 read-only 0x00000000 PAC_ PAC Secure Status Locked 0 1 PM_ PM Secure Status Locked 1 1 MCLK_ MCLK Secure Status Locked 2 1 RSTC_ RSTC Secure Status Locked 3 1 OSCCTRL_ OSCCTRL Secure Status Locked 4 1 OSC32KCTRL_ OSC32KCTRL Secure Status Locked 5 1 SUPC_ SUPC Secure Status Locked 6 1 GCLK_ GCLK Secure Status Locked 7 1 WDT_ WDT Secure Status Locked 8 1 RTC_ RTC Secure Status Locked 9 1 EIC_ EIC Secure Status Locked 10 1 FREQM_ FREQM Secure Status Locked 11 1 PORT_ PORT Secure Status Locked 12 1 AC_ AC Secure Status Locked 13 1 SECLOCKB Peripheral secure status locked - Bridge B 0x78 32 read-only 0x00000003 IDAU_ IDAU Secure Status Locked 0 1 DSU_ DSU Secure Status Locked 1 1 NVMCTRL_ NVMCTRL Secure Status Locked 2 1 DMAC_ DMAC Secure Status Locked 3 1 SECLOCKC Peripheral secure status locked - Bridge C 0x7C 32 read-only 0x00000000 EVSYS_ EVSYS Secure Status Locked 0 1 SERCOM0_ SERCOM0 Secure Status Locked 1 1 SERCOM1_ SERCOM1 Secure Status Locked 2 1 SERCOM2_ SERCOM2 Secure Status Locked 3 1 TC0_ TC0 Secure Status Locked 4 1 TC1_ TC1 Secure Status Locked 5 1 TC2_ TC2 Secure Status Locked 6 1 ADC_ ADC Secure Status Locked 7 1 DAC_ DAC Secure Status Locked 8 1 PTC_ PTC Secure Status Locked 9 1 TRNG_ TRNG Secure Status Locked 10 1 CCL_ CCL Secure Status Locked 11 1 OPAMP_ OPAMP Secure Status Locked 12 1 TRAM_ TRAM Secure Status Locked 13 1 PAC_SEC PAC_SEC_ 0x40000200 PM U22403.1.0 Power Manager PM PM_ 0x40000400 0 0xA registers SLEEPCFG Sleep Configuration 0x1 8 0x02 SLEEPMODE Sleep Mode 0 3 SLEEPMODESelect IDLE CPU, AHB, APB clocks are OFF 2 STANDBY All Clocks are OFF 4 OFF All power domains are powered OFF 6 PLCFG Performance Level Configuration 0x2 8 0x00 PLSEL Performance Level Select 0 2 PLSELSelect PL0 Performance Level 0 0x0 PL2 Performance Level 2 0x2 PLDIS Performance Level Disable 7 1 PWCFG Power Configuration 0x3 8 0x00 RAMPSWC RAM Power Switch Configuration 0 2 RAMPSWCSelect 16KB 16KB Available 0x0 12KB 12KB Available 0x1 8KB 8KB Available 0x2 4KB 4KB Available 0x3 INTENCLR Interrupt Enable Clear 0x4 8 0x00 PLRDY Performance Level Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x5 8 0x00 PLRDY Performance Level Ready interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 0x00 PLRDY Performance Level Ready 0 1 STDBYCFG Standby Configuration 0x8 16 0x0000 PDCFG Power Domain Configuration 0 1 PDCFGSelect DEFAULT PDSW power domain switching is handled by hardware. 0 PDSW PDSW is forced ACTIVE. 1 DPGPDSW Dynamic Power Gating for PDSW 4 1 DPGPDSWSelect 0 Dynamic Power Gating disabled 0 1 Dynamic Power Gating enabled 1 VREGSMOD Voltage Regulator Standby mode 6 2 VREGSMODSelect AUTO Automatic mode 0 PERFORMANCE Performance oriented 1 LP Low Power oriented 2 BBIASHS Back Bias for HSRAM 10 1 BBIASTR Back Bias for Trust RAM 12 1 PORT U22103.0.0 Port Module PORT PORT_ 0x40003000 0 0x80 registers PORT 10 1 0x80 GROUP[%s] 0x00 DIR Data Direction 0x0 32 0x00000000 DIR Port Data Direction 0 32 DIRCLR Data Direction Clear 0x4 32 0x00000000 DIRCLR Port Data Direction Clear 0 32 DIRSET Data Direction Set 0x8 32 0x00000000 DIRSET Port Data Direction Set 0 32 DIRTGL Data Direction Toggle 0xC 32 0x00000000 DIRTGL Port Data Direction Toggle 0 32 OUT Data Output Value 0x10 32 0x00000000 OUT PORT Data Output Value 0 32 OUTCLR Data Output Value Clear 0x14 32 0x00000000 OUTCLR PORT Data Output Value Clear 0 32 OUTSET Data Output Value Set 0x18 32 0x00000000 OUTSET PORT Data Output Value Set 0 32 OUTTGL Data Output Value Toggle 0x1C 32 0x00000000 OUTTGL PORT Data Output Value Toggle 0 32 IN Data Input Value 0x20 32 read-only 0x00000000 IN PORT Data Input Value 0 32 CTRL Control 0x24 32 0x00000000 SAMPLING Input Sampling Mode 0 32 WRCONFIG Write Configuration 0x28 32 write-only 0x00000000 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUXEN Peripheral Multiplexer Enable 16 1 INEN Input Enable 17 1 PULLEN Pull Enable 18 1 DRVSTR Output Driver Strength Selection 22 1 PMUX Peripheral Multiplexing 24 4 WRPMUX Write PMUX 28 1 WRPINCFG Write PINCFG 30 1 HWSEL Half-Word Select 31 1 EVCTRL Event Input Control 0x2C 32 0x00000000 PID0 PORT Event Pin Identifier 0 0 5 EVACT0 PORT Event Action 0 5 2 EVACT0Select OUT Event output to pin 0x0 SET Set output register of pin on event 0x1 CLR Clear output register of pin on event 0x2 TGL Toggle output register of pin on event 0x3 PORTEI0 PORT Event Input Enable 0 7 1 PID1 PORT Event Pin Identifier 1 8 5 EVACT1 PORT Event Action 1 13 2 PORTEI1 PORT Event Input Enable 1 15 1 PID2 PORT Event Pin Identifier 2 16 5 EVACT2 PORT Event Action 2 21 2 PORTEI2 PORT Event Input Enable 2 23 1 PID3 PORT Event Pin Identifier 3 24 5 EVACT3 PORT Event Action 3 29 2 PORTEI3 PORT Event Input Enable 3 31 1 16 1 PMUX[%s] Peripheral Multiplexing 0x30 8 0x00 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 32 1 PINCFG[%s] Pin Configuration 0x40 8 0x00 PMUXEN Peripheral Multiplexer Enable 0 1 INEN Input Enable 1 1 PULLEN Pull Enable 2 1 DRVSTR Output Driver Strength Selection 6 1 INTENCLR Interrupt Enable Clear 0x60 32 0x00000000 NSCHK Non-Secure Check Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x64 32 0x00000000 NSCHK Non-Secure Check Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x68 32 0x00000000 NSCHK Non-Secure Check 0 1 NONSEC Security Attribution 0x6C 32 0x00000000 NONSEC Port Security Attribution 0 32 NSCHK Security Attribution Check 0x70 32 0x00000000 NSCHK Port Security Attribution Check 0 32 PORT_SEC PORT_SEC_ 0x40003200 PORT_IOBUS PORT_IOBUS_ 0x60000000 PORT_IOBUS_SEC PORT_IOBUS_SEC_ 0x60000200 PTC U22155.0.0 Peripheral Touch Controller PTC PTC_ 0x42002400 0 0x1 reserved PTC 42 RSTC U22393.0.0 Reset Controller RSTC RSTC_ 0x40000C00 0 0x1 registers RCAUSE Reset Cause 0x0 8 read-only POR Power On Reset 0 1 BODCORE Brown Out CORE Detector Reset 1 1 BODVDD Brown Out VDD Detector Reset 2 1 EXT External Reset 4 1 WDT Watchdog Reset 5 1 SYST System Reset Request 6 1 RTC U22503.0.0 Real-Time Counter RTC RTC_ 0x40002400 0 0x70 registers RTC 2 MODE0 32-bit Counter with Single 32-bit Compare RtcMode0 0x0 CTRLA MODE0 Control A 0x0 16 0x0000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 MATCHCLR Clear on Match 7 1 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xB GPTRST GP Registers Reset On Tamper Enable 14 1 COUNTSYNC Count Read Synchronization Enable 15 1 CTRLB MODE0 Control B 0x2 16 0x0000 GP0EN General Purpose 0 Enable 0 1 DEBMAJ Debouncer Majority Enable 4 1 DEBASYNC Debouncer Asynchronous Enable 5 1 RTCOUT RTC Output Enable 6 1 DMAEN DMA Enable 7 1 DEBF Debounce Frequency 8 3 DEBFSelect DIV2 CLK_RTC_DEB = CLK_RTC/2 0x0 DIV4 CLK_RTC_DEB = CLK_RTC/4 0x1 DIV8 CLK_RTC_DEB = CLK_RTC/8 0x2 DIV16 CLK_RTC_DEB = CLK_RTC/16 0x3 DIV32 CLK_RTC_DEB = CLK_RTC/32 0x4 DIV64 CLK_RTC_DEB = CLK_RTC/64 0x5 DIV128 CLK_RTC_DEB = CLK_RTC/128 0x6 DIV256 CLK_RTC_DEB = CLK_RTC/256 0x7 ACTF Active Layer Frequency 12 3 ACTFSelect DIV2 CLK_RTC_OUT = CLK_RTC/2 0x0 DIV4 CLK_RTC_OUT = CLK_RTC/4 0x1 DIV8 CLK_RTC_OUT = CLK_RTC/8 0x2 DIV16 CLK_RTC_OUT = CLK_RTC/16 0x3 DIV32 CLK_RTC_OUT = CLK_RTC/32 0x4 DIV64 CLK_RTC_OUT = CLK_RTC/64 0x5 DIV128 CLK_RTC_OUT = CLK_RTC/128 0x6 DIV256 CLK_RTC_OUT = CLK_RTC/256 0x7 SEPTO Separate Tamper Outputs 15 1 EVCTRL MODE0 Event Control 0x4 32 0x00000000 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 CMPEO0 Compare 0 Event Output Enable 8 1 TAMPEREO Tamper Event Output Enable 14 1 OVFEO Overflow Event Output Enable 15 1 TAMPEVEI Tamper Event Input Enable 16 1 PERDEO Periodic Interval Daily Event Output Enable 24 1 INTENCLR MODE0 Interrupt Enable Clear 0x8 16 0x0000 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 CMP0 Compare 0 Interrupt Enable 8 1 TAMPER Tamper Enable 14 1 OVF Overflow Interrupt Enable 15 1 INTENSET MODE0 Interrupt Enable Set 0xA 16 0x0000 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 CMP0 Compare 0 Interrupt Enable 8 1 TAMPER Tamper Enable 14 1 OVF Overflow Interrupt Enable 15 1 INTFLAG MODE0 Interrupt Flag Status and Clear 0xC 16 0x0000 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 CMP0 Compare 0 8 1 TAMPER Tamper 14 1 OVF Overflow 15 1 DBGCTRL Debug Control 0xE 8 0x00 DBGRUN Run During Debug 0 1 SYNCBUSY MODE0 Synchronization Busy Status 0x10 32 read-only 0x00000000 SWRST Software Reset Busy 0 1 ENABLE Enable Bit Busy 1 1 FREQCORR FREQCORR Register Busy 2 1 COUNT COUNT Register Busy 3 1 COMP0 COMP 0 Register Busy 5 1 COUNTSYNC Count Synchronization Enable Bit Busy 15 1 GP0 General Purpose 0 Register Busy 16 1 GP1 General Purpose 1 Register Busy 17 1 FREQCORR Frequency Correction 0x14 8 0x00 VALUE Correction Value 0 7 SIGN Correction Sign 7 1 COUNT MODE0 Counter Value 0x18 32 0x00000000 COUNT Counter Value 0 32 1 4 COMP[%s] MODE0 Compare n Value 0x20 32 0x00000000 COMP Compare Value 0 32 2 4 GP[%s] General Purpose 0x40 32 0x00000000 GP General Purpose 0 32 TAMPCTRL Tamper Control 0x60 32 0x00000000 IN0ACT Tamper Input 0 Action 0 2 IN0ACTSelect OFF Off (Disabled) 0x0 WAKE Wake and set Tamper flag 0x1 CAPTURE Capture timestamp and set Tamper flag 0x2 ACTL Compare IN0 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag 0x3 IN1ACT Tamper Input 1 Action 2 2 IN1ACTSelect OFF Off (Disabled) 0x0 WAKE Wake and set Tamper flag 0x1 CAPTURE Capture timestamp and set Tamper flag 0x2 ACTL Compare IN1 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag 0x3 IN2ACT Tamper Input 2 Action 4 2 IN2ACTSelect OFF Off (Disabled) 0x0 WAKE Wake and set Tamper flag 0x1 CAPTURE Capture timestamp and set Tamper flag 0x2 ACTL Compare IN2 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag 0x3 IN3ACT Tamper Input 3 Action 6 2 IN3ACTSelect OFF Off (Disabled) 0x0 WAKE Wake and set Tamper flag 0x1 CAPTURE Capture timestamp and set Tamper flag 0x2 ACTL Compare IN3 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag 0x3 TAMLVL0 Tamper Level Select 0 16 1 TAMLVL1 Tamper Level Select 1 17 1 TAMLVL2 Tamper Level Select 2 18 1 TAMLVL3 Tamper Level Select 3 19 1 DEBNC0 Debouncer Enable 0 24 1 DEBNC1 Debouncer Enable 1 25 1 DEBNC2 Debouncer Enable 2 26 1 DEBNC3 Debouncer Enable 3 27 1 TIMESTAMP MODE0 Timestamp 0x64 32 read-only 0x00000000 COUNT Count Timestamp Value 0 32 TAMPID Tamper ID 0x68 32 0x00000000 TAMPID0 Tamper Input 0 Detected 0 1 TAMPID1 Tamper Input 1 Detected 1 1 TAMPID2 Tamper Input 2 Detected 2 1 TAMPID3 Tamper Input 3 Detected 3 1 TAMPEVT Tamper Event Detected 31 1 TAMPCTRLB Tamper Control B 0x6C 32 0x00000000 ALSI0 Active Layer Select Internal 0 0 1 ALSI1 Active Layer Select Internal 1 1 1 ALSI2 Active Layer Select Internal 2 2 1 ALSI3 Active Layer Select Internal 3 3 1 MODE1 16-bit Counter with Two 16-bit Compares MODE0 RtcMode1 0x0 CTRLA MODE1 Control A 0x0 16 0x0000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0 COUNT16 Mode 1: 16-bit Counter 1 CLOCK Mode 2: Clock/Calendar 2 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xB GPTRST GP Registers Reset On Tamper Enable 14 1 COUNTSYNC Count Read Synchronization Enable 15 1 CTRLB MODE1 Control B 0x2 16 0x0000 GP0EN General Purpose 0 Enable 0 1 DEBMAJ Debouncer Majority Enable 4 1 DEBASYNC Debouncer Asynchronous Enable 5 1 RTCOUT RTC Output Enable 6 1 DMAEN DMA Enable 7 1 DEBF Debounce Frequency 8 3 DEBFSelect DIV2 CLK_RTC_DEB = CLK_RTC/2 0x0 DIV4 CLK_RTC_DEB = CLK_RTC/4 0x1 DIV8 CLK_RTC_DEB = CLK_RTC/8 0x2 DIV16 CLK_RTC_DEB = CLK_RTC/16 0x3 DIV32 CLK_RTC_DEB = CLK_RTC/32 0x4 DIV64 CLK_RTC_DEB = CLK_RTC/64 0x5 DIV128 CLK_RTC_DEB = CLK_RTC/128 0x6 DIV256 CLK_RTC_DEB = CLK_RTC/256 0x7 ACTF Active Layer Frequency 12 3 ACTFSelect DIV2 CLK_RTC_OUT = CLK_RTC/2 0x0 DIV4 CLK_RTC_OUT = CLK_RTC/4 0x1 DIV8 CLK_RTC_OUT = CLK_RTC/8 0x2 DIV16 CLK_RTC_OUT = CLK_RTC/16 0x3 DIV32 CLK_RTC_OUT = CLK_RTC/32 0x4 DIV64 CLK_RTC_OUT = CLK_RTC/64 0x5 DIV128 CLK_RTC_OUT = CLK_RTC/128 0x6 DIV256 CLK_RTC_OUT = CLK_RTC/256 0x7 SEPTO Separate Tamper Outputs 15 1 EVCTRL MODE1 Event Control 0x4 32 0x00000000 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 CMPEO0 Compare 0 Event Output Enable 8 1 CMPEO1 Compare 1 Event Output Enable 9 1 TAMPEREO Tamper Event Output Enable 14 1 OVFEO Overflow Event Output Enable 15 1 TAMPEVEI Tamper Event Input Enable 16 1 PERDEO Periodic Interval Daily Event Output Enable 24 1 INTENCLR MODE1 Interrupt Enable Clear 0x8 16 0x0000 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 TAMPER Tamper Enable 14 1 OVF Overflow Interrupt Enable 15 1 INTENSET MODE1 Interrupt Enable Set 0xA 16 0x0000 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 TAMPER Tamper Enable 14 1 OVF Overflow Interrupt Enable 15 1 INTFLAG MODE1 Interrupt Flag Status and Clear 0xC 16 0x0000 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 CMP0 Compare 0 8 1 CMP1 Compare 1 9 1 TAMPER Tamper 14 1 OVF Overflow 15 1 DBGCTRL Debug Control 0xE 8 0x00 DBGRUN Run During Debug 0 1 SYNCBUSY MODE1 Synchronization Busy Status 0x10 32 read-only 0x00000000 SWRST Software Reset Bit Busy 0 1 ENABLE Enable Bit Busy 1 1 FREQCORR FREQCORR Register Busy 2 1 COUNT COUNT Register Busy 3 1 PER PER Register Busy 4 1 COMP0 COMP 0 Register Busy 5 1 COMP1 COMP 1 Register Busy 6 1 COUNTSYNC Count Synchronization Enable Bit Busy 15 1 GP0 General Purpose 0 Register Busy 16 1 GP1 General Purpose 1 Register Busy 17 1 FREQCORR Frequency Correction 0x14 8 0x00 VALUE Correction Value 0 7 SIGN Correction Sign 7 1 COUNT MODE1 Counter Value 0x18 16 0x0000 COUNT Counter Value 0 16 PER MODE1 Counter Period 0x1C 16 0x0000 PER Counter Period 0 16 2 2 COMP[%s] MODE1 Compare n Value 0x20 16 0x0000 COMP Compare Value 0 16 2 4 GP[%s] General Purpose 0x40 32 0x00000000 GP General Purpose 0 32 TAMPCTRL Tamper Control 0x60 32 0x00000000 IN0ACT Tamper Input 0 Action 0 2 IN0ACTSelect OFF Off (Disabled) 0x0 WAKE Wake and set Tamper flag 0x1 CAPTURE Capture timestamp and set Tamper flag 0x2 ACTL Compare IN0 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag 0x3 IN1ACT Tamper Input 1 Action 2 2 IN1ACTSelect OFF Off (Disabled) 0x0 WAKE Wake and set Tamper flag 0x1 CAPTURE Capture timestamp and set Tamper flag 0x2 ACTL Compare IN1 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag 0x3 IN2ACT Tamper Input 2 Action 4 2 IN2ACTSelect OFF Off (Disabled) 0x0 WAKE Wake and set Tamper flag 0x1 CAPTURE Capture timestamp and set Tamper flag 0x2 ACTL Compare IN2 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag 0x3 IN3ACT Tamper Input 3 Action 6 2 IN3ACTSelect OFF Off (Disabled) 0x0 WAKE Wake and set Tamper flag 0x1 CAPTURE Capture timestamp and set Tamper flag 0x2 ACTL Compare IN3 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag 0x3 TAMLVL0 Tamper Level Select 0 16 1 TAMLVL1 Tamper Level Select 1 17 1 TAMLVL2 Tamper Level Select 2 18 1 TAMLVL3 Tamper Level Select 3 19 1 DEBNC0 Debouncer Enable 0 24 1 DEBNC1 Debouncer Enable 1 25 1 DEBNC2 Debouncer Enable 2 26 1 DEBNC3 Debouncer Enable 3 27 1 TIMESTAMP MODE1 Timestamp 0x64 32 read-only 0x00000000 COUNT Count Timestamp Value 0 16 TAMPID Tamper ID 0x68 32 0x00000000 TAMPID0 Tamper Input 0 Detected 0 1 TAMPID1 Tamper Input 1 Detected 1 1 TAMPID2 Tamper Input 2 Detected 2 1 TAMPID3 Tamper Input 3 Detected 3 1 TAMPEVT Tamper Event Detected 31 1 TAMPCTRLB Tamper Control B 0x6C 32 0x00000000 ALSI0 Active Layer Select Internal 0 0 1 ALSI1 Active Layer Select Internal 1 1 1 ALSI2 Active Layer Select Internal 2 2 1 ALSI3 Active Layer Select Internal 3 3 1 MODE2 Clock/Calendar with Alarm MODE0 RtcMode2 0x0 CTRLA MODE2 Control A 0x0 16 0x0000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0 COUNT16 Mode 1: 16-bit Counter 1 CLOCK Mode 2: Clock/Calendar 2 CLKREP Clock Representation 6 1 MATCHCLR Clear on Match 7 1 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xB GPTRST GP Registers Reset On Tamper Enable 14 1 CLOCKSYNC Clock Read Synchronization Enable 15 1 CTRLB MODE2 Control B 0x2 16 0x0000 GP0EN General Purpose 0 Enable 0 1 DEBMAJ Debouncer Majority Enable 4 1 DEBASYNC Debouncer Asynchronous Enable 5 1 RTCOUT RTC Output Enable 6 1 DMAEN DMA Enable 7 1 DEBF Debounce Frequency 8 3 DEBFSelect DIV2 CLK_RTC_DEB = CLK_RTC/2 0x0 DIV4 CLK_RTC_DEB = CLK_RTC/4 0x1 DIV8 CLK_RTC_DEB = CLK_RTC/8 0x2 DIV16 CLK_RTC_DEB = CLK_RTC/16 0x3 DIV32 CLK_RTC_DEB = CLK_RTC/32 0x4 DIV64 CLK_RTC_DEB = CLK_RTC/64 0x5 DIV128 CLK_RTC_DEB = CLK_RTC/128 0x6 DIV256 CLK_RTC_DEB = CLK_RTC/256 0x7 ACTF Active Layer Frequency 12 3 ACTFSelect DIV2 CLK_RTC_OUT = CLK_RTC/2 0x0 DIV4 CLK_RTC_OUT = CLK_RTC/4 0x1 DIV8 CLK_RTC_OUT = CLK_RTC/8 0x2 DIV16 CLK_RTC_OUT = CLK_RTC/16 0x3 DIV32 CLK_RTC_OUT = CLK_RTC/32 0x4 DIV64 CLK_RTC_OUT = CLK_RTC/64 0x5 DIV128 CLK_RTC_OUT = CLK_RTC/128 0x6 DIV256 CLK_RTC_OUT = CLK_RTC/256 0x7 SEPTO Separate Tamper Outputs 15 1 EVCTRL MODE2 Event Control 0x4 32 0x00000000 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 ALARMEO0 Alarm 0 Event Output Enable 8 1 TAMPEREO Tamper Event Output Enable 14 1 OVFEO Overflow Event Output Enable 15 1 TAMPEVEI Tamper Event Input Enable 16 1 PERDEO Periodic Interval Daily Event Output Enable 24 1 INTENCLR MODE2 Interrupt Enable Clear 0x8 16 0x0000 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 ALARM0 Alarm 0 Interrupt Enable 8 1 TAMPER Tamper Enable 14 1 OVF Overflow Interrupt Enable 15 1 INTENSET MODE2 Interrupt Enable Set 0xA 16 0x0000 PER0 Periodic Interval 0 Enable 0 1 PER1 Periodic Interval 1 Enable 1 1 PER2 Periodic Interval 2 Enable 2 1 PER3 Periodic Interval 3 Enable 3 1 PER4 Periodic Interval 4 Enable 4 1 PER5 Periodic Interval 5 Enable 5 1 PER6 Periodic Interval 6 Enable 6 1 PER7 Periodic Interval 7 Enable 7 1 ALARM0 Alarm 0 Interrupt Enable 8 1 TAMPER Tamper Enable 14 1 OVF Overflow Interrupt Enable 15 1 INTFLAG MODE2 Interrupt Flag Status and Clear 0xC 16 0x0000 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 ALARM0 Alarm 0 8 1 TAMPER Tamper 14 1 OVF Overflow 15 1 DBGCTRL Debug Control 0xE 8 0x00 DBGRUN Run During Debug 0 1 SYNCBUSY MODE2 Synchronization Busy Status 0x10 32 read-only 0x00000000 SWRST Software Reset Bit Busy 0 1 ENABLE Enable Bit Busy 1 1 FREQCORR FREQCORR Register Busy 2 1 CLOCK CLOCK Register Busy 3 1 ALARM0 ALARM 0 Register Busy 5 1 MASK0 MASK 0 Register Busy 11 1 CLOCKSYNC Clock Synchronization Enable Bit Busy 15 1 GP0 General Purpose 0 Register Busy 16 1 GP1 General Purpose 1 Register Busy 17 1 FREQCORR Frequency Correction 0x14 8 0x00 VALUE Correction Value 0 7 SIGN Correction Sign 7 1 CLOCK MODE2 Clock Value 0x18 32 0x00000000 SECOND Second 0 6 MINUTE Minute 6 6 HOUR Hour 12 5 DAY Day 17 5 MONTH Month 22 4 YEAR Year 26 6 1 0x8 MODE2_ALARM[%s] 0x20 ALARM MODE2_ALARM Alarm n Value 0x0 32 0x00000000 SECOND Second 0 6 MINUTE Minute 6 6 HOUR Hour 12 5 HOURSelect AM Morning hour 0x00 PM Afternoon hour 0x10 DAY Day 17 5 MONTH Month 22 4 YEAR Year 26 6 MASK MODE2_ALARM Alarm n Mask 0x4 8 0x00 SEL Alarm Mask Selection 0 3 SELSelect OFF Alarm Disabled 0x0 SS Match seconds only 0x1 MMSS Match seconds and minutes only 0x2 HHMMSS Match seconds, minutes, and hours only 0x3 DDHHMMSS Match seconds, minutes, hours, and days only 0x4 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x5 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x6 2 4 GP[%s] General Purpose 0x40 32 0x00000000 GP General Purpose 0 32 TAMPCTRL Tamper Control 0x60 32 0x00000000 IN0ACT Tamper Input 0 Action 0 2 IN0ACTSelect OFF Off (Disabled) 0x0 WAKE Wake and set Tamper flag 0x1 CAPTURE Capture timestamp and set Tamper flag 0x2 ACTL Compare IN0 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag 0x3 IN1ACT Tamper Input 1 Action 2 2 IN1ACTSelect OFF Off (Disabled) 0x0 WAKE Wake and set Tamper flag 0x1 CAPTURE Capture timestamp and set Tamper flag 0x2 ACTL Compare IN1 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag 0x3 IN2ACT Tamper Input 2 Action 4 2 IN2ACTSelect OFF Off (Disabled) 0x0 WAKE Wake and set Tamper flag 0x1 CAPTURE Capture timestamp and set Tamper flag 0x2 ACTL Compare IN2 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag 0x3 IN3ACT Tamper Input 3 Action 6 2 IN3ACTSelect OFF Off (Disabled) 0x0 WAKE Wake and set Tamper flag 0x1 CAPTURE Capture timestamp and set Tamper flag 0x2 ACTL Compare IN3 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag 0x3 TAMLVL0 Tamper Level Select 0 16 1 TAMLVL1 Tamper Level Select 1 17 1 TAMLVL2 Tamper Level Select 2 18 1 TAMLVL3 Tamper Level Select 3 19 1 DEBNC0 Debouncer Enable 0 24 1 DEBNC1 Debouncer Enable 1 25 1 DEBNC2 Debouncer Enable 2 26 1 DEBNC3 Debouncer Enable 3 27 1 TIMESTAMP MODE2 Timestamp 0x64 32 read-only 0x00000000 SECOND Second Timestamp Value 0 6 MINUTE Minute Timestamp Value 6 6 HOUR Hour Timestamp Value 12 5 DAY Day Timestamp Value 17 5 MONTH Month Timestamp Value 22 4 YEAR Year Timestamp Value 26 6 TAMPID Tamper ID 0x68 32 0x00000000 TAMPID0 Tamper Input 0 Detected 0 1 TAMPID1 Tamper Input 1 Detected 1 1 TAMPID2 Tamper Input 2 Detected 2 1 TAMPID3 Tamper Input 3 Detected 3 1 TAMPEVT Tamper Event Detected 31 1 TAMPCTRLB Tamper Control B 0x6C 32 0x00000000 ALSI0 Active Layer Select Internal 0 0 1 ALSI1 Active Layer Select Internal 1 1 1 ALSI2 Active Layer Select Internal 2 2 1 ALSI3 Active Layer Select Internal 3 3 1 SERCOM0 U22014.1.0 Serial Communication Interface SERCOM SERCOM_ 0x42000400 0 0x31 registers SERCOM0_0 22 SERCOM0_1 23 SERCOM0_2 24 SERCOM0_OTHER 25 I2CM I2C Master Mode SercomI2cm 0x0 CTRLA I2CM Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 RUNSTDBY Run in Standby 7 1 PINOUT Pin Usage 16 1 SDAHOLD SDA Hold Time 20 2 MEXTTOEN Master SCL Low Extend Timeout 22 1 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SCLSM SCL Clock Stretch Mode 27 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 CTRLB I2CM Control B 0x4 32 0x00000000 SMEN Smart Mode Enable 8 1 QCEN Quick Command Enable 9 1 CMD Command 16 2 ACKACT Acknowledge Action 18 1 BAUD I2CM Baud Rate 0xC 32 0x00000000 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 INTENCLR I2CM Interrupt Enable Clear 0x14 8 0x00 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET I2CM Interrupt Enable Set 0x16 8 0x00 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG I2CM Interrupt Flag Status and Clear 0x18 8 0x00 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 ERROR Combined Error Interrupt 7 1 STATUS I2CM Status 0x1A 16 0x0000 BUSERR Bus Error 0 1 ARBLOST Arbitration Lost 1 1 RXNACK Received Not Acknowledge 2 1 BUSSTATE Bus State 4 2 LOWTOUT SCL Low Timeout 6 1 CLKHOLD Clock Hold 7 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 LENERR Length Error 10 1 SYNCBUSY I2CM Synchronization Busy 0x1C 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE SERCOM Enable Synchronization Busy 1 1 SYSOP System Operation Synchronization Busy 2 1 ADDR I2CM Address 0x24 32 0x00000000 ADDR Address Value 0 11 LENEN Length Enable 13 1 HS High Speed Mode 14 1 TENBITEN Ten Bit Addressing Enable 15 1 LEN Length 16 8 DATA I2CM Data 0x28 8 0x00 DATA Data Value 0 8 DBGCTRL I2CM Debug Control 0x30 8 0x00 DBGSTOP Debug Mode 0 1 I2CS I2C Slave Mode I2CM SercomI2cs 0x0 CTRLA I2CS Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 PINOUT Pin Usage 16 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SCLSM SCL Clock Stretch Mode 27 1 LOWTOUTEN SCL Low Timeout Enable 30 1 CTRLB I2CS Control B 0x4 32 0x00000000 SMEN Smart Mode Enable 8 1 GCMD PMBus Group Command 9 1 AACKEN Automatic Address Acknowledge 10 1 AMODE Address Mode 14 2 CMD Command 16 2 ACKACT Acknowledge Action 18 1 INTENCLR I2CS Interrupt Enable Clear 0x14 8 0x00 PREC Stop Received Interrupt Disable 0 1 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET I2CS Interrupt Enable Set 0x16 8 0x00 PREC Stop Received Interrupt Enable 0 1 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG I2CS Interrupt Flag Status and Clear 0x18 8 0x00 PREC Stop Received Interrupt 0 1 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 STATUS I2CS Status 0x1A 16 0x0000 BUSERR Bus Error 0 1 COLL Transmit Collision 1 1 RXNACK Received Not Acknowledge 2 1 DIR Read/Write Direction 3 1 SR Repeated Start 4 1 LOWTOUT SCL Low Timeout 6 1 CLKHOLD Clock Hold 7 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 HS High Speed 10 1 SYNCBUSY I2CS Synchronization Busy 0x1C 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE SERCOM Enable Synchronization Busy 1 1 ADDR I2CS Address 0x24 32 0x00000000 GENCEN General Call Address Enable 0 1 ADDR Address Value 1 10 TENBITEN Ten Bit Addressing Enable 15 1 ADDRMASK Address Mask 17 10 DATA I2CS Data 0x28 8 0x00 DATA Data Value 0 8 SPI SPI Mode I2CM SercomSpi 0x0 CTRLA SPI Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 IBON Immediate Buffer Overflow Notification 8 1 DOPO Data Out Pinout 16 2 DIPO Data In Pinout 20 2 FORM Frame Format 24 4 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 CTRLB SPI Control B 0x4 32 0x00000000 CHSIZE Character Size 0 3 PLOADEN Data Preload Enable 6 1 SSDE Slave Select Low Detect Enable 9 1 MSSEN Master Slave Select Enable 13 1 AMODE Address Mode 14 2 RXEN Receiver Enable 17 1 BAUD SPI Baud Rate 0xC 8 0x00 BAUD Baud Rate Value 0 8 INTENCLR SPI Interrupt Enable Clear 0x14 8 0x00 DRE Data Register Empty Interrupt Disable 0 1 TXC Transmit Complete Interrupt Disable 1 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET SPI Interrupt Enable Set 0x16 8 0x00 DRE Data Register Empty Interrupt Enable 0 1 TXC Transmit Complete Interrupt Enable 1 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG SPI Interrupt Flag Status and Clear 0x18 8 0x00 DRE Data Register Empty Interrupt 0 1 TXC Transmit Complete Interrupt 1 1 RXC Receive Complete Interrupt 2 1 SSL Slave Select Low Interrupt Flag 3 1 ERROR Combined Error Interrupt 7 1 STATUS SPI Status 0x1A 16 0x0000 BUFOVF Buffer Overflow 2 1 SYNCBUSY SPI Synchronization Busy 0x1C 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE SERCOM Enable Synchronization Busy 1 1 CTRLB CTRLB Synchronization Busy 2 1 ADDR SPI Address 0x24 32 0x00000000 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 DATA SPI Data 0x28 32 0x00000000 DATA Data Value 0 9 DBGCTRL SPI Debug Control 0x30 8 0x00 DBGSTOP Debug Mode 0 1 USART USART Mode I2CM SercomUsart 0x0 CTRLA USART Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 IBON Immediate Buffer Overflow Notification 8 1 TXINV Transmit Data Invert 9 1 RXINV Receive Data Invert 10 1 SAMPR Sample 13 3 TXPO Transmit Data Pinout 16 2 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 FORM Frame Format 24 4 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 CTRLB USART Control B 0x4 32 0x00000000 CHSIZE Character Size 0 3 SBMODE Stop Bit Mode 6 1 COLDEN Collision Detection Enable 8 1 SFDE Start of Frame Detection Enable 9 1 ENC Encoding Format 10 1 PMODE Parity Mode 13 1 TXEN Transmitter Enable 16 1 RXEN Receiver Enable 17 1 LINCMD LIN Command 24 2 CTRLC USART Control C 0x8 32 0x00000000 GTIME Guard Time 0 3 BRKLEN LIN Master Break Length 8 2 HDRDLY LIN Master Header Delay 10 2 INACK Inhibit Not Acknowledge 16 1 DSNACK Disable Successive NACK 17 1 MAXITER Maximum Iterations 20 3 BAUD USART Baud Rate 0xC 16 0x0000 BAUD Baud Rate Value 0 16 BAUD_FRAC_MODE USART Baud Rate BAUD 0xC 16 0x0000 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRACFP_MODE USART Baud Rate BAUD 0xC 16 0x0000 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART Baud Rate BAUD 0xC 16 0x0000 BAUD Baud Rate Value 0 16 RXPL USART Receive Pulse Length 0xE 8 0x00 RXPL Receive Pulse Length 0 8 INTENCLR USART Interrupt Enable Clear 0x14 8 0x00 DRE Data Register Empty Interrupt Disable 0 1 TXC Transmit Complete Interrupt Disable 1 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 RXBRK Break Received Interrupt Disable 5 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET USART Interrupt Enable Set 0x16 8 0x00 DRE Data Register Empty Interrupt Enable 0 1 TXC Transmit Complete Interrupt Enable 1 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 RXBRK Break Received Interrupt Enable 5 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG USART Interrupt Flag Status and Clear 0x18 8 0x00 DRE Data Register Empty Interrupt 0 1 TXC Transmit Complete Interrupt 1 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 CTSIC Clear To Send Input Change Interrupt 4 1 RXBRK Break Received Interrupt 5 1 ERROR Combined Error Interrupt 7 1 STATUS USART Status 0x1A 16 0x0000 PERR Parity Error 0 1 FERR Frame Error 1 1 BUFOVF Buffer Overflow 2 1 CTS Clear To Send 3 1 ISF Inconsistent Sync Field 4 1 COLL Collision Detected 5 1 TXE Transmitter Empty 6 1 ITER Maximum Number of Repetitions Reached 7 1 SYNCBUSY USART Synchronization Busy 0x1C 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE SERCOM Enable Synchronization Busy 1 1 CTRLB CTRLB Synchronization Busy 2 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 RXERRCNT USART Receive Error Count 0x20 8 read-only 0x00 DATA USART Data 0x28 16 0x0000 DATA Data Value 0 9 DBGCTRL USART Debug Control 0x30 8 0x00 DBGSTOP Debug Mode 0 1 SERCOM1 0x42000800 SERCOM1_0 26 SERCOM1_1 27 SERCOM1_2 28 SERCOM1_OTHER 29 SERCOM2 0x42000C00 SERCOM2_0 30 SERCOM2_1 31 SERCOM2_2 32 SERCOM2_OTHER 33 SUPC U21174.0.0 Supply Controller SUPC SUPC_ 0x40001800 0 0x34 registers INTENCLR Interrupt Enable Clear 0x0 32 0x00000000 BOD33RDY BOD33 Ready 0 1 BOD33DET BOD33 Detection 1 1 B33SRDY BOD33 Synchronization Ready 2 1 BOD12RDY BOD12 Ready 3 1 BOD12DET BOD12 Detection 4 1 B12SRDY BOD12 Synchronization Ready 5 1 VREGRDY Voltage Regulator Ready 8 1 VCORERDY VDDCORE Ready 10 1 ULPVREFRDY ULPVREF Voltage Reference Ready 11 1 INTENSET Interrupt Enable Set 0x4 32 0x00000000 BOD33RDY BOD33 Ready 0 1 BOD33DET BOD33 Detection 1 1 B33SRDY BOD33 Synchronization Ready 2 1 BOD12RDY BOD12 Ready 3 1 BOD12DET BOD12 Detection 4 1 B12SRDY BOD12 Synchronization Ready 5 1 VREGRDY Voltage Regulator Ready 8 1 VCORERDY VDDCORE Ready 10 1 ULPVREFRDY ULPVREF Voltage Reference Ready 11 1 INTFLAG Interrupt Flag Status and Clear 0x8 32 0x00000000 BOD33RDY BOD33 Ready 0 1 BOD33DET BOD33 Detection 1 1 B33SRDY BOD33 Synchronization Ready 2 1 BOD12RDY BOD12 Ready 3 1 BOD12DET BOD12 Detection 4 1 B12SRDY BOD12 Synchronization Ready 5 1 VREGRDY Voltage Regulator Ready 8 1 VCORERDY VDDCORE Ready 10 1 ULPVREFRDY ULPVREF Voltage Reference Ready 11 1 STATUS Power and Clocks Status 0xC 32 read-only 0x00000000 BOD33RDY BOD33 Ready 0 1 BOD33DET BOD33 Detection 1 1 B33SRDY BOD33 Synchronization Ready 2 1 BOD12RDY BOD12 Ready 3 1 BOD12DET BOD12 Detection 4 1 B12SRDY BOD12 Synchronization Ready 5 1 VREGRDY Voltage Regulator Ready 8 1 VCORERDY VDDCORE Ready 10 1 ULPVREFRDY Low Power Voltage Reference Ready 12 1 ULPBIASRDY Low Power Voltage Bias Ready 13 1 BOD33 BOD33 Control 0x10 32 0x00000000 ENABLE Enable 1 1 HYST Hysteresis Enable 2 1 ACTION Action when Threshold Crossed 3 2 ACTIONSelect NONE No action 0x0 RESET The BOD33 generates a reset 0x1 INT The BOD33 generates an interrupt 0x2 BKUP The BOD33 puts the device in backup sleep mode if VMON=0 0x3 STDBYCFG Configuration in Standby mode 5 1 RUNSTDBY Run during Standby 6 1 ACTCFG Configuration in Active mode 8 1 REFSEL BOD33 Voltage Reference Selection 11 1 REFSELSelect SEL_VREFDETREF Selects VREFDETREF for the BOD33 0 SEL_ULPVREF Selects ULPVREF for the BOD33 1 PSEL Prescaler Select 12 4 PSELSelect DIV2 Divide clock by 2 0x0 DIV4 Divide clock by 4 0x1 DIV8 Divide clock by 8 0x2 DIV16 Divide clock by 16 0x3 DIV32 Divide clock by 32 0x4 DIV64 Divide clock by 64 0x5 DIV128 Divide clock by 128 0x6 DIV256 Divide clock by 256 0x7 DIV512 Divide clock by 512 0x8 DIV1024 Divide clock by 1024 0x9 DIV2048 Divide clock by 2048 0xA DIV4096 Divide clock by 4096 0xB DIV8192 Divide clock by 8192 0xC DIV16384 Divide clock by 16384 0xD DIV32768 Divide clock by 32768 0xE DIV65536 Divide clock by 65536 0xF LEVEL Threshold Level for VDD 16 6 BOD12 BOD12 Control 0x14 32 0x00000000 ENABLE Enable 1 1 HYST Hysteresis Enable 2 1 ACTION Action when Threshold Crossed 3 2 ACTIONSelect NONE No action 0x0 RESET The BOD12 generates a reset 0x1 INT The BOD12 generates an interrupt 0x2 STDBYCFG Configuration in Standby mode 5 1 RUNSTDBY Run during Standby 6 1 ACTCFG Configuration in Active mode 8 1 PSEL Prescaler Select 12 4 PSELSelect DIV2 Divide clock by 2 0x0 DIV4 Divide clock by 4 0x1 DIV8 Divide clock by 8 0x2 DIV16 Divide clock by 16 0x3 DIV32 Divide clock by 32 0x4 DIV64 Divide clock by 64 0x5 DIV128 Divide clock by 128 0x6 DIV256 Divide clock by 256 0x7 DIV512 Divide clock by 512 0x8 DIV1024 Divide clock by 1024 0x9 DIV2048 Divide clock by 2048 0xA DIV4096 Divide clock by 4096 0xB DIV8192 Divide clock by 8192 0xC DIV16384 Divide clock by 16384 0xD DIV32768 Divide clock by 32768 0xE DIV65536 Divide clock by 65536 0xF LEVEL Threshold Level 16 6 VREG VREG Control 0x18 32 0x00000002 ENABLE Enable 1 1 SEL Voltage Regulator Selection in active mode 2 2 SELSelect LDO LDO selection 0x0 BUCK Buck selection 0x1 STDBYPL0 Standby in PL0 5 1 RUNSTDBY Run during Standby 6 1 LPEFF Low Power efficiency 8 1 VREFSEL Voltage Regulator Voltage Reference Selection 9 1 VSVSTEP Voltage Scaling Voltage Step 16 4 VSPER Voltage Scaling Period 24 8 VREF VREF Control 0x1C 32 0x00000000 TSEN Temperature Sensor Output Enable 1 1 VREFOE Voltage Reference Output Enable 2 1 TSSEL Temperature Sensor Selection 3 1 RUNSTDBY Run during Standby 6 1 ONDEMAND On Demand Control 7 1 SEL Voltage Reference Selection 16 4 SELSelect 1V0 1.0V voltage reference typical value 0x0 1V1 1.1V voltage reference typical value 0x1 1V2 1.2V voltage reference typical value 0x2 1V25 1.25V voltage reference typical value 0x3 2V0 2.0V voltage reference typical value 0x4 2V2 2.2V voltage reference typical value 0x5 2V4 2.4V voltage reference typical value 0x6 2V5 2.5V voltage reference typical value 0x7 EVCTRL Event Control 0x2C 32 0x00000000 BOD33DETEO BOD33 Detection Event Output Enable 1 1 BOD12DETEO BOD12 Detection Event Output Enable 4 1 VREGSUSP VREG Suspend Control 0x30 32 0x00000000 VREGSEN Enable Voltage Regulator Suspend 0 1 TC0 U22493.1.0 Basic Timer Counter TC TC_ 0x42001000 0 0x38 registers TC0 34 COUNT8 8-bit Counter Mode TcCount8 0x0 CTRLA Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CTRLBCLR Control B Clear 0x4 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 CTRLBSET Control B Set 0x5 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 EVCTRL Event Control 0x6 16 0x0000 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 TCINV TC Event Input Polarity 4 1 TCEI TC Event Enable 5 1 OVFEO Event Output Enable 8 1 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 INTENCLR Interrupt Enable Clear 0x8 8 0x00 OVF OVF Interrupt Disable 0 1 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 INTENSET Interrupt Enable Set 0x9 8 0x00 OVF OVF Interrupt Enable 0 1 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 0x00 OVF OVF Interrupt Flag 0 1 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 STATUS Status 0xB 8 0x01 STOP Stop Status Flag 0 1 SLAVE Slave Status Flag 1 1 PERBUFV Synchronization Busy Status 3 1 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 WAVE Waveform Generation Control 0xC 8 0x00 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 DRVCTRL Control C 0xD 8 0x00 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 DBGCTRL Debug Control 0xF 8 0x00 DBGRUN Run During Debug 0 1 SYNCBUSY Synchronization Status 0x10 32 read-only 0x00000000 SWRST swrst 0 1 ENABLE enable 1 1 CTRLB CTRLB 2 1 STATUS STATUS 3 1 COUNT Counter 4 1 PER Period 5 1 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT COUNT8 Count 0x14 8 0x00 COUNT Counter Value 0 8 PER COUNT8 Period 0x1B 8 0xFF PER Period Value 0 8 2 1 CC[%s] COUNT8 Compare and Capture 0x1C 8 0x00 CC Counter/Compare Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 0xFF PERBUF Period Buffer Value 0 8 2 1 CCBUF[%s] COUNT8 Compare and Capture Buffer 0x30 8 0x00 CCBUF Counter/Compare Buffer Value 0 8 COUNT16 16-bit Counter Mode COUNT8 TcCount16 0x0 CTRLA Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CTRLBCLR Control B Clear 0x4 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 CTRLBSET Control B Set 0x5 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 EVCTRL Event Control 0x6 16 0x0000 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 TCINV TC Event Input Polarity 4 1 TCEI TC Event Enable 5 1 OVFEO Event Output Enable 8 1 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 INTENCLR Interrupt Enable Clear 0x8 8 0x00 OVF OVF Interrupt Disable 0 1 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 INTENSET Interrupt Enable Set 0x9 8 0x00 OVF OVF Interrupt Enable 0 1 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 0x00 OVF OVF Interrupt Flag 0 1 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 STATUS Status 0xB 8 0x01 STOP Stop Status Flag 0 1 SLAVE Slave Status Flag 1 1 PERBUFV Synchronization Busy Status 3 1 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 WAVE Waveform Generation Control 0xC 8 0x00 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 DRVCTRL Control C 0xD 8 0x00 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 DBGCTRL Debug Control 0xF 8 0x00 DBGRUN Run During Debug 0 1 SYNCBUSY Synchronization Status 0x10 32 read-only 0x00000000 SWRST swrst 0 1 ENABLE enable 1 1 CTRLB CTRLB 2 1 STATUS STATUS 3 1 COUNT Counter 4 1 PER Period 5 1 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT COUNT16 Count 0x14 16 0x0000 COUNT Counter Value 0 16 PER COUNT16 Period 0x1A 16 0xFFFF PER Period Value 0 16 2 2 CC[%s] COUNT16 Compare and Capture 0x1C 16 0x0000 CC Counter/Compare Value 0 16 PERBUF COUNT16 Period Buffer 0x2E 16 0xFFFF PERBUF Period Buffer Value 0 16 2 2 CCBUF[%s] COUNT16 Compare and Capture Buffer 0x30 16 0x0000 CCBUF Counter/Compare Buffer Value 0 16 COUNT32 32-bit Counter Mode COUNT8 TcCount32 0x0 CTRLA Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CTRLBCLR Control B Clear 0x4 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 CTRLBSET Control B Set 0x5 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 EVCTRL Event Control 0x6 16 0x0000 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 TCINV TC Event Input Polarity 4 1 TCEI TC Event Enable 5 1 OVFEO Event Output Enable 8 1 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 INTENCLR Interrupt Enable Clear 0x8 8 0x00 OVF OVF Interrupt Disable 0 1 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 INTENSET Interrupt Enable Set 0x9 8 0x00 OVF OVF Interrupt Enable 0 1 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 0x00 OVF OVF Interrupt Flag 0 1 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 STATUS Status 0xB 8 0x01 STOP Stop Status Flag 0 1 SLAVE Slave Status Flag 1 1 PERBUFV Synchronization Busy Status 3 1 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 WAVE Waveform Generation Control 0xC 8 0x00 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 DRVCTRL Control C 0xD 8 0x00 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 DBGCTRL Debug Control 0xF 8 0x00 DBGRUN Run During Debug 0 1 SYNCBUSY Synchronization Status 0x10 32 read-only 0x00000000 SWRST swrst 0 1 ENABLE enable 1 1 CTRLB CTRLB 2 1 STATUS STATUS 3 1 COUNT Counter 4 1 PER Period 5 1 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT COUNT32 Count 0x14 32 0x00000000 COUNT Counter Value 0 32 PER COUNT32 Period 0x18 32 0xFFFFFFFF PER Period Value 0 32 2 4 CC[%s] COUNT32 Compare and Capture 0x1C 32 0x00000000 CC Counter/Compare Value 0 32 PERBUF COUNT32 Period Buffer 0x2C 32 0xFFFFFFFF PERBUF Period Buffer Value 0 32 2 4 CCBUF[%s] COUNT32 Compare and Capture Buffer 0x30 32 0x00000000 CCBUF Counter/Compare Buffer Value 0 32 TC1 0x42001400 TC1 35 TC2 0x42001800 TC2 36 TRAM U28011.0.0 TrustRAM TRAM TRAM_ 0x42003400 0 0x290 registers TRAM 44 CTRLA Control 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 TAMPERS Tamper Erase 4 1 DRP Data Remanence Prevention 6 1 SILACC Silent Access 7 1 INTENCLR Interrupt Enable Clear 0x4 8 0x00 ERR TrustRAM Readout Error Interrupt Enable 0 1 DRP Data Remanence Prevention Ended Interrupt Enable 1 1 INTENSET Interrupt Enable Set 0x5 8 0x00 ERR TrustRAM Readout Error Interrupt Enable 0 1 DRP Data Remanence Prevention Ended Interrupt Enable 1 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 0x00 ERR TrustRAM Readout Error 0 1 DRP Data Remanence Prevention Ended 1 1 STATUS Status 0x7 8 read-only 0x00 RAMINV RAM Inversion Bit 0 1 DRP Data Remanence Prevention Ongoing 1 1 SYNCBUSY Synchronization Busy Status 0x8 32 read-only 0x00000000 SWRST Software Reset Busy 0 1 ENABLE Enable Busy 1 1 DSCC Data Scramble Control 0xC 32 write-only 0x00000000 DSCKEY Data Scramble Key 0 30 DSCEN Data Scramble Enable 31 1 PERMW Permutation Write 0x10 8 write-only 0x00 DATA Permutation Scrambler Data Input 0 3 PERMR Permutation Read 0x11 8 read-only 0x00 DATA Permutation Scrambler Data Output 0 3 64 4 RAM[%s] TrustRAM 0x100 32 0x00000000 DATA Trust RAM Data 0 32 TRNG U22421.2.0 True Random Generator TRNG TRNG_ 0x42002800 0 0x24 registers TRNG 43 CTRLA Control A 0x0 8 0x00 ENABLE Enable 1 1 RUNSTDBY Run in Standby 6 1 EVCTRL Event Control 0x4 8 0x00 DATARDYEO Data Ready Event Output 0 1 INTENCLR Interrupt Enable Clear 0x8 8 0x00 DATARDY Data Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x9 8 0x00 DATARDY Data Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 0x00 DATARDY Data Ready Interrupt Flag 0 1 DATA Output Data 0x20 32 read-only 0x00000000 DATA Output Data 0 32 WDT U22512.0.0 Watchdog Timer WDT WDT_ 0x40002000 0 0xD registers WDT 1 CTRLA Control 0x0 8 0x00 ENABLE Enable 1 1 WEN Watchdog Timer Window Mode Enable 2 1 RUNSTDBY Run During Standby 6 1 ALWAYSON Always-On 7 1 CONFIG Configuration 0x1 8 0xBB PER Time-Out Period 0 4 PERSelect CYC8 8 clock cycles 0x0 CYC16 16 clock cycles 0x1 CYC32 32 clock cycles 0x2 CYC64 64 clock cycles 0x3 CYC128 128 clock cycles 0x4 CYC256 256 clock cycles 0x5 CYC512 512 clock cycles 0x6 CYC1024 1024 clock cycles 0x7 CYC2048 2048 clock cycles 0x8 CYC4096 4096 clock cycles 0x9 CYC8192 8192 clock cycles 0xA CYC16384 16384 clock cycles 0xB WINDOW Window Mode Time-Out Period 4 4 WINDOWSelect CYC8 8 clock cycles 0x0 CYC16 16 clock cycles 0x1 CYC32 32 clock cycles 0x2 CYC64 64 clock cycles 0x3 CYC128 128 clock cycles 0x4 CYC256 256 clock cycles 0x5 CYC512 512 clock cycles 0x6 CYC1024 1024 clock cycles 0x7 CYC2048 2048 clock cycles 0x8 CYC4096 4096 clock cycles 0x9 CYC8192 8192 clock cycles 0xA CYC16384 16384 clock cycles 0xB EWCTRL Early Warning Interrupt Control 0x2 8 0x0B EWOFFSET Early Warning Interrupt Time Offset 0 4 EWOFFSETSelect CYC8 8 clock cycles 0x0 CYC16 16 clock cycles 0x1 CYC32 32 clock cycles 0x2 CYC64 64 clock cycles 0x3 CYC128 128 clock cycles 0x4 CYC256 256 clock cycles 0x5 CYC512 512 clock cycles 0x6 CYC1024 1024 clock cycles 0x7 CYC2048 2048 clock cycles 0x8 CYC4096 4096 clock cycles 0x9 CYC8192 8192 clock cycles 0xA CYC16384 16384 clock cycles 0xB INTENCLR Interrupt Enable Clear 0x4 8 0x00 EW Early Warning Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x5 8 0x00 EW Early Warning Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 0x00 EW Early Warning 0 1 SYNCBUSY Synchronization Busy 0x8 32 read-only 0x00000000 ENABLE Enable Synchronization Busy 1 1 WEN Window Enable Synchronization Busy 2 1 RUNSTDBY Run During Standby Synchronization Busy 3 1 ALWAYSON Always-On Synchronization Busy 4 1 CLEAR Clear Synchronization Busy 5 1 CLEAR Clear 0xC 8 write-only 0x00 CLEAR Watchdog Clear 0 8 CLEARSelect KEY Clear Key 0xA5 CoreDebug Debug Control Block CoreDebug CoreDebug_ 0xE000EDF0 0 0x1C registers DHCSR Debug Halting Control and Status Register 0x0 32 C_DEBUGEN Enable Halting debug 0 1 C_HALT Halt processor 1 1 C_STEP Enable single step 2 1 C_MASKINTS Mask PendSV, SysTick and external configurable interrupts 3 1 S_SNAPSTALL Snap stall control 5 1 S_REGRDY Register ready status 16 1 S_HALT Halted status 17 1 S_SLEEP Sleeping status 18 1 S_LOCKUP Lockup status 19 1 S_SDE Secure debug enabled 20 1 S_RETIRE_ST Retire sticky status 24 1 S_RESET_ST Reset sticky status 25 1 S_RESTART_ST Restart sticky status 26 1 DCRSR Debug Core Register Select Register 0x4 32 write-only REGSEL Register selector 0 7 REGWnR Register write/not-read access 16 1 DEMCR Debug Exception and Monitor Control Register 0xC 32 VC_CORERESET Core reset Halting debug vector catch enable 0 1 VC_MMERR MemManage exception Halting debug vector catch enable 4 1 VC_NOCPERR UsageFault exception coprocessor access Halting debug vector catch enable 5 1 VC_CHKERR UsageFault exception checking error Halting debug vector catch enable 6 1 VC_STATERR UsageFault exception state information error Halting debug vector catch enable 7 1 VC_BUSERR BusFault exception Halting debug vector catch enable 8 1 VC_INTERR Excception entry and return faults Halting debug vector catch enable 9 1 VC_HARDERR HardFault exception Halting debug vector catch enable 10 1 VC_SFERR SecureFault exception Halting debug vector catch enable 11 1 MON_EN DebugMonitor enable 16 1 MON_PEND DebugMonitor pending state 17 1 MON_STEP Enable DebugMonitor stepping 18 1 MON_REQ DebugMonitor semaphore bit 19 1 SDME Secure DebugMonitor enable 20 1 TRCENA Global DWT and ITM features enable 24 1 DAUTHCTRL Debug Authentication Control Register 0x14 32 SPIDENSEL Secure invasive debug enable select 0 1 INTSPIDEN Internal Secure invasive debug enable 1 1 SPNIDENSEL Secure non-invasive debug enable select 2 1 INTSPNIDEN Internal Secure non-invasive debug enable 3 1 DSCSR Debug Security Control and Status Register 0x18 32 SBRSELEN Secure Banked register select enable 0 1 SBRSEL Secure Banked register select 1 1 CDS Current domain Secure 16 1 CDSKEY CDS field write-enable key 17 1 CoreDebug_NS 0xE002EDF0 DIB Debug Identification Block DIB DIB_ 0xE000EFB0 0 0x50 registers DLAR SCS Software Lock Access Register 0x0 32 write-only KEY Lock access control 0 32 KEYSelect UNLOCK Unlock key value 0xC5ACCE55 DLSR SCS Software Lock Status Register 0x4 32 read-only SLI Software Lock implemented 0 1 SLK Software Lock status 1 1 nTT Not thirty-two bit 2 1 DAUTHSTATUS Debug Authentication Status Register 0x8 32 read-only NSID 0 1 NSIDSelect NO Non-secure invasive debug prohibited 2 YES Non-secure invasive debug allowed 3 NSNID 2 1 NSNIDSelect NO Non-secure non-invasive debug prohibited 2 YES Non-secure non-invasive debug allowed 3 SID 4 2 SIDSelect NOSEC Security Extension not implemented 0 NO Secure invasive debug prohibited 2 YES Secure invasive debug allowed 3 SNID 6 2 SNIDSelect NOSEC Security Extension not implemented 0 NO Secure non-invasive debug prohibited 2 YES Secure non-invasive debug allowed 3 DDEVARCH SCS Device Architecture Register 0xC 32 read-only 0x47702A04 ARCHPART Architecture Part 0 12 ARCHVER Architecture Version 12 4 REVISION Revision 16 4 PRESENT DEVARCH Present 20 1 ARCHITECT Architect 21 11 DDEVTYPE SCS Device Type Register 0x1C 32 read-only 0x00000000 MAJOR Major type 0 4 SUB Sub-type 4 4 DPIDR4 SCS Peripheral Identification Register 4 0x20 32 read-only DES_2 JEP106 continuation code 0 4 SIZE 4KB count 4 4 DPIDR5 SCS Peripheral Identification Register 5 0x24 32 read-only 0x00000000 DPIDR6 SCS Peripheral Identification Register 6 0x28 32 read-only 0x00000000 DPIDR7 SCS Peripheral Identification Register 7 0x2C 32 read-only 0x00000000 DPIDR0 SCS Peripheral Identification Register 0 0x30 32 read-only PART_0 Part number bits[7:0] 0 8 DPIDR1 SCS Peripheral Identification Register 1 0x34 32 read-only PART_1 Part number bits[11:8] 0 4 DES_0 JEP106 identification code bits [3:0] 4 4 DPIDR2 SCS Peripheral Identification Register 2 0x38 32 read-only DES_1 JEP106 identification code bits[6:4] 0 3 JEDEC JEDEC assignee value is used 3 1 REVISION Component revision 4 4 DPIDR3 SCS Peripheral Identification Register 3 0x3C 32 read-only CMOD Customer Modified 0 4 REVAND RevAnd 4 4 DCIDR0 SCS Component Identification Register 0 0x40 32 read-only 0x0000000D PRMBL_0 CoreSight component identification preamble 0 8 DCIDR1 SCS Component Identification Register 1 0x44 32 read-only 0x00000090 PRMBL_1 CoreSight component identification preamble 0 4 CLASS CoreSight component class 4 4 DCIDR2 SCS Component Identification Register 2 0x48 32 read-only 0x00000005 PRMBL_2 CoreSight component identification preamble 0 8 DCIDR3 SCS Component Identification Register 3 0x4C 32 read-only 0x000000B1 PRMBL_3 CoreSight component identification preamble 0 8 DIB_NS 0xE002EFB0 DWT Data Watchpoint and Trace DWT DWT_ 0xE0001000 0 0x1000 registers DWT_CTRL DWT Control Register 0x0 32 0x0B000000 CYCCNTENA CYCCNT enable 0 1 POSTPRESET POSTCNT preset 1 4 POSTINIT POSTCNT initial 5 4 CYCTAP Cycle count tap 9 1 SYNCTAP Synchronization tap 10 2 PCSAMPLENA PC sample enable 12 1 EXCTRCENA Exception trace enable 16 1 CPIEVTENA CPI event enable 17 1 EXCEVTENA Exception event enable 18 1 SLEEPEVTENA Sleep event enable 19 1 LSUEVTENA LSU event enable 20 1 FOLDEVTENA Fold event enable 21 1 CYCEVTENA Cycle event enable 22 1 CYCDISS Cycle counter disabled secure 23 1 NOPRFCNT No profile counters 24 1 NOCYCCNT No cycle count 25 1 NOEXTTRIG No external triggers 26 1 NOTRCPKT No trace packets 27 1 NUMCOMP Number of comparators 28 4 DWT_PCSR DWT Program Counter Sample Register 0x1C 32 read-only EIASAMPLE Executed instruction address sample 0 32 2 0x10 COMPARATOR[%s] 0x020 DWT_COMP DWT Comparator Register n 0x0 32 VALUE Cycle/PC/data value or data address 0 32 DWT_FUNCTION DWT Function Register x 0x8 32 MATCH Match type 0 4 ACTION Action on match 4 2 DATAVSIZE Data value size 10 2 MATCHED Comparator matched 24 1 ID Identify capability 27 5 DWT_LAR DWT Software Lock Access Register 0xFB0 32 write-only KEY Lock access control 0 32 KEYSelect UNLOCK Unlock key value 0xC5ACCE55 DWT_LSR DWT Software Lock Status Register 0xFB4 32 read-only SLI Software Lock implemented 0 1 SLK Software Lock status 1 1 nTT Not thirty-two bit 2 1 DWT_DEVARCH DWT Device Architecture Register 0xFBC 32 read-only 0x47701A02 ARCHPART Architecture Part 0 12 ARCHVER Architecture Version 12 4 REVISION Revision 16 4 PRESENT DEVARCH Present 20 1 ARCHITECT Architect 21 11 DWT_DEVTYPE DWT Device Type Register 0xFCC 32 read-only 0x00000000 MAJOR Major type 0 4 SUB Sub-type 4 4 DWT_PIDR4 DWT Peripheral Identification Register 4 0xFD0 32 read-only DES_2 JEP106 continuation code 0 4 SIZE 4KB count 4 4 DWT_PIDR5 DWT Peripheral Identification Register 5 0xFD4 32 read-only 0x00000000 DWT_PIDR6 DWT Peripheral Identification Register 6 0xFD8 32 read-only 0x00000000 DWT_PIDR7 DWT Peripheral Identification Register 7 0xFDC 32 read-only 0x00000000 DWT_PIDR0 DWT Peripheral Identification Register 0 0xFE0 32 read-only PART_0 Part number bits[7:0] 0 8 DWT_PIDR1 DWT Peripheral Identification Register 1 0xFE4 32 read-only PART_1 Part number bits[11:8] 0 4 DES_0 JEP106 identification code bits [3:0] 4 4 DWT_PIDR2 DWT Peripheral Identification Register 2 0xFE8 32 read-only DES_1 JEP106 identification code bits[6:4] 0 3 JEDEC JEDEC assignee value is used 3 1 REVISION Component revision 4 4 DWT_PIDR3 DWT Peripheral Identification Register 3 0xFEC 32 read-only CMOD Customer Modified 0 4 REVAND RevAnd 4 4 DWT_CIDR0 DWT Component Identification Register 0 0xFF0 32 read-only 0x0000000D PRMBL_0 CoreSight component identification preamble 0 8 DWT_CIDR1 DWT Component Identification Register 1 0xFF4 32 read-only 0x00000090 PRMBL_1 CoreSight component identification preamble 0 4 CLASS CoreSight component class 4 4 DWT_CIDR2 DWT Component Identification Register 2 0xFF8 32 read-only 0x00000005 PRMBL_2 CoreSight component identification preamble 0 8 DWT_CIDR3 DWT Component Identification Register 3 0xFFC 32 read-only 0x000000B1 PRMBL_3 CoreSight component identification preamble 0 8 FPB Flash Patch and Breakpoint FPB FPB_ 0xE0002000 0 0x1000 registers FP_CTRL Flash Patch Control Register 0x0 32 ENABLE Flash Patch global enable 0 1 KEY FP_CTRL write-enable key 1 1 NUM_CODE Number of implemented code comparators bits [3:0] 4 4 NUM_LIT Number of literal comparators 8 4 NUM_CODE_1 Number of implemented code comparators bits [6:4] 12 3 REV Revision 28 4 FP_REMAP Flash Patch Remap Register 0x4 32 read-only REMAP Remap address 5 24 RMPSPT Remap supported 29 1 4 4 FP_COMP[%s] Flash Patch Comparator Register n 0x8 32 BE Breakpoint enable 0 1 FPADDR Flash Patch address 2 27 FE Flash Patch enable 31 1 4 4 FP_COMP_BREAKPOINT_MODE[%s] Flash Patch Comparator Register n FP_COMP[%s] 0x8 32 BE Breakpoint enable 0 1 BPADDR Breakpoint address 1 31 FP_LAR FPB Software Lock Access Register 0xFB0 32 write-only KEY Lock access control 0 32 KEYSelect UNLOCK Unlock key value 0xC5ACCE55 FP_LSR FPB Software Lock Status Register 0xFB4 32 read-only SLI Software Lock implemented 0 1 SLK Software Lock status 1 1 nTT Not thirty-two bit 2 1 FP_DEVARCH FPB Device Architecture Register 0xFBC 32 read-only 0x47701A03 ARCHPART Architecture Part 0 12 ARCHVER Architecture Version 12 4 REVISION Revision 16 4 PRESENT DEVARCH Present 20 1 ARCHITECT Architect 21 11 FP_DEVTYPE FPB Device Type Register 0xFCC 32 read-only 0x00000000 MAJOR Major type 0 4 SUB Sub-type 4 4 FP_PIDR4 FP Peripheral Identification Register 4 0xFD0 32 read-only DES_2 JEP106 continuation code 0 4 SIZE 4KB count 4 4 FP_PIDR5 FP Peripheral Identification Register 5 0xFD4 32 read-only 0x00000000 FP_PIDR6 FP Peripheral Identification Register 6 0xFD8 32 read-only 0x00000000 FP_PIDR7 FP Peripheral Identification Register 7 0xFDC 32 read-only 0x00000000 FP_PIDR0 FP Peripheral Identification Register 0 0xFE0 32 read-only PART_0 Part number bits[7:0] 0 8 FP_PIDR1 FP Peripheral Identification Register 1 0xFE4 32 read-only PART_1 Part number bits[11:8] 0 4 DES_0 JEP106 identification code bits [3:0] 4 4 FP_PIDR2 FP Peripheral Identification Register 2 0xFE8 32 read-only DES_1 JEP106 identification code bits[6:4] 0 3 JEDEC JEDEC assignee value is used 3 1 REVISION Component revision 4 4 FP_PIDR3 FP Peripheral Identification Register 3 0xFEC 32 read-only CMOD Customer Modified 0 4 REVAND RevAnd 4 4 FP_CIDR0 FP Component Identification Register 0 0xFF0 32 read-only 0x0000000D PRMBL_0 CoreSight component identification preamble 0 8 FP_CIDR1 FP Component Identification Register 1 0xFF4 32 read-only 0x00000090 PRMBL_1 CoreSight component identification preamble 0 4 CLASS CoreSight component class 4 4 FP_CIDR2 FP Component Identification Register 2 0xFF8 32 read-only 0x00000005 PRMBL_2 CoreSight component identification preamble 0 8 FP_CIDR3 FP Component Identification Register 3 0xFFC 32 read-only 0x000000B1 PRMBL_3 CoreSight component identification preamble 0 8 ICB Implementation Control Block ICB ICB_ 0xE000E000 0 0xC registers ICTR Interrupt Controller Type Register 0x4 32 read-only INTLINESNUM Interrupt line set number 0 4 ACTLR Auxiliary Control Register 0x8 32 ICB_NS 0xE002E000 MPU Memory Protection Unit MPU MPU_ 0xE000ED90 0 0x38 registers MPU_TYPE MPU Type Register 0x0 32 read-only SEPARATE Separate instructions and data address regions 0 1 DREGION Number of MPU data regions 8 8 MPU_CTRL MPU Control Register 0x4 32 ENABLE MPU enable 0 1 HFNMIENA HardFault, NMI enable 1 1 PRIVDEFENA Privileged default enable 2 1 MPU_RNR MPU Region Number Register 0x8 32 REGION Selected region number 0 8 MPU_RBAR MPU Region Base Address Register 0xC 32 XN Execute Never 0 1 AP Access permissions 1 2 APSelect RWPRIV Read/write by privileged code only 0 RWANY Read/write by any privilege level 1 RPRIV Read-only by privileged code only 2 RANY Read-only by any privilege level 3 SH Shareability 3 2 SHSelect NO Non-shareable 0 OUTER Outer shareable 2 INNER Inner shareable 3 BASE Base address 5 27 MPU_RLAR MPU Region Limit Address Register 0x10 32 EN Region enable 0 1 AttrInd Attribute Index 1 3 LIMIT Limit address 5 27 MPU_MAIR0 MPU Memory Attribute Indirection Register 0 0x30 32 Attr0 Attribute of MPU region 0 0 8 Attr1 Attribute of MPU region 1 8 8 Attr2 Attribute of MPU region 2 16 8 Attr3 Attribute of MPU region 3 24 8 MPU_MAIR1 MPU Memory Attribute Indirection Register 1 0x34 32 MPU_NS 0xE002ED90 NVIC Nested Vectored Interrupt Controller NVIC NVIC_ 0xE000E100 0 0x348 registers 2 4 NVIC_ISER[%s] Interrupt Set Enable Register n 0x0 32 SETENA Set enable 0 32 2 4 NVIC_ICER[%s] Interrupt Clear Enable Register n 0x80 32 CLRENA Clear enable 0 32 2 4 NVIC_ISPR[%s] Interrupt Set Pending Register n 0x100 32 SETPEND Set pending 0 32 2 4 NVIC_ICPR[%s] Interrupt Clear Pending Register n 0x180 32 CLRPEND Clear pending 0 32 2 4 NVIC_IABR[%s] Interrupt Active Bit Register n 0x200 32 read-only ACTIVE Active state 0 32 2 4 NVIC_ITNS[%s] Interrupt Target Non-secure Register n 0x280 32 ITNS Interrupt Targets Non-secure 0 32 12 4 NVIC_IPR[%s] Interrupt Priority Register n 0x300 32 PRI_N0 Priority of interrupt number 4n+0 0 8 PRI_N1 Priority of interrupt number 4n+1 8 8 PRI_N2 Priority of interrupt number 4n+2 16 8 PRI_N3 Priority of interrupt number 4n+3 24 8 NVIC_NS 0xE002E100 SCB System Control Block SCB SCB_ 0xE000ED00 0 0x88 registers CPUID CPUID base register 0x0 32 read-only Revision Revision number 0 4 PartNo Part number, 0xD20=Cortex-M23 4 12 Architecture Architecture version, 0xC=ARMv8-M Base Line, 0xF=ARMv8-M Main Line 16 4 Variant Variant number 20 4 Implementer Implementer code, ARM=0x41 24 8 ICSR Interrupt Control and State Register 0x4 32 VECTACTIVE Vector active 0 9 RETTOBASE Return to base 11 1 VECTPENDING Vector pending 12 9 ISRPENDING Interrupt pending 22 1 ISRPREEMPT Interrupt preempt 23 1 PENDSTCLR Pend SysTick clear 25 1 PENDSTCLRSelect VALUE_0 No effect 0 VALUE_1 Removes the pending state from the SysTick exception 1 PENDSTSET Pend SysTick set 26 1 PENDSTSETSelect VALUE_0 Write: no effect; read: SysTick exception is not pending 0 VALUE_1 Write: changes SysTick exception state to pending; read: SysTick exception is pending 1 PENDSVCLR Pend PendSV clear 27 1 PENDSVCLRSelect VALUE_0 No effect 0 VALUE_1 Removes the pending state from the PendSV exception 1 PENDSVSET Pend PendSV set 28 1 PENDSVSETSelect VALUE_0 Write: no effect; read: PendSV exception is not pending 0 VALUE_1 Write: changes PendSV exception state to pending; read: PendSV exception is pending 1 PENDNMICLR Pend NMI clear 30 1 PENDNMISET Pend NMI set 31 1 PENDNMISETSelect VALUE_0 Write: no effect; read: NMI exception is not pending 0 VALUE_1 Write: changes NMI exception state to pending; read: NMI exception is pending 1 VTOR Vector Table Offset Register 0x8 32 TBLOFF Vector table base offset 7 25 AIRCR Application Interrupt and Reset Control Register 0xC 32 VECTCLRACTIVE Debug: Clear Active State 1 1 VECTCLRACTIVESelect NO Do not clear active state 0x0 YES Clear active state 0x1 SYSRESETREQ System Reset Request 2 1 SYSRESETREQSelect NO Do not request a system reset 0 YES Request a system reset 1 SYSRESETREQS System Reset Request Secure only 3 1 SYSRESETREQSSelect BOTH SYSRESETREQ functionality is available to both Security states 0x0 SECURE SYSRESETREQ functionality is only available to Secure state 0x1 BFHFNMINS BusFault, HardFault and NMI Non-secure enable 13 1 BFHFNMINSSelect SECURE BusFault, HardFault, and NMI are Secure 0x0 NON_SECURE BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault 0x1 PRIS Prioritize Secure Exceptions 14 1 PRISSelect SAME Priority ranges of Secure and Non-secure exceptions are identical 0x0 NS_DEPRIO Non-secure exceptions are de-prioritized 0x1 ENDIANNESS Data Endianness, 0=little, 1=big 15 1 ENDIANNESSSelect LITTLE Little-endian 0 BIG Big-endian 1 VECTKEY Register Key (0x05FA) 16 16 SCR System Control Register 0x10 32 SLEEPONEXIT Sleep on exit 1 1 SLEEPONEXITSelect VALUE_0 O not sleep when returning to Thread mode 0 VALUE_1 Enter sleep, or deep sleep, on return from an ISR 1 SLEEPDEEP Sleep deep 2 1 SLEEPDEEPSelect VALUE_0 Sleep 0 VALUE_1 Deep sleep 1 SLEEPDEEPS Sleep deep secure 3 1 SEVONPEND Send Event on Pending bit 4 1 SEVONPENDSelect VALUE_0 Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 0 VALUE_1 Enabled events and all interrupts, including disabled interrupts, can wakeup the processor 1 CCR Configuration and Control Register 0x14 32 USERSETMPEND User set main pending 1 1 UNALIGN_TRP Unaligned trap 3 1 UNALIGN_TRPSelect VALUE_0 Do not trap unaligned halfword and word accesses 0 VALUE_1 Trap unaligned halfword and word accesses 1 DIV_0_TRP Divide by zero trap 4 1 BFHFNMIGN BusFault in HardFault or NMI ignore 8 1 STKOFHFNMIGN Stack overflow in HardFault and NMI ignore 10 1 DC Data cache enable 16 1 IC Instruction cache enable 17 1 BP Branch prediction enable 18 1 SHPR2 System Handler Priority Register 2 0x1C 32 PRI_11 Priority of system handler 11, SVCall 24 8 SHPR3 System Handler Priority Register 3 0x20 32 PRI_12 Priority of system handler 12, DebugMonitor 0 8 PRI_14 Priority of system handler 14, PendSV 16 8 PRI_15 Priority of system handler 15, SysTick 24 8 SHCSR System Handler Control and State Register 0x24 32 HARDFAULTACT HardFault exception active state 2 1 NMIACT NMI exception active state 5 1 SVCALLACT SVCall exception active state 7 1 PENDSVACT PendSV exception active state 10 1 SYSTICKACT SysTick exception active state 11 1 SVCALLPENDED SVCall exception pended state 15 1 HARDFAULTPENDED HardFault exception pended state 21 1 DFSR Debug Fault Status Register 0x30 32 HALTED Halt or step event 0 1 BKPT Breakpoint event 1 1 DWTTRAP Watchpoint event 2 1 VCATCH Vector Catch event 3 1 EXTERNAL External event 4 1 AFSR Auxiliary Fault Status Register 0x3C 32 CLIDR Cache Level ID Register 0x78 32 read-only Ctype1 Cache type at level 1 0 3 Ctype1Select NO No cache 0 IC Instruction cache only 1 DC Data cache only 2 SEPARATE Separate instruction and data caches 3 UNIFIED Unified cache 4 Ctype2 Cache type at level 2 3 3 Ctype2Select NO No cache 0 IC Instruction cache only 1 DC Data cache only 2 SEPARATE Separate instruction and data caches 3 UNIFIED Unified cache 4 Ctype3 Cache type at level 3 6 3 Ctype3Select NO No cache 0 IC Instruction cache only 1 DC Data cache only 2 SEPARATE Separate instruction and data caches 3 UNIFIED Unified cache 4 Ctype4 Cache type at level 4 9 3 Ctype4Select NO No cache 0 IC Instruction cache only 1 DC Data cache only 2 SEPARATE Separate instruction and data caches 3 UNIFIED Unified cache 4 Ctype5 Cache type at level 5 12 3 Ctype5Select NO No cache 0 IC Instruction cache only 1 DC Data cache only 2 SEPARATE Separate instruction and data caches 3 UNIFIED Unified cache 4 Ctype6 Cache type at level 6 15 3 Ctype6Select NO No cache 0 IC Instruction cache only 1 DC Data cache only 2 SEPARATE Separate instruction and data caches 3 UNIFIED Unified cache 4 Ctype7 Cache type at level 7 18 3 Ctype7Select NO No cache 0 IC Instruction cache only 1 DC Data cache only 2 SEPARATE Separate instruction and data caches 3 UNIFIED Unified cache 4 LoUIS Level of Unification Inner Shareable 21 3 LoC Level of Coherence 24 3 LoUU Level of Unification Uniprocessor 27 3 ICB Inner cache boundary 30 2 ICBSelect NO Not disclosed in this mechanism 0 L1 L1 cache is the highest inner level 1 L2 L2 cache is the highest inner level 2 L3 L3 cache is the highest inner level 3 CTR Cache Type Register 0x7C 32 read-only IminLine Instruction cache minimum line length 0 4 DminLine Data cache minimum line length 16 4 ERG Exclusives Reservation Granule 20 4 CWG Cache Write-back Granule 24 4 Format Cache Type Register format 29 3 FormatSelect NO No cache type information provided 0 YES Cache type information is provided 4 CCSIDR Current Cache Size ID register 0x80 32 read-only LineSize log2(number of words per line) - 2 0 3 Associativity Associativity - 1 3 10 NumSets Number of sets - 1 13 15 WA Write-Allocate 28 1 RA Read-Allocate 29 1 WB Write-Back 30 1 WT Write-Through 31 1 CSSELR Cache Size Selection Register 0x84 32 InD Instruction not Data 0 1 Level Cache level - 1 1 3 SCB_NS 0xE002ED00 SysTick SysTick Timer SysTick SysTick_ 0xE000E010 0 0x10 registers SYST_CSR SysTick Control and Status Register 0x0 32 ENABLE SysTick enable 0 1 TICKINT Tick interrupt 1 1 CLKSOURCE Clock source 2 1 COUNTFLAG Count flag 16 1 SYST_RVR SysTick Reload Value Register 0x4 32 RELOAD Counter reload value 24 1 SYST_CVR SysTick Current Value Register 0x8 32 CURRENT Current counter value 24 1 SYST_CALIB SysTick Calibration Value Register 0xC 32 read-only TENMS Ten milliseconds 0 24 SKEW Skew 30 1 NOREF No reference 31 1 SysTick_NS 0xE002E010