Microchip Technology MCHP ATSAMD51J20A SAMD51 0 Microchip ATSAMD51J20A Microcontroller CM4 r0p1 selectable true true 3 false 8 32 32 read-write 0x00000000 0xFFFFFFFF AC U25011.0.0 Analog Comparators AC AC_ 0x42002000 0 0x26 registers AC 122 CTRLA Control A 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 CTRLB Control B 0x1 8 write-only 0x00 START0 Comparator 0 Start Comparison 0 1 START1 Comparator 1 Start Comparison 1 1 EVCTRL Event Control 0x2 16 0x0000 COMPEO0 Comparator 0 Event Output Enable 0 1 COMPEO1 Comparator 1 Event Output Enable 1 1 WINEO0 Window 0 Event Output Enable 4 1 COMPEI0 Comparator 0 Event Input Enable 8 1 COMPEI1 Comparator 1 Event Input Enable 9 1 INVEI0 Comparator 0 Input Event Invert Enable 12 1 INVEI1 Comparator 1 Input Event Invert Enable 13 1 INTENCLR Interrupt Enable Clear 0x4 8 0x00 COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 WIN0 Window 0 Interrupt Enable 4 1 INTENSET Interrupt Enable Set 0x5 8 0x00 COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 WIN0 Window 0 Interrupt Enable 4 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 0x00 COMP0 Comparator 0 0 1 COMP1 Comparator 1 1 1 WIN0 Window 0 4 1 STATUSA Status A 0x7 8 read-only 0x00 STATE0 Comparator 0 Current State 0 1 STATE1 Comparator 1 Current State 1 1 WSTATE0 Window 0 Current State 4 2 WSTATE0Select ABOVE Signal is above window 0 INSIDE Signal is inside window 1 BELOW Signal is below window 2 STATUSB Status B 0x8 8 read-only 0x00 READY0 Comparator 0 Ready 0 1 READY1 Comparator 1 Ready 1 1 DBGCTRL Debug Control 0x9 8 0x00 DBGRUN Debug Run 0 1 WINCTRL Window Control 0xA 8 0x00 WEN0 Window 0 Mode Enable 0 1 WINTSEL0 Window 0 Interrupt Selection 1 2 WINTSEL0Select ABOVE Interrupt on signal above window 0 INSIDE Interrupt on signal inside window 1 BELOW Interrupt on signal below window 2 OUTSIDE Interrupt on signal outside window 3 2 1 SCALER[%s] Scaler n 0xC 8 0x00 VALUE Scaler Value 0 6 2 4 COMPCTRL[%s] Comparator Control n 0x10 32 0x00000000 ENABLE Enable 1 1 SINGLE Single-Shot Mode 2 1 INTSEL Interrupt Selection 3 2 INTSELSelect TOGGLE Interrupt on comparator output toggle 0 RISING Interrupt on comparator output rising 1 FALLING Interrupt on comparator output falling 2 EOC Interrupt on end of comparison (single-shot mode only) 3 RUNSTDBY Run in Standby 6 1 MUXNEG Negative Input Mux Selection 8 3 MUXNEGSelect PIN0 I/O pin 0 0 PIN1 I/O pin 1 1 PIN2 I/O pin 2 2 PIN3 I/O pin 3 3 GND Ground 4 VSCALE VDD scaler 5 BANDGAP Internal bandgap voltage 6 DAC DAC output 7 MUXPOS Positive Input Mux Selection 12 3 MUXPOSSelect PIN0 I/O pin 0 0 PIN1 I/O pin 1 1 PIN2 I/O pin 2 2 PIN3 I/O pin 3 3 VSCALE VDD Scaler 4 SWAP Swap Inputs and Invert 15 1 SPEED Speed Selection 16 2 SPEEDSelect HIGH High speed 3 HYSTEN Hysteresis Enable 19 1 HYST Hysteresis Level 20 2 HYSTSelect HYST50 50mV 0 HYST100 100mV 1 HYST150 150mV 2 FLEN Filter Length 24 3 FLENSelect OFF No filtering 0 MAJ3 3-bit majority function (2 of 3) 1 MAJ5 5-bit majority function (3 of 5) 2 OUT Output 28 2 OUTSelect OFF The output of COMPn is not routed to the COMPn I/O port 0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 1 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port 2 SYNCBUSY Synchronization Busy 0x20 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE Enable Synchronization Busy 1 1 WINCTRL WINCTRL Synchronization Busy 2 1 COMPCTRL0 COMPCTRL 0 Synchronization Busy 3 1 COMPCTRL1 COMPCTRL 1 Synchronization Busy 4 1 CALIB Calibration 0x24 16 0x0101 BIAS0 COMP0/1 Bias Scaling 0 2 ADC0 U25001.0.0 Analog Digital Converter ADC ADC_ 0x43001C00 0 0x4A registers ADC0_OTHER 118 ADC0_RESRDY 119 CTRLA Control A 0x0 16 0x0000 SWRST Software Reset 0 1 ENABLE Enable 1 1 DUALSEL Dual Mode Trigger Selection 3 2 DUALSELSelect BOTH Start event or software trigger will start a conversion on both ADCs 0 INTERLEAVE START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 1 SLAVEEN Slave Enable 5 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 PRESCALER Prescaler Configuration 8 3 PRESCALERSelect DIV2 Peripheral clock divided by 2 0 DIV4 Peripheral clock divided by 4 1 DIV8 Peripheral clock divided by 8 2 DIV16 Peripheral clock divided by 16 3 DIV32 Peripheral clock divided by 32 4 DIV64 Peripheral clock divided by 64 5 DIV128 Peripheral clock divided by 128 6 DIV256 Peripheral clock divided by 256 7 R2R Rail to Rail Operation Enable 15 1 EVCTRL Event Control 0x2 8 0x00 FLUSHEI Flush Event Input Enable 0 1 STARTEI Start Conversion Event Input Enable 1 1 FLUSHINV Flush Event Invert Enable 2 1 STARTINV Start Conversion Event Invert Enable 3 1 RESRDYEO Result Ready Event Out 4 1 WINMONEO Window Monitor Event Out 5 1 DBGCTRL Debug Control 0x3 8 0x00 DBGRUN Debug Run 0 1 INPUTCTRL Input Control 0x4 16 0x0000 MUXPOS Positive Mux Input Selection 0 5 MUXPOSSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 AIN6 ADC AIN6 Pin 0x6 AIN7 ADC AIN7 Pin 0x7 AIN8 ADC AIN8 Pin 0x8 AIN9 ADC AIN9 Pin 0x9 AIN10 ADC AIN10 Pin 0xA AIN11 ADC AIN11 Pin 0xB AIN12 ADC AIN12 Pin 0xC AIN13 ADC AIN13 Pin 0xD AIN14 ADC AIN14 Pin 0xE AIN15 ADC AIN15 Pin 0xF AIN16 ADC AIN16 Pin 0x10 AIN17 ADC AIN17 Pin 0x11 AIN18 ADC AIN18 Pin 0x12 AIN19 ADC AIN19 Pin 0x13 AIN20 ADC AIN20 Pin 0x14 AIN21 ADC AIN21 Pin 0x15 AIN22 ADC AIN22 Pin 0x16 AIN23 ADC AIN23 Pin 0x17 SCALEDCOREVCC 1/4 Scaled Core Supply 0x18 SCALEDVBAT 1/4 Scaled VBAT Supply 0x19 SCALEDIOVCC 1/4 Scaled I/O Supply 0x1A BANDGAP Bandgap Voltage 0x1B PTAT Temperature Sensor 0x1C CTAT Temperature Sensor 0x1D DAC DAC Output 0x1E PTC PTC output (only on ADC0) 0x1F DIFFMODE Differential Mode 7 1 MUXNEG Negative Mux Input Selection 8 5 MUXNEGSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 AIN6 ADC AIN6 Pin 0x6 AIN7 ADC AIN7 Pin 0x7 GND Internal Ground 0x18 DSEQSTOP Stop DMA Sequencing 15 1 CTRLB Control B 0x6 16 0x0000 LEFTADJ Left-Adjusted Result 0 1 FREERUN Free Running Mode 1 1 CORREN Digital Correction Logic Enable 2 1 RESSEL Conversion Result Resolution 3 2 RESSELSelect 12BIT 12-bit result 0x0 16BIT For averaging mode output 0x1 10BIT 10-bit result 0x2 8BIT 8-bit result 0x3 WINMODE Window Monitor Mode 8 3 WINMODESelect DISABLE No window mode (default) 0 MODE1 RESULT > WINLT 1 MODE2 RESULT < WINUT 2 MODE3 WINLT < RESULT < WINUT 3 MODE4 !(WINLT < RESULT < WINUT) 4 WINSS Window Single Sample 11 1 REFCTRL Reference Control 0x8 8 0x00 REFSEL Reference Selection 0 4 REFSELSelect INTREF Internal Bandgap Reference 0x0 INTVCC0 1/2 VDDANA 0x2 INTVCC1 VDDANA 0x3 AREFA External Reference 0x4 AREFB External Reference 0x5 AREFC External Reference (only on ADC1) 0x6 REFCOMP Reference Buffer Offset Compensation Enable 7 1 AVGCTRL Average Control 0xA 8 0x00 SAMPLENUM Number of Samples to be Collected 0 4 SAMPLENUMSelect 1 1 sample 0x0 2 2 samples 0x1 4 4 samples 0x2 8 8 samples 0x3 16 16 samples 0x4 32 32 samples 0x5 64 64 samples 0x6 128 128 samples 0x7 256 256 samples 0x8 512 512 samples 0x9 1024 1024 samples 0xA ADJRES Adjusting Result / Division Coefficient 4 3 SAMPCTRL Sample Time Control 0xB 8 0x00 SAMPLEN Sampling Time Length 0 6 OFFCOMP Comparator Offset Compensation Enable 7 1 WINLT Window Monitor Lower Threshold 0xC 16 0x0000 WINLT Window Lower Threshold 0 16 WINUT Window Monitor Upper Threshold 0xE 16 0x0000 WINUT Window Upper Threshold 0 16 GAINCORR Gain Correction 0x10 16 0x0000 GAINCORR Gain Correction Value 0 12 OFFSETCORR Offset Correction 0x12 16 0x0000 OFFSETCORR Offset Correction Value 0 12 SWTRIG Software Trigger 0x14 8 0x00 FLUSH ADC Conversion Flush 0 1 START Start ADC Conversion 1 1 INTENCLR Interrupt Enable Clear 0x2C 8 0x00 RESRDY Result Ready Interrupt Disable 0 1 OVERRUN Overrun Interrupt Disable 1 1 WINMON Window Monitor Interrupt Disable 2 1 INTENSET Interrupt Enable Set 0x2D 8 0x00 RESRDY Result Ready Interrupt Enable 0 1 OVERRUN Overrun Interrupt Enable 1 1 WINMON Window Monitor Interrupt Enable 2 1 INTFLAG Interrupt Flag Status and Clear 0x2E 8 0x00 RESRDY Result Ready Interrupt Flag 0 1 OVERRUN Overrun Interrupt Flag 1 1 WINMON Window Monitor Interrupt Flag 2 1 STATUS Status 0x2F 8 read-only 0x00 ADCBUSY ADC Busy Status 0 1 WCC Window Comparator Counter 2 6 SYNCBUSY Synchronization Busy 0x30 32 read-only 0x00000000 SWRST SWRST Synchronization Busy 0 1 ENABLE ENABLE Synchronization Busy 1 1 INPUTCTRL Input Control Synchronization Busy 2 1 CTRLB Control B Synchronization Busy 3 1 REFCTRL Reference Control Synchronization Busy 4 1 AVGCTRL Average Control Synchronization Busy 5 1 SAMPCTRL Sampling Time Control Synchronization Busy 6 1 WINLT Window Monitor Lower Threshold Synchronization Busy 7 1 WINUT Window Monitor Upper Threshold Synchronization Busy 8 1 GAINCORR Gain Correction Synchronization Busy 9 1 OFFSETCORR Offset Correction Synchronization Busy 10 1 SWTRIG Software Trigger Synchronization Busy 11 1 DSEQDATA DMA Sequencial Data 0x34 32 write-only 0x00000000 DATA DMA Sequential Data 0 32 DSEQCTRL DMA Sequential Control 0x38 32 0x00000000 INPUTCTRL Input Control 0 1 CTRLB Control B 1 1 REFCTRL Reference Control 2 1 AVGCTRL Average Control 3 1 SAMPCTRL Sampling Time Control 4 1 WINLT Window Monitor Lower Threshold 5 1 WINUT Window Monitor Upper Threshold 6 1 GAINCORR Gain Correction 7 1 OFFSETCORR Offset Correction 8 1 AUTOSTART ADC Auto-Start Conversion 31 1 DSEQSTAT DMA Sequencial Status 0x3C 32 read-only 0x00000000 INPUTCTRL Input Control 0 1 CTRLB Control B 1 1 REFCTRL Reference Control 2 1 AVGCTRL Average Control 3 1 SAMPCTRL Sampling Time Control 4 1 WINLT Window Monitor Lower Threshold 5 1 WINUT Window Monitor Upper Threshold 6 1 GAINCORR Gain Correction 7 1 OFFSETCORR Offset Correction 8 1 BUSY DMA Sequencing Busy 31 1 RESULT Result Conversion Value 0x40 16 read-only 0x0000 RESULT Result Conversion Value 0 16 RESS Last Sample Result 0x44 16 read-only 0x0000 RESS Last ADC conversion result 0 16 CALIB Calibration 0x48 16 0x0000 BIASCOMP Bias Comparator Scaling 0 3 BIASR2R Bias R2R Ampli scaling 4 3 BIASREFBUF Bias Reference Buffer Scaling 8 3 ADC1 0x43002000 ADC1_OTHER 120 ADC1_RESRDY 121 AES U22382.2.0 Advanced Encryption Standard AES AES_ 0x42002400 0 0x88 registers AES 130 CTRLA Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 AESMODE AES Modes of operation 2 3 AESMODESelect ECB Electronic code book mode 0x0 CBC Cipher block chaining mode 0x1 OFB Output feedback mode 0x2 CFB Cipher feedback mode 0x3 COUNTER Counter mode 0x4 CCM CCM mode 0x5 GCM Galois counter mode 0x6 CFBS Cipher Feedback Block Size 5 3 CFBSSelect 128BIT 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode 0x0 64BIT 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode 0x1 32BIT 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode 0x2 16BIT 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode 0x3 8BIT 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode 0x4 KEYSIZE Encryption Key Size 8 2 KEYSIZESelect 128BIT 128-bit Key for Encryption / Decryption 0x0 192BIT 192-bit Key for Encryption / Decryption 0x1 256BIT 256-bit Key for Encryption / Decryption 0x2 CIPHER Cipher Mode 10 1 CIPHERSelect DEC Decryption 0x0 ENC Encryption 0x1 STARTMODE Start Mode Select 11 1 STARTMODESelect MANUAL Start Encryption / Decryption in Manual mode 0x0 AUTO Start Encryption / Decryption in Auto mode 0x1 LOD Last Output Data Mode 12 1 LODSelect NONE No effect 0x0 LAST Start encryption in Last Output Data mode 0x1 KEYGEN Last Key Generation 13 1 KEYGENSelect NONE No effect 0x0 LAST Start Computation of the last NK words of the expanded key 0x1 XORKEY XOR Key Operation 14 1 XORKEYSelect NONE No effect 0x0 XOR The user keyword gets XORed with the previous keyword register content. 0x1 CTYPE Counter Measure Type 16 4 CTRLB Control B 0x4 8 0x00 START Start Encryption/Decryption 0 1 NEWMSG New message 1 1 EOM End of message 2 1 GFMUL GF Multiplication 3 1 INTENCLR Interrupt Enable Clear 0x5 8 0x00 ENCCMP Encryption Complete Interrupt Enable 0 1 GFMCMP GF Multiplication Complete Interrupt Enable 1 1 INTENSET Interrupt Enable Set 0x6 8 0x00 ENCCMP Encryption Complete Interrupt Enable 0 1 GFMCMP GF Multiplication Complete Interrupt Enable 1 1 INTFLAG Interrupt Flag Status 0x7 8 0x00 ENCCMP Encryption Complete 0 1 GFMCMP GF Multiplication Complete 1 1 DATABUFPTR Data buffer pointer 0x8 8 0x00 INDATAPTR Input Data Pointer 0 2 DBGCTRL Debug control 0x9 8 0x00 DBGRUN Debug Run 0 1 8 4 KEYWORD[%s] Keyword n 0xC 32 write-only 0x00000000 INDATA Indata 0x38 32 0x00000000 4 4 INTVECTV[%s] Initialisation Vector n 0x3C 32 write-only 0x00000000 4 4 HASHKEY[%s] Hash key n 0x5C 32 0x00000000 4 4 GHASH[%s] Galois Hash n 0x6C 32 0x00000000 CIPLEN Cipher Length 0x80 32 0x00000000 RANDSEED Random Seed 0x84 32 0x00000000 CCL U22251.1.0 Configurable Custom Logic CCL CCL_ 0x42003800 0 0x18 registers CTRL Control 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 RUNSTDBY Run in Standby 6 1 2 1 SEQCTRL[%s] SEQ Control x 0x4 8 0x00 SEQSEL Sequential Selection 0 4 SEQSELSelect DISABLE Sequential logic is disabled 0 DFF D flip flop 1 JK JK flip flop 2 LATCH D latch 3 RS RS latch 4 4 4 LUTCTRL[%s] LUT Control x 0x8 32 0x00000000 ENABLE LUT Enable 1 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0 SYNCH Synchronizer enabled 1 FILTER Filter enabled 2 EDGESEL Edge Selection 7 1 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INSEL1 Input Selection 1 12 4 INSEL1Select MASK Masked input 0x0 FEEDBACK Feedback input source 0x1 LINK Linked LUT input source 0x2 EVENT Event input source 0x3 IO I/O pin input source 0x4 AC AC input source 0x5 TC TC input source 0x6 ALTTC Alternate TC input source 0x7 TCC TCC input source 0x8 SERCOM SERCOM input source 0x9 INSEL2 Input Selection 2 16 4 INSEL2Select MASK Masked input 0x0 FEEDBACK Feedback input source 0x1 LINK Linked LUT input source 0x2 EVENT Event input source 0x3 IO I/O pin input source 0x4 AC AC input source 0x5 TC TC input source 0x6 ALTTC Alternate TC input source 0x7 TCC TCC input source 0x8 SERCOM SERCOM input source 0x9 INVEI Inverted Event Input Enable 20 1 LUTEI LUT Event Input Enable 21 1 LUTEO LUT Event Output Enable 22 1 TRUTH Truth Value 24 8 CMCC U20156.0.0 Cortex M Cache Controller CMCC CMCC_ 0x41006000 0 0x38 registers TYPE Cache Type Register 0x0 32 read-only 0x000012D2 GCLK dynamic Clock Gating supported 1 1 RRP Round Robin Policy supported 4 1 WAYNUM Number of Way 5 2 WAYNUMSelect DMAPPED Direct Mapped Cache 0 ARCH2WAY 2-WAY set associative 1 ARCH4WAY 4-WAY set associative 2 LCKDOWN Lock Down supported 7 1 CSIZE Cache Size 8 3 CSIZESelect CSIZE_1KB Cache Size is 1 KB 0 CSIZE_2KB Cache Size is 2 KB 1 CSIZE_4KB Cache Size is 4 KB 2 CSIZE_8KB Cache Size is 8 KB 3 CSIZE_16KB Cache Size is 16 KB 4 CSIZE_32KB Cache Size is 32 KB 5 CSIZE_64KB Cache Size is 64 KB 6 CLSIZE Cache Line Size 11 3 CLSIZESelect CLSIZE_4B Cache Line Size is 4 bytes 0 CLSIZE_8B Cache Line Size is 8 bytes 1 CLSIZE_16B Cache Line Size is 16 bytes 2 CLSIZE_32B Cache Line Size is 32 bytes 3 CLSIZE_64B Cache Line Size is 64 bytes 4 CLSIZE_128B Cache Line Size is 128 bytes 5 CFG Cache Configuration Register 0x4 32 0x00000020 ICDIS Instruction Cache Disable 1 1 DCDIS Data Cache Disable 2 1 CSIZESW Cache size configured by software 4 3 CSIZESWSelect CONF_CSIZE_1KB The Cache Size is configured to 1KB 0 CONF_CSIZE_2KB The Cache Size is configured to 2KB 1 CONF_CSIZE_4KB The Cache Size is configured to 4KB 2 CONF_CSIZE_8KB The Cache Size is configured to 8KB 3 CONF_CSIZE_16KB The Cache Size is configured to 16KB 4 CONF_CSIZE_32KB The Cache Size is configured to 32KB 5 CONF_CSIZE_64KB The Cache Size is configured to 64KB 6 CTRL Cache Control Register 0x8 32 write-only 0x00000000 CEN Cache Controller Enable 0 1 SR Cache Status Register 0xC 32 read-only 0x00000000 CSTS Cache Controller Status 0 1 LCKWAY Cache Lock per Way Register 0x10 32 0x00000000 LCKWAY Lockdown way Register 0 4 MAINT0 Cache Maintenance Register 0 0x20 32 write-only 0x00000000 INVALL Cache Controller invalidate All 0 1 MAINT1 Cache Maintenance Register 1 0x24 32 write-only 0x00000000 INDEX Invalidate Index 4 8 WAY Invalidate Way 28 4 WAYSelect WAY0 Way 0 is selection for index invalidation 0 WAY1 Way 1 is selection for index invalidation 1 WAY2 Way 2 is selection for index invalidation 2 WAY3 Way 3 is selection for index invalidation 3 MCFG Cache Monitor Configuration Register 0x28 32 0x00000000 MODE Cache Controller Monitor Counter Mode 0 2 MODESelect CYCLE_COUNT Cycle counter 0 IHIT_COUNT Instruction hit counter 1 DHIT_COUNT Data hit counter 2 MEN Cache Monitor Enable Register 0x2C 32 0x00000000 MENABLE Cache Controller Monitor Enable 0 1 MCTRL Cache Monitor Control Register 0x30 32 write-only 0x00000000 SWRST Cache Controller Software Reset 0 1 MSR Cache Monitor Status Register 0x34 32 read-only 0x00000000 EVENT_CNT Monitor Event Counter 0 32 DAC U25021.0.0 Digital-to-Analog Converter DAC DAC_ 0x43002400 0 0x20 registers DAC_OTHER 123 DAC_EMPTY_0 124 DAC_EMPTY_1 125 DAC_RESRDY_0 126 DAC_RESRDY_1 127 CTRLA Control A 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable DAC Controller 1 1 CTRLB Control B 0x1 8 0x02 DIFF Differential mode enable 0 1 REFSEL Reference Selection for DAC0/1 1 2 REFSELSelect VREFPU External reference unbuffered 0 VDDANA Analog supply 1 VREFPB External reference buffered 2 INTREF Internal bandgap reference 3 EVCTRL Event Control 0x2 8 0x00 STARTEI0 Start Conversion Event Input DAC 0 0 1 STARTEI1 Start Conversion Event Input DAC 1 1 1 EMPTYEO0 Data Buffer Empty Event Output DAC 0 2 1 EMPTYEO1 Data Buffer Empty Event Output DAC 1 3 1 INVEI0 Enable Invertion of DAC 0 input event 4 1 INVEI1 Enable Invertion of DAC 1 input event 5 1 RESRDYEO0 Result Ready Event Output 0 6 1 RESRDYEO1 Result Ready Event Output 1 7 1 INTENCLR Interrupt Enable Clear 0x4 8 0x00 UNDERRUN0 Underrun 0 Interrupt Enable 0 1 UNDERRUN1 Underrun 1 Interrupt Enable 1 1 EMPTY0 Data Buffer 0 Empty Interrupt Enable 2 1 EMPTY1 Data Buffer 1 Empty Interrupt Enable 3 1 RESRDY0 Result 0 Ready Interrupt Enable 4 1 RESRDY1 Result 1 Ready Interrupt Enable 5 1 OVERRUN0 Overrun 0 Interrupt Enable 6 1 OVERRUN1 Overrun 1 Interrupt Enable 7 1 INTENSET Interrupt Enable Set 0x5 8 0x00 UNDERRUN0 Underrun 0 Interrupt Enable 0 1 UNDERRUN1 Underrun 1 Interrupt Enable 1 1 EMPTY0 Data Buffer 0 Empty Interrupt Enable 2 1 EMPTY1 Data Buffer 1 Empty Interrupt Enable 3 1 RESRDY0 Result 0 Ready Interrupt Enable 4 1 RESRDY1 Result 1 Ready Interrupt Enable 5 1 OVERRUN0 Overrun 0 Interrupt Enable 6 1 OVERRUN1 Overrun 1 Interrupt Enable 7 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 0x00 UNDERRUN0 Result 0 Underrun 0 1 UNDERRUN1 Result 1 Underrun 1 1 EMPTY0 Data Buffer 0 Empty 2 1 EMPTY1 Data Buffer 1 Empty 3 1 RESRDY0 Result 0 Ready 4 1 RESRDY1 Result 1 Ready 5 1 OVERRUN0 Result 0 Overrun 6 1 OVERRUN1 Result 1 Overrun 7 1 STATUS Status 0x7 8 read-only 0x00 READY0 DAC 0 Startup Ready 0 1 READY1 DAC 1 Startup Ready 1 1 EOC0 DAC 0 End of Conversion 2 1 EOC1 DAC 1 End of Conversion 3 1 SYNCBUSY Synchronization Busy 0x8 32 read-only 0x00000000 SWRST Software Reset 0 1 ENABLE DAC Enable Status 1 1 DATA0 Data DAC 0 2 1 DATA1 Data DAC 1 3 1 DATABUF0 Data Buffer DAC 0 4 1 DATABUF1 Data Buffer DAC 1 5 1 2 2 DACCTRL[%s] DAC n Control 0xC 16 0x0000 LEFTADJ Left Adjusted Data 0 1 ENABLE Enable DAC0 1 1 CCTRL Current Control 2 2 CCTRLSelect CC100K 100kSPS 0x0 CC1M 500kSPS 0x1 CC12M 1MSPS 0x2 FEXT Standalone Filter 5 1 RUNSTDBY Run in Standby 6 1 DITHER Dithering Mode 7 1 REFRESH Refresh period 8 4 REFRESHSelect REFRESH_0 Do not Refresh 0 REFRESH_1 Refresh every 30 us 1 REFRESH_2 Refresh every 60 us 2 REFRESH_3 Refresh every 90 us 3 REFRESH_4 Refresh every 120 us 4 REFRESH_5 Refresh every 150 us 5 REFRESH_6 Refresh every 180 us 6 REFRESH_7 Refresh every 210 us 7 REFRESH_8 Refresh every 240 us 8 REFRESH_9 Refresh every 270 us 9 REFRESH_10 Refresh every 300 us 10 REFRESH_11 Refresh every 330 us 11 REFRESH_12 Refresh every 360 us 12 REFRESH_13 Refresh every 390 us 13 REFRESH_14 Refresh every 420 us 14 REFRESH_15 Refresh every 450 us 15 OSR Sampling Rate 13 3 OSRSelect OSR_1 No Over Sampling 0 OSR_2 2x Over Sampling Ratio 1 OSR_4 4x Over Sampling Ratio 2 OSR_8 8x Over Sampling Ratio 3 OSR_16 16x Over Sampling Ratio 4 OSR_32 32x Over Sampling Ratio 5 2 2 DATA[%s] DAC n Data 0x10 16 write-only 0x0000 DATA DAC0 Data 0 16 2 2 DATABUF[%s] DAC n Data Buffer 0x14 16 write-only 0x0000 DATABUF DAC0 Data Buffer 0 16 DBGCTRL Debug Control 0x18 8 0x00 DBGRUN Debug Run 0 1 2 2 RESULT[%s] Filter Result 0x1C 16 read-only 0x0000 RESULT Filter Result 0 16 DMAC U25031.0.1 Direct Memory Access Controller DMAC DMAC_ 0x4100A000 0 0x360 registers DMAC_0 31 DMAC_1 32 DMAC_2 33 DMAC_3 34 DMAC_OTHER 35 CTRL Control 0x0 16 0x0000 SWRST Software Reset 0 1 DMAENABLE DMA Enable 1 1 LVLEN0 Priority Level 0 Enable 8 1 LVLEN1 Priority Level 1 Enable 9 1 LVLEN2 Priority Level 2 Enable 10 1 LVLEN3 Priority Level 3 Enable 11 1 CRCCTRL CRC Control 0x2 16 0x0000 CRCBEATSIZE CRC Beat Size 0 2 CRCBEATSIZESelect BYTE 8-bit bus transfer 0x0 HWORD 16-bit bus transfer 0x1 WORD 32-bit bus transfer 0x2 CRCPOLY CRC Polynomial Type 2 2 CRCPOLYSelect CRC16 CRC-16 (CRC-CCITT) 0x0 CRC32 CRC32 (IEEE 802.3) 0x1 CRCSRC CRC Input Source 8 6 CRCSRCSelect DISABLE CRC Disabled 0x00 IO I/O interface 0x01 CRCMODE CRC Operating Mode 14 2 CRCMODESelect DEFAULT Default operating mode 0 CRCMON Memory CRC monitor operating mode 2 CRCGEN Memory CRC generation operating mode 3 CRCDATAIN CRC Data Input 0x4 32 0x00000000 CRCDATAIN CRC Data Input 0 32 CRCCHKSUM CRC Checksum 0x8 32 0x00000000 CRCCHKSUM CRC Checksum 0 32 CRCSTATUS CRC Status 0xC 8 0x00 CRCBUSY CRC Module Busy 0 1 CRCZERO CRC Zero 1 1 CRCERR CRC Error 2 1 DBGCTRL Debug Control 0xD 8 0x00 DBGRUN Debug Run 0 1 SWTRIGCTRL Software Trigger Control 0x10 32 0x00000000 SWTRIG0 Channel 0 Software Trigger 0 1 SWTRIG1 Channel 1 Software Trigger 1 1 SWTRIG2 Channel 2 Software Trigger 2 1 SWTRIG3 Channel 3 Software Trigger 3 1 SWTRIG4 Channel 4 Software Trigger 4 1 SWTRIG5 Channel 5 Software Trigger 5 1 SWTRIG6 Channel 6 Software Trigger 6 1 SWTRIG7 Channel 7 Software Trigger 7 1 SWTRIG8 Channel 8 Software Trigger 8 1 SWTRIG9 Channel 9 Software Trigger 9 1 SWTRIG10 Channel 10 Software Trigger 10 1 SWTRIG11 Channel 11 Software Trigger 11 1 SWTRIG12 Channel 12 Software Trigger 12 1 SWTRIG13 Channel 13 Software Trigger 13 1 SWTRIG14 Channel 14 Software Trigger 14 1 SWTRIG15 Channel 15 Software Trigger 15 1 SWTRIG16 Channel 16 Software Trigger 16 1 SWTRIG17 Channel 17 Software Trigger 17 1 SWTRIG18 Channel 18 Software Trigger 18 1 SWTRIG19 Channel 19 Software Trigger 19 1 SWTRIG20 Channel 20 Software Trigger 20 1 SWTRIG21 Channel 21 Software Trigger 21 1 SWTRIG22 Channel 22 Software Trigger 22 1 SWTRIG23 Channel 23 Software Trigger 23 1 SWTRIG24 Channel 24 Software Trigger 24 1 SWTRIG25 Channel 25 Software Trigger 25 1 SWTRIG26 Channel 26 Software Trigger 26 1 SWTRIG27 Channel 27 Software Trigger 27 1 SWTRIG28 Channel 28 Software Trigger 28 1 SWTRIG29 Channel 29 Software Trigger 29 1 SWTRIG30 Channel 30 Software Trigger 30 1 SWTRIG31 Channel 31 Software Trigger 31 1 PRICTRL0 Priority Control 0 0x14 32 0x40404040 LVLPRI0 Level 0 Channel Priority Number 0 5 QOS0 Level 0 Quality of Service 5 2 QOS0Select REGULAR Regular delivery 0 SHORTAGE Bandwidth shortage 1 SENSITIVE Latency sensitive 2 CRITICAL Latency critical 3 RRLVLEN0 Level 0 Round-Robin Scheduling Enable 7 1 LVLPRI1 Level 1 Channel Priority Number 8 5 QOS1 Level 1 Quality of Service 13 2 QOS1Select REGULAR Regular delivery 0 SHORTAGE Bandwidth shortage 1 SENSITIVE Latency sensitive 2 CRITICAL Latency critical 3 RRLVLEN1 Level 1 Round-Robin Scheduling Enable 15 1 LVLPRI2 Level 2 Channel Priority Number 16 5 QOS2 Level 2 Quality of Service 21 2 QOS2Select REGULAR Regular delivery 0 SHORTAGE Bandwidth shortage 1 SENSITIVE Latency sensitive 2 CRITICAL Latency critical 3 RRLVLEN2 Level 2 Round-Robin Scheduling Enable 23 1 LVLPRI3 Level 3 Channel Priority Number 24 5 QOS3 Level 3 Quality of Service 29 2 QOS3Select REGULAR Regular delivery 0 SHORTAGE Bandwidth shortage 1 SENSITIVE Latency sensitive 2 CRITICAL Latency critical 3 RRLVLEN3 Level 3 Round-Robin Scheduling Enable 31 1 INTPEND Interrupt Pending 0x20 16 0x0000 ID Channel ID 0 5 TERR Transfer Error 8 1 TCMPL Transfer Complete 9 1 SUSP Channel Suspend 10 1 CRCERR CRC Error 12 1 FERR Fetch Error 13 1 BUSY Busy 14 1 PEND Pending 15 1 INTSTATUS Interrupt Status 0x24 32 read-only 0x00000000 CHINT0 Channel 0 Pending Interrupt 0 1 CHINT1 Channel 1 Pending Interrupt 1 1 CHINT2 Channel 2 Pending Interrupt 2 1 CHINT3 Channel 3 Pending Interrupt 3 1 CHINT4 Channel 4 Pending Interrupt 4 1 CHINT5 Channel 5 Pending Interrupt 5 1 CHINT6 Channel 6 Pending Interrupt 6 1 CHINT7 Channel 7 Pending Interrupt 7 1 CHINT8 Channel 8 Pending Interrupt 8 1 CHINT9 Channel 9 Pending Interrupt 9 1 CHINT10 Channel 10 Pending Interrupt 10 1 CHINT11 Channel 11 Pending Interrupt 11 1 CHINT12 Channel 12 Pending Interrupt 12 1 CHINT13 Channel 13 Pending Interrupt 13 1 CHINT14 Channel 14 Pending Interrupt 14 1 CHINT15 Channel 15 Pending Interrupt 15 1 CHINT16 Channel 16 Pending Interrupt 16 1 CHINT17 Channel 17 Pending Interrupt 17 1 CHINT18 Channel 18 Pending Interrupt 18 1 CHINT19 Channel 19 Pending Interrupt 19 1 CHINT20 Channel 20 Pending Interrupt 20 1 CHINT21 Channel 21 Pending Interrupt 21 1 CHINT22 Channel 22 Pending Interrupt 22 1 CHINT23 Channel 23 Pending Interrupt 23 1 CHINT24 Channel 24 Pending Interrupt 24 1 CHINT25 Channel 25 Pending Interrupt 25 1 CHINT26 Channel 26 Pending Interrupt 26 1 CHINT27 Channel 27 Pending Interrupt 27 1 CHINT28 Channel 28 Pending Interrupt 28 1 CHINT29 Channel 29 Pending Interrupt 29 1 CHINT30 Channel 30 Pending Interrupt 30 1 CHINT31 Channel 31 Pending Interrupt 31 1 BUSYCH Busy Channels 0x28 32 read-only 0x00000000 BUSYCH0 Busy Channel 0 0 1 BUSYCH1 Busy Channel 1 1 1 BUSYCH2 Busy Channel 2 2 1 BUSYCH3 Busy Channel 3 3 1 BUSYCH4 Busy Channel 4 4 1 BUSYCH5 Busy Channel 5 5 1 BUSYCH6 Busy Channel 6 6 1 BUSYCH7 Busy Channel 7 7 1 BUSYCH8 Busy Channel 8 8 1 BUSYCH9 Busy Channel 9 9 1 BUSYCH10 Busy Channel 10 10 1 BUSYCH11 Busy Channel 11 11 1 BUSYCH12 Busy Channel 12 12 1 BUSYCH13 Busy Channel 13 13 1 BUSYCH14 Busy Channel 14 14 1 BUSYCH15 Busy Channel 15 15 1 BUSYCH16 Busy Channel 16 16 1 BUSYCH17 Busy Channel 17 17 1 BUSYCH18 Busy Channel 18 18 1 BUSYCH19 Busy Channel 19 19 1 BUSYCH20 Busy Channel 20 20 1 BUSYCH21 Busy Channel 21 21 1 BUSYCH22 Busy Channel 22 22 1 BUSYCH23 Busy Channel 23 23 1 BUSYCH24 Busy Channel 24 24 1 BUSYCH25 Busy Channel 25 25 1 BUSYCH26 Busy Channel 26 26 1 BUSYCH27 Busy Channel 27 27 1 BUSYCH28 Busy Channel 28 28 1 BUSYCH29 Busy Channel 29 29 1 BUSYCH30 Busy Channel 30 30 1 BUSYCH31 Busy Channel 31 31 1 PENDCH Pending Channels 0x2C 32 read-only 0x00000000 PENDCH0 Pending Channel 0 0 1 PENDCH1 Pending Channel 1 1 1 PENDCH2 Pending Channel 2 2 1 PENDCH3 Pending Channel 3 3 1 PENDCH4 Pending Channel 4 4 1 PENDCH5 Pending Channel 5 5 1 PENDCH6 Pending Channel 6 6 1 PENDCH7 Pending Channel 7 7 1 PENDCH8 Pending Channel 8 8 1 PENDCH9 Pending Channel 9 9 1 PENDCH10 Pending Channel 10 10 1 PENDCH11 Pending Channel 11 11 1 PENDCH12 Pending Channel 12 12 1 PENDCH13 Pending Channel 13 13 1 PENDCH14 Pending Channel 14 14 1 PENDCH15 Pending Channel 15 15 1 PENDCH16 Pending Channel 16 16 1 PENDCH17 Pending Channel 17 17 1 PENDCH18 Pending Channel 18 18 1 PENDCH19 Pending Channel 19 19 1 PENDCH20 Pending Channel 20 20 1 PENDCH21 Pending Channel 21 21 1 PENDCH22 Pending Channel 22 22 1 PENDCH23 Pending Channel 23 23 1 PENDCH24 Pending Channel 24 24 1 PENDCH25 Pending Channel 25 25 1 PENDCH26 Pending Channel 26 26 1 PENDCH27 Pending Channel 27 27 1 PENDCH28 Pending Channel 28 28 1 PENDCH29 Pending Channel 29 29 1 PENDCH30 Pending Channel 30 30 1 PENDCH31 Pending Channel 31 31 1 ACTIVE Active Channel and Levels 0x30 32 read-only 0x00000000 LVLEX0 Level 0 Channel Trigger Request Executing 0 1 LVLEX1 Level 1 Channel Trigger Request Executing 1 1 LVLEX2 Level 2 Channel Trigger Request Executing 2 1 LVLEX3 Level 3 Channel Trigger Request Executing 3 1 ID Active Channel ID 8 5 ABUSY Active Channel Busy 15 1 BTCNT Active Channel Block Transfer Count 16 16 BASEADDR Descriptor Memory Section Base Address 0x34 32 0x00000000 BASEADDR Descriptor Memory Base Address 0 32 WRBADDR Write-Back Memory Section Base Address 0x38 32 0x00000000 WRBADDR Write-Back Memory Base Address 0 32 32 0x10 CHANNEL[%s] 0x40 CHCTRLA Channel n Control A 0x0 32 0x00000000 SWRST Channel Software Reset 0 1 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 CHCTRLB Channel n Control B 0x4 8 0x00 CMD Software Command 0 2 CMDSelect NOACT No action 0x0 SUSPEND Channel suspend operation 0x1 RESUME Channel resume operation 0x2 CHPRILVL Channel n Priority Level 0x5 8 0x00 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHEVCTRL Channel n Event Control 0x6 8 0x00 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 CHINTENCLR Channel n Interrupt Enable Clear 0xC 8 0x00 TERR Channel Transfer Error Interrupt Enable 0 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 SUSP Channel Suspend Interrupt Enable 2 1 CHINTENSET Channel n Interrupt Enable Set 0xD 8 0x00 TERR Channel Transfer Error Interrupt Enable 0 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 SUSP Channel Suspend Interrupt Enable 2 1 CHINTFLAG Channel n Interrupt Flag Status and Clear 0xE 8 0x00 TERR Channel Transfer Error 0 1 TCMPL Channel Transfer Complete 1 1 SUSP Channel Suspend 2 1 CHSTATUS Channel n Status 0xF 8 0x00 PEND Channel Pending 0 1 BUSY Channel Busy 1 1 FERR Channel Fetch Error 2 1 CRCERR Channel CRC Error 3 1 DSU U24101.0.0 Device Service Unit DSU DSU_ 0x41002000 0 0x2000 registers CTRL Control 0x0 8 write-only 0x00 SWRST Software Reset 0 1 CRC 32-bit Cyclic Redundancy Code 2 1 MBIST Memory built-in self-test 3 1 CE Chip-Erase 4 1 ARR Auxiliary Row Read 6 1 SMSA Start Memory Stream Access 7 1 STATUSA Status A 0x1 8 0x00 DONE Done 0 1 CRSTEXT CPU Reset Phase Extension 1 1 BERR Bus Error 2 1 FAIL Failure 3 1 PERR Protection Error 4 1 STATUSB Status B 0x2 8 read-only 0x00 PROT Protected 0 1 DBGPRES Debugger Present 1 1 DCCD0 Debug Communication Channel 0 Dirty 2 1 DCCD1 Debug Communication Channel 1 Dirty 3 1 HPE Hot-Plugging Enable 4 1 CELCK Chip Erase Locked 5 1 TDCCD0 Test Debug Communication Channel 0 Dirty 6 1 TDCCD1 Test Debug Communication Channel 1 Dirty 7 1 ADDR Address 0x4 32 0x00000000 AMOD Access Mode 0 2 ADDR Address 2 30 LENGTH Length 0x8 32 0x00000000 LENGTH Length 2 30 DATA Data 0xC 32 0x00000000 DATA Data 0 32 2 4 DCC[%s] Debug Communication Channel n 0x10 32 0x00000000 DATA Data 0 32 DID Device Identification 0x18 32 read-only 0x60060204 DEVSEL Device Select 0 8 REVISION Revision Number 8 4 DIE Die Number 12 4 SERIES Series 16 6 SERIESSelect 0 Cortex-M0+ processor, basic feature set 0 1 Cortex-M0+ processor, USB 1 FAMILY Family 23 5 FAMILYSelect 0 General purpose microcontroller 0 1 PicoPower 1 PROCESSOR Processor 28 4 PROCESSORSelect CM0P Cortex-M0+ 0x1 CM23 Cortex-M23 0x2 CM3 Cortex-M3 0x3 CM4 Cortex-M4 0x5 CM4F Cortex-M4 with FPU 0x6 CM33 Cortex-M33 0x7 CFG Configuration 0x1C 32 0x00000002 LQOS Latency Quality Of Service 0 2 DCCDMALEVEL DMA Trigger Level 2 2 DCCDMALEVELSelect EMPTY Trigger rises when DCC is empty 0 FULL Trigger rises when DCC is full 1 ETBRAMEN Trace Control 4 1 2 4 DCFG[%s] Device Configuration 0xF0 32 0x00000000 DCFG Device Configuration 0 32 ENTRY0 CoreSight ROM Table Entry 0 0x1000 32 read-only 0x9F0FC002 EPRES Entry Present 0 1 FMT Format 1 1 ADDOFF Address Offset 12 20 ENTRY1 CoreSight ROM Table Entry 1 0x1004 32 read-only 0x00000000 END CoreSight ROM Table End 0x1008 32 read-only 0x00000000 END End Marker 0 32 MEMTYPE CoreSight ROM Table Memory Type 0x1FCC 32 read-only 0x00000000 SMEMP System Memory Present 0 1 PID4 Peripheral Identification 4 0x1FD0 32 read-only 0x00000000 JEPCC JEP-106 Continuation Code 0 4 FKBC 4KB count 4 4 PID5 Peripheral Identification 5 0x1FD4 32 read-only 0x00000000 PID6 Peripheral Identification 6 0x1FD8 32 read-only 0x00000000 PID7 Peripheral Identification 7 0x1FDC 32 read-only 0x00000000 PID0 Peripheral Identification 0 0x1FE0 32 read-only 0x000000D0 PARTNBL Part Number Low 0 8 PID1 Peripheral Identification 1 0x1FE4 32 read-only 0x000000FC PARTNBH Part Number High 0 4 JEPIDCL Low part of the JEP-106 Identity Code 4 4 PID2 Peripheral Identification 2 0x1FE8 32 read-only 0x00000009 JEPIDCH JEP-106 Identity Code High 0 3 JEPU JEP-106 Identity Code is used 3 1 REVISION Revision Number 4 4 PID3 Peripheral Identification 3 0x1FEC 32 read-only 0x00000000 CUSMOD ARM CUSMOD 0 4 REVAND Revision Number 4 4 CID0 Component Identification 0 0x1FF0 32 read-only 0x0000000D PREAMBLEB0 Preamble Byte 0 0 8 CID1 Component Identification 1 0x1FF4 32 read-only 0x00000010 PREAMBLE Preamble 0 4 CCLASS Component Class 4 4 CID2 Component Identification 2 0x1FF8 32 read-only 0x00000005 PREAMBLEB2 Preamble Byte 2 0 8 CID3 Component Identification 3 0x1FFC 32 read-only 0x000000B1 PREAMBLEB3 Preamble Byte 3 0 8 EIC U22543.0.0 External Interrupt Controller EIC EIC_ 0x40002800 0 0x3C registers EIC_EXTINT_0 12 EIC_EXTINT_1 13 EIC_EXTINT_2 14 EIC_EXTINT_3 15 EIC_EXTINT_4 16 EIC_EXTINT_5 17 EIC_EXTINT_6 18 EIC_EXTINT_7 19 EIC_EXTINT_8 20 EIC_EXTINT_9 21 EIC_EXTINT_10 22 EIC_EXTINT_11 23 EIC_EXTINT_12 24 EIC_EXTINT_13 25 EIC_EXTINT_14 26 EIC_EXTINT_15 27 CTRLA Control A 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 CKSEL Clock Selection 4 1 CKSELSelect CLK_GCLK Clocked by GCLK 0 CLK_ULP32K Clocked by ULP32K 1 NMICTRL Non-Maskable Interrupt Control 0x1 8 0x00 NMISENSE Non-Maskable Interrupt Sense Configuration 0 3 NMISENSESelect NONE No detection 0 RISE Rising-edge detection 1 FALL Falling-edge detection 2 BOTH Both-edges detection 3 HIGH High-level detection 4 LOW Low-level detection 5 NMIFILTEN Non-Maskable Interrupt Filter Enable 3 1 NMIASYNCH Asynchronous Edge Detection Mode 4 1 NMIASYNCHSelect SYNC Edge detection is clock synchronously operated 0 ASYNC Edge detection is clock asynchronously operated 1 NMIFLAG Non-Maskable Interrupt Flag Status and Clear 0x2 16 0x0000 NMI Non-Maskable Interrupt 0 1 SYNCBUSY Synchronization Busy 0x4 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy Status 0 1 ENABLE Enable Synchronization Busy Status 1 1 EVCTRL Event Control 0x8 32 0x00000000 EXTINTEO External Interrupt Event Output Enable 0 16 INTENCLR Interrupt Enable Clear 0xC 32 0x00000000 EXTINT External Interrupt Enable 0 16 INTENSET Interrupt Enable Set 0x10 32 0x00000000 EXTINT External Interrupt Enable 0 16 INTFLAG Interrupt Flag Status and Clear 0x14 32 0x00000000 EXTINT External Interrupt 0 16 ASYNCH External Interrupt Asynchronous Mode 0x18 32 0x00000000 ASYNCH Asynchronous Edge Detection Mode 0 16 ASYNCHSelect SYNC Edge detection is clock synchronously operated 0 ASYNC Edge detection is clock asynchronously operated 1 2 4 CONFIG[%s] External Interrupt Sense Configuration 0x1C 32 0x00000000 SENSE0 Input Sense Configuration 0 0 3 SENSE0Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN0 Filter Enable 0 3 1 SENSE1 Input Sense Configuration 1 4 3 SENSE1Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN1 Filter Enable 1 7 1 SENSE2 Input Sense Configuration 2 8 3 SENSE2Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN2 Filter Enable 2 11 1 SENSE3 Input Sense Configuration 3 12 3 SENSE3Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN3 Filter Enable 3 15 1 SENSE4 Input Sense Configuration 4 16 3 SENSE4Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN4 Filter Enable 4 19 1 SENSE5 Input Sense Configuration 5 20 3 SENSE5Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN5 Filter Enable 5 23 1 SENSE6 Input Sense Configuration 6 24 3 SENSE6Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN6 Filter Enable 6 27 1 SENSE7 Input Sense Configuration 7 28 3 SENSE7Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN7 Filter Enable 7 31 1 DEBOUNCEN Debouncer Enable 0x30 32 0x00000000 DEBOUNCEN Debouncer Enable 0 16 DPRESCALER Debouncer Prescaler 0x34 32 0x00000000 PRESCALER0 Debouncer Prescaler 0 3 PRESCALER0Select DIV2 EIC clock divided by 2 0 DIV4 EIC clock divided by 4 1 DIV8 EIC clock divided by 8 2 DIV16 EIC clock divided by 16 3 DIV32 EIC clock divided by 32 4 DIV64 EIC clock divided by 64 5 DIV128 EIC clock divided by 128 6 DIV256 EIC clock divided by 256 7 STATES0 Debouncer number of states 3 1 STATES0Select LFREQ3 3 low frequency samples 0 LFREQ7 7 low frequency samples 1 PRESCALER1 Debouncer Prescaler 4 3 PRESCALER1Select DIV2 EIC clock divided by 2 0 DIV4 EIC clock divided by 4 1 DIV8 EIC clock divided by 8 2 DIV16 EIC clock divided by 16 3 DIV32 EIC clock divided by 32 4 DIV64 EIC clock divided by 64 5 DIV128 EIC clock divided by 128 6 DIV256 EIC clock divided by 256 7 STATES1 Debouncer number of states 7 1 STATES1Select LFREQ3 3 low frequency samples 0 LFREQ7 7 low frequency samples 1 TICKON Pin Sampler frequency selection 16 1 TICKONSelect CLK_GCLK_EIC Clocked by GCLK 0 CLK_LFREQ Clocked by Low Frequency Clock 1 PINSTATE Pin State 0x38 32 read-only 0x00000000 PINSTATE Pin State 0 16 EVSYS U25041.0.0 Event System Interface EVSYS EVSYS_ 0x4100E000 0 0x2BC registers EVSYS_0 36 EVSYS_1 37 EVSYS_2 38 EVSYS_3 39 EVSYS_OTHER 40 CTRLA Control 0x0 8 0x00 SWRST Software Reset 0 1 SWEVT Software Event 0x4 32 write-only 0x00000000 CHANNEL0 Channel 0 Software Selection 0 1 CHANNEL1 Channel 1 Software Selection 1 1 CHANNEL2 Channel 2 Software Selection 2 1 CHANNEL3 Channel 3 Software Selection 3 1 CHANNEL4 Channel 4 Software Selection 4 1 CHANNEL5 Channel 5 Software Selection 5 1 CHANNEL6 Channel 6 Software Selection 6 1 CHANNEL7 Channel 7 Software Selection 7 1 CHANNEL8 Channel 8 Software Selection 8 1 CHANNEL9 Channel 9 Software Selection 9 1 CHANNEL10 Channel 10 Software Selection 10 1 CHANNEL11 Channel 11 Software Selection 11 1 CHANNEL12 Channel 12 Software Selection 12 1 CHANNEL13 Channel 13 Software Selection 13 1 CHANNEL14 Channel 14 Software Selection 14 1 CHANNEL15 Channel 15 Software Selection 15 1 CHANNEL16 Channel 16 Software Selection 16 1 CHANNEL17 Channel 17 Software Selection 17 1 CHANNEL18 Channel 18 Software Selection 18 1 CHANNEL19 Channel 19 Software Selection 19 1 CHANNEL20 Channel 20 Software Selection 20 1 CHANNEL21 Channel 21 Software Selection 21 1 CHANNEL22 Channel 22 Software Selection 22 1 CHANNEL23 Channel 23 Software Selection 23 1 CHANNEL24 Channel 24 Software Selection 24 1 CHANNEL25 Channel 25 Software Selection 25 1 CHANNEL26 Channel 26 Software Selection 26 1 CHANNEL27 Channel 27 Software Selection 27 1 CHANNEL28 Channel 28 Software Selection 28 1 CHANNEL29 Channel 29 Software Selection 29 1 CHANNEL30 Channel 30 Software Selection 30 1 CHANNEL31 Channel 31 Software Selection 31 1 PRICTRL Priority Control 0x8 8 0x00 PRI Channel Priority Number 0 4 RREN Round-Robin Scheduling Enable 7 1 INTPEND Channel Pending Interrupt 0x10 16 0x4000 ID Channel ID 0 4 OVR Channel Overrun 8 1 EVD Channel Event Detected 9 1 READY Ready 14 1 BUSY Busy 15 1 INTSTATUS Interrupt Status 0x14 32 read-only 0x00000000 CHINT0 Channel 0 Pending Interrupt 0 1 CHINT1 Channel 1 Pending Interrupt 1 1 CHINT2 Channel 2 Pending Interrupt 2 1 CHINT3 Channel 3 Pending Interrupt 3 1 CHINT4 Channel 4 Pending Interrupt 4 1 CHINT5 Channel 5 Pending Interrupt 5 1 CHINT6 Channel 6 Pending Interrupt 6 1 CHINT7 Channel 7 Pending Interrupt 7 1 CHINT8 Channel 8 Pending Interrupt 8 1 CHINT9 Channel 9 Pending Interrupt 9 1 CHINT10 Channel 10 Pending Interrupt 10 1 CHINT11 Channel 11 Pending Interrupt 11 1 BUSYCH Busy Channels 0x18 32 read-only 0x00000000 BUSYCH0 Busy Channel 0 0 1 BUSYCH1 Busy Channel 1 1 1 BUSYCH2 Busy Channel 2 2 1 BUSYCH3 Busy Channel 3 3 1 BUSYCH4 Busy Channel 4 4 1 BUSYCH5 Busy Channel 5 5 1 BUSYCH6 Busy Channel 6 6 1 BUSYCH7 Busy Channel 7 7 1 BUSYCH8 Busy Channel 8 8 1 BUSYCH9 Busy Channel 9 9 1 BUSYCH10 Busy Channel 10 10 1 BUSYCH11 Busy Channel 11 11 1 READYUSR Ready Users 0x1C 32 read-only 0xFFFFFFFF READYUSR0 Ready User for Channel 0 0 1 READYUSR1 Ready User for Channel 1 1 1 READYUSR2 Ready User for Channel 2 2 1 READYUSR3 Ready User for Channel 3 3 1 READYUSR4 Ready User for Channel 4 4 1 READYUSR5 Ready User for Channel 5 5 1 READYUSR6 Ready User for Channel 6 6 1 READYUSR7 Ready User for Channel 7 7 1 READYUSR8 Ready User for Channel 8 8 1 READYUSR9 Ready User for Channel 9 9 1 READYUSR10 Ready User for Channel 10 10 1 READYUSR11 Ready User for Channel 11 11 1 32 0x8 CHANNEL[%s] 0x020 CHANNEL Channel n Control 0x0 32 0x00008000 EVGEN Event Generator Selection 0 7 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 RUNSTDBY Run in standby 14 1 ONDEMAND Generic Clock On Demand 15 1 CHINTENCLR Channel n Interrupt Enable Clear 0x4 8 0x00 OVR Channel Overrun Interrupt Disable 0 1 EVD Channel Event Detected Interrupt Disable 1 1 CHINTENSET Channel n Interrupt Enable Set 0x5 8 0x00 OVR Channel Overrun Interrupt Enable 0 1 EVD Channel Event Detected Interrupt Enable 1 1 CHINTFLAG Channel n Interrupt Flag Status and Clear 0x6 8 0x00 OVR Channel Overrun 0 1 EVD Channel Event Detected 1 1 CHSTATUS Channel n Status 0x7 8 read-only 0x01 RDYUSR Ready User 0 1 BUSYCH Busy Channel 1 1 67 4 USER[%s] User Multiplexer n 0x120 32 0x00000000 CHANNEL Channel Event Selection 0 6 FREQM U22571.1.0 Frequency Meter FREQM FREQM_ 0x40002C00 0 0x14 registers FREQM 28 CTRLA Control A Register 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 CTRLB Control B Register 0x1 8 write-only 0x00 START Start Measurement 0 1 CFGA Config A register 0x2 16 0x0000 REFNUM Number of Reference Clock Cycles 0 8 INTENCLR Interrupt Enable Clear Register 0x8 8 0x00 DONE Measurement Done Interrupt Enable 0 1 INTENSET Interrupt Enable Set Register 0x9 8 0x00 DONE Measurement Done Interrupt Enable 0 1 INTFLAG Interrupt Flag Register 0xA 8 0x00 DONE Measurement Done 0 1 STATUS Status Register 0xB 8 0x00 BUSY FREQM Status 0 1 OVF Sticky Count Value Overflow 1 1 SYNCBUSY Synchronization Busy Register 0xC 32 read-only 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 VALUE Count Value Register 0x10 32 read-only 0x00000000 VALUE Measurement Value 0 24 GCLK U21221.2.0 Generic Clock Generator GCLK GCLK_ 0x40001C00 0 0x1A0 registers CTRLA Control 0x0 8 0x00 SWRST Software Reset 0 1 SYNCBUSY Synchronization Busy 0x4 32 read-only 0x00000000 SWRST Software Reset Synchroniation Busy bit 0 1 GENCTRL Generic Clock Generator Control n Synchronization Busy bits 2 12 GENCTRLSelect GCLK0 Generic clock generator 0 0x0001 GCLK1 Generic clock generator 1 0x0002 GCLK2 Generic clock generator 2 0x0004 GCLK3 Generic clock generator 3 0x0008 GCLK4 Generic clock generator 4 0x0010 GCLK5 Generic clock generator 5 0x0020 GCLK6 Generic clock generator 6 0x0040 GCLK7 Generic clock generator 7 0x0080 GCLK8 Generic clock generator 8 0x0100 GCLK9 Generic clock generator 9 0x0200 GCLK10 Generic clock generator 10 0x0400 GCLK11 Generic clock generator 11 0x0800 12 4 GENCTRL[%s] Generic Clock Generator Control 0x20 32 0x00000000 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OOV Output Off Value 10 1 OE Output Enable 11 1 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0x0 DIV2 Divide input by 2^(divider factor+ 1) 0x1 RUNSTDBY Run in Standby 13 1 DIV Division Factor 16 16 48 4 PCHCTRL[%s] Peripheral Clock Control 0x80 32 0x00000000 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB CHEN Channel Enable 6 1 WRTLOCK Write Lock 7 1 HMATRIX I76382.1.4 HSB Matrix HMATRIXB HMATRIXB_ 0x4100C000 0 0xB0 registers 16 0x8 PRS[%s] 0x080 PRAS Priority A for Slave 0x0 32 0x00000000 PRBS Priority B for Slave 0x4 32 0x00000000 ICM U20101.2.0 Integrity Check Monitor ICM ICM_ 0x42002C00 0 0x58 registers ICM 132 CFG Configuration 0x0 32 0x00000000 WBDIS Write Back Disable 0 1 EOMDIS End of Monitoring Disable 1 1 SLBDIS Secondary List Branching Disable 2 1 BBC Bus Burden Control 4 4 ASCD Automatic Switch To Compare Digest 8 1 DUALBUFF Dual Input Buffer 9 1 UIHASH User Initial Hash Value 12 1 UALGO User SHA Algorithm 13 3 UALGOSelect SHA1 SHA1 Algorithm 0x0 SHA256 SHA256 Algorithm 0x1 SHA224 SHA224 Algorithm 0x4 HAPROT Region Hash Area Protection 16 6 DAPROT Region Descriptor Area Protection 24 6 CTRL Control 0x4 32 write-only ENABLE ICM Enable 0 1 DISABLE ICM Disable Register 1 1 SWRST Software Reset 2 1 REHASH Recompute Internal Hash 4 4 RMDIS Region Monitoring Disable 8 4 RMEN Region Monitoring Enable 12 4 SR Status 0x8 32 read-only 0x00000000 ENABLE ICM Controller Enable Register 0 1 RAWRMDIS RAW Region Monitoring Disabled Status 8 4 RMDIS Region Monitoring Disabled Status 12 4 IER Interrupt Enable 0x10 32 write-only RHC Region Hash Completed Interrupt Enable 0 4 RDM Region Digest Mismatch Interrupt Enable 4 4 RBE Region Bus Error Interrupt Enable 8 4 RWC Region Wrap Condition detected Interrupt Enable 12 4 REC Region End bit Condition Detected Interrupt Enable 16 4 RSU Region Status Updated Interrupt Disable 20 4 URAD Undefined Register Access Detection Interrupt Enable 24 1 IDR Interrupt Disable 0x14 32 write-only 0x00000000 RHC Region Hash Completed Interrupt Disable 0 4 RDM Region Digest Mismatch Interrupt Disable 4 4 RBE Region Bus Error Interrupt Disable 8 4 RWC Region Wrap Condition Detected Interrupt Disable 12 4 REC Region End bit Condition detected Interrupt Disable 16 4 RSU Region Status Updated Interrupt Disable 20 4 URAD Undefined Register Access Detection Interrupt Disable 24 1 IMR Interrupt Mask 0x18 32 read-only 0x00000000 RHC Region Hash Completed Interrupt Mask 0 4 RDM Region Digest Mismatch Interrupt Mask 4 4 RBE Region Bus Error Interrupt Mask 8 4 RWC Region Wrap Condition Detected Interrupt Mask 12 4 REC Region End bit Condition Detected Interrupt Mask 16 4 RSU Region Status Updated Interrupt Mask 20 4 URAD Undefined Register Access Detection Interrupt Mask 24 1 ISR Interrupt Status 0x1C 32 read-only 0x00000000 RHC Region Hash Completed 0 4 RDM Region Digest Mismatch 4 4 RBE Region Bus Error 8 4 RWC Region Wrap Condition Detected 12 4 REC Region End bit Condition Detected 16 4 RSU Region Status Updated Detected 20 4 URAD Undefined Register Access Detection Status 24 1 UASR Undefined Access Status 0x20 32 read-only 0x00000000 URAT Undefined Register Access Trace 0 3 URATSelect UNSPEC_STRUCT_MEMBER Unspecified structure member set to one detected when the descriptor is loaded 0x0 CFG_MODIFIED CFG modified during active monitoring 0x1 DSCR_MODIFIED DSCR modified during active monitoring 0x2 HASH_MODIFIED HASH modified during active monitoring 0x3 READ_ACCESS Write-only register read access 0x4 DSCR Region Descriptor Area Start Address 0x30 32 0x00000000 DASA Descriptor Area Start Address 6 26 HASH Region Hash Area Start Address 0x34 32 0x00000000 HASA Hash Area Start Address 7 25 8 4 UIHVAL[%s] User Initial Hash Value n 0x38 32 write-only 0x00000000 VAL Initial Hash Value 0 32 I2S U22242.0.0 Inter-IC Sound Interface I2S I2S_ 0x43002800 0 0x38 registers I2S 128 CTRLA Control A 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 CKEN0 Clock Unit 0 Enable 2 1 CKEN1 Clock Unit 1 Enable 3 1 TXEN Tx Serializer Enable 4 1 RXEN Rx Serializer Enable 5 1 2 4 CLKCTRL[%s] Clock Unit n Control 0x4 32 0x00000000 SLOTSIZE Slot Size 0 2 SLOTSIZESelect 8 8-bit Slot for Clock Unit n 0x0 16 16-bit Slot for Clock Unit n 0x1 24 24-bit Slot for Clock Unit n 0x2 32 32-bit Slot for Clock Unit n 0x3 NBSLOTS Number of Slots in Frame 2 3 FSWIDTH Frame Sync Width 5 2 FSWIDTHSelect SLOT Frame Sync Pulse is 1 Slot wide (default for I2S protocol) 0x0 HALF Frame Sync Pulse is half a Frame wide 0x1 BIT Frame Sync Pulse is 1 Bit wide 0x2 BURST Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested 0x3 BITDELAY Data Delay from Frame Sync 7 1 BITDELAYSelect LJ Left Justified (0 Bit Delay) 0x0 I2S I2S (1 Bit Delay) 0x1 FSSEL Frame Sync Select 8 1 FSSELSelect SCKDIV Divided Serial Clock n is used as Frame Sync n source 0x0 FSPIN FSn input pin is used as Frame Sync n source 0x1 FSINV Frame Sync Invert 9 1 FSOUTINV Frame Sync Output Invert 10 1 SCKSEL Serial Clock Select 11 1 SCKSELSelect MCKDIV Divided Master Clock n is used as Serial Clock n source 0x0 SCKPIN SCKn input pin is used as Serial Clock n source 0x1 SCKOUTINV Serial Clock Output Invert 12 1 MCKSEL Master Clock Select 13 1 MCKSELSelect GCLK GCLK_I2S_n is used as Master Clock n source 0x0 MCKPIN MCKn input pin is used as Master Clock n source 0x1 MCKEN Master Clock Enable 14 1 MCKOUTINV Master Clock Output Invert 15 1 MCKDIV Master Clock Division Factor 16 6 MCKOUTDIV Master Clock Output Division Factor 24 6 INTENCLR Interrupt Enable Clear 0xC 16 0x0000 RXRDY0 Receive Ready 0 Interrupt Enable 0 1 RXRDY1 Receive Ready 1 Interrupt Enable 1 1 RXOR0 Receive Overrun 0 Interrupt Enable 4 1 RXOR1 Receive Overrun 1 Interrupt Enable 5 1 TXRDY0 Transmit Ready 0 Interrupt Enable 8 1 TXRDY1 Transmit Ready 1 Interrupt Enable 9 1 TXUR0 Transmit Underrun 0 Interrupt Enable 12 1 TXUR1 Transmit Underrun 1 Interrupt Enable 13 1 INTENSET Interrupt Enable Set 0x10 16 0x0000 RXRDY0 Receive Ready 0 Interrupt Enable 0 1 RXRDY1 Receive Ready 1 Interrupt Enable 1 1 RXOR0 Receive Overrun 0 Interrupt Enable 4 1 RXOR1 Receive Overrun 1 Interrupt Enable 5 1 TXRDY0 Transmit Ready 0 Interrupt Enable 8 1 TXRDY1 Transmit Ready 1 Interrupt Enable 9 1 TXUR0 Transmit Underrun 0 Interrupt Enable 12 1 TXUR1 Transmit Underrun 1 Interrupt Enable 13 1 INTFLAG Interrupt Flag Status and Clear 0x14 16 0x0000 RXRDY0 Receive Ready 0 0 1 RXRDY1 Receive Ready 1 1 1 RXOR0 Receive Overrun 0 4 1 RXOR1 Receive Overrun 1 5 1 TXRDY0 Transmit Ready 0 8 1 TXRDY1 Transmit Ready 1 9 1 TXUR0 Transmit Underrun 0 12 1 TXUR1 Transmit Underrun 1 13 1 SYNCBUSY Synchronization Status 0x18 16 read-only 0x0000 SWRST Software Reset Synchronization Status 0 1 ENABLE Enable Synchronization Status 1 1 CKEN0 Clock Unit 0 Enable Synchronization Status 2 1 CKEN1 Clock Unit 1 Enable Synchronization Status 3 1 TXEN Tx Serializer Enable Synchronization Status 4 1 RXEN Rx Serializer Enable Synchronization Status 5 1 TXDATA Tx Data Synchronization Status 8 1 RXDATA Rx Data Synchronization Status 9 1 TXCTRL Tx Serializer Control 0x20 32 0x00000000 SERMODE Serializer Mode 0 2 SERMODESelect RX Receive 0x0 TX Transmit 0x1 PDM2 Receive one PDM data on each serial clock edge 0x2 TXDEFAULT Line Default Line when Slot Disabled 2 2 TXDEFAULTSelect ZERO Output Default Value is 0 0x0 ONE Output Default Value is 1 0x1 HIZ Output Default Value is high impedance 0x3 TXSAME Transmit Data when Underrun 4 1 TXSAMESelect ZERO Zero data transmitted in case of underrun 0x0 SAME Last data transmitted in case of underrun 0x1 CLKSEL Clock Unit Selection 5 1 CLKSELSelect CLK0 Use Clock Unit 0 0x0 CLK1 Use Clock Unit 1 0x1 SLOTADJ Data Slot Formatting Adjust 7 1 SLOTADJSelect RIGHT Data is right adjusted in slot 0x0 LEFT Data is left adjusted in slot 0x1 DATASIZE Data Word Size 8 3 DATASIZESelect 32 32 bits 0x0 24 24 bits 0x1 20 20 bits 0x2 18 18 bits 0x3 16 16 bits 0x4 16C 16 bits compact stereo 0x5 8 8 bits 0x6 8C 8 bits compact stereo 0x7 WORDADJ Data Word Formatting Adjust 12 1 WORDADJSelect RIGHT Data is right adjusted in word 0x0 LEFT Data is left adjusted in word 0x1 EXTEND Data Formatting Bit Extension 13 2 EXTENDSelect ZERO Extend with zeroes 0x0 ONE Extend with ones 0x1 MSBIT Extend with Most Significant Bit 0x2 LSBIT Extend with Least Significant Bit 0x3 BITREV Data Formatting Bit Reverse 15 1 BITREVSelect MSBIT Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) 0x0 LSBIT Transfer Data Least Significant Bit (LSB) first 0x1 SLOTDIS0 Slot 0 Disabled for this Serializer 16 1 SLOTDIS1 Slot 1 Disabled for this Serializer 17 1 SLOTDIS2 Slot 2 Disabled for this Serializer 18 1 SLOTDIS3 Slot 3 Disabled for this Serializer 19 1 SLOTDIS4 Slot 4 Disabled for this Serializer 20 1 SLOTDIS5 Slot 5 Disabled for this Serializer 21 1 SLOTDIS6 Slot 6 Disabled for this Serializer 22 1 SLOTDIS7 Slot 7 Disabled for this Serializer 23 1 MONO Mono Mode 24 1 MONOSelect STEREO Normal mode 0x0 MONO Left channel data is duplicated to right channel 0x1 DMA Single or Multiple DMA Channels 25 1 DMASelect SINGLE Single DMA channel 0x0 MULTIPLE One DMA channel per data channel 0x1 RXCTRL Rx Serializer Control 0x24 32 0x00000000 SERMODE Serializer Mode 0 2 SERMODESelect RX Receive 0x0 PDM2 Receive one PDM data on each serial clock edge 0x2 CLKSEL Clock Unit Selection 5 1 CLKSELSelect CLK0 Use Clock Unit 0 0x0 CLK1 Use Clock Unit 1 0x1 SLOTADJ Data Slot Formatting Adjust 7 1 SLOTADJSelect RIGHT Data is right adjusted in slot 0x0 LEFT Data is left adjusted in slot 0x1 DATASIZE Data Word Size 8 3 DATASIZESelect 32 32 bits 0x0 24 24 bits 0x1 20 20 bits 0x2 18 18 bits 0x3 16 16 bits 0x4 16C 16 bits compact stereo 0x5 8 8 bits 0x6 8C 8 bits compact stereo 0x7 WORDADJ Data Word Formatting Adjust 12 1 WORDADJSelect RIGHT Data is right adjusted in word 0x0 LEFT Data is left adjusted in word 0x1 EXTEND Data Formatting Bit Extension 13 2 EXTENDSelect ZERO Extend with zeroes 0x0 ONE Extend with ones 0x1 MSBIT Extend with Most Significant Bit 0x2 LSBIT Extend with Least Significant Bit 0x3 BITREV Data Formatting Bit Reverse 15 1 BITREVSelect MSBIT Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) 0x0 LSBIT Transfer Data Least Significant Bit (LSB) first 0x1 SLOTDIS0 Slot 0 Disabled for this Serializer 16 1 SLOTDIS1 Slot 1 Disabled for this Serializer 17 1 SLOTDIS2 Slot 2 Disabled for this Serializer 18 1 SLOTDIS3 Slot 3 Disabled for this Serializer 19 1 SLOTDIS4 Slot 4 Disabled for this Serializer 20 1 SLOTDIS5 Slot 5 Disabled for this Serializer 21 1 SLOTDIS6 Slot 6 Disabled for this Serializer 22 1 SLOTDIS7 Slot 7 Disabled for this Serializer 23 1 MONO Mono Mode 24 1 MONOSelect STEREO Normal mode 0x0 MONO Left channel data is duplicated to right channel 0x1 DMA Single or Multiple DMA Channels 25 1 DMASelect SINGLE Single DMA channel 0x0 MULTIPLE One DMA channel per data channel 0x1 RXLOOP Loop-back Test Mode 26 1 TXDATA Tx Data 0x30 32 write-only 0x00000000 DATA Sample Data 0 32 RXDATA Rx Data 0x34 32 read-only 0x00000000 DATA Sample Data 0 32 MCLK U24081.0.0 Main Clock MCLK MCLK_ 0x40000800 0 0x24 registers MCLK 1 INTENCLR Interrupt Enable Clear 0x1 8 0x00 CKRDY Clock Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x2 8 0x00 CKRDY Clock Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x3 8 0x01 CKRDY Clock Ready 0 1 HSDIV HS Clock Division 0x4 8 read-only 0x01 DIV CPU Clock Division Factor 0 8 DIVSelect DIV1 Divide by 1 0x01 CPUDIV CPU Clock Division 0x5 8 0x01 DIV Low-Power Clock Division Factor 0 8 DIVSelect DIV1 Divide by 1 0x01 DIV2 Divide by 2 0x02 DIV4 Divide by 4 0x04 DIV8 Divide by 8 0x08 DIV16 Divide by 16 0x10 DIV32 Divide by 32 0x20 DIV64 Divide by 64 0x40 DIV128 Divide by 128 0x80 AHBMASK AHB Mask 0x10 32 0x00FFFFFF HPB0_ HPB0 AHB Clock Mask 0 1 HPB1_ HPB1 AHB Clock Mask 1 1 HPB2_ HPB2 AHB Clock Mask 2 1 HPB3_ HPB3 AHB Clock Mask 3 1 DSU_ DSU AHB Clock Mask 4 1 HMATRIX_ HMATRIX AHB Clock Mask 5 1 NVMCTRL_ NVMCTRL AHB Clock Mask 6 1 HSRAM_ HSRAM AHB Clock Mask 7 1 CMCC_ CMCC AHB Clock Mask 8 1 DMAC_ DMAC AHB Clock Mask 9 1 USB_ USB AHB Clock Mask 10 1 BKUPRAM_ BKUPRAM AHB Clock Mask 11 1 PAC_ PAC AHB Clock Mask 12 1 QSPI_ QSPI AHB Clock Mask 13 1 SDHC0_ SDHC0 AHB Clock Mask 15 1 ICM_ ICM AHB Clock Mask 19 1 PUKCC_ PUKCC AHB Clock Mask 20 1 QSPI_2X_ QSPI_2X AHB Clock Mask 21 1 NVMCTRL_SMEEPROM_ NVMCTRL_SMEEPROM AHB Clock Mask 22 1 NVMCTRL_CACHE_ NVMCTRL_CACHE AHB Clock Mask 23 1 APBAMASK APBA Mask 0x14 32 0x000007FF PAC_ PAC APB Clock Enable 0 1 PM_ PM APB Clock Enable 1 1 MCLK_ MCLK APB Clock Enable 2 1 RSTC_ RSTC APB Clock Enable 3 1 OSCCTRL_ OSCCTRL APB Clock Enable 4 1 OSC32KCTRL_ OSC32KCTRL APB Clock Enable 5 1 SUPC_ SUPC APB Clock Enable 6 1 GCLK_ GCLK APB Clock Enable 7 1 WDT_ WDT APB Clock Enable 8 1 RTC_ RTC APB Clock Enable 9 1 EIC_ EIC APB Clock Enable 10 1 FREQM_ FREQM APB Clock Enable 11 1 SERCOM0_ SERCOM0 APB Clock Enable 12 1 SERCOM1_ SERCOM1 APB Clock Enable 13 1 TC0_ TC0 APB Clock Enable 14 1 TC1_ TC1 APB Clock Enable 15 1 APBBMASK APBB Mask 0x18 32 0x00018056 USB_ USB APB Clock Enable 0 1 DSU_ DSU APB Clock Enable 1 1 NVMCTRL_ NVMCTRL APB Clock Enable 2 1 PORT_ PORT APB Clock Enable 4 1 HMATRIX_ HMATRIX APB Clock Enable 6 1 EVSYS_ EVSYS APB Clock Enable 7 1 SERCOM2_ SERCOM2 APB Clock Enable 9 1 SERCOM3_ SERCOM3 APB Clock Enable 10 1 TCC0_ TCC0 APB Clock Enable 11 1 TCC1_ TCC1 APB Clock Enable 12 1 TC2_ TC2 APB Clock Enable 13 1 TC3_ TC3 APB Clock Enable 14 1 RAMECC_ RAMECC APB Clock Enable 16 1 APBCMASK APBC Mask 0x1C 32 0x00002000 TCC2_ TCC2 APB Clock Enable 3 1 TCC3_ TCC3 APB Clock Enable 4 1 TC4_ TC4 APB Clock Enable 5 1 TC5_ TC5 APB Clock Enable 6 1 PDEC_ PDEC APB Clock Enable 7 1 AC_ AC APB Clock Enable 8 1 AES_ AES APB Clock Enable 9 1 TRNG_ TRNG APB Clock Enable 10 1 ICM_ ICM APB Clock Enable 11 1 QSPI_ QSPI APB Clock Enable 13 1 CCL_ CCL APB Clock Enable 14 1 APBDMASK APBD Mask 0x20 32 0x00000000 SERCOM4_ SERCOM4 APB Clock Enable 0 1 SERCOM5_ SERCOM5 APB Clock Enable 1 1 TCC4_ TCC4 APB Clock Enable 4 1 ADC0_ ADC0 APB Clock Enable 7 1 ADC1_ ADC1 APB Clock Enable 8 1 DAC_ DAC APB Clock Enable 9 1 I2S_ I2S APB Clock Enable 10 1 PCC_ PCC APB Clock Enable 11 1 NVMCTRL U24091.0.0 Non-Volatile Memory Controller NVMCTRL NVMCTRL_ 0x41004000 0 0x30 registers NVMCTRL_0 29 NVMCTRL_1 30 CTRLA Control A 0x0 16 0x0004 AUTOWS Auto Wait State Enable 2 1 SUSPEN Suspend Enable 3 1 WMODE Write Mode 4 2 WMODESelect MAN Manual Write 0 ADW Automatic Double Word Write 1 AQW Automatic Quad Word 2 AP Automatic Page Write 3 PRM Power Reduction Mode during Sleep 6 2 PRMSelect SEMIAUTO NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. 0 FULLAUTO NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode. 1 MANUAL NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. 3 RWS NVM Read Wait States 8 4 AHBNS0 Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated 12 1 AHBNS1 Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated 13 1 CACHEDIS0 AHB0 Cache Disable 14 1 CACHEDIS1 AHB1 Cache Disable 15 1 CTRLB Control B 0x4 16 write-only 0x0000 CMD Command 0 7 CMDSelect EP Erase Page - Only supported in the USER and AUX pages. 0x0 EB Erase Block - Erases the block addressed by the ADDR register, not supported in the user page 0x1 WP Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page 0x3 WQW Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register. 0x4 SWRST Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers 0x10 LR Lock Region - Locks the region containing the address location in the ADDR register. 0x11 UR Unlock Region - Unlocks the region containing the address location in the ADDR register. 0x12 SPRM Sets the power reduction mode. 0x13 CPRM Clears the power reduction mode. 0x14 PBC Page Buffer Clear - Clears the page buffer. 0x15 SSB Set Security Bit 0x16 BKSWRST Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK 0x17 CELCK Chip Erase Lock - DSU.CE command is not available 0x18 CEULCK Chip Erase Unlock - DSU.CE command is available 0x19 SBPDIS Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence 0x1A CBPDIS Clears STATUS.BPDIS, Boot loader protection is not discarded 0x1B ASEES0 Activate SmartEEPROM Sector 0, deactivate Sector 1 0x30 ASEES1 Activate SmartEEPROM Sector 1, deactivate Sector 0 0x31 SEERALOC Starts SmartEEPROM sector reallocation algorithm 0x32 SEEFLUSH Flush SMEE data when in buffered mode 0x33 LSEE Lock access to SmartEEPROM data from any mean 0x34 USEE Unlock access to SmartEEPROM data 0x35 LSEER Lock access to the SmartEEPROM Register Address Space (above 64KB) 0x36 USEER Unlock access to the SmartEEPROM Register Address Space (above 64KB) 0x37 CMDEX Command Execution 8 8 CMDEXSelect KEY Execution Key 0xA5 PARAM NVM Parameter 0x8 32 read-only 0x00060000 NVMP NVM Pages 0 16 PSZ Page Size 16 3 PSZSelect 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 SEE SmartEEPROM Supported 31 1 SEESelect A 163840 bytes 0xA 9 147456 bytes 0x9 8 131072 bytes 0x8 7 114688 bytes 0x7 6 98304 bytes 0x6 5 81920 bytes 0x5 4 65536 bytes 0x4 3 49152 bytes 0x3 2 32768 bytes 0x2 1 16384 bytes 0x1 0 0 bytes 0x0 INTENCLR Interrupt Enable Clear 0xC 16 0x0000 DONE Command Done Interrupt Clear 0 1 ADDRE Address Error 1 1 PROGE Programming Error Interrupt Clear 2 1 LOCKE Lock Error Interrupt Clear 3 1 ECCSE ECC Single Error Interrupt Clear 4 1 ECCDE ECC Dual Error Interrupt Clear 5 1 NVME NVM Error Interrupt Clear 6 1 SUSP Suspended Write Or Erase Interrupt Clear 7 1 SEESFULL Active SEES Full Interrupt Clear 8 1 SEESOVF Active SEES Overflow Interrupt Clear 9 1 SEEWRC SEE Write Completed Interrupt Clear 10 1 INTENSET Interrupt Enable Set 0xE 16 0x0000 DONE Command Done Interrupt Enable 0 1 ADDRE Address Error Interrupt Enable 1 1 PROGE Programming Error Interrupt Enable 2 1 LOCKE Lock Error Interrupt Enable 3 1 ECCSE ECC Single Error Interrupt Enable 4 1 ECCDE ECC Dual Error Interrupt Enable 5 1 NVME NVM Error Interrupt Enable 6 1 SUSP Suspended Write Or Erase Interrupt Enable 7 1 SEESFULL Active SEES Full Interrupt Enable 8 1 SEESOVF Active SEES Overflow Interrupt Enable 9 1 SEEWRC SEE Write Completed Interrupt Enable 10 1 INTFLAG Interrupt Flag Status and Clear 0x10 16 0x0000 DONE Command Done 0 1 ADDRE Address Error 1 1 PROGE Programming Error 2 1 LOCKE Lock Error 3 1 ECCSE ECC Single Error 4 1 ECCDE ECC Dual Error 5 1 NVME NVM Error 6 1 SUSP Suspended Write Or Erase Operation 7 1 SEESFULL Active SEES Full 8 1 SEESOVF Active SEES Overflow 9 1 SEEWRC SEE Write Completed 10 1 STATUS Status 0x12 16 read-only 0x0000 READY Ready to accept a command 0 1 PRM Power Reduction Mode 1 1 LOAD NVM Page Buffer Active Loading 2 1 SUSP NVM Write Or Erase Operation Is Suspended 3 1 AFIRST BANKA First 4 1 BPDIS Boot Loader Protection Disable 5 1 BOOTPROT Boot Loader Protection Size 8 4 BOOTPROTSelect 0 0 kbytes 0xF 8 8 kbytes 0xE 16 16 kbytes 0xD 24 24 kbytes 0xC 32 32 kbytes 0xB 40 40 kbytes 0xA 48 48 kbytes 0x9 56 56 kbytes 0x8 64 64 kbytes 0x7 72 72 kbytes 0x6 80 80 kbytes 0x5 88 88 kbytes 0x4 96 96 kbytes 0x3 104 104 kbytes 0x2 112 112 kbytes 0x1 120 120 kbytes 0x0 ADDR Address 0x14 32 0x00000000 ADDR NVM Address 0 24 RUNLOCK Lock Section 0x18 32 read-only 0x00000000 RUNLOCK Region Un-Lock Bits 0 32 2 4 PBLDATA[%s] Page Buffer Load Data x 0x1C 32 read-only 0xFFFFFFFF DATA Page Buffer Data 0 32 ECCERR ECC Error Status Register 0x24 32 read-only 0x00000000 ADDR Error Address 0 24 TYPEL Low Double-Word Error Type 28 2 TYPELSelect None No Error Detected Since Last Read 0 Single At Least One Single Error Detected Since last Read 1 Dual At Least One Dual Error Detected Since Last Read 2 TYPEH High Double-Word Error Type 30 2 TYPEHSelect None No Error Detected Since Last Read 0 Single At Least One Single Error Detected Since last Read 1 Dual At Least One Dual Error Detected Since Last Read 2 DBGCTRL Debug Control 0x28 8 0x00 ECCDIS Debugger ECC Read Disable 0 1 ECCELOG Debugger ECC Error Tracking Mode 1 1 SEECFG SmartEEPROM Configuration Register 0x2A 8 0x00 WMODE Write Mode 0 1 WMODESelect UNBUFFERED A NVM write command is issued after each write in the pagebuffer 0 BUFFERED A NVM write command is issued when a write to a new page is requested 1 APRDIS Automatic Page Reallocation Disable 1 1 SEESTAT SmartEEPROM Status Register 0x2C 32 read-only 0x00000000 ASEES Active SmartEEPROM Sector 0 1 LOAD Page Buffer Loaded 1 1 BUSY Busy 2 1 LOCK SmartEEPROM Write Access Is Locked 3 1 RLOCK SmartEEPROM Write Access To Register Address Space Is Locked 4 1 SBLK Blocks Number In a Sector 8 4 PSZ SmartEEPROM Page Size 16 3 OSCCTRL U24011.0.0 Oscillators Control OSCCTRL OSCCTRL_ 0x40001000 0 0x58 registers OSCCTRL_XOSC0 2 OSCCTRL_XOSC1 3 OSCCTRL_DFLL 4 OSCCTRL_DPLL0 5 OSCCTRL_DPLL1 6 EVCTRL Event Control 0x0 8 0x00 CFDEO0 Clock 0 Failure Detector Event Output Enable 0 1 CFDEO1 Clock 1 Failure Detector Event Output Enable 1 1 INTENCLR Interrupt Enable Clear 0x4 32 0x00000000 XOSCRDY0 XOSC 0 Ready Interrupt Enable 0 1 XOSCRDY1 XOSC 1 Ready Interrupt Enable 1 1 XOSCFAIL0 XOSC 0 Clock Failure Detector Interrupt Enable 2 1 XOSCFAIL1 XOSC 1 Clock Failure Detector Interrupt Enable 3 1 DFLLRDY DFLL Ready Interrupt Enable 8 1 DFLLOOB DFLL Out Of Bounds Interrupt Enable 9 1 DFLLLCKF DFLL Lock Fine Interrupt Enable 10 1 DFLLLCKC DFLL Lock Coarse Interrupt Enable 11 1 DFLLRCS DFLL Reference Clock Stopped Interrupt Enable 12 1 DPLL0LCKR DPLL0 Lock Rise Interrupt Enable 16 1 DPLL0LCKF DPLL0 Lock Fall Interrupt Enable 17 1 DPLL0LTO DPLL0 Lock Timeout Interrupt Enable 18 1 DPLL0LDRTO DPLL0 Loop Divider Ratio Update Complete Interrupt Enable 19 1 DPLL1LCKR DPLL1 Lock Rise Interrupt Enable 24 1 DPLL1LCKF DPLL1 Lock Fall Interrupt Enable 25 1 DPLL1LTO DPLL1 Lock Timeout Interrupt Enable 26 1 DPLL1LDRTO DPLL1 Loop Divider Ratio Update Complete Interrupt Enable 27 1 INTENSET Interrupt Enable Set 0x8 32 0x00000000 XOSCRDY0 XOSC 0 Ready Interrupt Enable 0 1 XOSCRDY1 XOSC 1 Ready Interrupt Enable 1 1 XOSCFAIL0 XOSC 0 Clock Failure Detector Interrupt Enable 2 1 XOSCFAIL1 XOSC 1 Clock Failure Detector Interrupt Enable 3 1 DFLLRDY DFLL Ready Interrupt Enable 8 1 DFLLOOB DFLL Out Of Bounds Interrupt Enable 9 1 DFLLLCKF DFLL Lock Fine Interrupt Enable 10 1 DFLLLCKC DFLL Lock Coarse Interrupt Enable 11 1 DFLLRCS DFLL Reference Clock Stopped Interrupt Enable 12 1 DPLL0LCKR DPLL0 Lock Rise Interrupt Enable 16 1 DPLL0LCKF DPLL0 Lock Fall Interrupt Enable 17 1 DPLL0LTO DPLL0 Lock Timeout Interrupt Enable 18 1 DPLL0LDRTO DPLL0 Loop Divider Ratio Update Complete Interrupt Enable 19 1 DPLL1LCKR DPLL1 Lock Rise Interrupt Enable 24 1 DPLL1LCKF DPLL1 Lock Fall Interrupt Enable 25 1 DPLL1LTO DPLL1 Lock Timeout Interrupt Enable 26 1 DPLL1LDRTO DPLL1 Loop Divider Ratio Update Complete Interrupt Enable 27 1 INTFLAG Interrupt Flag Status and Clear 0xC 32 0x00000000 XOSCRDY0 XOSC 0 Ready 0 1 XOSCRDY1 XOSC 1 Ready 1 1 XOSCFAIL0 XOSC 0 Clock Failure Detector 2 1 XOSCFAIL1 XOSC 1 Clock Failure Detector 3 1 DFLLRDY DFLL Ready 8 1 DFLLOOB DFLL Out Of Bounds 9 1 DFLLLCKF DFLL Lock Fine 10 1 DFLLLCKC DFLL Lock Coarse 11 1 DFLLRCS DFLL Reference Clock Stopped 12 1 DPLL0LCKR DPLL0 Lock Rise 16 1 DPLL0LCKF DPLL0 Lock Fall 17 1 DPLL0LTO DPLL0 Lock Timeout 18 1 DPLL0LDRTO DPLL0 Loop Divider Ratio Update Complete 19 1 DPLL1LCKR DPLL1 Lock Rise 24 1 DPLL1LCKF DPLL1 Lock Fall 25 1 DPLL1LTO DPLL1 Lock Timeout 26 1 DPLL1LDRTO DPLL1 Loop Divider Ratio Update Complete 27 1 STATUS Status 0x10 32 read-only 0x00000000 XOSCRDY0 XOSC 0 Ready 0 1 XOSCRDY1 XOSC 1 Ready 1 1 XOSCFAIL0 XOSC 0 Clock Failure Detector 2 1 XOSCFAIL1 XOSC 1 Clock Failure Detector 3 1 XOSCCKSW0 XOSC 0 Clock Switch 4 1 XOSCCKSW1 XOSC 1 Clock Switch 5 1 DFLLRDY DFLL Ready 8 1 DFLLOOB DFLL Out Of Bounds 9 1 DFLLLCKF DFLL Lock Fine 10 1 DFLLLCKC DFLL Lock Coarse 11 1 DFLLRCS DFLL Reference Clock Stopped 12 1 DPLL0LCKR DPLL0 Lock Rise 16 1 DPLL0LCKF DPLL0 Lock Fall 17 1 DPLL0TO DPLL0 Timeout 18 1 DPLL0LDRTO DPLL0 Loop Divider Ratio Update Complete 19 1 DPLL1LCKR DPLL1 Lock Rise 24 1 DPLL1LCKF DPLL1 Lock Fall 25 1 DPLL1TO DPLL1 Timeout 26 1 DPLL1LDRTO DPLL1 Loop Divider Ratio Update Complete 27 1 2 4 XOSCCTRL[%s] External Multipurpose Crystal Oscillator Control 0x14 32 0x00000080 ENABLE Oscillator Enable 1 1 XTALEN Crystal Oscillator Enable 2 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 LOWBUFGAIN Low Buffer Gain Enable 8 1 IPTAT Oscillator Current Reference 9 2 IMULT Oscillator Current Multiplier 11 4 ENALC Automatic Loop Control Enable 15 1 CFDEN Clock Failure Detector Enable 16 1 SWBEN Xosc Clock Switch Enable 17 1 STARTUP Start-Up Time 20 4 STARTUPSelect CYCLE1 31 us 0 CYCLE2 61 us 1 CYCLE4 122 us 2 CYCLE8 244 us 3 CYCLE16 488 us 4 CYCLE32 977 us 5 CYCLE64 1953 us 6 CYCLE128 3906 us 7 CYCLE256 7813 us 8 CYCLE512 15625 us 9 CYCLE1024 31250 us 10 CYCLE2048 62500 us 11 CYCLE4096 125000 us 12 CYCLE8192 250000 us 13 CYCLE16384 500000 us 14 CYCLE32768 1000000 us 15 CFDPRESC Clock Failure Detector Prescaler 24 4 CFDPRESCSelect DIV1 48 MHz 0 DIV2 24 MHz 1 DIV4 12 MHz 2 DIV8 6 MHz 3 DIV16 3 MHz 4 DIV32 1.5 MHz 5 DIV64 0.75 MHz 6 DIV128 0.3125 MHz 7 DFLLCTRLA DFLL48M Control A 0x1C 8 0x82 ENABLE DFLL Enable 1 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 DFLLCTRLB DFLL48M Control B 0x20 8 0x00 MODE Operating Mode Selection 0 1 STABLE Stable DFLL Frequency 1 1 LLAW Lose Lock After Wake 2 1 USBCRM USB Clock Recovery Mode 3 1 CCDIS Chill Cycle Disable 4 1 QLDIS Quick Lock Disable 5 1 BPLCKC Bypass Coarse Lock 6 1 WAITLOCK Wait Lock 7 1 DFLLVAL DFLL48M Value 0x24 32 0x00000000 FINE Fine Value 0 8 COARSE Coarse Value 10 6 DIFF Multiplication Ratio Difference 16 16 DFLLMUL DFLL48M Multiplier 0x28 32 0x00000000 MUL DFLL Multiply Factor 0 16 FSTEP Fine Maximum Step 16 8 CSTEP Coarse Maximum Step 26 6 DFLLSYNC DFLL48M Synchronization 0x2C 8 0x00 ENABLE ENABLE Synchronization Busy 1 1 DFLLCTRLB DFLLCTRLB Synchronization Busy 2 1 DFLLVAL DFLLVAL Synchronization Busy 3 1 DFLLMUL DFLLMUL Synchronization Busy 4 1 2 0x14 DPLL[%s] 0x30 DPLLCTRLA DPLL Control A 0x0 8 0x80 ENABLE DPLL Enable 1 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 DPLLRATIO DPLL Ratio Control 0x4 32 0x00000000 LDR Loop Divider Ratio 0 13 LDRFRAC Loop Divider Ratio Fractional Part 16 5 DPLLCTRLB DPLL Control B 0x8 32 0x00000020 FILTER Proportional Integral Filter Selection 0 4 FILTERSelect FILTER1 Bandwidth = 92.7Khz and Damping Factor = 0.76 0 FILTER2 Bandwidth = 131Khz and Damping Factor = 1.08 1 FILTER3 Bandwidth = 46.4Khz and Damping Factor = 0.38 2 FILTER4 Bandwidth = 65.6Khz and Damping Factor = 0.54 3 FILTER5 Bandwidth = 131Khz and Damping Factor = 0.56 4 FILTER6 Bandwidth = 185Khz and Damping Factor = 0.79 5 FILTER7 Bandwidth = 65.6Khz and Damping Factor = 0.28 6 FILTER8 Bandwidth = 92.7Khz and Damping Factor = 0.39 7 FILTER9 Bandwidth = 46.4Khz and Damping Factor = 1.49 8 FILTER10 Bandwidth = 65.6Khz and Damping Factor = 2.11 9 FILTER11 Bandwidth = 23.2Khz and Damping Factor = 0.75 10 FILTER12 Bandwidth = 32.8Khz and Damping Factor = 1.06 11 FILTER13 Bandwidth = 65.6Khz and Damping Factor = 1.07 12 FILTER14 Bandwidth = 92.7Khz and Damping Factor = 1.51 13 FILTER15 Bandwidth = 32.8Khz and Damping Factor = 0.53 14 FILTER16 Bandwidth = 46.4Khz and Damping Factor = 0.75 15 WUF Wake Up Fast 4 1 REFCLK Reference Clock Selection 5 3 REFCLKSelect GCLK Dedicated GCLK clock reference 0x0 XOSC32 XOSC32K clock reference 0x1 XOSC0 XOSC0 clock reference 0x2 XOSC1 XOSC1 clock reference 0x3 LTIME Lock Time 8 3 LTIMESelect DEFAULT No time-out. Automatic lock 0x0 800US Time-out if no lock within 800us 0x4 900US Time-out if no lock within 900us 0x5 1MS Time-out if no lock within 1ms 0x6 1P1MS Time-out if no lock within 1.1ms 0x7 LBYPASS Lock Bypass 11 1 DCOFILTER Sigma-Delta DCO Filter Selection 12 3 DCOFILTERSelect FILTER1 Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21 0 FILTER2 Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6 1 FILTER3 Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1 2 FILTER4 Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8 3 FILTER5 Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64 4 FILTER6 Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55 5 FILTER7 Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45 6 FILTER8 Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4 7 DCOEN DCO Filter Enable 15 1 DIV Clock Divider 16 11 DPLLSYNCBUSY DPLL Synchronization Busy 0xC 32 read-only 0x00000000 ENABLE DPLL Enable Synchronization Status 1 1 DPLLRATIO DPLL Loop Divider Ratio Synchronization Status 2 1 DPLLSTATUS DPLL Status 0x10 32 read-only 0x00000000 LOCK DPLL Lock Status 0 1 CLKRDY DPLL Clock Ready 1 1 OSC32KCTRL U24001.0.0 32kHz Oscillators Control OSC32KCTRL OSC32KCTRL_ 0x40001400 0 0x20 registers OSC32KCTRL 7 INTENCLR Interrupt Enable Clear 0x0 32 0x00000000 XOSC32KRDY XOSC32K Ready Interrupt Enable 0 1 XOSC32KFAIL XOSC32K Clock Failure Detector Interrupt Enable 2 1 INTENSET Interrupt Enable Set 0x4 32 0x00000000 XOSC32KRDY XOSC32K Ready Interrupt Enable 0 1 XOSC32KFAIL XOSC32K Clock Failure Detector Interrupt Enable 2 1 INTFLAG Interrupt Flag Status and Clear 0x8 32 0x00000000 XOSC32KRDY XOSC32K Ready 0 1 XOSC32KFAIL XOSC32K Clock Failure Detector 2 1 STATUS Power and Clocks Status 0xC 32 read-only 0x00000000 XOSC32KRDY XOSC32K Ready 0 1 XOSC32KFAIL XOSC32K Clock Failure Detector 2 1 XOSC32KSW XOSC32K Clock switch 3 1 RTCCTRL RTC Clock Selection 0x10 8 0x00 RTCSEL RTC Clock Selection 0 3 RTCSELSelect ULP1K 1.024kHz from 32kHz internal ULP oscillator 0 ULP32K 32.768kHz from 32kHz internal ULP oscillator 1 XOSC1K 1.024kHz from 32.768kHz internal oscillator 4 XOSC32K 32.768kHz from 32.768kHz external crystal oscillator 5 XOSC32K 32kHz External Crystal Oscillator (XOSC32K) Control 0x14 16 0x2080 ENABLE Oscillator Enable 1 1 XTALEN Crystal Oscillator Enable 2 1 EN32K 32kHz Output Enable 3 1 EN1K 1kHz Output Enable 4 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 STARTUP Oscillator Start-Up Time 8 3 STARTUPSelect CYCLE2048 62.6 ms 0 CYCLE4096 125 ms 1 CYCLE16384 500 ms 2 CYCLE32768 1000 ms 3 CYCLE65536 2000 ms 4 CYCLE131072 4000 ms 5 CYCLE262144 8000 ms 6 WRTLOCK Write Lock 12 1 CGM Control Gain Mode 13 2 CGMSelect XT Standard mode 1 HS High Speed mode 2 CFDCTRL Clock Failure Detector Control 0x16 8 0x00 CFDEN Clock Failure Detector Enable 0 1 SWBACK Clock Switch Back 1 1 CFDPRESC Clock Failure Detector Prescaler 2 1 EVCTRL Event Control 0x17 8 0x00 CFDEO Clock Failure Detector Event Output Enable 0 1 OSCULP32K 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control 0x1C 32 0x00000000 EN32K Enable Out 32k 1 1 EN1K Enable Out 1k 2 1 CALIB Oscillator Calibration 8 6 WRTLOCK Write Lock 15 1 PAC U21201.2.0 Peripheral Access Controller PAC PAC_ 0x40000000 0 0x44 registers PAC 41 WRCTRL Write control 0x0 32 0x00000000 PERID Peripheral identifier 0 16 KEY Peripheral access control key 16 8 KEYSelect OFF No action 0 CLR Clear protection 1 SET Set protection 2 SETLCK Set and lock protection 3 EVCTRL Event control 0x4 8 0x00 ERREO Peripheral acess error event output 0 1 INTENCLR Interrupt enable clear 0x8 8 0x00 ERR Peripheral access error interrupt disable 0 1 INTENSET Interrupt enable set 0x9 8 0x00 ERR Peripheral access error interrupt enable 0 1 INTFLAGAHB Bridge interrupt flag status 0x10 32 0x00000000 FLASH_ FLASH 0 1 FLASH_ALT_ FLASH_ALT 1 1 SEEPROM_ SEEPROM 2 1 RAMCM4S_ RAMCM4S 3 1 RAMPPPDSU_ RAMPPPDSU 4 1 RAMDMAWR_ RAMDMAWR 5 1 RAMDMACICM_ RAMDMACICM 6 1 HPB0_ HPB0 7 1 HPB1_ HPB1 8 1 HPB2_ HPB2 9 1 HPB3_ HPB3 10 1 PUKCC_ PUKCC 11 1 SDHC0_ SDHC0 12 1 QSPI_ QSPI 14 1 BKUPRAM_ BKUPRAM 15 1 INTFLAGA Peripheral interrupt flag status - Bridge A 0x14 32 0x00000000 PAC_ PAC 0 1 PM_ PM 1 1 MCLK_ MCLK 2 1 RSTC_ RSTC 3 1 OSCCTRL_ OSCCTRL 4 1 OSC32KCTRL_ OSC32KCTRL 5 1 SUPC_ SUPC 6 1 GCLK_ GCLK 7 1 WDT_ WDT 8 1 RTC_ RTC 9 1 EIC_ EIC 10 1 FREQM_ FREQM 11 1 SERCOM0_ SERCOM0 12 1 SERCOM1_ SERCOM1 13 1 TC0_ TC0 14 1 TC1_ TC1 15 1 INTFLAGB Peripheral interrupt flag status - Bridge B 0x18 32 0x00000000 USB_ USB 0 1 DSU_ DSU 1 1 NVMCTRL_ NVMCTRL 2 1 CMCC_ CMCC 3 1 PORT_ PORT 4 1 DMAC_ DMAC 5 1 HMATRIX_ HMATRIX 6 1 EVSYS_ EVSYS 7 1 SERCOM2_ SERCOM2 9 1 SERCOM3_ SERCOM3 10 1 TCC0_ TCC0 11 1 TCC1_ TCC1 12 1 TC2_ TC2 13 1 TC3_ TC3 14 1 RAMECC_ RAMECC 16 1 INTFLAGC Peripheral interrupt flag status - Bridge C 0x1C 32 0x00000000 TCC2_ TCC2 3 1 TCC3_ TCC3 4 1 TC4_ TC4 5 1 TC5_ TC5 6 1 PDEC_ PDEC 7 1 AC_ AC 8 1 AES_ AES 9 1 TRNG_ TRNG 10 1 ICM_ ICM 11 1 PUKCC_ PUKCC 12 1 QSPI_ QSPI 13 1 CCL_ CCL 14 1 INTFLAGD Peripheral interrupt flag status - Bridge D 0x20 32 0x00000000 SERCOM4_ SERCOM4 0 1 SERCOM5_ SERCOM5 1 1 TCC4_ TCC4 4 1 ADC0_ ADC0 7 1 ADC1_ ADC1 8 1 DAC_ DAC 9 1 I2S_ I2S 10 1 PCC_ PCC 11 1 STATUSA Peripheral write protection status - Bridge A 0x34 32 read-only 0x00010000 PAC_ PAC APB Protect Enable 0 1 PM_ PM APB Protect Enable 1 1 MCLK_ MCLK APB Protect Enable 2 1 RSTC_ RSTC APB Protect Enable 3 1 OSCCTRL_ OSCCTRL APB Protect Enable 4 1 OSC32KCTRL_ OSC32KCTRL APB Protect Enable 5 1 SUPC_ SUPC APB Protect Enable 6 1 GCLK_ GCLK APB Protect Enable 7 1 WDT_ WDT APB Protect Enable 8 1 RTC_ RTC APB Protect Enable 9 1 EIC_ EIC APB Protect Enable 10 1 FREQM_ FREQM APB Protect Enable 11 1 SERCOM0_ SERCOM0 APB Protect Enable 12 1 SERCOM1_ SERCOM1 APB Protect Enable 13 1 TC0_ TC0 APB Protect Enable 14 1 TC1_ TC1 APB Protect Enable 15 1 STATUSB Peripheral write protection status - Bridge B 0x38 32 read-only 0x00000002 USB_ USB APB Protect Enable 0 1 DSU_ DSU APB Protect Enable 1 1 NVMCTRL_ NVMCTRL APB Protect Enable 2 1 CMCC_ CMCC APB Protect Enable 3 1 PORT_ PORT APB Protect Enable 4 1 DMAC_ DMAC APB Protect Enable 5 1 HMATRIX_ HMATRIX APB Protect Enable 6 1 EVSYS_ EVSYS APB Protect Enable 7 1 SERCOM2_ SERCOM2 APB Protect Enable 9 1 SERCOM3_ SERCOM3 APB Protect Enable 10 1 TCC0_ TCC0 APB Protect Enable 11 1 TCC1_ TCC1 APB Protect Enable 12 1 TC2_ TC2 APB Protect Enable 13 1 TC3_ TC3 APB Protect Enable 14 1 RAMECC_ RAMECC APB Protect Enable 16 1 STATUSC Peripheral write protection status - Bridge C 0x3C 32 read-only 0x00000000 TCC2_ TCC2 APB Protect Enable 3 1 TCC3_ TCC3 APB Protect Enable 4 1 TC4_ TC4 APB Protect Enable 5 1 TC5_ TC5 APB Protect Enable 6 1 PDEC_ PDEC APB Protect Enable 7 1 AC_ AC APB Protect Enable 8 1 AES_ AES APB Protect Enable 9 1 TRNG_ TRNG APB Protect Enable 10 1 ICM_ ICM APB Protect Enable 11 1 PUKCC_ PUKCC APB Protect Enable 12 1 QSPI_ QSPI APB Protect Enable 13 1 CCL_ CCL APB Protect Enable 14 1 STATUSD Peripheral write protection status - Bridge D 0x40 32 read-only 0x00000000 SERCOM4_ SERCOM4 APB Protect Enable 0 1 SERCOM5_ SERCOM5 APB Protect Enable 1 1 TCC4_ TCC4 APB Protect Enable 4 1 ADC0_ ADC0 APB Protect Enable 7 1 ADC1_ ADC1 APB Protect Enable 8 1 DAC_ DAC APB Protect Enable 9 1 I2S_ I2S APB Protect Enable 10 1 PCC_ PCC APB Protect Enable 11 1 PCC U20171.1.0 Parallel Capture Controller PCC PCC_ 0x43002C00 0 0xE8 registers PCC 129 MR Mode Register 0x0 32 0x00000000 PCEN Parallel Capture Enable 0 1 DSIZE Data size 4 2 SCALE Scale data 8 1 ALWYS Always Sampling 9 1 HALFS Half Sampling 10 1 FRSTS First sample 11 1 ISIZE Input Data Size 16 3 CID Clear If Disabled 30 2 IER Interrupt Enable Register 0x4 32 write-only 0x00000000 DRDY Data Ready Interrupt Enable 0 1 OVRE Overrun Error Interrupt Enable 1 1 IDR Interrupt Disable Register 0x8 32 write-only 0x00000000 DRDY Data Ready Interrupt Disable 0 1 OVRE Overrun Error Interrupt Disable 1 1 IMR Interrupt Mask Register 0xC 32 read-only 0x00000000 DRDY Data Ready Interrupt Mask 0 1 OVRE Overrun Error Interrupt Mask 1 1 ISR Interrupt Status Register 0x10 32 read-only 0x00000000 DRDY Data Ready Interrupt Status 0 1 OVRE Overrun Error Interrupt Status 1 1 RHR Reception Holding Register 0x14 32 read-only 0x00000000 RDATA Reception Data 0 32 WPMR Write Protection Mode Register 0xE0 32 0x00000000 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPSR Write Protection Status Register 0xE4 32 read-only 0x00000000 WPVS Write Protection Violation Source 0 1 WPVSRC Write Protection Violation Status 8 16 PDEC U22631.0.0 Quadrature Decodeur PDEC PDEC_ 0x42001C00 0 0x38 registers PDEC_OTHER 115 PDEC_MC0 116 PDEC_MC1 117 CTRLA Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operation Mode 2 2 MODESelect QDEC QDEC operating mode 0 HALL HALL operating mode 1 COUNTER COUNTER operating mode 2 RUNSTDBY Run in Standby 6 1 CONF PDEC Configuration 8 3 CONFSelect X4 Quadrature decoder direction 0 X4S Secure Quadrature decoder direction 1 X2 Decoder direction 2 X2S Secure decoder direction 3 AUTOC Auto correction mode 4 ALOCK Auto Lock 11 1 SWAP PDEC Phase A and B Swap 14 1 PEREN Period Enable 15 1 PINEN0 PDEC Input From Pin 0 Enable 16 1 PINEN1 PDEC Input From Pin 1 Enable 17 1 PINEN2 PDEC Input From Pin 2 Enable 18 1 PINVEN0 IO Pin 0 Invert Enable 20 1 PINVEN1 IO Pin 1 Invert Enable 21 1 PINVEN2 IO Pin 2 Invert Enable 22 1 ANGULAR Angular Counter Length 24 3 MAXCMP Maximum Consecutive Missing Pulses 28 4 CTRLBCLR Control B Clear 0x4 8 0x00 LUPD Lock Update 1 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a counter restart or retrigger 1 UPDATE Force update of double buffered registers 2 READSYNC Force a read synchronization of COUNT 3 START Start QDEC/HALL 4 STOP Stop QDEC/HALL 5 CTRLBSET Control B Set 0x5 8 0x00 LUPD Lock Update 1 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a counter restart or retrigger 1 UPDATE Force update of double buffered registers 2 READSYNC Force a read synchronization of COUNT 3 START Start QDEC/HALL 4 STOP Stop QDEC/HALL 5 EVCTRL Event Control 0x6 16 0x0000 EVACT Event Action 0 2 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger on event 1 COUNT Count on event 2 EVINV Inverted Event Input Enable 2 3 EVEI Event Input Enable 5 3 OVFEO Overflow/Underflow Output Event Enable 8 1 ERREO Error Output Event Enable 9 1 DIREO Direction Output Event Enable 10 1 VLCEO Velocity Output Event Enable 11 1 MCEO0 Match Channel 0 Event Output Enable 12 1 MCEO1 Match Channel 1 Event Output Enable 13 1 INTENCLR Interrupt Enable Clear 0x8 8 0x00 OVF Overflow/Underflow Interrupt Disable 0 1 ERR Error Interrupt Disable 1 1 DIR Direction Interrupt Disable 2 1 VLC Velocity Interrupt Disable 3 1 MC0 Channel 0 Compare Match Disable 4 1 MC1 Channel 1 Compare Match Disable 5 1 INTENSET Interrupt Enable Set 0x9 8 0x00 OVF Overflow/Underflow Interrupt Enable 0 1 ERR Error Interrupt Enable 1 1 DIR Direction Interrupt Enable 2 1 VLC Velocity Interrupt Enable 3 1 MC0 Channel 0 Compare Match Enable 4 1 MC1 Channel 1 Compare Match Enable 5 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 0x00 OVF Overflow/Underflow 0 1 ERR Error 1 1 DIR Direction Change 2 1 VLC Velocity 3 1 MC0 Channel 0 Compare Match 4 1 MC1 Channel 1 Compare Match 5 1 STATUS Status 0xC 16 0x0040 QERR Quadrature Error Flag 0 1 IDXERR Index Error Flag 1 1 MPERR Missing Pulse Error flag 2 1 WINERR Window Error Flag 4 1 HERR Hall Error Flag 5 1 STOP Stop 6 1 DIR Direction Status Flag 7 1 PRESCBUFV Prescaler Buffer Valid 8 1 FILTERBUFV Filter Buffer Valid 9 1 CCBUFV0 Compare Channel 0 Buffer Valid 12 1 CCBUFV1 Compare Channel 1 Buffer Valid 13 1 DBGCTRL Debug Control 0xF 8 0x00 DBGRUN Debug Run Mode 0 1 SYNCBUSY Synchronization Status 0x10 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE Enable Synchronization Busy 1 1 CTRLB Control B Synchronization Busy 2 1 STATUS Status Synchronization Busy 3 1 PRESC Prescaler Synchronization Busy 4 1 FILTER Filter Synchronization Busy 5 1 COUNT Count Synchronization Busy 6 1 CC0 Compare Channel 0 Synchronization Busy 7 1 CC1 Compare Channel 1 Synchronization Busy 8 1 PRESC Prescaler Value 0x14 8 0x00 PRESC Prescaler Value 0 4 PRESCSelect DIV1 No division 0 DIV2 Divide by 2 1 DIV4 Divide by 4 2 DIV8 Divide by 8 3 DIV16 Divide by 16 4 DIV32 Divide by 32 5 DIV64 Divide by 64 6 DIV128 Divide by 128 7 DIV256 Divide by 256 8 DIV512 Divide by 512 9 DIV1024 Divide by 1024 10 FILTER Filter Value 0x15 8 0x00 FILTER Filter Value 0 8 PRESCBUF Prescaler Buffer Value 0x18 8 0x00 PRESCBUF Prescaler Buffer Value 0 4 PRESCBUFSelect DIV1 No division 0 DIV2 Divide by 2 1 DIV4 Divide by 4 2 DIV8 Divide by 8 3 DIV16 Divide by 16 4 DIV32 Divide by 32 5 DIV64 Divide by 64 6 DIV128 Divide by 128 7 DIV256 Divide by 256 8 DIV512 Divide by 512 9 DIV1024 Divide by 1024 10 FILTERBUF Filter Buffer Value 0x19 8 0x00 FILTERBUF Filter Buffer Value 0 8 COUNT Counter Value 0x1C 32 0x00000000 COUNT Counter Value 0 16 2 4 CC[%s] Channel n Compare Value 0x20 32 0x00000000 CC Channel Compare Value 0 16 2 4 CCBUF[%s] Channel Compare Buffer Value 0x30 32 0x00000000 CCBUF Channel Compare Buffer Value 0 16 PM U24061.0.0 Power Manager PM PM_ 0x40000400 0 0x13 registers PM 0 CTRLA Control A 0x0 8 0x00 IORET I/O Retention 2 1 SLEEPCFG Sleep Configuration 0x1 8 0x02 SLEEPMODE Sleep Mode 0 3 SLEEPMODESelect IDLE CPU, AHBx, and APBx clocks are OFF 2 STANDBY All Clocks are OFF 4 HIBERNATE Backup domain is ON as well as some PDRAMs 5 BACKUP Only Backup domain is powered ON 6 OFF All power domains are powered OFF 7 INTENCLR Interrupt Enable Clear 0x4 8 0x00 SLEEPRDY Sleep Mode Entry Ready Enable 0 1 INTENSET Interrupt Enable Set 0x5 8 0x00 SLEEPRDY Sleep Mode Entry Ready Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 0x00 SLEEPRDY Sleep Mode Entry Ready 0 1 STDBYCFG Standby Configuration 0x8 8 0x00 RAMCFG Ram Configuration 0 2 RAMCFGSelect RET All the system RAM is retained 0 PARTIAL Only the first 32Kbytes of the system RAM is retained 1 OFF All the system RAM is turned OFF 2 FASTWKUP Fast Wakeup 4 2 FASTWKUPSelect NO Fast Wakeup is disabled 0 NVM Fast Wakeup is enabled on NVM 1 MAINVREG Fast Wakeup is enabled on the main voltage regulator (MAINVREG) 2 BOTH Fast Wakeup is enabled on both NVM and MAINVREG 3 HIBCFG Hibernate Configuration 0x9 8 0x00 RAMCFG Ram Configuration 0 2 RAMCFGSelect RET All the system RAM is retained 0 PARTIAL Only the first 32Kbytes of the system RAM is retained 1 OFF All the system RAM is turned OFF 2 BRAMCFG Backup Ram Configuration 2 2 BRAMCFGSelect RET All the backup RAM is retained 0 PARTIAL Only the first 4Kbytes of the backup RAM is retained 1 OFF All the backup RAM is turned OFF 2 BKUPCFG Backup Configuration 0xA 8 0x00 BRAMCFG Ram Configuration 0 2 BRAMCFGSelect RET All the backup RAM is retained 0 PARTIAL Only the first 4Kbytes of the backup RAM is retained 1 OFF All the backup RAM is turned OFF 2 PWSAKDLY Power Switch Acknowledge Delay 0x12 8 0x00 DLYVAL Delay Value 0 7 IGNACK Ignore Acknowledge 7 1 PORT U22102.2.0 Port Module PORT PORT_ 0x41008000 0 0x100 registers 2 0x80 GROUP[%s] 0x00 DIR Data Direction 0x0 32 0x00000000 DIR Port Data Direction 0 32 DIRCLR Data Direction Clear 0x4 32 0x00000000 DIRCLR Port Data Direction Clear 0 32 DIRSET Data Direction Set 0x8 32 0x00000000 DIRSET Port Data Direction Set 0 32 DIRTGL Data Direction Toggle 0xC 32 0x00000000 DIRTGL Port Data Direction Toggle 0 32 OUT Data Output Value 0x10 32 0x00000000 OUT PORT Data Output Value 0 32 OUTCLR Data Output Value Clear 0x14 32 0x00000000 OUTCLR PORT Data Output Value Clear 0 32 OUTSET Data Output Value Set 0x18 32 0x00000000 OUTSET PORT Data Output Value Set 0 32 OUTTGL Data Output Value Toggle 0x1C 32 0x00000000 OUTTGL PORT Data Output Value Toggle 0 32 IN Data Input Value 0x20 32 read-only 0x00000000 IN PORT Data Input Value 0 32 CTRL Control 0x24 32 0x00000000 SAMPLING Input Sampling Mode 0 32 WRCONFIG Write Configuration 0x28 32 write-only 0x00000000 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUXEN Peripheral Multiplexer Enable 16 1 INEN Input Enable 17 1 PULLEN Pull Enable 18 1 DRVSTR Output Driver Strength Selection 22 1 PMUX Peripheral Multiplexing 24 4 WRPMUX Write PMUX 28 1 WRPINCFG Write PINCFG 30 1 HWSEL Half-Word Select 31 1 EVCTRL Event Input Control 0x2C 32 0x00000000 PID0 PORT Event Pin Identifier 0 0 5 EVACT0 PORT Event Action 0 5 2 EVACT0Select OUT Event output to pin 0x0 SET Set output register of pin on event 0x1 CLR Clear output register of pin on event 0x2 TGL Toggle output register of pin on event 0x3 PORTEI0 PORT Event Input Enable 0 7 1 PID1 PORT Event Pin Identifier 1 8 5 EVACT1 PORT Event Action 1 13 2 PORTEI1 PORT Event Input Enable 1 15 1 PID2 PORT Event Pin Identifier 2 16 5 EVACT2 PORT Event Action 2 21 2 PORTEI2 PORT Event Input Enable 2 23 1 PID3 PORT Event Pin Identifier 3 24 5 EVACT3 PORT Event Action 3 29 2 PORTEI3 PORT Event Input Enable 3 31 1 16 1 PMUX[%s] Peripheral Multiplexing 0x30 8 0x00 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 32 1 PINCFG[%s] Pin Configuration 0x40 8 0x00 PMUXEN Peripheral Multiplexer Enable 0 1 INEN Input Enable 1 1 PULLEN Pull Enable 2 1 DRVSTR Output Driver Strength Selection 6 1 QSPI U20081.6.3 Quad SPI interface QSPI QSPI_ 0x42003400 0 0x48 registers QSPI 134 CTRLA Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 LASTXFER Last Transfer 24 1 CTRLB Control B 0x4 32 0x00000000 MODE Serial Memory Mode 0 1 MODESelect SPI SPI operating mode 0 MEMORY Serial Memory operating mode 1 LOOPEN Local Loopback Enable 1 1 WDRBT Wait Data Read Before Transfer 2 1 SMEMREG Serial Memory reg 3 1 CSMODE Chip Select Mode 4 2 CSMODESelect NORELOAD The chip select is deasserted if TD has not been reloaded before the end of the current transfer. 0x0 LASTXFER The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. 0x1 SYSTEMATICALLY The chip select is deasserted systematically after each transfer. 0x2 DATALEN Data Length 8 4 DATALENSelect 8BITS 8-bits transfer 0x0 9BITS 9 bits transfer 0x1 10BITS 10-bits transfer 0x2 11BITS 11-bits transfer 0x3 12BITS 12-bits transfer 0x4 13BITS 13-bits transfer 0x5 14BITS 14-bits transfer 0x6 15BITS 15-bits transfer 0x7 16BITS 16-bits transfer 0x8 DLYBCT Delay Between Consecutive Transfers 16 8 DLYCS Minimum Inactive CS Delay 24 8 BAUD Baud Rate 0x8 32 0x00000000 CPOL Clock Polarity 0 1 CPHA Clock Phase 1 1 BAUD Serial Clock Baud Rate 8 8 DLYBS Delay Before SCK 16 8 RXDATA Receive Data 0xC 32 read-only 0x00000000 DATA Receive Data 0 16 TXDATA Transmit Data 0x10 32 write-only 0x00000000 DATA Transmit Data 0 16 INTENCLR Interrupt Enable Clear 0x14 32 0x00000000 RXC Receive Data Register Full Interrupt Disable 0 1 DRE Transmit Data Register Empty Interrupt Disable 1 1 TXC Transmission Complete Interrupt Disable 2 1 ERROR Overrun Error Interrupt Disable 3 1 CSRISE Chip Select Rise Interrupt Disable 8 1 INSTREND Instruction End Interrupt Disable 10 1 INTENSET Interrupt Enable Set 0x18 32 0x00000000 RXC Receive Data Register Full Interrupt Enable 0 1 DRE Transmit Data Register Empty Interrupt Enable 1 1 TXC Transmission Complete Interrupt Enable 2 1 ERROR Overrun Error Interrupt Enable 3 1 CSRISE Chip Select Rise Interrupt Enable 8 1 INSTREND Instruction End Interrupt Enable 10 1 INTFLAG Interrupt Flag Status and Clear 0x1C 32 0x00000000 RXC Receive Data Register Full 0 1 DRE Transmit Data Register Empty 1 1 TXC Transmission Complete 2 1 ERROR Overrun Error 3 1 CSRISE Chip Select Rise 8 1 INSTREND Instruction End 10 1 STATUS Status Register 0x20 32 read-only 0x00000200 ENABLE Enable 1 1 CSSTATUS Chip Select 9 1 INSTRADDR Instruction Address 0x30 32 0x00000000 ADDR Instruction Address 0 32 INSTRCTRL Instruction Code 0x34 32 0x00000000 INSTR Instruction Code 0 8 OPTCODE Option Code 16 8 INSTRFRAME Instruction Frame 0x38 32 0x00000000 WIDTH Instruction Code, Address, Option Code and Data Width 0 3 WIDTHSelect SINGLE_BIT_SPI Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI 0x0 DUAL_OUTPUT Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI 0x1 QUAD_OUTPUT Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI 0x2 DUAL_IO Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI 0x3 QUAD_IO Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI 0x4 DUAL_CMD Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI 0x5 QUAD_CMD Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI 0x6 INSTREN Instruction Enable 4 1 ADDREN Address Enable 5 1 OPTCODEEN Option Enable 6 1 DATAEN Data Enable 7 1 OPTCODELEN Option Code Length 8 2 OPTCODELENSelect 1BIT 1-bit length option code 0x0 2BITS 2-bits length option code 0x1 4BITS 4-bits length option code 0x2 8BITS 8-bits length option code 0x3 ADDRLEN Address Length 10 1 ADDRLENSelect 24BITS 24-bits address length 0 32BITS 32-bits address length 1 TFRTYPE Data Transfer Type 12 2 TFRTYPESelect READ Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. 0x0 READMEMORY Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. 0x1 WRITE Write transfer into the serial memory.Scrambling is not performed. 0x2 WRITEMEMORY Write data transfer into the serial memory.If enabled, scrambling is performed. 0x3 CRMODE Continuous Read Mode 14 1 DDREN Double Data Rate Enable 15 1 DUMMYLEN Dummy Cycles Length 16 5 SCRAMBCTRL Scrambling Mode 0x40 32 0x00000000 ENABLE Scrambling/Unscrambling Enable 0 1 RANDOMDIS Scrambling/Unscrambling Random Value Disable 1 1 SCRAMBKEY Scrambling Key 0x44 32 write-only 0x00000000 KEY Scrambling User Key 0 32 RAMECC U22681.0.0 RAM ECC RAMECC RAMECC_ 0x41020000 0 0x10 registers RAMECC 45 INTENCLR Interrupt Enable Clear 0x0 8 0x00 SINGLEE Single Bit ECC Error Interrupt Enable Clear 0 1 DUALE Dual Bit ECC Error Interrupt Enable Clear 1 1 INTENSET Interrupt Enable Set 0x1 8 0x00 SINGLEE Single Bit ECC Error Interrupt Enable Set 0 1 DUALE Dual Bit ECC Error Interrupt Enable Set 1 1 INTFLAG Interrupt Flag 0x2 8 0x00 SINGLEE Single Bit ECC Error Interrupt 0 1 DUALE Dual Bit ECC Error Interrupt 1 1 STATUS Status 0x3 8 read-only 0x00 ECCDIS ECC Disable 0 1 ERRADDR Error Address 0x4 32 read-only 0x00000000 ERRADDR Error Address 0 17 DBGCTRL Debug Control 0xF 8 0x00 ECCDIS ECC Disable 0 1 ECCELOG ECC Error Log 1 1 RSTC U22394.0.0 Reset Controller RSTC RSTC_ 0x40000C00 0 0x3 registers RCAUSE Reset Cause 0x0 8 read-only POR Power On Reset 0 1 BODCORE Brown Out CORE Detector Reset 1 1 BODVDD Brown Out VDD Detector Reset 2 1 NVM NVM Reset 3 1 EXT External Reset 4 1 WDT Watchdog Reset 5 1 SYST System Reset Request 6 1 BACKUP Backup Reset 7 1 BKUPEXIT Backup Exit Source 0x2 8 read-only 0x00 RTC Real Timer Counter Interrupt 1 1 BBPS Battery Backup Power Switch 2 1 HIB Hibernate 7 1 RTC U22502.1.0 Real-Time Counter RTC RTC_ 0x40002400 0 0xA0 registers RTC 11 MODE0 32-bit Counter with Single 32-bit Compare RtcMode0 0x0 CTRLA MODE0 Control A 0x0 16 0x0000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 MATCHCLR Clear on Match 7 1 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xB BKTRST BKUP Registers Reset On Tamper Enable 13 1 GPTRST GP Registers Reset On Tamper Enable 14 1 COUNTSYNC Count Read Synchronization Enable 15 1 CTRLB MODE0 Control B 0x2 16 0x0000 GP0EN General Purpose 0 Enable 0 1 GP2EN General Purpose 2 Enable 1 1 DEBMAJ Debouncer Majority Enable 4 1 DEBASYNC Debouncer Asynchronous Enable 5 1 RTCOUT RTC Output Enable 6 1 DMAEN DMA Enable 7 1 DEBF Debounce Freqnuency 8 3 DEBFSelect DIV2 CLK_RTC_DEB = CLK_RTC/2 0x0 DIV4 CLK_RTC_DEB = CLK_RTC/4 0x1 DIV8 CLK_RTC_DEB = CLK_RTC/8 0x2 DIV16 CLK_RTC_DEB = CLK_RTC/16 0x3 DIV32 CLK_RTC_DEB = CLK_RTC/32 0x4 DIV64 CLK_RTC_DEB = CLK_RTC/64 0x5 DIV128 CLK_RTC_DEB = CLK_RTC/128 0x6 DIV256 CLK_RTC_DEB = CLK_RTC/256 0x7 ACTF Active Layer Freqnuency 12 3 ACTFSelect DIV2 CLK_RTC_OUT = CLK_RTC/2 0x0 DIV4 CLK_RTC_OUT = CLK_RTC/4 0x1 DIV8 CLK_RTC_OUT = CLK_RTC/8 0x2 DIV16 CLK_RTC_OUT = CLK_RTC/16 0x3 DIV32 CLK_RTC_OUT = CLK_RTC/32 0x4 DIV64 CLK_RTC_OUT = CLK_RTC/64 0x5 DIV128 CLK_RTC_OUT = CLK_RTC/128 0x6 DIV256 CLK_RTC_OUT = CLK_RTC/256 0x7 EVCTRL MODE0 Event Control 0x4 32 0x00000000 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 CMPEO0 Compare 0 Event Output Enable 8 1 CMPEO1 Compare 1 Event Output Enable 9 1 TAMPEREO Tamper Event Output Enable 14 1 OVFEO Overflow Event Output Enable 15 1 TAMPEVEI Tamper Event Input Enable 16 1 INTENCLR MODE0 Interrupt Enable Clear 0x8 16 0x0000 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 TAMPER Tamper Enable 14 1 OVF Overflow Interrupt Enable 15 1 INTENSET MODE0 Interrupt Enable Set 0xA 16 0x0000 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 TAMPER Tamper Enable 14 1 OVF Overflow Interrupt Enable 15 1 INTFLAG MODE0 Interrupt Flag Status and Clear 0xC 16 0x0000 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 CMP0 Compare 0 8 1 CMP1 Compare 1 9 1 TAMPER Tamper 14 1 OVF Overflow 15 1 DBGCTRL Debug Control 0xE 8 0x00 DBGRUN Run During Debug 0 1 SYNCBUSY MODE0 Synchronization Busy Status 0x10 32 read-only 0x00000000 SWRST Software Reset Busy 0 1 ENABLE Enable Bit Busy 1 1 FREQCORR FREQCORR Register Busy 2 1 COUNT COUNT Register Busy 3 1 COMP0 COMP 0 Register Busy 5 1 COMP1 COMP 1 Register Busy 6 1 COUNTSYNC Count Synchronization Enable Bit Busy 15 1 GP0 General Purpose 0 Register Busy 16 1 GP1 General Purpose 1 Register Busy 17 1 GP2 General Purpose 2 Register Busy 18 1 GP3 General Purpose 3 Register Busy 19 1 FREQCORR Frequency Correction 0x14 8 0x00 VALUE Correction Value 0 7 SIGN Correction Sign 7 1 COUNT MODE0 Counter Value 0x18 32 0x00000000 COUNT Counter Value 0 32 2 4 COMP[%s] MODE0 Compare n Value 0x20 32 0x00000000 COMP Compare Value 0 32 4 4 GP[%s] General Purpose 0x40 32 0x00000000 GP General Purpose 0 32 TAMPCTRL Tamper Control 0x60 32 0x00000000 IN0ACT Tamper Input 0 Action 0 2 IN0ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN0 to OUT 0x3 IN1ACT Tamper Input 1 Action 2 2 IN1ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN1 to OUT 0x3 IN2ACT Tamper Input 2 Action 4 2 IN2ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN2 to OUT 0x3 IN3ACT Tamper Input 3 Action 6 2 IN3ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN3 to OUT 0x3 IN4ACT Tamper Input 4 Action 8 2 IN4ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN4 to OUT 0x3 TAMLVL0 Tamper Level Select 0 16 1 TAMLVL1 Tamper Level Select 1 17 1 TAMLVL2 Tamper Level Select 2 18 1 TAMLVL3 Tamper Level Select 3 19 1 TAMLVL4 Tamper Level Select 4 20 1 DEBNC0 Debouncer Enable 0 24 1 DEBNC1 Debouncer Enable 1 25 1 DEBNC2 Debouncer Enable 2 26 1 DEBNC3 Debouncer Enable 3 27 1 DEBNC4 Debouncer Enable 4 28 1 TIMESTAMP MODE0 Timestamp 0x64 32 read-only 0x00000000 COUNT Count Timestamp Value 0 32 TAMPID Tamper ID 0x68 32 0x00000000 TAMPID0 Tamper Input 0 Detected 0 1 TAMPID1 Tamper Input 1 Detected 1 1 TAMPID2 Tamper Input 2 Detected 2 1 TAMPID3 Tamper Input 3 Detected 3 1 TAMPID4 Tamper Input 4 Detected 4 1 TAMPEVT Tamper Event Detected 31 1 8 4 BKUP[%s] Backup 0x80 32 0x00000000 BKUP Backup 0 32 MODE1 16-bit Counter with Two 16-bit Compares MODE0 RtcMode1 0x0 CTRLA MODE1 Control A 0x0 16 0x0000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0 COUNT16 Mode 1: 16-bit Counter 1 CLOCK Mode 2: Clock/Calendar 2 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xB BKTRST BKUP Registers Reset On Tamper Enable 13 1 GPTRST GP Registers Reset On Tamper Enable 14 1 COUNTSYNC Count Read Synchronization Enable 15 1 CTRLB MODE1 Control B 0x2 16 0x0000 GP0EN General Purpose 0 Enable 0 1 GP2EN General Purpose 2 Enable 1 1 DEBMAJ Debouncer Majority Enable 4 1 DEBASYNC Debouncer Asynchronous Enable 5 1 RTCOUT RTC Output Enable 6 1 DMAEN DMA Enable 7 1 DEBF Debounce Freqnuency 8 3 DEBFSelect DIV2 CLK_RTC_DEB = CLK_RTC/2 0x0 DIV4 CLK_RTC_DEB = CLK_RTC/4 0x1 DIV8 CLK_RTC_DEB = CLK_RTC/8 0x2 DIV16 CLK_RTC_DEB = CLK_RTC/16 0x3 DIV32 CLK_RTC_DEB = CLK_RTC/32 0x4 DIV64 CLK_RTC_DEB = CLK_RTC/64 0x5 DIV128 CLK_RTC_DEB = CLK_RTC/128 0x6 DIV256 CLK_RTC_DEB = CLK_RTC/256 0x7 ACTF Active Layer Freqnuency 12 3 ACTFSelect DIV2 CLK_RTC_OUT = CLK_RTC/2 0x0 DIV4 CLK_RTC_OUT = CLK_RTC/4 0x1 DIV8 CLK_RTC_OUT = CLK_RTC/8 0x2 DIV16 CLK_RTC_OUT = CLK_RTC/16 0x3 DIV32 CLK_RTC_OUT = CLK_RTC/32 0x4 DIV64 CLK_RTC_OUT = CLK_RTC/64 0x5 DIV128 CLK_RTC_OUT = CLK_RTC/128 0x6 DIV256 CLK_RTC_OUT = CLK_RTC/256 0x7 EVCTRL MODE1 Event Control 0x4 32 0x00000000 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 CMPEO0 Compare 0 Event Output Enable 8 1 CMPEO1 Compare 1 Event Output Enable 9 1 CMPEO2 Compare 2 Event Output Enable 10 1 CMPEO3 Compare 3 Event Output Enable 11 1 TAMPEREO Tamper Event Output Enable 14 1 OVFEO Overflow Event Output Enable 15 1 TAMPEVEI Tamper Event Input Enable 16 1 INTENCLR MODE1 Interrupt Enable Clear 0x8 16 0x0000 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 CMP2 Compare 2 Interrupt Enable 10 1 CMP3 Compare 3 Interrupt Enable 11 1 TAMPER Tamper Enable 14 1 OVF Overflow Interrupt Enable 15 1 INTENSET MODE1 Interrupt Enable Set 0xA 16 0x0000 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 CMP2 Compare 2 Interrupt Enable 10 1 CMP3 Compare 3 Interrupt Enable 11 1 TAMPER Tamper Enable 14 1 OVF Overflow Interrupt Enable 15 1 INTFLAG MODE1 Interrupt Flag Status and Clear 0xC 16 0x0000 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 CMP0 Compare 0 8 1 CMP1 Compare 1 9 1 CMP2 Compare 2 10 1 CMP3 Compare 3 11 1 TAMPER Tamper 14 1 OVF Overflow 15 1 DBGCTRL Debug Control 0xE 8 0x00 DBGRUN Run During Debug 0 1 SYNCBUSY MODE1 Synchronization Busy Status 0x10 32 read-only 0x00000000 SWRST Software Reset Bit Busy 0 1 ENABLE Enable Bit Busy 1 1 FREQCORR FREQCORR Register Busy 2 1 COUNT COUNT Register Busy 3 1 PER PER Register Busy 4 1 COMP0 COMP 0 Register Busy 5 1 COMP1 COMP 1 Register Busy 6 1 COMP2 COMP 2 Register Busy 7 1 COMP3 COMP 3 Register Busy 8 1 COUNTSYNC Count Synchronization Enable Bit Busy 15 1 GP0 General Purpose 0 Register Busy 16 1 GP1 General Purpose 1 Register Busy 17 1 GP2 General Purpose 2 Register Busy 18 1 GP3 General Purpose 3 Register Busy 19 1 FREQCORR Frequency Correction 0x14 8 0x00 VALUE Correction Value 0 7 SIGN Correction Sign 7 1 COUNT MODE1 Counter Value 0x18 16 0x0000 COUNT Counter Value 0 16 PER MODE1 Counter Period 0x1C 16 0x0000 PER Counter Period 0 16 4 2 COMP[%s] MODE1 Compare n Value 0x20 16 0x0000 COMP Compare Value 0 16 4 4 GP[%s] General Purpose 0x40 32 0x00000000 GP General Purpose 0 32 TAMPCTRL Tamper Control 0x60 32 0x00000000 IN0ACT Tamper Input 0 Action 0 2 IN0ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN0 to OUT 0x3 IN1ACT Tamper Input 1 Action 2 2 IN1ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN1 to OUT 0x3 IN2ACT Tamper Input 2 Action 4 2 IN2ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN2 to OUT 0x3 IN3ACT Tamper Input 3 Action 6 2 IN3ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN3 to OUT 0x3 IN4ACT Tamper Input 4 Action 8 2 IN4ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN4 to OUT 0x3 TAMLVL0 Tamper Level Select 0 16 1 TAMLVL1 Tamper Level Select 1 17 1 TAMLVL2 Tamper Level Select 2 18 1 TAMLVL3 Tamper Level Select 3 19 1 TAMLVL4 Tamper Level Select 4 20 1 DEBNC0 Debouncer Enable 0 24 1 DEBNC1 Debouncer Enable 1 25 1 DEBNC2 Debouncer Enable 2 26 1 DEBNC3 Debouncer Enable 3 27 1 DEBNC4 Debouncer Enable 4 28 1 TIMESTAMP MODE1 Timestamp 0x64 32 read-only 0x00000000 COUNT Count Timestamp Value 0 16 TAMPID Tamper ID 0x68 32 0x00000000 TAMPID0 Tamper Input 0 Detected 0 1 TAMPID1 Tamper Input 1 Detected 1 1 TAMPID2 Tamper Input 2 Detected 2 1 TAMPID3 Tamper Input 3 Detected 3 1 TAMPID4 Tamper Input 4 Detected 4 1 TAMPEVT Tamper Event Detected 31 1 8 4 BKUP[%s] Backup 0x80 32 0x00000000 BKUP Backup 0 32 MODE2 Clock/Calendar with Alarm MODE0 RtcMode2 0x0 CTRLA MODE2 Control A 0x0 16 0x0000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0 COUNT16 Mode 1: 16-bit Counter 1 CLOCK Mode 2: Clock/Calendar 2 CLKREP Clock Representation 6 1 MATCHCLR Clear on Match 7 1 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xB BKTRST BKUP Registers Reset On Tamper Enable 13 1 GPTRST GP Registers Reset On Tamper Enable 14 1 CLOCKSYNC Clock Read Synchronization Enable 15 1 CTRLB MODE2 Control B 0x2 16 0x0000 GP0EN General Purpose 0 Enable 0 1 GP2EN General Purpose 2 Enable 1 1 DEBMAJ Debouncer Majority Enable 4 1 DEBASYNC Debouncer Asynchronous Enable 5 1 RTCOUT RTC Output Enable 6 1 DMAEN DMA Enable 7 1 DEBF Debounce Freqnuency 8 3 DEBFSelect DIV2 CLK_RTC_DEB = CLK_RTC/2 0x0 DIV4 CLK_RTC_DEB = CLK_RTC/4 0x1 DIV8 CLK_RTC_DEB = CLK_RTC/8 0x2 DIV16 CLK_RTC_DEB = CLK_RTC/16 0x3 DIV32 CLK_RTC_DEB = CLK_RTC/32 0x4 DIV64 CLK_RTC_DEB = CLK_RTC/64 0x5 DIV128 CLK_RTC_DEB = CLK_RTC/128 0x6 DIV256 CLK_RTC_DEB = CLK_RTC/256 0x7 ACTF Active Layer Freqnuency 12 3 ACTFSelect DIV2 CLK_RTC_OUT = CLK_RTC/2 0x0 DIV4 CLK_RTC_OUT = CLK_RTC/4 0x1 DIV8 CLK_RTC_OUT = CLK_RTC/8 0x2 DIV16 CLK_RTC_OUT = CLK_RTC/16 0x3 DIV32 CLK_RTC_OUT = CLK_RTC/32 0x4 DIV64 CLK_RTC_OUT = CLK_RTC/64 0x5 DIV128 CLK_RTC_OUT = CLK_RTC/128 0x6 DIV256 CLK_RTC_OUT = CLK_RTC/256 0x7 EVCTRL MODE2 Event Control 0x4 32 0x00000000 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 ALARMEO0 Alarm 0 Event Output Enable 8 1 ALARMEO1 Alarm 1 Event Output Enable 9 1 TAMPEREO Tamper Event Output Enable 14 1 OVFEO Overflow Event Output Enable 15 1 TAMPEVEI Tamper Event Input Enable 16 1 INTENCLR MODE2 Interrupt Enable Clear 0x8 16 0x0000 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 ALARM0 Alarm 0 Interrupt Enable 8 1 ALARM1 Alarm 1 Interrupt Enable 9 1 TAMPER Tamper Enable 14 1 OVF Overflow Interrupt Enable 15 1 INTENSET MODE2 Interrupt Enable Set 0xA 16 0x0000 PER0 Periodic Interval 0 Enable 0 1 PER1 Periodic Interval 1 Enable 1 1 PER2 Periodic Interval 2 Enable 2 1 PER3 Periodic Interval 3 Enable 3 1 PER4 Periodic Interval 4 Enable 4 1 PER5 Periodic Interval 5 Enable 5 1 PER6 Periodic Interval 6 Enable 6 1 PER7 Periodic Interval 7 Enable 7 1 ALARM0 Alarm 0 Interrupt Enable 8 1 ALARM1 Alarm 1 Interrupt Enable 9 1 TAMPER Tamper Enable 14 1 OVF Overflow Interrupt Enable 15 1 INTFLAG MODE2 Interrupt Flag Status and Clear 0xC 16 0x0000 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 ALARM0 Alarm 0 8 1 ALARM1 Alarm 1 9 1 TAMPER Tamper 14 1 OVF Overflow 15 1 DBGCTRL Debug Control 0xE 8 0x00 DBGRUN Run During Debug 0 1 SYNCBUSY MODE2 Synchronization Busy Status 0x10 32 read-only 0x00000000 SWRST Software Reset Bit Busy 0 1 ENABLE Enable Bit Busy 1 1 FREQCORR FREQCORR Register Busy 2 1 CLOCK CLOCK Register Busy 3 1 ALARM0 ALARM 0 Register Busy 5 1 ALARM1 ALARM 1 Register Busy 6 1 MASK0 MASK 0 Register Busy 11 1 MASK1 MASK 1 Register Busy 12 1 CLOCKSYNC Clock Synchronization Enable Bit Busy 15 1 GP0 General Purpose 0 Register Busy 16 1 GP1 General Purpose 1 Register Busy 17 1 GP2 General Purpose 2 Register Busy 18 1 GP3 General Purpose 3 Register Busy 19 1 FREQCORR Frequency Correction 0x14 8 0x00 VALUE Correction Value 0 7 SIGN Correction Sign 7 1 CLOCK MODE2 Clock Value 0x18 32 0x00000000 SECOND Second 0 6 MINUTE Minute 6 6 HOUR Hour 12 5 HOURSelect AM AM when CLKREP in 12-hour 0x00 PM PM when CLKREP in 12-hour 0x10 DAY Day 17 5 MONTH Month 22 4 YEAR Year 26 6 4 4 GP[%s] General Purpose 0x40 32 0x00000000 GP General Purpose 0 32 ALARM0 MODE2_ALARM Alarm n Value 0x20 32 0x00000000 SECOND Second 0 6 MINUTE Minute 6 6 HOUR Hour 12 5 HOURSelect AM Morning hour 0x00 PM Afternoon hour 0x10 DAY Day 17 5 MONTH Month 22 4 YEAR Year 26 6 MASK0 MODE2_ALARM Alarm n Mask 0x24 8 0x00 SEL Alarm Mask Selection 0 3 SELSelect OFF Alarm Disabled 0x0 SS Match seconds only 0x1 MMSS Match seconds and minutes only 0x2 HHMMSS Match seconds, minutes, and hours only 0x3 DDHHMMSS Match seconds, minutes, hours, and days only 0x4 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x5 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x6 ALARM1 MODE2_ALARM Alarm n Value 0x28 32 0x00000000 SECOND Second 0 6 MINUTE Minute 6 6 HOUR Hour 12 5 HOURSelect AM Morning hour 0x00 PM Afternoon hour 0x10 DAY Day 17 5 MONTH Month 22 4 YEAR Year 26 6 MASK1 MODE2_ALARM Alarm n Mask 0x2C 8 0x00 SEL Alarm Mask Selection 0 3 SELSelect OFF Alarm Disabled 0x0 SS Match seconds only 0x1 MMSS Match seconds and minutes only 0x2 HHMMSS Match seconds, minutes, and hours only 0x3 DDHHMMSS Match seconds, minutes, hours, and days only 0x4 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x5 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x6 TAMPCTRL Tamper Control 0x60 32 0x00000000 IN0ACT Tamper Input 0 Action 0 2 IN0ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN0 to OUT 0x3 IN1ACT Tamper Input 1 Action 2 2 IN1ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN1 to OUT 0x3 IN2ACT Tamper Input 2 Action 4 2 IN2ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN2 to OUT 0x3 IN3ACT Tamper Input 3 Action 6 2 IN3ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN3 to OUT 0x3 IN4ACT Tamper Input 4 Action 8 2 IN4ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN4 to OUT 0x3 TAMLVL0 Tamper Level Select 0 16 1 TAMLVL1 Tamper Level Select 1 17 1 TAMLVL2 Tamper Level Select 2 18 1 TAMLVL3 Tamper Level Select 3 19 1 TAMLVL4 Tamper Level Select 4 20 1 DEBNC0 Debouncer Enable 0 24 1 DEBNC1 Debouncer Enable 1 25 1 DEBNC2 Debouncer Enable 2 26 1 DEBNC3 Debouncer Enable 3 27 1 DEBNC4 Debouncer Enable 4 28 1 TIMESTAMP MODE2 Timestamp 0x64 32 read-only 0x00000000 SECOND Second Timestamp Value 0 6 MINUTE Minute Timestamp Value 6 6 HOUR Hour Timestamp Value 12 5 HOURSelect AM AM when CLKREP in 12-hour 0x00 PM PM when CLKREP in 12-hour 0x10 DAY Day Timestamp Value 17 5 MONTH Month Timestamp Value 22 4 YEAR Year Timestamp Value 26 6 TAMPID Tamper ID 0x68 32 0x00000000 TAMPID0 Tamper Input 0 Detected 0 1 TAMPID1 Tamper Input 1 Detected 1 1 TAMPID2 Tamper Input 2 Detected 2 1 TAMPID3 Tamper Input 3 Detected 3 1 TAMPID4 Tamper Input 4 Detected 4 1 TAMPEVT Tamper Event Detected 31 1 8 4 BKUP[%s] Backup 0x80 32 0x00000000 BKUP Backup 0 32 SDHC0 U20111.8.3 SD/MMC Host Controller SDHC SDHC_ 0x45000000 0 0x235 registers SDHC0 135 SSAR SDMA System Address / Argument 2 0x0 32 0x00000000 ADDR SDMA System Address 0 32 SSAR_CMD23_MODE SDMA System Address / Argument 2 SSAR 0x0 32 0x00000000 ARG2 Argument 2 0 32 BSR Block Size 0x4 16 0x0000 BLOCKSIZE Transfer Block Size 0 10 BOUNDARY SDMA Buffer Boundary 12 3 BOUNDARYSelect 4K 4k bytes 0 8K 8k bytes 1 16K 16k bytes 2 32K 32k bytes 3 64K 64k bytes 4 128K 128k bytes 5 256K 256k bytes 6 512K 512k bytes 7 BCR Block Count 0x6 16 0x0000 BCNT Blocks Count for Current Transfer 0 16 ARG1R Argument 1 0x8 32 0x00000000 ARG Argument 1 0 32 TMR Transfer Mode 0xC 16 0x0000 DMAEN DMA Enable 0 1 DMAENSelect DISABLE No data transfer or Non DMA data transfer 0 ENABLE DMA data transfer 1 BCEN Block Count Enable 1 1 BCENSelect DISABLE Disable 0 ENABLE Enable 1 ACMDEN Auto Command Enable 2 2 ACMDENSelect DISABLED Auto Command Disabled 0 CMD12 Auto CMD12 Enable 1 CMD23 Auto CMD23 Enable 2 DTDSEL Data Transfer Direction Selection 4 1 DTDSELSelect WRITE Write (Host to Card) 0 READ Read (Card to Host) 1 MSBSEL Multi/Single Block Selection 5 1 MSBSELSelect SINGLE Single Block 0 MULTIPLE Multiple Block 1 CR Command 0xE 16 0x0000 RESPTYP Response Type 0 2 RESPTYPSelect NONE No response 0 136_BIT 136-bit response 1 48_BIT 48-bit response 2 48_BIT_BUSY 48-bit response check busy after response 3 CMDCCEN Command CRC Check Enable 3 1 CMDCCENSelect DISABLE Disable 0 ENABLE Enable 1 CMDICEN Command Index Check Enable 4 1 CMDICENSelect DISABLE Disable 0 ENABLE Enable 1 DPSEL Data Present Select 5 1 DPSELSelect NO_DATA No Data Present 0 DATA Data Present 1 CMDTYP Command Type 6 2 CMDTYPSelect NORMAL Other commands 0 SUSPEND CMD52 for writing Bus Suspend in CCCR 1 RESUME CMD52 for writing Function Select in CCCR 2 ABORT CMD12, CMD52 for writing I/O Abort in CCCR 3 CMDIDX Command Index 8 6 4 4 RR[%s] Response 0x10 32 read-only 0x00000000 CMDRESP Command Response 0 32 BDPR Buffer Data Port 0x20 32 0x00000000 BUFDATA Buffer Data 0 32 PSR Present State 0x24 32 read-only 0x00F80000 CMDINHC Command Inhibit (CMD) 0 1 CMDINHCSelect CAN Can issue command using only CMD line 0 CANNOT Cannot issue command 1 CMDINHD Command Inhibit (DAT) 1 1 CMDINHDSelect CAN Can issue command which uses the DAT line 0 CANNOT Cannot issue command which uses the DAT line 1 DLACT DAT Line Active 2 1 DLACTSelect INACTIVE DAT Line Inactive 0 ACTIVE DAT Line Active 1 RTREQ Re-Tuning Request 3 1 RTREQSelect OK Fixed or well-tuned sampling clock 0 REQUIRED Sampling clock needs re-tuning 1 WTACT Write Transfer Active 8 1 WTACTSelect NO No valid data 0 YES Transferring data 1 RTACT Read Transfer Active 9 1 RTACTSelect NO No valid data 0 YES Transferring data 1 BUFWREN Buffer Write Enable 10 1 BUFWRENSelect DISABLE Write disable 0 ENABLE Write enable 1 BUFRDEN Buffer Read Enable 11 1 BUFRDENSelect DISABLE Read disable 0 ENABLE Read enable 1 CARDINS Card Inserted 16 1 CARDINSSelect NO Reset or Debouncing or No Card 0 YES Card inserted 1 CARDSS Card State Stable 17 1 CARDSSSelect NO Reset or Debouncing 0 YES No Card or Insered 1 CARDDPL Card Detect Pin Level 18 1 CARDDPLSelect NO No card present (SDCD#=1) 0 YES Card present (SDCD#=0) 1 WRPPL Write Protect Pin Level 19 1 WRPPLSelect PROTECTED Write protected (SDWP#=0) 0 ENABLED Write enabled (SDWP#=1) 1 DATLL DAT[3:0] Line Level 20 4 CMDLL CMD Line Level 24 1 HC1R Host Control 1 0x28 8 0xE00 LEDCTRL LED Control 0 1 LEDCTRLSelect OFF LED off 0 ON LED on 1 DW Data Width 1 1 DWSelect 1BIT 1-bit mode 0 4BIT 4-bit mode 1 HSEN High Speed Enable 2 1 HSENSelect NORMAL Normal Speed mode 0 HIGH High Speed mode 1 DMASEL DMA Select 3 2 DMASELSelect SDMA SDMA is selected 0 32BIT 32-bit Address ADMA2 is selected 2 CARDDTL Card Detect Test Level 6 1 CARDDTLSelect NO No Card 0 YES Card Inserted 1 CARDDSEL Card Detect Signal Selection 7 1 CARDDSELSelect NORMAL SDCD# is selected (for normal use) 0 TEST The Card Select Test Level is selected (for test purpose) 1 HC1R_EMMC_MODE Host Control 1 HC1R 0x28 8 0xE00 DW Data Width 1 1 DWSelect 1BIT 1-bit mode 0 4BIT 4-bit mode 1 HSEN High Speed Enable 2 1 HSENSelect NORMAL Normal Speed mode 0 HIGH High Speed mode 1 DMASEL DMA Select 3 2 DMASELSelect SDMA SDMA is selected 0 32BIT 32-bit Address ADMA2 is selected 2 PCR Power Control 0x29 8 0x0E SDBPWR SD Bus Power 0 1 SDBPWRSelect OFF Power off 0 ON Power on 1 SDBVSEL SD Bus Voltage Select 1 3 SDBVSELSelect 1V8 1.8V (Typ.) 5 3V0 3.0V (Typ.) 6 3V3 3.3V (Typ.) 7 BGCR Block Gap Control 0x2A 8 0x00 STPBGR Stop at Block Gap Request 0 1 STPBGRSelect TRANSFER Transfer 0 STOP Stop 1 CONTR Continue Request 1 1 CONTRSelect GO_ON Not affected 0 RESTART Restart 1 RWCTRL Read Wait Control 2 1 RWCTRLSelect DISABLE Disable Read Wait Control 0 ENABLE Enable Read Wait Control 1 INTBG Interrupt at Block Gap 3 1 INTBGSelect DISABLED Disabled 0 ENABLED Enabled 1 BGCR_EMMC_MODE Block Gap Control BGCR 0x2A 8 0x00 STPBGR Stop at Block Gap Request 0 1 STPBGRSelect TRANSFER Transfer 0 STOP Stop 1 CONTR Continue Request 1 1 CONTRSelect GO_ON Not affected 0 RESTART Restart 1 WCR Wakeup Control 0x2B 8 0x00 WKENCINT Wakeup Event Enable on Card Interrupt 0 1 WKENCINTSelect DISABLE Disable 0 ENABLE Enable 1 WKENCINS Wakeup Event Enable on Card Insertion 1 1 WKENCINSSelect DISABLE Disable 0 ENABLE Enable 1 WKENCREM Wakeup Event Enable on Card Removal 2 1 WKENCREMSelect DISABLE Disable 0 ENABLE Enable 1 CCR Clock Control 0x2C 16 0x0000 INTCLKEN Internal Clock Enable 0 1 INTCLKENSelect OFF Stop 0 ON Oscillate 1 INTCLKS Internal Clock Stable 1 1 INTCLKSSelect NOT_READY Not Ready 0 READY Ready 1 SDCLKEN SD Clock Enable 2 1 SDCLKENSelect DISABLE Disable 0 ENABLE Enable 1 CLKGSEL Clock Generator Select 5 1 CLKGSELSelect DIV Divided Clock Mode 0 PROG Programmable Clock Mode 1 USDCLKFSEL Upper Bits of SDCLK Frequency Select 6 2 SDCLKFSEL SDCLK Frequency Select 8 8 TCR Timeout Control 0x2E 8 0x00 DTCVAL Data Timeout Counter Value 0 4 SRR Software Reset 0x2F 8 0x00 SWRSTALL Software Reset For All 0 1 SWRSTALLSelect WORK Work 0 RESET Reset 1 SWRSTCMD Software Reset For CMD Line 1 1 SWRSTCMDSelect WORK Work 0 RESET Reset 1 SWRSTDAT Software Reset For DAT Line 2 1 SWRSTDATSelect WORK Work 0 RESET Reset 1 NISTR Normal Interrupt Status 0x30 16 0x0000 CMDC Command Complete 0 1 CMDCSelect NO No command complete 0 YES Command complete 1 TRFC Transfer Complete 1 1 TRFCSelect NO Not complete 0 YES Command execution is completed 1 BLKGE Block Gap Event 2 1 BLKGESelect NO No Block Gap Event 0 STOP Transaction stopped at block gap 1 DMAINT DMA Interrupt 3 1 DMAINTSelect NO No DMA Interrupt 0 YES DMA Interrupt is generated 1 BWRRDY Buffer Write Ready 4 1 BWRRDYSelect NO Not ready to write buffer 0 YES Ready to write buffer 1 BRDRDY Buffer Read Ready 5 1 BRDRDYSelect NO Not ready to read buffer 0 YES Ready to read buffer 1 CINS Card Insertion 6 1 CINSSelect NO Card state stable or Debouncing 0 YES Card inserted 1 CREM Card Removal 7 1 CREMSelect NO Card state stable or Debouncing 0 YES Card Removed 1 CINT Card Interrupt 8 1 CINTSelect NO No Card Interrupt 0 YES Generate Card Interrupt 1 ERRINT Error Interrupt 15 1 ERRINTSelect NO No Error 0 YES Error 1 NISTR_EMMC_MODE Normal Interrupt Status NISTR 0x30 16 0x0000 CMDC Command Complete 0 1 CMDCSelect NO No command complete 0 YES Command complete 1 TRFC Transfer Complete 1 1 TRFCSelect NO Not complete 0 YES Command execution is completed 1 BLKGE Block Gap Event 2 1 BLKGESelect NO No Block Gap Event 0 STOP Transaction stopped at block gap 1 DMAINT DMA Interrupt 3 1 DMAINTSelect NO No DMA Interrupt 0 YES DMA Interrupt is generated 1 BWRRDY Buffer Write Ready 4 1 BWRRDYSelect NO Not ready to write buffer 0 YES Ready to write buffer 1 BRDRDY Buffer Read Ready 5 1 BRDRDYSelect NO Not ready to read buffer 0 YES Ready to read buffer 1 BOOTAR Boot Acknowledge Received 14 1 ERRINT Error Interrupt 15 1 ERRINTSelect NO No Error 0 YES Error 1 EISTR Error Interrupt Status 0x32 16 0x0000 CMDTEO Command Timeout Error 0 1 CMDTEOSelect NO No Error 0 YES Timeout 1 CMDCRC Command CRC Error 1 1 CMDCRCSelect NO No Error 0 YES CRC Error Generated 1 CMDEND Command End Bit Error 2 1 CMDENDSelect NO No error 0 YES End Bit Error Generated 1 CMDIDX Command Index Error 3 1 CMDIDXSelect NO No Error 0 YES Error 1 DATTEO Data Timeout Error 4 1 DATTEOSelect NO No Error 0 YES Timeout 1 DATCRC Data CRC Error 5 1 DATCRCSelect NO No Error 0 YES Error 1 DATEND Data End Bit Error 6 1 DATENDSelect NO No Error 0 YES Error 1 CURLIM Current Limit Error 7 1 CURLIMSelect NO No Error 0 YES Power Fail 1 ACMD Auto CMD Error 8 1 ACMDSelect NO No Error 0 YES Error 1 ADMA ADMA Error 9 1 ADMASelect NO No Error 0 YES Error 1 EISTR_EMMC_MODE Error Interrupt Status EISTR 0x32 16 0x0000 CMDTEO Command Timeout Error 0 1 CMDTEOSelect NO No Error 0 YES Timeout 1 CMDCRC Command CRC Error 1 1 CMDCRCSelect NO No Error 0 YES CRC Error Generated 1 CMDEND Command End Bit Error 2 1 CMDENDSelect NO No error 0 YES End Bit Error Generated 1 CMDIDX Command Index Error 3 1 CMDIDXSelect NO No Error 0 YES Error 1 DATTEO Data Timeout Error 4 1 DATTEOSelect NO No Error 0 YES Timeout 1 DATCRC Data CRC Error 5 1 DATCRCSelect NO No Error 0 YES Error 1 DATEND Data End Bit Error 6 1 DATENDSelect NO No Error 0 YES Error 1 CURLIM Current Limit Error 7 1 CURLIMSelect NO No Error 0 YES Power Fail 1 ACMD Auto CMD Error 8 1 ACMDSelect NO No Error 0 YES Error 1 ADMA ADMA Error 9 1 ADMASelect NO No Error 0 YES Error 1 BOOTAE Boot Acknowledge Error 12 1 BOOTAESelect 0 FIFO contains at least one byte 0 1 FIFO is empty 1 NISTER Normal Interrupt Status Enable 0x34 16 0x0000 CMDC Command Complete Status Enable 0 1 CMDCSelect MASKED Masked 0 ENABLED Enabled 1 TRFC Transfer Complete Status Enable 1 1 TRFCSelect MASKED Masked 0 ENABLED Enabled 1 BLKGE Block Gap Event Status Enable 2 1 BLKGESelect MASKED Masked 0 ENABLED Enabled 1 DMAINT DMA Interrupt Status Enable 3 1 DMAINTSelect MASKED Masked 0 ENABLED Enabled 1 BWRRDY Buffer Write Ready Status Enable 4 1 BWRRDYSelect MASKED Masked 0 ENABLED Enabled 1 BRDRDY Buffer Read Ready Status Enable 5 1 BRDRDYSelect MASKED Masked 0 ENABLED Enabled 1 CINS Card Insertion Status Enable 6 1 CINSSelect MASKED Masked 0 ENABLED Enabled 1 CREM Card Removal Status Enable 7 1 CREMSelect MASKED Masked 0 ENABLED Enabled 1 CINT Card Interrupt Status Enable 8 1 CINTSelect MASKED Masked 0 ENABLED Enabled 1 NISTER_EMMC_MODE Normal Interrupt Status Enable NISTER 0x34 16 0x0000 CMDC Command Complete Status Enable 0 1 CMDCSelect MASKED Masked 0 ENABLED Enabled 1 TRFC Transfer Complete Status Enable 1 1 TRFCSelect MASKED Masked 0 ENABLED Enabled 1 BLKGE Block Gap Event Status Enable 2 1 BLKGESelect MASKED Masked 0 ENABLED Enabled 1 DMAINT DMA Interrupt Status Enable 3 1 DMAINTSelect MASKED Masked 0 ENABLED Enabled 1 BWRRDY Buffer Write Ready Status Enable 4 1 BWRRDYSelect MASKED Masked 0 ENABLED Enabled 1 BRDRDY Buffer Read Ready Status Enable 5 1 BRDRDYSelect MASKED Masked 0 ENABLED Enabled 1 BOOTAR Boot Acknowledge Received Status Enable 14 1 EISTER Error Interrupt Status Enable 0x36 16 0x0000 CMDTEO Command Timeout Error Status Enable 0 1 CMDTEOSelect MASKED Masked 0 ENABLED Enabled 1 CMDCRC Command CRC Error Status Enable 1 1 CMDCRCSelect MASKED Masked 0 ENABLED Enabled 1 CMDEND Command End Bit Error Status Enable 2 1 CMDENDSelect MASKED Masked 0 ENABLED Enabled 1 CMDIDX Command Index Error Status Enable 3 1 CMDIDXSelect MASKED Masked 0 ENABLED Enabled 1 DATTEO Data Timeout Error Status Enable 4 1 DATTEOSelect MASKED Masked 0 ENABLED Enabled 1 DATCRC Data CRC Error Status Enable 5 1 DATCRCSelect MASKED Masked 0 ENABLED Enabled 1 DATEND Data End Bit Error Status Enable 6 1 DATENDSelect MASKED Masked 0 ENABLED Enabled 1 CURLIM Current Limit Error Status Enable 7 1 CURLIMSelect MASKED Masked 0 ENABLED Enabled 1 ACMD Auto CMD Error Status Enable 8 1 ACMDSelect MASKED Masked 0 ENABLED Enabled 1 ADMA ADMA Error Status Enable 9 1 ADMASelect MASKED Masked 0 ENABLED Enabled 1 EISTER_EMMC_MODE Error Interrupt Status Enable EISTER 0x36 16 0x0000 CMDTEO Command Timeout Error Status Enable 0 1 CMDTEOSelect MASKED Masked 0 ENABLED Enabled 1 CMDCRC Command CRC Error Status Enable 1 1 CMDCRCSelect MASKED Masked 0 ENABLED Enabled 1 CMDEND Command End Bit Error Status Enable 2 1 CMDENDSelect MASKED Masked 0 ENABLED Enabled 1 CMDIDX Command Index Error Status Enable 3 1 CMDIDXSelect MASKED Masked 0 ENABLED Enabled 1 DATTEO Data Timeout Error Status Enable 4 1 DATTEOSelect MASKED Masked 0 ENABLED Enabled 1 DATCRC Data CRC Error Status Enable 5 1 DATCRCSelect MASKED Masked 0 ENABLED Enabled 1 DATEND Data End Bit Error Status Enable 6 1 DATENDSelect MASKED Masked 0 ENABLED Enabled 1 CURLIM Current Limit Error Status Enable 7 1 CURLIMSelect MASKED Masked 0 ENABLED Enabled 1 ACMD Auto CMD Error Status Enable 8 1 ACMDSelect MASKED Masked 0 ENABLED Enabled 1 ADMA ADMA Error Status Enable 9 1 ADMASelect MASKED Masked 0 ENABLED Enabled 1 BOOTAE Boot Acknowledge Error Status Enable 12 1 NISIER Normal Interrupt Signal Enable 0x38 16 0x0000 CMDC Command Complete Signal Enable 0 1 CMDCSelect MASKED Masked 0 ENABLED Enabled 1 TRFC Transfer Complete Signal Enable 1 1 TRFCSelect MASKED Masked 0 ENABLED Enabled 1 BLKGE Block Gap Event Signal Enable 2 1 BLKGESelect MASKED Masked 0 ENABLED Enabled 1 DMAINT DMA Interrupt Signal Enable 3 1 DMAINTSelect MASKED Masked 0 ENABLED Enabled 1 BWRRDY Buffer Write Ready Signal Enable 4 1 BWRRDYSelect MASKED Masked 0 ENABLED Enabled 1 BRDRDY Buffer Read Ready Signal Enable 5 1 BRDRDYSelect MASKED Masked 0 ENABLED Enabled 1 CINS Card Insertion Signal Enable 6 1 CINSSelect MASKED Masked 0 ENABLED Enabled 1 CREM Card Removal Signal Enable 7 1 CREMSelect MASKED Masked 0 ENABLED Enabled 1 CINT Card Interrupt Signal Enable 8 1 CINTSelect MASKED Masked 0 ENABLED Enabled 1 NISIER_EMMC_MODE Normal Interrupt Signal Enable NISIER 0x38 16 0x0000 CMDC Command Complete Signal Enable 0 1 CMDCSelect MASKED Masked 0 ENABLED Enabled 1 TRFC Transfer Complete Signal Enable 1 1 TRFCSelect MASKED Masked 0 ENABLED Enabled 1 BLKGE Block Gap Event Signal Enable 2 1 BLKGESelect MASKED Masked 0 ENABLED Enabled 1 DMAINT DMA Interrupt Signal Enable 3 1 DMAINTSelect MASKED Masked 0 ENABLED Enabled 1 BWRRDY Buffer Write Ready Signal Enable 4 1 BWRRDYSelect MASKED Masked 0 ENABLED Enabled 1 BRDRDY Buffer Read Ready Signal Enable 5 1 BRDRDYSelect MASKED Masked 0 ENABLED Enabled 1 BOOTAR Boot Acknowledge Received Signal Enable 14 1 EISIER Error Interrupt Signal Enable 0x3A 16 0x0000 CMDTEO Command Timeout Error Signal Enable 0 1 CMDTEOSelect MASKED Masked 0 ENABLED Enabled 1 CMDCRC Command CRC Error Signal Enable 1 1 CMDCRCSelect MASKED Masked 0 ENABLED Enabled 1 CMDEND Command End Bit Error Signal Enable 2 1 CMDENDSelect MASKED Masked 0 ENABLED Enabled 1 CMDIDX Command Index Error Signal Enable 3 1 CMDIDXSelect MASKED Masked 0 ENABLED Enabled 1 DATTEO Data Timeout Error Signal Enable 4 1 DATTEOSelect MASKED Masked 0 ENABLED Enabled 1 DATCRC Data CRC Error Signal Enable 5 1 DATCRCSelect MASKED Masked 0 ENABLED Enabled 1 DATEND Data End Bit Error Signal Enable 6 1 DATENDSelect MASKED Masked 0 ENABLED Enabled 1 CURLIM Current Limit Error Signal Enable 7 1 CURLIMSelect MASKED Masked 0 ENABLED Enabled 1 ACMD Auto CMD Error Signal Enable 8 1 ACMDSelect MASKED Masked 0 ENABLED Enabled 1 ADMA ADMA Error Signal Enable 9 1 ADMASelect MASKED Masked 0 ENABLED Enabled 1 EISIER_EMMC_MODE Error Interrupt Signal Enable EISIER 0x3A 16 0x0000 CMDTEO Command Timeout Error Signal Enable 0 1 CMDTEOSelect MASKED Masked 0 ENABLED Enabled 1 CMDCRC Command CRC Error Signal Enable 1 1 CMDCRCSelect MASKED Masked 0 ENABLED Enabled 1 CMDEND Command End Bit Error Signal Enable 2 1 CMDENDSelect MASKED Masked 0 ENABLED Enabled 1 CMDIDX Command Index Error Signal Enable 3 1 CMDIDXSelect MASKED Masked 0 ENABLED Enabled 1 DATTEO Data Timeout Error Signal Enable 4 1 DATTEOSelect MASKED Masked 0 ENABLED Enabled 1 DATCRC Data CRC Error Signal Enable 5 1 DATCRCSelect MASKED Masked 0 ENABLED Enabled 1 DATEND Data End Bit Error Signal Enable 6 1 DATENDSelect MASKED Masked 0 ENABLED Enabled 1 CURLIM Current Limit Error Signal Enable 7 1 CURLIMSelect MASKED Masked 0 ENABLED Enabled 1 ACMD Auto CMD Error Signal Enable 8 1 ACMDSelect MASKED Masked 0 ENABLED Enabled 1 ADMA ADMA Error Signal Enable 9 1 ADMASelect MASKED Masked 0 ENABLED Enabled 1 BOOTAE Boot Acknowledge Error Signal Enable 12 1 ACESR Auto CMD Error Status 0x3C 16 read-only 0x0000 ACMD12NE Auto CMD12 Not Executed 0 1 ACMD12NESelect EXEC Executed 0 NOT_EXEC Not executed 1 ACMDTEO Auto CMD Timeout Error 1 1 ACMDTEOSelect NO No error 0 YES Timeout 1 ACMDCRC Auto CMD CRC Error 2 1 ACMDCRCSelect NO No error 0 YES CRC Error Generated 1 ACMDEND Auto CMD End Bit Error 3 1 ACMDENDSelect NO No error 0 YES End Bit Error Generated 1 ACMDIDX Auto CMD Index Error 4 1 ACMDIDXSelect NO No error 0 YES Error 1 CMDNI Command not Issued By Auto CMD12 Error 7 1 CMDNISelect OK No error 0 NOT_ISSUED Not Issued 1 HC2R Host Control 2 0x3E 16 0x0000 UHSMS UHS Mode Select 0 3 UHSMSSelect SDR12 SDR12 0 SDR25 SDR25 1 SDR50 SDR50 2 SDR104 SDR104 3 DDR50 DDR50 4 VS18EN 1.8V Signaling Enable 3 1 VS18ENSelect S33V 3.3V Signaling 0 S18V 1.8V Signaling 1 DRVSEL Driver Strength Select 4 2 DRVSELSelect B Driver Type B is Selected (Default) 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 EXTUN Execute Tuning 6 1 EXTUNSelect NO Not Tuned or Tuning Completed 0 REQUESTED Execute Tuning 1 SLCKSEL Sampling Clock Select 7 1 SLCKSELSelect FIXED Fixed clock is used to sample data 0 TUNED Tuned clock is used to sample data 1 ASINTEN Asynchronous Interrupt Enable 14 1 ASINTENSelect DISABLED Disabled 0 ENABLED Enabled 1 PVALEN Preset Value Enable 15 1 PVALENSelect HOST SDCLK and Driver Strength are controlled by Host Controller 0 AUTO Automatic Selection by Preset Value is Enabled 1 HC2R_EMMC_MODE Host Control 2 HC2R 0x3E 16 0x0000 HS200EN HS200 Mode Enable 0 4 HS200ENSelect SDR12 SDR12 0 SDR25 SDR25 1 SDR50 SDR50 2 SDR104 SDR104 3 DDR50 DDR50 4 DRVSEL Driver Strength Select 4 2 DRVSELSelect B Driver Type B is Selected (Default) 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 EXTUN Execute Tuning 6 1 EXTUNSelect NO Not Tuned or Tuning Completed 0 REQUESTED Execute Tuning 1 SLCKSEL Sampling Clock Select 7 1 SLCKSELSelect FIXED Fixed clock is used to sample data 0 TUNED Tuned clock is used to sample data 1 PVALEN Preset Value Enable 15 1 PVALENSelect HOST SDCLK and Driver Strength are controlled by Host Controller 0 AUTO Automatic Selection by Preset Value is Enabled 1 CA0R Capabilities 0 0x40 32 read-only 0x27E80080 TEOCLKF Timeout Clock Frequency 0 6 TEOCLKFSelect OTHER Get information via another method 0 TEOCLKU Timeout Clock Unit 7 1 TEOCLKUSelect KHZ KHz 0 MHZ MHz 1 BASECLKF Base Clock Frequency 8 8 BASECLKFSelect OTHER Get information via another method 0 MAXBLKL Max Block Length 16 2 MAXBLKLSelect 512 512 bytes 0 1024 1024 bytes 1 2048 2048 bytes 2 ED8SUP 8-bit Support for Embedded Device 18 1 ED8SUPSelect NO 8-bit Bus Width not Supported 0 YES 8-bit Bus Width Supported 1 ADMA2SUP ADMA2 Support 19 1 ADMA2SUPSelect NO ADMA2 not Supported 0 YES ADMA2 Supported 1 HSSUP High Speed Support 21 1 HSSUPSelect NO High Speed not Supported 0 YES High Speed Supported 1 SDMASUP SDMA Support 22 1 SDMASUPSelect NO SDMA not Supported 0 YES SDMA Supported 1 SRSUP Suspend/Resume Support 23 1 SRSUPSelect NO Suspend/Resume not Supported 0 YES Suspend/Resume Supported 1 V33VSUP Voltage Support 3.3V 24 1 V33VSUPSelect NO 3.3V Not Supported 0 YES 3.3V Supported 1 V30VSUP Voltage Support 3.0V 25 1 V30VSUPSelect NO 3.0V Not Supported 0 YES 3.0V Supported 1 V18VSUP Voltage Support 1.8V 26 1 V18VSUPSelect NO 1.8V Not Supported 0 YES 1.8V Supported 1 SB64SUP 64-Bit System Bus Support 28 1 SB64SUPSelect NO 32-bit Address Descriptors and System Bus 0 YES 64-bit Address Descriptors and System Bus 1 ASINTSUP Asynchronous Interrupt Support 29 1 ASINTSUPSelect NO Asynchronous Interrupt not Supported 0 YES Asynchronous Interrupt supported 1 SLTYPE Slot Type 30 2 SLTYPESelect REMOVABLE Removable Card Slot 0 EMBEDDED Embedded Slot for One Device 1 CA1R Capabilities 1 0x44 32 read-only 0x00000070 SDR50SUP SDR50 Support 0 1 SDR50SUPSelect NO SDR50 is Not Supported 0 YES SDR50 is Supported 1 SDR104SUP SDR104 Support 1 1 SDR104SUPSelect NO SDR104 is Not Supported 0 YES SDR104 is Supported 1 DDR50SUP DDR50 Support 2 1 DDR50SUPSelect NO DDR50 is Not Supported 0 YES DDR50 is Supported 1 DRVASUP Driver Type A Support 4 1 DRVASUPSelect NO Driver Type A is Not Supported 0 YES Driver Type A is Supported 1 DRVCSUP Driver Type C Support 5 1 DRVCSUPSelect NO Driver Type C is Not Supported 0 YES Driver Type C is Supported 1 DRVDSUP Driver Type D Support 6 1 DRVDSUPSelect NO Driver Type D is Not Supported 0 YES Driver Type D is Supported 1 TCNTRT Timer Count for Re-Tuning 8 4 TCNTRTSelect DISABLED Re-Tuning Timer disabled 0 1S 1 second 1 2S 2 seconds 2 4S 4 seconds 3 8S 8 seconds 4 16S 16 seconds 5 32S 32 seconds 6 64S 64 seconds 7 128S 128 seconds 8 256S 256 seconds 9 512S 512 seconds 10 1024S 1024 seconds 11 OTHER Get information from other source 15 TSDR50 Use Tuning for SDR50 13 1 TSDR50Select NO SDR50 does not require tuning 0 YES SDR50 requires tuning 1 CLKMULT Clock Multiplier 16 8 CLKMULTSelect NO Clock Multiplier is Not Supported 0 MCCAR Maximum Current Capabilities 0x48 32 read-only 0x00000000 MAXCUR33V Maximum Current for 3.3V 0 8 MAXCUR33VSelect OTHER Get information via another method 0 4MA 4mA 1 8MA 8mA 2 12MA 12mA 3 MAXCUR30V Maximum Current for 3.0V 8 8 MAXCUR30VSelect OTHER Get information via another method 0 4MA 4mA 1 8MA 8mA 2 12MA 12mA 3 MAXCUR18V Maximum Current for 1.8V 16 8 MAXCUR18VSelect OTHER Get information via another method 0 4MA 4mA 1 8MA 8mA 2 12MA 12mA 3 FERACES Force Event for Auto CMD Error Status 0x50 16 write-only 0x0000 ACMD12NE Force Event for Auto CMD12 Not Executed 0 1 ACMD12NESelect NO No Interrupt 0 YES Interrupt is generated 1 ACMDTEO Force Event for Auto CMD Timeout Error 1 1 ACMDTEOSelect NO No Interrupt 0 YES Interrupt is generated 1 ACMDCRC Force Event for Auto CMD CRC Error 2 1 ACMDCRCSelect NO No Interrupt 0 YES Interrupt is generated 1 ACMDEND Force Event for Auto CMD End Bit Error 3 1 ACMDENDSelect NO No Interrupt 0 YES Interrupt is generated 1 ACMDIDX Force Event for Auto CMD Index Error 4 1 ACMDIDXSelect NO No Interrupt 0 YES Interrupt is generated 1 CMDNI Force Event for Command Not Issued By Auto CMD12 Error 7 1 CMDNISelect NO No Interrupt 0 YES Interrupt is generated 1 FEREIS Force Event for Error Interrupt Status 0x52 16 write-only 0x0000 CMDTEO Force Event for Command Timeout Error 0 1 CMDTEOSelect NO No Interrupt 0 YES Interrupt is generated 1 CMDCRC Force Event for Command CRC Error 1 1 CMDCRCSelect NO No Interrupt 0 YES Interrupt is generated 1 CMDEND Force Event for Command End Bit Error 2 1 CMDENDSelect NO No Interrupt 0 YES Interrupt is generated 1 CMDIDX Force Event for Command Index Error 3 1 CMDIDXSelect NO No Interrupt 0 YES Interrupt is generated 1 DATTEO Force Event for Data Timeout Error 4 1 DATTEOSelect NO No Interrupt 0 YES Interrupt is generated 1 DATCRC Force Event for Data CRC Error 5 1 DATCRCSelect NO No Interrupt 0 YES Interrupt is generated 1 DATEND Force Event for Data End Bit Error 6 1 DATENDSelect NO No Interrupt 0 YES Interrupt is generated 1 CURLIM Force Event for Current Limit Error 7 1 CURLIMSelect NO No Interrupt 0 YES Interrupt is generated 1 ACMD Force Event for Auto CMD Error 8 1 ACMDSelect NO No Interrupt 0 YES Interrupt is generated 1 ADMA Force Event for ADMA Error 9 1 ADMASelect NO No Interrupt 0 YES Interrupt is generated 1 BOOTAE Force Event for Boot Acknowledge Error 12 1 BOOTAESelect NO No Interrupt 0 YES Interrupt is generated 1 AESR ADMA Error Status 0x54 8 read-only 0x00 ERRST ADMA Error State 0 2 ERRSTSelect STOP ST_STOP (Stop DMA) 0 FDS ST_FDS (Fetch Descriptor) 1 TFR ST_TFR (Transfer Data) 3 LMIS ADMA Length Mismatch Error 2 1 LMISSelect NO No Error 0 YES Error 1 1 4 ASAR[%s] ADMA System Address n 0x58 32 0x00000000 ADMASA ADMA System Address 0 32 8 2 PVR[%s] Preset Value n 0x60 16 0x0000 SDCLKFSEL SDCLK Frequency Select Value for Initialization 0 10 CLKGSEL Clock Generator Select Value for Initialization 10 1 CLKGSELSelect DIV Host Controller Ver2.00 Compatible Clock Generator (Divider) 0 PROG Programmable Clock Generator 1 DRVSEL Driver Strength Select Value for Initialization 14 2 DRVSELSelect B Driver Type B is Selected 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 SISR Slot Interrupt Status 0xFC 16 read-only 0x20000 INTSSL Interrupt Signal for Each Slot 0 1 HCVR Host Controller Version 0xFE 16 read-only 0x1802 SVER Spec Version 0 8 VVER Vendor Version 8 8 MC1R MMC Control 1 0x204 8 0x00 CMDTYP e.MMC Command Type 0 2 CMDTYPSelect NORMAL Not a MMC specific command 0 WAITIRQ Wait IRQ Command 1 STREAM Stream Command 2 BOOT Boot Command 3 DDR e.MMC HSDDR Mode 3 1 OPD e.MMC Open Drain Mode 4 1 BOOTA e.MMC Boot Acknowledge Enable 5 1 RSTN e.MMC Reset Signal 6 1 FCD e.MMC Force Card Detect 7 1 MC2R MMC Control 2 0x205 8 write-only 0x00 SRESP e.MMC Abort Wait IRQ 0 1 ABOOT e.MMC Abort Boot 1 1 ACR AHB Control 0x208 32 0x00000000 BMAX AHB Maximum Burst 0 2 BMAXSelect INCR16 0 INCR8 1 INCR4 2 SINGLE 3 CC2R Clock Control 2 0x20C 32 0x00000000 FSDCLKD Force SDCK Disabled 0 1 FSDCLKDSelect NOEFFECT No effect 0 DISABLE SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled 1 CACR Capabilities Control 0x230 32 0x00000000 CAPWREN Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) 0 1 KEY Key (0x46) 8 8 DBGR Debug 0x234 8 0x00 NIDBG Non-intrusive debug enable 0 1 NIDBGSelect IDBG Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer) 0 NIDBG Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer) 1 SERCOM0 U22015.0.0 Serial Communication Interface SERCOM SERCOM_ 0x40003000 0 0x31 registers SERCOM0_0 46 SERCOM0_1 47 SERCOM0_2 48 SERCOM0_OTHER 49 I2CM I2C Master Mode SercomI2cm 0x0 CTRLA I2CM Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 RUNSTDBY Run in Standby 7 1 PINOUT Pin Usage 16 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0x0 75NS 50-100ns hold time 0x1 450NS 300-600ns hold time 0x2 600NS 400-800ns hold time 0x3 MEXTTOEN Master SCL Low Extend Timeout 22 1 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0x0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 0x1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 0x2 SCLSM SCL Clock Stretch Mode 27 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0x0 55US 5-6 SCL Time-Out(50-60us) 0x1 105US 10-11 SCL Time-Out(100-110us) 0x2 205US 20-21 SCL Time-Out(200-210us) 0x3 LOWTOUTEN SCL Low Timeout Enable 30 1 CTRLB I2CM Control B 0x4 32 0x00000000 SMEN Smart Mode Enable 8 1 QCEN Quick Command Enable 9 1 CMD Command 16 2 ACKACT Acknowledge Action 18 1 CTRLC I2CM Control C 0x8 32 0x00000000 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Data transaction from/to DATA register are 8-bit 0x0 DATA_TRANS_32BIT Data transaction from/to DATA register are 32-bit 0x1 BAUD I2CM Baud Rate 0xC 32 0x00000000 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 INTENCLR I2CM Interrupt Enable Clear 0x14 8 0x00 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET I2CM Interrupt Enable Set 0x16 8 0x00 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG I2CM Interrupt Flag Status and Clear 0x18 8 0x00 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 ERROR Combined Error Interrupt 7 1 STATUS I2CM Status 0x1A 16 0x0000 BUSERR Bus Error 0 1 ARBLOST Arbitration Lost 1 1 RXNACK Received Not Acknowledge 2 1 BUSSTATE Bus State 4 2 LOWTOUT SCL Low Timeout 6 1 CLKHOLD Clock Hold 7 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 LENERR Length Error 10 1 SYNCBUSY I2CM Synchronization Busy 0x1C 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE SERCOM Enable Synchronization Busy 1 1 SYSOP System Operation Synchronization Busy 2 1 LENGTH Length Synchronization Busy 4 1 ADDR I2CM Address 0x24 32 0x00000000 ADDR Address Value 0 11 LENEN Length Enable 13 1 HS High Speed Mode 14 1 TENBITEN Ten Bit Addressing Enable 15 1 LEN Length 16 8 DATA I2CM Data 0x28 8 0x00 DATA Data Value 0 8 DBGCTRL I2CM Debug Control 0x30 8 0x00 DBGSTOP Debug Mode 0 1 I2CS I2C Slave Mode I2CM SercomI2cs 0x0 CTRLA I2CS Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 RUNSTDBY Run during Standby 7 1 PINOUT Pin Usage 16 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0x0 75NS 50-100ns hold time 0x1 450NS 300-600ns hold time 0x2 600NS 400-800ns hold time 0x3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0x0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 0x1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 0x2 SCLSM SCL Clock Stretch Mode 27 1 LOWTOUTEN SCL Low Timeout Enable 30 1 CTRLB I2CS Control B 0x4 32 0x00000000 SMEN Smart Mode Enable 8 1 GCMD PMBus Group Command 9 1 AACKEN Automatic Address Acknowledge 10 1 AMODE Address Mode 14 2 CMD Command 16 2 ACKACT Acknowledge Action 18 1 CTRLC I2CS Control C 0x8 32 0x00000000 SDASETUP SDA Setup Time 0 4 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Data transaction from/to DATA register are 8-bit 0x0 DATA_TRANS_32BIT Data transaction from/to DATA register are 32-bit 0x1 INTENCLR I2CS Interrupt Enable Clear 0x14 8 0x00 PREC Stop Received Interrupt Disable 0 1 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET I2CS Interrupt Enable Set 0x16 8 0x00 PREC Stop Received Interrupt Enable 0 1 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG I2CS Interrupt Flag Status and Clear 0x18 8 0x00 PREC Stop Received Interrupt 0 1 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 STATUS I2CS Status 0x1A 16 0x0000 BUSERR Bus Error 0 1 COLL Transmit Collision 1 1 RXNACK Received Not Acknowledge 2 1 DIR Read/Write Direction 3 1 SR Repeated Start 4 1 LOWTOUT SCL Low Timeout 6 1 CLKHOLD Clock Hold 7 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 HS High Speed 10 1 LENERR Transaction Length Error 11 1 SYNCBUSY I2CS Synchronization Busy 0x1C 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH Length Synchronization Busy 4 1 LENGTH I2CS Length 0x22 16 0x0000 LEN Data Length 0 8 LENEN Data Length Enable 8 1 ADDR I2CS Address 0x24 32 0x00000000 GENCEN General Call Address Enable 0 1 ADDR Address Value 1 10 TENBITEN Ten Bit Addressing Enable 15 1 ADDRMASK Address Mask 17 10 DATA I2CS Data 0x28 32 0x00000000 DATA Data Value 0 32 SPIS SPI Slave Mode I2CM SercomSpis 0x0 CTRLA SPIS Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 RUNSTDBY Run during Standby 7 1 IBON Immediate Buffer Overflow Notification 8 1 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0x0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 0x2 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0x0 PAD1 SERCOM PAD[1] is used as data input 0x1 PAD2 SERCOM PAD[2] is used as data input 0x2 PAD3 SERCOM PAD[3] is used as data input 0x3 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0x0 SPI_FRAME_WITH_ADDR SPI Frame with Addr 0x2 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0x0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW SCK is low when idle 0x0 IDLE_HIGH SCK is high when idle 0x1 DORD Data Order 30 1 DORDSelect MSB MSB is transferred first 0x0 LSB LSB is transferred first 0x1 CTRLB SPIS Control B 0x4 32 0x00000000 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 bits 0x0 9_BIT 9 bits 0x1 PLOADEN Data Preload Enable 6 1 SSDE Slave Select Low Detect Enable 9 1 MSSEN Master Slave Select Enable 13 1 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0x0 2_ADDRESSES Two unique Addressess 0x1 RANGE Address Range 0x2 RXEN Receiver Enable 17 1 CTRLC SPIS Control C 0x8 32 0x00000000 ICSPACE Inter-Character Spacing 0 6 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0x0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 0x1 BAUD SPIS Baud Rate 0xC 8 0x00 BAUD Baud Rate Value 0 8 INTENCLR SPIS Interrupt Enable Clear 0x14 8 0x00 DRE Data Register Empty Interrupt Disable 0 1 TXC Transmit Complete Interrupt Disable 1 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET SPIS Interrupt Enable Set 0x16 8 0x00 DRE Data Register Empty Interrupt Enable 0 1 TXC Transmit Complete Interrupt Enable 1 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG SPIS Interrupt Flag Status and Clear 0x18 8 0x00 DRE Data Register Empty Interrupt 0 1 TXC Transmit Complete Interrupt 1 1 RXC Receive Complete Interrupt 2 1 SSL Slave Select Low Interrupt Flag 3 1 ERROR Combined Error Interrupt 7 1 STATUS SPIS Status 0x1A 16 0x0000 BUFOVF Buffer Overflow 2 1 LENERR Transaction Length Error 11 1 SYNCBUSY SPIS Synchronization Busy 0x1C 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE SERCOM Enable Synchronization Busy 1 1 CTRLB CTRLB Synchronization Busy 2 1 LENGTH LENGTH Synchronization Busy 4 1 LENGTH SPIS Length 0x22 16 0x0000 LEN Data Length 0 8 LENEN Data Length Enable 8 1 ADDR SPIS Address 0x24 32 0x00000000 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 DATA SPIS Data 0x28 32 0x00000000 DATA Data Value 0 32 DBGCTRL SPIS Debug Control 0x30 8 0x00 DBGSTOP Debug Mode 0 1 SPIM SPI Master Mode I2CM SercomSpim 0x0 CTRLA SPIM Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 RUNSTDBY Run during Standby 7 1 IBON Immediate Buffer Overflow Notification 8 1 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0x0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 0x2 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0x0 PAD1 SERCOM PAD[1] is used as data input 0x1 PAD2 SERCOM PAD[2] is used as data input 0x2 PAD3 SERCOM PAD[3] is used as data input 0x3 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0x0 SPI_FRAME_WITH_ADDR SPI Frame with Addr 0x2 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0x0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW SCK is low when idle 0x0 IDLE_HIGH SCK is high when idle 0x1 DORD Data Order 30 1 DORDSelect MSB MSB is transferred first 0x0 LSB LSB is transferred first 0x1 CTRLB SPIM Control B 0x4 32 0x00000000 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 bits 0x0 9_BIT 9 bits 0x1 PLOADEN Data Preload Enable 6 1 SSDE Slave Select Low Detect Enable 9 1 MSSEN Master Slave Select Enable 13 1 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0x0 2_ADDRESSES Two unique Addressess 0x1 RANGE Address Range 0x2 RXEN Receiver Enable 17 1 CTRLC SPIM Control C 0x8 32 0x00000000 ICSPACE Inter-Character Spacing 0 6 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0x0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 0x1 BAUD SPIM Baud Rate 0xC 8 0x00 BAUD Baud Rate Value 0 8 INTENCLR SPIM Interrupt Enable Clear 0x14 8 0x00 DRE Data Register Empty Interrupt Disable 0 1 TXC Transmit Complete Interrupt Disable 1 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET SPIM Interrupt Enable Set 0x16 8 0x00 DRE Data Register Empty Interrupt Enable 0 1 TXC Transmit Complete Interrupt Enable 1 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG SPIM Interrupt Flag Status and Clear 0x18 8 0x00 DRE Data Register Empty Interrupt 0 1 TXC Transmit Complete Interrupt 1 1 RXC Receive Complete Interrupt 2 1 SSL Slave Select Low Interrupt Flag 3 1 ERROR Combined Error Interrupt 7 1 STATUS SPIM Status 0x1A 16 0x0000 BUFOVF Buffer Overflow 2 1 LENERR Transaction Length Error 11 1 SYNCBUSY SPIM Synchronization Busy 0x1C 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE SERCOM Enable Synchronization Busy 1 1 CTRLB CTRLB Synchronization Busy 2 1 LENGTH LENGTH Synchronization Busy 4 1 LENGTH SPIM Length 0x22 16 0x0000 LEN Data Length 0 8 LENEN Data Length Enable 8 1 ADDR SPIM Address 0x24 32 0x00000000 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 DATA SPIM Data 0x28 32 0x00000000 DATA Data Value 0 32 DBGCTRL SPIM Debug Control 0x30 8 0x00 DBGSTOP Debug Mode 0 1 USART_EXT USART EXTERNAL CLOCK Mode I2CM SercomUsart_ext 0x0 CTRLA USART_EXT Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 RUNSTDBY Run during Standby 7 1 IBON Immediate Buffer Overflow Notification 8 1 TXINV Transmit Data Invert 9 1 RXINV Receive Data Invert 10 1 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0x0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 0x1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 0x2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 0x3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 0x4 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 SERCOM PAD[0] is used for data transmission 0x0 PAD3 SERCOM_PAD[0] is used for data transmission 0x3 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0x0 PAD1 SERCOM PAD[1] is used for data reception 0x1 PAD2 SERCOM PAD[2] is used for data reception 0x2 PAD3 SERCOM PAD[3] is used for data reception 0x3 SAMPA Sample Adjustment 22 2 FORM Frame Format 24 4 FORMSelect USART_FRAME_NO_PARITY USART frame 0x0 USART_FRAME_WITH_PARITY USART frame with parity 0x1 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 0x2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud - break detection and auto-baud 0x4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 0x5 USART_FRAME_ISO_7816 ISO 7816 0x7 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0x0 SYNC Synchronous Communication 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0x0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 0x1 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0x0 LSB LSB is transmitted first 0x1 CTRLB USART_EXT Control B 0x4 32 0x00000000 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0x0 9_BIT 9 Bits 0x1 5_BIT 5 Bits 0x5 6_BIT 6 Bits 0x6 7_BIT 7 Bits 0x7 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0x0 2_BIT Two Stop Bits 0x1 COLDEN Collision Detection Enable 8 1 SFDE Start of Frame Detection Enable 9 1 ENC Encoding Format 10 1 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 TXEN Transmitter Enable 16 1 RXEN Receiver Enable 17 1 LINCMD LIN Command 24 2 CTRLC USART_EXT Control C 0x8 32 0x00000000 GTIME Guard Time 0 3 BRKLEN LIN Master Break Length 8 2 HDRDLY LIN Master Header Delay 10 2 INACK Inhibit Not Acknowledge 16 1 DSNACK Disable Successive NACK 17 1 MAXITER Maximum Iterations 20 3 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0x0 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 0x1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 0x2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 0x3 BAUD USART_EXT Baud Rate 0xC 16 0x0000 BAUD Baud Rate Value 0 16 BAUD_FRAC_MODE USART_EXT Baud Rate BAUD 0xC 16 0x0000 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRACFP_MODE USART_EXT Baud Rate BAUD 0xC 16 0x0000 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART_EXT Baud Rate BAUD 0xC 16 0x0000 BAUD Baud Rate Value 0 16 RXPL USART_EXT Receive Pulse Length 0xE 8 0x00 RXPL Receive Pulse Length 0 8 INTENCLR USART_EXT Interrupt Enable Clear 0x14 8 0x00 DRE Data Register Empty Interrupt Disable 0 1 TXC Transmit Complete Interrupt Disable 1 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 RXBRK Break Received Interrupt Disable 5 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET USART_EXT Interrupt Enable Set 0x16 8 0x00 DRE Data Register Empty Interrupt Enable 0 1 TXC Transmit Complete Interrupt Enable 1 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 RXBRK Break Received Interrupt Enable 5 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG USART_EXT Interrupt Flag Status and Clear 0x18 8 0x00 DRE Data Register Empty Interrupt 0 1 TXC Transmit Complete Interrupt 1 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 CTSIC Clear To Send Input Change Interrupt 4 1 RXBRK Break Received Interrupt 5 1 ERROR Combined Error Interrupt 7 1 STATUS USART_EXT Status 0x1A 16 0x0000 PERR Parity Error 0 1 FERR Frame Error 1 1 BUFOVF Buffer Overflow 2 1 CTS Clear To Send 3 1 ISF Inconsistent Sync Field 4 1 COLL Collision Detected 5 1 TXE Transmitter Empty 6 1 ITER Maximum Number of Repetitions Reached 7 1 SYNCBUSY USART_EXT Synchronization Busy 0x1C 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE SERCOM Enable Synchronization Busy 1 1 CTRLB CTRLB Synchronization Busy 2 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT USART_EXT Receive Error Count 0x20 8 read-only 0x00 LENGTH USART_EXT Length 0x22 16 0x0000 LEN Data Length 0 8 LENEN Data Length Enable 8 2 DATA USART_EXT Data 0x28 32 0x00000000 DATA Data Value 0 32 DBGCTRL USART_EXT Debug Control 0x30 8 0x00 DBGSTOP Debug Mode 0 1 USART_INT USART INTERNAL CLOCK Mode I2CM SercomUsart_int 0x0 CTRLA USART_INT Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 RUNSTDBY Run during Standby 7 1 IBON Immediate Buffer Overflow Notification 8 1 TXINV Transmit Data Invert 9 1 RXINV Receive Data Invert 10 1 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0x0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 0x1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 0x2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 0x3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 0x4 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 SERCOM PAD[0] is used for data transmission 0x0 PAD3 SERCOM_PAD[0] is used for data transmission 0x3 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0x0 PAD1 SERCOM PAD[1] is used for data reception 0x1 PAD2 SERCOM PAD[2] is used for data reception 0x2 PAD3 SERCOM PAD[3] is used for data reception 0x3 SAMPA Sample Adjustment 22 2 FORM Frame Format 24 4 FORMSelect USART_FRAME_NO_PARITY USART frame 0x0 USART_FRAME_WITH_PARITY USART frame with parity 0x1 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 0x2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud - break detection and auto-baud 0x4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 0x5 USART_FRAME_ISO_7816 ISO 7816 0x7 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0x0 SYNC Synchronous Communication 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0x0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 0x1 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0x0 LSB LSB is transmitted first 0x1 CTRLB USART_INT Control B 0x4 32 0x00000000 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0x0 9_BIT 9 Bits 0x1 5_BIT 5 Bits 0x5 6_BIT 6 Bits 0x6 7_BIT 7 Bits 0x7 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0x0 2_BIT Two Stop Bits 0x1 COLDEN Collision Detection Enable 8 1 SFDE Start of Frame Detection Enable 9 1 ENC Encoding Format 10 1 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 TXEN Transmitter Enable 16 1 RXEN Receiver Enable 17 1 LINCMD LIN Command 24 2 CTRLC USART_INT Control C 0x8 32 0x00000000 GTIME Guard Time 0 3 BRKLEN LIN Master Break Length 8 2 HDRDLY LIN Master Header Delay 10 2 INACK Inhibit Not Acknowledge 16 1 DSNACK Disable Successive NACK 17 1 MAXITER Maximum Iterations 20 3 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0x0 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 0x1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 0x2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 0x3 BAUD USART_INT Baud Rate 0xC 16 0x0000 BAUD Baud Rate Value 0 16 BAUD_FRAC_MODE USART_INT Baud Rate BAUD 0xC 16 0x0000 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRACFP_MODE USART_INT Baud Rate BAUD 0xC 16 0x0000 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART_INT Baud Rate BAUD 0xC 16 0x0000 BAUD Baud Rate Value 0 16 RXPL USART_INT Receive Pulse Length 0xE 8 0x00 RXPL Receive Pulse Length 0 8 INTENCLR USART_INT Interrupt Enable Clear 0x14 8 0x00 DRE Data Register Empty Interrupt Disable 0 1 TXC Transmit Complete Interrupt Disable 1 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 RXBRK Break Received Interrupt Disable 5 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET USART_INT Interrupt Enable Set 0x16 8 0x00 DRE Data Register Empty Interrupt Enable 0 1 TXC Transmit Complete Interrupt Enable 1 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 RXBRK Break Received Interrupt Enable 5 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG USART_INT Interrupt Flag Status and Clear 0x18 8 0x00 DRE Data Register Empty Interrupt 0 1 TXC Transmit Complete Interrupt 1 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 CTSIC Clear To Send Input Change Interrupt 4 1 RXBRK Break Received Interrupt 5 1 ERROR Combined Error Interrupt 7 1 STATUS USART_INT Status 0x1A 16 0x0000 PERR Parity Error 0 1 FERR Frame Error 1 1 BUFOVF Buffer Overflow 2 1 CTS Clear To Send 3 1 ISF Inconsistent Sync Field 4 1 COLL Collision Detected 5 1 TXE Transmitter Empty 6 1 ITER Maximum Number of Repetitions Reached 7 1 SYNCBUSY USART_INT Synchronization Busy 0x1C 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE SERCOM Enable Synchronization Busy 1 1 CTRLB CTRLB Synchronization Busy 2 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT USART_INT Receive Error Count 0x20 8 read-only 0x00 LENGTH USART_INT Length 0x22 16 0x0000 LEN Data Length 0 8 LENEN Data Length Enable 8 2 DATA USART_INT Data 0x28 32 0x00000000 DATA Data Value 0 32 DBGCTRL USART_INT Debug Control 0x30 8 0x00 DBGSTOP Debug Mode 0 1 SERCOM1 0x40003400 SERCOM1_0 50 SERCOM1_1 51 SERCOM1_2 52 SERCOM1_OTHER 53 SERCOM2 0x41012000 SERCOM2_0 54 SERCOM2_1 55 SERCOM2_2 56 SERCOM2_OTHER 57 SERCOM3 0x41014000 SERCOM3_0 58 SERCOM3_1 59 SERCOM3_2 60 SERCOM3_OTHER 61 SERCOM4 0x43000000 SERCOM4_0 62 SERCOM4_1 63 SERCOM4_2 64 SERCOM4_OTHER 65 SERCOM5 0x43000400 SERCOM5_0 66 SERCOM5_1 67 SERCOM5_2 68 SERCOM5_OTHER 69 SUPC U24071.1.0 Supply Controller SUPC SUPC_ 0x40001800 0 0x2C registers SUPC_OTHER 8 SUPC_BODDET 9 INTENCLR Interrupt Enable Clear 0x0 32 0x00000000 BOD33RDY BOD33 Ready 0 1 BOD33DET BOD33 Detection 1 1 B33SRDY BOD33 Synchronization Ready 2 1 VREGRDY Voltage Regulator Ready 8 1 VCORERDY VDDCORE Ready 10 1 INTENSET Interrupt Enable Set 0x4 32 0x00000000 BOD33RDY BOD33 Ready 0 1 BOD33DET BOD33 Detection 1 1 B33SRDY BOD33 Synchronization Ready 2 1 VREGRDY Voltage Regulator Ready 8 1 VCORERDY VDDCORE Ready 10 1 INTFLAG Interrupt Flag Status and Clear 0x8 32 0x00000000 BOD33RDY BOD33 Ready 0 1 BOD33DET BOD33 Detection 1 1 B33SRDY BOD33 Synchronization Ready 2 1 VREGRDY Voltage Regulator Ready 8 1 VCORERDY VDDCORE Ready 10 1 STATUS Power and Clocks Status 0xC 32 read-only 0x00000000 BOD33RDY BOD33 Ready 0 1 BOD33DET BOD33 Detection 1 1 B33SRDY BOD33 Synchronization Ready 2 1 VREGRDY Voltage Regulator Ready 8 1 VCORERDY VDDCORE Ready 10 1 BOD33 BOD33 Control 0x10 32 0x00000000 ENABLE Enable 1 1 ACTION Action when Threshold Crossed 2 2 ACTIONSelect NONE No action 0x0 RESET The BOD33 generates a reset 0x1 INT The BOD33 generates an interrupt 0x2 BKUP The BOD33 puts the device in backup sleep mode 0x3 STDBYCFG Configuration in Standby mode 4 1 RUNSTDBY Run in Standby mode 5 1 RUNHIB Run in Hibernate mode 6 1 RUNBKUP Run in Backup mode 7 1 HYST Hysteresis value 8 4 PSEL Prescaler Select 12 3 PSELSelect NODIV Not divided 0x0 DIV4 Divide clock by 4 0x1 DIV8 Divide clock by 8 0x2 DIV16 Divide clock by 16 0x3 DIV32 Divide clock by 32 0x4 DIV64 Divide clock by 64 0x5 DIV128 Divide clock by 128 0x6 DIV256 Divide clock by 256 0x7 LEVEL Threshold Level for VDD 16 8 VBATLEVEL Threshold Level in battery backup sleep mode for VBAT 24 8 VREG VREG Control 0x18 32 0x00000002 ENABLE Enable 1 1 SEL Voltage Regulator Selection 2 1 SELSelect LDO LDO selection 0x0 BUCK Buck selection 0x1 RUNBKUP Run in Backup mode 7 1 VSEN Voltage Scaling Enable 16 1 VSPER Voltage Scaling Period 24 3 VREF VREF Control 0x1C 32 0x00000000 TSEN Temperature Sensor Output Enable 1 1 VREFOE Voltage Reference Output Enable 2 1 TSSEL Temperature Sensor Selection 3 1 RUNSTDBY Run during Standby 6 1 ONDEMAND On Demand Contrl 7 1 SEL Voltage Reference Selection 16 4 SELSelect 1V0 1.0V voltage reference typical value 0x0 1V1 1.1V voltage reference typical value 0x1 1V2 1.2V voltage reference typical value 0x2 1V25 1.25V voltage reference typical value 0x3 2V0 2.0V voltage reference typical value 0x4 2V2 2.2V voltage reference typical value 0x5 2V4 2.4V voltage reference typical value 0x6 2V5 2.5V voltage reference typical value 0x7 BBPS Battery Backup Power Switch 0x20 32 0x00000000 CONF Battery Backup Configuration 0 1 CONFSelect BOD33 The power switch is handled by the BOD33 0x0 FORCED In Backup Domain, the backup domain is always supplied by battery backup power 0x1 WAKEEN Wake Enable 2 1 BKOUT Backup Output Control 0x24 32 0x00000000 ENOUT0 Enable OUT0 0 1 ENOUT1 Enable OUT1 1 1 CLROUT0 Clear OUT0 8 1 CLROUT1 Clear OUT1 9 1 SETOUT0 Set OUT0 16 1 SETOUT1 Set OUT1 17 1 RTCTGLOUT0 RTC Toggle OUT0 24 1 RTCTGLOUT1 RTC Toggle OUT1 25 1 BKIN Backup Input Control 0x28 32 read-only 0x00000000 BKIN0 Backup Input 0 0 1 BKIN1 Backup Input 1 1 1 TC0 U22493.0.0 Basic Timer Counter TC TC_ 0x40003800 0 0x38 registers TC0 107 COUNT8 8-bit Counter Mode TcCount8 0x0 CTRLA Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CTRLBCLR Control B Clear 0x4 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 CTRLBSET Control B Set 0x5 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 EVCTRL Event Control 0x6 16 0x0000 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 TCINV TC Event Input Polarity 4 1 TCEI TC Event Enable 5 1 OVFEO Event Output Enable 8 1 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 INTENCLR Interrupt Enable Clear 0x8 8 0x00 OVF OVF Interrupt Disable 0 1 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 INTENSET Interrupt Enable Set 0x9 8 0x00 OVF OVF Interrupt Enable 0 1 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 0x00 OVF OVF Interrupt Flag 0 1 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 STATUS Status 0xB 8 0x01 STOP Stop Status Flag 0 1 SLAVE Slave Status Flag 1 1 PERBUFV Synchronization Busy Status 3 1 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 WAVE Waveform Generation Control 0xC 8 0x00 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 DRVCTRL Control C 0xD 8 0x00 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 DBGCTRL Debug Control 0xF 8 0x00 DBGRUN Run During Debug 0 1 SYNCBUSY Synchronization Status 0x10 32 read-only 0x00000000 SWRST swrst 0 1 ENABLE enable 1 1 CTRLB CTRLB 2 1 STATUS STATUS 3 1 COUNT Counter 4 1 PER Period 5 1 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT COUNT8 Count 0x14 8 0x00 COUNT Counter Value 0 8 PER COUNT8 Period 0x1B 8 0xFF PER Period Value 0 8 2 1 CC[%s] COUNT8 Compare and Capture 0x1C 8 0x00 CC Counter/Compare Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 0xFF PERBUF Period Buffer Value 0 8 2 1 CCBUF[%s] COUNT8 Compare and Capture Buffer 0x30 8 0x00 CCBUF Counter/Compare Buffer Value 0 8 COUNT16 16-bit Counter Mode COUNT8 TcCount16 0x0 CTRLA Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CTRLBCLR Control B Clear 0x4 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 CTRLBSET Control B Set 0x5 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 EVCTRL Event Control 0x6 16 0x0000 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 TCINV TC Event Input Polarity 4 1 TCEI TC Event Enable 5 1 OVFEO Event Output Enable 8 1 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 INTENCLR Interrupt Enable Clear 0x8 8 0x00 OVF OVF Interrupt Disable 0 1 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 INTENSET Interrupt Enable Set 0x9 8 0x00 OVF OVF Interrupt Enable 0 1 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 0x00 OVF OVF Interrupt Flag 0 1 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 STATUS Status 0xB 8 0x01 STOP Stop Status Flag 0 1 SLAVE Slave Status Flag 1 1 PERBUFV Synchronization Busy Status 3 1 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 WAVE Waveform Generation Control 0xC 8 0x00 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 DRVCTRL Control C 0xD 8 0x00 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 DBGCTRL Debug Control 0xF 8 0x00 DBGRUN Run During Debug 0 1 SYNCBUSY Synchronization Status 0x10 32 read-only 0x00000000 SWRST swrst 0 1 ENABLE enable 1 1 CTRLB CTRLB 2 1 STATUS STATUS 3 1 COUNT Counter 4 1 PER Period 5 1 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT COUNT16 Count 0x14 16 0x0000 COUNT Counter Value 0 16 2 2 CC[%s] COUNT16 Compare and Capture 0x1C 16 0x0000 CC Counter/Compare Value 0 16 2 2 CCBUF[%s] COUNT16 Compare and Capture Buffer 0x30 16 0x0000 CCBUF Counter/Compare Buffer Value 0 16 COUNT32 32-bit Counter Mode COUNT8 TcCount32 0x0 CTRLA Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CTRLBCLR Control B Clear 0x4 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 CTRLBSET Control B Set 0x5 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 EVCTRL Event Control 0x6 16 0x0000 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 TCINV TC Event Input Polarity 4 1 TCEI TC Event Enable 5 1 OVFEO Event Output Enable 8 1 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 INTENCLR Interrupt Enable Clear 0x8 8 0x00 OVF OVF Interrupt Disable 0 1 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 INTENSET Interrupt Enable Set 0x9 8 0x00 OVF OVF Interrupt Enable 0 1 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 0x00 OVF OVF Interrupt Flag 0 1 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 STATUS Status 0xB 8 0x01 STOP Stop Status Flag 0 1 SLAVE Slave Status Flag 1 1 PERBUFV Synchronization Busy Status 3 1 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 WAVE Waveform Generation Control 0xC 8 0x00 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 DRVCTRL Control C 0xD 8 0x00 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 DBGCTRL Debug Control 0xF 8 0x00 DBGRUN Run During Debug 0 1 SYNCBUSY Synchronization Status 0x10 32 read-only 0x00000000 SWRST swrst 0 1 ENABLE enable 1 1 CTRLB CTRLB 2 1 STATUS STATUS 3 1 COUNT Counter 4 1 PER Period 5 1 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT COUNT32 Count 0x14 32 0x00000000 COUNT Counter Value 0 32 2 4 CC[%s] COUNT32 Compare and Capture 0x1C 32 0x00000000 CC Counter/Compare Value 0 32 2 4 CCBUF[%s] COUNT32 Compare and Capture Buffer 0x30 32 0x00000000 CCBUF Counter/Compare Buffer Value 0 32 TC1 0x40003C00 TC1 108 TC2 0x4101A000 TC2 109 TC3 0x4101C000 TC3 110 TC4 0x42001400 TC4 111 TC5 0x42001800 TC5 112 TCC0 U22133.1.0 Timer Counter Control TCC TCC_ 0x41016000 0 0x88 registers TCC0_OTHER 85 TCC0_MC0 86 TCC0_MC1 87 TCC0_MC2 88 TCC0_MC3 89 TCC0_MC4 90 TCC0_MC5 91 CTRLA Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0 DITH4 Dithering is done every 16 PWM frames 1 DITH5 Dithering is done every 32 PWM frames 2 DITH6 Dithering is done every 64 PWM frames 3 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0 DIV2 Divide by 2 1 DIV4 Divide by 4 2 DIV8 Divide by 8 3 DIV16 Divide by 16 4 DIV64 Divide by 64 5 DIV256 Divide by 256 6 DIV1024 Divide by 1024 7 RUNSTDBY Run in Standby 11 1 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0 PRESC Reload or reset counter on next prescaler clock 1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 2 ALOCK Auto Lock 14 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 DMAOS DMA One-shot Trigger Mode 23 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 CPTEN4 Capture Channel 4 Enable 28 1 CPTEN5 Capture Channel 5 Enable 29 1 CTRLBCLR Control B Clear 0x4 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 CTRLBSET Control B Set 0x5 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 SYNCBUSY Synchronization Busy 0x8 32 read-only 0x00000000 SWRST Swrst Busy 0 1 ENABLE Enable Busy 1 1 CTRLB Ctrlb Busy 2 1 STATUS Status Busy 3 1 COUNT Count Busy 4 1 PATT Pattern Busy 5 1 WAVE Wave Busy 6 1 PER Period Busy 7 1 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 CC4 Compare Channel 4 Busy 12 1 CC5 Compare Channel 5 Busy 13 1 FCTRLA Recoverable Fault A Configuration 0xC 32 0x00000000 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 RESTART Fault A Restart 7 1 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 FILTERVAL Fault A Filter Value 24 4 FCTRLB Recoverable Fault B Configuration 0x10 32 0x00000000 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 RESTART Fault B Restart 7 1 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 FILTERVAL Fault B Filter Value 24 4 WEXCTRL Waveform Extension Configuration 0x14 32 0x00000000 OTMX Output Matrix 0 2 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 DTHS Dead-time High Side Outputs Value 24 8 DRVCTRL Driver Control 0x18 32 0x00000000 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 DBGCTRL Debug Control 0x1E 8 0x00 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 EVCTRL Event Control 0x20 32 0x00000000 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0 RETRIGGER Start, restart or re-trigger counter on event 1 COUNTEV Count on event 2 START Start counter on event 3 INC Increment counter on event 4 COUNT Count on active state of asynchronous event 5 STAMP Stamp capture 6 FAULT Non-recoverable fault 7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0 RETRIGGER Re-trigger counter on event 1 DIR Direction control 2 STOP Stop counter on event 3 DEC Decrement counter on event 4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 6 FAULT Non-recoverable fault 7 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0 END An interrupt/event is generated when a counter cycle ends 1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 3 OVFEO Overflow/Underflow Output Event Enable 8 1 TRGEO Retrigger Output Event Enable 9 1 CNTEO Timer/counter Output Event Enable 10 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEI4 Match or Capture Channel 4 Event Input Enable 20 1 MCEI5 Match or Capture Channel 5 Event Input Enable 21 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 MCEO4 Match or Capture Channel 4 Event Output Enable 28 1 MCEO5 Match or Capture Channel 5 Event Output Enable 29 1 INTENCLR Interrupt Enable Clear 0x24 32 0x00000000 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 CNT Counter Interrupt Enable 2 1 ERR Error Interrupt Enable 3 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 INTENSET Interrupt Enable Set 0x28 32 0x00000000 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 CNT Counter Interrupt Enable 2 1 ERR Error Interrupt Enable 3 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 INTFLAG Interrupt Flag Status and Clear 0x2C 32 0x00000000 OVF Overflow 0 1 TRG Retrigger 1 1 CNT Counter 2 1 ERR Error 3 1 UFS Non-Recoverable Update Fault 10 1 DFS Non-Recoverable Debug Fault 11 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 MC4 Match or Capture 4 20 1 MC5 Match or Capture 5 21 1 STATUS Status 0x30 32 0x00000001 STOP Stop 0 1 IDX Ramp 1 1 UFS Non-recoverable Update Fault State 2 1 DFS Non-Recoverable Debug Fault State 3 1 SLAVE Slave 4 1 PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 FAULTAIN Recoverable Fault A Input 8 1 FAULTBIN Recoverable Fault B Input 9 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 FAULTA Recoverable Fault A State 12 1 FAULTB Recoverable Fault B State 13 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT1 Non-Recoverable Fault 1 State 15 1 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CCBUFV4 Compare Channel 4 Buffer Valid 20 1 CCBUFV5 Compare Channel 5 Buffer Valid 21 1 CMP0 Compare Channel 0 Value 24 1 CMP1 Compare Channel 1 Value 25 1 CMP2 Compare Channel 2 Value 26 1 CMP3 Compare Channel 3 Value 27 1 CMP4 Compare Channel 4 Value 28 1 CMP5 Compare Channel 5 Value 29 1 COUNT Count 0x34 32 0x00000000 COUNT Counter Value 0 24 COUNT_DITH4_MODE Count COUNT 0x34 32 0x00000000 COUNT Counter Value 4 20 COUNT_DITH5_MODE Count COUNT 0x34 32 0x00000000 COUNT Counter Value 5 19 COUNT_DITH6_MODE Count COUNT 0x34 32 0x00000000 COUNT Counter Value 6 18 PATT Pattern 0x38 16 0x0000 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 WAVE Waveform Control 0x3C 32 0x00000000 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 DSCRITICAL Dual-slope critical 4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 7 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0 RAMP2A Alternative RAMP2 operation 1 RAMP2 RAMP2 operation 2 RAMP2C Critical RAMP2 operation 3 CIPEREN Circular period Enable 7 1 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 POL4 Channel 4 Polarity 20 1 POL5 Channel 5 Polarity 21 1 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 PER Period 0x40 32 0xFFFFFFFF PER Period Value 0 24 PER_DITH4_MODE Period PER 0x40 32 0xFFFFFFFF DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 PER_DITH5_MODE Period PER 0x40 32 0xFFFFFFFF DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 PER_DITH6_MODE Period PER 0x40 32 0xFFFFFFFF DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 6 4 CC[%s] Compare and Capture 0x44 32 0x00000000 CC Channel Compare/Capture Value 0 24 6 4 CC_DITH4_MODE[%s] Compare and Capture CC[%s] 0x44 32 0x00000000 DITHER Dithering Cycle Number 0 4 CC Channel Compare/Capture Value 4 20 6 4 CC_DITH5_MODE[%s] Compare and Capture CC[%s] 0x44 32 0x00000000 DITHER Dithering Cycle Number 0 5 CC Channel Compare/Capture Value 5 19 6 4 CC_DITH6_MODE[%s] Compare and Capture CC[%s] 0x44 32 0x00000000 DITHER Dithering Cycle Number 0 6 CC Channel Compare/Capture Value 6 18 PATTBUF Pattern Buffer 0x64 16 0x0000 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 PERBUF Period Buffer 0x6C 32 0xFFFFFFFF PERBUF Period Buffer Value 0 24 PERBUF_DITH4_MODE Period Buffer PERBUF 0x6C 32 0xFFFFFFFF DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 PERBUF_DITH5_MODE Period Buffer PERBUF 0x6C 32 0xFFFFFFFF DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 PERBUF_DITH6_MODE Period Buffer PERBUF 0x6C 32 0xFFFFFFFF DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 6 4 CCBUF[%s] Compare and Capture Buffer 0x70 32 0x00000000 CCBUF Channel Compare/Capture Buffer Value 0 24 6 4 CCBUF_DITH4_MODE[%s] Compare and Capture Buffer CCBUF[%s] 0x70 32 0x00000000 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 6 4 CCBUF_DITH5_MODE[%s] Compare and Capture Buffer CCBUF[%s] 0x70 32 0x00000000 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF Channel Compare/Capture Buffer Value 5 19 6 4 CCBUF_DITH6_MODE[%s] Compare and Capture Buffer CCBUF[%s] 0x70 32 0x00000000 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF Channel Compare/Capture Buffer Value 6 18 TCC1 0x41018000 TCC1_OTHER 92 TCC1_MC0 93 TCC1_MC1 94 TCC1_MC2 95 TCC1_MC3 96 TCC2 0x42000C00 TCC2_OTHER 97 TCC2_MC0 98 TCC2_MC1 99 TCC2_MC2 100 TCC3 0x42001000 TCC3_OTHER 101 TCC3_MC0 102 TCC3_MC1 103 TCC4 0x43001000 TCC4_OTHER 104 TCC4_MC0 105 TCC4_MC1 106 TRNG U22421.1.0 True Random Generator TRNG TRNG_ 0x42002800 0 0x24 registers TRNG 131 CTRLA Control A 0x0 8 0x00 ENABLE Enable 1 1 RUNSTDBY Run in Standby 6 1 EVCTRL Event Control 0x4 8 0x00 DATARDYEO Data Ready Event Output 0 1 INTENCLR Interrupt Enable Clear 0x8 8 0x00 DATARDY Data Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x9 8 0x00 DATARDY Data Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 0x00 DATARDY Data Ready Interrupt Flag 0 1 DATA Output Data 0x20 32 read-only 0x00000000 DATA Output Data 0 32 USB U22221.2.0 Universal Serial Bus USB USB_ 0x41000000 0 0x200 registers USB_OTHER 80 USB_SOF_HSOF 81 USB_TRCPT0 82 USB_TRCPT1 83 DEVICE USB is Device UsbDevice 0x0 CTRLA Control A 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 RUNSTDBY Run in Standby Mode 2 1 MODE Operating Mode 7 1 MODESelect DEVICE Device Mode 0 HOST Host Mode 1 SYNCBUSY Synchronization Busy 0x2 8 read-only 0x00 SWRST Software Reset Synchronization Busy 0 1 ENABLE Enable Synchronization Busy 1 1 QOSCTRL USB Quality Of Service 0x3 8 0x0F CQOS Configuration Quality of Service 0 2 DQOS Data Quality of Service 2 2 CTRLB DEVICE Control B 0x8 16 0x0001 DETACH Detach 0 1 UPRSM Upstream Resume 1 1 SPDCONF Speed Configuration 2 2 SPDCONFSelect FS FS : Full Speed 0x0 LS LS : Low Speed 0x1 HS HS : High Speed capable 0x2 HSTM HSTM: High Speed Test Mode (force high-speed mode for test mode) 0x3 NREPLY No Reply 4 1 TSTJ Test mode J 5 1 TSTK Test mode K 6 1 TSTPCKT Test packet mode 7 1 OPMODE2 Specific Operational Mode 8 1 GNAK Global NAK 9 1 LPMHDSK Link Power Management Handshake 10 2 LPMHDSKSelect NO No handshake. LPM is not supported 0 ACK ACK 1 NYET NYET 2 STALL STALL 3 DADD DEVICE Device Address 0xA 8 0x00 DADD Device Address 0 7 ADDEN Device Address Enable 7 1 STATUS DEVICE Status 0xC 8 read-only 0x40 SPEED Speed Status 2 2 SPEEDSelect FS Full-speed mode 0x0 LS Low-speed mode 0x1 HS High-speed mode 0x2 LINESTATE USB Line State Status 6 2 LINESTATESelect 0 SE0/RESET 0x0 1 FS-J or LS-K State 0x1 2 FS-K or LS-J State 0x2 FSMSTATUS Finite State Machine Status 0xD 8 read-only 0x01 FSMSTATE Fine State Machine Status 0 7 FSMSTATESelect OFF OFF (L3). It corresponds to the powered-off, disconnected, and disabled state 0x1 ON ON (L0). It corresponds to the Idle and Active states 0x2 SUSPEND SUSPEND (L2) 0x4 SLEEP SLEEP (L1) 0x8 DNRESUME DNRESUME. Down Stream Resume. 0x10 UPRESUME UPRESUME. Up Stream Resume. 0x20 RESET RESET. USB lines Reset. 0x40 FNUM DEVICE Device Frame Number 0x10 16 read-only 0x0000 MFNUM Micro Frame Number 0 3 FNUM Frame Number 3 11 FNCERR Frame Number CRC Error 15 1 INTENCLR DEVICE Device Interrupt Enable Clear 0x14 16 0x0000 SUSPEND Suspend Interrupt Enable 0 1 MSOF Micro Start of Frame Interrupt Enable in High Speed Mode 1 1 SOF Start Of Frame Interrupt Enable 2 1 EORST End of Reset Interrupt Enable 3 1 WAKEUP Wake Up Interrupt Enable 4 1 EORSM End Of Resume Interrupt Enable 5 1 UPRSM Upstream Resume Interrupt Enable 6 1 RAMACER Ram Access Interrupt Enable 7 1 LPMNYET Link Power Management Not Yet Interrupt Enable 8 1 LPMSUSP Link Power Management Suspend Interrupt Enable 9 1 INTENSET DEVICE Device Interrupt Enable Set 0x18 16 0x0000 SUSPEND Suspend Interrupt Enable 0 1 MSOF Micro Start of Frame Interrupt Enable in High Speed Mode 1 1 SOF Start Of Frame Interrupt Enable 2 1 EORST End of Reset Interrupt Enable 3 1 WAKEUP Wake Up Interrupt Enable 4 1 EORSM End Of Resume Interrupt Enable 5 1 UPRSM Upstream Resume Interrupt Enable 6 1 RAMACER Ram Access Interrupt Enable 7 1 LPMNYET Link Power Management Not Yet Interrupt Enable 8 1 LPMSUSP Link Power Management Suspend Interrupt Enable 9 1 INTFLAG DEVICE Device Interrupt Flag 0x1C 16 0x0000 SUSPEND Suspend 0 1 MSOF Micro Start of Frame in High Speed Mode 1 1 SOF Start Of Frame 2 1 EORST End of Reset 3 1 WAKEUP Wake Up 4 1 EORSM End Of Resume 5 1 UPRSM Upstream Resume 6 1 RAMACER Ram Access 7 1 LPMNYET Link Power Management Not Yet 8 1 LPMSUSP Link Power Management Suspend 9 1 EPINTSMRY DEVICE End Point Interrupt Summary 0x20 16 read-only 0x0000 EPINT0 End Point 0 Interrupt 0 1 EPINT1 End Point 1 Interrupt 1 1 EPINT2 End Point 2 Interrupt 2 1 EPINT3 End Point 3 Interrupt 3 1 EPINT4 End Point 4 Interrupt 4 1 EPINT5 End Point 5 Interrupt 5 1 EPINT6 End Point 6 Interrupt 6 1 EPINT7 End Point 7 Interrupt 7 1 DESCADD Descriptor Address 0x24 32 0x00000000 DESCADD Descriptor Address Value 0 32 PADCAL USB PAD Calibration 0x28 16 0x0000 TRANSP USB Pad Transp calibration 0 5 TRANSN USB Pad Transn calibration 6 5 TRIM USB Pad Trim calibration 12 3 8 0x20 DEVICE_ENDPOINT[%s] 0x100 EPCFG DEVICE_ENDPOINT End Point Configuration 0x0 8 0x00 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 EPSTATUSCLR DEVICE_ENDPOINT End Point Pipe Status Clear 0x4 8 write-only 0x00 DTGLOUT Data Toggle OUT Clear 0 1 DTGLIN Data Toggle IN Clear 1 1 CURBK Current Bank Clear 2 1 STALLRQ0 Stall 0 Request Clear 4 1 STALLRQ1 Stall 1 Request Clear 5 1 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 EPSTATUSSET DEVICE_ENDPOINT End Point Pipe Status Set 0x5 8 write-only 0x00 DTGLOUT Data Toggle OUT Set 0 1 DTGLIN Data Toggle IN Set 1 1 CURBK Current Bank Set 2 1 STALLRQ0 Stall 0 Request Set 4 1 STALLRQ1 Stall 1 Request Set 5 1 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 EPSTATUS DEVICE_ENDPOINT End Point Pipe Status 0x6 8 read-only 0x00 DTGLOUT Data Toggle Out 0 1 DTGLIN Data Toggle In 1 1 CURBK Current Bank 2 1 STALLRQ0 Stall 0 Request 4 1 STALLRQ1 Stall 1 Request 5 1 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 EPINTFLAG DEVICE_ENDPOINT End Point Interrupt Flag 0x7 8 0x00 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 EPINTENCLR DEVICE_ENDPOINT End Point Interrupt Clear Flag 0x8 8 0x00 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 EPINTENSET DEVICE_ENDPOINT End Point Interrupt Set Flag 0x9 8 0x00 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 HOST USB is Host DEVICE UsbHost 0x0 CTRLA Control A 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 RUNSTDBY Run in Standby Mode 2 1 MODE Operating Mode 7 1 MODESelect DEVICE Device Mode 0 HOST Host Mode 1 SYNCBUSY Synchronization Busy 0x2 8 read-only 0x00 SWRST Software Reset Synchronization Busy 0 1 ENABLE Enable Synchronization Busy 1 1 QOSCTRL USB Quality Of Service 0x3 8 0x0F CQOS Configuration Quality of Service 0 2 DQOS Data Quality of Service 2 2 CTRLB HOST Control B 0x8 16 0x0000 RESUME Send USB Resume 1 1 SPDCONF Speed Configuration for Host 2 2 SPDCONFSelect NORMAL Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. 0x0 FS Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. 0x3 AUTORESUME Auto Resume Enable 4 1 TSTJ Test mode J 5 1 TSTK Test mode K 6 1 SOFE Start of Frame Generation Enable 8 1 BUSRESET Send USB Reset 9 1 VBUSOK VBUS is OK 10 1 L1RESUME Send L1 Resume 11 1 HSOFC HOST Host Start Of Frame Control 0xA 8 0x00 FLENC Frame Length Control 0 4 FLENCE Frame Length Control Enable 7 1 STATUS HOST Status 0xC 8 0x00 SPEED Speed Status 2 2 LINESTATE USB Line State Status 6 2 FSMSTATUS Finite State Machine Status 0xD 8 read-only 0x01 FSMSTATE Fine State Machine Status 0 7 FSMSTATESelect OFF OFF (L3). It corresponds to the powered-off, disconnected, and disabled state 0x1 ON ON (L0). It corresponds to the Idle and Active states 0x2 SUSPEND SUSPEND (L2) 0x4 SLEEP SLEEP (L1) 0x8 DNRESUME DNRESUME. Down Stream Resume. 0x10 UPRESUME UPRESUME. Up Stream Resume. 0x20 RESET RESET. USB lines Reset. 0x40 FNUM HOST Host Frame Number 0x10 16 0x0000 MFNUM Micro Frame Number 0 3 FNUM Frame Number 3 11 FLENHIGH HOST Host Frame Length 0x12 8 read-only 0x00 FLENHIGH Frame Length 0 8 INTENCLR HOST Host Interrupt Enable Clear 0x14 16 0x0000 HSOF Host Start Of Frame Interrupt Disable 2 1 RST BUS Reset Interrupt Disable 3 1 WAKEUP Wake Up Interrupt Disable 4 1 DNRSM DownStream to Device Interrupt Disable 5 1 UPRSM Upstream Resume from Device Interrupt Disable 6 1 RAMACER Ram Access Interrupt Disable 7 1 DCONN Device Connection Interrupt Disable 8 1 DDISC Device Disconnection Interrupt Disable 9 1 INTENSET HOST Host Interrupt Enable Set 0x18 16 0x0000 HSOF Host Start Of Frame Interrupt Enable 2 1 RST Bus Reset Interrupt Enable 3 1 WAKEUP Wake Up Interrupt Enable 4 1 DNRSM DownStream to the Device Interrupt Enable 5 1 UPRSM Upstream Resume fromthe device Interrupt Enable 6 1 RAMACER Ram Access Interrupt Enable 7 1 DCONN Link Power Management Interrupt Enable 8 1 DDISC Device Disconnection Interrupt Enable 9 1 INTFLAG HOST Host Interrupt Flag 0x1C 16 0x0000 HSOF Host Start Of Frame 2 1 RST Bus Reset 3 1 WAKEUP Wake Up 4 1 DNRSM Downstream 5 1 UPRSM Upstream Resume from the Device 6 1 RAMACER Ram Access 7 1 DCONN Device Connection 8 1 DDISC Device Disconnection 9 1 PINTSMRY HOST Pipe Interrupt Summary 0x20 16 read-only 0x0000 EPINT0 Pipe 0 Interrupt 0 1 EPINT1 Pipe 1 Interrupt 1 1 EPINT2 Pipe 2 Interrupt 2 1 EPINT3 Pipe 3 Interrupt 3 1 EPINT4 Pipe 4 Interrupt 4 1 EPINT5 Pipe 5 Interrupt 5 1 EPINT6 Pipe 6 Interrupt 6 1 EPINT7 Pipe 7 Interrupt 7 1 DESCADD Descriptor Address 0x24 32 0x00000000 DESCADD Descriptor Address Value 0 32 PADCAL USB PAD Calibration 0x28 16 0x0000 TRANSP USB Pad Transp calibration 0 5 TRANSN USB Pad Transn calibration 6 5 TRIM USB Pad Trim calibration 12 3 8 0x20 HOST_PIPE[%s] 0x100 PCFG HOST_PIPE End Point Configuration 0x0 8 0x00 PTOKEN Pipe Token 0 2 BK Pipe Bank 2 1 PTYPE Pipe Type 3 3 BINTERVAL HOST_PIPE Bus Access Period of Pipe 0x3 8 0x00 BITINTERVAL Bit Interval 0 8 PSTATUSCLR HOST_PIPE End Point Pipe Status Clear 0x4 8 write-only 0x00 DTGL Data Toggle clear 0 1 CURBK Curren Bank clear 2 1 PFREEZE Pipe Freeze Clear 4 1 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 PSTATUSSET HOST_PIPE End Point Pipe Status Set 0x5 8 write-only 0x00 DTGL Data Toggle Set 0 1 CURBK Current Bank Set 2 1 PFREEZE Pipe Freeze Set 4 1 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 PSTATUS HOST_PIPE End Point Pipe Status 0x6 8 read-only 0x00 DTGL Data Toggle 0 1 CURBK Current Bank 2 1 PFREEZE Pipe Freeze 4 1 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 PINTFLAG HOST_PIPE Pipe Interrupt Flag 0x7 8 0x00 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 PERR Pipe Error Interrupt Flag 3 1 TXSTP Transmit Setup Interrupt Flag 4 1 STALL Stall Interrupt Flag 5 1 PINTENCLR HOST_PIPE Pipe Interrupt Flag Clear 0x8 8 0x00 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 PERR Pipe Error Interrupt Disable 3 1 TXSTP Transmit Setup Interrupt Disable 4 1 STALL Stall Inetrrupt Disable 5 1 PINTENSET HOST_PIPE Pipe Interrupt Flag Set 0x9 8 0x00 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 PERR Pipe Error Interrupt Enable 3 1 TXSTP Transmit Setup Interrupt Enable 4 1 STALL Stall Interrupt Enable 5 1 WDT U22511.1.0 Watchdog Timer WDT WDT_ 0x40002000 0 0xD registers WDT 10 CTRLA Control 0x0 8 0x00 ENABLE Enable 1 1 WEN Watchdog Timer Window Mode Enable 2 1 ALWAYSON Always-On 7 1 CONFIG Configuration 0x1 8 0xBB PER Time-Out Period 0 4 PERSelect CYC8 8 clock cycles 0x0 CYC16 16 clock cycles 0x1 CYC32 32 clock cycles 0x2 CYC64 64 clock cycles 0x3 CYC128 128 clock cycles 0x4 CYC256 256 clock cycles 0x5 CYC512 512 clock cycles 0x6 CYC1024 1024 clock cycles 0x7 CYC2048 2048 clock cycles 0x8 CYC4096 4096 clock cycles 0x9 CYC8192 8192 clock cycles 0xA CYC16384 16384 clock cycles 0xB WINDOW Window Mode Time-Out Period 4 4 WINDOWSelect CYC8 8 clock cycles 0x0 CYC16 16 clock cycles 0x1 CYC32 32 clock cycles 0x2 CYC64 64 clock cycles 0x3 CYC128 128 clock cycles 0x4 CYC256 256 clock cycles 0x5 CYC512 512 clock cycles 0x6 CYC1024 1024 clock cycles 0x7 CYC2048 2048 clock cycles 0x8 CYC4096 4096 clock cycles 0x9 CYC8192 8192 clock cycles 0xA CYC16384 16384 clock cycles 0xB EWCTRL Early Warning Interrupt Control 0x2 8 0x0B EWOFFSET Early Warning Interrupt Time Offset 0 4 EWOFFSETSelect CYC8 8 clock cycles 0x0 CYC16 16 clock cycles 0x1 CYC32 32 clock cycles 0x2 CYC64 64 clock cycles 0x3 CYC128 128 clock cycles 0x4 CYC256 256 clock cycles 0x5 CYC512 512 clock cycles 0x6 CYC1024 1024 clock cycles 0x7 CYC2048 2048 clock cycles 0x8 CYC4096 4096 clock cycles 0x9 CYC8192 8192 clock cycles 0xA CYC16384 16384 clock cycles 0xB INTENCLR Interrupt Enable Clear 0x4 8 0x00 EW Early Warning Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x5 8 0x00 EW Early Warning Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 0x00 EW Early Warning 0 1 SYNCBUSY Synchronization Busy 0x8 32 read-only 0x00000000 ENABLE Enable Synchronization Busy 1 1 WEN Window Enable Synchronization Busy 2 1 ALWAYSON Always-On Synchronization Busy 3 1 CLEAR Clear Synchronization Busy 4 1 CLEAR Clear 0xC 8 write-only 0x00 CLEAR Watchdog Clear 0 8 CLEARSelect KEY Clear Key 0xA5 CoreDebug Core Debug Register CoreDebug CoreDebug_ 0xE000EDF0 0 0x10 registers DHCSR Debug Halting Control and Status Register 0x0 32 C_DEBUGEN 0 1 C_HALT 1 1 C_STEP 2 1 C_MASKINTS 3 1 C_SNAPSTALL 5 1 S_REGRDY 16 1 read-only S_HALT 17 1 read-only S_SLEEP 18 1 read-only S_LOCKUP 19 1 read-only S_RETIRE_ST 24 1 read-only S_RESET_ST 25 1 read-only DBGKEY 16 16 write-only DCRSR Debug Core Register Selector Register 0x4 32 write-only REGSEL 0 5 REGWnR 16 1 DCRDR Debug Core Register Data Register 0x8 32 DEMCR Debug Exception and Monitor Control Register 0xC 32 VC_CORERESET 0 1 VC_MMERR 4 1 VC_NOCPERR 5 1 VC_CHKERR 6 1 VC_STATERR 7 1 VC_BUSERR 8 1 VC_INTERR 9 1 VC_HARDERR 10 1 MON_EN 16 1 MON_PEND 17 1 MON_STEP 18 1 MON_REQ 19 1 TRCENA 24 1 DWT Data Watchpoint and Trace Register DWT DWT_ 0xE0001000 0 0x5C registers CTRL Control Register 0x0 32 CYCCNTENA 0 1 POSTPRESET 1 4 POSTINIT 5 4 CYCTAP 9 1 SYNCTAP 10 2 PCSAMPLENA 12 1 EXCTRCENA 16 1 CPIEVTENA 17 1 EXCEVTENA 18 1 SLEEPEVTENA 19 1 LSUEVTENA 20 1 FOLDEVTENA 21 1 CYCEVTENA 22 1 NOPRFCNT 24 1 NOCYCCNT 25 1 NOEXTTRIG 26 1 NOTRCPKT 27 1 NUMCOMP 28 4 CYCCNT Cycle Count Register 0x4 32 CPICNT CPI Count Register 0x8 32 CPICNT 0 8 EXCCNT Exception Overhead Count Register 0xC 32 EXCCNT 0 8 SLEEPCNT Sleep Count Register 0x10 32 SLEEPCNT 0 8 LSUCNT LSU Count Register 0x14 32 LSUCNT 0 8 FOLDCNT Folded-instruction Count Register 0x18 32 FOLDCNT 0 8 PCSR Program Counter Sample Register 0x1C 32 read-only COMP0 Comparator Register 0 0x20 32 MASK0 Mask Register 0 0x24 32 MASK 0 5 FUNCTION0 Function Register 0 0x28 32 FUNCTION 0 4 EMITRANGE 5 1 CYCMATCH 7 1 DATAVMATCH 8 1 LNK1ENA 9 1 DATAVSIZE 10 2 DATAVADDR0 12 4 DATAVADDR1 16 4 MATCHED 24 1 COMP1 Comparator Register 1 0x30 32 MASK1 Mask Register 1 0x34 32 MASK 0 5 FUNCTION1 Function Register 1 0x38 32 FUNCTION 0 4 EMITRANGE 5 1 CYCMATCH 7 1 DATAVMATCH 8 1 LNK1ENA 9 1 DATAVSIZE 10 2 DATAVADDR0 12 4 DATAVADDR1 16 4 MATCHED 24 1 COMP2 Comparator Register 2 0x40 32 MASK2 Mask Register 2 0x44 32 MASK 0 5 FUNCTION2 Function Register 2 0x48 32 FUNCTION 0 4 EMITRANGE 5 1 CYCMATCH 7 1 DATAVMATCH 8 1 LNK1ENA 9 1 DATAVSIZE 10 2 DATAVADDR0 12 4 DATAVADDR1 16 4 MATCHED 24 1 COMP3 Comparator Register 3 0x50 32 MASK3 Mask Register 3 0x54 32 MASK 0 5 FUNCTION3 Function Register 3 0x58 32 FUNCTION 0 4 EMITRANGE 5 1 CYCMATCH 7 1 DATAVMATCH 8 1 LNK1ENA 9 1 DATAVSIZE 10 2 DATAVADDR0 12 4 DATAVADDR1 16 4 MATCHED 24 1 ETM Embedded Trace Macrocell ETM ETM_ 0xE0041000 0 0x1000 registers CR ETM Main Control Register 0x0 32 0x00000411 ETMPD ETM Power Down 0 1 PORTSIZE Port Size bits 2:0 4 3 STALL Stall Processor 7 1 BROUT Branch Output 8 1 DBGRQ Debug Request Control 9 1 PROG ETM Programming 10 1 PORTSEL ETM Port Select 11 1 PORTMODE2 Port Mode bit 2 13 1 PORTMODE Port Mode bits 1:0 16 2 PORTSIZE3 Port Size bit 3 21 1 TSEN TimeStamp Enable 28 1 CCR ETM Configuration Code Register 0x4 32 read-only 0x8C802000 TRIGGER ETM Trigger Event Register 0x8 32 SR ETM Status Register 0x10 32 SCR ETM System Configuration Register 0x14 32 read-only 0x00020D09 TEEVR ETM TraceEnable Event Register 0x20 32 TECR1 ETM TraceEnable Control 1 Register 0x24 32 FFLR ETM FIFO Full Level Register 0x28 32 CNTRLDVR1 ETM Free-running Counter Reload Value 0x140 32 SYNCFR ETM Synchronization Frequency Register 0x1E0 32 read-only 0x00000400 IDR ETM ID Register 0x1E4 32 read-only 0x4114F250 CCER ETM Configuration Code Extension Register 0x1E8 32 read-only 0x18541800 TESSEICR ETM TraceEnable Start/Stop EmbeddedICE Control Register 0x1F0 32 TSEVT ETM TimeStamp Event Register 0x1F8 32 TRACEIDR ETM CoreSight Trace ID Register 0x200 32 0x00000000 IDR2 ETM ID Register 2 0x208 32 read-only 0x00000000 PDSR ETM Device Power-Down Status Register 0x314 32 read-only 0x00000001 ITMISCIN ETM Integration Test Miscellaneous Inputs 0xEE0 32 read-only ITTRIGOUT ETM Integration Test Trigger Out 0xEE8 32 write-only ITATBCTR2 ETM Integration Test ATB Control 2 0xEF0 32 read-only ITATBCTR0 ETM Integration Test ATB Control 0 0xEF8 32 write-only ITCTRL ETM Integration Mode Control Register 0xF00 32 0x00000000 INTEGRATION 0 1 CLAIMSET ETM Claim Tag Set Register 0xFA0 32 CLAIMCLR ETM Claim Tag Clear Register 0xFA4 32 LAR ETM Lock Access Register 0xFB0 32 write-only LSR ETM Lock Status Register 0xFB4 32 read-only Present 0 1 Access 1 1 ByteAcc 2 1 AUTHSTATUS ETM Authentication Status Register 0xFB8 32 read-only DEVTYPE ETM CoreSight Device Type Register 0xFCC 32 read-only 0x00000013 PIDR4 ETM Peripheral Identification Register #4 0xFD0 32 read-only 0x00000004 PIDR5 ETM Peripheral Identification Register #5 0xFD4 32 read-only 0x00000000 PIDR6 ETM Peripheral Identification Register #6 0xFD8 32 read-only 0x00000000 PIDR7 ETM Peripheral Identification Register #7 0xFDC 32 read-only 0x00000000 PIDR0 ETM Peripheral Identification Register #0 0xFE0 32 read-only 0x00000025 PIDR1 ETM Peripheral Identification Register #1 0xFE4 32 read-only 0x000000B9 PIDR2 ETM Peripheral Identification Register #2 0xFE8 32 read-only 0x0000000B PIDR3 ETM Peripheral Identification Register #3 0xFEC 32 read-only 0x00000000 CIDR0 ETM Component Identification Register #0 0xFF0 32 read-only 0x0000000D CIDR1 ETM Component Identification Register #1 0xFF4 32 read-only 0x00000090 CIDR2 ETM Component Identification Register #2 0xFF8 32 read-only 0x00000005 CIDR3 ETM Component Identification Register #3 0xFFC 32 read-only 0x000000B1 FPU Floating Point Unit FPU FPU_ 0xE000EF30 0 0x18 registers FPCCR Floating-Point Context Control Register 0x4 32 0xC0000000 LSPACT 0 1 USER 1 1 THREAD 3 1 HFRDY 4 1 MMRDY 5 1 BFRDY 6 1 MONRDY 8 1 LSPEN 30 1 ASPEN 31 1 FPCAR Floating-Point Context Address Register 0x8 32 ADDRESS Address for FP registers in exception stack frame 3 29 FPDSCR Floating-Point Default Status Control Register 0xC 32 0x00000000 RMODE Default value for FPSCR.RMODE 22 2 RMODESelect RN Round to Nearest 0x0 RP Round towards Positive Infinity 0x1 RM Round towards Negative Infinity 0x2 RZ Round towards Zero 0x3 FZ Default value for FPSCR.FZ 24 1 DN Default value for FPSCR.DN 25 1 AHP Default value for FPSCR.AHP 26 1 MVFR0 Media and FP Feature Register 0 0x10 32 read-only A_SIMD_registers 0 4 Single_precision 4 4 Double_precision 8 4 FP_excep_trapping 12 4 Divide 16 4 Square_root 20 4 Short_vectors 24 4 FP_rounding_modes 28 4 MVFR1 Media and FP Feature Register 1 0x14 32 read-only FtZ_mode 0 4 D_NaN_mode 4 4 FP_HPFP 24 4 FP_fused_MAC 28 4 ITM Instrumentation Trace Macrocell ITM ITM_ 0xE0000000 0 0xF00 registers 32 4 PORT_WORD_MODE[%s] ITM Stimulus Port Registers 0x0 32 write-only PORT 0 32 32 4 PORT_BYTE_MODE[%s] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x0 32 write-only PORT 0 8 32 4 PORT_HWORD_MODE[%s] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x0 32 write-only PORT 0 16 TER ITM Trace Enable Register 0xE00 32 TPR ITM Trace Privilege Register 0xE40 32 PRIVMASK 0 4 TCR ITM Trace Control Register 0xE80 32 ITMENA 0 1 TSENA 1 1 SYNCENA 2 1 DWTENA 3 1 SWOENA 4 1 STALLENA 5 1 TSPrescale 8 2 GTSFREQ 10 2 TraceBusID 16 7 BUSY 23 1 IWR ITM Integration Write Register 0xEF8 32 write-only ATVALIDM 0 1 IRR ITM Integration Read Register 0xEFC 32 read-only ATREADYM 0 1 MPU Memory Protection Unit MPU MPU_ 0xE000ED90 0 0x2C registers TYPE MPU Type Register 0x0 32 read-only SEPARATE Separate instruction and Data Memory MapsRegions 0 1 DREGION Number of Data Regions 8 8 IREGION Number of Instruction Regions 16 8 CTRL MPU Control Register 0x4 32 ENABLE MPU Enable 0 1 HFNMIENA Enable Hard Fault and NMI handlers 1 1 PRIVDEFENA Enables privileged software access to default memory map 2 1 RNR MPU Region Number Register 0x8 32 REGION Region referenced by RBAR and RASR 0 8 RBAR MPU Region Base Address Register 0xC 32 REGION Region number 0 4 VALID Region number valid 4 1 ADDR Region base address 5 27 RASR MPU Region Attribute and Size Register 0x10 32 ENABLE Region Enable 0 1 SIZE Region Size 1 1 SRD Sub-region disable 8 8 B Bufferable bit 16 1 C Cacheable bit 17 1 S Shareable bit 18 1 TEX TEX bit 19 3 AP Access Permission 24 3 XN Execute Never Attribute 28 1 RBAR_A1 MPU Alias 1 Region Base Address Register 0x14 32 REGION Region number 0 4 VALID Region number valid 4 1 ADDR Region base address 5 27 RASR_A1 MPU Alias 1 Region Attribute and Size Register 0x18 32 ENABLE Region Enable 0 1 SIZE Region Size 1 1 SRD Sub-region disable 8 8 B Bufferable bit 16 1 C Cacheable bit 17 1 S Shareable bit 18 1 TEX TEX bit 19 3 AP Access Permission 24 3 XN Execute Never Attribute 28 1 RBAR_A2 MPU Alias 2 Region Base Address Register 0x1C 32 REGION Region number 0 4 VALID Region number valid 4 1 ADDR Region base address 5 27 RASR_A2 MPU Alias 2 Region Attribute and Size Register 0x20 32 ENABLE Region Enable 0 1 SIZE Region Size 1 1 SRD Sub-region disable 8 8 B Bufferable bit 16 1 C Cacheable bit 17 1 S Shareable bit 18 1 TEX TEX bit 19 3 AP Access Permission 24 3 XN Execute Never Attribute 28 1 RBAR_A3 MPU Alias 3 Region Base Address Register 0x24 32 REGION Region number 0 4 VALID Region number valid 4 1 ADDR Region base address 5 27 RASR_A3 MPU Alias 3 Region Attribute and Size Register 0x28 32 ENABLE Region Enable 0 1 SIZE Region Size 1 1 SRD Sub-region disable 8 8 B Bufferable bit 16 1 C Cacheable bit 17 1 S Shareable bit 18 1 TEX TEX bit 19 3 AP Access Permission 24 3 XN Execute Never Attribute 28 1 NVIC Nested Vectored Interrupt Controller NVIC NVIC_ 0xE000E100 0 0xE04 registers 5 4 ISER[%s] Interrupt Set Enable Register 0x0 32 0 SETENA Interrupt set enable bits 0 32 5 4 ICER[%s] Interrupt Clear Enable Register 0x80 32 0 CLRENA Interrupt clear-enable bits 0 32 5 4 ISPR[%s] Interrupt Set Pending Register 0x100 32 0 SETPEND Interrupt set-pending bits 0 32 5 4 ICPR[%s] Interrupt Clear Pending Register 0x180 32 0 CLRPEND Interrupt clear-pending bits 0 32 5 4 IABR[%s] Interrupt Active Bit Register 0x200 32 0 ACTIVE Interrupt active bits 0 32 35 1 IP[%s] Interrupt Priority Register n 0x300 8 0 PRI0 Priority of interrupt n 0 3 STIR Software Trigger Interrupt Register 0xE00 32 write-only INTID Interrupt ID to trigger 0 9 SysTick System timer SysTick SysTick_ 0xE000E010 0 0x10 registers CSR SysTick Control and Status Register 0x0 32 0x4 ENABLE SysTick Counter Enable 0 1 ENABLESelect VALUE_0 Counter disabled 0 VALUE_1 Counter enabled 1 TICKINT SysTick Exception Request Enable 1 1 TICKINTSelect VALUE_0 Counting down to 0 does not assert the SysTick exception request 0 VALUE_1 Counting down to 0 asserts the SysTick exception request 1 CLKSOURCE Clock Source 0=external, 1=processor 2 1 CLKSOURCESelect VALUE_0 External clock 0 VALUE_1 Processor clock 1 COUNTFLAG Timer counted to 0 since last read of register 16 1 RVR SysTick Reload Value Register 0x4 32 RELOAD Value to load into the SysTick Current Value Register when the counter reaches 0 0 24 CVR SysTick Current Value Register 0x8 32 CURRENT Current value at the time the register is accessed 0 24 CALIB SysTick Calibration Value Register 0xC 32 read-only 0 TENMS Reload value to use for 10ms timing 0 24 SKEW TENMS is rounded from non-integer ratio 30 1 SKEWSelect VALUE_0 10ms calibration value is exact 0 VALUE_1 10ms calibration value is inexact, because of the clock frequency 1 NOREF No Separate Reference Clock 31 1 NOREFSelect VALUE_0 The reference clock is provided 0 VALUE_1 The reference clock is not provided 1 SystemControl System Control Registers SystemControl SystemControl_ 0xE000E000 0 0xD8C registers ICTR Interrupt Controller Type Register 0x4 32 read-only INTLINESNUM 0 4 ACTLR Auxiliary Control Register 0x8 32 DISMCYCINT Disable interruption of LDM/STM instructions 0 1 DISDEFWBUF Disable wruite buffer use during default memory map accesses 1 1 DISFOLD Disable IT folding 2 1 DISFPCA Disable automatic update of CONTROL.FPCA 8 1 DISOOFP Disable out-of-order FP instructions 9 1 CPUID CPUID Base Register 0xD00 32 read-only 0x410FC240 REVISION Processor revision number 0 4 PARTNO Process Part Number, 0xC24=Cortex-M4 4 12 CONSTANT Constant 16 4 VARIANT Variant number 20 4 IMPLEMENTER Implementer code, 0x41=ARM 24 8 ICSR Interrupt Control and State Register 0xD04 32 0 VECTACTIVE Active exception number 0 9 RETTOBASE No preempted active exceptions to execute 11 1 VECTPENDING Exception number of the highest priority pending enabled exception 12 6 ISRPENDING Interrupt pending flag 22 1 ISRPREEMPT Debug only 23 1 PENDSTCLR SysTick clear-pending bit 25 1 PENDSTCLRSelect VALUE_0 No effect 0 VALUE_1 Removes the pending state from the SysTick exception 1 PENDSTSET SysTick set-pending bit 26 1 PENDSTSETSelect VALUE_0 Write: no effect; read: SysTick exception is not pending 0 VALUE_1 Write: changes SysTick exception state to pending; read: SysTick exception is pending 1 PENDSVCLR PendSV clear-pending bit 27 1 PENDSVCLRSelect VALUE_0 No effect 0 VALUE_1 Removes the pending state from the PendSV exception 1 PENDSVSET PendSV set-pending bit 28 1 PENDSVSETSelect VALUE_0 Write: no effect; read: PendSV exception is not pending 0 VALUE_1 Write: changes PendSV exception state to pending; read: PendSV exception is pending 1 NMIPENDSET NMI set-pending bit 31 1 NMIPENDSETSelect VALUE_0 Write: no effect; read: NMI exception is not pending 0 VALUE_1 Write: changes NMI exception state to pending; read: NMI exception is pending 1 VTOR Vector Table Offset Register 0xD08 32 0x00000000 TBLOFF Vector table base offset 7 25 AIRCR Application Interrupt and Reset Control Register 0xD0C 32 0xFA050000 VECTRESET Must write 0 0 1 VECTCLRACTIVE Must write 0 1 1 SYSRESETREQ System Reset Request 2 1 SYSRESETREQSelect VALUE_0 No system reset request 0 VALUE_1 Asserts a signal to the outer system that requests a reset 1 PRIGROUP Interrupt priority grouping 8 3 ENDIANNESS Data endianness, 0=little, 1=big 15 1 ENDIANNESSSelect VALUE_0 Little-endian 0 VALUE_1 Big-endian 1 VECTKEY Register key 16 16 SCR System Control Register 0xD10 32 0 SLEEPONEXIT Sleep-on-exit on handler return 1 1 SLEEPONEXITSelect VALUE_0 Do not sleep when returning to Thread mode 0 VALUE_1 Enter sleep, or deep sleep, on return from an ISR 1 SLEEPDEEP Deep Sleep used as low power mode 2 1 SLEEPDEEPSelect VALUE_0 Sleep 0 VALUE_1 Deep sleep 1 SEVONPEND Send Event on Pending bit 4 1 SEVONPENDSelect VALUE_0 Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 0 VALUE_1 Enabled events and all interrupts, including disabled interrupts, can wakeup the processor 1 CCR Configuration and Control Register 0xD14 32 0x00000200 NONBASETHRDENA Indicates how processor enters Thread mode 0 1 USERSETMPEND Enables unprivileged software access to STIR register 1 1 UNALIGN_TRP Enables unaligned access traps 3 1 UNALIGN_TRPSelect VALUE_0 Do not trap unaligned halfword and word accesses 0 VALUE_1 Trap unaligned halfword and word accesses 1 DIV_0_TRP Enables divide by 0 trap 4 1 BFHFNMIGN Ignore LDM/STM BusFault for -1/-2 priority handlers 8 1 STKALIGN Indicates stack alignment on exception entry 9 1 STKALIGNSelect VALUE_0 4-byte aligned 0 VALUE_1 8-byte aligned 1 SHPR1 System Handler Priority Register 1 0xD18 32 PRI_4 Priority of system handler 4, MemManage 0 8 PRI_5 Priority of system handler 5, BusFault 8 8 PRI_6 Priority of system handler 6, UsageFault 16 8 SHPR2 System Handler Priority Register 2 0xD1C 32 0 PRI_11 Priority of system handler 11, SVCall 24 8 SHPR3 System Handler Priority Register 3 0xD20 32 0 PRI_14 Priority of system handler 14, PendSV 16 8 PRI_15 Priority of system handler 15, SysTick exception 24 8 SHCSR System Handler Control and State Register 0xD24 32 MEMFAULTACT MemManage exception active bit 0 1 BUSFAULTACT BusFault exception active bit 1 1 USGFAULTACT UsageFault exception active bit 3 1 SVCALLACT SVCall active bit 7 1 MONITORACT DebugMonitor exception active bit 8 1 PENDSVACT PendSV exception active bit 10 1 SYSTICKACT SysTick exception active bit 11 1 USGFAULTPENDED UsageFault exception pending bit 12 1 MEMFAULTPENDED MemManage exception pending bit 13 1 BUSFAULTPENDED BusFault exception pending bit 14 1 SVCALLPENDED SVCall pending bit 15 1 MEMFAULTENA MemManage enable bit 16 1 BUSFAULTENA BusFault enable bit 17 1 USGFAULTENA UsageFault enable bit 18 1 CFSR Configurable Fault Status Register 0xD28 32 IACCVIOL Instruction access violation 0 1 DACCVIOL Data access violation 1 1 MUNSTKERR MemManage Fault on unstacking for exception return 3 1 MSTKERR MemManage Fault on stacking for exception entry 4 1 MLSPERR MemManager Fault occured during FP lazy state preservation 5 1 MMARVALID MemManage Fault Address Register valid 7 1 IBUSERR Instruction bus error 8 1 PRECISERR Precise data bus error 9 1 IMPRECISERR Imprecise data bus error 10 1 UNSTKERR BusFault on unstacking for exception return 11 1 STKERR BusFault on stacking for exception entry 12 1 LSPERR BusFault occured during FP lazy state preservation 13 1 BFARVALID BusFault Address Register valid 15 1 UNDEFINSTR Undefined instruction UsageFault 16 1 INVSTATE Invalid state UsageFault 17 1 INVPC Invalid PC load UsageFault 18 1 NOCP No coprocessor UsageFault 19 1 UNALIGNED Unaligned access UsageFault 24 1 DIVBYZERO Divide by zero UsageFault 25 1 HFSR HardFault Status Register 0xD2C 32 VECTTBL BusFault on a Vector Table read during exception processing 1 1 FORCED Forced Hard Fault 30 1 DEBUGEVT Debug: always write 0 31 1 DFSR Debug Fault Status Register 0xD30 32 HALTED 0 1 BKPT 1 1 DWTTRAP 2 1 VCATCH 3 1 EXTERNAL 4 1 MMFAR MemManage Fault Address Register 0xD34 32 ADDRESS Address that generated the MemManage fault 0 32 BFAR BusFault Address Register 0xD38 32 ADDRESS Address that generated the BusFault 0 32 AFSR Auxiliary Fault Status Register 0xD3C 32 IMPDEF AUXFAULT input signals 0 32 2 4 PFR[%s] Processor Feature Register 0xD40 32 DFR Debug Feature Register 0xD48 32 read-only ADR Auxiliary Feature Register 0xD4C 32 read-only 4 4 MMFR[%s] Memory Model Feature Register 0xD50 32 read-only 5 4 ISAR[%s] Instruction Set Attributes Register 0xD60 32 read-only CPACR Coprocessor Access Control Register 0xD88 32 CP10 Access privileges for coprocessor 10 20 2 CP10Select DENIED Access denied 0x0 PRIV Privileged access only 0x1 FULL Full access 0x3 CP11 Access privileges for coprocessor 11 22 2 CP11Select DENIED Access denied 0x0 PRIV Privileged access only 0x1 FULL Full access 0x3 TPI Trace Port Interface Register TPI TPI_ 0xE0040000 0 0xFD0 registers SSPSR Supported Parallel Port Size Register 0x0 32 read-only CSPSR Current Parallel Port Size Register 0x4 32 ACPR Asynchronous Clock Prescaler Register 0x10 32 PRESCALER 0 13 SPPR Selected Pin Protocol Register 0xF0 32 TXMODE 0 2 FFSR Formatter and Flush Status Register 0x300 32 read-only FlInProg 0 1 FtStopped 1 1 TCPresent 2 1 FtNonStop 3 1 FFCR Formatter and Flush Control Register 0x304 32 EnFCont 1 1 TrigIn 8 1 FSCR Formatter Synchronization Counter Register 0x308 32 read-only TRIGGER TRIGGER 0xEE8 32 read-only TRIGGER 0 1 FIFO0 Integration ETM Data 0xEEC 32 read-only ETM0 0 8 ETM1 8 8 ETM2 16 8 ETM_bytecount 24 2 ETM_ATVALID 26 1 ITM_bytecount 27 2 ITM_ATVALID 29 1 ITATBCTR2 ITATBCTR2 0xEF0 32 read-only ATREADY 0 1 ITATBCTR0 ITATBCTR0 0xEF8 32 read-only ATREADY 0 1 FIFO1 Integration ITM Data 0xEFC 32 read-only ITM0 0 8 ITM1 8 8 ITM2 16 8 ETM_bytecount 24 2 ETM_ATVALID 26 1 ITM_bytecount 27 2 ITM_ATVALID 29 1 ITCTRL Integration Mode Control 0xF00 32 Mode 0 1 CLAIMSET Claim tag set 0xFA0 32 CLAIMCLR Claim tag clear 0xFA4 32 DEVID TPIU_DEVID 0xFC8 32 read-only NrTraceInput 0 1 AsynClkIn 5 1 MinBufSz 6 3 PTINVALID 9 1 MANCVALID 10 1 NRZVALID 11 1 DEVTYPE TPIU_DEVTYPE 0xFCC 32 read-only SubType 0 4 MajorType 4 4