Allwinner D1H 1.0 Allwinner's D1-H chip unofficial SVD file maintained by community 8 32 32 read-write 0x00000000 0xFFFFFFFF CCU Clock Controller Unit System 0x02001000 0 0x10000 registers PLL_CPU_CTRL PLL_CPU Control Register 0x0000 PLL_EN PLL Enable [31:31] disable 0 enable 1 PLL_LDO_EN LDO Enable [30:30] disable 0 enable 1 LOCK_ENABLE Lock Enable [29:29] disable 0 enable 1 LOCK PLL Lock Status [28:28] read-only unlocked 0 locked 1 PLL_OUTPUT_GATE PLL Output Gating Enable [27:27] disable 0 enable 1 PLL_LOCK_TIME PLL Lock Time [26:24] PLL_N PLL N [15:8] PLL_UNLOCK_MDSEL PLL Unlock Level [7:6] CC_21_29 0b00 CC_22_28 0b01 CC_20_30 0b1x PLL_LOCK_MDSEL PLL Lock Level [5:5] CC_24_26 0 CC_23_27 1 PLL_M PLL M [1:0] PLL_DDR_CTRL PLL_DDR Control Register 0x0010 PLL_EN PLL Enable [31:31] disable 0 enable 1 PLL_LDO_EN LDO Enable [30:30] disable 0 enable 1 LOCK_ENABLE Lock Enable [29:29] disable 0 enable 1 LOCK PLL Lock Status [28:28] read-only unlocked 0 locked 1 PLL_OUTPUT_GATE PLL Output Gating Enable [27:27] disable 0 enable 1 PLL_SDM_EN PLL SDM Enable [24:24] disable 0 enable 1 PLL_N PLL N [15:8] PLL_UNLOCK_MDSEL PLL Unlock Level [7:6] CC_21_29 0b00 CC_22_28 0b01 CC_20_30 0b1x PLL_LOCK_MDSEL PLL Lock Level [5:5] CC_24_26 0 CC_23_27 1 PLL_INPUT_DIV2 PLL Input Div M1 [1:1] PLL_OUTPUT_DIV2 PLL Output Div M0 [0:0] PLL_PERI_CTRL PLL_PERI Control Register 0x0020 PLL_EN PLL Enable [31:31] disable 0 enable 1 PLL_LDO_EN LDO Enable [30:30] disable 0 enable 1 LOCK_ENABLE Lock Enable [29:29] disable 0 enable 1 LOCK PLL Lock Status [28:28] read-only unlocked 0 locked 1 PLL_OUTPUT_GATE PLL Output Gating Enable [27:27] disable 0 enable 1 PLL_SDM_EN PLL SDM Enable [24:24] disable 0 enable 1 PLL_P1 PLL Output Div P1 [22:20] PLL_P0 PLL Output Div P0 [18:16] PLL_N PLL N [15:8] PLL_UNLOCK_MDSEL PLL Unlock Level [7:6] CC_21_29 0b00 CC_22_28 0b01 CC_20_30 0b1x PLL_LOCK_MDSEL PLL Lock Level [5:5] CC_24_26 0 CC_23_27 1 PLL_INPUT_DIV2 PLL Input Div M [1:1] PLL_VIDEO0_CTRL PLL_VIDEO0 Control Register 0x0040 PLL_EN PLL Enable [31:31] disable 0 enable 1 PLL_LDO_EN LDO Enable [30:30] disable 0 enable 1 LOCK_ENABLE Lock Enable [29:29] disable 0 enable 1 LOCK PLL Lock Status [28:28] read-only unlocked 0 locked 1 PLL_OUTPUT_GATE PLL Output Gating Enable [27:27] disable 0 enable 1 PLL_SDM_EN PLL SDM Enable [24:24] disable 0 enable 1 PLL_N PLL N [15:8] PLL_UNLOCK_MDSEL PLL Unlock Level [7:6] CC_21_29 0b00 CC_22_28 0b01 CC_20_30 0b1x PLL_LOCK_MDSEL PLL Lock Level [5:5] CC_24_26 0 CC_23_27 1 PLL_INPUT_DIV2 PLL Input Div M [1:1] PLL_OUTPUT_DIV2 PLL Output Div D [0:0] PLL_VIDEO1_CTRL PLL_VIDEO1 Control Register 0x0048 PLL_EN PLL Enable [31:31] disable 0 enable 1 PLL_LDO_EN LDO Enable [30:30] disable 0 enable 1 LOCK_ENABLE Lock Enable [29:29] disable 0 enable 1 LOCK PLL Lock Status [28:28] read-only unlocked 0 locked 1 PLL_OUTPUT_GATE PLL Output Gating Enable [27:27] disable 0 enable 1 PLL_SDM_EN PLL SDM Enable [24:24] disable 0 enable 1 PLL_N PLL N [15:8] PLL_UNLOCK_MDSEL PLL Unlock Level [7:6] CC_21_29 0b00 CC_22_28 0b01 CC_20_30 0b1x PLL_LOCK_MDSEL PLL Lock Level [5:5] CC_24_26 0 CC_23_27 1 PLL_INPUT_DIV2 PLL Input Div M [1:1] PLL_OUTPUT_DIV2 PLL Output Div D [0:0] PLL_VE_CTRL PLL_VE Control Register 0x0058 PLL_EN PLL Enable [31:31] disable 0 enable 1 PLL_LDO_EN LDO Enable [30:30] disable 0 enable 1 LOCK_ENABLE Lock Enable [29:29] disable 0 enable 1 LOCK PLL Lock Status [28:28] read-only unlocked 0 locked 1 PLL_OUTPUT_GATE PLL Output Gating Enable [27:27] disable 0 enable 1 PLL_SDM_EN PLL SDM Enable [24:24] disable 0 enable 1 PLL_N PLL N [15:8] PLL_UNLOCK_MDSEL PLL Unlock Level [7:6] CC_21_29 0b00 CC_22_28 0b01 CC_20_30 0b1x PLL_LOCK_MDSEL PLL Lock Level [5:5] CC_24_26 0 CC_23_27 1 PLL_INPUT_DIV2 PLL Input Div M1 [1:1] PLL_OUTPUT_DIV2 PLL Output Div M0 [0:0] PLL_AUDIO0_CTRL PLL_AUDIO0 Control Register 0x0078 PLL_EN PLL Enable [31:31] disable 0 enable 1 PLL_LDO_EN LDO Enable [30:30] disable 0 enable 1 LOCK_ENABLE Lock Enable [29:29] disable 0 enable 1 LOCK PLL Lock Status [28:28] read-only unlocked 0 locked 1 PLL_OUTPUT_GATE PLL Output Gating Enable [27:27] disable 0 enable 1 PLL_SDM_EN PLL SDM Enable [24:24] disable 0 enable 1 PLL_P PLL Post-div P [21:16] PLL_N PLL N [15:8] PLL_UNLOCK_MDSEL PLL Unlock Level [7:6] CC_21_29 0b00 CC_22_28 0b01 CC_20_30 0b1x PLL_LOCK_MDSEL PLL Lock Level [5:5] CC_24_26 0 CC_23_27 1 PLL_INPUT_DIV2 PLL Input Div M1 [1:1] PLL_OUTPUT_DIV2 PLL Output Div M0 [0:0] PLL_AUDIO1_CTRL PLL_AUDIO1 Control Register 0x0080 PLL_EN PLL Enable [31:31] disable 0 enable 1 PLL_LDO_EN LDO Enable [30:30] disable 0 enable 1 LOCK_ENABLE Lock Enable [29:29] disable 0 enable 1 LOCK PLL Lock Status [28:28] read-only unlocked 0 locked 1 PLL_OUTPUT_GATE PLL Output Gating Enable [27:27] disable 0 enable 1 PLL_SDM_EN PLL SDM Enable [24:24] disable 0 enable 1 PLL_P1 PLL Output Div P1 [22:20] PLL_P0 PLL Output Div P0 [18:16] PLL_N PLL N [15:8] PLL_UNLOCK_MDSEL PLL Unlock Level [7:6] CC_21_29 0b00 CC_22_28 0b01 CC_20_30 0b1x PLL_LOCK_MDSEL PLL Lock Level [5:5] CC_24_26 0 CC_23_27 1 PLL_INPUT_DIV2 PLL Input Div M [1:1] PLL_DDR_PAT0_CTRL PLL_DDR Pattern0 Control Register 0x0110 SIG_DELT_PAT_EN Sigma-Delta Pattern Enable [31:31] SPR_FREQ_MODE Spread Frequency Mode [30:29] DC0 0b00 DC1 0b01 Triangular_1 0b10 Triangular_n 0b11 WAVE_STEP Wave Step [28:20] SDM_CLK_SEL SDM Clock Select [19:19] F_24_M 0 F_12_M 1 FREQ Frequency [18:17] F_31_5_k 0b00 F_32_k 0b01 F_32_5_k 0b10 F_33_k 0b11 WAVE_BOT Wave Bottom [16:0] PLL_DDR_PAT1_CTRL PLL_DDR Pattern1 Control Register 0x0114 DITHER_EN Dither Enable [24:24] FRAC_EN Fraction Enable [20:20] FRAC_IN Fraction In [16:0] PLL_PERI_PAT0_CTRL PLL_PERI Pattern0 Control Register 0x0120 SIG_DELT_PAT_EN Sigma-Delta Pattern Enable [31:31] SPR_FREQ_MODE Spread Frequency Mode [30:29] DC0 0b00 DC1 0b01 Triangular_1 0b10 Triangular_n 0b11 WAVE_STEP Wave Step [28:20] SDM_CLK_SEL SDM Clock Select [19:19] F_24_M 0 F_12_M 1 FREQ Frequency [18:17] F_31_5_k 0b00 F_32_k 0b01 F_32_5_k 0b10 F_33_k 0b11 WAVE_BOT Wave Bottom [16:0] PLL_PERI_PAT1_CTRL PLL_PERI Pattern1 Control Register 0x0124 DITHER_EN Dither Enable [24:24] FRAC_EN Fraction Enable [20:20] FRAC_IN Fraction In [16:0] PLL_VIDEO0_PAT0_CTRL PLL_VIDEO0 Pattern0 Control Register 0x0140 SIG_DELT_PAT_EN Sigma-Delta Pattern Enable [31:31] SPR_FREQ_MODE Spread Frequency Mode [30:29] DC0 0b00 DC1 0b01 Triangular_1 0b10 Triangular_n 0b11 WAVE_STEP Wave Step [28:20] SDM_CLK_SEL SDM Clock Select [19:19] F_24_M 0 F_12_M 1 FREQ Frequency [18:17] F_31_5_k 0b00 F_32_k 0b01 F_32_5_k 0b10 F_33_k 0b11 WAVE_BOT Wave Bottom [16:0] PLL_VIDEO0_PAT1_CTRL PLL_VIDEO0 Pattern1 Control Register 0x0144 DITHER_EN Dither Enable [24:24] FRAC_EN Fraction Enable [20:20] FRAC_IN Fraction In [16:0] PLL_VIDEO1_PAT0_CTRL PLL_VIDEO1 Pattern0 Control Register 0x0148 SIG_DELT_PAT_EN Sigma-Delta Pattern Enable [31:31] SPR_FREQ_MODE Spread Frequency Mode [30:29] DC0 0b00 DC1 0b01 Triangular_1 0b10 Triangular_n 0b11 WAVE_STEP Wave Step [28:20] SDM_CLK_SEL SDM Clock Select [19:19] F_24_M 0 F_12_M 1 FREQ Frequency [18:17] F_31_5_k 0b00 F_32_k 0b01 F_32_5_k 0b10 F_33_k 0b11 WAVE_BOT Wave Bottom [16:0] PLL_VIDEO1_PAT1_CTRL PLL_VIDEO1 Pattern1 Control Register 0x014C DITHER_EN Dither Enable [24:24] FRAC_EN Fraction Enable [20:20] FRAC_IN Fraction In [16:0] PLL_VE_PAT0_CTRL PLL_VE Pattern0 Control Register 0x0158 SIG_DELT_PAT_EN Sigma-Delta Pattern Enable [31:31] SPR_FREQ_MODE Spread Frequency Mode [30:29] DC0 0b00 DC1 0b01 Triangular_1 0b10 Triangular_n 0b11 WAVE_STEP Wave Step [28:20] SDM_CLK_SEL SDM Clock Select [19:19] F_24_M 0 F_12_M 1 FREQ Frequency [18:17] F_31_5_k 0b00 F_32_k 0b01 F_32_5_k 0b10 F_33_k 0b11 WAVE_BOT Wave Bottom [16:0] PLL_VE_PAT1_CTRL PLL_VE Pattern1 Control Register 0x015C DITHER_EN Dither Enable [24:24] FRAC_EN Fraction Enable [20:20] FRAC_IN Fraction In [16:0] PLL_AUDIO0_PAT0_CTRL PLL_AUDIO0 Pattern0 Control Register 0x0178 SIG_DELT_PAT_EN Sigma-Delta Pattern Enable [31:31] SPR_FREQ_MODE Spread Frequency Mode [30:29] DC0 0b00 DC1 0b01 Triangular_1 0b10 Triangular_n 0b11 WAVE_STEP Wave Step [28:20] SDM_CLK_SEL SDM Clock Select [19:19] F_24_M 0 F_12_M 1 FREQ Frequency [18:17] F_31_5_k 0b00 F_32_k 0b01 F_32_5_k 0b10 F_33_k 0b11 WAVE_BOT Wave Bottom [16:0] PLL_AUDIO0_PAT1_CTRL PLL_AUDIO0 Pattern1 Control Register 0x017C DITHER_EN Dither Enable [24:24] FRAC_EN Fraction Enable [20:20] FRAC_IN Fraction In [16:0] PLL_AUDIO1_PAT0_CTRL PLL_AUDIO1 Pattern0 Control Register 0x0180 SIG_DELT_PAT_EN Sigma-Delta Pattern Enable [31:31] SPR_FREQ_MODE Spread Frequency Mode [30:29] DC0 0b00 DC1 0b01 Triangular_1 0b10 Triangular_n 0b11 WAVE_STEP Wave Step [28:20] SDM_CLK_SEL SDM Clock Select [19:19] F_24_M 0 F_12_M 1 FREQ Frequency [18:17] F_31_5_k 0b00 F_32_k 0b01 F_32_5_k 0b10 F_33_k 0b11 WAVE_BOT Wave Bottom [16:0] PLL_AUDIO1_PAT1_CTRL PLL_AUDIO1 Pattern1 Control Register 0x0184 DITHER_EN Dither Enable [24:24] FRAC_EN Fraction Enable [20:20] FRAC_IN Fraction In [16:0] PLL_CPU_BIAS PLL_CPU Bias Register 0x0300 PLL_VCO_RST_IN VCO reset in [31:31] PLL_CP PLL current bias control [20:16] PLL_DDR_BIAS PLL_DDR Bias Register 0x0310 PLL_CP PLL current bias control [20:16] PLL_PERI_BIAS PLL_PERI Bias Register 0x0320 PLL_CP PLL current bias control [20:16] PLL_VIDEO0_BIAS PLL_VIDEO0 Bias Register 0x0340 PLL_CP PLL current bias control [20:16] PLL_VIDEO1_BIAS PLL_VIDEO1 Bias Register 0x0348 PLL_CP PLL current bias control [20:16] PLL_VE_BIAS PLL_VE Bias Register 0x0358 PLL_CP PLL current bias control [20:16] PLL_AUDIO0_BIAS PLL_AUDIO0 Bias Register 0x0378 PLL_CP PLL current bias control [20:16] PLL_AUDIO1_BIAS PLL_AUDIO1 Bias Register 0x0380 PLL_CP PLL current bias control [20:16] PLL_CPU_TUN PLL_CPU Tuning Register 0x0400 PLL_VCO VCO range control [30:28] PLL_VCO_GAIN KVCO gain control [26:24] PLL_CNT_INT Counter initial control [22:16] PLL_REG_OD PLL-REG-OD0 for verify [15:15] PLL_B_IN PLL-B-IN [6:0] for verify [14:8] PLL_REG_OD1 PLL-REG-OD1 for verify [7:7] PLL_B_OUT PLL-B-OUT [6:0] for verify [6:0] read-only CPU_AXI_CFG CPU_AXI Configuration Register 0x0500 CPU_CLK_SEL Clock Source Select [26:24] HOSC 0b000 CLK32K 0b001 CLK16M_RC 0b010 PLL_CPU_P 0b011 PLL_PERI_1X 0b100 PLL_PERI_2X 0b101 PLL_PERI_800M 0b110 PLL_CPU_OUT_EXT_DIVP PLL Output External Divider P [17:16] P1 0b00 P2 0b01 P4 0b10 CPU_DIV2 Factor N [9:8] CPU_DIV1 Factor M [1:0] CPU_GATING CPU_GATING Configuration Register 0x0504 CPU_GATING Gating Special Clock [31:31] OFF 0 ON 1 CPU_GATING_FIELD CPU Gating Field [15:0] PSI_CLK PSI Clock Register 0x0510 CLK_SRC_SEL Clock Source Select [25:24] HOSC 0b00 CLK32K 0b01 CLK16M_RC 0b10 PLL_PERI_1X 0b11 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [1:0] 2 0x4 APB%s_CLK APB Clock Register 0x0520 CLK_SRC_SEL Clock Source Select [25:24] HOSC 0b00 CLK32K 0b01 PSI_CLK 0b10 PLL_PERI_1X 0b11 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [4:0] MBUS_CLK MBUS Clock Register 0x0540 MBUS_RST MBUS Reset [30:30] Assert 0 Deassert 1 DE_CLK DE Clock Register 0x0600 CLK_GATING Gating Clock [31:31] OFF 0 ON 1 CLK_SRC_SEL Clock Source Select [26:24] PLL_PERI_2X 0b000 PLL_VIDEO0_4X 0b001 PLL_VIDEO1_4X 0b010 PLL_AUDIO1_DIV2 0b011 FACTOR_M Factor M [4:0] DE_BGR DE Bus Gating Reset Register 0x060C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 DI_CLK DI Clock Register 0x0620 CLK_GATING Gating Clock [31:31] OFF 0 ON 1 CLK_SRC_SEL Clock Source Select [26:24] PLL_PERI_2X 0b000 PLL_VIDEO0_4X 0b001 PLL_VIDEO1_4X 0b010 PLL_AUDIO1_DIV2 0b011 FACTOR_M Factor M [4:0] DI_BGR DI Bus Gating Reset Register 0x062C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 G2D_CLK G2D Clock Register 0x0630 CLK_GATING Gating Clock [31:31] OFF 0 ON 1 CLK_SRC_SEL Clock Source Select [26:24] PLL_PERI_2X 0b000 PLL_VIDEO0_4X 0b001 PLL_VIDEO1_4X 0b010 PLL_AUDIO1_DIV2 0b011 FACTOR_M Factor M [4:0] G2D_BGR G2D Bus Gating Reset Register 0x063C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 CE_CLK CE Clock Register 0x0680 CLK_GATING Gating Clock [31:31] OFF 0 ON 1 CLK_SRC_SEL Clock Source Select [26:24] HOSC 0b00 PLL_PERI_2X 0b01 PLL_PERI_1X 0b10 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [3:0] CE_BGR CE Bus Gating Reset Register 0x068C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 VE_CLK VE Clock Register 0x0690 CLK_GATING Gating Clock [31:31] OFF 0 ON 1 CLK_SRC_SEL Clock Source Select [24:24] VEPLL 0 PLL_PERI_2X 1 FACTOR_M Factor M [4:0] VE_BGR VE Bus Gating Reset Register 0x069C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 DMA_BGR DMA Bus Gating Reset Register 0x070C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 MSGBOX_BGR MSGBOX Bus Gating Reset Register 0x071C 3 1 MSGBOX%s_RST CPU, DSP, RISC-V MSGBOX Reset [16:16] Assert 0 Deassert 1 3 1 MSGBOX%s_GATING Gating Clock for CPU, DSP, RISC-V MSGBOX [0:0] Mask 0 Pass 1 SPINLOCK_BGR SPINLOCK Bus Gating Reset Register 0x072C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 HSTIMER_BGR HSTIMER Bus Gating Reset Register 0x073C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 AVS_CLK AVS Clock Register 0x0740 CLK_GATING Gating Clock [31:31] OFF 0 ON 1 DBGSYS_BGR DBGSYS Bus Gating Reset Register 0x078C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 PWM_BGR PWM Bus Gating Reset Register 0x07AC RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 IOMMU_BGR IOMMU Bus Gating Reset Register 0x07BC GATING Gating Clock [0:0] Mask 0 Pass 1 DRAM_CLK DRAM Clock Register 0x0800 CLK_GATING Gating Clock [31:31] OFF 0 ON 1 SDRCLK_UPD SDRCLK Configuration 0 Update [27:27] invalid 0 valid 1 CLK_SRC_SEL Clock Source Select [26:24] PLL_DDR 0b00 PLL_AUDIO1_DIV2 0b01 PLL_PERI_2X 0b10 PLL_PERI_800M 0b11 DRAM_DIV2 Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 DRAM_DIV1 Factor M [1:0] MBUS_MAT_CLK_GATING MBUS Master Clock Gating Register 0x0804 RISCV_MCLK_EN Gating MBUS Clock [11:11] Mask 0 Pass 1 G2D_MCLK_EN Gating MBUS Clock [10:10] Mask 0 Pass 1 CSI_MCLK_EN Gating MBUS Clock [8:8] Mask 0 Pass 1 TVIN_MCLK_EN Gating MBUS Clock [7:7] Mask 0 Pass 1 CE_MCLK_EN Gating MBUS Clock [2:2] Mask 0 Pass 1 VE_MCLK_EN Gating MBUS Clock [1:1] Mask 0 Pass 1 DMA_MCLK_EN Gating MBUS Clock [0:0] Mask 0 Pass 1 DRAM_BGR DRAM Bus Gating Reset Register 0x080C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 SMHC0_CLK SMHC0 Clock Register 0x0830 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] HOSC 0b000 PLL_PERI_1X 0b001 PLL_PERI_2X 0b010 PLL_AUDIO1_DIV2 0b011 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [3:0] SMHC1_CLK SMHC1 Clock Register 0x0834 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] HOSC 0b000 PLL_PERI_1X 0b001 PLL_PERI_2X 0b010 PLL_AUDIO1_DIV2 0b011 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [3:0] SMHC2_CLK SMHC2 Clock Register 0x0838 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] HOSC 0b000 PLL_PERI_1X 0b001 PLL_PERI_2X 0b010 PLL_PERI_800M 0b011 PLL_AUDIO1_DIV2 0b100 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [3:0] SMHC_BGR SMHC Bus Gating Reset Register 0x084C 3 1 SMHC%s_RST Reset [16:16] Assert 0 Deassert 1 3 1 SMHC%s_GATING Gating Clock [0:0] Mask 0 Pass 1 UART_BGR UART Bus Gating Reset Register 0x090C 6 1 UART%s_RST Reset [16:16] Assert 0 Deassert 1 6 1 UART%s_GATING Gating Clock [0:0] Mask 0 Pass 1 TWI_BGR TWI Bus Gating Reset Register 0x091C 4 1 TWI%s_RST Reset [16:16] Assert 0 Deassert 1 4 1 TWI%s_GATING Gating Clock [0:0] Mask 0 Pass 1 SPI0_CLK SPI0 Clock Register 0x0940 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] HOSC 0b000 PLL_PERI_1X 0b001 PLL_PERI_2X 0b010 PLL_AUDIO1_DIV2 0b011 PLL_AUDIO1_DIV5 0b100 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [3:0] SPI1_CLK SPI1 Clock Register 0x0944 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] HOSC 0b000 PLL_PERI_1X 0b001 PLL_PERI_2X 0b010 PLL_AUDIO1_DIV2 0b011 PLL_AUDIO1_DIV5 0b100 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [3:0] SPI_BGR SPI Bus Gating Reset Register 0x096C 2 1 SPI%s_RST Reset [16:16] Assert 0 Deassert 1 2 1 SPI%s_GATING Gating Clock [0:0] Mask 0 Pass 1 EMAC_25M_CLK EMAC_25M Clock Register 0x0970 CLK_GATING Gating Special Clock [31:31] Off 0 On 1 CLK_SRC_GATING Gating the Source Clock of Special Clock [31:31] Off 0 On 1 EMAC_BGR EMAC Bus Gating Reset Register 0x097C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 IRTX_CLK IRTX Clock Register 0x09C0 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] HOSC 0 PLL_PERI_1X 1 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [3:0] IRTX_BGR IRTX Bus Gating Reset Register 0x09CC RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 GPADC_BGR GPADC Bus Gating Reset Register 0x09EC RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 THS_BGR THS Bus Gating Reset Register 0x09FC RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 3 0x4 I2S%s_CLK I2S Clock Register 0x0A10 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] PLL_AUDIO0_1X 0b00 PLL_AUDIO0_4X 0b01 PLL_AUDIO1_DIV2 0b10 PLL_AUDIO1_DIV5 0b11 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [4:0] I2S2_ASRC_CLK I2S2_ASRC Clock Register 0x0A1C CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] PLL_AUDIO0_4X 0b00 PLL_PERI_1X 0b01 PLL_AUDIO1_DIV2 0b10 PLL_AUDIO1_DIV5 0b11 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [4:0] I2S_BGR I2S Bus Gating Reset Register 0x0A20 3 1 I2S%s_RST Reset [16:16] Assert 0 Deassert 1 3 1 I2S%s_GATING Gating Clock [0:0] Mask 0 Pass 1 OWA_TX_CLK OWA_TX Clock Register 0x0A24 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] PLL_AUDIO0_1X 0b00 PLL_AUDIO0_4X 0b01 PLL_AUDIO1_DIV2 0b10 PLL_AUDIO1_DIV5 0b11 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [4:0] OWA_RX_CLK OWA_RX Clock Register 0x0A28 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] PLL_PERI_1X 0b00 PLL_AUDIO1_DIV2 0b01 PLL_AUDIO1_DIV5 0b10 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [4:0] OWA_BGR OWA Bus Gating Reset Register 0x0A2C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 DMIC_CLK DMIC Clock Register 0x0A40 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] PLL_PERI_1X 0b00 PLL_AUDIO1_DIV2 0b01 PLL_AUDIO1_DIV5 0b10 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [4:0] DMIC_BGR DMIC Bus Gating Reset Register 0x0A4C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 AUDIO_CODEC_DAC_CLK AUDIO_CODEC_DAC Clock Register 0x0A50 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] PLL_AUDIO0_1X 0b00 PLL_AUDIO1_DIV2 0b01 PLL_AUDIO1_DIV5 0b10 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [4:0] AUDIO_CODEC_ADC_CLK AUDIO_CODEC_ADC Clock Register 0x0A54 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] PLL_AUDIO0_1X 0b00 PLL_AUDIO1_DIV2 0b01 PLL_AUDIO1_DIV5 0b10 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [4:0] AUDIO_CODEC_BGR AUDIO_CODEC Bus Gating Reset Register 0x0A5C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 USB0_CLK USB0 Clock Register 0x0A70 CLKEN Gating Special Clock [31:31] Off 0 On 1 RSTN PHY Reset [30:30] Assert 0 Deassert 1 CLK12M_SEL OHCI 12M Source Select [25:24] DIV_48M 0b00 DIV_24M 0b01 RTC_32K 0b10 USB1_CLK USB1 Clock Register 0x0A74 CLKEN Gating Special Clock [31:31] Off 0 On 1 RSTN PHY Reset [30:30] Assert 0 Deassert 1 CLK12M_SEL OHCI 12M Source Select [25:24] DIV_48M 0b00 DIV_24M 0b01 RTC_32K 0b10 USB_BGR USB Bus Gating Reset Register 0x0A8C USBOTG0_RST USBOTG0 Reset [24:24] Assert 0 Deassert 1 2 1 USBEHCI%s_RST USBEHCI Reset [20:20] Assert 0 Deassert 1 2 1 USBOHCI%s_RST USBOHCI Reset [16:16] Assert 0 Deassert 1 USBOTG0_GATING USBOTG0 Gating Clock [8:8] Mask 0 Pass 1 2 1 USBEHCI%s_GATING USBEHCI Gating Clock [4:4] Mask 0 Pass 1 2 1 USBOHCI%s_GATING USBOHCI Gating Clock [0:0] Mask 0 Pass 1 LRADC_BGR LRADC Bus Gating Reset Register 0x0A9C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 DPSS_TOP_BGR DPSS_TOP Bus Gating Reset Register 0x0ABC RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 DSI_CLK DSI Clock Register 0x0B24 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] HOSC 0b000 PLL_PERI_1X 0b001 PLL_VIDEO0_2X 0b010 PLL_VIDEO1_2X 0b011 PLL_AUDIO1_DIV2 0b100 FACTOR_M Factor M [3:0] DSI_BGR DSI Bus Gating Reset Register 0x0B4C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 TCONLCD_CLK TCONLCD Clock Register 0x0B60 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] PLL_VIDEO0_1X 0b000 PLL_VIDEO0_4X 0b001 PLL_VIDEO1_1X 0b010 PLL_VIDEO1_4X 0b011 PLL_PERI_2X 0b100 PLL_AUDIO1_DIV2 0b101 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [3:0] TCONLCD_BGR TCONLCD Bus Gating Reset Register 0x0B7C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 TCONTV_CLK TCONTV Clock Register 0x0B80 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] PLL_VIDEO0_1X 0b000 PLL_VIDEO0_4X 0b001 PLL_VIDEO1_1X 0b010 PLL_VIDEO1_4X 0b011 PLL_PERI_2X 0b100 PLL_AUDIO1_DIV2 0b101 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [3:0] TCONTV_BGR TCONTV Bus Gating Reset Register 0x0B9C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 LVDS_BGR LVDS Bus Gating Reset Register 0x0BAC RST Reset [16:16] Assert 0 Deassert 1 TVE_CLK TVE Clock Register 0x0BB0 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] PLL_VIDEO0_1X 0b000 PLL_VIDEO0_4X 0b001 PLL_VIDEO1_1X 0b010 PLL_VIDEO1_4X 0b011 PLL_PERI_2X 0b100 PLL_AUDIO1_DIV2 0b101 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [3:0] TVE_BGR TVE Bus Gating Reset Register 0x0BBC RST Reset [17:17] Assert 0 Deassert 1 TOP_RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [1:1] Mask 0 Pass 1 TOP_GATING Gating Clock [0:0] Mask 0 Pass 1 TVD_CLK TVD Clock Register 0x0BC0 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] HOSC 0b000 PLL_VIDEO0_1X 0b001 PLL_VIDEO1_1X 0b010 PLL_PERI_1X 0b011 FACTOR_M Factor M [4:0] TVD_BGR TVD Bus Gating Reset Register 0x0BDC RST Reset [17:17] Assert 0 Deassert 1 TOP_RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [1:1] Mask 0 Pass 1 TOP_GATING Gating Clock [0:0] Mask 0 Pass 1 LEDC_CLK LEDC Clock Register 0x0BF0 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] HOSC 0 PLL_PERI_1X 1 FACTOR_N Factor N [9:8] N1 0b00 N2 0b01 N4 0b10 N8 0b11 FACTOR_M Factor M [3:0] LEDC_BGR LEDC Bus Gating Reset Register 0x0BFC RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 CSI_CLK CSI Clock Register 0x0C04 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] PLL_PERI_2X 0b000 PLL_VIDEO0_2X 0b001 PLL_VIDEO1_2X 0b010 FACTOR_M Factor M [3:0] CSI_MASTER_CLK CSI Master Clock Register 0x0C08 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] HOSC 0b000 PLL_PERI_1X 0b001 PLL_VIDEO0_1X 0b010 PLL_VIDEO1_1X 0b011 PLL_AUDIO1_DIV2 0b100 PLL_AUDIO1_DIV5 0b101 FACTOR_M Factor M [4:0] CSI_BGR CSI Bus Gating Reset Register 0x0C1C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 TPADC_CLK TPADC Clock Register 0x0C50 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] HOSC 0 PLL_AUDIO0_1X 1 TPADC_BGR TPADC Bus Gating Reset Register 0x0C5C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 DSP_CLK DSP Clock Register 0x0C70 CLK_GATING Gating Clock [31:31] Off 0 On 1 CLK_SRC_SEL Clock Source Select [26:24] HOSC 0b000 CLK32K 0b001 CLK16M_RC 0b010 PLL_PERI_2X 0b011 PLL_AUDIO1_DIV2 0b100 FACTOR_M Factor M [4:0] DSP_BGR DSP Bus Gating Reset Register 0x0C7C DBG_RST Reset [18:18] Assert 0 Deassert 1 CFG_RST Reset [17:17] Assert 0 Deassert 1 RST Reset [16:16] Assert 0 Deassert 1 CFG_GATING Gating Clock [1:1] Mask 0 Pass 1 RISCV_CLK RISC-V Clock Register 0x0D00 CLK_SRC_SEL Clock Source Select [26:24] HOSC 0b000 CLK32K 0b001 CLK16M_RC 0b010 PLL_PERI_800M 0b011 PLL_PERI_1X 0b100 PLL_CPU 0b101 PLL_AUDIO1_DIV2 0b110 AXI_DIV_CFG Factor N [9:8] DIV_CFG Factor M [4:0] RISCV_GATING RISC-V GATING Configuration Register 0x0D04 GATING Gating Clock [31:31] Mask 0 Pass 1 GATING_FIELD [15:0] RISCV_CFG_BGR RISC-V_CFG Bus Gating Reset Register 0x0D0C RST Reset [16:16] Assert 0 Deassert 1 GATING Gating Clock [0:0] Mask 0 Pass 1 PLL_LOCK_DBG_CTRL PLL Lock Debug Control Register 0x0F04 PLL_LOCK_FLAG_EN Debug Enable [31:31] Disable 0 Enable 1 CLK_SRC_SEL Clock Source Select [22:20] PLL_CPUX 0b000 PLL_DDR 0b001 PLL_PERI_2X 0b010 PLL_VIDEO0_4X 0b011 PLL_VIDEO1_4X 0b100 PLL_VE 0b101 PLL_AUDIO0 0b110 PLL_AUDIO1 0b111 FRE_DET_CTRL Frequency Detect Control Register 0x0F08 ERROR_FLAG Error Flag [31:31] zeroToClear W0C 0 Error 1 DET_TIME Detect Time [8:4] FRE_DET_IRQ_EN Frequence Detect IRQ Enable [1:1] Disable 0 Enable 1 FRE_DET_FUN_EN Frequence Detect Function Enable [0:0] Disable 0 Enable 1 FRE_UP_LIM Frequency Up Limit Register 0x0F0C FRE_DOWN_LIM Frequency Down Limit Register 0x0F10 CCU_FAN_GATE CCU FANOUT CLOCK GATE Register 0x0F30 CLK32K_EN Gating for CLK32K [4:4] OFF 0 ON 1 CLK25M_EN Gating for CLK25M [3:3] OFF 0 ON 1 CLK16M_EN Gating for CLK16M [2:2] OFF 0 ON 1 CLK12M_EN Gating for CLK12M [1:1] OFF 0 ON 1 CLK24M_EN Gating for CLK24M [0:0] OFF 0 ON 1 CLK27M_FAN CLK27M FANOUT Register 0x0F34 GATING Gating for CLK27M [31:31] OFF 0 ON 1 CLK_SRC_SEL Clock Source Select [25:24] PLL_VIDEO0_1X 0 PLL_VIDEO1_1X 1 DIV1 Factor N [9:8] DIV0 Factor M [4:0] PCLK_FAN PCLK FANOUT Register 0x0F38 GATING Gating for PCLK [31:31] OFF 0 ON 1 DIV Factor M [4:0] CCU_FAN CCU FANOUT Register 0x0F3C 3 1 CLK_FANOUT%s_EN Gating for CLK_FANOUT [21:21] OFF 0 ON 1 3 3 CLK_FANOUT%s_SEL [2:0] CLK32K 0b000 CLK12M 0b001 CLK16M 0b010 CLK24M 0b011 CLK25M 0b100 CLK27M 0b101 PCLK 0b110 SYS_CFG System Configuration System 0x03000000 0 0x1000 registers DSP_BOOT_RAMMAP DSP Boot SRAM Remap Control Register 0x0008 DSP_BOOT_SRAM_REMAP_ENABLE [0:0] DSP_SYS 0 SYS_BOOT 1 VER Version Register 0x0024 read-only BOOT_SEL_PAD_STA [12:11] FEL_SEL_PAD_STA Fel Select Pin Status [8:8] RUN_FEL 0 TRY_MEDIA_BOOT 1 EMAC_EPHY_CLK0 EMAC-EPHY Clock Register 0 0x0030 BPS_EFUSE [31:28] XMII_SEL [27:27] Internal 0 External 1 EPHY_MODE [26:25] Normal 0b00 Simulation 0b01 AFE_Test 0b10 PHY_ADDR [24:20] CLK_SEL [18:18] F25M 0 F24M 1 LED_POL [17:17] High 0 Low 1 SHUTDOWN [16:16] Power_up 0 Shut_down 1 PHY_SELECT [15:15] External 0 Internal 1 RMII_EN [13:13] Disable 0 Enable 1 ETXDC [12:10] ERXDC [9:5] ERXIE [4:4] Disable 0 Enable 1 ETXIE [3:3] Disable 0 Enable 1 EPIT [2:2] MII 0 RGMII 1 ETCS [1:0] MII 0b00 External_GMII_RGMII 0b01 Internal_GMII_RGMII 0b10 SYS_LDO_CTRL System LDO Control Register 0x0150 SPARE [31:24] LDOB_TRIM [15:8] O1_167 0b000000 O1_18 0b000001 O1_193 0b000010 O1_207 0b000011 O1_22 0b000100 O1_233 0b000101 O1_247 0b000110 O1_260 0b000111 O1_273 0b001000 O1_287 0b001001 O1_3 0b001010 O1_313 0b001011 O1_327 0b001100 O1_340 0b001101 O1_353 0b001110 O1_367 0b001111 O1_38 0b010000 O1_393 0b010001 O1_407 0b010010 O1_42 0b010011 O1_433 0b010100 O1_447 0b010101 O1_46 0b010110 O1_473 0b010111 O1_487 0b011000 O1_5 0b011001 O1_513 0b011010 O1_527 0b011011 O1_54 0b011100 O1_553 0b011101 O1_567 0b011110 O1_58 0b011111 O1_593 0b100000 O1_607 0b100001 O1_627 0b100010 O1_64 0b100011 O1_653 0b100100 O1_667 0b100101 O1_680 0b100110 O1_693 0b100111 O1_707 0b101000 O1_720 0b101001 O1_733 0b101010 O1_747 0b101011 O1_76 0b101100 O1_773 0b101101 O1_787 0b101110 O1_8 0b101111 O1_813 0b110000 O1_827 0b110001 O1_84 0b110010 O1_853 0b110011 O1_867 0b110100 O1_88 0b110101 O1_893 0b110110 O1_907 0b110111 O1_92 0b111000 O1_933 0b111001 O1_947 0b111010 O1_96 0b111011 O1_973 0b111100 O1_987 0b111101 O2 0b111110 O2_013 0b111111 LDOA_TRIM [7:0] O1_593 0b00000 O1_607 0b00001 O1_627 0b00010 O1_64 0b00011 O1_653 0b00100 O1_667 0b00101 O1_680 0b00110 O1_693 0b00111 O1_707 0b01000 O1_720 0b01001 O1_733 0b01010 O1_747 0b01011 O1_76 0b01100 O1_773 0b01101 O1_787 0b01110 O1_8 0b01111 O1_813 0b10000 O1_827 0b10001 O1_84 0b10010 O1_853 0b10011 O1_867 0b10100 O1_88 0b10101 O1_893 0b10110 O1_907 0b10111 O1_92 0b11000 O1_933 0b11001 O1_947 0b11010 O1_96 0b11011 O1_973 0b11100 O1_987 0b11101 O2 0b11110 O2_013 0b11111 RESCAL_CTRL Resistor Calibration Control Register 0x0160 DDR_RES240_Trimming_SEL 240ohms Resistor Trimming Source Select [8:8] RESCAL 0 RES240_TRIM 1 RESCAL_MODE RESCAL Calibration Mode Select [2:2] Auto_Calibration 0 CAL_ANA_EN Calibration Circuits Analog Enable [1:1] Disable 0 Enable 1 CAL_EN Auto Calibration Enable [0:0] Disable 0 Enable 1 RES240_CTRL 240ohms Resistor Manual Control Register 0x0168 DDR_RES240_TRIM 240ohms Resistor trimming bit [5:0] RESCAL_STATUS Resistor Calibration Status Register 0x016C read-only COUT Calibration Circuits Analog COmpare Output [8:8] RES_CAL_DO RESCAL Calibration Results Output [5:0] RISCV_CFG RISC-V System Configuration System 0x06010000 0 0x1000 registers RISCV_STA_ADD0_REG RISCV Start Address0 Register 0x0004 RISCV_STA_ADD1_REG RISCV Start Address1 Register 0x0008 STA_ADD_H Start Address High 8-bit [7:0] RF1P_CFG_REG RF1P Configuration Register 0x0010 RF1P_CFG RF1P Configuration [7:0] ROM_CFG_REG ROM Configuration Register 0x001C ROM_CFG ROM Configuration [7:0] WAKEUP_EN_REG Wakeup Enable Register 0x0020 WP_EN Wakeup Enable [0:0] 5 0x04 WAKEUP_MASK%s_REG Wakeup Mask Register 0x0024 TS_TMODE_SEL_REG Timestamp Test Mode Select Register 0x0040 TS_TEST_MODE_EN Timestamp Test Mode Enable [0:0] Normal 0 Test 1 SRAM_ADDR_TWIST_REG SRAM Address Twist Register 0x0044 SRAM_TS_KF SRAM Twist Keyfield [31:16] write-only SRAM_ADDR_TS_FG SRAM Address Twist Flag [0:0] WORK_MODE_REG Work Mode Register 0x0048 read-only WM_STA Work Mode Status [1:0] Normal 0b00 Low_Power 0b01 Debug 0b10 RETITE_PC0_REG Retire PC0 Register 0x0050 read-only RETITE_PC1_REG Retire PC1 Register 0x0054 read-only RT_SIG Retire Signal [31:31] not_have 0 have 1 RT_PC_H Retire PC[39:32] [7:0] 5 0x04 IRQ_MODE%s_REG IRQ Mode Register 0x0060 RISCV_AXI_PMU_CTRL RISCV AXI PMU Control Register 0x0104 PMU_CLR PMU Clear [1:1] clear no_operation 0 cleared 1 PMU_EN PMU Enable [0:0] disabled 0 enabled 1 RISCV_AXI_PMU_PRD RISCV AXI PMU Period Register 0x0108 RISCV_AXI_PMU_LAT_RD RISCV AXI PMU Read Latency Register 0x010C read-only RISCV_AXI_PMU_LAT_WR RISCV AXI PMU Write Latency Register 0x0110 read-only RISCV_AXI_PMU_REQ_RD RISCV AXI PMU Read Request Register 0x0114 read-only RISCV_AXI_PMU_REQ_WR RISCV AXI PMU Write Request Register 0x0118 read-only RISCV_AXI_PMU_BW_RD RISCV AXI PMU Read Bandwidth Register 0x011C read-only RISCV_AXI_PMU_BW_WR RISCV AXI PMU Write Bandwidth Register 0x0120 read-only CLINT Core-Local Interruptor System 0x14000000 0 0x10000 registers msip MSIP Register for hart 0 0x0000 0 1 mtimecmpl MTIMECMPL Register for hart 0 0x4000 mtimecmph MTIMECMPH Register for hart 0 0x4004 mtime MTIME\n\nREF: opensbi 0xBFF8 64 read-only ssip SSIP Register for hart 0 0xC000 0 1 stimecmpl STIMECMPL Register for hart 0 0xD000 stimecmph STIMECMPH Register for hart 0 0xD004 TIMER Timer Module, includes timer0, timer1, watchdog and audio video synchronization System 0x02050000 0 0x1000 registers TIMER0 75 TIMER1 76 WATCHDOG 79 tmr_irq_en Timer IRQ Enable Register 0x0000 tmr1_irq_en [1:1] disabled 0 enabled 1 tmr0_irq_en [0:0] disabled 0 enabled 1 tmr_irq_sta Timer Status Register 0x0004 tmr1_irq_pend [1:1] no_effect 0 pending Indicates that the interval value of the timer 1 is reached. Write 1 to clear the pending status. 1 tmr0_irq_pend [0:0] no_effect 0 pending Indicates that the interval value of the timer 0 is reached. Write 1 to clear the pending status. 1 2 0x10 tmr%s_ctrl Timer IRQ Enable Register 0x0010 tmr_mode [7:7] periodic 0 single_counting 1 tmr_clk_pres [6:4] P1 0b000 P2 0b001 P4 0b010 P8 0b011 P16 0b100 P32 0b101 P64 0b110 P128 0b111 tmr_clk_src [3:2] losc 0 osc24_m 1 tmr_reload [1:1] no_effect 0 reload 1 tmr_en [0:0] stop_pause 0 start 1 2 0x10 tmr%s_intv_value Timer Interval Value Register 0x0014 2 0x10 tmr%s_cur_value Timer Current Value Register 0x0018 wdog_irq_en Watchdog IRQ Enable Register 0x00A0 wdog_irq_en [0:0] disabled 0 enabled 1 wdog_irq_sta Watchdog Status Register 0x00A4 wdog_irq_pend [0:0] no_effect 0 pending Indicates that the interval value of the watchdog is reached. 1 wdog_soft_rst Watchdog Software Reset Register 0x00A8 KEY_FIELD Key Field [31:16] write-only SOFT_RST_EN Soft Reset Enable [0:0] Deassert 0 Reset 1 wdog_ctrl Watchdog Control Register 0x00B0 WDOG_KEY_FIELD Watchdog Key Field [12:1] write-only WDOG_RESTART Watchdog Restart [0:0] oneToSet no_effect 0 restart 1 wdog_cfg Watchdog Configuration Register 0x00B4 KEY_FIELD Key Field [31:16] write-only WDOG_CLK_SRC Select the clock source for the watchdog. [8:8] HOSC_32K 0 LOSC_32K 1 WDOG_MODE Configure the operating mode for the watchdog [1:0] whold_system 0b01 only_interrupt 0b10 wdog_mode Watchdog Mode Register 0x00B8 KEY_FIELD Key Field [31:16] write-only WDOG_INTV_VALUE Watchdog Interval Value [7:4] C16000 0b0000 C32000 0b0001 C64000 0b0010 C96000 0b0011 C128000 0b0100 C160000 0b0101 C192000 0b0110 C256000 0b0111 C320000 0b1000 C384000 0b1001 C448000 0b1010 C512000 0b1011 WDOG_EN Watchdog Enable [0:0] no_effect 0 enable 1 wdog_output_cfg Watchdog Output Configuration Register 0x00BC WDOG_OUTPUT_CONFIG Configure the valid time for the watchdog reset signal. [11:0] avs_cnt_ctl AVS Counter Control Register 0x00C0 2 1 AVS_CNT%s_PS Audio Video Sync Counter Pause Control [8:8] not_pause 0 pause 1 2 1 AVS_CNT%s_EN Audio Video Sync Counter Enable [0:0] disabled 0 enabled 1 avs_cnt0 AVS Counter 0 Register 0x00C4 avs_cnt1 AVS Counter 1 Register 0x00C8 avs_cnt_div AVS Counter Divisor Register 0x00CC 2 16 AVS_CNT%s_D The divisor factor of AVS [11:0] HSTimer High Speed Timer System 0x03008000 0 0x1000 registers HSTIMER0 71 HSTIMER1 72 HS_TMR_IRQ_EN HS Timer IRQ Enable Register 0x0000 2 1 HS_TMR%s_INT_EN HSTimer Interrupt Enable [0:0] disabled 0 enabled 1 HS_TMR_IRQ_STAS HS Timer Status Register 0x0004 2 1 HS_TMR%s_IRQ_PEND HSTimer IRQ Pending [0:0] oneToClear no_effect 0 pending 1 2 0x20 HS_TMR%s_CTRL HS Timer Control Register 0x0020 HS_TMR_TEST Select the operating mode for HSTimer [31:31] Normal 0 Test 1 HS_TMR_MODE Select the timing mode for HSTimer [7:7] periodic 0 one_shot 1 HS_TMR_CLK Select the pre-scale for the HSTimer clock sources [6:4] P1 0b000 P2 0b001 P4 0b010 P8 0b011 P16 0b100 HS_TMR_RELOAD HSTimer Reload [1:1] oneToSet no_effect 0 reload 1 HS_TMR_EN HSTimer Enable [0:0] stop_pause 0 start 1 2 0x20 HS_TMR%s_INTV_LO HS Timer Interval Value Low Register 0x0024 2 0x20 HS_TMR%s_INTV_HI HS Timer Interval Value High Register 0x0028 HS_TMR_INTV_VALUE_HI [23:0] 2 0x20 HS_TMR%s_CURNT_LO HS Timer Current Value Low Register 0x002C 2 0x20 HS_TMR%s_CURNT_HI HS Timer Current Value High Register 0x0030 HS_TMR_CUR_VALUE_HI [23:0] PLIC Platform Level Interrupt Control System 0x10000000 256 0x4 prio[%s] Interrupt Priority Register 0x000000 priority 0 4 P0 Priority 0 (never interrupt) 0 P1 Priority 1 1 P2 Priority 2 2 P3 Priority 3 3 P4 Priority 4 4 P5 Priority 5 5 P6 Priority 6 6 P7 Priority 7 7 P8 Priority 8 8 P9 Priority 9 9 P10 Priority 10 10 P11 Priority 11 11 P12 Priority 12 12 P13 Priority 13 13 P14 Priority 14 14 P15 Priority 15 15 P16 Priority 16 16 P17 Priority 17 17 P18 Priority 18 18 P19 Priority 19 19 P20 Priority 20 20 P21 Priority 21 21 P22 Priority 22 22 P23 Priority 23 23 P24 Priority 24 24 P25 Priority 25 25 P26 Priority 26 26 P27 Priority 27 27 P28 Priority 28 28 P29 Priority 29 29 P30 Priority 30 30 P31 Priority 31 31 9 0x4 ip[%s] Interrupt Pending Register 0x001000 9 0x04 mie[%s] Machine Mode Interrupt Enable Register 0x002000 9 0x04 sie[%s] Supervisor Mode Interrupt Enable Register 0x002080 ctrl Control Register 0x1FFFFC ctrl PLIC Control [0:0] m Only the machine mode can access to all registers in PLIC. Supervisor mode can only access the interrupt threshold register and the interrupt response/completion register. 0 ms The machine mode and the supervisor mode can access all registers. CTRL is accessible only in the machine mode. 1 mth Machine Mode Priority Threshold Register 0x200000 priority 0 4 P0 Priority 0 (never interrupt) 0 P1 Priority 1 1 P2 Priority 2 2 P3 Priority 3 3 P4 Priority 4 4 P5 Priority 5 5 P6 Priority 6 6 P7 Priority 7 7 P8 Priority 8 8 P9 Priority 9 9 P10 Priority 10 10 P11 Priority 11 11 P12 Priority 12 12 P13 Priority 13 13 P14 Priority 14 14 P15 Priority 15 15 P16 Priority 16 16 P17 Priority 17 17 P18 Priority 18 18 P19 Priority 19 19 P20 Priority 20 20 P21 Priority 21 21 P22 Priority 22 22 P23 Priority 23 23 P24 Priority 24 24 P25 Priority 25 25 P26 Priority 26 26 P27 Priority 27 27 P28 Priority 28 28 P29 Priority 29 29 P30 Priority 30 30 P31 Priority 31 31 mclaim Machine Mode Claim/Complete Register 0x200004 mclaim [9:0] sth Supervisor Mode Priority Threshold Register 0x201000 priority 0 4 P0 Priority 0 (never interrupt) 0 P1 Priority 1 1 P2 Priority 2 2 P3 Priority 3 3 P4 Priority 4 4 P5 Priority 5 5 P6 Priority 6 6 P7 Priority 7 7 P8 Priority 8 8 P9 Priority 9 9 P10 Priority 10 10 P11 Priority 11 11 P12 Priority 12 12 P13 Priority 13 13 P14 Priority 14 14 P15 Priority 15 15 P16 Priority 16 16 P17 Priority 17 17 P18 Priority 18 18 P19 Priority 19 19 P20 Priority 20 20 P21 Priority 21 21 P22 Priority 22 22 P23 Priority 23 23 P24 Priority 24 24 P25 Priority 25 25 P26 Priority 26 26 P27 Priority 27 27 P28 Priority 28 28 P29 Priority 29 29 P30 Priority 30 30 P31 Priority 31 31 sclaim Supervisor Mode Claim/Complete Register 0x201004 sclaim [9:0] DMAC Direct Memory Access Controller System 0x03002000 0 0x1000 registers DMAC_NS 66 DMAC_IRQ_EN_REG0 DMAC IRQ Enable Register 0 0x0000 DMAC_IRQ_EN_REG1 DMAC IRQ Enable Register 1 0x0004 DMAC_IRQ_PEND_REG0 DMAC IRQ Pending Register 0 0x0010 DMAC_IRQ_PEND_REG1 DMAC IRQ Pending Register 1 0x0014 DMAC_AUTO_GATE_REG DMAC Auto Gating Register 0x0028 DMAC_STA_REG DMAC Status Register 0x0030 16 0x0040 DMAC_EN_REG%s DMAC Channel Enable Register 0x0100 16 0x0040 DMAC_PAU_REG%s DMAC Channel Pause Register 0x0104 16 0x0040 DMAC_DESC_ADDR_REG%s DMAC Channel Start Address Register 0x0108 16 0x0040 DMAC_CFG_REG%s DMAC Channel Configuration Register 0x010C 16 0x0040 DMAC_CUR_SRC_REG%s DMAC Channel Current Source Register 0x0110 16 0x0040 DMAC_CUR_DEST_REG%s DMAC Channel Current Destination Register 0x0114 16 0x0040 DMAC_BCNT_LEFT_REG%s DMAC Channel Byte Counter Left Register 0x0118 16 0x0040 DMAC_PARA_REG%s DMAC Channel Parameter Register 0x011C 16 0x0040 DMAC_MODE_REG%s DMAC Mode Register 0x0128 16 0x0040 DMAC_FDESC_ADDR_REG%s DMAC Former Descriptor Address Register 0x012C 16 0x0040 DMAC_PKG_NUM_REG%s DMAC Package Number Register 0x0130 THC Thermal Sensor Controller System 0x02009400 0 0x400 registers THS 74 THS_CTRL THS Control Register 0x0000 THS_EN THS Enable Register 0x0004 THS_PER THS Period Control Register 0x0008 THS_DATA_INTC THS Data Interrupt Control Register 0x0010 THS_SHUT_INTC THS Shut Interrupt Control Register 0x0014 THS_ALARM_INTC THS Alarm Interrupt Control Register 0x0018 THS_DATA_INTS THS Data Interrupt Status Register 0x0020 THS_SHUT_INTS THS Shut Interrupt Status Register 0x0024 THS_ALARMO_INTS THS Alarm off Interrupt Status Register 0x0028 THS_ALARM_INTS THS Alarm Interrupt Status Register 0x002C THS_FILTER THS Median Filter Control Register 0x0030 THS_ALARM_CTRL THS Alarm Threshold Control Register 0x0040 THS_SHUTDOWN_CTRL THS Shutdown Threshold Control Register 0x0080 THS_CDATA THS Calibration Data 0x00A0 THS_DATA THS Data Register 0x00C0 IOMMU I/O Memory Management Unit System 0x02010000 0 0x10000 registers IOMMU 80 IOMMU_RESET_REG IOMMU Reset Register 0x0010 IOMMU_ENABLE_REG IOMMU Enable Register 0x0020 IOMMU_BYPASS_REG IOMMU Bypass Register 0x0030 IOMMU_AUTO_GATING_REG IOMMU Auto Gating Register 0x0040 IOMMU_WBUF_CTRL_REG IOMMU Write Buffer Control Register 0x0044 IOMMU_OOO_CTRL_REG IOMMU Out of Order Control Register 0x0048 IOMMU_4KB_BDY_PRT_CTRL_REG IOMMU 4KB Boundary Protect Control Register 0x004C IOMMU_TTB_REG IOMMU Translation Table Base Register 0x0050 IOMMU_TLB_ENABLE_REG IOMMU TLB Enable Register 0x0060 IOMMU_TLB_PREFETCH_REG IOMMU TLB Prefetch Register 0x0070 IOMMU_TLB_FLUSH_ENABLE_REG IOMMU TLB Flush Enable Register 0x0080 IOMMU_TLB_IVLD_MODE_SEL_REG IOMMU TLB Invalidation Mode Select Register 0x0084 IOMMU_TLB_IVLD_STA_ADDR_REG IOMMU TLB Invalidation Start Address Register 0x0088 IOMMU_TLB_IVLD_END_ADDR_REG IOMMU TLB Invalidation End Address Register 0x008C IOMMU_TLB_IVLD_ADDR_REG IOMMU TLB Invalidation Address Register 0x0090 IOMMU_TLB_IVLD_ADDR_MASK_REG IOMMU TLB Invalidation Address Mask Register 0x0094 IOMMU_TLB_IVLD_ENABLE_REG IOMMU TLB Invalidation Enable Register 0x0098 IOMMU_PC_IVLD_MODE_SEL_REG IOMMU PC Invalidation Mode Select Register 0x009C IOMMU_PC_IVLD_ADDR_REG IOMMU PC Invalidation Address Register 0x00A0 IOMMU_PC_IVLD_STA_ADDR_REG IOMMU PC Invalidation Start Address Register 0x00A4 IOMMU_PC_IVLD_ENABLE_REG IOMMU PC Invalidation Enable Register 0x00A8 IOMMU_PC_IVLD_END_ADDR_REG IOMMU PC Invalidation End Address Register 0x00AC IOMMU_DM_AUT_CTRL0_REG IOMMU Domain Authority Control 0 Register 0x00B0 IOMMU_DM_AUT_CTRL1_REG IOMMU Domain Authority Control 1 Register 0x00B4 IOMMU_DM_AUT_CTRL2_REG IOMMU Domain Authority Control 2 Register 0x00B8 IOMMU_DM_AUT_CTRL3_REG IOMMU Domain Authority Control 3 Register 0x00BC IOMMU_DM_AUT_CTRL4_REG IOMMU Domain Authority Control 4 Register 0x00C0 IOMMU_DM_AUT_CTRL5_REG IOMMU Domain Authority Control 5 Register 0x00C4 IOMMU_DM_AUT_CTRL6_REG IOMMU Domain Authority Control 6 Register 0x00C8 IOMMU_DM_AUT_CTRL7_REG IOMMU Domain Authority Control 7 Register 0x00CC IOMMU_DM_AUT_OVWT_REG IOMMU Domain Authority Overwrite Register 0x00D0 IOMMU_INT_ENABLE_REG IOMMU Interrupt Enable Register 0x0100 IOMMU_INT_CLR_REG IOMMU Interrupt Clear Register 0x0104 IOMMU_INT_STA_REG IOMMU Interrupt Status Register 0x0108 IOMMU_INT_ERR_ADDR0_REG IOMMU Interrupt Error Address 0 0x0110 IOMMU_INT_ERR_ADDR1_REG IOMMU Interrupt Error Address 1 0x0114 IOMMU_INT_ERR_ADDR2_REG IOMMU Interrupt Error Address 2 0x0118 IOMMU_INT_ERR_ADDR3_REG IOMMU Interrupt Error Address 3 0x011C IOMMU_INT_ERR_ADDR4_REG IOMMU Interrupt Error Address 4 0x0120 IOMMU_INT_ERR_ADDR5_REG IOMMU Interrupt Error Address 5 0x0124 IOMMU_INT_ERR_ADDR6_REG IOMMU Interrupt Error Address 6 0x0128 IOMMU_INT_ERR_ADDR7_REG IOMMU Interrupt Error Address 7 0x0130 IOMMU_INT_ERR_ADDR8_REG IOMMU Interrupt Error Address 8 0x0134 IOMMU_INT_ERR_DATA0_REG IOMMU Interrupt Error Data 0 Register 0x0150 IOMMU_INT_ERR_DATA1_REG IOMMU Interrupt Error Data 1 Register 0x0154 IOMMU_INT_ERR_DATA2_REG IOMMU Interrupt Error Data 2 Register 0x0158 IOMMU_INT_ERR_DATA3_REG IOMMU Interrupt Error Data 3 Register 0x015C IOMMU_INT_ERR_DATA4_REG IOMMU Interrupt Error Data 4 Register 0x0160 IOMMU_INT_ERR_DATA5_REG IOMMU Interrupt Error Data 5 Register 0x0164 IOMMU_INT_ERR_DATA6_REG IOMMU Interrupt Error Data 6 Register 0x0168 IOMMU_INT_ERR_DATA7_REG IOMMU Interrupt Error Data 7 Register 0x0170 IOMMU_INT_ERR_DATA8_REG IOMMU Interrupt Error Data 8 Register 0x0174 IOMMU_L1PG_INT_REG IOMMU L1 Page Table Interrupt Register 0x0180 IOMMU_L2PG_INT_REG IOMMU L2 Page Table Interrupt Register 0x0184 IOMMU_VA_REG IOMMU Virtual Address Register 0x0190 IOMMU_VA_DATA_REG IOMMU Virtual Address Data Register 0x0194 IOMMU_VA_CONFIG_REG IOMMU Virtual Address Configuration Register 0x0198 IOMMU_PMU_ENABLE_REG IOMMU PMU Enable Register 0x0200 IOMMU_PMU_CLR_REG IOMMU PMU Clear Register 0x0210 IOMMU_PMU_ACCESS_LOW0_REG IOMMU PMU Access Low 0 Register 0x0230 IOMMU_PMU_ACCESS_HIGH0_REG IOMMU PMU Access High 0 Register 0x0234 IOMMU_PMU_HIT_LOW0_REG IOMMU PMU Hit Low 0 Register 0x0238 IOMMU_PMU_HIT_HIGH0_REG IOMMU PMU Hit High 0 Register 0x023C IOMMU_PMU_ACCESS_LOW1_REG IOMMU PMU Access Low 1 Register 0x0240 IOMMU_PMU_ACCESS_HIGH1_REG IOMMU PMU Access High 1 Register 0x0244 IOMMU_PMU_HIT_LOW1_REG IOMMU PMU Hit Low 1 Register 0x0248 IOMMU_PMU_HIT_HIGH1_REG IOMMU PMU Hit High 1 Register 0x024C IOMMU_PMU_ACCESS_LOW2_REG IOMMU PMU Access Low 2 Register 0x0250 IOMMU_PMU_ACCESS_HIGH2_REG IOMMU PMU Access High 2 Register 0x0254 IOMMU_PMU_HIT_LOW2_REG IOMMU PMU Hit Low 2 Register 0x0258 IOMMU_PMU_HIT_HIGH2_REG IOMMU PMU Hit High 2 Register 0x025C IOMMU_PMU_ACCESS_LOW3_REG IOMMU PMU Access Low 3 Register 0x0260 IOMMU_PMU_ACCESS_HIGH3_REG IOMMU PMU Access High 3 Register 0x0264 IOMMU_PMU_HIT_LOW3_REG IOMMU PMU Hit Low 3 Register 0x0268 IOMMU_PMU_HIT_HIGH3_REG IOMMU PMU Hit High 3 Register 0x026C IOMMU_PMU_ACCESS_LOW4_REG IOMMU PMU Access Low 4 Register 0x0270 IOMMU_PMU_ACCESS_HIGH4_REG IOMMU PMU Access High 4 Register 0x0274 IOMMU_PMU_HIT_LOW4_REG IOMMU PMU Hit Low 4 Register 0x0278 IOMMU_PMU_HIT_HIGH4_REG IOMMU PMU Hit High 4 Register 0x027C IOMMU_PMU_ACCESS_LOW5_REG IOMMU PMU Access Low 5 Register 0x0280 IOMMU_PMU_ACCESS_HIGH5_REG IOMMU PMU Access High 5 Register 0x0284 IOMMU_PMU_HIT_LOW5_REG IOMMU PMU Hit Low 5 Register 0x0288 IOMMU_PMU_HIT_HIGH5_REG IOMMU PMU Hit High 5 Register 0x028C IOMMU_PMU_ACCESS_LOW6_REG IOMMU PMU Access Low 6 Register 0x0290 IOMMU_PMU_ACCESS_HIGH6_REG IOMMU PMU Access High 6 Register 0x0294 IOMMU_PMU_HIT_LOW6_REG IOMMU PMU Hit Low 6 Register 0x0298 IOMMU_PMU_HIT_HIGH6_REG IOMMU PMU Hit High 6 Register 0x029C IOMMU_PMU_ACCESS_LOW7_REG IOMMU PMU Access Low 7 Register 0x02D0 IOMMU_PMU_ACCESS_HIGH7_REG IOMMU PMU Access High 7 Register 0x02D4 IOMMU_PMU_HIT_LOW7_REG IOMMU PMU Hit Low 7 Register 0x02D8 IOMMU_PMU_HIT_HIGH7_REG IOMMU PMU Hit High 7 Register 0x02DC IOMMU_PMU_ACCESS_LOW8_REG IOMMU PMU Access Low 8 Register 0x02E0 IOMMU_PMU_ACCESS_HIGH8_REG IOMMU PMU Access High 8 Register 0x02E4 IOMMU_PMU_HIT_LOW8_REG IOMMU PMU Hit Low 8 Register 0x02E8 IOMMU_PMU_HIT_HIGH8_REG IOMMU PMU Hit High 8 Register 0x02EC IOMMU_PMU_TL_LOW0_REG IOMMU Total Latency Low 0 Register 0x0300 IOMMU_PMU_TL_HIGH0_REG IOMMU Total Latency High 0 Register 0x0304 IOMMU_PMU_ML0_REG IOMMU Max Latency 0 Register 0x0308 IOMMU_PMU_TL_LOW1_REG IOMMU Total Latency Low 1 Register 0x0310 IOMMU_PMU_TL_HIGH1_REG IOMMU Total Latency High 1 Register 0x0314 IOMMU_PMU_ML1_REG IOMMU Max Latency 1 Register 0x0318 IOMMU_PMU_TL_LOW2_REG IOMMU Total Latency Low 2 Register 0x0320 IOMMU_PMU_TL_HIGH2_REG IOMMU Total Latency High 2 Register 0x0324 IOMMU_PMU_ML2_REG IOMMU Max Latency 2 Register 0x0328 IOMMU_PMU_TL_LOW3_REG IOMMU Total Latency Low 3 Register 0x0330 IOMMU_PMU_TL_HIGH3_REG IOMMU Total Latency High 3 Register 0x0334 IOMMU_PMU_ML3_REG IOMMU Max Latency 3 Register 0x0338 IOMMU_PMU_TL_LOW4_REG IOMMU Total Latency Low 4 Register 0x0340 IOMMU_PMU_TL_HIGH4_REG IOMMU Total Latency High 4 Register 0x0344 IOMMU_PMU_ML4_REG IOMMU Max Latency 4 Register 0x0348 IOMMU_PMU_TL_LOW5_REG IOMMU Total Latency Low 5 Register 0x0350 IOMMU_PMU_TL_HIGH5_REG IOMMU Total Latency High 5 Register 0x0354 IOMMU_PMU_ML5_REG IOMMU Max Latency 5 Register 0x0358 IOMMU_PMU_TL_LOW6_REG IOMMU Total Latency Low 6 Register 0x0360 IOMMU_PMU_TL_HIGH6_REG IOMMU Total Latency High 6 Register 0x0364 IOMMU_PMU_ML6_REG IOMMU Max Latency 6 Register 0x0368 DSP_MSGBOX DSP Message Box System 0x01701000 0 0x1000 registers 2 0x0100 MSGBOX_RD_IRQ_EN_REG_%s MSGBOX Read IRQ Enable Register 0x0020 2 0x0100 MSGBOX_RD_IRQ_STATUS_REG_%s MSGBOX Read IRQ Status Register 0x0024 2 0x0100 MSGBOX_WR_IRQ_EN_REG_%s MSGBOX Write IRQ Enable Register 0x0030 2 0x0100 MSGBOX_WR_IRQ_STATUS_REG_%s MSGBOX Write IRQ Status Register 0x0034 2 0x0100 MSGBOX_DEBUG_REG_%s MSGBOX Debug Register 0x0040 2 0x0100 MSGBOX_FIFO_STATUS_REG_N%s MSGBOX FIFO Status Register 0x0050 3 0x0004 MSGBOX_FIFO_STATUS_REG_P%s MSGBOX FIFO Status Register 0 2 0x0100 MSGBOX_MSG_STATUS_REG_N%s MSGBOX Message Status Register 0x0060 3 0x0004 MSGBOX_MSG_STATUS_REG_P%s MSGBOX Message Status Register 0 2 0x0100 MSGBOX_MSG_REG_N%s MSGBOX Message Queue Register 0x0070 3 0x0004 MSGBOX_MSG_REG_P%s MSGBOX Message Queue Register 0 2 0x0100 MSGBOX_WR_INT_THRESHOLD_REG_N%s MSGBOX Write IRQ Threshold Register 0x0080 3 0x0004 MSGBOX_WR_INT_THRESHOLD_REG_P%s MSGBOX Write IRQ Threshold Register 0 RISC_V_MSGBOX RISC-V Message Box System 0x0601F000 0 0x1000 registers RISC-V_MBOX_RISC-V 144 RISC-V_MBOX_DSP 145 2 0x0100 MSGBOX_RD_IRQ_EN_REG_%s MSGBOX Read IRQ Enable Register 0x0020 2 0x0100 MSGBOX_RD_IRQ_STATUS_REG_%s MSGBOX Read IRQ Status Register 0x0024 2 0x0100 MSGBOX_WR_IRQ_EN_REG_%s MSGBOX Write IRQ Enable Register 0x0030 2 0x0100 MSGBOX_WR_IRQ_STATUS_REG_%s MSGBOX Write IRQ Status Register 0x0034 2 0x0100 MSGBOX_DEBUG_REG_%s MSGBOX Debug Register 0x0040 2 0x0100 MSGBOX_FIFO_STATUS_REG_N%s MSGBOX FIFO Status Register 0x0050 3 0x0004 MSGBOX_FIFO_STATUS_REG_P%s MSGBOX FIFO Status Register 0 2 0x0100 MSGBOX_MSG_STATUS_REG_N%s MSGBOX Message Status Register 0x0060 3 0x0004 MSGBOX_MSG_STATUS_REG_P%s MSGBOX Message Status Register 0 2 0x0100 MSGBOX_MSG_REG_N%s MSGBOX Message Queue Register 0x0070 3 0x0004 MSGBOX_MSG_REG_P%s MSGBOX Message Queue Register 0 2 0x0100 MSGBOX_WR_INT_THRESHOLD_REG_N%s MSGBOX Write IRQ Threshold Register 0x0080 3 0x0004 MSGBOX_WR_INT_THRESHOLD_REG_P%s MSGBOX Write IRQ Threshold Register 0 Spinlock Spinlock System 0x03005000 0 0x1000 registers SPINLOCK 70 SPINLOCK_SYSTATUS_REG Spinlock System Status Register 0x0000 SPINLOCK_STATUS_REG Spinlock Status Register 0x0010 SPINLOCK_IRQ_EN_REG Spinlock Interrupt Enable Register 0x0020 SPINLOCK_IRQ_STA_REG Spinlock Interrupt Status Register 0x0040 SPINLOCK_LOCKID0_REG Spinlock Lockid0 Register 0x0080 SPINLOCK_LOCKID1_REG Spinlock Lockid1 Register 0x0084 SPINLOCK_LOCKID2_REG Spinlock Lockid2 Register 0x0088 SPINLOCK_LOCKID3_REG Spinlock Lockid3 Register 0x008C SPINLOCK_LOCKID4_REG Spinlock Lockid4 Register 0x0090 32 0x0004 SPINLOCK_LOCK_REG%s Spinlock Register 0x0100 RTC Real Time CLock System 0x07090000 0 0x1000 registers LOSC_CTRL_REG Low Oscillator Control Register 0x0000 LOSC_AUTO_SWT_STA_REG LOSC Auto Switch Status Register 0x0004 INTOSC_CLK_PRESCAL_REG Internal OSC Clock Pre-scalar Register 0x0008 RTC_DAY_REG RTC Year-Month-Day Register 0x0010 RTC_HH_MM_SS_REG RTC Hour-Minute-Second Register 0x0014 ALARM0_DAY_SET_REG Alarm 0 Day Setting Register 0x0020 ALARM0_CUR_VLU_REG Alarm 0 Counter Current Value Register 0x0024 ALARM0_ENABLE_REG Alarm 0 Enable Register 0x0028 ALARM0_IRQ_EN Alarm 0 IRQ Enable Register 0x002C ALARM0_IRQ_STA_REG Alarm 0 IRQ Status Register 0x0030 ALARM_CONFIG_REG Alarm Configuration Register 0x0050 _32K_FOUT_CTRL_GATING_REG 32K Fanout Control Gating Register 0x0060 8 0x04 GP_DATA_REG%s General Purpose Register 0x0100 FBOOT_INFO_REG0 Fast Boot Information Register0 0x0120 FBOOT_INFO_REG1 Fast Boot Information Register1 0x0124 DCXO_CTRL_REG DCXO Control Register 0x0160 RTC_VIO_REG RTC_VIO Regulation Register 0x0190 IC_CHARA_REG IC Characteristic Register 0x01F0 VDD_OFF_GATING_CTRL_REG VDD Off Gating Control Register 0x01F4 EFUSE_HV_PWRSWT_CTRL_REG Efuse High Voltage Power Switch Control Register 0x0204 RTC_SPI_CLK_CTRL_REG RTC SPI Clock Control Register 0x0310 TCON_LCD0 Timing COntroller LCD VideoOutputInterfaces 0x05461000 0 0x1000 registers LCD_GCTL_REG LCD Global Control Register 0x0000 LCD_GINT0_REG LCD Global Interrupt Register0 0x0004 LCD_GINT1_REG LCD Global Interrupt Register1 0x0008 LCD_FRM_CTL_REG LCD FRM Control Register 0x0010 6 0x04 LCD_FRM_SEED_REG%s LCD FRM Seed Register 0x0014 4 0x04 LCD_FRM_TAB_REG%s LCD FRM Table Register 0x002C LCD_3D_FIFO_REG LCD 3D FIFO Register 0x003C LCD_CTL_REG LCD Control Register 0x0040 LCD_DCLK_REG LCD Data Clock Register 0x0044 LCD_BASIC0_REG LCD Basic Timing Register0 0x0048 LCD_BASIC1_REG LCD Basic Timing Register1 0x004C LCD_BASIC2_REG LCD Basic Timing Register2 0x0050 LCD_BASIC3_REG LCD Basic Timing Register3 0x0054 LCD_HV_IF_REG LCD HV Panel Interface Register 0x0058 LCD_CPU_IF_REG LCD CPU Panel Interface Register 0x0060 LCD_CPU_WR_REG LCD CPU Panel Write Data Register 0x0064 LCD_CPU_RD0_REG LCD CPU Panel Read Data Register0 0x0068 LCD_CPU_RD1_REG LCD CPU Panel Read Data Register1 0x006C LCD_LVDS_IF_REG LCD LVDS Configure Register 0x0084 LCD_IO_POL_REG LCD IO Polarity Register 0x0088 LCD_IO_TRI_REG LCD IO Control Register 0x008C LCD_DEBUG_REG LCD Debug Register 0x00FC LCD_CEU_CTL_REG LCD CEU Control Register 0x0100 3 0x04 LCD_CEU_COEF_MUL_REG%s LCD CEU Coefficient Register0 0x0110 3 0x10 LCD_CEU_COEF_ADD_REG%s LCD CEU Coefficient Register1 0x011C 3 0x04 LCD_CEU_COEF_RANG_REG%s LCD CEU Coefficient Register2 0x0140 LCD_CPU_TRI0_REG LCD CPU Panel Trigger Register0 0x0160 LCD_CPU_TRI1_REG LCD CPU Panel Trigger Register1 0x0164 LCD_CPU_TRI2_REG LCD CPU Panel Trigger Register2 0x0168 LCD_CPU_TRI3_REG LCD CPU Panel Trigger Register3 0x016C LCD_CPU_TRI4_REG LCD CPU Panel Trigger Register4 0x0170 LCD_CPU_TRI5_REG LCD CPU Panel Trigger Register5 0x0174 LCD_CMAP_CTL_REG LCD Color Map Control Register 0x0180 LCD_CMAP_ODD0_REG LCD Color Map Odd Line Register0 0x0190 LCD_CMAP_ODD1_REG LCD Color Map Odd Line Register1 0x0194 LCD_CMAP_EVEN0_REG LCD Color Map Even Line Register0 0x0198 LCD_CMAP_EVEN1_REG LCD Color Map Even Line Register1 0x019C LCD_SAFE_PERIOD_REG LCD Safe Period Register 0x01F0 LCD_LVDS0_ANA_REG LCD LVDS Analog Register 0 0x0220 LCD_LVDS1_ANA_REG LCD LVDS Analog Register 1 0x0224 LCD_SYNC_CTL_REG LCD Sync Control Register 0x0230 LCD_SYNC_POS_REG LCD Sync Position Register 0x0234 LCD_SLAVE_STOP_POS_REG LCD Slave Stop Position Register 0x0238 LCD_LVDS1_IF_REG LCD LVDS1 IF Register 0x0244 256 0x04 LCD_GAMMA_TABLE_REG%s LCD Gamma Table Register 0x0400 TCON_TV0 Timing COntroller TV VideoOutputInterfaces 0x05470000 0 0x1000 registers TV_GCTL_REG TV Global Control Register 0x0000 TV_GINT0_REG TV Global Interrupt Register0 0x0004 TV_GINT1_REG TV Global Interrupt Register1 0x0008 TV_SRC_CTL_REG TV Source Control Register 0x0040 TV_CTL_REG TV Control Register 0x0090 TV_BASIC0_REG TV Basic Timing Register0 0x0094 TV_BASIC1_REG TV Basic Timing Register1 0x0098 TV_BASIC2_REG TV Basic Timing Register2 0x009C TV_BASIC3_REG TV Basic Timing Register3 0x00A0 TV_BASIC4_REG TV Basic Timing Register4 0x00A4 TV_BASIC5_REG TV Basic Timing Register5 0x00A8 TV_IO_POL_REG TV SYNC Signal Polarity Register 0x0088 TV_IO_TRI_REG TV SYNC Signal IO Control Register 0x008C TV_DEBUG_REG TV Debug Register 0x00FC TV_CEU_CTL_REG TV CEU Control Register 0x0100 11 0x04 TV_CEU_COEF_MUL_REG%s TV CEU Coefficient Register0 0x0110 3 0x04 TV_CEU_COEF_RANG_REG%s TV CEU Coefficient Register2 0x0140 TV_SAFE_PERIOD_REG TV Safe Period Register 0x01F0 TV_FILL_CTL_REG TV Fill Data Control Register 0x0300 3 0x0C TV_FILL_BEGIN_REG%s TV Fill Data Begin Register 0x0304 3 0x0C TV_FILL_END_REG%s TV Fill Data End Register 0x0308 3 0x0C TV_FILL_DATA_REG%s TV Fill Data Value Register 0x030C TV_DATA_IO_POL0_REG TCON Data IO Polarity Control0 0x0330 TV_DATA_IO_POL1_REG TCON Data IO Polarity Control1 0x0334 TV_DATA_IO_TRI0_REG TCON Data IO Enable Control0 0x0338 TV_DATA_IO_TRI1_REG TCON Data IO Enable Control1 0x033C TV_PIXELDEPTH_MODE_REG TV Pixeldepth Mode Control Register 0x0340 TVE_TOP TV Encoder TOP VideoOutputInterfaces 0x05600000 0 0x4000 registers TVE_DAC_MAP TV Encoder DAC MAP Register 0x0020 TVE_DAC_STATUS TV Encoder DAC STAUTS Register 0x0024 TVE_DAC_CFG0 TV Encoder DAC CFG0 Register 0x0028 TVE_DAC_CFG1 TV Encoder DAC CFG1 Register 0x002C TVE_DAC_CFG2 TV Encoder DAC CFG2 Register 0x0030 TVE_DAC_CFG3 TV Encoder DAC CFG2 Register 0x0034 TVE_DAC_TEST TV Encoder DAC TEST Register 0x00F0 TVE TV Encoder VideoOutputInterfaces 0x05604000 0 0x4000 registers TVE_000_REG TV Encoder Clock Gating Register 0x0000 TVE_004_REG TV Encoder Configuration Register 0x0004 TVE_008_REG TV Encoder DAC Register1 0x0008 TVE_00C_REG TV Encoder Notch and DAC Delay Register 0x000C TVE_010_REG TV Encoder Chroma Frequency Register 0x0010 TVE_014_REG TV Encoder Front/Back Porch Register 0x0014 TVE_018_REG TV Encoder HD Mode VSYNC Register 0x0018 TVE_01C_REG TV Encoder Line Number Register 0x001C TVE_020_REG TV Encoder Level Register 0x0020 TVE_024_REG TV Encoder DAC Register2 0x0024 TVE_030_REG TV Encoder Auto Detection Enable Register 0x0030 TVE_034_REG TV Encoder Auto Detection Interrupt Status Register 0x0034 TVE_038_REG TV Encoder Auto Detection Status Register 0x0038 TVE_03C_REG TV Encoder Auto Detection De-bounce Setting Register 0x003C TVE_0F8_REG TV Encoder Auto Detect Configuration Register0 0x00F8 TVE_0FC_REG TV Encoder Auto Detect Configuration Register1 0x00FC TVE_100_REG TV Encoder Color Burst Phase Reset Configuration Register 0x0100 TVE_104_REG TV Encoder VSYNC Number Register 0x0104 TVE_108_REG TV Encoder Notch Filter Frequency Register 0x0108 TVE_10C_REG TV Encoder Cb/Cr Level/Gain Register 0x010C TVE_110_REG TV Encoder Tint and Color Burst Phase Register 0x0110 TVE_114_REG TV Encoder Burst Width Register 0x0114 TVE_118_REG TV Encoder Cb/Cr Gain Register 0x0118 TVE_11C_REG TV Encoder Sync and VBI Level Register 0x011C TVE_120_REG TV Encoder White Level Register 0x0120 TVE_124_REG TV Encoder Video Active Line Register 0x0124 TVE_128_REG TV Encoder Video Chroma BW and CompGain Register 0x0128 TVE_12C_REG TV Encoder Register 0x012C TVE_130_REG TV Encoder Re-sync Parameters Register 0x0130 TVE_134_REG TV Encoder Slave Parameter Register 0x0134 TVE_138_REG TV Encoder Configuration Register0 0x0138 TVE_13C_REG TV Encoder Configuration Register1 0x013C TVE_380_REG TV Encoder Low Pass Control Register 0x0380 TVE_384_REG TV Encoder Low Pass Filter Control Register 0x0384 CSIC CMOS Sensor Interface Controller VideoInputInterfaces 0x05800000 0 0x400000 registers CSI_DMA0 111 CSI_DMA1 112 CSI_TOP_PKT 122 CSIC_CCU CSIC_CCU 0x0000 CCU_CLK_MODE_REG CCU Clock Mode Register 0x0000 CCU_PARSER_CLK_EN_REG CCU Parser Clock Enable Register 0x0004 CCU_POST0_CLK_EN_REG CCU Post0 Clock Enable Register 0x000C CSIC_TOP CSIC_TOP 0x0800 CSIC_TOP_EN_REG CSIC TOP Enable Register 0x0000 CSIC_PTN_GEN_EN_REG CSIC Pattern Generation Enable Register 0x0004 CSIC_PTN_CTRL_REG CSIC Pattern Control Register 0x0008 CSIC_PTN_LEN_REG CSIC Pattern Generation Length Register 0x0020 CSIC_PTN_ADDR_REG CSIC Pattern Generation Address Register 0x0024 CSIC_PTN_ISP_SIZE_REG CSIC Pattern ISP Size Register 0x0028 CSIC_DMA0_INPUT_SEL_REG CSIC DMA0 Input Select Register 0x00A0 CSIC_DMA1_INPUT_SEL_REG CSIC DMA1 Input Select Register 0x00A4 CSIC_BIST_CS_REG CSIC BIST CS Register 0x00DC CSIC_BIST_CONTROL_REG CSIC BIST Control Register 0x00E0 CSIC_BIST_START_REG CSIC BIST Start Register 0x00E4 CSIC_BIST_END_REG CSIC BIST End Register 0x00E8 CSIC_BIST_DATA_MASK_REG CSIC BIST Data Mask Register 0x00EC CSIC_MBUS_REQ_MAX_REG CSIC MBUS REQ MAX Register 0x00F0 CSIC_MULF_MOD_REG CSIC Multi-Frame Mode Register 0x0100 CSIC_MULF_INT_REG CSIC Multi-Frame Interrupt Register 0x0104 CSIC_PARSER0 CSIC_PARSER0 0x1000 PRS_EN_REG Parser Enable Register 0x0000 PRS_NCSIC_IF_CFG_REG Parser NCSIC Interface Configuration Register 0x0004 PRS_CAP_REG Parser Capture Register 0x000C CSIC_PRS_SIGNAL_STA_REG CSIC Parser Signal Status Register 0x0010 CSIC_PRS_NCSIC_BT656_HEAD_CFG_REG CSIC Parser NCSIC BT656 Header Configuration Register 0x0014 PRS_C0_INFMT_REG Parser Channel_0 Input Format Register 0x0024 PRS_C0_OUTPUT_HSIZE_REG Parser Channel_0 Output Horizontal Size Register 0x0028 PRS_C0_OUTPUT_VSIZE_REG Parser Channel_0 Output Vertical Size Register 0x002C PRS_C0_INPUT_PARA0_REG Parser Channel_0 Input Parameter0 Register 0x0030 PRS_C0_INPUT_PARA1_REG Parser Channel_0 Input Parameter1 Register 0x0034 PRS_C0_INPUT_PARA2_REG Parser Channel_0 Input Parameter2 Register 0x0038 PRS_C0_INPUT_PARA3_REG Parser Channel_0 Input Parameter3 Register 0x003C PRS_C0_INT_EN_REG Parser Channel_0 Interrupt Enable Register 0x0040 PRS_C0_INT_STA_REG Parser Channel_0 Interrupt Status Register 0x0044 PRS_CH0_LINE_TIME_REG Parser Channel_0 Line Time Register 0x0048 PRS_C1_INFMT_REG Parser Channel_1 Input Format Register 0x0124 PRS_C1_OUTPUT_HSIZE_REG Parser Channel_1 Output Horizontal Size 0x0128 PRS_C1_OUTPUT_VSIZE_REG Parser Channel_1 Output Vertical Size Register 0x012C PRS_C1_INPUT_PARA0_REG Parser Channel_1 Input Parameter0 Register 0x0130 PRS_C1_INPUT_PARA1_REG Parser Channel_1 Input Parameter1 Register 0x0134 PRS_C1_INPUT_PARA2_REG Parser Channel_1 Input Parameter2 Register 0x0138 PRS_C1_INPUT_PARA3_REG Parser Channel_1 Input Parameter3 Register 0x013C PRS_C1_INT_EN_REG Parser Channel_1 Interrupt Enable Register 0x0140 PRS_C1_INT_STA_REG Parser Channel_1 Interrupt Status Register 0x0144 PRS_CH1_LINE_TIME_REG Parser Channel_1 Line Time Register 0x0148 PRS_C2_INFMT_REG Parser Channel_2 Input Format Register 0x0224 PRS_C2_OUTPUT_HSIZE_REG Parser Channel_2 Output Horizontal Size Register 0x0228 PRS_C2_OUTPUT_VSIZE_REG Parser Channel_2 Output Vertical Size Register 0x022C PRS_C2_INPUT_PARA0_REG Parser Channel_2 Input Parameter0 Register 0x0230 PRS_C2_INPUT_PARA1_REG Parser Channel_2 Input Parameter1 Register 0x0234 PRS_C2_INPUT_PARA2_REG Parser Channel_2 Input Parameter2 Register 0x0238 PRS_C2_INPUT_PARA3_REG Parser Channel_2 Input Parameter3 Register 0x023C PRS_C2_INT_EN_REG Parser Channel_2 Interrupt Enable Register 0x0240 PRS_C2_INT_STA_REG Parser Channel_2 Interrupt Status Register 0x0244 PRS_CH2_LINE_TIME_REG Parser Channel_2 Line Time Register 0x0248 PRS_C3_INFMT_REG Parser Channel_3 Input Format Register 0x0324 PRS_C3_OUTPUT_HSIZE_REG Parser Channel_3 Output Horizontal Size Register 0x0328 PRS_C3_OUTPUT_VSIZE_REG Parser Channel_3 Output Vertical Size Register 0x032C PRS_C3_INPUT_PARA0_REG Parser Channel_3 Input Parameter0 Register 0x0330 PRS_C3_INPUT_PARA1_REG Parser Channel_3 Input Parameter1 Register 0x0334 PRS_C3_INPUT_PARA2_REG Parser Channel_3 Input Parameter2 Register 0x0338 PRS_C3_INPUT_PARA3_REG Parser Channel_3 Input Parameter3 Register 0x033C PRS_C3_INT_EN_REG Parser Channel_3 Interrupt Enable Register 0x0340 PRS_C3_INT_STA_REG Parser Channel_3 Interrupt Status Register 0x0344 PRS_CH3_LINE_TIME_REG Parser Channel_3 Line Time Register 0x0348 CSIC_PRS_NCSIC_RX_SIGNAL0_DLY_ADJ_REG CSIC Parser NCSIC RX Signal0 Delay Adjust Register 0x0500 CSIC_PRS_NCSIC_RX_SIGNAL5_DLY_ADJ_REG CSIC Parser NCSIC RX Signal5 Delay Adjust Register 0x0514 CSIC_PRS_NCSIC_RX_SIGNAL6_DLY_ADJ_REG CSIC Parser NCSIC RX Signal6 Delay Adjust Register 0x0518 2 0x0200 CSIC_DMA%s CSIC_DMA 0x9000 CSIC_DMA_EN_REG CSIC DMA Enable Register 0x0000 CSIC_DMA_CFG_REG CSIC DMA Configuration Register 0x0004 CSIC_DMA_HSIZE_REG CSIC DMA Horizontal Size Register 0x0010 CSIC_DMA_VSIZE_REG CSIC DMA Vertical Size Register 0x0014 CSIC_DMA_F0_BUFA_REG CSIC DMA FIFO 0 Output Buffer-A Address Register 0x0020 CSIC_DMA_F0_BUFA_RESULT_REG CSIC DMA FIFO 0 Output Buffer-A Address Result Register 0x0024 CSIC_DMA_F1_BUFA_REG CSIC DMA FIFO 1 Output Buffer-A Address Register 0x0028 CSIC_DMA_F1_BUFA_RESULT_REG CSIC DMA FIFO 1 Output Buffer-A Address Result Register 0x002C CSIC_DMA_F2_BUFA_REG CSIC DMA FIFO 2 Output Buffer-A Address Register 0x0030 CSIC_DMA_F2_BUFA_RESULT_REG CSIC DMA FIFO 2 Output Buffer-A Address Result Register 0x0034 CSIC_DMA_BUF_LEN_REG CSIC DMA Buffer Length Register 0x0038 CSIC_DMA_FLIP_SIZE_REG CSIC DMA Flip Size Register 0x003C CSIC_DMA_VI_TO_TH0_REG CSIC DMA Video Input Timeout Threshold0 Register 0x0040 CSIC_DMA_VI_TO_TH1_REG CSIC DMA Video Input Timeout Threshold1 Register 0x0044 CSIC_DMA_VI_TO_CNT_VAL_REG CSIC DMA Video Input Timeout Counter Value Register 0x0048 CSIC_DMA_CAP_STA_REG CSIC DMA Capture Status Register 0x004C CSIC_DMA_INT_EN_REG CSIC DMA Interrupt Enable Register 0x0050 CSIC_DMA_INT_STA_REG CSIC DMA Interrupt Status Register 0x0054 CSIC_DMA_LINE_CNT_REG CSIC DMA LINE Counter Register 0x0058 CSIC_DMA_FRM_CNT_REG CSIC DMA Frame Counter Register 0x005C CSIC_DMA_FRM_CLK_CNT_REG CSIC DMA Frame Clock Counter Register 0x0060 CSIC_DMA_ACC_ITNL_CLK_CNT_REG CSIC DMA Accumulated And Internal Clock Counter Register 0x0064 CSIC_DMA_FIFO_STAT_REG CSIC DMA FIFO Statistic Register 0x0068 CSIC_DMA_FIFO_THRS_REG CSIC DMA FIFO Threshold Register 0x006C CSIC_DMA_PCLK_STAT_REG CSIC DMA PCLK Statistic Register 0x0070 CSIC_DMA_BUF_ADDR_FIFO0_ENTRY_REG CSIC DMA BUF Address FIFO0 Entry Register 0x0080 CSIC_DMA_BUF_ADDR_FIFO1_ENTRY_REG CSIC DMA BUF Address FIFO1 Entry Register 0x0084 CSIC_DMA_BUF_ADDR_FIFO2_ENTRY_REG CSIC DMA BUF Address FIFO2 Entry Register 0x0088 CSIC_DMA_BUF_TH_REG CSIC DMA BUF Threshold Register 0x008C CSIC_DMA_BUF_ADDR_FIFO_CON_REG CSIC DMA BUF Address FIFO Content Register 0x0090 CSIC_DMA_STORED_FRM_CNT_REG CSIC DMA Stored Frame Counter Register 0x0094 CSIC_FEATURE_REG CSIC DMA Feature List Register 0x01F4 TVD_TOP Television Decoder TOP VideoInputInterfaces 0x05C00000 0 0x1000 registers TVD 123 TVD_TOP_MAP TVD TOP MAP Register 0x0000 TVD_3D_CTL1 TVD 3D DMA CONTROL Register1 0x0008 TVD_3D_CTL2 TVD 3D DMA CONTROL Register2 0x000C TVD_3D_CTL3 TVD 3D DMA CONTROL Register3 0x0010 TVD_3D_CTL4 TVD 3D DMA CONTROL Register4 0x0014 TVD_3D_CTL5 TVD 3D DMA CONTROL Register5 0x0018 4 0x20 TVD_TOP_CTL%s TVD TOP CONTROL Register 0x0024 4 0x20 TVD_ADC_CTL%s TVD ADC CONTROL Register 0x0028 4 0x20 TVD_ADC_CFG%s TVD ADC CONFIGURATION Register 0x002C TVD0 Television Decoder VideoInputInterfaces 0x05C01000 0 0x1000 registers TVD_EN TVD MODULE CONTROL Register 0x0000 TVD_MODE TVD MODE CONTROL Register 0x0004 TVD_CLAMP_AGC1 TVD CLAMP And AGC CONTROL Register1 0x0008 TVD_CLAMP_AGC2 TVD CLAMP And AGC CONTROL Register2 0x000C TVD_HLOCK1 TVD HLOCK CONTROL Register1 0x0010 TVD_HLOCK2 TVD HLOCK CONTROL Register2 0x0014 TVD_HLOCK3 TVD HLOCK CONTROL Register3 0x0018 TVD_HLOCK4 TVD HLOCK CONTROL Register4 0x001C TVD_HLOCK5 TVD HLOCK CONTROL Register5 0x0020 TVD_VLOCK1 TVD VLOCK CONTROL Register1 0x0024 TVD_VLOCK2 TVD VLOCK CONTROL Register2 0x0028 TVD_CLOCK1 TVD CHROMA LOCK CONTROL Register1 0x0030 TVD_CLOCK2 TVD CHROMA LOCK CONTROL Register2 0x0034 TVD_YC_SEP1 TVD YC SEPERATION CONROL Register1 0x0040 TVD_YC_SEP2 TVD YC SEPERATION CONROL Register2 0x0044 TVD_ENHANCE1 TVD ENHANCEMENT CONTROL Register1 0x0050 TVD_ENHANCE2 TVD ENHANCEMENT CONTROL Register2 0x0054 TVD_ENHANCE3 TVD ENHANCEMENT CONTROL Register3 0x0058 TVD_WB1 TVD WB DMA CONTROL Register1 0x0060 TVD_WB2 TVD WB DMA CONTROL Register2 0x0064 TVD_WB3 TVD WB DMA CONTROL Register3 0x0068 TVD_WB4 TVD WB DMA CONTROL Register4 0x006C TVD_IRQ_CTL TVD DMA Interrupt Control Register 0x0080 TVD_IRQ_STATUS TVD DMA Interrupt Status Register 0x0090 TVD_DEBUG1 TVD DEBUG CONTROL Register1 0x0100 TVD_STATUS1 TVD DEBUG STATUS Register1 0x0180 TVD_STATUS2 TVD DEBUG STATUS Register2 0x0184 TVD_STATUS3 TVD DEBUG STATUS Register3 0x0188 TVD_STATUS4 TVD DEBUG STATUS Register4 0x018C TVD_STATUS5 TVD DEBUG STATUS Register5 0x0190 TVD_STATUS6 TVD DEBUG STATUS Register6 0x0194 3 0x1000 SMHC[%s] SD/MMC Host Controller Memory 0x04020000 0 0x1000 registers SMHC0 56 SMHC1 57 SMHC2 58 SMHC_CTRL Control Register 0x0000 FIFO_AC_MOD FIFO Accesss Mode [31:31] DMA DMA bus 0 AHB AHB bus 1 TIME_UNIT_CMD Time unit for command line [12:12] C1 1 card clock period 0 C256 256 card clock period 1 TIME_UNIT_DAT Time unit for data line [11:11] C1 1 card clock period 0 C256 256 card clock period 1 DDR_MOD_SEL DDR Mode Select [10:10] SDR SDR mode 0 DDR DDR mode 1 CD_DBC_ENB Card Detect (Data[3] status) De-bounce Enable [8:8] disable Disable de-bounce 0 enable Enable de-bounce 1 DMA_ENB DMA Global Enable [5:5] disable Disable DMA to transfer data via AHB bus 0 enable Enable DMA to transfer data 1 INE_ENB GLobal Interrupt Enable [4:4] disable Disable interrupts 0 enable Enable interrupts 1 DMA_RST DMA Reset [2:2] FIFO_RST FIFO Reset [1:1] no_effect 0 reset 1 SOFT_RST Software Reset [0:0] no_effect 0 reset 1 SMHC_CLKDIV Clock Control Register 0x0004 MASK_DATA0 [31:31] not_mask Do not mask data0 when update clock 0 mask Mask data0 when update clock 1 CCLK_CTRL Card Clock Output Control [17:17] on Card clock is always on 0 off_idle Turn off card clock when FSM is in IDLE state 1 CCLK_ENB Card Clock Enable [16:16] off Card Clock is off 0 on Card Clock is on 1 CCLK_DIV Card Clock Divider [7:0] SMHC_TMOUT Time Out Register 0x0008 DTO_LMT Data Iimeout Limit [31:8] RTO_LMT Response Timeout Limit [7:0] SMHC_CTYPE Bus Width Register 0x000C CARD_WID Card Width [1:0] b1 1-bit width 0b00 b4 4-bit width 0b01 b8 8-bit width 0b1x SMHC_BLKSIZ Block Size Register 0x0010 BLK_SZ Block SIze [15:0] SMHC_BYTCNT Byte Count Register 0x0014 SMHC_CMD Command Register 0x0018 CMD_LOAD Start Command [31:31] VOL_SW Voltage Switch [28:28] normal Normal command 0 voltage_switch Voltage switch command, set for CMD11 only 1 BOOT_ABT Boot Abort [27:27] EXP_BOOT_ACK Expect Boot Acknowledge [26:26] BOOT_MOD Boot Mode [25:24] normal Normal command 0b00 mandatory_boot Mandatory Boot operation 0b01 alternate_boot Alternate Boot operation 0b10 PRG_CLK Change Clock [21:21] normal Normal command 0 change Change Card Clock 1 SEND_INIT_SEQ Send Initialization [15:15] normal Normal command sending 0 init_cmd Send initialization sequence before sending this command 1 STOP_ABT_CMD Stop Abort Command [14:14] normal Normal command sending 0 stop Send Stop or Abort command to stop the current data transfer in progress 1 WAIT_PRE_OVER Wait for Data Transfer Over [13:13] at_once Send command at once, does not care about data transferring 0 wait Wait for data transfer completion before sending the current command 1 STOP_CMD_FLAG Send Stop CMD Automatically (CMD12) [12:12] no_stop Do not send stop command at the end of the data transfer 0 auto_stop Send stop command automatically at the end of the data transfer 1 TRANS_MODE Transfer Mode [11:11] block Block data transfer command 0 stream Stream data transfer commmand 1 TRANS_DIR Transfer Direction [10:10] read Read operation 0 write Write operation 1 DATA_TRANS Data Transfer [9:9] without Without data transfer 0 with With data transfer 1 CHK_RESP_CRC Check Response CRC [8:8] not_check Do not check response CRC 0 check Check response CRC 1 LONG_RESP Response Type [7:7] short Short Response (48 bits) 0 long Long Response (136 bits) 1 RESP_RCV Response Receive [6:6] without Command without response 0 with Command with response 1 CMD_IDX CMD Index [5:0] SMHC_CMDARG Command Argument Register 0x001C SMHC_RESP0 Response 0 Register 0x0020 read-only SMHC_RESP1 Response 1 Register 0x0024 read-only SMHC_RESP2 Response 2 Register 0x0028 read-only SMHC_RESP3 Response 3 Register 0x002C read-only SMHC_INTMASK Interrupt Mask Register 0x0030 CARD_REMOVAL_INT_EN Card Removed Interrupt Enable [31:31] CARD_INSERT_INT_EN Card Inserted Interrupt Enable [30:30] SDIO_INT_EN SDIO Interrupt Enable [16:16] DEE_INT_EN Data End-bit Error Interrupt Enable [15:15] ACD_INT_EN Auto Command Done Interrupt Enable [14:14] DSE_BC_INT_EN Data Start Error Interrupt Enable [13:13] CB_IW_INT_EN Command Busy and Illegal Write Interrupt Enable [12:12] FU_FO_INT_EN FIFO Underrun/Overflow Interrupt Enable [11:11] DSTO_VSD_INT_EN Data Starvation Timeout/V1.8 Switch Done Interrupt Enable [10:10] DTO_BDS_INT_EN Data Timeout/Boot Data Start Interrupt Enable [9:9] RTO_BACK_INT_EN Response Timeout/Boot ACK Received Interrupt Enable [8:8] DCE_INT_EN Data CRC Error Interrupt Enable [7:7] RCE_INT_EN Response CRC Error Interrupt Enable [6:6] DRR_INT_EN Data Receive Request Interrupt Enable [5:5] DTR_INT_EN Data Transmit Request Interrupt Enable [4:4] DTC_INT_EN Data Transfer Complete Interrupt Enable [3:3] CC_INT_EN Command Complete Interrupt Enable [2:2] RE_INT_EN Response Error Interrupt Enable [1:1] SMHC_MINTSTS Masked Interrupt Status Register 0x0034 read-only M_CARD_REMOVAL_INT Card Removed [31:31] M_CARD_INSERT Card Inserted [30:30] M_SDIO_INT SDIO Interrupt [16:16] M_DEE_INT Data End-bit Error [15:15] M_ACD_INT Auto Command Done [14:14] M_DSE_BC_INT Data Start Error/Busy Clear [13:13] M_CB_IW_INT Command Busy and Illegal Write [12:12] M_FU_FO_INT FIFO Underrun/Overflow [11:11] M_DSTO_VSD_INT Data Starvation Timeout/V1.8 Switch Done [10:10] M_DTO_BDS_INT Data Timeout/Boot Data Start [9:9] M_RTO_BACK_INT Response Timeout/Boot ACK Received [8:8] M_DCE_INT Data CRC Error [7:7] M_RCE_INT Response CRC Error [6:6] M_DRR_INT Data Receive Request [5:5] M_DTR_INT Data Transmit Request [4:4] M_DTC_INT Data Transfer Complete [3:3] M_CC_INT Command Complete [2:2] M_RE_INT Response Errors [1:1] SMHC_RINTSTS Raw Interrupt Status Register 0x0038 CARD_REMOVAL Card Removed [31:31] CARD_INSERT Card Inserted [30:30] SDIOI_INT SDIO Interrupt [16:16] DEE Data End-bit Error [15:15] ACD Auto Command Done [14:14] DSE_BC Data Start Error/Busy Clear [13:13] CB_IW Command Busy and Illegal Write [12:12] FU_FO FIFO Underrun/Overflow [11:11] DSTO_VSD Data Starvation Timeout/V1.8 Switch Done [10:10] DTO_BDS Data Timeout/Boot Data Start [9:9] RTO_BACK Response Timeout/Boot ACK Received [8:8] DCE Data CRC Error [7:7] RCE Response CRC Error [6:6] DRR Data Receive Request [5:5] DTR Data Transmit Request [4:4] DTC Data Transfer Complete [3:3] CC Command Complete [2:2] RE Response Error [1:1] SMHC_STATUS Status Register 0x003C read-only DMA_REQ DMA Request [31:31] FIFO_LEVEL FIFO Level [25:17] RESP_IDX Response Index [16:11] FSM_BUSY Data FSM Busy [10:10] CARD_BUSY Card Data Busy [9:9] not_busy Card data is not busy 0 busy Card data is busy 1 CARD_PRESENT Data[3] Statuss [8:8] not_present The card is not present 0 present The card is present 1 FSM_STA Command FSM States [7:4] idle Idle 0b0000 sis Send init sequence 0b0001 txcsb TX CMD start bit 0b0010 txctb TX CMD TX bit 0b0011 txcia TX CMD index + argument 0b0100 txcc TX CMD CRC7 0b0101 txceb TX CMD end bit 0b0110 rxrsb RX response start bit 0b0111 rxrir RX response IRQ responses 0b1000 rxrtb RX response TX bit 0b1001 rxrci RX response CMD index 0b1010 rxrd RX response data 0b1011 rxrc RX response CRC7 0b1100 rxreb RX response end bit 0b1101 cpwn CMD path wait NCC 0b1110 wait Wait; CMD-to-response turn around 0b1111 FIFO_FULL sFIFO Full [3:3] not_full FIFO is not full 0 full FIFO is full 1 FIFO_EMPTY FIFO Empty [2:2] not_sempty FIFO is not empty 0 empty FIFO is empty 1 FIFO_TX_LEVEL FIFO TX Water Level Flag [1:1] not_reach FIFO does not reach the transmit trigger level 0 reach FIFO reaches the transmit trigger level 1 FIFO_RX_LEVEL FIFO RX Water Level Flag [0:0] not_reach FIFO does not reach the receive trigger level 0 reach FIFO reaches the receive trigger level 1 SMHC_FIFOTH FIFO Water Level Register 0x0040 BSIZE_OF_TRANS sBurst Size of Multiple Transaction [30:28] T1 1 transfer 0b000 T4 4 transfers 0b001 T8 8 transfers 0b010 T16 16 transfers 0b011 RX_TL RX Trigger Level [23:16] TX_TL TX Trigger Level [7:0] SMHC_FUNS FIFO Function Select Register 0x0044 ABT_RDATA Abort Read Data [2:2] ignored 0 abort 1 READ_WAIT Read Wait [1:1] clear Clear SDIO read wait 0 assert Assert SDIO read wait 1 HOST_SEND_MIMC_IRQRESQ Host Send MMC IRQ Response [0:0] ignored 0 send Send auto IRQ response 1 SMHC_TBC0 Transferred Byte Count between Controller and Card 0x0048 read-only SMHC_TBC1 Transferred Byte Count between Host Memory and Internal FIFO 0x004C read-only SMHC_DBGC Current Debug Control Register 0x0050 SMHC_CSDC CRC Status Detect Control Registers 0x0054 CRC_DET_PARA [3:0] HS400 0b110 Other 0b011 SMHC_A12A Auto Command 12 Argument Register 0x0058 SD_A12A [15:0] SMHC_NTSR SD New Timing Set Register 0x005C MODE_SELECT [31:31] old_mode Old mode of Sample/Output Timing 0 new_mode New mode of Sample/Output Timing 1 CMD_DAT_RX_PHASE_CLR Clear the input phase of command lines and data lines during the update clock operation [24:24] Disabled Disabled 0 Enabled Enabled 1 DAT_CRC_STATUS_RX_PHASE_CLR Clear the input phase of data lines before receiving the CRC status [22:22] Disabled Disabled 0 Enabled Enabled 1 DAT_TRANS_RX_PHASE_CLR Clear the input phase of data lines before transferring the data [21:21] Disabled Disabled 0 Enabled Enabled 1 DAT_RECV_RX_PHASE_CLR Clear the input phase of data lines before receiving the data [20:20] Disabled Disabled 0 Enabled Enabled 1 CMD_SEND_RX_PHASE_CLR Clear command rx phase before sending the command [16:16] Disabled Disabled 0 Enabled Enabled 1 DAT_SAMPLE_TIMING_PHASE [9:8] O90 Sample timing phase offset 90 0b00 O180 Sample timing phase offset 180 0b01 O270 Sample timing phase offset 270 0b10 O0 Sample timing phase offset 0 (only for SD2 hs400 mode) 0b11 CMD_SAMPLE_TIMING_PHASE [5:4] O90 Sample timing phase offset 90 0b00 O180 Sample timing phase offset 180 0b01 O270 Sample timing phase offset 270 0b10 O0 Ignore 0b11 HS400_NEW_SAMPLE_EN [0:0] disable Disable hs400 new sample method 0 enable Enable hs400 new sample method 1 SMHC_HWRST Hardware Reset Register 0x0078 HW_RST [0:0] active Active mode 0 Reset Reset 1 SMHC_IDMAC IDMAC Control Register 0x0080 DES_LOAD_CTRL [31:31] write-only IDMAC_ENB IDMAC Enable [7:7] FIX_BUST_CTRL Fixed Burst [1:1] IDMAC_RST DMA Reset [0:0] SMHC_DLBA Descriptor List Base Address Register 0x0084 SMHC_IDST IDMAC Status Register 0x0088 IDMAC_ERR_STA Error Bits [12:10] read-only transmission Host Abort received during the transmission 0b001 reception Host Abort received during the reception 0b010 ABN_INT_SUM Abnormal Interrupt Summary [9:9] NOR_INT_SUM Normal Interrupt Summary [8:8] ERR_FLAG_SUM Card Error Summary [5:5] DES_UNAVL_INT Descriptor Unavailable Interrupt [4:4] FATAL_BERR_INT Fatal Bus Error Interrupt [2:2] RX_INT Receive Interrupt [1:1] TX_INT Transmit Interrupt [0:0] SMHC_IDIE IDMAC Interrupt Enable Register 0x008C ERR_SUM_INT_ENB Card Error Summary Interrupt Enable [5:5] DES_UNAVL_INT_ENB Descriptor Unavailable Interrupt [4:4] FERR_INT_ENB Fatal Bus Error Enable [2:2] RX_INT_ENB Receive Interrupt Enables [1:1] TX_INT_ENB Transmit Interrupt Enable [0:0] SMHC_THLD Card Threshold Control Register 0x0100 CARD_WR_THLD Card Read/Write Threshold Size [27:16] CARD_WR_THLD_ENB Card Read/Write Threshold Enable [2:2] disabled Card write threshold disabled 0 enabled Card write threshold enabled 1 BCIG Busy Clear Interrupt Generation [1:1] disabled Busy clear interrupt disabled 0 enabled Busy clear interrupt enabled 1 CARD_RD_THLD_ENB Card Read Threshold Enable [0:0] disabled Card read threshold disabled 0 enabled Card read threshold enabled 1 SMHC_SFC Sample FIFO Control Register 0x0104 STOP_CLK_CTRL Stop Clock Control [4:1] BYPASS_EN Bypass enable [0:0] SMHC_A23A Auto Command 23 Argument Register 0x0108 EMMC_DDR_SBIT_DET eMMC4.5 DDR Start Bit Detection Control Register 0x010C HS400_MD_EN HS400 Mode Enable [31:31] disabled Disabled 0 enabled Enabled 1 HALF_START_BIT Control for start bit detection mechanism inside mstorage based on duration of start bit [0:0] full Full cycle 0 less Less than one full cycle 1 SMHC_EXT_CMD Extended Command Register 0x0138 AUTO_CMD23_EN Send CMD23 Automatically [0:0] SMHC_EXT_RESP Extended Response Register 0x013C read-only SMHC_DRV_DL Drive Delay Control Register 0x0140 DAT_DRV_PH_SEL Data Drive Phase Select [17:17] CMD_DRV_PH_SEL Command Drive Phase Select [16:16] SMHC_SMAP_DL Sample Delay Control Register 0x0144 SAMP_DL_CAL_START Sample Delay Calibration Start [15:15] SAMP_DL_CAL_DONE Sample Delay Calibration Done [14:14] read-only SAMP_DL Sample Delay [13:8] read-only SAMP_DL_SW_EN Sample Delay Software Enable [7:7] SAMP_DL_SW Sample Delay Software [5:0] SMHC_DS_DL Data Strobe Delay Control Register 0x0148 DS_DL_CAL_START Data Strobe Delay Calibration Start [15:15] DS_DL_CAL_DONE Data Strobe Delay Calibration Done [14:14] read-only DS_DL Data Strobe Delay [13:8] read-only DS_DL_SW_EN Sample Delay Software Enable [7:7] DS_DL_SW Data Storbe Delay Software [5:0] SMHC_HS400_DL HS400 Delay Control Register 0x014C HS400_DL_CAL_START HS400 Delay Calibration Start [15:15] HS400_DL_CAL_DONE HS400 Delay Calibration Done [14:14] read-only HS400_DL HS400 Delay [11:8] read-only HS400_DL_SW_EN Sample Delay Software Enable [7:7] HS400_DL_SW HS400 Delay Software [3:0] SMHC_FIFO Read/Write FIFO 0x0200 3 0x1000 I2S_PCM[%s] I2S/PCM Audio 0x02032000 0 0x1000 registers I2S_PCM0 42 I2S_PCM1 43 I2S_PCM2 44 I2S_PCM_CTL I2S/PCM Control Register 0x0000 I2S_PCM_FMT0 I2S/PCM Format Register 0 0x0004 I2S_PCM_FMT1 I2S/PCM Format Register 1 0x0008 I2S_PCM_ISTA I2S/PCM Interrupt Status Register 0x000C I2S_PCM_RXFIFO I2S/PCM RXFIFO Register 0x0010 I2S_PCM_FCTL I2S/PCM FIFO Control Register 0x0014 I2S_PCM_FSTA I2S/PCM FIFO Status Register 0x0018 I2S_PCM_INT I2S/PCM DMA and Interrupt Control Register 0x001C I2S_PCM_TXFIFO I2S/PCM TXFIFO Register 0x0020 I2S_PCM_CLKD I2S/PCM Clock Divide Register 0x0024 I2S_PCM_TXCNT I2S/PCM TX Sample Counter Register 0x0028 I2S_PCM_RXCNT I2S/PCM RX Sample Counter Register 0x002C I2S_PCM_CHCFG I2S/PCM Channel Configuration Register 0x0030 I2S_PCM_TX0CHSEL I2S/PCM TX0 Channel Select Register 0x0034 I2S_PCM_TX1CHSEL I2S/PCM TX1 Channel Select Register 0x0038 I2S_PCM_TX2CHSEL I2S/PCM TX2 Channel Select Register 0x003C I2S_PCM_TX3CHSEL I2S/PCM TX3 Channel Select Register 0x0040 I2S_PCM_TX0CHMAP0 I2S/PCM TX0 Channel Mapping Register0 0x0044 I2S_PCM_TX0CHMAP1 I2S/PCM TX0 Channel Mapping Register1 0x0048 I2S_PCM_TX1CHMAP0 I2S/PCM TX1 Channel Mapping Register0 0x004C I2S_PCM_TX1CHMAP1 I2S/PCM TX1 Channel Mapping Register1 0x0050 I2S_PCM_TX2CHMAP0 I2S/PCM TX2 Channel Mapping Register0 0x0054 I2S_PCM_TX2CHMAP1 I2S/PCM TX2 Channel Mapping Register1 0x0058 I2S_PCM_TX3CHMAP0 I2S/PCM TX3 Channel Mapping Register0 0x005C I2S_PCM_TX3CHMAP1 I2S/PCM TX3 Channel Mapping Register1 0x0060 I2S_PCM_RXCHSEL I2S/PCM RX Channel Select Register 0x0064 I2S_PCM_RXCHMAP0 I2S/PCM RX Channel Mapping Register0 0x0068 I2S_PCM_RXCHMAP1 I2S/PCM RX Channel Mapping Register1 0x006C I2S_PCM_RXCHMAP2 I2S/PCM RX Channel Mapping Register2 0x0070 I2S_PCM_RXCHMAP3 I2S/PCM RX Channel Mapping Register3 0x0074 MCLKCFG ASRC MCLK Configuration Register 0x0080 FsoutCFG ASRC Out Sample Rate Configuration Register 0x0084 FsinEXTCFG ASRC Input Sample Pulse Extend Configuration Register 0x0088 ASRCCFG ASRC Enable Register 0x008C ASRCMANCFG ASRC Manual Ratio Configuration Register 0x0090 ASRCRATIOSTAT ASRC Status Register 0x0094 ASRCFIFOSTAT ASRC FIFO Level Status Register 0x0098 ASRCMBISTCFG ASRC MBIST Test Configuration Register 0x009C ASRCMBISTSTAT ASRC MBIST Test Status Register 0x00A0 DMIC DMIC Audio 0x02031000 0 0x400 registers DMIC 40 DMIC_EN DMIC Enable Control Register 0x0000 DMIC_SR DMIC Sample Rate Register 0x0004 DMIC_CTR DMIC Control Register 0x0008 DMIC_DATA DMIC Data Register 0x0010 DMIC_INTC DMIC Interrupt Control Register 0x0014 DMIC_INTS DMIC Interrupt Status Register 0x0018 DMIC_RXFIFO_CTR DMIC RXFIFO Control Register 0x001C DMIC_RXFIFO_STA DMIC RXFIFO Status Register 0x0020 DMIC_CH_NUM DMIC Channel Numbers Register 0x0024 DMIC_CH_MAP DMIC Channel Mapping Register 0x0028 DMIC_CNT DMIC Counter Register 0x002C DATA0_DATA1_VOL_CTR Data0 and Data1 Volume Control Register 0x0030 DATA2_DATA3_VOL_CTR Data2 And Data3 Volume Control Register 0x0034 HPF_EN_CTR High Pass Filter Enable Control Register 0x0038 HPF_COEF_REG High Pass Filter Coefficient Register 0x003C HPF_GAIN_REG High Pass Filter Gain Register 0x0040 OWA One Wire Audio Audio 0x02036000 0 0x400 registers OWA 39 OWA_GEN_CTL OWA General Control Register 0x0000 OWA_TX_CFIG OWA TX Configuration Register 0x0004 OWA_RX_CFIG OWA RX Configuration Register 0x0008 OWA_ISTA OWA Interrupt Status Register 0x000C OWA_RXFIFO OWA RXFIFO Register 0x0010 OWA_FCTL OWA FIFO Control Register 0x0014 OWA_FSTA OWA FIFO Status Register 0x0018 OWA_INT OWA Interrupt Control Register 0x001C OWA_TX_FIFO OWA TX FIFO Register 0x0020 OWA_TX_CNT OWA TX Counter Register 0x0024 OWA_RX_CNT OWA RX Counter Register 0x0028 OWA_TX_CHSTA0 OWA TX Channel Status Register0 0x002C OWA_TX_CHSTA1 OWA TX Channel Status Register1 0x0030 OWA_RXCHSTA0 OWA RX Channel Status Register0 0x0034 OWA_RXCHSTA1 OWA RX Channel Status Register1 0x0038 OWA_EXP_CTL OWA Expand Control Register 0x0040 OWA_EXP_ISTA OWA Expand Interrupt Status Register 0x0044 OWA_EXP_INFO_0 OWA Expand Infomation Register0 0x0048 OWA_EXP_INFO_1 OWA Expand Infomation Register1 0x004C OWA_EXP_DBG_0 OWA Expand Debug Register0 0x0050 OWA_EXP_DBG_1 OWA Expand Debug Register1 0x0054 AudioCodec Audio Codec Audio 0x02030000 0 0x1000 registers AUDIO_CODEC 41 AC_DAC_DPC DAC Digital Part Control Register 0x0000 DAC_VOL_CTRL DAC Volume Control Register 0x0004 AC_DAC_FIFOC DAC FIFO Control Register 0x0010 AC_DAC_FIFOS DAC FIFO Status Register 0x0014 AC_DAC_TXDATA DAC TX DATA Register 0x0020 AC_DAC_CNT DAC TX FIFO Counter Register 0x0024 AC_DAC_DG DAC Debug Register 0x0028 AC_ADC_FIFOC ADC FIFO Control Register 0x0030 ADC_VOL_CTRL1 ADC Volume Control1 Register 0x0034 AC_ADC_FIFOS ADC FIFO Status Register 0x0038 AC_ADC_RXDATA ADC RX Data Register 0x0040 AC_ADC_CNT ADC RX Counter Register 0x0044 AC_ADC_DG ADC Debug Register 0x004C ADC_DIG_CTRL ADC Digtial Control Register 0x0050 VRA1SPEEDUP_DOWN_CTRL VRA1 Speedup Down Control Register 0x0054 AC_DAC_DAP_CTRL DAC DAP Control Register 0x00F0 AC_ADC_DAP_CTR ADC DAP Control Register 0x00F8 AC_DAC_DRC_HHPFC DAC DRC High HPF Coef Register 0x0100 AC_DAC_DRC_LHPFC DAC DRC Low HPF Coef Register 0x0104 AC_DAC_DRC_CTRL DAC DRC Control Register 0x0108 AC_DAC_DRC_LPFHAT DAC DRC Left Peak Filter High Attack Time Coef Register 0x010C AC_DAC_DRC_LPFLAT DAC DRC Left Peak Filter Low Attack Time Coef Register 0x0110 AC_DAC_DRC_RPFHAT DAC DRC Right Peak Filter High Attack Time Coef Register 0x0114 AC_DAC_DRC_RPFLAT DAC DRC Peak Filter Low Attack Time Coef Register 0x0118 AC_DAC_DRC_LPFHRT DAC DRC Left Peak Filter High Release Time Coef Register 0x011C AC_DAC_DRC_LPFLRT DAC DRC Left Peak Filter Low Release Time Coef Register 0x0120 AC_DAC_DRC_RPFHRT DAC DRC Right Peak filter High Release Time Coef Register 0x0124 AC_DAC_DRC_RPFLRT DAC DRC Right Peak filter Low Release Time Coef Register 0x0128 AC_DAC_DRC_LRMSHAT DAC DRC Left RMS Filter High Coef Register 0x012C AC_DAC_DRC_LRMSLAT DAC DRC Left RMS Filter Low Coef Register 0x0130 AC_DAC_DRC_RRMSHAT DAC DRC Right RMS Filter High Coef Register 0x0134 AC_DAC_DRC_RRMSLAT DAC DRC Right RMS Filter Low Coef Register 0x0138 AC_DAC_DRC_HCT DAC DRC Compressor Threshold High Setting Register 0x013C AC_DAC_DRC_LCT DAC DRC Compressor Slope High Setting Register 0x0140 AC_DAC_DRC_HKC DAC DRC Compressor Slope High Setting Register 0x0144 AC_DAC_DRC_LKC DAC DRC Compressor Slope Low Setting Register 0x0148 AC_DAC_DRC_HOPC DAC DRC Compressor High Output at Compressor Threshold Register 0x014C AC_DAC_DRC_LOPC DAC DRC Compressor Low Output at Compressor Threshold Register 0x0150 AC_DAC_DRC_HLT DAC DRC Limiter Threshold High Setting Register 0x0154 AC_DAC_DRC_LLT DAC DRC Limiter Threshold Low Setting Register 0x0158 AC_DAC_DRC_HKl DAC DRC Limiter Slope High Setting Register 0x015C AC_DAC_DRC_LKl DAC DRC Limiter Slope Low Setting Register 0x0160 AC_DAC_DRC_HOPL DAC DRC Limiter High Output at Limiter Threshold 0x0164 AC_DAC_DRC_LOPL DAC DRC Limiter Low Output at Limiter Threshold 0x0168 AC_DAC_DRC_HET DAC DRC Expander Threshold High Setting Register 0x016C AC_DAC_DRC_LET DAC DRC Expander Threshold Low Setting Register 0x0170 AC_DAC_DRC_HKE DAC DRC Expander Slope High Setting Register 0x0174 AC_DAC_DRC_LKE DAC DRC Expander Slope Low Setting Register 0x0178 AC_DAC_DRC_HOPE DAC DRC Expander High Output at Expander Threshold 0x017C AC_DAC_DRC_LOPE DAC DRC Expander Low Output at Expander Threshold 0x0180 AC_DAC_DRC_HKN DAC DRC Linear Slope High Setting Register 0x0184 AC_DAC_DRC_LKN DAC DRC Linear Slope Low Setting Register 0x0188 AC_DAC_DRC_SFHAT DAC DRC Smooth filter Gain High Attack Time Coef Register 0x018C AC_DAC_DRC_SFLAT DAC DRC Smooth filter Gain Low Attack Time Coef Register 0x0190 AC_DAC_DRC_SFHRT DAC DRC Smooth filter Gain High Release Time Coef Register 0x0194 AC_DAC_DRC_SFLRT DAC DRC Smooth filter Gain Low Release Time Coef Register 0x0198 AC_DAC_DRC_MXGHS DAC DRC MAX Gain High Setting Register 0x019C AC_DAC_DRC_MXGLS DAC DRC MAX Gain Low Setting Register 0x01A0 AC_DAC_DRC_MNGHS DAC DRC MIN Gain High Setting Register 0x01A4 AC_DAC_DRC_MNGLS DAC DRC MIN Gain Low Setting Register 0x01A8 AC_DAC_DRC_EPSHC DAC DRC Expander Smooth Time High Coef Register 0x01AC AC_DAC_DRC_EPSLC DAC DRC Expander Smooth Time Low Coef Register 0x01B0 AC_DAC_DRC_HPFHGAIN DAC DRC HPF Gain High Coef Register 0x01B8 AC_DAC_DRC_HPFLGAIN DAC DRC HPF Gain Low Coef Register 0x01BC AC_ADC_DRC_HHPFC ADC DRC High HPF Coef Register 0x0200 AC_ADC_DRC_LHPFC ADC DRC Low HPF Coef Register 0x0204 AC_ADC_DRC_CTRL ADC DRC Control Register 0x0208 AC_ADC_DRC_LPFHAT ADC DRC Left Peak Filter High Attack Time Coef Register 0x020C AC_ADC_DRC_LPFLAT ADC DRC Left Peak Filter Low Attack Time Coef Register 0x0210 AC_ADC_DRC_RPFHAT ADC DRC Right Peak Filter High Attack Time Coef Register 0x0214 AC_ADC_DRC_RPFLAT ADC DRC Right Peak Filter Low Attack Time Coef Register 0x0218 AC_ADC_DRC_LPFHRT ADC DRC Left Peak Filter High Release Time Coef Register 0x021C AC_ADC_DRC_LPFLRT ADC DRC Left Peak Filter Low Release Time Coef Register 0x0220 AC_ADC_DRC_RPFHRT ADC DRC Right Peak Filter High Release Time Coef Register 0x0224 AC_ADC_DRC_RPFLRT ADC DRC Right Peak Filter Low Release Time Coef Register 0x0228 AC_ADC_DRC_LRMSHAT ADC DRC Left RMS Filter High Coef Register 0x022C AC_ADC_DRC_LRMSLAT ADC DRC Left RMS Filter Low Coef Register 0x0230 AC_ADC_DRC_RRMSHAT ADC DRC Right RMS Filter High Coef Register 0x0234 AC_ADC_DRC_RRMSLAT ADC DRC Right RMS Filter Low Coef Register 0x0238 AC_ADC_DRC_HCT ADC DRC Compressor Threshold High Setting Register 0x023C AC_ADC_DRC_LCT ADC DRC Compressor Slope High Setting Register 0x0240 AC_ADC_DRC_HKC ADC DRC Compressor Slope High Setting Register 0x0244 AC_ADC_DRC_LKC ADC DRC Compressor Slope Low Setting Register 0x0248 AC_ADC_DRC_HOPC ADC DRC Compressor High Output at Compressor Threshold Register 0x024C AC_ADC_DRC_LOPC ADC DRC Compressor Low Output at Compressor Threshold Register 0x0250 AC_ADC_DRC_HLT ADC DRC Limiter Threshold High Setting Register 0x0254 AC_ADC_DRC_LLT ADC DRC Limiter Threshold Low Setting Register 0x0258 AC_ADC_DRC_HKl ADC DRC Limiter Slope High Setting Register 0x025C AC_ADC_DRC_LKl ADC DRC Limiter Slope Low Setting Register 0x0260 AC_ADC_DRC_HOPL ADC DRC Limiter High Output at Limiter Threshold 0x0264 AC_ADC_DRC_LOPL ADC DRC Limiter Low Output at Limiter Threshold 0x0268 AC_ADC_DRC_HET ADC DRC Expander Threshold High Setting Register 0x026C AC_ADC_DRC_LET ADC DRC Expander Threshold Low Setting Register 0x0270 AC_ADC_DRC_HKE ADC DRC Expander Slope High Setting Register 0x0274 AC_ADC_DRC_LKE ADC DRC Expander Slope Low Setting Register 0x0278 AC_ADC_DRC_HOPE ADC DRC Expander High Output at Expander Threshold 0x027C AC_ADC_DRC_LOPE ADC DRC Expander Low Output at Expander Threshold 0x0280 AC_ADC_DRC_HKN ADC DRC Linear Slope High Setting Register 0x0284 AC_ADC_DRC_LKN ADC DRC Linear Slope Low Setting Register 0x0288 AC_ADC_DRC_SFHAT ADC DRC Smooth filter Gain High Attack Time Coef Register 0x028C AC_ADC_DRC_SFLAT ADC DRC Smooth filter Gain Low Attack Time Coef Register 0x0290 AC_ADC_DRC_SFHRT ADC DRC Smooth filter Gain High Release Time Coef Register 0x0294 AC_ADC_DRC_SFLRT ADC DRC Smooth filter Gain Low Release Time Coef Register 0x0298 AC_ADC_DRC_MXGHS ADC DRC MAX Gain High Setting Register 0x029C AC_ADC_DRC_MXGLS ADC DRC MAX Gain Low Setting Register 0x02A0 AC_ADC_DRC_MNGHS ADC DRC MIN Gain High Setting Register 0x02A4 AC_ADC_DRC_MNGLS ADC DRC MIN Gain Low Setting Register 0x02A8 AC_ADC_DRC_EPSHC ADC DRC Expander Smooth Time High Coef Register 0x02AC AC_ADC_DRC_EPSLC ADC DRC Expander Smooth Time Low Coef Register 0x02B0 AC_ADC_DRC_HPFHGAIN ADC DRC HPF Gain High Coef Register 0x02B8 AC_ADC_DRC_HPFLGAIN ADC DRC HPF Gain Low Coef Register 0x02BC ADC1_REG ADC1 Analog Control Register 0x0300 ADC2_REG ADC2 Analog Control Register 0x0304 ADC3_REG ADC3 Analog Control Register 0x0308 DAC_REG DAC Analog Control Register 0x0310 MICBIAS_REG MICBIAS Analog Control Register 0x0318 RAMP_REG BIAS Analog Control Register 0x031C BIAS_REG BIAS Analog Control Register 0x0320 ADC5_REG ADC5 Analog Control Register 0x0330 4 0x400 TWI[%s] Two Wire Interface Interfaces 0x02502000 0 0x400 registers TWI0 25 TWI1 26 TWI2 27 TWI3 28 TWI_ADDR TWI Slave Address Register 0x0000 SLA Slave Address [7:1] GCE [0:0] disable 0 enable 1 TWI_XADDR TWI Extended Slave Address Register 0x0004 SLAX Extend Slave Address\n\nSLAX[7:0] [7:0] TWI_DATA TWI Data Byte Register 0x0008 data Data byte transmitted or received [7:0] TWI_CNTR TWI Control Register 0x000C int_en Interrupt Enable [7:7] low The interrupt line always low 0 high The interrupt line will go high when INT_FLAG is set 1 bus_en TWI Bus Enable [6:6] ignored 0 respond 1 m_sta Master Mode Start [5:5] m_stp Master Mode Stop [4:4] int_flag Interrupt Flag [3:3] a_ack Assert Acknowledge [2:2] clk_count_mode [0:0] oscl scl clock high period count on oscl 0 iscl scl clock high period count on iscl 1 TWI_STAT TWI Status Register 0x0010 read-only sta [7:0] be Bus error 0x00 sct START condition transmitted 0x08 rsct Repeated START condition transmitted 0x10 awbt_ar Address + Write bit transmitted, ACK received 0x18 awbt_anr Address + Write bit transmitted, ACK not received 0x20 dbtm_ar Data byte transmitted in master mode, ACK received 0x28 dbtm_anr Data byte transmitted in master mode, ACK not received 0x30 al_a_db Arbitration lost in address or data byte 0x38 arbt_ar Address + Read bit transmitted, ACK received 0x40 arbt_anr Address + Read bit transmitted, ACK not received 0x48 dbrm_at Data byte received in master mode, ACK transmitted 0x50 dbrm_ant Data byte received in master mode, not ACK transmitted 0x58 sawr_at Slave address + Write bit received, ACK transmitted 0x60 al_am_sawr_at Arbitration lost in the address as master, slave address + Write bit received, ACK transmitted 0x68 gcar_at General Call address received, ACK transmitted 0x70 al_am_gcar_at Arbitration lost in the address as master, General Call address received, ACK transmitted 0x78 dbr_sar_at Data byte received after slave address received, ACK transmitted 0x80 dbr_sar_ant Data byte received after slave address received, not ACK transmitted 0x88 dbr_gcr_at Data byte received after General Call received, ACK transmitted 0x90 dbr_gcr_ant Data byte received after General Call received, not ACK transmitted 0x98 srscrs STOP or repeated START condition received in slave mode 0xA0 sarr_at Slave address + Read bit received, ACK transmitted 0xA8 al_am_sarr_at Arbitration lost in the address as master, slave address + Read bit received, ACK transmitted 0xB0 dbts_ar Data byte transmitted in slave mode, ACK received 0xB8 dbts_anr Data byte transmitted in slave mode, ACK not received 0xC0 lbts_ar The Last byte transmitted in slave mode, ACK received 0xC8 sawt_ar Second Address byte + Write bit transmitted, ACK received 0xD0 sawt_anr Second Address byte + Write bit transmitted, ACK not received 0xD8 nrsi No relevant status information, INT_FLAG=0 0xF8 TWI_CCR TWI Clock Control Register 0x0014 clk_duty Setting duty cycle of clock as master [7:7] P50 50% 0 P40 40% 1 clk_m [6:3] clk_n [2:0] TWI_SRST TWI Software Reset Register 0x0018 soft_rst Soft Reset [0:0] TWI_EFR TWI Enhance Feature Register 0x001C dbn Data Byte Number Follow Read Command Control [1:0] B0 No data byte can be written after the read command 0b00 B1 1-byte data can be written after the read command 0b01 B2 2-byte data can be written after the read command 0b10 B3 3-byte data can be written after the read command 0b11 TWI_LCR TWI Line Control Register 0x0020 scl_state Current State of TWI_SCL [5:5] read-only low 0 high 1 sda_state Current State of TWI_SDA [4:4] read-only low 0 high 1 scl_ctl TWI_SCL Line State Control Bit [3:3] low 0 high 1 scl_ctl_en TWI_SCL Line State Control Enable [2:2] disable 0 enable 1 sda_ctl TWI_SDA Line State Control Bit [1:1] low 0 high 1 sda_ctl_en TWI_SDA Line State Control Enable [0:0] disable 0 enable 1 TWI_DRV_CTRL TWI_DRV Control Register 0x0200 start_tran Start transmission [31:31] idle 0 start 1 restart_mode Restart mode [29:29] restart 0 stop_restart 1 read_tran_mode Read transition mode [28:28] send 0 not_send 1 tran_result Transition result [27:24] ok 0 fail 1 twi_sta TWI status [23:16] read-only be bus error 0x00 sct START condition transmitted 0x08 rsct Repeated START condition transmitted 0x10 awbt_ar Address + Write bit transmitted, ACK received 0x18 awbt_anr Address + Write bit transmitted, ACK not received 0x20 dbtm_ar Data byte transmitted in master mode, ACK received 0x28 dbtm_anr Data byte transmitted in master mode, ACK not received 0x30 al_a_db Arbitration lost in address or data byte 0x38 arbt_ar Address + Read bit transmitted, ACK received 0x40 arbt_anr Address + Read bit transmitted, ACK not received 0x48 dbrm_ar Data byte received in master mode, ACK received 0x50 dbrm_anr Data byte received in master mode, ACK not received 0x58 t_s9sc Timeout when sending the 9th SCL clock 0x01 timeout_n Timeout number [15:8] soft_reset Software reset [1:1] normal 0 reset 1 twi_drv_en [0:0] disable 0 enable 1 TWI_DRV_CFG TWI_DRV Transmission Configuration Register 0x0204 pkt_interval [31:16] packet_cnt [15:0] TWI_DRV_SLV TWI_DRV Slave ID Register 0x0208 slv_id Slave device ID [15:9] cmd R/W operation to slave device [8:8] write 0 read 1 slv_id_x SLAX[7:0] [7:0] TWI_DRV_FMT TWI_DRV Packet Format Register 0x020C addr_byte [23:16] data_byte [15:0] TWI_DRV_BUS_CTRL TWI_DRV Bus Control Register 0x0210 clk_count_mode [16:16] write-only oscl scl clock high period count on oscl 0 iscl scl clock high period count on iscl 1 clk_duty Setting duty cycle of clock as master [15:15] P50 50% 0 P40 40% 1 clk_n [14:12] clk_m [11:8] scl_sta SCL current status [7:7] read-only sda_sta SDA current status [6:6] read-only scl_mov SCL manual output value [3:3] sda_mov SDA manual output value [2:2] scl_moe SCL manual output enable [1:1] sda_moe SDA manual output enable [0:0] TWI_DRV_INT_CTRL TWI_DRV Interrupt Control Register 0x0214 rx_req_int_en [19:19] tx_req_int_en [18:18] tran_err_int_en [17:17] tran_com_int_en [16:16] rx_req_pd [3:3] tx_req_pd [2:2] tran_err_pd [1:1] tran_com_pd [0:0] TWI_DRV_DMA_CFG TWI_DRV DMA Configure Register 0x0218 dma_rx_en [24:23] rx_trig [21:16] dma_tx_en [8:8] tx_trig [5:0] TWI_DRV_FIFO_CON TWI_DRV FIFO Content Register 0x021C recv_fifo_clear [22:22] recv_fifo_content [21:16] send_fifo_clear [6:6] send_fifo_content [5:0] TWI_DRV_SEND_FIFO_ACC TWI_DRV Send Data FIFO Access Register 0x0300 write-only send_data_fifo [7:0] TWI_DRV_RECV_FIFO_ACC TWI_DRV Receive Data FIFO Access Register 0x0304 read-only recv_data_fifo [7:0] 6 0x400 UART[%s] Universal Asynchronous Receiver Transmitter Interfaces 0x02500000 0 0x400 registers UART0 18 UART1 19 UART2 20 UART3 21 UART4 22 UART5 23 RBR UART Receive Buffer Register 0x0000 read-only rbr [7:0] THR UART Transmit Holding Register 0x0000 write-only thr [7:0] DLL UART Divisor Latch Low Register 0x0000 dll [7:0] DLH UART Divisor Latch High Register 0x0004 dlh [7:0] IER UART Interrupt Enable Register 0x0004 ptime Programmable THRE Interrupt Mode Enable [7:7] disable 0 enable 1 rs485_int_en RS485 Interrupt Enable [4:4] disable 0 enable 1 edssi Enable Modem Status Interrupt [3:3] disable 0 enable 1 elsi Enable Receiver Line Status Interrupt [2:2] disable 0 enable 1 etbei Enable Transmit Holding Register Empty Interrupt [1:1] disable 0 enable 1 erbfi Enable Received Data Available Interrupt [0:0] disable 0 enable 1 IIR UART Interrupt Identity Register 0x0008 read-only feflag FIFOs Enable Flag [7:6] disable 0b00 enable 0b11 iid Interrupt ID [3:0] modem_status 0b0000 no_interrupt_pending 0b0001 thr_empty 0b0010 rs485_interrupt 0b0011 received_data_available 0b0100 receiver_line_status 0b0110 busy_detect 0b0111 character_timeout 0b1100 FCR UART FIFO Control Register 0x0008 write-only rt [7:6] one_character 0b00 quarter_full 0b01 half_full 0b10 two_less_than_full 0b11 tft [5:4] empty 0b00 two_characters 0b01 quarter_full 0b10 half_full 0b11 dmam [3:3] mode_0 0 mode_1 1 xfifor [2:2] rfifor [1:1] fifoe [0:0] LCR UART Line Control Register 0x000C dlab Divisor Latch Access Bit [7:7] rx_buffer 0 divisor_latch 1 bc Break Control Bit [6:6] eps Even Parity Select [5:4] odd 0 even 1 rs485_data 0b10 rs485_addr 0b11 pen Parity Enable [3:3] disabled 0 enabled 1 stop Number of stop bits [2:2] one 1 stop bit 0 two 1.5 stop bits when DLS(LCR[1:0]) is zero, else 2 stop bits 1 dls Data Length Select [1:0] five 5 bits 0b00 six 6 bits 0b01 seven 7 bits 0b10 eight 8 bits 0b11 MCR UART Modem Control Register 0x0010 function UART Function: Select IrDA or RS485 [7:6] UART 0b00 IrDA_SIR 0b01 RS485 0b10 reserved 0b11 afce Auto Flow Control Enable [5:5] disabled 0 enabled 1 loop Loop Back Mode [4:4] normal 0 loop_back 1 rts Request to Send [1:1] deasserted 0 asserted 1 dtr Data Terminal Ready [0:0] deasserted 0 asserted 1 LSR UART Line Status Register 0x0014 read-only fifoerr RX Data Error in FIFO [7:7] error 1 temt Transmitter Empty [6:6] empty 1 thre TX Holding Register Empty [5:5] empty 1 bi Break Interrupt [4:4] fe Framing Error [3:3] error 1 pe Parity Error [2:2] error 1 oe Overrun Error [1:1] error 1 dr Data Ready [0:0] ready 1 MSR UART Modem Status Register 0x0018 read-only dcd Line State of Data Carrier Detect [7:7] deasserted 0 asserted 1 ri Line State of Ring Indicator [6:6] deasserted 0 asserted 1 dsr Line State of Data Set Ready [5:5] deasserted 0 asserted 1 cts Line State of Clear To Send [4:4] deasserted 0 asserted 1 ddcd Delta Data Carrier Detect [3:3] no_change 0 change 1 teri Trailing Edge Ring Indicator [2:2] no_change 0 change 1 ddsr Delta Data Set Ready [1:1] no_change 0 change 1 dcts Delta Clear to Send [0:0] no_change 0 change 1 SCH UART Scratch Register 0x001C scratch [7:0] USR UART Status Register 0x007C read-only rff RX FIFO Full [4:4] not_full 0 full 1 rfne RX FIFO Not Empty [3:3] empty 0 not_empty 1 tfe TX FIFO Empty [2:2] not_empty 0 empty 1 tfnf TX FIFO Not Full [1:1] full 0 not_full 1 busy UART Busy Bit [0:0] idle 0 busy 1 TFL UART Transmit FIFO Level Register 0x0080 read-only tfl TX FIFO Level [8:0] RFL UART Receive FIFO Level Register 0x0084 read-only rfl RX FIFO Level [8:0] HSK UART DMA Handshake Configuration Register 0x0088 hsk Handshake configuration [7:0] wait_cycle 0xA5 handshake 0xE5 DMA_REQ_EN UART DMA Request Enable Register 0x008C timeout_enable DMA Timeout Enable [2:2] disable 0 enable 1 tx_req_enable DMA TX REQ Enable [1:1] disable 0 enable 1 rx_req_enable DMA RX REQ Enable [0:0] disable 0 enable 1 HALT UART Halt TX Register 0x00A4 pte The sending of TX_REQ [7:7] dma_pte_rx The Transmission of RX_DRQ [6:6] sir_rx_invert SIR RX Pulse Polarity Invert [5:5] not_invert 0 invert 1 sir_tx_invert SIR TX Pulse Polarity Invert [4:4] not_invert 0 invert 1 change_update [2:2] finished 0 update_trigger 1 chcfg_at_busy [1:1] disable 0 enable 1 halt_tx [0:0] disabled 0 enabled 1 DBG_DLL UART Debug DLL Register 0x00B0 read-only DBG_DLL [7:0] DBG_DLH UART Debug DLH Register 0x00B4 read-only DBG_DLH [7:0] FCC UART FIFO Clock Control Register 0x00F0 fifo_depth [31:8] read-only rx_fifo_clock_mode [2:2] wr_apb Sync mode, writing/reading clocks use apb clock 0 w_apb_r_ahb Sync mode, writing clock uses apb clock, reading clock uses ahb clock 1 tx_fifo_clock_enable [1:1] disable 0 enable 1 rx_fifo_clock_enable [0:0] disable 0 enable 1 RXDMA_CTRL UART RXDMA Control Register 0x0100 timeout_threshold RXDMA Timeout Threshold\n\nUnit is 1 UART bit time [23:8] timeout_enable RXDMA Timeout Enable [6:6] ahb_burst_mode Set for AHB port burst supported [5:4] SINGLE 0b00 INCR4 0b01 INCR8 0b10 INCR16 0b11 blk_size [3:2] B8 0b00 B16 0b01 B32 0b10 B64 0b11 mode [1:1] Continous 0 Limited 1 enable [0:0] Disable 0 Enable 1 RXDMA_STR UART RXDMA Start Register 0x0104 start [0:0] RXDMA_STA UART RXDMA Status Register 0x0108 buffer_read_address_updating [1:1] ready 0 busy 1 busy [0:0] idle 0 busy 1 RXDMA_LMT UART RXDMA Limit Register 0x010C limit_size [15:0] RXDMA_SADDRL UART RXDMA Buffer Start Address Low Register 0x0110 RXDMA_SADDRH UART RXDMA Buffer Start Address High Register 0x0114 saddr RXDMA Buffer Start Address [33:32] [1:0] RXDMA_BL UART RXDMA Buffer Length Register 0x0118 buffer_length [15:0] RXDMA_IE UART RXDMA Interrupt Enable Register 0x0120 buffer_overrun [3:3] timeout_done [2:2] blk_done [1:1] limit_done [0:0] RXDMA_IS UART RXDMA Interrupt Status Register 0x0124 buffer_overrun [3:3] timeout_done [2:2] blk_done [1:1] limit_done [0:0] RXDMA_WADDRL UART RXDMA Write Address Low Register 0x0128 read-only RXDMA_WADDRH UART RXDMA Write Address High Register 0x012C read-only waddr RXDMA Current Write Address [33:32] [1:0] RXDMA_RADDRL UART RXDMA Read Address Low Register 0x0130 RXDMA_RADDRH UART RXDMA Read Address High Register 0x0134 raddr RXDMA Current Read Address [33:32] [1:0] RXDMA_DCNT UART RXDMA Data Count Register 0x0138 data_count [15:0] SPI0 Serial Peripheral Interface Interfaces 0x04025000 0 0x1000 registers SPI0 31 SPI_GCR SPI Global Control Register 0x0004 srst Soft reset [31:31] tp_en Transmit Pause Enable [7:7] normal normal operation, ignore RXFIFO status 0 stop_when_full Stop transmit data when RXFIFO full 1 mode_selec Sample timing Mode Select [2:2] old_mode Old mode of Sample Timing 0 new_mode New mode of Sample Timing 1 mode SPI Function Mode Select [1:1] slave 0 master 1 en SPI Module Enable Control [0:0] disable 0 enable 1 SPI_TCR SPI Transfer Control Register 0x0008 xch Exchange Burst [31:31] idle 0 initiate_exchange 1 sdc1 Master Sample Data Control register1 [15:15] normal normal operation, do not delay the internal read sample point 0 delay delay the internal read sample point 1 sddm Sending Data Delay Mode [14:14] normal normal sending 0 delay delay sending 1 sdm Master Sample Data Mode [13:13] delay delay sample mode 0 normal normal sample mode 1 fbs First Transmit Bit Select [12:12] msb MSB first 0 lsb LSB first 1 sdc Master Sample Data Control [11:11] normal Normal operation, do not delay the internal read sample point 0 delay Delay the internal read sample point 1 rpsm Rapids Mode Select [10:10] normal Normal write mode 0 rapid Rapid write mode 1 ddb Dummy Burst Type [9:9] zero The bit value of dummy SPI burst is zero 0 one The bit value of dummy SPI burst is one 1 dhb Discard Hash Burst [8:8] receive Receiving all SPI bursts in the BC period 0 discard Discard unused SPI bursts 1 ss_level [7:7] low 0 high 1 ss_owner [6:6] spi_controller 0 software 1 ss_sel [5:4] ss0 0b00 ss1 0b01 ss2 0b10 ss3 0b11 ssctl [3:3] assert SPI_SSx remains asserted between SPI bursts 0 negate Negate SPI_SSx between SPI bursts 1 spol SPI Chip Select Signal Polarity Control [2:2] high Active high polarity 0 low Active low polarity 1 cpol SPI Clock Polarity Control [1:1] high Active high polarity 0 low Active low polarity 1 cpha SPI Clock/Data Phase Control [0:0] P0 Phase 0 (Leading edge for sample data) 0 P1 Phase 1 (Leading edge for setup data) 1 SPI_IER SPI Interrupt Control Register 0x0010 ss_int_en SSI Interrupt Enable [13:13] disable 0 enable 1 tc_int_en Transfer Completed Interrupt Enable [12:12] disable 0 enable 1 tf_udr_int_en TXFIFO Underrun Interrupt Enable [11:11] disable 0 enable 1 tf_ovf_int_en TXFIFO Overflow Interrupt Enable [10:10] disable 0 enable 1 rf_udr_int_en RXFIFO Underrun Interrupt Enable [9:9] disable 0 enable 1 rf_ovf_int_en RXFIFO Overflow Interrupt Enable [8:8] disable 0 enable 1 tf_full_int_en TXFIFO Full Interrupt Enable [6:6] disable 0 enable 1 tf_emp_int_en TXFIFO Empty Interrupt Enable [5:5] disable 0 enable 1 tf_erq_int_en TXFIFO Empty Request Interrupt Enable [4:4] disable 0 enable 1 rf_full_int_en RXFIFO Full Interrupt Enable [2:2] disable 0 enable 1 rf_emp_int_en RXFIFO Empty Interrupt Enable [1:1] disable 0 enable 1 rf_rdy_int_en RXFIFO Ready Request Interrupt Enable [0:0] disable 0 enable 1 SPI_ISR SPI Interrupt Status Register 0x0014 ssi SS Invalid Enable [13:13] tc Transfer Completed [12:12] busy 0 transfer_completed 1 tf_udr TXFIFO Underrun [11:11] not_underrun 0 underrun 1 tf_ovf TXFIFO Overflow [10:10] not_overflow 0 overflow 1 rf_udr RXFIFO Underrun [9:9] not_underrun 0 underrun 1 rf_ovf RXFIFO Overflow [8:8] not_overflow 0 overflow 1 tf_full TXFIFO Full [6:6] not_full 0 full 1 tf_emp TXFIFO Empty [5:5] not_empty 0 empty 1 tf_ready TXFIFO Ready [4:4] rf_full RXFIFO Full [2:2] not_full 0 full 1 rf_emp RXFIFO Empty [1:1] not_empty 0 empty 1 rf_rdy RXFIFO Ready [0:0] SPI_FCR SPI FIFO Control Register 0x0018 tf_rst TXFIFO Reset [31:31] tf_test_en TXFIFO Test Mode Enable [30:30] disable 0 enable 1 tf_drq_en TXFIFO DMA Request Enable [24:24] disable 0 enable 1 tf_trig_level TXFIFO Empty Request Trigger Level [23:16] rf_rst RXFIFO Reset [15:15] rf_test_en RXFIFO Test Mode Enable [14:14] disable 0 enable 1 rf_drq_en RXFIFO DMA Request Enable [8:8] disable 0 enable 1 rf_trig_level RXFIFO Ready Request Trigger Level [7:0] SPI_FSR SPI FIFO Status Register 0x001C read-only tb_wr TXFIFO Write Buffer Write Enable [31:31] tb_cnt TXFIFO Write Buffer Counter [30:28] tf_cnt TXFIFO Counter\n\nThese bits indicate the number of bytes in TXFIFO [23:16] rb_wr RXFIFO Write Buffer Write Enable [15:15] rb_cnt RXFIFO Write Buffer Counter [14:12] rf_cnt RXFIFO Counter\n\nThese bits indicate the number of bytes in RXFIFO [7:0] SPI_WCR SPI Wait Clock Register 0x0020 swc Dual mode direction switch wait clock counter [19:16] wwc Wait clock counter [15:0] SPI_SAMP_DL SPI Sample Delay Control Register 0x0028 samp_dl_cal_start Sample Delay Calibration Start [15:15] samp_dl_cal_done Sample Delay Calibration Dont [14:14] read-only samp_dl Sample Delay [13:8] read-only samp_dl_sw_en Sample Delay Software Enable [7:7] samp_dl_sw Sample Delay Software [5:0] SPI_MBC SPI Master Burst Counter Register 0x0030 mbc Master Burst Counter [23:0] SPI_MTC SPI Master Transmit Counter Register 0x0034 mwtc Master Write Transmit Counter [23:0] SPI_BCC SPI Master Burst Control Register 0x0038 quad_en Quad Mode Enable [29:29] disable 0 enable 1 drm Master Dual Mode RX Enable [28:28] single 0 dual 1 dbc Master Dummy Burst Counter [27:24] stc Master Single Mode Transmit Counter [23:0] SPI_BATC SPI Bit-Aligned Transfer Configure Register 0x0040 tce Transfer Control Enable [31:31] idle 0 init 1 msms Master Sample Standard [30:30] delay 0 standard 1 tbc Transfer Bits Completed [25:25] busy 0 completed 1 tbc_int_en Transfer Bits Completed Interrupt Enable [24:24] disable 0 enable 1 rx_frm_len Configure the length of serial data frame of RX [21:16] tx_frm_len Configure the length of serial data frame of TX [13:8] ss_level [7:7] low 0 high 1 ss_owner SS Output Owner Select [6:6] SPI_controller 0 Software 1 spol SPI Chip Select Signal Polarity Control [5:5] high 0 low 1 ss_sel SPI Chip Select [3:2] SS0 0b00 SS1 0b01 SS2 0b10 SS3 0b11 wms Work Mode Select [1:0] byte_aligned 0b00 reserved 0b01 bit_aligned_3wire 0b10 bit_aligned_standard 0b11 SPI_BA_CCR SPI Bit-Aligned Clock Configuration Register 0x0044 cdr_n Clock Divide Rate [7:0] SPI_TBR SPI TX Bit Register\n\nVTB [31:0]: The Value of the Transmit Bits 0x0048 SPI_RBR SPI RX Bit Register\n\nVRB [31:0]: The Value of the Receive Bits 0x004C SPI_NDMA_MODE_CTL SPI Normal DMA Mode Control Register 0x0088 spi_act_m SPI NDMA Active Mode [7:6] low 0b00 high 0b01 drq_control 0b10 controller_control 0b11 spi_ack_m SPI NDMA Acknowledge Mode [5:5] ignore 0 after_detect 1 spi_dma_wait [4:0] SPI_TXD SPI TX Data Register\n\nTDATA [31:0]: Transmit Data 0x0200 SPI_RXD SPI RX Data Register\n\nRDATA [31:0]: Receive Data 0x0300 SPI_DBI Serial Peripheral Interface Display Bus Interface Interfaces 0x04026000 0 0x1000 registers SPI1 32 SPI_GCR SPI Global Control Register 0x0004 srst Soft reset [31:31] tp_en Transmit Pause Enable [7:7] normal normal operation, ignore RXFIFO status 0 stop_when_full Stop transmit data when RXFIFO full 1 mode_selec Sample timing Mode Select [2:2] old_mode Old mode of Sample Timing 0 new_mode New mode of Sample Timing 1 mode SPI Function Mode Select [1:1] slave 0 master 1 en SPI Module Enable Control [0:0] disable 0 enable 1 SPI_TCR SPI Transfer Control Register 0x0008 xch Exchange Burst [31:31] idle 0 initiate_exchange 1 sdc1 Master Sample Data Control register1 [15:15] normal normal operation, do not delay the internal read sample point 0 delay delay the internal read sample point 1 sddm Sending Data Delay Mode [14:14] normal normal sending 0 delay delay sending 1 sdm Master Sample Data Mode [13:13] delay delay sample mode 0 normal normal sample mode 1 fbs First Transmit Bit Select [12:12] msb MSB first 0 lsb LSB first 1 sdc Master Sample Data Control [11:11] normal Normal operation, do not delay the internal read sample point 0 delay Delay the internal read sample point 1 rpsm Rapids Mode Select [10:10] normal Normal write mode 0 rapid Rapid write mode 1 ddb Dummy Burst Type [9:9] zero The bit value of dummy SPI burst is zero 0 one The bit value of dummy SPI burst is one 1 dhb Discard Hash Burst [8:8] receive Receiving all SPI bursts in the BC period 0 discard Discard unused SPI bursts 1 ss_level [7:7] low 0 high 1 ss_owner [6:6] spi_controller 0 software 1 ss_sel [5:4] ss0 0b00 ss1 0b01 ss2 0b10 ss3 0b11 ssctl [3:3] assert SPI_SSx remains asserted between SPI bursts 0 negate Negate SPI_SSx between SPI bursts 1 spol SPI Chip Select Signal Polarity Control [2:2] high Active high polarity 0 low Active low polarity 1 cpol SPI Clock Polarity Control [1:1] high Active high polarity 0 low Active low polarity 1 cpha SPI Clock/Data Phase Control [0:0] P0 Phase 0 (Leading edge for sample data) 0 P1 Phase 1 (Leading edge for setup data) 1 SPI_IER SPI Interrupt Control Register 0x0010 ss_int_en SSI Interrupt Enable [13:13] disable 0 enable 1 tc_int_en Transfer Completed Interrupt Enable [12:12] disable 0 enable 1 tf_udr_int_en TXFIFO Underrun Interrupt Enable [11:11] disable 0 enable 1 tf_ovf_int_en TXFIFO Overflow Interrupt Enable [10:10] disable 0 enable 1 rf_udr_int_en RXFIFO Underrun Interrupt Enable [9:9] disable 0 enable 1 rf_ovf_int_en RXFIFO Overflow Interrupt Enable [8:8] disable 0 enable 1 tf_full_int_en TXFIFO Full Interrupt Enable [6:6] disable 0 enable 1 tf_emp_int_en TXFIFO Empty Interrupt Enable [5:5] disable 0 enable 1 tf_erq_int_en TXFIFO Empty Request Interrupt Enable [4:4] disable 0 enable 1 rf_full_int_en RXFIFO Full Interrupt Enable [2:2] disable 0 enable 1 rf_emp_int_en RXFIFO Empty Interrupt Enable [1:1] disable 0 enable 1 rf_rdy_int_en RXFIFO Ready Request Interrupt Enable [0:0] disable 0 enable 1 SPI_ISR SPI Interrupt Status Register 0x0014 ssi SS Invalid Enable [13:13] tc Transfer Completed [12:12] busy 0 transfer_completed 1 tf_udr TXFIFO Underrun [11:11] not_underrun 0 underrun 1 tf_ovf TXFIFO Overflow [10:10] not_overflow 0 overflow 1 rf_udr RXFIFO Underrun [9:9] not_underrun 0 underrun 1 rf_ovf RXFIFO Overflow [8:8] not_overflow 0 overflow 1 tf_full TXFIFO Full [6:6] not_full 0 full 1 tf_emp TXFIFO Empty [5:5] not_empty 0 empty 1 tf_ready TXFIFO Ready [4:4] rf_full RXFIFO Full [2:2] not_full 0 full 1 rf_emp RXFIFO Empty [1:1] not_empty 0 empty 1 rf_rdy RXFIFO Ready [0:0] SPI_FCR SPI FIFO Control Register 0x0018 tf_rst TXFIFO Reset [31:31] tf_test_en TXFIFO Test Mode Enable [30:30] disable 0 enable 1 tf_drq_en TXFIFO DMA Request Enable [24:24] disable 0 enable 1 tf_trig_level TXFIFO Empty Request Trigger Level [23:16] rf_rst RXFIFO Reset [15:15] rf_test_en RXFIFO Test Mode Enable [14:14] disable 0 enable 1 rf_drq_en RXFIFO DMA Request Enable [8:8] disable 0 enable 1 rf_trig_level RXFIFO Ready Request Trigger Level [7:0] SPI_FSR SPI FIFO Status Register 0x001C read-only tb_wr TXFIFO Write Buffer Write Enable [31:31] tb_cnt TXFIFO Write Buffer Counter [30:28] tf_cnt TXFIFO Counter\n\nThese bits indicate the number of bytes in TXFIFO [23:16] rb_wr RXFIFO Write Buffer Write Enable [15:15] rb_cnt RXFIFO Write Buffer Counter [14:12] rf_cnt RXFIFO Counter\n\nThese bits indicate the number of bytes in RXFIFO [7:0] SPI_WCR SPI Wait Clock Register 0x0020 swc Dual mode direction switch wait clock counter [19:16] wwc Wait clock counter [15:0] SPI_SAMP_DL SPI Sample Delay Control Register 0x0028 samp_dl_cal_start Sample Delay Calibration Start [15:15] samp_dl_cal_done Sample Delay Calibration Dont [14:14] read-only samp_dl Sample Delay [13:8] read-only samp_dl_sw_en Sample Delay Software Enable [7:7] samp_dl_sw Sample Delay Software [5:0] SPI_MBC SPI Master Burst Counter Register 0x0030 mbc Master Burst Counter [23:0] SPI_MTC SPI Master Transmit Counter Register 0x0034 mwtc Master Write Transmit Counter [23:0] SPI_BCC SPI Master Burst Control Register 0x0038 quad_en Quad Mode Enable [29:29] disable 0 enable 1 drm Master Dual Mode RX Enable [28:28] single 0 dual 1 dbc Master Dummy Burst Counter [27:24] stc Master Single Mode Transmit Counter [23:0] SPI_BATC SPI Bit-Aligned Transfer Configure Register 0x0040 tce Transfer Control Enable [31:31] idle 0 init 1 msms Master Sample Standard [30:30] delay 0 standard 1 tbc Transfer Bits Completed [25:25] busy 0 completed 1 tbc_int_en Transfer Bits Completed Interrupt Enable [24:24] disable 0 enable 1 rx_frm_len Configure the length of serial data frame of RX [21:16] tx_frm_len Configure the length of serial data frame of TX [13:8] ss_level [7:7] low 0 high 1 ss_owner SS Output Owner Select [6:6] SPI_controller 0 Software 1 spol SPI Chip Select Signal Polarity Control [5:5] high 0 low 1 ss_sel SPI Chip Select [3:2] SS0 0b00 SS1 0b01 SS2 0b10 SS3 0b11 wms Work Mode Select [1:0] byte_aligned 0b00 reserved 0b01 bit_aligned_3wire 0b10 bit_aligned_standard 0b11 SPI_BA_CCR SPI Bit-Aligned Clock Configuration Register 0x0044 cdr_n Clock Divide Rate [7:0] SPI_TBR SPI TX Bit Register\n\nVTB [31:0]: The Value of the Transmit Bits 0x0048 SPI_RBR SPI RX Bit Register\n\nVRB [31:0]: The Value of the Receive Bits 0x004C SPI_NDMA_MODE_CTL SPI Normal DMA Mode Control Register 0x0088 spi_act_m SPI NDMA Active Mode [7:6] low 0b00 high 0b01 drq_control 0b10 controller_control 0b11 spi_ack_m SPI NDMA Acknowledge Mode [5:5] ignore 0 after_detect 1 spi_dma_wait [4:0] DBI_CTL_0 DBI Control Register 0 0x0100 cmdt Command Type [31:31] write 0 read 1 wcdc Write Command Dummy Cycles [30:20] dat_seq Output Data Sequence [19:19] msb 0 lsb 1 rgb_seq Output RGB Sequence [18:16] RGB 0b000 RBG 0b001 GRB 0b010 GBR 0b011 BRG 0b100 BGR 0b101 tran_mod Transmit Mode [15:15] command_parameter 0 video 1 dat_fmt Output Data Format [14:12] RGB111 0b000 RGB444 0b001 RGB565 0b010 RGB666 0b011 RGB888 0b100 dbi_interface [10:8] L3I1 3 Line Interface I 0b000 L3I2 3 Line Interface II 0b001 L4I1 4 Line Interface I 0b010 L4I2 4 Line Interface II 0b011 D2LI 2 Data Lane Interface 0b100 rgb_src_fmt RGB Source Format [7:4] RGB 0b000 RBG 0b001 GRB 0b010 GBR 0b011 BRG 0b100 BGR 0b101 GRBG_0 0b110 GBRG_0 0b111 GRBG_1 0b1000 GBRG_1 0b1001 dum_val Dummy Cycle Value [3:3] rgb_bo RGB Bit Order [2:2] data 0 swap 1 element_a_pos Element A Position [1:1] 31_24 0 7_0 1 vi_src_type Video Source Type [0:0] rgb32 0 rgb16 1 DBI_CTL_1 DBI Control Register 1 0x0104 dbi_soft_trg DBI Soft Trigger [31:31] dbi_en_mode_sel DBI Enable Mode Select [30:29] DBI 0b00 Software 0b01 Timer 0b10 TE 0b11 RGB666_FMT 2 Data Lane RGB666 Format [27:26] normal 0b00 special_ilitek 0b01 special_new_vision 0b10 dbi_rxclk_inv DBI RX Clock Inverse [25:25] positive 0 negative 1 dbi_clko_mod DBI Output Clock Mode [24:24] always_on 0 auto_gating 1 dbi_clko_inv DBI Clock Output Inverse [23:23] dcx_data DCX Data Value [22:22] RGB16_data_source_select RGB 16 Data Source Select [21:21] rdat_lsb Bit Order of Read Data [20:20] rcdc Read Command Dummy Cycles [15:8] rdbn Read Data Number of Bytes [7:0] DBI_CTL_2 DBI Control Register 2 0x0108 dbi_fifo_drq_en DBI FIFO DMA Request Enable [15:15] dbi_trig_level DBI FIFO Empty Request Trigger Level [14:8] dbi_sdq_out_sel DBI SDI PIN Output Select [6:6] dbi_dcx_sel DBI DCX PIN Function Select [5:5] dbi_sdi_sel DBI SDI PIN FUnction Select [4:3] dbi_sdi 0b00 dbi_te 0b01 dbi_dcx 0b10 te_dbc_sel TE debounce function select [2:2] te_trig_sel TE edge trigger select [1:1] te_en TE Enable [0:0] DBI_TIMER DBI Timer Control Register 0x010C dbi_tm_en DBI Timer Enable [31:31] enable 0 disable 1 dbi_timer_value [30:0] DBI_VIDEO_SZIE DBI Video Size Configuration Register 0x0110 v_size [26:16] h_size [10:0] DBI_INT DBI Interrupt Register 0x0120 dbi_fifo_empty_int [14:14] dbi_fifo_full_int [13:13] timer_int [12:12] rd_done_int [11:11] te_int [10:10] fram_done_int [9:9] line_done_int [8:8] dbi_fifo_empty_int_en [6:6] dbi_fifo_full_int_en [5:5] timer_int_en [4:4] rd_done_int_en [3:3] te_int_en [2:2] fram_done_int_en [1:1] line_done_int_en [0:0] DBI_DEBUG_0 DBI BEBUG 0 Register 0x0124 read-only dbi_fifo_avail [22:16] te_val [12:12] dbi_rxcs [11:8] sh_cs [7:4] dbi_txcs [3:2] mem_cs [1:0] DBI_DEBUG_1 DBI BEBUG 1 Register 0x0128 read-only lcnt [25:16] ccnt [11:0] SPI_TXD SPI TX Data Register\n\nTDATA [31:0]: Transmit Data 0x0200 SPI_RXD SPI RX Data Register\n\nRDATA [31:0]: Receive Data 0x0300 USB0 USB2.0 DRD Interfaces 0x04100000 0 0x100000 registers USB0_DEVICE 45 USB0_EHCI 46 USB0_OHCI 47 USB1 USB2.0 HOST Interfaces 0x04200000 0 0x100000 registers USB1_EHCI 49 USB1_OHCI 50 E_CAPLENGTH EHCI Capability Register Length Register 0x0000 E_HCIVERSION EHCI Host Interface Version Number Register 0x0002 E_HCSPARAMS EHCI Host Control Structural Parameter Register 0x0004 E_HCCPARAMS EHCI Host Control Capability Parameter Register 0x0008 E_HCSPPORTROUTE EHCI Companion Port Route Description 0x000C E_USBCMD EHCI USB Command Register 0x0010 E_USBSTS EHCI USB Status Register 0x0014 E_USBINTR EHCI USB Interrupt Enable Register 0x0018 E_FRINDEX EHCI USB Frame Index Register 0x001C E_CTRLDSSEGMENT EHCI 4G Segment Selector Register 0x0020 E_PERIODICLISTBASE EHCI Frame List Base Address Register 0x0024 E_ASYNCLISTADDR EHCI Next Asynchronous List Address Register 0x0028 E_CONFIGFLAG EHCI Configured Flag Register 0x0050 E_PORTSC EHCI Port Status/Control Register 0x0054 O_HcControl OHCI Control Register 0x0404 O_HcCommandStatus OHCI Command Status Register 0x0408 O_HcInterruptStatus OHCI Interrupt Status Register 0x040C O_HcInterruptEnable OHCI Interrupt Enable Register 0x0410 O_HcInterruptDisable OHCI Interrupt Disable Register 0x0414 O_HcHCCA OHCI HCCA Base 0x0418 O_HcPeriodCurrentED OHCI Period Current ED Base 0x041C O_HcControlHeadED OHCI Control Head ED Base 0x0420 O_HcControlCurrentED OHCI Control Current ED Base 0x0424 O_HcBulkHeadED OHCI Bulk Head ED Base 0x0428 O_HcBulkCurrentED OHCI Bulk Current ED Base 0x042C O_HcDoneHead OHCI Done Head Base 0x0430 O_HcFmInterval OHCI Frame Interval Register 0x0434 O_HcFmRemaining OHCI Frame Remaining Register 0x0438 O_HcFmNumber OHCI Frame Number Register 0x043C O_HcPerioddicStart OHCI Periodic Start Register 0x0440 O_HcLSThreshold OHCI LS Threshold Register 0x0444 O_HcRhDescriptorA OHCI Root Hub Descriptor Register A 0x0448 O_HcRhDesriptorB OHCI Root Hub Descriptor Register B 0x044C O_HcRhStatus OHCI Root Hub Status Register 0x0450 O_HcRhPortStatus OHCI Root Hub Port Status Register 0x0454 HCI_Interface HCI Interface Register 0x0800 HCI_CTRL3 HCI Control Register 0x0808 PHY_Control PHY Control Register 0x0810 PHY_STATUS PHY Status Register 0x0824 HCI_SIE_PORT_DISABLE_CONTROL HCI SIE Port Disable Control Register 0x0828 GPIO Gerneral Purpose Input/Output Interfaces 0x02000000 0 0x800 registers GPIOB_NS 85 GPIOC_NS 87 GPIOD_NS 89 GPIOE_NS 91 GPIOF_NS 93 pb_cfg0 PB Configure Register 0 0x0030 pb7_select [31:28] input 0b0000 output 0b0001 lcd0_d17 0b0010 i2_s2_mclk 0b0011 twi3_sda 0b0100 ir_rx 0b0101 lcd0_d23 0b0110 uart3_rx 0b0111 cpubist1 0b1000 reserved 0b1001 pb_eint7 0b1110 io_disable 0b1111 pb6_select [27:24] input 0b0000 output 0b0001 lcd0_d16 0b0010 i2_s2_lrck 0b0011 twi3_sck 0b0100 pwm1 0b0101 lcd0_d22 0b0110 uart3_tx 0b0111 cpubist0 0b1000 reserved 0b1001 pb_eint6 0b1110 io_disable 0b1111 pb5_select [23:20] input 0b0000 output 0b0001 lcd0_d9 0b0010 i2_s2_bclk 0b0011 twi1_sda 0b0100 pwm0 0b0101 lcd0_d21 0b0110 uart5_rx 0b0111 reserved 0b1000 reserved 0b1001 pb_eint5 0b1110 io_disable 0b1111 pb4_select [19:16] input 0b0000 output 0b0001 lcd0_d8 0b0010 i2_s2_dout0 0b0011 twi1_sck 0b0100 i2_s2_din1 0b0101 lcd0_d20 0b0110 uart5_tx 0b0111 reserved 0b1000 reserved 0b1001 pb_eint4 0b1110 io_disable 0b1111 pb3_select [15:12] input 0b0000 output 0b0001 lcd0_d1 0b0010 i2_s2_dout1 0b0011 twi0_sck 0b0100 i2_s2_din0 0b0101 lcd0_d19 0b0110 uart4_rx 0b0111 reserved 0b1000 reserved 0b1001 pb_eint3 0b1110 io_disable 0b1111 pb2_select [11:8] input 0b0000 output 0b0001 lcd0_d0 0b0010 i2_s2_dout2 0b0011 twi0_sda 0b0100 i2_s2_din2 0b0101 lcd0_d18 0b0110 uart4_tx 0b0111 reserved 0b1000 reserved 0b1001 pb_eint2 0b1110 io_disable 0b1111 pb1_select [7:4] input 0b0000 output 0b0001 pwm4 0b0010 i2_s2_dout3 0b0011 twi2_sda 0b0100 i2_s2_din3 0b0101 uart0_rx 0b0110 uart2_rx 0b0111 ir_rx 0b1000 reserved 0b1001 pb_eint1 0b1110 io_disable 0b1111 pb0_select [3:0] input 0b0000 output 0b0001 pwm3 0b0010 ir_tx 0b0011 twi2_sck 0b0100 spi1_wp__dbi_te 0b0101 uart0_tx 0b0110 uart2_tx 0b0111 owa_out 0b1000 reserved 0b1001 pb_eint0 0b1110 io_disable 0b1111 pb_cfg1 PB Configure Register 1 0x0034 pb12_select [19:16] input 0b0000 output 0b0001 dmic_clk 0b0010 pwm0 0b0011 owa_in 0b0100 spi1_cs__dbi_csx 0b0101 clk_fanout2 0b0110 ir_rx 0b0111 reserved 0b1000 reserved 0b1001 pb_eint12 0b1110 io_disable 0b1111 pb11_select [15:12] input 0b0000 output 0b0001 dmic_data0 0b0010 pwm2 0b0011 twi0_sda 0b0100 spi1_clk__dbi_sclk 0b0101 clk_fanout1 0b0110 uart1_cts 0b0111 reserved 0b1000 reserved 0b1001 pb_eint11 0b1110 io_disable 0b1111 pb10_select [11:8] input 0b0000 output 0b0001 dmic_data1 0b0010 pwm7 0b0011 twi0_sck 0b0100 spi1_mosi__dbi_sdo 0b0101 clk_fanout0 0b0110 uart1_rts 0b0111 reserved 0b1000 reserved 0b1001 pb_eint10 0b1110 io_disable 0b1111 pb9_select [7:4] input 0b0000 output 0b0001 dmic_data2 0b0010 pwm6 0b0011 twi2_sda 0b0100 spi1_miso__dbi_sdi__dbi_te__dbi_dcx 0b0101 uart0_rx 0b0110 uart1_rx 0b0111 reserved 0b1000 reserved 0b1001 pb_eint9 0b1110 io_disable 0b1111 pb8_select [3:0] input 0b0000 output 0b0001 dmic_data3 0b0010 pwm5 0b0011 twi2_sck 0b0100 spi1_hold_dbi_dcx_dbi_wrx 0b0101 uart0_tx 0b0110 uart1_tx 0b0111 reserved 0b1000 reserved 0b1001 pb_eint8 0b1110 io_disable 0b1111 pb_dat PB Data Register 0x0040 pb_dat [12:0] pb_drv0 PB Multi_Driving Register 0 0x0044 8 4 PB%s_DRV PB Multi_Driving Select [1:0] L0 0 L1 1 L2 2 L3 3 pb_drv1 PB Multi_Driving Register 1 0x0048 5 4 8-12 PB%s_DRV PB Multi_Driving Select [1:0] L0 0 L1 1 L2 2 L3 3 pb_pull0 PB Pull Register 0 0x0054 13 2 PC%s_PULL PC Pull_up/down Select [1:0] pull_disable 0 pull_up 1 pull_down 2 reserved 3 pc_cfg0 PC Configure Register 0 0x0060 PC7_SELECT PC7 Select [31:28] Input 0b0000 SPI0_HOLD 0b0010 UART3_RX 0b0100 TCON_TRIG 0b0110 Reserved 0b1000 PC_EINT7 0b1110 Output 0b0001 SDC2_D3 0b0011 TWI3_SDA 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PC6_SELECT PC6 Select [27:24] Input 0b0000 SPI0_WP 0b0010 UART3_TX 0b0100 DBG_CLK 0b0110 Reserved 0b1000 PC_EINT6 0b1110 Output 0b0001 SDC2_D0 0b0011 TWI3_SCK 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PC5_SELECT PC5 Select [23:20] Input 0b0000 SPI0_MISO 0b0010 BOOT_SEL1 0b0100 Reserved 0b0110 Reserved 0b1000 PC_EINT5 0b1110 Output 0b0001 SDC2_D1 0b0011 Reserved 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PC4_SELECT PC4 Select [19:16] Input 0b0000 SPI0_MOSI 0b0010 BOOT_SEL0 0b0100 Reserved 0b0110 Reserved 0b1000 PC_EINT4 0b1110 Output 0b0001 SDC2_D2 0b0011 Reserved 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PC3_SELECT PC3 Select [15:12] Input 0b0000 SPI0_CS0 0b0010 Reserved 0b0100 Reserved 0b0110 Reserved 0b1000 PC_EINT3 0b1110 Output 0b0001 SDC2_CMD 0b0011 Reserved 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PC2_SELECT PC2 Select [11:8] Input 0b0000 SPI0_CLK 0b0010 Reserved 0b0100 Reserved 0b0110 Reserved 0b1000 PC_EINT2 0b1110 Output 0b0001 SDC2_CLK 0b0011 Reserved 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PC1_SELECT PC1 Select. [7:4] Input 0b0000 UART2_RX 0b0010 Reserved 0b0100 Reserved 0b0110 Reserved 0b1000 PC_EINT1 0b1110 Output 0b0001 TWI2_SDA 0b0011 Reserved 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PC0_SELECT PC0 Select [3:0] Input 0b0000 UART2_TX 0b0010 LEDC_DO 0b0100 Reserved 0b0110 Reserved 0b1000 PC_EINT0 0b1110 Output 0b0001 TWI2_SCK 0b0011 Reserved 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 pc_dat PC Data Register 0x0070 PC_DAT [7:0] pc_drv0 PC Multi_Driving Register 0 0x0074 8 4 PC%s_DRV PC Multi_Driving Select [1:0] L0 0 L1 1 L2 2 L3 3 pc_pull0 PC Pull Register 0 0x0084 8 2 PC%s_PULL PC Pull_up/down Select [1:0] pull_disable 0 pull_up 1 pull_down 2 reserved 3 pd_cfg0 PD Configure Register 0 0x0090 PD7_SELECT PD7 Select [31:28] Input 0b0000 LCD0_D11 0b0010 DSI_D2N 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT7 0b1110 Output 0b0001 LVDS0_CKN 0b0011 UART4_TX 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD6_SELECT PD6 Select [27:24] Input 0b0000 LCD0_D10 0b0010 DSI_D2P 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT6 0b1110 Output 0b0001 LVDS0_CKP 0b0011 UART5_RX 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD5_SELECT PD5 Select [23:20] Input 0b0000 LCD0_D7 0b0010 DSI_CKN 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT5 0b1110 Output 0b0001 LVDS0_V2N 0b0011 UART5_TX 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD4_SELECT PD4 Select [19:16] Input 0b0000 LCD0_D6 0b0010 DSI_CKP 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT4 0b1110 Output 0b0001 LVDS0_V2P 0b0011 UART2_CTS 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD3_SELECT PD3 Select [15:12] Input 0b0000 LCD0_D5 0b0010 DSI_D1N 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT3 0b1110 Output 0b0001 LVDS0_V1N 0b0011 UART2_RTS 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD2_SELECT PD2 Select [11:8] Input 0b0000 LCD0_D4 0b0010 DSI_D1P 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT2 0b1110 Output 0b0001 LVDS0_V1P 0b0011 UART2_RX 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD1_SELECT PD1 Select [7:4] Input 0b0000 LCD0_D3 0b0010 DSI_D0N 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT1 0b1110 Output 0b0001 LVDS0_V0N 0b0011 UART2_TX 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD0_SELECT PD0 Select [3:0] Input 0b0000 LCD0_D2 0b0010 DSI_D0P 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT0 0b1110 Output 0b0001 LVDS0_V0P 0b0011 TWI0_SCK 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 pd_cfg1 PD Configure Register 1 0x0094 PD15_SELECT PD15 Select [31:28] Input 0b0000 LCD0_D21 0b0010 SPI1_WP_DBI_TE 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT15 0b1110 Output 0b0001 LVDS1_V2N 0b0011 IR_RX 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD14_SELECT PD14 Select [27:24] Input 0b0000 LCD0_D20 0b0010 SPI1_HOLD_DBI_DCX_DBI_WRX 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT14 0b1110 Output 0b0001 LVDS1_V2P 0b0011 UART3_CTS 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD13_SELECT PD13 Select [23:20] Input 0b0000 Output 0b0001 LCD0_D19 0b0010 LVDS1_V1N 0b0011 SPI1_MISO_DBI_SDI_DBI_TE_DBI_DCX 0b0100 UART3_RTS 0b0101 Reserved 0b0110 Reserved 0b1000 PD_EINT13 0b1110 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD12_SELECT PD12 Select [19:16] Input 0b0000 LCD0_D18 0b0010 SPI1_MOSI_DBI_SDO 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT12 0b1110 Output 0b0001 LVDS1_V1P 0b0011 TWI0_SDA 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD11_SELECT PD11 Select [15:12] Input 0b0000 LCD0_D15 0b0010 SPI1_CLK_DBI_SCLK 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT11 0b1110 Output 0b0001 LVDS1_V0N 0b0011 UART3_RX 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD10_SELECT PD10 Select [11:8] Input 0b0000 LCD0_D14 0b0010 SPI1_CS_DBI_CSX 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT10 0b1110 Output 0b0001 LVDS1_V0P 0b0011 UART3_TX 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD9_SELECT PD9 Select [7:4] Input 0b0000 LCD0_D13 0b0010 DSI_D3N 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT9 0b1110 Output 0b0001 LVDS0_V3N 0b0011 PWM6 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD8_SELECT PD8 Select [3:0] Input 0b0000 LCD0_D12 0b0010 DSI_D3P 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT8 0b1110 Output 0b0001 LVDS0_V3P 0b0011 UART4_RX 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 pd_cfg2 PD Configure Register 2 0x0098 PD22_SELECT PD22 Select [27:24] Input 0b0000 OWA_OUT 0b0010 UART1_RX 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT22 0b1110 Output 0b0001 IR_RX 0b0011 PWM7 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD21_SELECT PD21 Select [23:20] Input 0b0000 LCD0_VSYNC 0b0010 UART1_TX 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT21 0b1110 Output 0b0001 TWI2_SDA 0b0011 PWM5 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD20_SELECT PD20 Select [19:16] Input 0b0000 LCD0_HSYNC 0b0010 DMIC_CLK 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT20 0b1110 Output 0b0001 TWI2_SCK 0b0011 PWM4 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD19_SELECT PD19 Select [15:12] Input 0b0000 LCD0_DE 0b0010 DMIC_DATA0 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT19 0b1110 Output 0b0001 LVDS1_V3N 0b0011 PWM3 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD18_SELECT PD18 Select [11:8] Input 0b0000 LCD0_CLK 0b0010 DMIC_DATA1 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT18 0b1110 Output 0b0001 LVDS1_V3P 0b0011 PWM2 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD17_SELECT PD17 Select [7:4] Input 0b0000 LCD0_D23 0b0010 DMIC_DATA2 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT17 0b1110 Output 0b0001 LVDS1_CKN 0b0011 PWM1 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PD16_SELECT PD16 Select [3:0] Input 0b0000 LCD0_D22 0b0010 DMIC_DATA3 0b0100 Reserved 0b0110 Reserved 0b1000 PD_EINT16 0b1110 Output 0b0001 LVDS1_CKP 0b0011 PWM0 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 pd_dat PD Data Register 0x00A0 pd_dat [22:0] pd_drv0 PD Multi_Driving Register 0 0x00A4 8 4 PD%s_DRV PD Multi_Driving Select [1:0] L0 0 L1 1 L2 2 L3 3 pd_drv1 PD Multi_Driving Register 1 0x00A8 8 4 8-15 PD%s_DRV PD Multi_Driving Select [1:0] L0 0 L1 1 L2 2 L3 3 pd_drv2 PD Multi_Driving Register 2 0x00AC 7 4 16-22 PD%s_DRV PD Multi_Driving Select [1:0] L0 0 L1 1 L2 2 L3 3 pd_pull0 PD Pull Register 0 0x00B4 16 2 PD%s_PULL PD Pull_up/down Select [1:0] pull_disable 0 pull_up 1 pull_down 2 reserved 3 pd_pull1 PD Pull Register 1 0x00B8 7 2 16-22 PD%s_PULL PD Pull_up/down Select [1:0] pull_disable 0 pull_up 1 pull_down 2 reserved 3 pe_cfg0 PE Configure Register 0 0x00C0 PE7_SELECT PE7 Select [31:28] Input 0b0000 NCSI0_D3 0b0010 TWI3_SDA 0b0100 D_JTAG_CK 0b0110 RGMII_CLKIN_RMII_RXER 0b1000 Reserved 0b1001 PE_EINT7 0b1110 IO_Disable 0b1111 Output 0b0001 UART5_RX 0b0011 OWA_OUT 0b0101 R_JTAG_CK 0b0111 PE6_SELECT PE6 Select [27:24] Input 0b0000 NCSI0_D2 0b0010 TWI3_SCK 0b0100 D_JTAG_DO 0b0110 RMII_TXCTRL_RMII_TXEN 0b1000 Reserved 0b1001 PE_EINT6 0b1110 IO_Disable 0b1111 Output 0b0001 UART5_TX 0b0011 OWA_IN 0b0101 R_JTAG_DO 0b0111 PE5_SELECT PE5 Select [23:20] Input 0b0000 NCSI0_D1 0b0010 TWI2_SDA 0b0100 D_JTAG_DI 0b0110 RGMII_TXD1_RMII_TXD1 0b1000 Reserved 0b1001 PE_EINT5 0b1110 IO_Disable 0b1111 Output 0b0001 UART4_RX 0b0011 LEDC_DO 0b0101 R_JTAG_DI 0b0111 PE4_SELECT PE4 Select [19:16] Input 0b0000 NCSI0_D0 0b0010 TWI2_SCK 0b0100 D_JTAG_MS 0b0110 RGMII_TXD0_RMII_TXD0 0b1000 Reserved 0b1001 PE_EINT4 0b1110 IO_Disable 0b1111 Output 0b0001 UART4_TX 0b0011 CLK_FANOUT2 0b0101 R_JTAG_MS 0b0111 PE3_SELECT PE3 Select [15:12] Input 0b0000 NCSI0_MCLK 0b0010 TWI0_SDA 0b0100 UART0_RX 0b0110 RGMII_TXCK_RMII_TXCK 0b1000 Reserved 0b1001 PE_EINT3 0b1110 IO_Disable 0b1111 Output 0b0001 UART2_RX 0b0011 CLK_FANOUT1 0b0101 Reserved 0b0111 PE2_SELECT PE2 Select [11:8] Input 0b0000 NCSI0_PCLK 0b0010 TWI0_SCK 0b0100 UART0_TX 0b0110 RGMII_RXD1_RMII_RXD1 0b1000 Reserved 0b1001 PE_EINT2 0b1110 IO_Disable 0b1111 Output 0b0001 UART2_TX 0b0011 CLK_FANOUT0 0b0101 Reserved 0b0111 PE1_SELECT PE1 Select [7:4] Input 0b0000 NCSI0_VSYNC 0b0010 TWI1_SDA 0b0100 Reserved 0b0110 RGMII_RXD0_RMII_RXD0 0b1000 PE_EINT1 0b1110 Output 0b0001 UART2_CTS 0b0011 LCD0_VSYNC 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PE0_SELECT PE0 Select [3:0] Input 0b0000 NCSI0_HSYNC 0b0010 TWI1_SCK 0b0100 Reserved 0b0110 RGMII_RXCTRL_RMII_CRS_DV 0b1000 PE_EINT0 0b1110 Output 0b0001 UART2_RTS 0b0011 LCD0_HSYNC 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 pe_cfg1 PE Configure Register 1 0x00C4 PE15_SELECT PE15 Select [31:28] Input 0b0000 TWI1_SDA 0b0010 PWM6 0b0100 DMIC_DATA1 0b0110 RGMII_RXCK 0b1000 PE_EINT15 0b1110 Output 0b0001 D_JTAG_DI 0b0011 I2S0_LRCK 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PE14_SELECT PE14 Select [27:24] Input 0b0000 TWI1_SCK 0b0010 I2S0_DOUT1 0b0100 DMIC_DATA2 0b0110 RGMII_RXD3 0b1000 PE_EINT14 0b1110 Output 0b0001 D_JTAG_MS 0b0011 I2S0_DIN0 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PE13_SELECT PE13 Select [23:20] Input 0b0000 TWI2_SDA 0b0010 I2S0_DOUT0 0b0100 DMIC_DATA3 0b0110 RGMII_RXD2 0b1000 PE_EINT13 0b1110 Output 0b0001 PWM5 0b0011 I2S0_DIN1 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PE12_SELECT PE12 Select [19:16] Input 0b0000 TWI2_SCK 0b0010 I2S0_DOUT2 0b0100 Reserved 0b0110 RGMII_TXD3 0b1000 PE_EINT12 0b1110 Output 0b0001 NCSI0_FIELD 0b0011 I2S0_DIN2 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PE11_SELECT PE11 Select [15:12] Input 0b0000 NCSI0_D7 0b0010 I2S0_DOUT3 0b0100 JTAG_CK 0b0110 RGMII_TXD2 0b1000 PE_EINT11 0b1110 Output 0b0001 UART1_RX 0b0011 I2S0_DIN3 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PE10_SELECT PE10 Select [11:8] Input 0b0000 NCSI0_D6 0b0010 PWM4 0b0100 JTAG_DO 0b0110 EPHY_25M 0b1000 PE_EINT10 0b1110 Output 0b0001 UART1_TX 0b0011 IR_RX 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PE9_SELECT PE9 Select [7:4] Input 0b0000 NCSI0_D5 0b0010 PWM3 0b0100 JTAG_DI 0b0110 MDIO 0b1000 PE_EINT9 0b1110 Output 0b0001 UART1_CTS 0b0011 UART3_RX 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PE8_SELECT PE8 Select [3:0] Input 0b0000 NCSI0_D4 0b0010 PWM2 0b0100 JTAG_MS 0b0110 MDC 0b1000 PE_EINT8 0b1110 Output 0b0001 UART1_RTS 0b0011 UART3_TX 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 pe_cfg2 PE Configure Register 2 0x00C8 PE17_SELECT PE17 Select [7:4] Input 0b0000 TWI3_SDA 0b0010 IR_TX 0b0100 DMIC_CLK 0b0110 Reserved 0b1000 PE_EINT17 0b1110 Output 0b0001 D_JTAG_CK 0b0011 I2S0_MCLK 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PE16_SELECT PE16 Select [3:0] Input 0b0000 TWI3_SCK 0b0010 PWM7 0b0100 DMIC_DATA0 0b0110 Reserved 0b1000 PE_EINT16 0b1110 Output 0b0001 D_JTAG_DO 0b0011 I2S0_BCLK 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 pe_dat PE Data Register 0x00D0 PE_DAT PE Data [17:0] pe_drv0 PE Multi_Driving Register 0 0x00D4 8 4 PE%s_DRV PE Multi_Driving Select [1:0] L0 0 L1 1 L2 2 L3 3 pe_drv1 PE Multi_Driving Register 1 0x00D8 8 4 8-15 PE%s_DRV PE Multi_Driving Select [1:0] L0 0 L1 1 L2 2 L3 3 pe_drv2 PE Multi_Driving Register 2 0x00DC 2 4 16-17 PE%s_DRV PE Multi_Driving Select [1:0] L0 0 L1 1 L2 2 L3 3 pe_pull0 PE Pull Register 0 0x00E4 16 2 PE%s_PULL PE Pull_up/down Select [1:0] pull_disable 0 pull_up 1 pull_down 2 reserved 3 pe_pull1 PE Pull Register 1 0x00E8 2 2 16-17 PE%s_PULL PE Pull_up/down Select [1:0] pull_disable 0 pull_up 1 pull_down 2 reserved 3 pf_cfg0 PF Configure Register 0 0x00F0 PF6_SELECT PF6 Select [27:24] Input 0b0000 Reserved 0b0010 IR_RX 0b0100 PWM5 0b0110 Reserved 0b1000 PF_EINT6 0b1110 Output 0b0001 OWA_OUT 0b0011 I2S2_MCLK 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PF5_SELECT PF5 Select [23:20] Input 0b0000 SDC0_D2 0b0010 R_JTAG_CK 0b0100 Reserved 0b0110 Reserved 0b1000 PF_EINT5 0b1110 Output 0b0001 JTAG_CK 0b0011 I2S2_LRCK 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PF4_SELECT PF4 Select [19:16] Input 0b0000 SDC0_D3 0b0010 TWI0_SDA 0b0100 IR_TX 0b0110 Reserved 0b1000 PF_EINT4 0b1110 Output 0b0001 UART0_RX 0b0011 PWM6 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PF3_SELECT PF3 Select [15:12] Input 0b0000 SDC0_CMD 0b0010 R_JTAG_DO 0b0100 Reserved 0b0110 Reserved 0b1000 PF_EINT3 0b1110 Output 0b0001 JTAG_DO 0b0011 I2S2_BCLK 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PF2_SELECT PF2 Select [11:8] Input 0b0000 SDC0_CLK 0b0010 TWI0_SCK 0b0100 OWA_IN 0b0110 Reserved 0b1000 PF_EINT2 0b1110 Output 0b0001 UART0_TX 0b0011 LEDC_DO 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PF1_SELECT PF1 Select [7:4] Input 0b0000 SDC0_D0 0b0010 R_JTAG_DI 0b0100 I2S2_DIN1 0b0110 Reserved 0b1000 PF_EINT1 0b1110 Output 0b0001 JTAG_DI 0b0011 I2S2_DOUT0 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PF0_SELECT PF0 Select [3:0] Input 0b0000 SDC0_D1 0b0010 R_JTAG_MS 0b0100 I2S2_DIN0 0b0110 Reserved 0b1000 PF_EINT0 0b1110 Output 0b0001 JTAG_MS 0b0011 I2S2_DOUT1 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 pf_dat PF Data Register 0x0100 PF_DAT PF Data [6:0] pf_drv0 PF Multi_Driving Register 0 0x0104 7 4 PF%s_DRV PF Multi_Driving Select [1:0] L0 0 L1 1 L2 2 L3 3 pf_pull0 PF Pull Register 0 0x0114 7 2 PF%s_PULL PF Pull_up/down Select [1:0] pull_disable 0 pull_up 1 pull_down 2 reserved 3 pg_cfg0 PG Configure Register 0 0x0120 PG7_SELECT PG7 Select [31:28] Input 0b0000 UART1_RX 0b0010 RGMII_TXD3 0b0100 Reserved 0b0110 Reserved 0b1000 PG_EINT7 0b1110 Output 0b0001 TWI2_SDA 0b0011 OWA_IN 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PG6_SELECT PG6 Select [27:24] Input 0b0000 UART1_TX 0b0010 RGMII_TXD2 0b0100 Reserved 0b0110 Reserved 0b1000 PG_EINT6 0b1110 Output 0b0001 TWI2_SCK 0b0011 PWM1 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PG5_SELECT PG5 Select [23:20] Input 0b0000 SDC1_D3 0b0010 RGMII_TXD1_RMII_TXD1 0b0100 Reserved 0b0110 Reserved 0b1000 PG_EINT5 0b1110 Output 0b0001 UART5_RX 0b0011 PWM4 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PG4_SELECT PG4 Select [19:16] Input 0b0000 SDC1_D2 0b0010 RGMII_TXD0_RMII_TXD0 0b0100 Reserved 0b0110 Reserved 0b1000 PG_EINT4 0b1110 Output 0b0001 UART5_TX 0b0011 PWM5 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PG3_SELECT PG3 Select [15:12] Input 0b0000 SDC1_D1 0b0010 RGMII_TXCK_RMII_TXCK 0b0100 Reserved 0b0110 Reserved 0b1000 PG_EINT3 0b1110 Output 0b0001 UART3_CTS 0b0011 UART4_RX 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PG2_SELECT PG2 Select [11:8] Input 0b0000 SDC1_D0 0b0010 RGMII_RXD1_RMII_RXD1 0b0100 Reserved 0b0110 Reserved 0b1000 PG_EINT2 0b1110 Output 0b0001 UART3_RTS 0b0011 UART4_TX 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PG1_SELECT PG1 Select [7:4] Input 0b0000 SDC1_CMD 0b0010 RGMII_RXD0_RMII_RXD0 0b0100 Reserved 0b0110 Reserved 0b1000 PG_EINT1 0b1110 Output 0b0001 UART3_RX 0b0011 PWM6 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PG0_SELECT PG0 Select [3:0] Input 0b0000 SDC1_CLK 0b0010 RGMII_RXCTRL_RMII_CRS_DV 0b0100 Reserved 0b0110 Reserved 0b1000 PG_EINT0 0b1110 Output 0b0001 UART3_TX 0b0011 PWM7 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 pg_cfg1 PG Configure Register 1 0x0124 PG15_SELECT PG15 Select [31:28] Input 0b0000 I2S1_DOUT0 0b0010 MDIO 0b0100 SPI0_HOLD 0b0110 Reserved 0b1000 PG_EINT15 0b1110 Output 0b0001 TWI2_SDA 0b0011 I2S1_DIN1 0b0101 UART1_CTS 0b0111 Reserved 0b1001 IO_Disable 0b1111 PG14_SELECT PG14 Select [27:24] Input 0b0000 I2S1_DIN0 0b0010 MDC 0b0100 SPI0_WP 0b0110 Reserved 0b1000 PG_EINT14 0b1110 Output 0b0001 TWI2_SCK 0b0011 I2S1_DOUT1 0b0101 UART1_RTS 0b0111 Reserved 0b1001 IO_Disable 0b1111 PG13_SELECT PG13 Select [23:20] Input 0b0000 I2S1_BCLK 0b0010 RGMII_CLKIN_RMII_RXER 0b0100 LEDC_DO 0b0110 Reserved 0b1000 PG_EINT13 0b1110 Output 0b0001 TWI0_SDA 0b0011 PWM2 0b0101 UART1_RX 0b0111 Reserved 0b1001 IO_Disable 0b1111 PG12_SELECT PG12 Select [19:16] Input 0b0000 Output 0b0001 I2S1_LRCK 0b0010 TWI0_SCK 0b0011 RGMII_TXCTRL_RMII_TXEN 0b0100 CLK_FANOUT2 0b0101 PWM0 0b0110 Reserved 0b1000 PG_EINT12 0b1110 UART1_TX 0b0111 Reserved 0b1001 IO_Disable 0b1111 PG11_SELECT PG11 Select [15:12] Input 0b0000 I2S1_MCLK 0b0010 EPHY_25M 0b0100 TCON_TRIG 0b0110 Reserved 0b1000 PG_EINT11 0b1110 Output 0b0001 TWI3_SDA 0b0011 CLK_FANOUT1 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PG10_SELECT PG10 Select [11:8] Input 0b0000 PWM3 0b0010 RGMII_RXCK 0b0100 IR_RX 0b0110 Reserved 0b1000 PG_EINT10 0b1110 Output 0b0001 TWI3_SCK 0b0011 CLK_FANOUT0 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PG9_SELECT PG9 Select [7:4] Input 0b0000 UART1_CTS 0b0010 RGMII_RXD3 0b0100 Reserved 0b0110 Reserved 0b1000 PG_EINT9 0b1110 Output 0b0001 TWI1_SDA 0b0011 UART3_RX 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 PG8_SELECT PG8 Select [3:0] Input 0b0000 UART1_RTS 0b0010 RGMII_RXD2 0b0100 Reserved 0b0110 Reserved 0b1000 PG_EINT8 0b1110 Output 0b0001 TWI1_SCK 0b0011 UART3_TX 0b0101 Reserved 0b0111 Reserved 0b1001 IO_Disable 0b1111 pg_cfg2 PG Configure Register 2 0x0128 PG18_SELECT PG18 Select [11:8] Input 0b0000 UART2_RX 0b0010 PWM6 0b0100 OWA_OUT 0b0110 Reserved 0b1000 PG_EINT18 0b1110 Output 0b0001 TWI3_SDA 0b0011 CLK_FANOUT1 0b0101 UART0_RX 0b0111 Reserved 0b1001 IO_Disable 0b1111 PG17_SELECT PG17 Select [7:4] Input 0b0000 UART2_TX 0b0010 PWM7 0b0100 IR_TX 0b0110 Reserved 0b1000 PG_EINT17 0b1110 Output 0b0001 TWI3_SCK 0b0011 CLK_FANOUT0 0b0101 UART0_TX 0b0111 Reserved 0b1001 IO_Disable 0b1111 PG16_SELECT PG16 Select [3:0] Input 0b0000 IR_RX 0b0010 PWM5 0b0100 OWA_IN 0b0110 Reserved 0b1000 PG_EINT16 0b1110 Output 0b0001 TCON_TRIG 0b0011 CLK_FANOUT2 0b0101 LEDC_DO 0b0111 Reserved 0b1001 IO_Disable 0b1111 pg_dat PG Data Register 0x0130 PG_DAT PG Data [18:0] pg_drv0 PG Multi_Driving Register 0 0x0134 8 4 PG%s_DRV PG Multi_Driving Select [1:0] L0 0 L1 1 L2 2 L3 3 pg_drv1 PG Multi_Driving Register 1 0x0138 8 4 8-15 PG%s_DRV PG Multi_Driving Select [1:0] L0 0 L1 1 L2 2 L3 3 pg_drv2 PG Multi_Driving Register 2 0x013C 3 4 16-18 PG%s_DRV PG Multi_Driving Select [1:0] L0 0 L1 1 L2 2 L3 3 pg_pull0 PG Pull Register 0 0x0144 16 2 PG%s_PULL PG Pull_up/down Select [1:0] pull_disable 0 pull_up 1 pull_down 2 reserved 3 pg_pull1 PG Pull Register 1 0x0148 3 2 16-18 PG%s_PULL PG Pull_up/down Select [1:0] pull_disable 0 pull_up 1 pull_down 2 reserved 3 pb_eint_cfg0 PB External Interrupt Configure Register 0 0x0220 8 4 EINT%s_CFG External INT Mode [3:0] positive_edge 0 negative_edge 1 high_level 2 low_level 3 double_edge 4 pb_eint_cfg1 PB External Interrupt Configure Register 1 0x0224 5 4 8-12 EINT%s_CFG External INT Mode [3:0] positive_edge 0 negative_edge 1 high_level 2 low_level 3 double_edge 4 pb_eint_ctl PB External Interrupt Control Register 0x0230 12 1 EINT%s_CTL External INT Enable [0:0] disable 0 enable 1 pb_eint_status PB External Interrupt Status Register 0x0234 12 1 EINT%s_STATUS External INT Pending Bit [0:0] no_pending 0 pending 1 pb_eint_deb PB External Interrupt Debounce Register 0x0238 DEB_CLK_PRE_SCALE Debounce Clock Pre_scale n [6:4] PIO_INT_CLK_SELECT PIO Interrupt Clock Select [0:0] LOSC_32KHz 0 HOSC_24MHz 1 pc_eint_cfg0 PC External Interrupt Configure Register 0 0x0240 8 4 EINT%s_CFG External INT Mode [3:0] positive_edge 0 negative_edge 1 high_level 2 low_level 3 double_edge 4 pc_eint_ctl PC External Interrupt Control Register 0x0250 8 1 EINT%s_CTL External INT Enable [0:0] disable 0 enable 1 pc_eint_status PC External Interrupt Status Register 0x0254 8 1 EINT%s_STATUS External INT Pending Bit [0:0] no_pending 0 pending 1 pc_eint_deb PC External Interrupt Debounce Register 0x0258 DEB_CLK_PRE_SCALE Debounce Clock Pre_scale n [6:4] PIO_INT_CLK_SELECT PIO Interrupt Clock Select [0:0] LOSC_32KHz 0 HOSC_24MHz 1 pd_eint_cfg0 PD External Interrupt Configure Register 0 0x0260 8 4 EINT%s_CFG External INT Mode [3:0] positive_edge 0 negative_edge 1 high_level 2 low_level 3 double_edge 4 pd_eint_cfg1 PD External Interrupt Configure Register 1 0x0264 8 4 8-15 EINT%s_CFG External INT Mode [3:0] positive_edge 0 negative_edge 1 high_level 2 low_level 3 double_edge 4 pd_eint_cfg2 PD External Interrupt Configure Register 2 0x0268 7 4 16-22 EINT%s_CFG External INT Mode [3:0] positive_edge 0 negative_edge 1 high_level 2 low_level 3 double_edge 4 pd_eint_ctl PD External Interrupt Control Register 0x0270 23 1 EINT%s_CTL External INT Enable [0:0] disable 0 enable 1 pd_eint_status PD External Interrupt Status Register 0x0274 23 1 EINT%s_STATUS External INT Pending Bit [0:0] no_pending 0 pending 1 pd_eint_deb PD External Interrupt Debounce Register 0x0278 DEB_CLK_PRE_SCALE Debounce Clock Pre_scale n [6:4] PIO_INT_CLK_SELECT PIO Interrupt Clock Select [0:0] LOSC_32KHz 0 HOSC_24MHz 1 pe_eint_cfg0 PE External Interrupt Configure Register 0 0x0280 8 4 EINT%s_CFG External INT Mode [3:0] positive_edge 0 negative_edge 1 high_level 2 low_level 3 double_edge 4 pe_eint_cfg1 PE External Interrupt Configure Register 1 0x0284 8 4 8-15 EINT%s_CFG External INT Mode [3:0] positive_edge 0 negative_edge 1 high_level 2 low_level 3 double_edge 4 pe_eint_cfg2 PE External Interrupt Configure Register 2 0x0288 2 4 16-17 EINT%s_CFG External INT Mode [3:0] positive_edge 0 negative_edge 1 high_level 2 low_level 3 double_edge 4 pe_eint_ctl PE External Interrupt Control Register 0x0290 18 1 EINT%s_CTL External INT Enable [0:0] disable 0 enable 1 pe_eint_status PE External Interrupt Status Register 0x0294 18 1 EINT%s_STATUS External INT Pending Bit [0:0] no_pending 0 pending 1 pe_eint_deb PE External Interrupt Debounce Register 0x0298 DEB_CLK_PRE_SCALE Debounce Clock Pre_scale n [6:4] PIO_INT_CLK_SELECT PIO Interrupt Clock Select [0:0] LOSC_32KHz 0 HOSC_24MHz 1 pf_eint_cfg0 PF External Interrupt Configure Register 0 0x02A0 7 4 EINT%s_CFG External INT Mode [3:0] positive_edge 0 negative_edge 1 high_level 2 low_level 3 double_edge 4 pf_eint_ctl PF External Interrupt Control Register 0x02B0 7 1 EINT%s_CTL External INT Enable [0:0] disable 0 enable 1 pf_eint_status PF External Interrupt Status Register 0x02B4 7 1 EINT%s_STATUS External INT Pending Bit [0:0] no_pending 0 pending 1 pf_eint_deb PF External Interrupt Debounce Register 0x02B8 DEB_CLK_PRE_SCALE Debounce Clock Pre_scale n [6:4] PIO_INT_CLK_SELECT PIO Interrupt Clock Select [0:0] LOSC_32KHz 0 HOSC_24MHz 1 pg_eint_cfg0 PG External Interrupt Configure Register 0 0x02C0 8 4 EINT%s_CFG External INT Mode [3:0] positive_edge 0 negative_edge 1 high_level 2 low_level 3 double_edge 4 pg_eint_cfg1 PG External Interrupt Configure Register 1 0x02C4 8 4 8-15 EINT%s_CFG External INT Mode [3:0] positive_edge 0 negative_edge 1 high_level 2 low_level 3 double_edge 4 pg_eint_cfg2 PG External Interrupt Configure Register 2 0x02C8 3 4 16-18 EINT%s_CFG External INT Mode [3:0] positive_edge 0 negative_edge 1 high_level 2 low_level 3 double_edge 4 pg_eint_ctl PG External Interrupt Control Register 0x02D0 19 1 EINT%s_CTL External INT Enable [0:0] disable 0 enable 1 pg_eint_status PG External Interrupt Status Register 0x02D4 18 1 EINT%s_STATUS External INT Pending Bit [0:0] no_pending 0 pending 1 pg_eint_deb PG External Interrupt Debounce Register 0x02D8 DEB_CLK_PRE_SCALE Debounce Clock Pre_scale n [6:4] PIO_INT_CLK_SELECT PIO Interrupt Clock Select [0:0] LOSC_32KHz 0 HOSC_24MHz 1 pio_pow_mod_sel PIO Group Withstand Voltage Mode Select Register 0x0340 VCC_IO_PWR_MOD_SEL VCC_IO POWER MODE Select [12:12] V33 3.3 V 0 V18 1.8 V 1 5 1 C,D,E,F,G P%s_PWR_MOD_SEL PX_POWER POWER MODE Select [2:2] V33 3.3 V 0 V18 1.8 V 1 pio_pow_ms_ctl PIO Group Withstand Voltage Mode Select Control Register 0x0344 VCCIO_WS_VOL_MOD_SEL VCC_IO Withstand Voltage Mode Select Control [12:12] enable 0 disable 1 5 1 C,D,E,F,G VCC_P%s_WS_VOL_MOD_SEL VCC_PX Withstand Voltage Mode Select Control [2:2] enable 0 disable 1 pio_pow_val PIO Group Power Value Register 0x0348 read-only VCCIO_PWS_VAL VCC_IO Power Value [12:12] 5 1 C,D,E,F,G P%s_PWR_VAL PX_Port Power Value [2:2] pio_pow_vol_sel_ctl PIO Group Power Voltage Select Control Register 0x0350 VCC_PF_PWR_VOL_SEL VCC_PF Power Voltage Select Control [0:0] V18 1.8V 0 V33 3.3V 1 GPADC General Purpose ADC Interfaces 0x02009000 0 0x400 registers GPADC 73 GP_SR_CON GPADC Sample Rate Configure Register 0x0000 GP_CTRL GPADC Control Register 0x0004 GP_CS_EN GPADC Compare and Select Enable Register 0x0008 GP_FIFO_INTC GPADC FIFO Interrupt Control Register 0x000C GP_FIFO_INTS GPADC FIFO Interrupt Status Register 0x0010 GP_FIFO_DATA GPADC FIFO Data Register 0x0014 GP_CDATA GPADC Calibration Data Register 0x0018 GP_DATAL_INTC GPADC Data Low Interrupt Configure Register 0x0020 GP_DATAH_INTC GPADC Data High Interrupt Configure Register 0x0024 GP_DATA_INTC GPADC Data Interrupt Configure Register 0x0028 GP_DATAL_INTS GPADC Data Low Interrupt Status Register 0x0030 GP_DATAH_INTS GPADC Data High Interrupt Status Register 0x0034 GP_DATA_INTS GPADC Data Interrupt Status Register 0x0038 GP_CH0_CMP_DATA GPADC CH0 Compare Data Register 0x0040 GP_CH1_CMP_DATA GPADC CH1 Compare Data Register 0x0044 GP_CH0_DATA GPADC CH0 Data Register 0x0080 GP_CH1_DATA GPADC CH1 Data Register 0x0084 TPADC Touch Panel ADC Interfaces 0x02009C00 0 0x400 registers TPADC 78 TP_CTRL0 TP Control Register 0 0x0000 TP_CTRL1 TP Control Register 1 0x0004 TP_CTRL2 TP Control Register 2 0x0008 TP_CTRL3 TP Control Register 3 0x000C TP_INT_FIFO_CTRL TP Interrupt FIFO Control Register 0x0010 TP_INT_FIFO_STAT TP Interrupt FIFO Status Register 0x0014 TP_CALI_DATA TP Calibration Data Register 0x001C TP_DATA TP Data Register 0x0024 LRADC Low Rate ADC Interfaces 0x02009800 0 0x400 registers LRADC 77 LRADC_CTRL LRADC Control Register 0x0000 LRADC_INTC LRADC Interrupt Control Register 0x0004 LRADC_INTS LRADC Interrupt Status Register 0x0008 LRADC_DATA LRADC Data Register 0x000C PWM Pulse Width Modulation Interfaces 0x02000C00 0 0x400 registers PWM 34 PIER PWM IRQ Enable Register 0x0000 PISR PWM IRQ Status Register 0x0004 CIER Capture IRQ Enable Register 0x0010 CISR Capture IRQ Status Register 0x0014 PCCR01 PWM01 Clock Configuration Register 0x0020 PCCR23 PWM23 Clock Configuration Register 0x0024 PCCR45 PWM45 Clock Configuration Register 0x0028 PCCR67 PWM67 Clock Configuration Register 0x002C PCGR PWM Clock Gating Register 0x0040 PDZCR01 PWM01 Dead Zone Control Register 0x0060 PDZCR23 PWM23 Dead Zone Control Register 0x0064 PDZCR45 PWM45 Dead Zone Control Register 0x0068 PDZCR67 PWM67 Dead Zone Control Register 0x006C PER PWM Enable Register 0x0080 PGR0 PWM Group0 Register 0x0090 PGR1 PWM Group1 Register 0x0094 PGR2 PWM Group2 Register 0x0098 PGR3 PWM Group3 Register 0x009C CER Capture Enable Register 0x00C0 8 0x0020 pcr%s PWM Control Register 0x0100 8 0x0020 ppr%s PWM Period Register 0x0104 8 0x0020 pcntr%s PWM Count Register 0x0108 8 0x0020 ppcntr%s PWM Pulse Count Register 0x010c 8 0x0020 ccr%s Capture Control Register 0x0110 8 0x0020 crlr%s Capture Rise Lock Register 0x0114 8 0x0020 cflr%s Capture Fall Lock Register 0x0118 LEDC LEDC Interfaces 0x02008000 0 0x400 registers LEDC 36 LEDC_CTRL LEDC Control Register 0x0000 TOTAL_DATA_LENGTH [28:16] RESET_LED_EN [10:10] LED_RGB_MODE [8:6] GRB 0b000 GBR 0b001 RGB 0b010 RBG 0b011 BGR 0b100 BRG 0b101 4 1 B,R,G,TOP LED_MSB_%s [2:2] LSB 0 MSB 1 LEDC_SOFT_RESET [1:1] LEDC_EN [0:0] Disable 0 Enable 1 LED_T01_TIMING_CTRL LEDC T0 T1 Timing Control Register 0x0004 T1H_TIME [26:21] 0 0x3f T1L_TIME [20:16] 0 0x1f T0H_TIME [10:6] 0 0x1f T0L_TIME [5:0] 0 0x1f LEDC_DATA_FINISH_CNT LEDC Data Finish Counter Register 0x0008 LED_WAIT_DATA_TIME [29:16] 0 0x1FFF LED_DATA_FINISH_CNT [12:0] read-only LED_RESET_TIMING_CTRL LEDC Reset Timing Control Register 0x000C TR_TIME [28:16] 1 0x1FFF LED_NUM [9:0] LEDC_WAIT_TIME0_CTRL LEDC Wait Time0 Control Register 0x0010 WAIT_TIM0_EN [8:8] Disable 0 Enable 1 TOTAL_WAIT_TIME0 [7:0] 1 0xFF LEDC_DATA LEDC Data Register 0x0014 write-only LEDC_DMA_CTRL LEDC DMA Control Register 0x0018 LEDC_DMA_EN [5:5] Disable 0 Enable 1 LEDC_FIFO_TRIG_LEVEL [4:0] LEDC_INT_CTRL LEDC Interrupt Control Register 0x001C GLOBAL_INT_EN [5:5] Disable 0 Enable 1 FIFO_OVERFLOW_INT_EN [4:4] Disable 0 Enable 1 WAITDATA_TIMEOUT_INT_EN [3:3] Disable 0 Enable 1 FIFO_CPUREQ_INT_EN [1:1] Disable 0 Enable 1 LED_TRANS_FINISH_INT_EN [0:0] Disable 0 Enable 1 LEDC_INT_STS LEDC Interrupt Status Register 0x0020 FIFO_EMPTY [17:17] read-only FIFO_FULL [16:16] read-only FIFO_WLW [15:10] read-only FIFO_OVERFLOW_INT [4:4] oneToClear not_overflow 0 overflow 1 WAITDATA_TIMEOUT_INT [3:3] oneToClear not_timeout 0 timeout 1 FIFO_CPUREQ_INT [1:1] oneToClear not_request 0 request 1 LEC_TRANS_FINISH_INT [0:0] oneToClear not_trans_complete 0 trans_complete 1 LEDC_WAIT_TIME1_CTRL LEDC Wait Time1 Control Register 0x0028 WAIT_TIM1_EN [31:31] Disable 0 Enable 1 TOTAL_WAIT_TIME1 [30:0] 0x80 0x7FFFFFFF 32 0x04 LEDC_FIFO_DATA%s LEDC FIFO Data Register 0x0030 read-only EMAC Ethernet Medium Access Controller Interfaces 0x04500000 0 0x10000 registers EMAC 62 EMAC_BASIC_CTL0 EMAC Basic Control Register0 0x0000 SPEED EMAC Working Speed [3:2] S1000 0b00 Reserved 0b01 S10 0b10 S100 0b11 LOOPBACK EMAC Loopback Mode For Test [1:1] Disable 0 Enable 1 DUPLEX EMAC Transfer Mode [0:0] Half_Duplex 0 Full_Duplex 1 EMAC_BASIC_CTL1 EMAC Basic Control Register1 0x0004 BURST_LEN The burst length of RX and TX DMA transfer [29:24] RX_TX_PRI RX TX DMA Priority [1:1] Same 0 RoT 1 SOFT_RST Soft Reset all Registers and Logic [0:0] no_valid 0 reset 1 EMAC_INT_STA EMAC Interrupt Status Register 0x0008 oneToClear RGMII_LINK_STA_P RMII Link Status Changed Interrupt Pending [16:16] No_Pending 0 Pending 1 RX_EARLY_P RX DMA Filled First Data Buffer of the Receive Frame Interrupt Pending [13:13] no_pending 0 pending 1 RX_OVERFLOW_P RX FIFO Overflow Error Interrupt Pending [12:12] no_pending 0 pending 1 RX_TIMEOUT_P RX Timeout Interrupt Pending [11:11] no_pending 0 pending 1 RX_DMA_STOPPED_P When this bit asserted, the RX DMA FSM is stopped. [10:10] RX_BUF_UA_P RX Buffer UA Interrupt Pending [9:9] no_pending 0 pending 1 RX_P Frame RX Completed Interrupt Pending [8:8] no_pending 0 pending 1 TX_EARLY_P Total interrupt pending which the frame is transmitted to FIFO [5:5] no_pending 0 pending 1 TX_UNDERFLOW_P TX FIFO Underflow Interrupt Pending [4:4] no_pending 0 pending 1 TX_TIMEOUT_P Transmitter Timeout Interrupt Pending [3:3] no_pending 0 pending 1 TX_BUF_UA_P TX Buffer UA Interrupt Pending [2:2] no_pending 0 pending 1 TX_DMA_STOPPED_P Transmission DMA Stopped Interrupt Pending [1:1] no_pending 0 pending 1 TX_P Frame Transmission Interrupt Pending [0:0] no_pending 0 pending 1 EMAC_INT_EN EMAC Interrupt Enable Register 0x000C RX_EARLY_INT_EN Early Receive Interrupt [13:13] Disable 0 Enable 1 RX_OVERFLOW_INT_EN Receive Overflow Interrupt [12:12] Disable 0 Enable 1 RX_TIMEOUT_INT_EN Receive Timeout Interrupt [11:11] Disable 0 Enable 1 RX_DMA_STOPPED_INT_EN Receive DMA FSM Stopped Interrupt [10:10] Disable 0 Enable 1 RX_BUF_UA_INT_EN Receive Buffer Unavailable Interrupt [9:9] Disable 0 Enable 1 RX_INT_EN Receive Interrupt [8:8] Disable 0 Enable 1 TX_EARLY_INT_EN Early Transmit Interrupt [5:5] Disable 0 Enable 1 TX_UNDERFLOW_INT_EN Transmit Underflow Interrupt [4:4] Disable 0 Enable 1 TX_TIMEOUT_INT_EN Transmit Timeout Interrupt [3:3] Disable 0 Enable 1 TX_BUF_UA_INT_EN Transmit Buffer Available Interrupt [2:2] Disable 0 Enable 1 TX_DMA_STOPPED_INT_EN Transmit DMA FSM Stopped Interrupt [1:1] Disable 0 Enable 1 TX_INT_EN Transmit Interrupt [0:0] Disable 0 Enable 1 EMAC_TX_CTL0 EMAC Transmit Control Register0 0x0010 TX_EN Enable Transmitter [31:31] Disable 0 Enable 1 TX_FRM_LEN_CTL Frame Transmit Length Control [30:30] B2048 0 B16384 1 EMAC_TX_CTL1 EMAC Transmit Control Register1 0x0014 TX_DMA_START Transmit DMA FSM Start [31:31] no_valid 0 start 1 TX_DMA_EN Transmit DMA Enable [30:30] stop 0 start 1 TX_TH Threshold value of TX DMA FIFO [10:8] T64 0b000 T128 0b001 T192 0b010 T256 0b011 TX_MD Transmission Mode [1:1] greater_than_th 0 locate_full_frame 1 FLUSH_TX_FIFO Flush the data in the TX FIFO [0:0] enable 0 disable 1 EMAC_TX_FLOW_CTL EMAC Transmit Flow Control Register 0x001C TX_FLOW_CTL_STA [31:31] TX_PAUSE_FRM_SLOT [21:20] PAUSE_TIME [19:4] ZQP_FRM_EN [1:1] disable 0 enable 1 TX_FLOW_CTL_EN TX Flow Control Enable [0:0] disable 0 enable 1 EMAC_TX_DMA_DESC_LIST EMAC Transmit Descriptor List Address Register 0x0020 EMAC_RX_CTL0 EMAC Receive Control Register0 0x0024 RX_EN Enable Receiver [31:31] disable 0 enable 1 RX_FRM_LEN_CTL Frame Receive Length Control [30:30] B2048 0 B16384 1 JUMBO_FRM_EN Jumbo Frame Enable [29:29] disable 0 enable 1 STRIP_FCS [28:28] CHECK_CRC Check CRC Enable [27:27] disable 0 check 1 RX_PAUSE_FRM_MD [17:17] only_multicast 0 also_unicast_mac0 1 RX_FLOW_CTL_EN [16:16] EMAC_RX_CTL1 EMAC Receive Control Register1 0x0028 RX_DMA_START [31:31] RX_EMA_EN Receive DMA Enable [30:30] stop 0 start 1 RX_FIFO_FLOW_CTL Receive FIFO Flow Control Enable [24:24] disable 0 enable 1 RX_FLOW_CTL_TH_DEACT Threshold for Deactivating Flow Control [23:22] FM1K 0b00 FM2K 0b01 FM3K 0b10 FM4K 0b11 RX_FLOW_CTL_TH_ACT Threshold for Activating Flow Control [21:20] FM1K 0b00 FM2K 0b01 FM3K 0b10 FM4K 0b11 RX_TH Threshold for RX DMA FIFO Start [5:4] T64 0b00 T32 0b01 T96 0b10 T128 0b11 RX_ERR_FRM [3:3] drop 0 forward 1 RX_RUNT_FRM [2:2] RX_MD Receive Mode [1:1] greater_than_th 0 locate_full_frame 1 FLUSH_RX_FRM Flush Receive Frames [0:0] enable 0 disable 1 EMAC_RX_DMA_DESC_LIST EMAC Receive Descriptor List Address Register 0x0034 EMAC_RX_FRM_FLT EMAC Receive Frame Filter Register 0x0038 DIS_ADDR_FILTER Disable Address Filter [31:31] Enable 0 Disable 1 DIS_BROADCAST Disable Receive Broadcast Frames [17:17] Receive 0 Drop 1 RX_ALL_MULTICAST Receive All Multicast Frames Filter [16:16] Filter 0 Receive_all 1 CTL_FRM_FILTER Receive Control Frames Filter [13:12] Drop_all 0b0x Receive_all 0b10 Receive_all_when_filter 0b11 HASH_MULTICAST Filter Multicast Frames Set [9:9] DA_field 0 hash_table 1 HASH_UNICAST Filter Unicast Frames Set [8:8] DA_field 0 hash_table 1 SA_FILTER_EN Receive SA Filter Enable [6:6] receive_update 0 update_drop_unmatched 1 SA_INV_FILTER Receive SA Invert Filter Set [5:5] matched 0 unmatched 1 DA_INV_FILTER [4:4] normal 0 inverse_cmp_da 1 FLT_MD [1:1] passed_when_matched 0 receive_when_passed 1 RX_ALL Receive All Frame [0:0] receive_when_passed 0 receive_all_update 1 EMAC_RX_HASH0 EMAC Hash Table Register0 0x0040 EMAC_RX_HASH1 EMAC Hash Table Register1 0x0044 EMAC_MII_CMD EMAC Management Interface Command Register 0x0048 MDC_DIV_RATIO_M MDC Clock DIvider Ratio [22:20] R16 0b000 R32 0b001 R64 0b010 R128 0b011 PHY_ADDR PHY Address [16:12] PHY_REG_ADDR PHY Register Address [8:4] MII_WR MII Write and Read [1:1] R 0 W 1 MII_BUSY MII Status [0:0] EMAC_MII_DATA EMAC Management Interface Data Register 0x004C MII_DATA [15:0] EMAC_ADDR_HIGH0 EMAC MAC Address High Register 0x0050 MAC_ADDR_HIGH0 [15:0] 7 0x08 1-7 EMAC_ADDR_HIGH%s EMAC MAC Address High Register 0x0058 MAC_ADDR_CTL MAC Address Valid [31:31] invalid 0 valid 1 MAC_ADDR_TYPE MAC Address Type [30:30] dst 0 src 1 MAC_ADDR_BYTE_CTL MAC Address Byte Control Mask [29:24] MAC_ADDR_HIGH [15:0] 8 0x08 EMAC_ADDR_LOW%s EMAC MAC Address Low Register 0x0054 EMAC_TX_DMA_STA EMAC Transmit DMA Status Register 0x00B0 read-only TX_DMA_STA The State of Transmit DMA FSM [2:0] stop 0b000 run_fetch_desc 0b001 run_wait_sta 0b010 run_trans_data 0b011 suspend 0b110 run_close_desc 0b111 EMAC_TX_CUR_DESC EMAC Current Transmit Descriptor Register 0x00B4 read-only EMAC_TX_CUR_BUF EMAC Current Transmit Buffer Address Register 0x00B8 read-only EMAC_RX_DMA_STA EMAC Receive DMA Status Register 0x00C0 read-only RX_DMA_STA The State of RX DMA FSM [2:0] stop 0b000 run_fetch_desc 0b001 run_wait_frm 0b011 suspend 0b100 run_close_desc 0b101 run_trans_data 0b111 EMAC_RX_CUR_DESC EMAC Current Receive Descriptor Register 0x00C4 read-only EMAC_RX_CUR_BUF EMAC Current Receive Buffer Address Register 0x00C8 read-only EMAC_RGMII_STA EMAC RGMII Status Register 0x00D0 RGMII_LINK The link status of the RGMII interface [3:3] down 0 up 1 RGMII_LINK_SPD The link speed of the RGMII interface [2:1] S2_5 0b00 S25 0b01 S125 0b10 RGMII_LINK_MD The link mode of the RGMII interface [0:0] half_duplex 0 full_duplex 1 CIR_RX Counsumer Infrared Receiver Interfaces 0x07040000 0 0x400 registers IR_RX 167 CIR_CTL CIR Control Register 0x0000 CIR_RXPCFG CIR Receiver Pulse Configure Register 0x0010 CIR_RXFIFO CIR Receiver FIFO Register 0x0020 CIR_RXINT CIR Receiver Interrupt Control Register 0x002C CIR_RXSTA CIR Receiver Status Register 0x0030 CIR_RXCFG CIR Receiver Configure Register 0x0034 CIR_TX Counsumer Infrared Transmitter Interfaces 0x02003000 0 0x400 registers IR_TX 35 CIR_TGLR CIR Transmit Global Register 0x0000 CIR_TMCR CIR Transmit Modulation Control Register 0x0004 CIR_TCR CIR Transmit Control Register 0x0008 CIR_IDC_H CIR Transmit Idle Duration Threshold High Bit Register 0x000C CIR_IDC_L CIR Transmit Idle Duration Threshold Low Bit Register 0x0010 CIR_TICR_H CIR Transmit Idle Counter High Bit Register 0x0014 CIR_TICR_L CIR Transmit Idle Counter Low Bit Register 0x0018 CIR_TEL CIR TX FIFO Empty Level Register 0x0020 CIR_TXINT CIR Transmit Interrupt Control Register 0x0024 CIR_TAC CIR Transmit FIFO Available Counter Register 0x0028 CIR_TXSTA CIR Transmit Status Register 0x002C CIR_TXT CIR Transmit Threshold Register 0x0030 CIR_DMA CIR DMA Control Register 0x0034 CIR_TXFIFO CIR Transmit FIFO Data Register 0x0080 CE_NS Crypoto Engine SecuritySystem 0x03040000 0 0x800 registers CE_NS 68 CE_TDA Task Descriptor Address 0x0000 CE_ICR Interrupt Control Register 0x0008 CE_ISR Interrupt Status Register 0x000C CE_TLR Task Load Register 0x0010 CE_TSR Task Status Register 0x0014 CE_ESR Error Status Register 0x0018 CE_CSA DMA Current Source Address 0x0024 CE_CDA DMA Current Destination Address 0x0028 CE_TPR Throughput Register 0x002C