Atmel AT91SAM9M10 SAM9M 20130207 Atmel AT91SAM9M10 device: ARM926EJ Embedded Microprocessor Unit, 400MHz, DDR2/LPDDR, Video Decoder, LCD, HS USB, 10/100 Ethernet, Dual EBI, 324 Pins (refer to http://www.atmel.com/devices/SAM9M10.aspx for more) 8 32 LCDC 6385D LCD Controller 0x00500000 0 0x100000 registers LCDC 23 DMABADDR1 DMA Base Address Register 1 0x00000000 32 read-write 0x00000000 BADDR_U 2 30 read-write DMABADDR2 DMA Base Address Register 2 0x00000004 32 read-write 0x00000000 BADDR_L 0 32 read-write DMAFRMPT1 DMA Frame Pointer Register 1 0x00000008 32 read-only 0x00000000 FRMPT_U 0 23 read-only DMAFRMPT2 DMA Frame Pointer Register 2 0x0000000C 32 read-only 0x00000000 FRMPT_L 0 23 read-only DMAFRMADD1 DMA Frame Address Register 1 0x00000010 32 read-only 0x00000000 FRMADD_U 0 32 read-only DMAFRMADD2 DMA Frame Address Register 2 0x00000014 32 read-only 0x00000000 FRMADD_L 0 32 read-only DMAFRMCFG DMA Frame Configuration Register 0x00000018 32 read-write 0x00000000 FRMSIZE Frame Size 0 23 read-write BRSTLN Burst Length in Words 24 7 read-write DMACON DMA Control Register 0x0000001C 32 read-write 0x00000000 DMAEN DMA Enable 0 1 read-write DMARST DMA Reset (Write-only) 1 1 read-write DMABUSY DMA Busy 2 1 read-write DMAUPDT DMA Configuration Update 3 1 read-write DMA2DEN DMA 2D Addressing Enable 4 1 read-write DMA2DCFG DMA Control Register 0x00000020 32 read-write 0x00000000 ADDRINC DMA 2D Addressing Address increment 0 16 read-write PIXELOFF DAM2D Addressing Pixel offset 24 5 read-write LCDCON1 LCD Control Register 1 0x00000800 32 read-write 0x00002000 BYPASS Bypass LCDDOTCK Divider 0 1 read-write CLKVAL Clock Divider 12 9 read-write LINECNT Line Counter (Read-only) 21 11 read-write LCDCON2 LCD Control Register 2 0x00000804 32 read-write 0x00000000 DISTYPE Display Type 0 2 read-write SCANMOD Scan Mode 2 1 read-write IFWIDTH Interface width (STN) 3 2 read-write PIXELSIZE Bits per pixel 5 3 read-write INVVD LCDD polarity 8 1 read-write INVFRAME LCDVSYNC polarity 9 1 read-write INVLINE LCDHSYNC polarity 10 1 read-write INVCLK LCDDOTCK polarity 11 1 read-write INVDVAL LCDDEN polarity 12 1 read-write CLKMOD LCDDOTCK mode 15 1 read-write MEMOR Memory Ordering Format 30 2 read-write LCDTIM1 LCD Timing Register 1 0x00000808 32 read-write 0x00000000 VFP Vertical Front Porch 0 8 read-write VBP Vertical Back Porch 8 8 read-write VPW Vertical Synchronization pulse width 16 6 read-write VHDLY Vertical to horizontal delay 24 4 read-write STUCKTO1 31 1 read-write LCDTIM2 LCD Timing Register 2 0x0000080C 32 read-write 0x00000000 HBP Horizontal Back Porch 0 8 read-write HPW Horizontal synchronization pulse width 8 6 read-write HFP Horizontal Front Porch 21 11 read-write LCDFRMCFG LCD Frame Configuration Register 0x00000810 32 read-write 0x00000000 LINEVAL Vertical size of LCD module 0 11 read-write LINESIZE Horizontal size of LCD module, in pixels, minus 1 21 11 read-write LCDFIFO LCD FIFO Register 0x00000814 32 read-write 0x00000000 FIFOTH FIFO Threshold 0 16 read-write DP1_2 Dithering Pattern DP1_2 0x0000081C 32 read-write 0x000000A5 DP1_2 Pattern value for half duty cycle 0 8 read-write DP4_7 Dithering Pattern DP4_7 0x00000820 32 read-write 0x05AF0FA5 DP4_7 Pattern value for 4/7 duty cycle 0 28 read-write DP3_5 Dithering Pattern DP3_5 0x00000824 32 read-write 0x000A5A5F DP3_5 Pattern value for 3/5 duty cycle 0 20 read-write DP2_3 Dithering Pattern DP2_3 0x00000828 32 read-write 0x00000A5F DP2_3 Pattern value for 2/3 duty cycle 0 12 read-write DP5_7 Dithering Pattern DP5_7 0x0000082C 32 read-write 0x0FAF5FA5 DP5_7 Pattern value for 5/7 duty cycle 0 28 read-write DP3_4 Dithering Pattern DP3_4 0x00000830 32 read-write 0x0000FAF5 DP3_4 Pattern value for 3/4 duty cycle 0 16 read-write DP4_5 Dithering Pattern DP4_5 0x00000834 32 read-write 0x000FAF5F DP4_5 Pattern value for 4/5 duty cycle 0 20 read-write DP6_7 Dithering Pattern DP6_7 0x00000838 32 read-write 0x0F5FFAFF DP6_7 Pattern value for 6/7 duty cycle 0 28 read-write PWRCON Power Control Register 0x0000083C 32 read-write 0x0000000E LCD_PWR LCD module power control 0 1 read-write GUARD_TIME 1 7 read-write LCD_BUSY 31 1 read-write CONTRAST_CTR Contrast Control Register 0x00000840 32 read-write 0x00000000 PS 0 2 read-write POL 2 1 read-write ENA 3 1 read-write CONTRAST_VAL Contrast Value Register 0x00000844 32 read-write 0x00000000 LCD_IER LCD Interrupt Enable Register 0x00000848 32 write-only 0x00000000 LNIE Line interrupt enable 0 1 write-only LSTLNIE Last line interrupt enable 1 1 write-only EOFIE DMA End of frame interrupt enable 2 1 write-only UFLWIE FIFO underflow interrupt enable 4 1 write-only OWRIE FIFO overwrite interrupt enable 5 1 write-only MERIE DMA memory error interrupt enable 6 1 write-only LCD_IDR LCD Interrupt Disable Register 0x0000084C 32 write-only 0x00000000 LNID Line interrupt disable 0 1 write-only LSTLNID Last line interrupt disable 1 1 write-only EOFID DMA End of frame interrupt disable 2 1 write-only UFLWID FIFO underflow interrupt disable 4 1 write-only OWRID FIFO overwrite interrupt disable 5 1 write-only MERID DMA Memory error interrupt disable 6 1 write-only LCD_IMR LCD Interrupt Mask Register 0x00000850 32 read-only 0x00000000 LNIM Line interrupt mask 0 1 read-only LSTLNIM Last line interrupt mask 1 1 read-only EOFIM DMA End of frame interrupt mask 2 1 read-only UFLWIM FIFO underflow interrupt mask 4 1 read-only OWRIM FIFO overwrite interrupt mask 5 1 read-only MERIM DMA Memory error interrupt mask 6 1 read-only LCD_ISR LCD Interrupt Status Register 0x00000854 32 read-only 0x00000000 LNIS Line interrupt status 0 1 read-only LSTLNIS Last line interrupt status 1 1 read-only EOFIS DMA End of frame interrupt status 2 1 read-only UFLWIS FIFO underflow interrupt status 4 1 read-only OWRIS FIFO overwrite interrupt status 5 1 read-only MERIS DMA Memory error interrupt status 6 1 read-only LCD_ICR LCD Interrupt Clear Register 0x00000858 32 write-only 0x00000000 LNIC Line interrupt clear 0 1 write-only LSTLNIC Last line interrupt clear 1 1 write-only EOFIC DMA End of frame interrupt clear 2 1 write-only UFLWIC FIFO underflow interrupt clear 4 1 write-only OWRIC FIFO overwrite interrupt clear 5 1 write-only MERIC DMA Memory error interrupt clear 6 1 write-only LCD_ITR LCD Interrupt Test Register 0x00000860 32 write-only 0x00000000 LNIT Line interrupt test 0 1 write-only LSTLNIT Last line interrupt test 1 1 write-only EOFIT DMA End of frame interrupt test 2 1 write-only UFLWIT FIFO underflow interrupt test 4 1 write-only OWRIT FIFO overwrite interrupt test 5 1 write-only MERIT DMA Memory error interrupt test 6 1 write-only LCD_IRR LCD Interrupt Raw Status Register 0x00000864 32 read-only 0x00000000 LNIR Line interrupt raw status 0 1 read-only LSTLNIR Last line interrupt raw status 1 1 read-only EOFIR DMA End of frame interrupt raw status 2 1 read-only UFLWIR FIFO underflow interrupt raw status 4 1 read-only OWRIR FIFO overwrite interrupt raw status 5 1 read-only MERIR DMA Memory error interrupt raw status 6 1 read-only LCD_WPCR Write Protection Control Register 0x000008E4 32 read-write 0x00000000 LCD_WPSR Write Protection Status Register 0x000008E8 32 read-only 0x00000000 WPVS Write Protect Enable 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only 256 4 0-255 LUTENTRY[%s] Palette entry 0x00000C00 32 read-write VDEC 6377C Video Decoder VDEC_ 0x00900000 0 0x100000 registers VDEC 30 IDR ID Register 0x00000000 32 read-only 0x81701000 BUILD_VER Build Version 0 4 read-only MINOR_VER Minor Version 4 8 read-only MAJOR_VER Major Version 12 4 read-only PROD_ID Product ID 16 16 read-only DIR Decoder Interrupt Register 0x00000004 32 read-write 0x00000000 DE Decoder Enable 0 1 read-write ID Interrupt Disable 4 1 read-write ISET Decoder Interrupt Set 8 1 read-write DR Decoder Ready 12 1 read-write BE Bus Error 13 1 read-write SBE Stream Buffer Empty 14 1 read-write ASOD ASO Detected 15 1 read-write ISE Input Stream Error 16 1 read-write JPEGSD JPEG Slice Decoded 17 1 read-write TO Timeout 18 1 read-write DDCR Decoder Device Configuration Register 0x00000008 32 read-write 0x00000400 MAX_BURST_LEN Maximum Burst Length for Decoder Bus Transactions 0 5 read-write PRIOR Decoder Core Internal Bus Service Priority 5 3 read-write DO_LE Decoder Output Endian Mode 8 1 read-write INTCE_LE Interface Endian Mode 9 1 read-write DDCGE Decoder Dynamic Clock Gating Enable 10 1 read-write LAT_COMP Decoder Latency Compensation 11 6 read-write DOPF Decoder Output Picture Format 17 1 read-write AHB_BURST AHB Precise Burst and Data Discard Enable 18 1 read-write DI_LE Decoder Input Endian Mode 21 1 read-write HTI Hardware Timeout Interrupt Enable 23 1 read-write CTLR0 Decoder Control Register 0 0x0000000C 32 read-write 0x00000000 HLOCK HLOCK Enable 8 1 read-write REFFIRST Reference Field First 11 1 read-write MV MPEG-2 Motion Vector Write Enable 12 1 read-write QUANT Quantization 13 1 read-write FILTDIS De-block Filtering Disable 14 1 read-write OUTDIS Disable Decoder Output Picture Writing 15 1 read-write REFFIELD Indicates Which Field Should Be Used As Reference 16 1 read-write FORWMODE Coding Mode of Forward Reference Picture 18 1 read-write PICFIELD Picture Field 19 1 read-write PICTYPE Picture Type 20 1 read-write PICBEN B Picture Enable 21 1 read-write PICSTRUCT Structure of the Current Picture 22 1 read-write PICMODE Coding mode of Current Picture 23 1 read-write RLCEN RLC Mode Enable 27 1 read-write DEC_MODE Decoding Mode 28 4 read-write CTLR1 Decoder Control Register 1 0x00000010 32 read-write 0x00000000 REF_FRAMES Number of Reference Frames/Semantics 0 5 read-write TOPF Top Field 5 1 read-write AVSM Alternative Vertical Scan Method 6 1 read-write HEIGHT_OFF Height Offset 7 4 read-write PIC_HEIGHT Picture Height 11 8 read-write WIDTH_OFF Width Offset 19 4 read-write PIC_WIDTH Picture Width 23 9 read-write CTLR2 Decoder Control Register 2 0x00000014 32 read-write 0x00000000 FIELDPIC Flag for Stream 0 1 read-write QP_FILT_CR_OFF 14 5 read-write QP_FILT_CB_OFF 19 5 read-write STREAM_START_BIT Stream Start Bit 26 6 read-write CTLR3 Decoder Control Register 3 0x00000018 32 read-write 0x00000000 STREAM_LEN Stream Length 0 24 read-write INIT_QP Quantization Initialization 25 6 read-write ST_COD_EN Stream Start Code 31 1 read-write CTLR4 Decoder Control Register 4 0x0000001C 32 read-write 0x00000000 FRAME_NUM Frame Number 0 16 read-write FRAME_NUM_LEN Frame Number length 16 5 read-write W_BIPR Weight Prediction for B Slices 26 2 read-write W_PRED Weight Prediction 28 1 read-write DIRMV_PRED Derive Luma Method 29 1 read-write BW Black and White Enable 30 1 read-write CABAC H.264 CABAC Enable 31 1 read-write CTLR5 Decoder Control Register 5 0x00000020 32 read-write 0x00000000 IDR_PIC_ID IDR Picture 0 16 read-write IDREN IDR Picture Enable 16 1 read-write REF_PIC_LEN Reference Picture Length 17 11 read-write EIGHT58 28 1 read-write RD_PIC Redundant Picture Present 29 1 read-write FILT_CTRL Extra Variables Controlling Characteristics of The Deblocking Filter 30 1 read-write CONS_INTRA Intra in Prediction 31 1 read-write CTLR6 Decoder Control Register 6 0x00000024 32 read-write 0x00000000 POC_LEN Picture Order length 0 8 read-write REF_IDX0 Maximum Reference Index 0 14 5 read-write REF_IDX1 Maximum Reference Index 1 19 5 read-write PPS_ID Picture Parameter 24 8 read-write DMVBA Base Address for Differential Motion Vector 0x00000028 32 read-write 0x00000000 MV_CONTROL_BASE Differential Motion Vector Base Address 2 30 read-write CTLR7 Decoder Control Register 7 0x0000002C 32 read-write 0x00000000 BA Base Address 2 30 read-write RLCVLCBA RLC/VLC Data Base Address 0x00000030 32 read-write 0x00000000 BA Base Address 2 30 read-write PICTBA Decoded Picture Base Address 0x00000034 32 read-write 0x00000000 BA Base Address 2 30 read-write 16 4 0-15 PIDXBA[%s] Reference Picture Index 0 Base Address 0x00000038 32 read-write BA Base Address 2 30 read-write PNR0 Reference Picture Numbers Register 0 0x00000078 32 read-write 0x00000000 REFER0 Reference Picture Number for Index 0 0 16 read-write REFER1 Reference Picture Number for Index 1 16 16 read-write PNR1 Reference Picture Numbers Register 1 0x0000007C 32 read-write 0x00000000 REFER2 Reference Picture Number for Index 2 0 16 read-write REFER3 Reference Picture Number for Index 3 16 16 read-write PNR2 Reference Picture Numbers Register 2 0x00000080 32 read-write 0x00000000 PNR3 Reference Picture Numbers Register 3 0x00000084 32 read-write 0x00000000 REFER4 Reference Picture Number for Index 4 0 16 read-write REFER5 Reference Picture Number for Index 5 16 16 read-write PNR4 Reference Picture Numbers Register 4 0x00000088 32 read-write 0x00000000 REFER8 Reference Picture Number for Index 8 0 16 read-write REFER9 Reference Picture Number for Index 9 16 16 read-write PNR5 Reference Picture Numbers Register 5 0x0000008C 32 read-write 0x00000000 REFER10 Reference Picture Number for Index 10 0 16 read-write REFER11 Reference Picture Number for Index 11 16 16 read-write PNR6 Reference Picture Numbers Register 6 0x00000090 32 read-write 0x00000000 REFER12 Reference Picture Number for Index 12 0 16 read-write REFER13 Reference Picture Number for Index 13 16 16 read-write PNR7 Reference Picture Numbers Register 7 0x00000094 32 read-write 0x00000000 REFER14 Reference Picture Number for Index 14 0 16 read-write REFER15 Reference Picture Number for Index 15 16 16 read-write PLTFR Reference Picture Long Term Flag Register 0x00000098 32 read-write 0x00000000 LTF Long Term Flag 0 32 read-write PVFR Reference Picture Valid Flag Register 0x0000009C 32 read-write 0x00000000 SDTBA Standard Dependent Tables Base Address 0x000000A0 32 read-write 0x00000000 BA Base Address 2 30 read-write DMMVBA Direct Mode Motion Vector Base Address 0x000000A4 32 read-write 0x00000000 BA Base Address 2 30 read-write IRPLR0 H264 Initial Reference Picture List Register 0 0x000000A8 32 read-write 0x00000000 IREFL_FW0 Initial Reference Picture List for Forward Picid 0 0 5 read-write IREFL_BW0 Initial Reference Picture List for Backward Picid 0 5 5 read-write IREFL_FW1 Initial Reference Picture List for Forward Picid 1 10 5 read-write IREFL_BW1 Initial Reference Picture List for Backward Picid 1 15 5 read-write IREFL_FW2 Initial Reference Picture List for Forward Picid 2 20 5 read-write IREFL_BW2 Initial Reference Picture List for Backward Picid 2 25 5 read-write IRPLR1 H264 Initial Reference Picture List Register 1 0x000000AC 32 read-write 0x00000000 IREFL_FW3 Initial Reference Picture List for Forward Picid 3 0 5 read-write IREFL_BW3 Initial Reference Picture List for Backward Picid 3 5 5 read-write IREFL_FW4 Initial Reference Picture List for Forward Picid 4 10 5 read-write IREFL_BW4 Initial Reference Picture List for Backward Picid 4 15 5 read-write IREFL_FW5 Initial Reference Picture List for Forward Picid 5 20 5 read-write IREFL_BW5 Initial Reference Picture List for Backward Picid 5 25 5 read-write IRPLR2 H264 Initial Reference Picture List Register 2 0x000000B0 32 read-write 0x00000000 IREFL_FW6 Initial Reference Picture List for Forward Picid 6 0 5 read-write IREFL_BW6 Initial Reference Picture List for Backward Picid 6 5 5 read-write IREFL_FW7 Initial Reference Picture List for Forward Picid 7 10 5 read-write IREFL_BW7 Initial Reference Picture List for Backward Picid 7 15 5 read-write IREFL_FW8 Initial Reference Picture List for Forward Picid 8 20 5 read-write IREFL_BW8 Initial Reference Picture List for Backward Picid 8 25 5 read-write IRPLR3 H264 Initial Reference Picture List Register 3 0x000000B4 32 read-write 0x00000000 IREFL_FW9 Initial Reference Picture List for Forward Picid 9 0 5 read-write IREFL_BW9 Initial Reference Picture List for Backward Picid 9 5 5 read-write IREFL_FW10 Initial Reference Picture List for Forward Picid 10 10 5 read-write IREFL_BW10 Initial Reference Picture List for Backward Picid 10 15 5 read-write IREFL_FW11 Initial Reference Picture List for Forward Picid 11 20 5 read-write IREFL_BW11 Initial Reference Picture List for Backward Picid 11 25 5 read-write IRPLR4 H264 Initial Reference Picture List Register 4 0x000000B8 32 read-write 0x00000000 IREFL_FW12 Initial Reference Picture List for Forward Picid 12 0 5 read-write IREFL_BW12 Initial Reference Picture List for Backward Picid 12 5 5 read-write IREFL_FW13 Initial Reference Picture List for Forward Picid 13 10 5 read-write IREFL_BW13 Initial Reference Picture List for Backward Picid 13 15 5 read-write IREFL_FW14 Initial Reference Picture List for Forward Picid 14 20 5 read-write IREFL_BW14 Initial Reference Picture List for Backward Picid 14 25 5 read-write IRPLR5 H264 Initial Reference Picture List Register 5 0x000000BC 32 read-write 0x00000000 IREFL_FW15 Initial Reference Picture List for Forward Picid 15 0 5 read-write IREFL_BW15 Initial Reference Picture List for Backward Picid 15 5 5 read-write ECR Error Concealment Register 0x000000C0 32 read-write 0x00000000 STARTMB_Y Start MB from SW for Y Dimension 15 8 read-write STARTMB_X Start MB from SW for X Dimension 23 9 read-write UDPHS 6227O USB High Speed Device Port UDPHS_ 0xFFF78000 0 0x4000 registers UDPHS 27 CTRL UDPHS Control Register 0x00000000 32 read-write 0x00000200 DEV_ADDR UDPHS Address 0 7 read-write FADDR_EN Function Address Enable 7 1 read-write EN_UDPHS UDPHS Enable 8 1 read-write DETACH Detach Command 9 1 read-write REWAKEUP Send Remote Wake Up 10 1 read-write PULLD_DIS Pull-Down Disable 11 1 read-write FNUM UDPHS Frame Number Register 0x00000004 32 read-only 0x00000000 MICRO_FRAME_NUM Microframe Number 0 3 read-only FRAME_NUMBER Frame Number as defined in the Packet Field Formats 3 11 read-only FNUM_ERR Frame Number CRC Error 31 1 read-only IEN UDPHS Interrupt Enable Register 0x00000010 32 read-write 0x00000010 DET_SUSPD Suspend Interrupt Enable 1 1 read-write MICRO_SOF Micro-SOF Interrupt Enable 2 1 read-write INT_SOF SOF Interrupt Enable 3 1 read-write ENDRESET End Of Reset Interrupt Enable 4 1 read-write WAKE_UP Wake Up CPU Interrupt Enable 5 1 read-write ENDOFRSM End Of Resume Interrupt Enable 6 1 read-write UPSTR_RES Upstream Resume Interrupt Enable 7 1 read-write EPT_0 Endpoint 0 Interrupt Enable 8 1 read-write EPT_1 Endpoint 1 Interrupt Enable 9 1 read-write EPT_2 Endpoint 2 Interrupt Enable 10 1 read-write EPT_3 Endpoint 3 Interrupt Enable 11 1 read-write EPT_4 Endpoint 4 Interrupt Enable 12 1 read-write EPT_5 Endpoint 5 Interrupt Enable 13 1 read-write EPT_6 Endpoint 6 Interrupt Enable 14 1 read-write DMA_1 DMA Channel 1 Interrupt Enable 25 1 read-write DMA_2 DMA Channel 2 Interrupt Enable 26 1 read-write DMA_3 DMA Channel 3 Interrupt Enable 27 1 read-write DMA_4 DMA Channel 4 Interrupt Enable 28 1 read-write DMA_5 DMA Channel 5 Interrupt Enable 29 1 read-write DMA_6 DMA Channel 6 Interrupt Enable 30 1 read-write INTSTA UDPHS Interrupt Status Register 0x00000014 32 read-only 0x00000000 SPEED Speed Status 0 1 read-only DET_SUSPD Suspend Interrupt 1 1 read-only MICRO_SOF Micro Start Of Frame Interrupt 2 1 read-only INT_SOF Start Of Frame Interrupt 3 1 read-only ENDRESET End Of Reset Interrupt 4 1 read-only WAKE_UP Wake Up CPU Interrupt 5 1 read-only ENDOFRSM End Of Resume Interrupt 6 1 read-only UPSTR_RES Upstream Resume Interrupt 7 1 read-only EPT_0 Endpoint 0 Interrupt 8 1 read-only EPT_1 Endpoint 1 Interrupt 9 1 read-only EPT_2 Endpoint 2 Interrupt 10 1 read-only EPT_3 Endpoint 3 Interrupt 11 1 read-only EPT_4 Endpoint 4 Interrupt 12 1 read-only EPT_5 Endpoint 5 Interrupt 13 1 read-only EPT_6 Endpoint 6 Interrupt 14 1 read-only DMA_1 DMA Channel 1 Interrupt 25 1 read-only DMA_2 DMA Channel 2 Interrupt 26 1 read-only DMA_3 DMA Channel 3 Interrupt 27 1 read-only DMA_4 DMA Channel 4 Interrupt 28 1 read-only DMA_5 DMA Channel 5 Interrupt 29 1 read-only DMA_6 DMA Channel 6 Interrupt 30 1 read-only CLRINT UDPHS Clear Interrupt Register 0x00000018 32 write-only DET_SUSPD Suspend Interrupt Clear 1 1 write-only MICRO_SOF Micro Start Of Frame Interrupt Clear 2 1 write-only INT_SOF Start Of Frame Interrupt Clear 3 1 write-only ENDRESET End Of Reset Interrupt Clear 4 1 write-only WAKE_UP Wake Up CPU Interrupt Clear 5 1 write-only ENDOFRSM End Of Resume Interrupt Clear 6 1 write-only UPSTR_RES Upstream Resume Interrupt Clear 7 1 write-only EPTRST UDPHS Endpoints Reset Register 0x0000001C 32 write-only EPT_0 Endpoint 0 Reset 0 1 write-only EPT_1 Endpoint 1 Reset 1 1 write-only EPT_2 Endpoint 2 Reset 2 1 write-only EPT_3 Endpoint 3 Reset 3 1 write-only EPT_4 Endpoint 4 Reset 4 1 write-only EPT_5 Endpoint 5 Reset 5 1 write-only EPT_6 Endpoint 6 Reset 6 1 write-only TST UDPHS Test Register 0x000000E0 32 read-write 0x00000000 SPEED_CFG Speed Configuration 0 2 read-write NORMAL Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode 0x0 HIGH_SPEED Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose. 0x2 FULL_SPEED Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake. 0x3 TST_J Test J Mode 2 1 read-write TST_K Test K Mode 3 1 read-write TST_PKT Test Packet Mode 4 1 read-write OPMODE2 OpMode2 5 1 read-write EPTCFG0 UDPHS Endpoint Configuration Register (endpoint = 0) 0x00000100 32 read-write 0x00000000 EPT_SIZE Endpoint Size 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_DIR Endpoint Direction 3 1 read-write EPT_TYPE Endpoint Type 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 BK_NUMBER Number of Banks 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 NB_TRANS Number Of Transaction per Microframe 8 2 read-write EPT_MAPD Endpoint Mapped 31 1 read-write EPTCTLENB0 UDPHS Endpoint Control Enable Register (endpoint = 0) 0x00000104 32 write-only EPT_ENABL Endpoint Enable 0 1 write-only AUTO_VALID Packet Auto-Valid Enable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only RX_SETUP Received SETUP 12 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only EPTCTLENB0_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 0) ISOENDPT 0x00000104 32 write-only EPT_ENABL Endpoint Enable 0 1 write-only AUTO_VALID Packet Auto-Valid Enable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only EPTCTLDIS0 UDPHS Endpoint Control Disable Register (endpoint = 0) 0x00000108 32 write-only EPT_DISABL Endpoint Disable 0 1 write-only AUTO_VALID Packet Auto-Valid Disable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only EPTCTLDIS0_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 0) ISOENDPT 0x00000108 32 write-only EPT_DISABL Endpoint Disable 0 1 write-only AUTO_VALID Packet Auto-Valid Disable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only EPTCTL0 UDPHS Endpoint Control Register (endpoint = 0) 0x0000010C 32 read-only 0x00000000 EPT_ENABL Endpoint Enable 0 1 read-only AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) 1 1 read-only INTDIS_DMA Interrupt Disables DMA 3 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled 8 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled 9 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled 10 1 read-only TXRDY TX Packet Ready Interrupt Enabled 11 1 read-only RX_SETUP Received SETUP Interrupt Enabled 12 1 read-only STALL_SNT Stall Sent Interrupt Enabled 13 1 read-only NAK_IN NAKIN Interrupt Enabled 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled 15 1 read-only BUSY_BANK Busy Bank Interrupt Enabled 18 1 read-only SHRT_PCKT Short Packet Interrupt Enabled 31 1 read-only EPTCTL0_ISOENDPT UDPHS Endpoint Control Register (endpoint = 0) ISOENDPT 0x0000010C 32 read-only 0x00000000 EPT_ENABL Endpoint Enable 0 1 read-only AUTO_VALID Packet Auto-Valid Enabled 1 1 read-only INTDIS_DMA Interrupt Disables DMA 3 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) 6 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) 7 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled 8 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled 9 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled 10 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled 11 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled 12 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled 14 1 read-only BUSY_BANK Busy Bank Interrupt Enabled 18 1 read-only SHRT_PCKT Short Packet Interrupt Enabled 31 1 read-only EPTSETSTA0 UDPHS Endpoint Set Status Register (endpoint = 0) 0x00000114 32 write-only FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA0_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 0) ISOENDPT 0x00000114 32 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTCLRSTA0 UDPHS Endpoint Clear Status Register (endpoint = 0) 0x00000118 32 write-only FRCESTALL Stall Handshake Request Clear 5 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only EPTCLRSTA0_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 0) ISOENDPT 0x00000118 32 write-only TOGGLESQ Data Toggle Clear 6 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only EPTSTA0 UDPHS Endpoint Status Register (endpoint = 0) 0x0000011C 32 read-only 0x00000040 FRCESTALL Stall Handshake Request 5 1 read-only TOGGLESQ_STA Toggle Sequencing 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 ERR_OVFLW Overflow Error 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank 9 1 read-only TX_COMPLT Transmitted IN Data Complete 10 1 read-only TXRDY TX Packet Ready 11 1 read-only RX_SETUP Received SETUP 12 1 read-only STALL_SNT Stall Sent 13 1 read-only NAK_IN NAK IN 14 1 read-only NAK_OUT NAK OUT 15 1 read-only CURBK_CTLDIR Current Bank/Control Direction 16 2 read-only BUSY_BANK_STA Busy Bank Number 18 2 read-only 1BUSYBANK 1 busy bank 0x0 2BUSYBANKS 2 busy banks 0x1 3BUSYBANKS 3 busy banks 0x2 BYTE_COUNT UDPHS Byte Count 20 11 read-only SHRT_PCKT Short Packet 31 1 read-only EPTSTA0_ISOENDPT UDPHS Endpoint Status Register (endpoint = 0) ISOENDPT 0x0000011C 32 read-only 0x00000040 TOGGLESQ_STA Toggle Sequencing 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 ERR_OVFLW Overflow Error 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank 9 1 read-only TX_COMPLT Transmitted IN Data Complete 10 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error 11 1 read-only ERR_FL_ISO Error Flow 12 1 read-only ERR_CRC_NTR CRC ISO Error/Number of Transaction Error 13 1 read-only ERR_FLUSH Bank Flush Error 14 1 read-only CURBK Current Bank 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 BUSY_BANK_STA Busy Bank Number 18 2 read-only 1BUSYBANK 1 busy bank 0x0 2BUSYBANKS 2 busy banks 0x1 3BUSYBANKS 3 busy banks 0x2 BYTE_COUNT UDPHS Byte Count 20 11 read-only SHRT_PCKT Short Packet 31 1 read-only EPTCFG1 UDPHS Endpoint Configuration Register (endpoint = 1) 0x00000120 32 read-write 0x00000000 EPT_SIZE Endpoint Size 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_DIR Endpoint Direction 3 1 read-write EPT_TYPE Endpoint Type 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 BK_NUMBER Number of Banks 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 NB_TRANS Number Of Transaction per Microframe 8 2 read-write EPT_MAPD Endpoint Mapped 31 1 read-write EPTCTLENB1 UDPHS Endpoint Control Enable Register (endpoint = 1) 0x00000124 32 write-only EPT_ENABL Endpoint Enable 0 1 write-only AUTO_VALID Packet Auto-Valid Enable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only RX_SETUP Received SETUP 12 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only EPTCTLENB1_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 1) ISOENDPT 0x00000124 32 write-only EPT_ENABL Endpoint Enable 0 1 write-only AUTO_VALID Packet Auto-Valid Enable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only EPTCTLDIS1 UDPHS Endpoint Control Disable Register (endpoint = 1) 0x00000128 32 write-only EPT_DISABL Endpoint Disable 0 1 write-only AUTO_VALID Packet Auto-Valid Disable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only EPTCTLDIS1_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 1) ISOENDPT 0x00000128 32 write-only EPT_DISABL Endpoint Disable 0 1 write-only AUTO_VALID Packet Auto-Valid Disable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only EPTCTL1 UDPHS Endpoint Control Register (endpoint = 1) 0x0000012C 32 read-only 0x00000000 EPT_ENABL Endpoint Enable 0 1 read-only AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) 1 1 read-only INTDIS_DMA Interrupt Disables DMA 3 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled 8 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled 9 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled 10 1 read-only TXRDY TX Packet Ready Interrupt Enabled 11 1 read-only RX_SETUP Received SETUP Interrupt Enabled 12 1 read-only STALL_SNT Stall Sent Interrupt Enabled 13 1 read-only NAK_IN NAKIN Interrupt Enabled 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled 15 1 read-only BUSY_BANK Busy Bank Interrupt Enabled 18 1 read-only SHRT_PCKT Short Packet Interrupt Enabled 31 1 read-only EPTCTL1_ISOENDPT UDPHS Endpoint Control Register (endpoint = 1) ISOENDPT 0x0000012C 32 read-only 0x00000000 EPT_ENABL Endpoint Enable 0 1 read-only AUTO_VALID Packet Auto-Valid Enabled 1 1 read-only INTDIS_DMA Interrupt Disables DMA 3 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) 6 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) 7 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled 8 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled 9 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled 10 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled 11 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled 12 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled 14 1 read-only BUSY_BANK Busy Bank Interrupt Enabled 18 1 read-only SHRT_PCKT Short Packet Interrupt Enabled 31 1 read-only EPTSETSTA1 UDPHS Endpoint Set Status Register (endpoint = 1) 0x00000134 32 write-only FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA1_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 1) ISOENDPT 0x00000134 32 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTCLRSTA1 UDPHS Endpoint Clear Status Register (endpoint = 1) 0x00000138 32 write-only FRCESTALL Stall Handshake Request Clear 5 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only EPTCLRSTA1_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 1) ISOENDPT 0x00000138 32 write-only TOGGLESQ Data Toggle Clear 6 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only EPTSTA1 UDPHS Endpoint Status Register (endpoint = 1) 0x0000013C 32 read-only 0x00000040 FRCESTALL Stall Handshake Request 5 1 read-only TOGGLESQ_STA Toggle Sequencing 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 ERR_OVFLW Overflow Error 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank 9 1 read-only TX_COMPLT Transmitted IN Data Complete 10 1 read-only TXRDY TX Packet Ready 11 1 read-only RX_SETUP Received SETUP 12 1 read-only STALL_SNT Stall Sent 13 1 read-only NAK_IN NAK IN 14 1 read-only NAK_OUT NAK OUT 15 1 read-only CURBK_CTLDIR Current Bank/Control Direction 16 2 read-only BUSY_BANK_STA Busy Bank Number 18 2 read-only 1BUSYBANK 1 busy bank 0x0 2BUSYBANKS 2 busy banks 0x1 3BUSYBANKS 3 busy banks 0x2 BYTE_COUNT UDPHS Byte Count 20 11 read-only SHRT_PCKT Short Packet 31 1 read-only EPTSTA1_ISOENDPT UDPHS Endpoint Status Register (endpoint = 1) ISOENDPT 0x0000013C 32 read-only 0x00000040 TOGGLESQ_STA Toggle Sequencing 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 ERR_OVFLW Overflow Error 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank 9 1 read-only TX_COMPLT Transmitted IN Data Complete 10 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error 11 1 read-only ERR_FL_ISO Error Flow 12 1 read-only ERR_CRC_NTR CRC ISO Error/Number of Transaction Error 13 1 read-only ERR_FLUSH Bank Flush Error 14 1 read-only CURBK Current Bank 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 BUSY_BANK_STA Busy Bank Number 18 2 read-only 1BUSYBANK 1 busy bank 0x0 2BUSYBANKS 2 busy banks 0x1 3BUSYBANKS 3 busy banks 0x2 BYTE_COUNT UDPHS Byte Count 20 11 read-only SHRT_PCKT Short Packet 31 1 read-only EPTCFG2 UDPHS Endpoint Configuration Register (endpoint = 2) 0x00000140 32 read-write 0x00000000 EPT_SIZE Endpoint Size 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_DIR Endpoint Direction 3 1 read-write EPT_TYPE Endpoint Type 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 BK_NUMBER Number of Banks 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 NB_TRANS Number Of Transaction per Microframe 8 2 read-write EPT_MAPD Endpoint Mapped 31 1 read-write EPTCTLENB2 UDPHS Endpoint Control Enable Register (endpoint = 2) 0x00000144 32 write-only EPT_ENABL Endpoint Enable 0 1 write-only AUTO_VALID Packet Auto-Valid Enable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only RX_SETUP Received SETUP 12 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only EPTCTLENB2_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 2) ISOENDPT 0x00000144 32 write-only EPT_ENABL Endpoint Enable 0 1 write-only AUTO_VALID Packet Auto-Valid Enable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only EPTCTLDIS2 UDPHS Endpoint Control Disable Register (endpoint = 2) 0x00000148 32 write-only EPT_DISABL Endpoint Disable 0 1 write-only AUTO_VALID Packet Auto-Valid Disable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only EPTCTLDIS2_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 2) ISOENDPT 0x00000148 32 write-only EPT_DISABL Endpoint Disable 0 1 write-only AUTO_VALID Packet Auto-Valid Disable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only EPTCTL2 UDPHS Endpoint Control Register (endpoint = 2) 0x0000014C 32 read-only 0x00000000 EPT_ENABL Endpoint Enable 0 1 read-only AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) 1 1 read-only INTDIS_DMA Interrupt Disables DMA 3 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled 8 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled 9 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled 10 1 read-only TXRDY TX Packet Ready Interrupt Enabled 11 1 read-only RX_SETUP Received SETUP Interrupt Enabled 12 1 read-only STALL_SNT Stall Sent Interrupt Enabled 13 1 read-only NAK_IN NAKIN Interrupt Enabled 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled 15 1 read-only BUSY_BANK Busy Bank Interrupt Enabled 18 1 read-only SHRT_PCKT Short Packet Interrupt Enabled 31 1 read-only EPTCTL2_ISOENDPT UDPHS Endpoint Control Register (endpoint = 2) ISOENDPT 0x0000014C 32 read-only 0x00000000 EPT_ENABL Endpoint Enable 0 1 read-only AUTO_VALID Packet Auto-Valid Enabled 1 1 read-only INTDIS_DMA Interrupt Disables DMA 3 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) 6 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) 7 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled 8 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled 9 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled 10 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled 11 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled 12 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled 14 1 read-only BUSY_BANK Busy Bank Interrupt Enabled 18 1 read-only SHRT_PCKT Short Packet Interrupt Enabled 31 1 read-only EPTSETSTA2 UDPHS Endpoint Set Status Register (endpoint = 2) 0x00000154 32 write-only FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA2_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 2) ISOENDPT 0x00000154 32 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTCLRSTA2 UDPHS Endpoint Clear Status Register (endpoint = 2) 0x00000158 32 write-only FRCESTALL Stall Handshake Request Clear 5 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only EPTCLRSTA2_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 2) ISOENDPT 0x00000158 32 write-only TOGGLESQ Data Toggle Clear 6 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only EPTSTA2 UDPHS Endpoint Status Register (endpoint = 2) 0x0000015C 32 read-only 0x00000040 FRCESTALL Stall Handshake Request 5 1 read-only TOGGLESQ_STA Toggle Sequencing 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 ERR_OVFLW Overflow Error 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank 9 1 read-only TX_COMPLT Transmitted IN Data Complete 10 1 read-only TXRDY TX Packet Ready 11 1 read-only RX_SETUP Received SETUP 12 1 read-only STALL_SNT Stall Sent 13 1 read-only NAK_IN NAK IN 14 1 read-only NAK_OUT NAK OUT 15 1 read-only CURBK_CTLDIR Current Bank/Control Direction 16 2 read-only BUSY_BANK_STA Busy Bank Number 18 2 read-only 1BUSYBANK 1 busy bank 0x0 2BUSYBANKS 2 busy banks 0x1 3BUSYBANKS 3 busy banks 0x2 BYTE_COUNT UDPHS Byte Count 20 11 read-only SHRT_PCKT Short Packet 31 1 read-only EPTSTA2_ISOENDPT UDPHS Endpoint Status Register (endpoint = 2) ISOENDPT 0x0000015C 32 read-only 0x00000040 TOGGLESQ_STA Toggle Sequencing 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 ERR_OVFLW Overflow Error 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank 9 1 read-only TX_COMPLT Transmitted IN Data Complete 10 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error 11 1 read-only ERR_FL_ISO Error Flow 12 1 read-only ERR_CRC_NTR CRC ISO Error/Number of Transaction Error 13 1 read-only ERR_FLUSH Bank Flush Error 14 1 read-only CURBK Current Bank 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 BUSY_BANK_STA Busy Bank Number 18 2 read-only 1BUSYBANK 1 busy bank 0x0 2BUSYBANKS 2 busy banks 0x1 3BUSYBANKS 3 busy banks 0x2 BYTE_COUNT UDPHS Byte Count 20 11 read-only SHRT_PCKT Short Packet 31 1 read-only EPTCFG3 UDPHS Endpoint Configuration Register (endpoint = 3) 0x00000160 32 read-write 0x00000000 EPT_SIZE Endpoint Size 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_DIR Endpoint Direction 3 1 read-write EPT_TYPE Endpoint Type 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 BK_NUMBER Number of Banks 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 NB_TRANS Number Of Transaction per Microframe 8 2 read-write EPT_MAPD Endpoint Mapped 31 1 read-write EPTCTLENB3 UDPHS Endpoint Control Enable Register (endpoint = 3) 0x00000164 32 write-only EPT_ENABL Endpoint Enable 0 1 write-only AUTO_VALID Packet Auto-Valid Enable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only RX_SETUP Received SETUP 12 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only EPTCTLENB3_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 3) ISOENDPT 0x00000164 32 write-only EPT_ENABL Endpoint Enable 0 1 write-only AUTO_VALID Packet Auto-Valid Enable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only EPTCTLDIS3 UDPHS Endpoint Control Disable Register (endpoint = 3) 0x00000168 32 write-only EPT_DISABL Endpoint Disable 0 1 write-only AUTO_VALID Packet Auto-Valid Disable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only EPTCTLDIS3_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 3) ISOENDPT 0x00000168 32 write-only EPT_DISABL Endpoint Disable 0 1 write-only AUTO_VALID Packet Auto-Valid Disable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only EPTCTL3 UDPHS Endpoint Control Register (endpoint = 3) 0x0000016C 32 read-only 0x00000000 EPT_ENABL Endpoint Enable 0 1 read-only AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) 1 1 read-only INTDIS_DMA Interrupt Disables DMA 3 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled 8 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled 9 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled 10 1 read-only TXRDY TX Packet Ready Interrupt Enabled 11 1 read-only RX_SETUP Received SETUP Interrupt Enabled 12 1 read-only STALL_SNT Stall Sent Interrupt Enabled 13 1 read-only NAK_IN NAKIN Interrupt Enabled 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled 15 1 read-only BUSY_BANK Busy Bank Interrupt Enabled 18 1 read-only SHRT_PCKT Short Packet Interrupt Enabled 31 1 read-only EPTCTL3_ISOENDPT UDPHS Endpoint Control Register (endpoint = 3) ISOENDPT 0x0000016C 32 read-only 0x00000000 EPT_ENABL Endpoint Enable 0 1 read-only AUTO_VALID Packet Auto-Valid Enabled 1 1 read-only INTDIS_DMA Interrupt Disables DMA 3 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) 6 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) 7 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled 8 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled 9 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled 10 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled 11 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled 12 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled 14 1 read-only BUSY_BANK Busy Bank Interrupt Enabled 18 1 read-only SHRT_PCKT Short Packet Interrupt Enabled 31 1 read-only EPTSETSTA3 UDPHS Endpoint Set Status Register (endpoint = 3) 0x00000174 32 write-only FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA3_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 3) ISOENDPT 0x00000174 32 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTCLRSTA3 UDPHS Endpoint Clear Status Register (endpoint = 3) 0x00000178 32 write-only FRCESTALL Stall Handshake Request Clear 5 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only EPTCLRSTA3_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 3) ISOENDPT 0x00000178 32 write-only TOGGLESQ Data Toggle Clear 6 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only EPTSTA3 UDPHS Endpoint Status Register (endpoint = 3) 0x0000017C 32 read-only 0x00000040 FRCESTALL Stall Handshake Request 5 1 read-only TOGGLESQ_STA Toggle Sequencing 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 ERR_OVFLW Overflow Error 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank 9 1 read-only TX_COMPLT Transmitted IN Data Complete 10 1 read-only TXRDY TX Packet Ready 11 1 read-only RX_SETUP Received SETUP 12 1 read-only STALL_SNT Stall Sent 13 1 read-only NAK_IN NAK IN 14 1 read-only NAK_OUT NAK OUT 15 1 read-only CURBK_CTLDIR Current Bank/Control Direction 16 2 read-only BUSY_BANK_STA Busy Bank Number 18 2 read-only 1BUSYBANK 1 busy bank 0x0 2BUSYBANKS 2 busy banks 0x1 3BUSYBANKS 3 busy banks 0x2 BYTE_COUNT UDPHS Byte Count 20 11 read-only SHRT_PCKT Short Packet 31 1 read-only EPTSTA3_ISOENDPT UDPHS Endpoint Status Register (endpoint = 3) ISOENDPT 0x0000017C 32 read-only 0x00000040 TOGGLESQ_STA Toggle Sequencing 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 ERR_OVFLW Overflow Error 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank 9 1 read-only TX_COMPLT Transmitted IN Data Complete 10 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error 11 1 read-only ERR_FL_ISO Error Flow 12 1 read-only ERR_CRC_NTR CRC ISO Error/Number of Transaction Error 13 1 read-only ERR_FLUSH Bank Flush Error 14 1 read-only CURBK Current Bank 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 BUSY_BANK_STA Busy Bank Number 18 2 read-only 1BUSYBANK 1 busy bank 0x0 2BUSYBANKS 2 busy banks 0x1 3BUSYBANKS 3 busy banks 0x2 BYTE_COUNT UDPHS Byte Count 20 11 read-only SHRT_PCKT Short Packet 31 1 read-only EPTCFG4 UDPHS Endpoint Configuration Register (endpoint = 4) 0x00000180 32 read-write 0x00000000 EPT_SIZE Endpoint Size 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_DIR Endpoint Direction 3 1 read-write EPT_TYPE Endpoint Type 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 BK_NUMBER Number of Banks 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 NB_TRANS Number Of Transaction per Microframe 8 2 read-write EPT_MAPD Endpoint Mapped 31 1 read-write EPTCTLENB4 UDPHS Endpoint Control Enable Register (endpoint = 4) 0x00000184 32 write-only EPT_ENABL Endpoint Enable 0 1 write-only AUTO_VALID Packet Auto-Valid Enable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only RX_SETUP Received SETUP 12 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only EPTCTLENB4_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 4) ISOENDPT 0x00000184 32 write-only EPT_ENABL Endpoint Enable 0 1 write-only AUTO_VALID Packet Auto-Valid Enable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only EPTCTLDIS4 UDPHS Endpoint Control Disable Register (endpoint = 4) 0x00000188 32 write-only EPT_DISABL Endpoint Disable 0 1 write-only AUTO_VALID Packet Auto-Valid Disable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only EPTCTLDIS4_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 4) ISOENDPT 0x00000188 32 write-only EPT_DISABL Endpoint Disable 0 1 write-only AUTO_VALID Packet Auto-Valid Disable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only EPTCTL4 UDPHS Endpoint Control Register (endpoint = 4) 0x0000018C 32 read-only 0x00000000 EPT_ENABL Endpoint Enable 0 1 read-only AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) 1 1 read-only INTDIS_DMA Interrupt Disables DMA 3 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled 8 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled 9 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled 10 1 read-only TXRDY TX Packet Ready Interrupt Enabled 11 1 read-only RX_SETUP Received SETUP Interrupt Enabled 12 1 read-only STALL_SNT Stall Sent Interrupt Enabled 13 1 read-only NAK_IN NAKIN Interrupt Enabled 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled 15 1 read-only BUSY_BANK Busy Bank Interrupt Enabled 18 1 read-only SHRT_PCKT Short Packet Interrupt Enabled 31 1 read-only EPTCTL4_ISOENDPT UDPHS Endpoint Control Register (endpoint = 4) ISOENDPT 0x0000018C 32 read-only 0x00000000 EPT_ENABL Endpoint Enable 0 1 read-only AUTO_VALID Packet Auto-Valid Enabled 1 1 read-only INTDIS_DMA Interrupt Disables DMA 3 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) 6 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) 7 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled 8 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled 9 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled 10 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled 11 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled 12 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled 14 1 read-only BUSY_BANK Busy Bank Interrupt Enabled 18 1 read-only SHRT_PCKT Short Packet Interrupt Enabled 31 1 read-only EPTSETSTA4 UDPHS Endpoint Set Status Register (endpoint = 4) 0x00000194 32 write-only FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA4_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 4) ISOENDPT 0x00000194 32 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTCLRSTA4 UDPHS Endpoint Clear Status Register (endpoint = 4) 0x00000198 32 write-only FRCESTALL Stall Handshake Request Clear 5 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only EPTCLRSTA4_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 4) ISOENDPT 0x00000198 32 write-only TOGGLESQ Data Toggle Clear 6 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only EPTSTA4 UDPHS Endpoint Status Register (endpoint = 4) 0x0000019C 32 read-only 0x00000040 FRCESTALL Stall Handshake Request 5 1 read-only TOGGLESQ_STA Toggle Sequencing 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 ERR_OVFLW Overflow Error 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank 9 1 read-only TX_COMPLT Transmitted IN Data Complete 10 1 read-only TXRDY TX Packet Ready 11 1 read-only RX_SETUP Received SETUP 12 1 read-only STALL_SNT Stall Sent 13 1 read-only NAK_IN NAK IN 14 1 read-only NAK_OUT NAK OUT 15 1 read-only CURBK_CTLDIR Current Bank/Control Direction 16 2 read-only BUSY_BANK_STA Busy Bank Number 18 2 read-only 1BUSYBANK 1 busy bank 0x0 2BUSYBANKS 2 busy banks 0x1 3BUSYBANKS 3 busy banks 0x2 BYTE_COUNT UDPHS Byte Count 20 11 read-only SHRT_PCKT Short Packet 31 1 read-only EPTSTA4_ISOENDPT UDPHS Endpoint Status Register (endpoint = 4) ISOENDPT 0x0000019C 32 read-only 0x00000040 TOGGLESQ_STA Toggle Sequencing 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 ERR_OVFLW Overflow Error 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank 9 1 read-only TX_COMPLT Transmitted IN Data Complete 10 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error 11 1 read-only ERR_FL_ISO Error Flow 12 1 read-only ERR_CRC_NTR CRC ISO Error/Number of Transaction Error 13 1 read-only ERR_FLUSH Bank Flush Error 14 1 read-only CURBK Current Bank 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 BUSY_BANK_STA Busy Bank Number 18 2 read-only 1BUSYBANK 1 busy bank 0x0 2BUSYBANKS 2 busy banks 0x1 3BUSYBANKS 3 busy banks 0x2 BYTE_COUNT UDPHS Byte Count 20 11 read-only SHRT_PCKT Short Packet 31 1 read-only EPTCFG5 UDPHS Endpoint Configuration Register (endpoint = 5) 0x000001A0 32 read-write 0x00000000 EPT_SIZE Endpoint Size 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_DIR Endpoint Direction 3 1 read-write EPT_TYPE Endpoint Type 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 BK_NUMBER Number of Banks 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 NB_TRANS Number Of Transaction per Microframe 8 2 read-write EPT_MAPD Endpoint Mapped 31 1 read-write EPTCTLENB5 UDPHS Endpoint Control Enable Register (endpoint = 5) 0x000001A4 32 write-only EPT_ENABL Endpoint Enable 0 1 write-only AUTO_VALID Packet Auto-Valid Enable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only RX_SETUP Received SETUP 12 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only EPTCTLENB5_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 5) ISOENDPT 0x000001A4 32 write-only EPT_ENABL Endpoint Enable 0 1 write-only AUTO_VALID Packet Auto-Valid Enable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only EPTCTLDIS5 UDPHS Endpoint Control Disable Register (endpoint = 5) 0x000001A8 32 write-only EPT_DISABL Endpoint Disable 0 1 write-only AUTO_VALID Packet Auto-Valid Disable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only EPTCTLDIS5_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 5) ISOENDPT 0x000001A8 32 write-only EPT_DISABL Endpoint Disable 0 1 write-only AUTO_VALID Packet Auto-Valid Disable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only EPTCTL5 UDPHS Endpoint Control Register (endpoint = 5) 0x000001AC 32 read-only 0x00000000 EPT_ENABL Endpoint Enable 0 1 read-only AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) 1 1 read-only INTDIS_DMA Interrupt Disables DMA 3 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled 8 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled 9 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled 10 1 read-only TXRDY TX Packet Ready Interrupt Enabled 11 1 read-only RX_SETUP Received SETUP Interrupt Enabled 12 1 read-only STALL_SNT Stall Sent Interrupt Enabled 13 1 read-only NAK_IN NAKIN Interrupt Enabled 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled 15 1 read-only BUSY_BANK Busy Bank Interrupt Enabled 18 1 read-only SHRT_PCKT Short Packet Interrupt Enabled 31 1 read-only EPTCTL5_ISOENDPT UDPHS Endpoint Control Register (endpoint = 5) ISOENDPT 0x000001AC 32 read-only 0x00000000 EPT_ENABL Endpoint Enable 0 1 read-only AUTO_VALID Packet Auto-Valid Enabled 1 1 read-only INTDIS_DMA Interrupt Disables DMA 3 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) 6 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) 7 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled 8 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled 9 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled 10 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled 11 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled 12 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled 14 1 read-only BUSY_BANK Busy Bank Interrupt Enabled 18 1 read-only SHRT_PCKT Short Packet Interrupt Enabled 31 1 read-only EPTSETSTA5 UDPHS Endpoint Set Status Register (endpoint = 5) 0x000001B4 32 write-only FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA5_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 5) ISOENDPT 0x000001B4 32 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTCLRSTA5 UDPHS Endpoint Clear Status Register (endpoint = 5) 0x000001B8 32 write-only FRCESTALL Stall Handshake Request Clear 5 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only EPTCLRSTA5_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 5) ISOENDPT 0x000001B8 32 write-only TOGGLESQ Data Toggle Clear 6 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only EPTSTA5 UDPHS Endpoint Status Register (endpoint = 5) 0x000001BC 32 read-only 0x00000040 FRCESTALL Stall Handshake Request 5 1 read-only TOGGLESQ_STA Toggle Sequencing 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 ERR_OVFLW Overflow Error 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank 9 1 read-only TX_COMPLT Transmitted IN Data Complete 10 1 read-only TXRDY TX Packet Ready 11 1 read-only RX_SETUP Received SETUP 12 1 read-only STALL_SNT Stall Sent 13 1 read-only NAK_IN NAK IN 14 1 read-only NAK_OUT NAK OUT 15 1 read-only CURBK_CTLDIR Current Bank/Control Direction 16 2 read-only BUSY_BANK_STA Busy Bank Number 18 2 read-only 1BUSYBANK 1 busy bank 0x0 2BUSYBANKS 2 busy banks 0x1 3BUSYBANKS 3 busy banks 0x2 BYTE_COUNT UDPHS Byte Count 20 11 read-only SHRT_PCKT Short Packet 31 1 read-only EPTSTA5_ISOENDPT UDPHS Endpoint Status Register (endpoint = 5) ISOENDPT 0x000001BC 32 read-only 0x00000040 TOGGLESQ_STA Toggle Sequencing 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 ERR_OVFLW Overflow Error 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank 9 1 read-only TX_COMPLT Transmitted IN Data Complete 10 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error 11 1 read-only ERR_FL_ISO Error Flow 12 1 read-only ERR_CRC_NTR CRC ISO Error/Number of Transaction Error 13 1 read-only ERR_FLUSH Bank Flush Error 14 1 read-only CURBK Current Bank 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 BUSY_BANK_STA Busy Bank Number 18 2 read-only 1BUSYBANK 1 busy bank 0x0 2BUSYBANKS 2 busy banks 0x1 3BUSYBANKS 3 busy banks 0x2 BYTE_COUNT UDPHS Byte Count 20 11 read-only SHRT_PCKT Short Packet 31 1 read-only EPTCFG6 UDPHS Endpoint Configuration Register (endpoint = 6) 0x000001C0 32 read-write 0x00000000 EPT_SIZE Endpoint Size 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_DIR Endpoint Direction 3 1 read-write EPT_TYPE Endpoint Type 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 BK_NUMBER Number of Banks 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 NB_TRANS Number Of Transaction per Microframe 8 2 read-write EPT_MAPD Endpoint Mapped 31 1 read-write EPTCTLENB6 UDPHS Endpoint Control Enable Register (endpoint = 6) 0x000001C4 32 write-only EPT_ENABL Endpoint Enable 0 1 write-only AUTO_VALID Packet Auto-Valid Enable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only RX_SETUP Received SETUP 12 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only EPTCTLENB6_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 6) ISOENDPT 0x000001C4 32 write-only EPT_ENABL Endpoint Enable 0 1 write-only AUTO_VALID Packet Auto-Valid Enable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only EPTCTLDIS6 UDPHS Endpoint Control Disable Register (endpoint = 6) 0x000001C8 32 write-only EPT_DISABL Endpoint Disable 0 1 write-only AUTO_VALID Packet Auto-Valid Disable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only EPTCTLDIS6_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 6) ISOENDPT 0x000001C8 32 write-only EPT_DISABL Endpoint Disable 0 1 write-only AUTO_VALID Packet Auto-Valid Disable 1 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only EPTCTL6 UDPHS Endpoint Control Register (endpoint = 6) 0x000001CC 32 read-only 0x00000000 EPT_ENABL Endpoint Enable 0 1 read-only AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) 1 1 read-only INTDIS_DMA Interrupt Disables DMA 3 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled 8 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled 9 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled 10 1 read-only TXRDY TX Packet Ready Interrupt Enabled 11 1 read-only RX_SETUP Received SETUP Interrupt Enabled 12 1 read-only STALL_SNT Stall Sent Interrupt Enabled 13 1 read-only NAK_IN NAKIN Interrupt Enabled 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled 15 1 read-only BUSY_BANK Busy Bank Interrupt Enabled 18 1 read-only SHRT_PCKT Short Packet Interrupt Enabled 31 1 read-only EPTCTL6_ISOENDPT UDPHS Endpoint Control Register (endpoint = 6) ISOENDPT 0x000001CC 32 read-only 0x00000000 EPT_ENABL Endpoint Enable 0 1 read-only AUTO_VALID Packet Auto-Valid Enabled 1 1 read-only INTDIS_DMA Interrupt Disables DMA 3 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) 6 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) 7 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled 8 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled 9 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled 10 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled 11 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled 12 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled 14 1 read-only BUSY_BANK Busy Bank Interrupt Enabled 18 1 read-only SHRT_PCKT Short Packet Interrupt Enabled 31 1 read-only EPTSETSTA6 UDPHS Endpoint Set Status Register (endpoint = 6) 0x000001D4 32 write-only FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA6_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 6) ISOENDPT 0x000001D4 32 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTCLRSTA6 UDPHS Endpoint Clear Status Register (endpoint = 6) 0x000001D8 32 write-only FRCESTALL Stall Handshake Request Clear 5 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only EPTCLRSTA6_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 6) ISOENDPT 0x000001D8 32 write-only TOGGLESQ Data Toggle Clear 6 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only EPTSTA6 UDPHS Endpoint Status Register (endpoint = 6) 0x000001DC 32 read-only 0x00000040 FRCESTALL Stall Handshake Request 5 1 read-only TOGGLESQ_STA Toggle Sequencing 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 ERR_OVFLW Overflow Error 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank 9 1 read-only TX_COMPLT Transmitted IN Data Complete 10 1 read-only TXRDY TX Packet Ready 11 1 read-only RX_SETUP Received SETUP 12 1 read-only STALL_SNT Stall Sent 13 1 read-only NAK_IN NAK IN 14 1 read-only NAK_OUT NAK OUT 15 1 read-only CURBK_CTLDIR Current Bank/Control Direction 16 2 read-only BUSY_BANK_STA Busy Bank Number 18 2 read-only 1BUSYBANK 1 busy bank 0x0 2BUSYBANKS 2 busy banks 0x1 3BUSYBANKS 3 busy banks 0x2 BYTE_COUNT UDPHS Byte Count 20 11 read-only SHRT_PCKT Short Packet 31 1 read-only EPTSTA6_ISOENDPT UDPHS Endpoint Status Register (endpoint = 6) ISOENDPT 0x000001DC 32 read-only 0x00000040 TOGGLESQ_STA Toggle Sequencing 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 ERR_OVFLW Overflow Error 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank 9 1 read-only TX_COMPLT Transmitted IN Data Complete 10 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error 11 1 read-only ERR_FL_ISO Error Flow 12 1 read-only ERR_CRC_NTR CRC ISO Error/Number of Transaction Error 13 1 read-only ERR_FLUSH Bank Flush Error 14 1 read-only CURBK Current Bank 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 BUSY_BANK_STA Busy Bank Number 18 2 read-only 1BUSYBANK 1 busy bank 0x0 2BUSYBANKS 2 busy banks 0x1 3BUSYBANKS 3 busy banks 0x2 BYTE_COUNT UDPHS Byte Count 20 11 read-only SHRT_PCKT Short Packet 31 1 read-only DMANXTDSC0 UDPHS DMA Next Descriptor Address Register (channel = 0) 0x00000300 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DMAADDRESS0 UDPHS DMA Channel Address Register (channel = 0) 0x00000304 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write DMACONTROL0 UDPHS DMA Channel Control Register (channel = 0) 0x00000308 32 read-write 0x00000000 CHANN_ENB (Channel Enable Command) 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable (Command) 1 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_B_EN End of Buffer Enable (Control) 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write DMASTATUS0 UDPHS DMA Channel Status Register (channel = 0) 0x0000030C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write DMANXTDSC1 UDPHS DMA Next Descriptor Address Register (channel = 1) 0x00000310 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DMAADDRESS1 UDPHS DMA Channel Address Register (channel = 1) 0x00000314 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write DMACONTROL1 UDPHS DMA Channel Control Register (channel = 1) 0x00000318 32 read-write 0x00000000 CHANN_ENB (Channel Enable Command) 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable (Command) 1 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_B_EN End of Buffer Enable (Control) 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write DMASTATUS1 UDPHS DMA Channel Status Register (channel = 1) 0x0000031C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write DMANXTDSC2 UDPHS DMA Next Descriptor Address Register (channel = 2) 0x00000320 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DMAADDRESS2 UDPHS DMA Channel Address Register (channel = 2) 0x00000324 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write DMACONTROL2 UDPHS DMA Channel Control Register (channel = 2) 0x00000328 32 read-write 0x00000000 CHANN_ENB (Channel Enable Command) 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable (Command) 1 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_B_EN End of Buffer Enable (Control) 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write DMASTATUS2 UDPHS DMA Channel Status Register (channel = 2) 0x0000032C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write DMANXTDSC3 UDPHS DMA Next Descriptor Address Register (channel = 3) 0x00000330 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DMAADDRESS3 UDPHS DMA Channel Address Register (channel = 3) 0x00000334 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write DMACONTROL3 UDPHS DMA Channel Control Register (channel = 3) 0x00000338 32 read-write 0x00000000 CHANN_ENB (Channel Enable Command) 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable (Command) 1 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_B_EN End of Buffer Enable (Control) 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write DMASTATUS3 UDPHS DMA Channel Status Register (channel = 3) 0x0000033C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write DMANXTDSC4 UDPHS DMA Next Descriptor Address Register (channel = 4) 0x00000340 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DMAADDRESS4 UDPHS DMA Channel Address Register (channel = 4) 0x00000344 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write DMACONTROL4 UDPHS DMA Channel Control Register (channel = 4) 0x00000348 32 read-write 0x00000000 CHANN_ENB (Channel Enable Command) 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable (Command) 1 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_B_EN End of Buffer Enable (Control) 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write DMASTATUS4 UDPHS DMA Channel Status Register (channel = 4) 0x0000034C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write DMANXTDSC5 UDPHS DMA Next Descriptor Address Register (channel = 5) 0x00000350 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DMAADDRESS5 UDPHS DMA Channel Address Register (channel = 5) 0x00000354 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write DMACONTROL5 UDPHS DMA Channel Control Register (channel = 5) 0x00000358 32 read-write 0x00000000 CHANN_ENB (Channel Enable Command) 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable (Command) 1 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_B_EN End of Buffer Enable (Control) 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write DMASTATUS5 UDPHS DMA Channel Status Register (channel = 5) 0x0000035C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write TC0 6082J Timer Counter 0 TC TC0_ 0xFFF7C000 0 0x4000 registers TC0 18 CCR0 Channel Control Register (channel = 0) 0x00000000 32 write-only CLKEN Counter Clock Enable Command 0 1 write-only CLKDIS Counter Clock Disable Command 1 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR0 Channel Mode Register (channel = 0) 0x00000004 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDBDIS Counter Clock Disable with RB Loading 7 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write WAVE 15 1 read-write LDRA RA Loading Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 CMR0_WAVE_EQ_1 Channel Mode Register (channel = 0) WAVE_EQ_1 0x00000004 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 ENETRG External Event Trigger Enable 12 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UP_RC UP mode with automatic trigger on RC Compare 0x1 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 WAVE 15 1 read-write ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 CV0 Counter Value (channel = 0) 0x00000010 32 read-only 0x00000000 CV Counter Value 0 16 read-only RA0 Register A (channel = 0) 0x00000014 32 read-write 0x00000000 RA Register A 0 16 read-write RB0 Register B (channel = 0) 0x00000018 32 read-write 0x00000000 RB Register B 0 16 read-write RC0 Register C (channel = 0) 0x0000001C 32 read-write 0x00000000 RC Register C 0 16 read-write SR0 Status Register (channel = 0) 0x00000020 32 read-only 0x00000000 COVFS Counter Overflow Status 0 1 read-only LOVRS Load Overrun Status 1 1 read-only CPAS RA Compare Status 2 1 read-only CPBS RB Compare Status 3 1 read-only CPCS RC Compare Status 4 1 read-only LDRAS RA Loading Status 5 1 read-only LDRBS RB Loading Status 6 1 read-only ETRGS External Trigger Status 7 1 read-only CLKSTA Clock Enabling Status 16 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only IER0 Interrupt Enable Register (channel = 0) 0x00000024 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IDR0 Interrupt Disable Register (channel = 0) 0x00000028 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IMR0 Interrupt Mask Register (channel = 0) 0x0000002C 32 read-only 0x00000000 COVFS Counter Overflow 0 1 read-only LOVRS Load Overrun 1 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only ETRGS External Trigger 7 1 read-only CCR1 Channel Control Register (channel = 1) 0x00000040 32 write-only CLKEN Counter Clock Enable Command 0 1 write-only CLKDIS Counter Clock Disable Command 1 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR1 Channel Mode Register (channel = 1) 0x00000044 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDBDIS Counter Clock Disable with RB Loading 7 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write WAVE 15 1 read-write LDRA RA Loading Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 CMR1_WAVE_EQ_1 Channel Mode Register (channel = 1) WAVE_EQ_1 0x00000044 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 ENETRG External Event Trigger Enable 12 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UP_RC UP mode with automatic trigger on RC Compare 0x1 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 WAVE 15 1 read-write ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 CV1 Counter Value (channel = 1) 0x00000050 32 read-only 0x00000000 CV Counter Value 0 16 read-only RA1 Register A (channel = 1) 0x00000054 32 read-write 0x00000000 RA Register A 0 16 read-write RB1 Register B (channel = 1) 0x00000058 32 read-write 0x00000000 RB Register B 0 16 read-write RC1 Register C (channel = 1) 0x0000005C 32 read-write 0x00000000 RC Register C 0 16 read-write SR1 Status Register (channel = 1) 0x00000060 32 read-only 0x00000000 COVFS Counter Overflow Status 0 1 read-only LOVRS Load Overrun Status 1 1 read-only CPAS RA Compare Status 2 1 read-only CPBS RB Compare Status 3 1 read-only CPCS RC Compare Status 4 1 read-only LDRAS RA Loading Status 5 1 read-only LDRBS RB Loading Status 6 1 read-only ETRGS External Trigger Status 7 1 read-only CLKSTA Clock Enabling Status 16 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only IER1 Interrupt Enable Register (channel = 1) 0x00000064 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IDR1 Interrupt Disable Register (channel = 1) 0x00000068 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IMR1 Interrupt Mask Register (channel = 1) 0x0000006C 32 read-only 0x00000000 COVFS Counter Overflow 0 1 read-only LOVRS Load Overrun 1 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only ETRGS External Trigger 7 1 read-only CCR2 Channel Control Register (channel = 2) 0x00000080 32 write-only CLKEN Counter Clock Enable Command 0 1 write-only CLKDIS Counter Clock Disable Command 1 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR2 Channel Mode Register (channel = 2) 0x00000084 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDBDIS Counter Clock Disable with RB Loading 7 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write WAVE 15 1 read-write LDRA RA Loading Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 CMR2_WAVE_EQ_1 Channel Mode Register (channel = 2) WAVE_EQ_1 0x00000084 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 ENETRG External Event Trigger Enable 12 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UP_RC UP mode with automatic trigger on RC Compare 0x1 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 WAVE 15 1 read-write ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 CV2 Counter Value (channel = 2) 0x00000090 32 read-only 0x00000000 CV Counter Value 0 16 read-only RA2 Register A (channel = 2) 0x00000094 32 read-write 0x00000000 RA Register A 0 16 read-write RB2 Register B (channel = 2) 0x00000098 32 read-write 0x00000000 RB Register B 0 16 read-write RC2 Register C (channel = 2) 0x0000009C 32 read-write 0x00000000 RC Register C 0 16 read-write SR2 Status Register (channel = 2) 0x000000A0 32 read-only 0x00000000 COVFS Counter Overflow Status 0 1 read-only LOVRS Load Overrun Status 1 1 read-only CPAS RA Compare Status 2 1 read-only CPBS RB Compare Status 3 1 read-only CPCS RC Compare Status 4 1 read-only LDRAS RA Loading Status 5 1 read-only LDRBS RB Loading Status 6 1 read-only ETRGS External Trigger Status 7 1 read-only CLKSTA Clock Enabling Status 16 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only IER2 Interrupt Enable Register (channel = 2) 0x000000A4 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IDR2 Interrupt Disable Register (channel = 2) 0x000000A8 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IMR2 Interrupt Mask Register (channel = 2) 0x000000AC 32 read-only 0x00000000 COVFS Counter Overflow 0 1 read-only LOVRS Load Overrun 1 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only ETRGS External Trigger 7 1 read-only BCR Block Control Register 0x000000C0 32 write-only SYNC Synchro Command 0 1 write-only BMR Block Mode Register 0x000000C4 32 read-write 0x00000000 TC0XC0S External Clock Signal 0 Selection 0 2 read-write TCLK0 Signal connected to XC0: TCLK0 0x0 TCLK1 Signal connected to XC0: TCLK1 0x2 TCLK2 Signal connected to XC0: TCLK2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 read-write TCLK0 Signal connected to XC1: TCLK0 0x0 TCLK1 Signal connected to XC1: TCLK1 0x2 TCLK2 Signal connected to XC1: TCLK2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 read-write TCLK0 Signal connected to XC2: TCLK0 0x0 TCLK1 Signal connected to XC2: TCLK1 0x2 TCLK2 Signal connected to XC2: TCLK2 0x3 HSMCI0 6449D High Speed MultiMedia Card Interface 0 HSMCI HSMCI0_ 0xFFF80000 0 0x4000 registers HSMCI0 11 CR Control Register 0x00000000 32 write-only MCIEN Multi-Media Interface Enable 0 1 write-only MCIDIS Multi-Media Interface Disable 1 1 write-only PWSEN Power Save Mode Enable 2 1 write-only PWSDIS Power Save Mode Disable 3 1 write-only SWRST Software Reset 7 1 write-only MR Mode Register 0x00000004 32 read-write 0x00000000 CLKDIV Clock Divider 0 8 read-write PWSDIV Power Saving Divider 8 3 read-write RDPROOF 11 1 read-write WRPROOF 12 1 read-write FBYTE Force Byte Transfer 13 1 read-write PADV Padding Value 14 1 read-write BLKLEN Data Block Length 16 16 read-write DTOR Data Timeout Register 0x00000008 32 read-write 0x00000000 DTOCYC Data Timeout Cycle Number 0 4 read-write DTOMUL Data Timeout Multiplier 4 3 read-write 1 DTOCYC 0x0 16 DTOCYC x 16 0x1 128 DTOCYC x 128 0x2 256 DTOCYC x 256 0x3 1024 DTOCYC x 1024 0x4 4096 DTOCYC x 4096 0x5 65536 DTOCYC x 65536 0x6 1048576 DTOCYC x 1048576 0x7 SDCR SD/SDIO Card Register 0x0000000C 32 read-write 0x00000000 SDCSEL SDCard/SDIO Slot 0 2 read-write SLOTA Slot A is selected. 0x0 SLOTB - 0x1 SLOTC - 0x2 SLOTD - 0x3 SDCBUS SDCard/SDIO Bus Width 6 2 read-write 1 1 bit 0x0 4 4 bit 0x1 8 8 bit 0x2 ARGR Argument Register 0x00000010 32 read-write 0x00000000 ARG Command Argument 0 32 read-write CMDR Command Register 0x00000014 32 write-only CMDNB Command Number 0 6 write-only RSPTYP Response Type 6 2 write-only NORESP No response. 0x0 48_BIT 48-bit response. 0x1 136_BIT 136-bit response. 0x2 R1B R1b response type 0x3 SPCMD Special Command 8 3 write-only STD Not a special CMD. 0x0 INIT Initialization CMD:74 clock cycles for initialization sequence. 0x1 SYNC Synchronized CMD:Wait for the end of the current data block transfer before sending the pending command. 0x2 CE_ATA CE-ATA Completion Signal disable Command.The host cancels the ability for the device to return a command completion signal on the command line. 0x3 IT_CMD Interrupt command:Corresponds to the Interrupt Mode (CMD40). 0x4 IT_RESP Interrupt response:Corresponds to the Interrupt Mode (CMD40). 0x5 BOR Boot Operation Request.Start a boot operation mode, the host processor can read boot data from the MMC device directly. 0x6 EBO End Boot Operation.This command allows the host processor to terminate the boot operation mode. 0x7 OPDCMD Open Drain Command 11 1 write-only PUSHPULL Push pull command. 0 OPENDRAIN Open drain command. 1 MAXLAT Max Latency for Command to Response 12 1 write-only 5 5-cycle max latency. 0 64 64-cycle max latency. 1 TRCMD Transfer Command 16 2 write-only NO_DATA No data transfer 0x0 START_DATA Start data transfer 0x1 STOP_DATA Stop data transfer 0x2 TRDIR Transfer Direction 18 1 write-only WRITE Write. 0 READ Read. 1 TRTYP Transfer Type 19 3 write-only SINGLE MMC/SDCard Single Block 0x0 MULTIPLE MMC/SDCard Multiple Block 0x1 STREAM MMC Stream 0x2 BYTE SDIO Byte 0x4 BLOCK SDIO Block 0x5 IOSPCMD SDIO Special Command 24 2 write-only STD Not an SDIO Special Command 0x0 SUSPEND SDIO Suspend Command 0x1 RESUME SDIO Resume Command 0x2 ATACS ATA with Command Completion Signal 26 1 write-only NORMAL Normal operation mode. 0 COMPLETION This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). 1 BOOT_ACK Boot Operation Acknowledge. 27 1 write-only BLKR Block Register 0x00000018 32 read-write 0x00000000 BCNT MMC/SDIO Block Count - SDIO Byte Count 0 16 read-write MULTIPLE MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. 0x0 BYTE SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. 0x4 BLOCK SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. 0x5 BLKLEN Data Block Length 16 16 read-write CSTOR Completion Signal Timeout Register 0x0000001C 32 read-write 0x00000000 CSTOCYC Completion Signal Timeout Cycle Number 0 4 read-write CSTOMUL Completion Signal Timeout Multiplier 4 3 read-write 1 CSTOCYC x 1 0x0 16 CSTOCYC x 16 0x1 128 CSTOCYC x 128 0x2 256 CSTOCYC x 256 0x3 1024 CSTOCYC x 1024 0x4 4096 CSTOCYC x 4096 0x5 65536 CSTOCYC x 65536 0x6 1048576 CSTOCYC x 1048576 0x7 4 4 0-3 RSPR[%s] Response Register 0x00000020 32 read-only RSP Response 0 32 read-only RDR Receive Data Register 0x00000030 32 read-only 0x00000000 DATA Data to Read 0 32 read-only TDR Transmit Data Register 0x00000034 32 write-only DATA Data to Write 0 32 write-only SR Status Register 0x00000040 32 read-only 0x0000C0E5 CMDRDY Command Ready 0 1 read-only RXRDY Receiver Ready 1 1 read-only TXRDY Transmit Ready 2 1 read-only BLKE Data Block Ended 3 1 read-only DTIP Data Transfer in Progress 4 1 read-only NOTBUSY HSMCI Not Busy 5 1 read-only MCI_SDIOIRQA 8 1 read-only SDIOWAIT SDIO Read Wait Operation Status 12 1 read-only CSRCV CE-ATA Completion Signal Received 13 1 read-only RINDE Response Index Error 16 1 read-only RDIRE Response Direction Error 17 1 read-only RCRCE Response CRC Error 18 1 read-only RENDE Response End Bit Error 19 1 read-only RTOE Response Time-out Error 20 1 read-only DCRCE Data CRC Error 21 1 read-only DTOE Data Time-out Error 22 1 read-only CSTOE Completion Signal Time-out Error 23 1 read-only BLKOVRE DMA Block Overrun Error 24 1 read-only DMADONE DMA Transfer done 25 1 read-only FIFOEMPTY FIFO empty flag 26 1 read-only XFRDONE Transfer Done flag 27 1 read-only ACKRCV Boot Operation Acknowledge Received 28 1 read-only ACKRCVE Boot Operation Acknowledge Error 29 1 read-only OVRE Overrun 30 1 read-only UNRE Underrun 31 1 read-only IER Interrupt Enable Register 0x00000044 32 write-only CMDRDY Command Ready Interrupt Enable 0 1 write-only RXRDY Receiver Ready Interrupt Enable 1 1 write-only TXRDY Transmit Ready Interrupt Enable 2 1 write-only BLKE Data Block Ended Interrupt Enable 3 1 write-only DTIP Data Transfer in Progress Interrupt Enable 4 1 write-only NOTBUSY Data Not Busy Interrupt Enable 5 1 write-only MCI_SDIOIRQA 8 1 write-only SDIOWAIT SDIO Read Wait Operation Status Interrupt Enable 12 1 write-only CSRCV Completion Signal Received Interrupt Enable 13 1 write-only RINDE Response Index Error Interrupt Enable 16 1 write-only RDIRE Response Direction Error Interrupt Enable 17 1 write-only RCRCE Response CRC Error Interrupt Enable 18 1 write-only RENDE Response End Bit Error Interrupt Enable 19 1 write-only RTOE Response Time-out Error Interrupt Enable 20 1 write-only DCRCE Data CRC Error Interrupt Enable 21 1 write-only DTOE Data Time-out Error Interrupt Enable 22 1 write-only CSTOE Completion Signal Timeout Error Interrupt Enable 23 1 write-only BLKOVRE DMA Block Overrun Error Interrupt Enable 24 1 write-only DMADONE DMA Transfer completed Interrupt Enable 25 1 write-only FIFOEMPTY FIFO empty Interrupt enable 26 1 write-only XFRDONE Transfer Done Interrupt enable 27 1 write-only ACKRCV Boot Acknowledge Interrupt Enable 28 1 write-only ACKRCVE Boot Acknowledge Error Interrupt Enable 29 1 write-only OVRE Overrun Interrupt Enable 30 1 write-only UNRE Underrun Interrupt Enable 31 1 write-only IDR Interrupt Disable Register 0x00000048 32 write-only CMDRDY Command Ready Interrupt Disable 0 1 write-only RXRDY Receiver Ready Interrupt Disable 1 1 write-only TXRDY Transmit Ready Interrupt Disable 2 1 write-only BLKE Data Block Ended Interrupt Disable 3 1 write-only DTIP Data Transfer in Progress Interrupt Disable 4 1 write-only NOTBUSY Data Not Busy Interrupt Disable 5 1 write-only MCI_SDIOIRQA 8 1 write-only SDIOWAIT SDIO Read Wait Operation Status Interrupt Disable 12 1 write-only CSRCV Completion Signal received interrupt Disable 13 1 write-only RINDE Response Index Error Interrupt Disable 16 1 write-only RDIRE Response Direction Error Interrupt Disable 17 1 write-only RCRCE Response CRC Error Interrupt Disable 18 1 write-only RENDE Response End Bit Error Interrupt Disable 19 1 write-only RTOE Response Time-out Error Interrupt Disable 20 1 write-only DCRCE Data CRC Error Interrupt Disable 21 1 write-only DTOE Data Time-out Error Interrupt Disable 22 1 write-only CSTOE Completion Signal Time out Error Interrupt Disable 23 1 write-only BLKOVRE DMA Block Overrun Error Interrupt Disable 24 1 write-only DMADONE DMA Transfer completed Interrupt Disable 25 1 write-only FIFOEMPTY FIFO empty Interrupt Disable 26 1 write-only XFRDONE Transfer Done Interrupt Disable 27 1 write-only ACKRCV Boot Acknowledge Interrupt Disable 28 1 write-only ACKRCVE Boot Acknowledge Error Interrupt Disable 29 1 write-only OVRE Overrun Interrupt Disable 30 1 write-only UNRE Underrun Interrupt Disable 31 1 write-only IMR Interrupt Mask Register 0x0000004C 32 read-only 0x00000000 CMDRDY Command Ready Interrupt Mask 0 1 read-only RXRDY Receiver Ready Interrupt Mask 1 1 read-only TXRDY Transmit Ready Interrupt Mask 2 1 read-only BLKE Data Block Ended Interrupt Mask 3 1 read-only DTIP Data Transfer in Progress Interrupt Mask 4 1 read-only NOTBUSY Data Not Busy Interrupt Mask 5 1 read-only MCI_SDIOIRQA 8 1 read-only SDIOWAIT SDIO Read Wait Operation Status Interrupt Mask 12 1 read-only CSRCV Completion Signal Received Interrupt Mask 13 1 read-only RINDE Response Index Error Interrupt Mask 16 1 read-only RDIRE Response Direction Error Interrupt Mask 17 1 read-only RCRCE Response CRC Error Interrupt Mask 18 1 read-only RENDE Response End Bit Error Interrupt Mask 19 1 read-only RTOE Response Time-out Error Interrupt Mask 20 1 read-only DCRCE Data CRC Error Interrupt Mask 21 1 read-only DTOE Data Time-out Error Interrupt Mask 22 1 read-only CSTOE Completion Signal Time-out Error Interrupt Mask 23 1 read-only BLKOVRE DMA Block Overrun Error Interrupt Mask 24 1 read-only DMADONE DMA Transfer Completed Interrupt Mask 25 1 read-only FIFOEMPTY FIFO Empty Interrupt Mask 26 1 read-only XFRDONE Transfer Done Interrupt Mask 27 1 read-only ACKRCV Boot Operation Acknowledge Received Interrupt Mask 28 1 read-only ACKRCVE Boot Operation Acknowledge Error Interrupt Mask 29 1 read-only OVRE Overrun Interrupt Mask 30 1 read-only UNRE Underrun Interrupt Mask 31 1 read-only DMA DMA Configuration Register 0x00000050 32 read-write 0x00000000 OFFSET DMA Write Buffer Offset 0 2 read-write CHKSIZE DMA Channel Read and Write Chunk Size 4 2 read-write 1 1 data available 0x0 4 4 data available 0x1 8 8 data available 0x2 16 16 data available 0x3 DMAEN DMA Hardware Handshaking Enable 8 1 read-write ROPT Read Optimization with padding 12 1 read-write CFG Configuration Register 0x00000054 32 read-write 0x00000000 FIFOMODE HSMCI Internal FIFO control mode 0 1 read-write FERRCTRL Flow Error flag reset control mode 4 1 read-write HSMODE High Speed Mode 8 1 read-write LSYNC Synchronize on the last block 12 1 read-write WPMR Write Protection Mode Register 0x000000E4 32 read-write WP_EN Write Protection Enable 0 1 read-write WP_KEY Write Protection Key password 8 24 read-write WPSR Write Protection Status Register 0x000000E8 32 read-only WP_VS Write Protection Violation Status 0 4 read-only NONE No Write Protection Violation occurred since the last read of this register (WP_SR) 0x0 WRITE Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) 0x1 RESET Software reset had been performed while Write Protection was enabled (since the last read). 0x2 BOTH Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. 0x3 WP_VSRC Write Protection Violation SouRCe 8 16 read-only TWI0 6212J Two-wire Interface 0 TWI TWI0_ 0xFFF84000 0 0x4000 registers TWI0 12 CR Control Register 0x00000000 32 write-only START Send a START Condition 0 1 write-only STOP Send a STOP Condition 1 1 write-only MSEN TWI Master Mode Enabled 2 1 write-only MSDIS TWI Master Mode Disabled 3 1 write-only SVEN TWI Slave Mode Enabled 4 1 write-only SVDIS TWI Slave Mode Disabled 5 1 write-only QUICK SMBUS Quick Command 6 1 write-only SWRST Software Reset 7 1 write-only MMR Master Mode Register 0x00000004 32 read-write 0x00000000 IADRSZ Internal Device Address Size 8 2 read-write NONE No internal device address 0x0 1_BYTE One-byte internal device address 0x1 2_BYTE Two-byte internal device address 0x2 3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 read-write DADR Device Address 16 7 read-write SMR Slave Mode Register 0x00000008 32 read-write 0x00000000 SADR Slave Address 16 7 read-write IADR Internal Address Register 0x0000000C 32 read-write 0x00000000 IADR Internal Address 0 24 read-write CWGR Clock Waveform Generator Register 0x00000010 32 read-write 0x00000000 CLDIV Clock Low Divider 0 8 read-write CHDIV Clock High Divider 8 8 read-write CKDIV Clock Divider 16 3 read-write SR Status Register 0x00000020 32 read-only 0x0000F009 TXCOMP Transmission Completed (automatically set / reset) 0 1 read-only RXRDY Receive Holding Register Ready (automatically set / reset) 1 1 read-only TXRDY Transmit Holding Register Ready (automatically set / reset) 2 1 read-only SVREAD Slave Read (automatically set / reset) 3 1 read-only SVACC Slave Access (automatically set / reset) 4 1 read-only GACC General Call Access (clear on read) 5 1 read-only OVRE Overrun Error (clear on read) 6 1 read-only NACK Not Acknowledged (clear on read) 8 1 read-only ARBLST Arbitration Lost (clear on read) 9 1 read-only SCLWS Clock Wait State (automatically set / reset) 10 1 read-only EOSACC End Of Slave Access (clear on read) 11 1 read-only IER Interrupt Enable Register 0x00000024 32 write-only TXCOMP Transmission Completed Interrupt Enable 0 1 write-only RXRDY Receive Holding Register Ready Interrupt Enable 1 1 write-only TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 write-only SVACC Slave Access Interrupt Enable 4 1 write-only GACC General Call Access Interrupt Enable 5 1 write-only OVRE Overrun Error Interrupt Enable 6 1 write-only NACK Not Acknowledge Interrupt Enable 8 1 write-only ARBLST Arbitration Lost Interrupt Enable 9 1 write-only SCL_WS Clock Wait State Interrupt Enable 10 1 write-only EOSACC End Of Slave Access Interrupt Enable 11 1 write-only IDR Interrupt Disable Register 0x00000028 32 write-only TXCOMP Transmission Completed Interrupt Disable 0 1 write-only RXRDY Receive Holding Register Ready Interrupt Disable 1 1 write-only TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 write-only SVACC Slave Access Interrupt Disable 4 1 write-only GACC General Call Access Interrupt Disable 5 1 write-only OVRE Overrun Error Interrupt Disable 6 1 write-only NACK Not Acknowledge Interrupt Disable 8 1 write-only ARBLST Arbitration Lost Interrupt Disable 9 1 write-only SCL_WS Clock Wait State Interrupt Disable 10 1 write-only EOSACC End Of Slave Access Interrupt Disable 11 1 write-only IMR Interrupt Mask Register 0x0000002C 32 read-only 0x00000000 TXCOMP Transmission Completed Interrupt Mask 0 1 read-only RXRDY Receive Holding Register Ready Interrupt Mask 1 1 read-only TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 read-only SVACC Slave Access Interrupt Mask 4 1 read-only GACC General Call Access Interrupt Mask 5 1 read-only OVRE Overrun Error Interrupt Mask 6 1 read-only NACK Not Acknowledge Interrupt Mask 8 1 read-only ARBLST Arbitration Lost Interrupt Mask 9 1 read-only SCL_WS Clock Wait State Interrupt Mask 10 1 read-only EOSACC End Of Slave Access Interrupt Mask 11 1 read-only RHR Receive Holding Register 0x00000030 32 read-only 0x00000000 RXDATA Master or Slave Receive Holding Data 0 8 read-only THR Transmit Holding Register 0x00000034 32 write-only 0x00000000 TXDATA Master or Slave Transmit Holding Data 0 8 write-only TWI1 6212J Two-wire Interface 1 TWI TWI1_ 0xFFF88000 0 0x4000 registers TWI1 13 CR Control Register 0x00000000 32 write-only START Send a START Condition 0 1 write-only STOP Send a STOP Condition 1 1 write-only MSEN TWI Master Mode Enabled 2 1 write-only MSDIS TWI Master Mode Disabled 3 1 write-only SVEN TWI Slave Mode Enabled 4 1 write-only SVDIS TWI Slave Mode Disabled 5 1 write-only QUICK SMBUS Quick Command 6 1 write-only SWRST Software Reset 7 1 write-only MMR Master Mode Register 0x00000004 32 read-write 0x00000000 IADRSZ Internal Device Address Size 8 2 read-write NONE No internal device address 0x0 1_BYTE One-byte internal device address 0x1 2_BYTE Two-byte internal device address 0x2 3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 read-write DADR Device Address 16 7 read-write SMR Slave Mode Register 0x00000008 32 read-write 0x00000000 SADR Slave Address 16 7 read-write IADR Internal Address Register 0x0000000C 32 read-write 0x00000000 IADR Internal Address 0 24 read-write CWGR Clock Waveform Generator Register 0x00000010 32 read-write 0x00000000 CLDIV Clock Low Divider 0 8 read-write CHDIV Clock High Divider 8 8 read-write CKDIV Clock Divider 16 3 read-write SR Status Register 0x00000020 32 read-only 0x0000F009 TXCOMP Transmission Completed (automatically set / reset) 0 1 read-only RXRDY Receive Holding Register Ready (automatically set / reset) 1 1 read-only TXRDY Transmit Holding Register Ready (automatically set / reset) 2 1 read-only SVREAD Slave Read (automatically set / reset) 3 1 read-only SVACC Slave Access (automatically set / reset) 4 1 read-only GACC General Call Access (clear on read) 5 1 read-only OVRE Overrun Error (clear on read) 6 1 read-only NACK Not Acknowledged (clear on read) 8 1 read-only ARBLST Arbitration Lost (clear on read) 9 1 read-only SCLWS Clock Wait State (automatically set / reset) 10 1 read-only EOSACC End Of Slave Access (clear on read) 11 1 read-only IER Interrupt Enable Register 0x00000024 32 write-only TXCOMP Transmission Completed Interrupt Enable 0 1 write-only RXRDY Receive Holding Register Ready Interrupt Enable 1 1 write-only TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 write-only SVACC Slave Access Interrupt Enable 4 1 write-only GACC General Call Access Interrupt Enable 5 1 write-only OVRE Overrun Error Interrupt Enable 6 1 write-only NACK Not Acknowledge Interrupt Enable 8 1 write-only ARBLST Arbitration Lost Interrupt Enable 9 1 write-only SCL_WS Clock Wait State Interrupt Enable 10 1 write-only EOSACC End Of Slave Access Interrupt Enable 11 1 write-only IDR Interrupt Disable Register 0x00000028 32 write-only TXCOMP Transmission Completed Interrupt Disable 0 1 write-only RXRDY Receive Holding Register Ready Interrupt Disable 1 1 write-only TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 write-only SVACC Slave Access Interrupt Disable 4 1 write-only GACC General Call Access Interrupt Disable 5 1 write-only OVRE Overrun Error Interrupt Disable 6 1 write-only NACK Not Acknowledge Interrupt Disable 8 1 write-only ARBLST Arbitration Lost Interrupt Disable 9 1 write-only SCL_WS Clock Wait State Interrupt Disable 10 1 write-only EOSACC End Of Slave Access Interrupt Disable 11 1 write-only IMR Interrupt Mask Register 0x0000002C 32 read-only 0x00000000 TXCOMP Transmission Completed Interrupt Mask 0 1 read-only RXRDY Receive Holding Register Ready Interrupt Mask 1 1 read-only TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 read-only SVACC Slave Access Interrupt Mask 4 1 read-only GACC General Call Access Interrupt Mask 5 1 read-only OVRE Overrun Error Interrupt Mask 6 1 read-only NACK Not Acknowledge Interrupt Mask 8 1 read-only ARBLST Arbitration Lost Interrupt Mask 9 1 read-only SCL_WS Clock Wait State Interrupt Mask 10 1 read-only EOSACC End Of Slave Access Interrupt Mask 11 1 read-only RHR Receive Holding Register 0x00000030 32 read-only 0x00000000 RXDATA Master or Slave Receive Holding Data 0 8 read-only THR Transmit Holding Register 0x00000034 32 write-only 0x00000000 TXDATA Master or Slave Transmit Holding Data 0 8 write-only USART0 6089Z Universal Synchronous Asynchronous Receiver Transmitter 0 USART USART0_ 0xFFF8C000 0 0x4000 registers USART0 7 CR Control Register 0x00000000 32 write-only RSTRX Reset Receiver 2 1 write-only RSTTX Reset Transmitter 3 1 write-only RXEN Receiver Enable 4 1 write-only RXDIS Receiver Disable 5 1 write-only TXEN Transmitter Enable 6 1 write-only TXDIS Transmitter Disable 7 1 write-only RSTSTA Reset Status Bits 8 1 write-only STTBRK Start Break 9 1 write-only STPBRK Stop Break 10 1 write-only STTTO Start Time-out 11 1 write-only SENDA Send Address 12 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RETTO Rearm Time-out 15 1 write-only RTSEN Request to Send Enable 18 1 write-only RTSDIS Request to Send Disable 19 1 write-only CR_SPI_MODE Control Register SPI_MODE 0x00000000 32 write-only RSTRX Reset Receiver 2 1 write-only RSTTX Reset Transmitter 3 1 write-only RXEN Receiver Enable 4 1 write-only RXDIS Receiver Disable 5 1 write-only TXEN Transmitter Enable 6 1 write-only TXDIS Transmitter Disable 7 1 write-only RSTSTA Reset Status Bits 8 1 write-only FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only MR Mode Register 0x00000004 32 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 SPI_MASTER SPI Master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK Master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 CHRL Character Length. 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 SYNC Synchronous Mode Select 8 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 CHMODE Channel Mode 14 2 read-write NORMAL Normal Mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 MSBF Bit Order 16 1 read-write MODE9 9-bit Character Length 17 1 read-write CLKO Clock Output Select 18 1 read-write OVER Oversampling Mode 19 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write DSNACK Disable Successive NACK 21 1 read-write VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write FILTER Infrared Receive Line Filter 28 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write ONEBIT Start Frame Delimiter Selector 31 1 read-write MR_SPI_MODE Mode Register SPI_MODE 0x00000004 32 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI Master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK Master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 CHRL Character Length. 6 2 read-write 8_BIT Character length is 8 bits 0x3 CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write WRDBT Wait Read Data Before Transfer 20 1 read-write IER Interrupt Enable Register 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only ENDRX End of Receive Transfer Interrupt Enable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Enable (available in all USART modes of operation) 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only TXBUFE Buffer Empty Interrupt Enable (available in all USART modes of operation) 11 1 write-only RXBUFF Buffer Full Interrupt Enable (available in all USART modes of operation) 12 1 write-only NACK Non AcknowledgeInterrupt Enable 13 1 write-only CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only IER_SPI_MODE Interrupt Enable Register SPI_MODE 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only IDR Interrupt Disable Register 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only ENDRX End of Receive Transfer Interrupt Disable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Disable (available in all USART modes of operation) 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only TXBUFE Buffer Empty Interrupt Disable (available in all USART modes of operation) 11 1 write-only RXBUFF Buffer Full Interrupt Disable (available in all USART modes of operation) 12 1 write-only NACK Non AcknowledgeInterrupt Disable 13 1 write-only CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only IDR_SPI_MODE Interrupt Disable Register SPI_MODE 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only IMR Interrupt Mask Register 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only ENDRX End of Receive Transfer Interrupt Mask (available in all USART modes of operation) 3 1 read-only ENDTX End of Transmit Interrupt Mask (available in all USART modes of operation) 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only TXBUFE Buffer Empty Interrupt Mask (available in all USART modes of operation) 11 1 read-only RXBUFF Buffer Full Interrupt Mask (available in all USART modes of operation) 12 1 read-only NACK Non AcknowledgeInterrupt Mask 13 1 read-only CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only IMR_SPI_MODE Interrupt Mask Register SPI_MODE 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only CSR Channel Status Register 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only RXBRK Break Received/End of Break 2 1 read-only ENDRX End of Receiver Transfer 3 1 read-only ENDTX End of Transmitter Transfer 4 1 read-only OVRE Overrun Error 5 1 read-only FRAME Framing Error 6 1 read-only PARE Parity Error 7 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXEMPTY Transmitter Empty 9 1 read-only ITER MaxNumber of Repetitions Reached 10 1 read-only TXBUFE Transmission Buffer Empty 11 1 read-only RXBUFF Reception Buffer Full 12 1 read-only NACK Non AcknowledgeInterrupt 13 1 read-only CTSIC Clear to Send Input Change Flag 19 1 read-only CTS Image of CTS Input 23 1 read-only MANERR Manchester Error 24 1 read-only CSR_SPI_MODE Channel Status Register SPI_MODE 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only OVRE Overrun Error 5 1 read-only TXEMPTY Transmitter Empty 9 1 read-only UNRE Underrun Error 10 1 read-only RHR Receiver Holding Register 0x00000018 32 read-only 0x00000000 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only THR Transmitter Holding Register 0x0000001C 32 write-only TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only BRGR Baud Rate Generator Register 0x00000020 32 read-write 0x00000000 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write RTOR Receiver Time-out Register 0x00000024 32 read-write 0x00000000 TO Time-out Value 0 16 read-write TTGR Transmitter Timeguard Register 0x00000028 32 read-write 0x00000000 TG Timeguard Value 0 8 read-write FIDI FI DI Ratio Register 0x00000040 32 read-write 0x00000174 FI_DI_RATIO FI Over DI Ratio Value 0 11 read-write NER Number of Errors Register 0x00000044 32 read-only NB_ERRORS Number of Errors 0 8 read-only IF IrDA Filter Register 0x0000004C 32 read-write 0x00000000 IRDA_FILTER IrDA Filter 0 8 read-write MAN Manchester Encoder Decoder Register 0x00000050 32 read-write 0xB0011004 TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 RX_MPOL Receiver Manchester Polarity 28 1 read-write ONE Must Be Set to 1 29 1 read-write DRIFT Drift Compensation 30 1 read-write RPR Receive Pointer Register 0x00000100 32 read-write 0x00000000 RXPTR Receive Pointer Register 0 32 read-write RCR Receive Counter Register 0x00000104 32 read-write 0x00000000 RXCTR Receive Counter Register 0 16 read-write TPR Transmit Pointer Register 0x00000108 32 read-write 0x00000000 TXPTR Transmit Counter Register 0 32 read-write TCR Transmit Counter Register 0x0000010C 32 read-write 0x00000000 TXCTR Transmit Counter Register 0 16 read-write RNPR Receive Next Pointer Register 0x00000110 32 read-write 0x00000000 RXNPTR Receive Next Pointer 0 32 read-write RNCR Receive Next Counter Register 0x00000114 32 read-write 0x00000000 RXNCTR Receive Next Counter 0 16 read-write TNPR Transmit Next Pointer Register 0x00000118 32 read-write 0x00000000 TXNPTR Transmit Next Pointer 0 32 read-write TNCR Transmit Next Counter Register 0x0000011C 32 read-write 0x00000000 TXNCTR Transmit Counter Next 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only USART1 6089Z Universal Synchronous Asynchronous Receiver Transmitter 1 USART USART1_ 0xFFF90000 0 0x4000 registers USART1 8 CR Control Register 0x00000000 32 write-only RSTRX Reset Receiver 2 1 write-only RSTTX Reset Transmitter 3 1 write-only RXEN Receiver Enable 4 1 write-only RXDIS Receiver Disable 5 1 write-only TXEN Transmitter Enable 6 1 write-only TXDIS Transmitter Disable 7 1 write-only RSTSTA Reset Status Bits 8 1 write-only STTBRK Start Break 9 1 write-only STPBRK Stop Break 10 1 write-only STTTO Start Time-out 11 1 write-only SENDA Send Address 12 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RETTO Rearm Time-out 15 1 write-only RTSEN Request to Send Enable 18 1 write-only RTSDIS Request to Send Disable 19 1 write-only CR_SPI_MODE Control Register SPI_MODE 0x00000000 32 write-only RSTRX Reset Receiver 2 1 write-only RSTTX Reset Transmitter 3 1 write-only RXEN Receiver Enable 4 1 write-only RXDIS Receiver Disable 5 1 write-only TXEN Transmitter Enable 6 1 write-only TXDIS Transmitter Disable 7 1 write-only RSTSTA Reset Status Bits 8 1 write-only FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only MR Mode Register 0x00000004 32 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 SPI_MASTER SPI Master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK Master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 CHRL Character Length. 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 SYNC Synchronous Mode Select 8 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 CHMODE Channel Mode 14 2 read-write NORMAL Normal Mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 MSBF Bit Order 16 1 read-write MODE9 9-bit Character Length 17 1 read-write CLKO Clock Output Select 18 1 read-write OVER Oversampling Mode 19 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write DSNACK Disable Successive NACK 21 1 read-write VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write FILTER Infrared Receive Line Filter 28 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write ONEBIT Start Frame Delimiter Selector 31 1 read-write MR_SPI_MODE Mode Register SPI_MODE 0x00000004 32 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI Master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK Master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 CHRL Character Length. 6 2 read-write 8_BIT Character length is 8 bits 0x3 CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write WRDBT Wait Read Data Before Transfer 20 1 read-write IER Interrupt Enable Register 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only ENDRX End of Receive Transfer Interrupt Enable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Enable (available in all USART modes of operation) 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only TXBUFE Buffer Empty Interrupt Enable (available in all USART modes of operation) 11 1 write-only RXBUFF Buffer Full Interrupt Enable (available in all USART modes of operation) 12 1 write-only NACK Non AcknowledgeInterrupt Enable 13 1 write-only CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only IER_SPI_MODE Interrupt Enable Register SPI_MODE 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only IDR Interrupt Disable Register 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only ENDRX End of Receive Transfer Interrupt Disable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Disable (available in all USART modes of operation) 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only TXBUFE Buffer Empty Interrupt Disable (available in all USART modes of operation) 11 1 write-only RXBUFF Buffer Full Interrupt Disable (available in all USART modes of operation) 12 1 write-only NACK Non AcknowledgeInterrupt Disable 13 1 write-only CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only IDR_SPI_MODE Interrupt Disable Register SPI_MODE 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only IMR Interrupt Mask Register 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only ENDRX End of Receive Transfer Interrupt Mask (available in all USART modes of operation) 3 1 read-only ENDTX End of Transmit Interrupt Mask (available in all USART modes of operation) 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only TXBUFE Buffer Empty Interrupt Mask (available in all USART modes of operation) 11 1 read-only RXBUFF Buffer Full Interrupt Mask (available in all USART modes of operation) 12 1 read-only NACK Non AcknowledgeInterrupt Mask 13 1 read-only CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only IMR_SPI_MODE Interrupt Mask Register SPI_MODE 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only CSR Channel Status Register 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only RXBRK Break Received/End of Break 2 1 read-only ENDRX End of Receiver Transfer 3 1 read-only ENDTX End of Transmitter Transfer 4 1 read-only OVRE Overrun Error 5 1 read-only FRAME Framing Error 6 1 read-only PARE Parity Error 7 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXEMPTY Transmitter Empty 9 1 read-only ITER MaxNumber of Repetitions Reached 10 1 read-only TXBUFE Transmission Buffer Empty 11 1 read-only RXBUFF Reception Buffer Full 12 1 read-only NACK Non AcknowledgeInterrupt 13 1 read-only CTSIC Clear to Send Input Change Flag 19 1 read-only CTS Image of CTS Input 23 1 read-only MANERR Manchester Error 24 1 read-only CSR_SPI_MODE Channel Status Register SPI_MODE 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only OVRE Overrun Error 5 1 read-only TXEMPTY Transmitter Empty 9 1 read-only UNRE Underrun Error 10 1 read-only RHR Receiver Holding Register 0x00000018 32 read-only 0x00000000 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only THR Transmitter Holding Register 0x0000001C 32 write-only TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only BRGR Baud Rate Generator Register 0x00000020 32 read-write 0x00000000 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write RTOR Receiver Time-out Register 0x00000024 32 read-write 0x00000000 TO Time-out Value 0 16 read-write TTGR Transmitter Timeguard Register 0x00000028 32 read-write 0x00000000 TG Timeguard Value 0 8 read-write FIDI FI DI Ratio Register 0x00000040 32 read-write 0x00000174 FI_DI_RATIO FI Over DI Ratio Value 0 11 read-write NER Number of Errors Register 0x00000044 32 read-only NB_ERRORS Number of Errors 0 8 read-only IF IrDA Filter Register 0x0000004C 32 read-write 0x00000000 IRDA_FILTER IrDA Filter 0 8 read-write MAN Manchester Encoder Decoder Register 0x00000050 32 read-write 0xB0011004 TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 RX_MPOL Receiver Manchester Polarity 28 1 read-write ONE Must Be Set to 1 29 1 read-write DRIFT Drift Compensation 30 1 read-write RPR Receive Pointer Register 0x00000100 32 read-write 0x00000000 RXPTR Receive Pointer Register 0 32 read-write RCR Receive Counter Register 0x00000104 32 read-write 0x00000000 RXCTR Receive Counter Register 0 16 read-write TPR Transmit Pointer Register 0x00000108 32 read-write 0x00000000 TXPTR Transmit Counter Register 0 32 read-write TCR Transmit Counter Register 0x0000010C 32 read-write 0x00000000 TXCTR Transmit Counter Register 0 16 read-write RNPR Receive Next Pointer Register 0x00000110 32 read-write 0x00000000 RXNPTR Receive Next Pointer 0 32 read-write RNCR Receive Next Counter Register 0x00000114 32 read-write 0x00000000 RXNCTR Receive Next Counter 0 16 read-write TNPR Transmit Next Pointer Register 0x00000118 32 read-write 0x00000000 TXNPTR Transmit Next Pointer 0 32 read-write TNCR Transmit Next Counter Register 0x0000011C 32 read-write 0x00000000 TXNCTR Transmit Counter Next 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only USART2 6089Z Universal Synchronous Asynchronous Receiver Transmitter 2 USART USART2_ 0xFFF94000 0 0x4000 registers USART2 9 CR Control Register 0x00000000 32 write-only RSTRX Reset Receiver 2 1 write-only RSTTX Reset Transmitter 3 1 write-only RXEN Receiver Enable 4 1 write-only RXDIS Receiver Disable 5 1 write-only TXEN Transmitter Enable 6 1 write-only TXDIS Transmitter Disable 7 1 write-only RSTSTA Reset Status Bits 8 1 write-only STTBRK Start Break 9 1 write-only STPBRK Stop Break 10 1 write-only STTTO Start Time-out 11 1 write-only SENDA Send Address 12 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RETTO Rearm Time-out 15 1 write-only RTSEN Request to Send Enable 18 1 write-only RTSDIS Request to Send Disable 19 1 write-only CR_SPI_MODE Control Register SPI_MODE 0x00000000 32 write-only RSTRX Reset Receiver 2 1 write-only RSTTX Reset Transmitter 3 1 write-only RXEN Receiver Enable 4 1 write-only RXDIS Receiver Disable 5 1 write-only TXEN Transmitter Enable 6 1 write-only TXDIS Transmitter Disable 7 1 write-only RSTSTA Reset Status Bits 8 1 write-only FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only MR Mode Register 0x00000004 32 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 SPI_MASTER SPI Master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK Master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 CHRL Character Length. 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 SYNC Synchronous Mode Select 8 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 CHMODE Channel Mode 14 2 read-write NORMAL Normal Mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 MSBF Bit Order 16 1 read-write MODE9 9-bit Character Length 17 1 read-write CLKO Clock Output Select 18 1 read-write OVER Oversampling Mode 19 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write DSNACK Disable Successive NACK 21 1 read-write VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write FILTER Infrared Receive Line Filter 28 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write ONEBIT Start Frame Delimiter Selector 31 1 read-write MR_SPI_MODE Mode Register SPI_MODE 0x00000004 32 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI Master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK Master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 CHRL Character Length. 6 2 read-write 8_BIT Character length is 8 bits 0x3 CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write WRDBT Wait Read Data Before Transfer 20 1 read-write IER Interrupt Enable Register 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only ENDRX End of Receive Transfer Interrupt Enable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Enable (available in all USART modes of operation) 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only TXBUFE Buffer Empty Interrupt Enable (available in all USART modes of operation) 11 1 write-only RXBUFF Buffer Full Interrupt Enable (available in all USART modes of operation) 12 1 write-only NACK Non AcknowledgeInterrupt Enable 13 1 write-only CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only IER_SPI_MODE Interrupt Enable Register SPI_MODE 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only IDR Interrupt Disable Register 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only ENDRX End of Receive Transfer Interrupt Disable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Disable (available in all USART modes of operation) 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only TXBUFE Buffer Empty Interrupt Disable (available in all USART modes of operation) 11 1 write-only RXBUFF Buffer Full Interrupt Disable (available in all USART modes of operation) 12 1 write-only NACK Non AcknowledgeInterrupt Disable 13 1 write-only CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only IDR_SPI_MODE Interrupt Disable Register SPI_MODE 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only IMR Interrupt Mask Register 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only ENDRX End of Receive Transfer Interrupt Mask (available in all USART modes of operation) 3 1 read-only ENDTX End of Transmit Interrupt Mask (available in all USART modes of operation) 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only TXBUFE Buffer Empty Interrupt Mask (available in all USART modes of operation) 11 1 read-only RXBUFF Buffer Full Interrupt Mask (available in all USART modes of operation) 12 1 read-only NACK Non AcknowledgeInterrupt Mask 13 1 read-only CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only IMR_SPI_MODE Interrupt Mask Register SPI_MODE 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only CSR Channel Status Register 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only RXBRK Break Received/End of Break 2 1 read-only ENDRX End of Receiver Transfer 3 1 read-only ENDTX End of Transmitter Transfer 4 1 read-only OVRE Overrun Error 5 1 read-only FRAME Framing Error 6 1 read-only PARE Parity Error 7 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXEMPTY Transmitter Empty 9 1 read-only ITER MaxNumber of Repetitions Reached 10 1 read-only TXBUFE Transmission Buffer Empty 11 1 read-only RXBUFF Reception Buffer Full 12 1 read-only NACK Non AcknowledgeInterrupt 13 1 read-only CTSIC Clear to Send Input Change Flag 19 1 read-only CTS Image of CTS Input 23 1 read-only MANERR Manchester Error 24 1 read-only CSR_SPI_MODE Channel Status Register SPI_MODE 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only OVRE Overrun Error 5 1 read-only TXEMPTY Transmitter Empty 9 1 read-only UNRE Underrun Error 10 1 read-only RHR Receiver Holding Register 0x00000018 32 read-only 0x00000000 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only THR Transmitter Holding Register 0x0000001C 32 write-only TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only BRGR Baud Rate Generator Register 0x00000020 32 read-write 0x00000000 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write RTOR Receiver Time-out Register 0x00000024 32 read-write 0x00000000 TO Time-out Value 0 16 read-write TTGR Transmitter Timeguard Register 0x00000028 32 read-write 0x00000000 TG Timeguard Value 0 8 read-write FIDI FI DI Ratio Register 0x00000040 32 read-write 0x00000174 FI_DI_RATIO FI Over DI Ratio Value 0 11 read-write NER Number of Errors Register 0x00000044 32 read-only NB_ERRORS Number of Errors 0 8 read-only IF IrDA Filter Register 0x0000004C 32 read-write 0x00000000 IRDA_FILTER IrDA Filter 0 8 read-write MAN Manchester Encoder Decoder Register 0x00000050 32 read-write 0xB0011004 TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 RX_MPOL Receiver Manchester Polarity 28 1 read-write ONE Must Be Set to 1 29 1 read-write DRIFT Drift Compensation 30 1 read-write RPR Receive Pointer Register 0x00000100 32 read-write 0x00000000 RXPTR Receive Pointer Register 0 32 read-write RCR Receive Counter Register 0x00000104 32 read-write 0x00000000 RXCTR Receive Counter Register 0 16 read-write TPR Transmit Pointer Register 0x00000108 32 read-write 0x00000000 TXPTR Transmit Counter Register 0 32 read-write TCR Transmit Counter Register 0x0000010C 32 read-write 0x00000000 TXCTR Transmit Counter Register 0 16 read-write RNPR Receive Next Pointer Register 0x00000110 32 read-write 0x00000000 RXNPTR Receive Next Pointer 0 32 read-write RNCR Receive Next Counter Register 0x00000114 32 read-write 0x00000000 RXNCTR Receive Next Counter 0 16 read-write TNPR Transmit Next Pointer Register 0x00000118 32 read-write 0x00000000 TXNPTR Transmit Next Pointer 0 32 read-write TNCR Transmit Next Counter Register 0x0000011C 32 read-write 0x00000000 TXNCTR Transmit Counter Next 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only USART3 6089Z Universal Synchronous Asynchronous Receiver Transmitter 3 USART USART3_ 0xFFF98000 0 0x4000 registers USART3 10 CR Control Register 0x00000000 32 write-only RSTRX Reset Receiver 2 1 write-only RSTTX Reset Transmitter 3 1 write-only RXEN Receiver Enable 4 1 write-only RXDIS Receiver Disable 5 1 write-only TXEN Transmitter Enable 6 1 write-only TXDIS Transmitter Disable 7 1 write-only RSTSTA Reset Status Bits 8 1 write-only STTBRK Start Break 9 1 write-only STPBRK Stop Break 10 1 write-only STTTO Start Time-out 11 1 write-only SENDA Send Address 12 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RETTO Rearm Time-out 15 1 write-only RTSEN Request to Send Enable 18 1 write-only RTSDIS Request to Send Disable 19 1 write-only CR_SPI_MODE Control Register SPI_MODE 0x00000000 32 write-only RSTRX Reset Receiver 2 1 write-only RSTTX Reset Transmitter 3 1 write-only RXEN Receiver Enable 4 1 write-only RXDIS Receiver Disable 5 1 write-only TXEN Transmitter Enable 6 1 write-only TXDIS Transmitter Disable 7 1 write-only RSTSTA Reset Status Bits 8 1 write-only FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only MR Mode Register 0x00000004 32 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 SPI_MASTER SPI Master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK Master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 CHRL Character Length. 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 SYNC Synchronous Mode Select 8 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 CHMODE Channel Mode 14 2 read-write NORMAL Normal Mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 MSBF Bit Order 16 1 read-write MODE9 9-bit Character Length 17 1 read-write CLKO Clock Output Select 18 1 read-write OVER Oversampling Mode 19 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write DSNACK Disable Successive NACK 21 1 read-write VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write FILTER Infrared Receive Line Filter 28 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write ONEBIT Start Frame Delimiter Selector 31 1 read-write MR_SPI_MODE Mode Register SPI_MODE 0x00000004 32 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI Master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK Master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 CHRL Character Length. 6 2 read-write 8_BIT Character length is 8 bits 0x3 CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write WRDBT Wait Read Data Before Transfer 20 1 read-write IER Interrupt Enable Register 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only ENDRX End of Receive Transfer Interrupt Enable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Enable (available in all USART modes of operation) 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only TXBUFE Buffer Empty Interrupt Enable (available in all USART modes of operation) 11 1 write-only RXBUFF Buffer Full Interrupt Enable (available in all USART modes of operation) 12 1 write-only NACK Non AcknowledgeInterrupt Enable 13 1 write-only CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only IER_SPI_MODE Interrupt Enable Register SPI_MODE 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only IDR Interrupt Disable Register 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only ENDRX End of Receive Transfer Interrupt Disable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Disable (available in all USART modes of operation) 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only TXBUFE Buffer Empty Interrupt Disable (available in all USART modes of operation) 11 1 write-only RXBUFF Buffer Full Interrupt Disable (available in all USART modes of operation) 12 1 write-only NACK Non AcknowledgeInterrupt Disable 13 1 write-only CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only IDR_SPI_MODE Interrupt Disable Register SPI_MODE 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only IMR Interrupt Mask Register 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only ENDRX End of Receive Transfer Interrupt Mask (available in all USART modes of operation) 3 1 read-only ENDTX End of Transmit Interrupt Mask (available in all USART modes of operation) 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only TXBUFE Buffer Empty Interrupt Mask (available in all USART modes of operation) 11 1 read-only RXBUFF Buffer Full Interrupt Mask (available in all USART modes of operation) 12 1 read-only NACK Non AcknowledgeInterrupt Mask 13 1 read-only CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only IMR_SPI_MODE Interrupt Mask Register SPI_MODE 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only CSR Channel Status Register 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only RXBRK Break Received/End of Break 2 1 read-only ENDRX End of Receiver Transfer 3 1 read-only ENDTX End of Transmitter Transfer 4 1 read-only OVRE Overrun Error 5 1 read-only FRAME Framing Error 6 1 read-only PARE Parity Error 7 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXEMPTY Transmitter Empty 9 1 read-only ITER MaxNumber of Repetitions Reached 10 1 read-only TXBUFE Transmission Buffer Empty 11 1 read-only RXBUFF Reception Buffer Full 12 1 read-only NACK Non AcknowledgeInterrupt 13 1 read-only CTSIC Clear to Send Input Change Flag 19 1 read-only CTS Image of CTS Input 23 1 read-only MANERR Manchester Error 24 1 read-only CSR_SPI_MODE Channel Status Register SPI_MODE 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only OVRE Overrun Error 5 1 read-only TXEMPTY Transmitter Empty 9 1 read-only UNRE Underrun Error 10 1 read-only RHR Receiver Holding Register 0x00000018 32 read-only 0x00000000 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only THR Transmitter Holding Register 0x0000001C 32 write-only TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only BRGR Baud Rate Generator Register 0x00000020 32 read-write 0x00000000 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write RTOR Receiver Time-out Register 0x00000024 32 read-write 0x00000000 TO Time-out Value 0 16 read-write TTGR Transmitter Timeguard Register 0x00000028 32 read-write 0x00000000 TG Timeguard Value 0 8 read-write FIDI FI DI Ratio Register 0x00000040 32 read-write 0x00000174 FI_DI_RATIO FI Over DI Ratio Value 0 11 read-write NER Number of Errors Register 0x00000044 32 read-only NB_ERRORS Number of Errors 0 8 read-only IF IrDA Filter Register 0x0000004C 32 read-write 0x00000000 IRDA_FILTER IrDA Filter 0 8 read-write MAN Manchester Encoder Decoder Register 0x00000050 32 read-write 0xB0011004 TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 RX_MPOL Receiver Manchester Polarity 28 1 read-write ONE Must Be Set to 1 29 1 read-write DRIFT Drift Compensation 30 1 read-write RPR Receive Pointer Register 0x00000100 32 read-write 0x00000000 RXPTR Receive Pointer Register 0 32 read-write RCR Receive Counter Register 0x00000104 32 read-write 0x00000000 RXCTR Receive Counter Register 0 16 read-write TPR Transmit Pointer Register 0x00000108 32 read-write 0x00000000 TXPTR Transmit Counter Register 0 32 read-write TCR Transmit Counter Register 0x0000010C 32 read-write 0x00000000 TXCTR Transmit Counter Register 0 16 read-write RNPR Receive Next Pointer Register 0x00000110 32 read-write 0x00000000 RXNPTR Receive Next Pointer 0 32 read-write RNCR Receive Next Counter Register 0x00000114 32 read-write 0x00000000 RXNCTR Receive Next Counter 0 16 read-write TNPR Transmit Next Pointer Register 0x00000118 32 read-write 0x00000000 TXNPTR Transmit Next Pointer 0 32 read-write TNCR Transmit Next Counter Register 0x0000011C 32 read-write 0x00000000 TXNCTR Transmit Counter Next 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only SSC0 6078I Synchronous Serial Controller 0 SSC SSC0_ 0xFFF9C000 0 0x4000 registers SSC0 16 CR Control Register 0x00000000 32 write-only RXEN Receive Enable 0 1 write-only RXDIS Receive Disable 1 1 write-only TXEN Transmit Enable 8 1 write-only TXDIS Transmit Disable 9 1 write-only SWRST Software Reset 15 1 write-only CMR Clock Mode Register 0x00000004 32 read-write 0x00000000 DIV Clock Divider 0 12 read-write RCMR Receive Clock Mode Register 0x00000010 32 read-write 0x00000000 CKS Receive Clock Selection 0 2 read-write MCK Divided Clock 0x0 TK TK Clock signal 0x1 RK RK pin 0x2 CKO Receive Clock Output Mode Selection 2 3 read-write NONE None 0x0 CONTINUOUS Continuous Receive Clock 0x1 TRANSFER Receive Clock only during data transfers 0x2 CKI Receive Clock Inversion 5 1 read-write CKG Receive Clock Gating Selection 6 2 read-write NONE None 0x0 CONTINUOUS Continuous Receive Clock 0x1 TRANSFER Receive Clock only during data transfers 0x2 START Receive Start Selection 8 4 read-write CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0x0 TRANSMIT Transmit start 0x1 RF_LOW Detection of a low level on RF signal 0x2 RF_HIGH Detection of a high level on RF signal 0x3 RF_FALLING Detection of a falling edge on RF signal 0x4 RF_RISING Detection of a rising edge on RF signal 0x5 RF_LEVEL Detection of any level change on RF signal 0x6 RF_EDGE Detection of any edge on RF signal 0x7 CMP_0 Compare 0 0x8 STOP Receive Stop Selection 12 1 read-write STTDLY Receive Start Delay 16 8 read-write PERIOD Receive Period Divider Selection 24 8 read-write RFMR Receive Frame Mode Register 0x00000014 32 read-write 0x00000000 DATLEN Data Length 0 5 read-write LOOP Loop Mode 5 1 read-write MSBF Most Significant Bit First 7 1 read-write DATNB Data Number per Frame 8 4 read-write FSLEN Receive Frame Sync Length 16 4 read-write FSOS Receive Frame Sync Output Selection 20 3 read-write NONE None 0x0 NEGATIVE Negative Pulse 0x1 POSITIVE Positive Pulse 0x2 LOW Driven Low during data transfer 0x3 HIGH Driven High during data transfer 0x4 TOGGLING Toggling at each start of data transfer 0x5 FSEDGE Frame Sync Edge Detection 24 1 read-write POSITIVE Positive Edge Detection 0 NEGATIVE Negative Edge Detection 1 FSLEN_EXT FSLEN Field Extension 28 4 read-write TCMR Transmit Clock Mode Register 0x00000018 32 read-write 0x00000000 CKS Transmit Clock Selection 0 2 read-write MCK Divided Clock 0x0 TK TK Clock signal 0x1 RK RK pin 0x2 CKO Transmit Clock Output Mode Selection 2 3 read-write NONE None 0x0 CONTINUOUS Continuous Receive Clock 0x1 TRANSFER Transmit Clock only during data transfers 0x2 CKI Transmit Clock Inversion 5 1 read-write CKG Transmit Clock Gating Selection 6 2 read-write NONE None 0x0 CONTINUOUS Transmit Clock enabled only if TF Low 0x1 TRANSFER Transmit Clock enabled only if TF High 0x2 START Transmit Start Selection 8 4 read-write CONTINUOUS Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. 0x0 RECEIVE Receive start 0x1 RF_LOW Detection of a low level on TF signal 0x2 RF_HIGH Detection of a high level on TF signal 0x3 RF_FALLING Detection of a falling edge on TF signal 0x4 RF_RISING Detection of a rising edge on TF signal 0x5 RF_LEVEL Detection of any level change on TF signal 0x6 RF_EDGE Detection of any edge on TF signal 0x7 CMP_0 Compare 0 0x8 STTDLY Transmit Start Delay 16 8 read-write PERIOD Transmit Period Divider Selection 24 8 read-write TFMR Transmit Frame Mode Register 0x0000001C 32 read-write 0x00000000 DATLEN Data Length 0 5 read-write DATDEF Data Default Value 5 1 read-write MSBF Most Significant Bit First 7 1 read-write DATNB Data Number per frame 8 4 read-write FSLEN Transmit Frame Syn Length 16 4 read-write FSOS Transmit Frame Sync Output Selection 20 3 read-write NONE None 0x0 NEGATIVE Negative Pulse 0x1 POSITIVE Positive Pulse 0x2 LOW Driven Low during data transfer 0x3 HIGH Driven High during data transfer 0x4 TOGGLING Toggling at each start of data transfer 0x5 FSDEN Frame Sync Data Enable 23 1 read-write FSEDGE Frame Sync Edge Detection 24 1 read-write POSITIVE Positive Edge Detection 0 NEGATIVE Negative Edge Detection 1 FSLEN_EXT FSLEN Field Extension 28 4 read-write RHR Receive Holding Register 0x00000020 32 read-only 0x00000000 RDAT Receive Data 0 32 read-only THR Transmit Holding Register 0x00000024 32 write-only TDAT Transmit Data 0 32 write-only RSHR Receive Sync. Holding Register 0x00000030 32 read-only 0x00000000 RSDAT Receive Synchronization Data 0 16 read-only TSHR Transmit Sync. Holding Register 0x00000034 32 read-write 0x00000000 TSDAT Transmit Synchronization Data 0 16 read-write RC0R Receive Compare 0 Register 0x00000038 32 read-write 0x00000000 CP0 Receive Compare Data 0 0 16 read-write RC1R Receive Compare 1 Register 0x0000003C 32 read-write 0x00000000 CP1 Receive Compare Data 1 0 16 read-write SR Status Register 0x00000040 32 read-only 0x000000CC TXRDY Transmit Ready 0 1 read-only TXEMPTY Transmit Empty 1 1 read-only ENDTX End of Transmission 2 1 read-only TXBUFE Transmit Buffer Empty 3 1 read-only RXRDY Receive Ready 4 1 read-only OVRUN Receive Overrun 5 1 read-only ENDRX End of Reception 6 1 read-only RXBUFF Receive Buffer Full 7 1 read-only CP0 Compare 0 8 1 read-only CP1 Compare 1 9 1 read-only TXSYN Transmit Sync 10 1 read-only RXSYN Receive Sync 11 1 read-only TXEN Transmit Enable 16 1 read-only RXEN Receive Enable 17 1 read-only IER Interrupt Enable Register 0x00000044 32 write-only TXRDY Transmit Ready Interrupt Enable 0 1 write-only TXEMPTY Transmit Empty Interrupt Enable 1 1 write-only ENDTX End of Transmission Interrupt Enable 2 1 write-only TXBUFE Transmit Buffer Empty Interrupt Enable 3 1 write-only RXRDY Receive Ready Interrupt Enable 4 1 write-only OVRUN Receive Overrun Interrupt Enable 5 1 write-only ENDRX End of Reception Interrupt Enable 6 1 write-only RXBUFF Receive Buffer Full Interrupt Enable 7 1 write-only CP0 Compare 0 Interrupt Enable 8 1 write-only CP1 Compare 1 Interrupt Enable 9 1 write-only TXSYN Tx Sync Interrupt Enable 10 1 write-only RXSYN Rx Sync Interrupt Enable 11 1 write-only IDR Interrupt Disable Register 0x00000048 32 write-only TXRDY Transmit Ready Interrupt Disable 0 1 write-only TXEMPTY Transmit Empty Interrupt Disable 1 1 write-only ENDTX End of Transmission Interrupt Disable 2 1 write-only TXBUFE Transmit Buffer Empty Interrupt Disable 3 1 write-only RXRDY Receive Ready Interrupt Disable 4 1 write-only OVRUN Receive Overrun Interrupt Disable 5 1 write-only ENDRX End of Reception Interrupt Disable 6 1 write-only RXBUFF Receive Buffer Full Interrupt Disable 7 1 write-only CP0 Compare 0 Interrupt Disable 8 1 write-only CP1 Compare 1 Interrupt Disable 9 1 write-only TXSYN Tx Sync Interrupt Enable 10 1 write-only RXSYN Rx Sync Interrupt Enable 11 1 write-only IMR Interrupt Mask Register 0x0000004C 32 read-only 0x00000000 TXRDY Transmit Ready Interrupt Mask 0 1 read-only TXEMPTY Transmit Empty Interrupt Mask 1 1 read-only ENDTX End of Transmission Interrupt Mask 2 1 read-only TXBUFE Transmit Buffer Empty Interrupt Mask 3 1 read-only RXRDY Receive Ready Interrupt Mask 4 1 read-only OVRUN Receive Overrun Interrupt Mask 5 1 read-only ENDRX End of Reception Interrupt Mask 6 1 read-only RXBUFF Receive Buffer Full Interrupt Mask 7 1 read-only CP0 Compare 0 Interrupt Mask 8 1 read-only CP1 Compare 1 Interrupt Mask 9 1 read-only TXSYN Tx Sync Interrupt Mask 10 1 read-only RXSYN Rx Sync Interrupt Mask 11 1 read-only RPR Receive Pointer Register 0x00000100 32 read-write 0x00000000 RXPTR Receive Pointer Register 0 32 read-write RCR Receive Counter Register 0x00000104 32 read-write 0x00000000 RXCTR Receive Counter Register 0 16 read-write TPR Transmit Pointer Register 0x00000108 32 read-write 0x00000000 TXPTR Transmit Counter Register 0 32 read-write TCR Transmit Counter Register 0x0000010C 32 read-write 0x00000000 TXCTR Transmit Counter Register 0 16 read-write RNPR Receive Next Pointer Register 0x00000110 32 read-write 0x00000000 RXNPTR Receive Next Pointer 0 32 read-write RNCR Receive Next Counter Register 0x00000114 32 read-write 0x00000000 RXNCTR Receive Next Counter 0 16 read-write TNPR Transmit Next Pointer Register 0x00000118 32 read-write 0x00000000 TXNPTR Transmit Next Pointer 0 32 read-write TNCR Transmit Next Counter Register 0x0000011C 32 read-write 0x00000000 TXNCTR Transmit Counter Next 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only SSC1 6078I Synchronous Serial Controller 1 SSC SSC1_ 0xFFFA0000 0 0x4000 registers SSC1 17 CR Control Register 0x00000000 32 write-only RXEN Receive Enable 0 1 write-only RXDIS Receive Disable 1 1 write-only TXEN Transmit Enable 8 1 write-only TXDIS Transmit Disable 9 1 write-only SWRST Software Reset 15 1 write-only CMR Clock Mode Register 0x00000004 32 read-write 0x00000000 DIV Clock Divider 0 12 read-write RCMR Receive Clock Mode Register 0x00000010 32 read-write 0x00000000 CKS Receive Clock Selection 0 2 read-write MCK Divided Clock 0x0 TK TK Clock signal 0x1 RK RK pin 0x2 CKO Receive Clock Output Mode Selection 2 3 read-write NONE None 0x0 CONTINUOUS Continuous Receive Clock 0x1 TRANSFER Receive Clock only during data transfers 0x2 CKI Receive Clock Inversion 5 1 read-write CKG Receive Clock Gating Selection 6 2 read-write NONE None 0x0 CONTINUOUS Continuous Receive Clock 0x1 TRANSFER Receive Clock only during data transfers 0x2 START Receive Start Selection 8 4 read-write CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0x0 TRANSMIT Transmit start 0x1 RF_LOW Detection of a low level on RF signal 0x2 RF_HIGH Detection of a high level on RF signal 0x3 RF_FALLING Detection of a falling edge on RF signal 0x4 RF_RISING Detection of a rising edge on RF signal 0x5 RF_LEVEL Detection of any level change on RF signal 0x6 RF_EDGE Detection of any edge on RF signal 0x7 CMP_0 Compare 0 0x8 STOP Receive Stop Selection 12 1 read-write STTDLY Receive Start Delay 16 8 read-write PERIOD Receive Period Divider Selection 24 8 read-write RFMR Receive Frame Mode Register 0x00000014 32 read-write 0x00000000 DATLEN Data Length 0 5 read-write LOOP Loop Mode 5 1 read-write MSBF Most Significant Bit First 7 1 read-write DATNB Data Number per Frame 8 4 read-write FSLEN Receive Frame Sync Length 16 4 read-write FSOS Receive Frame Sync Output Selection 20 3 read-write NONE None 0x0 NEGATIVE Negative Pulse 0x1 POSITIVE Positive Pulse 0x2 LOW Driven Low during data transfer 0x3 HIGH Driven High during data transfer 0x4 TOGGLING Toggling at each start of data transfer 0x5 FSEDGE Frame Sync Edge Detection 24 1 read-write POSITIVE Positive Edge Detection 0 NEGATIVE Negative Edge Detection 1 FSLEN_EXT FSLEN Field Extension 28 4 read-write TCMR Transmit Clock Mode Register 0x00000018 32 read-write 0x00000000 CKS Transmit Clock Selection 0 2 read-write MCK Divided Clock 0x0 TK TK Clock signal 0x1 RK RK pin 0x2 CKO Transmit Clock Output Mode Selection 2 3 read-write NONE None 0x0 CONTINUOUS Continuous Receive Clock 0x1 TRANSFER Transmit Clock only during data transfers 0x2 CKI Transmit Clock Inversion 5 1 read-write CKG Transmit Clock Gating Selection 6 2 read-write NONE None 0x0 CONTINUOUS Transmit Clock enabled only if TF Low 0x1 TRANSFER Transmit Clock enabled only if TF High 0x2 START Transmit Start Selection 8 4 read-write CONTINUOUS Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. 0x0 RECEIVE Receive start 0x1 RF_LOW Detection of a low level on TF signal 0x2 RF_HIGH Detection of a high level on TF signal 0x3 RF_FALLING Detection of a falling edge on TF signal 0x4 RF_RISING Detection of a rising edge on TF signal 0x5 RF_LEVEL Detection of any level change on TF signal 0x6 RF_EDGE Detection of any edge on TF signal 0x7 CMP_0 Compare 0 0x8 STTDLY Transmit Start Delay 16 8 read-write PERIOD Transmit Period Divider Selection 24 8 read-write TFMR Transmit Frame Mode Register 0x0000001C 32 read-write 0x00000000 DATLEN Data Length 0 5 read-write DATDEF Data Default Value 5 1 read-write MSBF Most Significant Bit First 7 1 read-write DATNB Data Number per frame 8 4 read-write FSLEN Transmit Frame Syn Length 16 4 read-write FSOS Transmit Frame Sync Output Selection 20 3 read-write NONE None 0x0 NEGATIVE Negative Pulse 0x1 POSITIVE Positive Pulse 0x2 LOW Driven Low during data transfer 0x3 HIGH Driven High during data transfer 0x4 TOGGLING Toggling at each start of data transfer 0x5 FSDEN Frame Sync Data Enable 23 1 read-write FSEDGE Frame Sync Edge Detection 24 1 read-write POSITIVE Positive Edge Detection 0 NEGATIVE Negative Edge Detection 1 FSLEN_EXT FSLEN Field Extension 28 4 read-write RHR Receive Holding Register 0x00000020 32 read-only 0x00000000 RDAT Receive Data 0 32 read-only THR Transmit Holding Register 0x00000024 32 write-only TDAT Transmit Data 0 32 write-only RSHR Receive Sync. Holding Register 0x00000030 32 read-only 0x00000000 RSDAT Receive Synchronization Data 0 16 read-only TSHR Transmit Sync. Holding Register 0x00000034 32 read-write 0x00000000 TSDAT Transmit Synchronization Data 0 16 read-write RC0R Receive Compare 0 Register 0x00000038 32 read-write 0x00000000 CP0 Receive Compare Data 0 0 16 read-write RC1R Receive Compare 1 Register 0x0000003C 32 read-write 0x00000000 CP1 Receive Compare Data 1 0 16 read-write SR Status Register 0x00000040 32 read-only 0x000000CC TXRDY Transmit Ready 0 1 read-only TXEMPTY Transmit Empty 1 1 read-only ENDTX End of Transmission 2 1 read-only TXBUFE Transmit Buffer Empty 3 1 read-only RXRDY Receive Ready 4 1 read-only OVRUN Receive Overrun 5 1 read-only ENDRX End of Reception 6 1 read-only RXBUFF Receive Buffer Full 7 1 read-only CP0 Compare 0 8 1 read-only CP1 Compare 1 9 1 read-only TXSYN Transmit Sync 10 1 read-only RXSYN Receive Sync 11 1 read-only TXEN Transmit Enable 16 1 read-only RXEN Receive Enable 17 1 read-only IER Interrupt Enable Register 0x00000044 32 write-only TXRDY Transmit Ready Interrupt Enable 0 1 write-only TXEMPTY Transmit Empty Interrupt Enable 1 1 write-only ENDTX End of Transmission Interrupt Enable 2 1 write-only TXBUFE Transmit Buffer Empty Interrupt Enable 3 1 write-only RXRDY Receive Ready Interrupt Enable 4 1 write-only OVRUN Receive Overrun Interrupt Enable 5 1 write-only ENDRX End of Reception Interrupt Enable 6 1 write-only RXBUFF Receive Buffer Full Interrupt Enable 7 1 write-only CP0 Compare 0 Interrupt Enable 8 1 write-only CP1 Compare 1 Interrupt Enable 9 1 write-only TXSYN Tx Sync Interrupt Enable 10 1 write-only RXSYN Rx Sync Interrupt Enable 11 1 write-only IDR Interrupt Disable Register 0x00000048 32 write-only TXRDY Transmit Ready Interrupt Disable 0 1 write-only TXEMPTY Transmit Empty Interrupt Disable 1 1 write-only ENDTX End of Transmission Interrupt Disable 2 1 write-only TXBUFE Transmit Buffer Empty Interrupt Disable 3 1 write-only RXRDY Receive Ready Interrupt Disable 4 1 write-only OVRUN Receive Overrun Interrupt Disable 5 1 write-only ENDRX End of Reception Interrupt Disable 6 1 write-only RXBUFF Receive Buffer Full Interrupt Disable 7 1 write-only CP0 Compare 0 Interrupt Disable 8 1 write-only CP1 Compare 1 Interrupt Disable 9 1 write-only TXSYN Tx Sync Interrupt Enable 10 1 write-only RXSYN Rx Sync Interrupt Enable 11 1 write-only IMR Interrupt Mask Register 0x0000004C 32 read-only 0x00000000 TXRDY Transmit Ready Interrupt Mask 0 1 read-only TXEMPTY Transmit Empty Interrupt Mask 1 1 read-only ENDTX End of Transmission Interrupt Mask 2 1 read-only TXBUFE Transmit Buffer Empty Interrupt Mask 3 1 read-only RXRDY Receive Ready Interrupt Mask 4 1 read-only OVRUN Receive Overrun Interrupt Mask 5 1 read-only ENDRX End of Reception Interrupt Mask 6 1 read-only RXBUFF Receive Buffer Full Interrupt Mask 7 1 read-only CP0 Compare 0 Interrupt Mask 8 1 read-only CP1 Compare 1 Interrupt Mask 9 1 read-only TXSYN Tx Sync Interrupt Mask 10 1 read-only RXSYN Rx Sync Interrupt Mask 11 1 read-only RPR Receive Pointer Register 0x00000100 32 read-write 0x00000000 RXPTR Receive Pointer Register 0 32 read-write RCR Receive Counter Register 0x00000104 32 read-write 0x00000000 RXCTR Receive Counter Register 0 16 read-write TPR Transmit Pointer Register 0x00000108 32 read-write 0x00000000 TXPTR Transmit Counter Register 0 32 read-write TCR Transmit Counter Register 0x0000010C 32 read-write 0x00000000 TXCTR Transmit Counter Register 0 16 read-write RNPR Receive Next Pointer Register 0x00000110 32 read-write 0x00000000 RXNPTR Receive Next Pointer 0 32 read-write RNCR Receive Next Counter Register 0x00000114 32 read-write 0x00000000 RXNCTR Receive Next Counter 0 16 read-write TNPR Transmit Next Pointer Register 0x00000118 32 read-write 0x00000000 TXNPTR Transmit Next Pointer 0 32 read-write TNCR Transmit Next Counter Register 0x0000011C 32 read-write 0x00000000 TXNCTR Transmit Counter Next 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only SPI0 6088O Serial Peripheral Interface 0 SPI SPI0_ 0xFFFA4000 0 0x4000 registers SPI0 14 CR Control Register 0x00000000 32 write-only SPIEN SPI Enable 0 1 write-only SPIDIS SPI Disable 1 1 write-only SWRST SPI Software Reset 7 1 write-only LASTXFER Last Transfer 24 1 write-only MR Mode Register 0x00000004 32 read-write 0x00000000 MSTR Master/Slave Mode 0 1 read-write PS Peripheral Select 1 1 read-write PCSDEC Chip Select Decode 2 1 read-write MODFDIS Mode Fault Detection 4 1 read-write WDRBT Wait Data Read Before Transfer 5 1 read-write LLB Local Loopback Enable 7 1 read-write PCS Peripheral Chip Select 16 4 read-write DLYBCS Delay Between Chip Selects 24 8 read-write RDR Receive Data Register 0x00000008 32 read-only 0x00000000 RD Receive Data 0 16 read-only PCS Peripheral Chip Select 16 4 read-only TDR Transmit Data Register 0x0000000C 32 write-only TD Transmit Data 0 16 write-only PCS Peripheral Chip Select 16 4 write-only LASTXFER Last Transfer 24 1 write-only SR Status Register 0x00000010 32 read-only 0x000000F0 RDRF Receive Data Register Full 0 1 read-only TDRE Transmit Data Register Empty 1 1 read-only MODF Mode Fault Error 2 1 read-only OVRES Overrun Error Status 3 1 read-only ENDRX End of RX buffer 4 1 read-only ENDTX End of TX buffer 5 1 read-only RXBUFF RX Buffer Full 6 1 read-only TXBUFE TX Buffer Empty 7 1 read-only NSSR NSS Rising 8 1 read-only TXEMPTY Transmission Registers Empty 9 1 read-only SPIENS SPI Enable Status 16 1 read-only IER Interrupt Enable Register 0x00000014 32 write-only RDRF Receive Data Register Full Interrupt Enable 0 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Enable 1 1 write-only MODF Mode Fault Error Interrupt Enable 2 1 write-only OVRES Overrun Error Interrupt Enable 3 1 write-only ENDRX End of Receive Buffer Interrupt Enable 4 1 write-only ENDTX End of Transmit Buffer Interrupt Enable 5 1 write-only RXBUFF Receive Buffer Full Interrupt Enable 6 1 write-only TXBUFE Transmit Buffer Empty Interrupt Enable 7 1 write-only NSSR NSS Rising Interrupt Enable 8 1 write-only TXEMPTY Transmission Registers Empty Enable 9 1 write-only IDR Interrupt Disable Register 0x00000018 32 write-only RDRF Receive Data Register Full Interrupt Disable 0 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Disable 1 1 write-only MODF Mode Fault Error Interrupt Disable 2 1 write-only OVRES Overrun Error Interrupt Disable 3 1 write-only ENDRX End of Receive Buffer Interrupt Disable 4 1 write-only ENDTX End of Transmit Buffer Interrupt Disable 5 1 write-only RXBUFF Receive Buffer Full Interrupt Disable 6 1 write-only TXBUFE Transmit Buffer Empty Interrupt Disable 7 1 write-only NSSR NSS Rising Interrupt Disable 8 1 write-only TXEMPTY Transmission Registers Empty Disable 9 1 write-only IMR Interrupt Mask Register 0x0000001C 32 read-only 0x00000000 RDRF Receive Data Register Full Interrupt Mask 0 1 read-only TDRE SPI Transmit Data Register Empty Interrupt Mask 1 1 read-only MODF Mode Fault Error Interrupt Mask 2 1 read-only OVRES Overrun Error Interrupt Mask 3 1 read-only ENDRX End of Receive Buffer Interrupt Mask 4 1 read-only ENDTX End of Transmit Buffer Interrupt Mask 5 1 read-only RXBUFF Receive Buffer Full Interrupt Mask 6 1 read-only TXBUFE Transmit Buffer Empty Interrupt Mask 7 1 read-only NSSR NSS Rising Interrupt Mask 8 1 read-only TXEMPTY Transmission Registers Empty Mask 9 1 read-only 4 4 0-3 CSR[%s] Chip Select Register 0x00000030 32 read-write CPOL Clock Polarity 0 1 read-write NCPHA Clock Phase 1 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 SCBR Serial Clock Baud Rate 8 8 read-write DLYBS Delay Before SPCK 16 8 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write RPR Receive Pointer Register 0x00000100 32 read-write 0x00000000 RXPTR Receive Pointer Register 0 32 read-write RCR Receive Counter Register 0x00000104 32 read-write 0x00000000 RXCTR Receive Counter Register 0 16 read-write TPR Transmit Pointer Register 0x00000108 32 read-write 0x00000000 TXPTR Transmit Counter Register 0 32 read-write TCR Transmit Counter Register 0x0000010C 32 read-write 0x00000000 TXCTR Transmit Counter Register 0 16 read-write RNPR Receive Next Pointer Register 0x00000110 32 read-write 0x00000000 RXNPTR Receive Next Pointer 0 32 read-write RNCR Receive Next Counter Register 0x00000114 32 read-write 0x00000000 RXNCTR Receive Next Counter 0 16 read-write TNPR Transmit Next Pointer Register 0x00000118 32 read-write 0x00000000 TXNPTR Transmit Next Pointer 0 32 read-write TNCR Transmit Next Counter Register 0x0000011C 32 read-write 0x00000000 TXNCTR Transmit Counter Next 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only SPI1 6088O Serial Peripheral Interface 1 SPI SPI1_ 0xFFFA8000 0 0x4000 registers SPI1 15 CR Control Register 0x00000000 32 write-only SPIEN SPI Enable 0 1 write-only SPIDIS SPI Disable 1 1 write-only SWRST SPI Software Reset 7 1 write-only LASTXFER Last Transfer 24 1 write-only MR Mode Register 0x00000004 32 read-write 0x00000000 MSTR Master/Slave Mode 0 1 read-write PS Peripheral Select 1 1 read-write PCSDEC Chip Select Decode 2 1 read-write MODFDIS Mode Fault Detection 4 1 read-write WDRBT Wait Data Read Before Transfer 5 1 read-write LLB Local Loopback Enable 7 1 read-write PCS Peripheral Chip Select 16 4 read-write DLYBCS Delay Between Chip Selects 24 8 read-write RDR Receive Data Register 0x00000008 32 read-only 0x00000000 RD Receive Data 0 16 read-only PCS Peripheral Chip Select 16 4 read-only TDR Transmit Data Register 0x0000000C 32 write-only TD Transmit Data 0 16 write-only PCS Peripheral Chip Select 16 4 write-only LASTXFER Last Transfer 24 1 write-only SR Status Register 0x00000010 32 read-only 0x000000F0 RDRF Receive Data Register Full 0 1 read-only TDRE Transmit Data Register Empty 1 1 read-only MODF Mode Fault Error 2 1 read-only OVRES Overrun Error Status 3 1 read-only ENDRX End of RX buffer 4 1 read-only ENDTX End of TX buffer 5 1 read-only RXBUFF RX Buffer Full 6 1 read-only TXBUFE TX Buffer Empty 7 1 read-only NSSR NSS Rising 8 1 read-only TXEMPTY Transmission Registers Empty 9 1 read-only SPIENS SPI Enable Status 16 1 read-only IER Interrupt Enable Register 0x00000014 32 write-only RDRF Receive Data Register Full Interrupt Enable 0 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Enable 1 1 write-only MODF Mode Fault Error Interrupt Enable 2 1 write-only OVRES Overrun Error Interrupt Enable 3 1 write-only ENDRX End of Receive Buffer Interrupt Enable 4 1 write-only ENDTX End of Transmit Buffer Interrupt Enable 5 1 write-only RXBUFF Receive Buffer Full Interrupt Enable 6 1 write-only TXBUFE Transmit Buffer Empty Interrupt Enable 7 1 write-only NSSR NSS Rising Interrupt Enable 8 1 write-only TXEMPTY Transmission Registers Empty Enable 9 1 write-only IDR Interrupt Disable Register 0x00000018 32 write-only RDRF Receive Data Register Full Interrupt Disable 0 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Disable 1 1 write-only MODF Mode Fault Error Interrupt Disable 2 1 write-only OVRES Overrun Error Interrupt Disable 3 1 write-only ENDRX End of Receive Buffer Interrupt Disable 4 1 write-only ENDTX End of Transmit Buffer Interrupt Disable 5 1 write-only RXBUFF Receive Buffer Full Interrupt Disable 6 1 write-only TXBUFE Transmit Buffer Empty Interrupt Disable 7 1 write-only NSSR NSS Rising Interrupt Disable 8 1 write-only TXEMPTY Transmission Registers Empty Disable 9 1 write-only IMR Interrupt Mask Register 0x0000001C 32 read-only 0x00000000 RDRF Receive Data Register Full Interrupt Mask 0 1 read-only TDRE SPI Transmit Data Register Empty Interrupt Mask 1 1 read-only MODF Mode Fault Error Interrupt Mask 2 1 read-only OVRES Overrun Error Interrupt Mask 3 1 read-only ENDRX End of Receive Buffer Interrupt Mask 4 1 read-only ENDTX End of Transmit Buffer Interrupt Mask 5 1 read-only RXBUFF Receive Buffer Full Interrupt Mask 6 1 read-only TXBUFE Transmit Buffer Empty Interrupt Mask 7 1 read-only NSSR NSS Rising Interrupt Mask 8 1 read-only TXEMPTY Transmission Registers Empty Mask 9 1 read-only 4 4 0-3 CSR[%s] Chip Select Register 0x00000030 32 read-write CPOL Clock Polarity 0 1 read-write NCPHA Clock Phase 1 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 SCBR Serial Clock Baud Rate 8 8 read-write DLYBS Delay Before SPCK 16 8 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write RPR Receive Pointer Register 0x00000100 32 read-write 0x00000000 RXPTR Receive Pointer Register 0 32 read-write RCR Receive Counter Register 0x00000104 32 read-write 0x00000000 RXCTR Receive Counter Register 0 16 read-write TPR Transmit Pointer Register 0x00000108 32 read-write 0x00000000 TXPTR Transmit Counter Register 0 32 read-write TCR Transmit Counter Register 0x0000010C 32 read-write 0x00000000 TXCTR Transmit Counter Register 0 16 read-write RNPR Receive Next Pointer Register 0x00000110 32 read-write 0x00000000 RXNPTR Receive Next Pointer 0 32 read-write RNCR Receive Next Counter Register 0x00000114 32 read-write 0x00000000 RXNCTR Receive Next Counter 0 16 read-write TNPR Transmit Next Pointer Register 0x00000118 32 read-write 0x00000000 TXNPTR Transmit Next Pointer 0 32 read-write TNCR Transmit Next Counter Register 0x0000011C 32 read-write 0x00000000 TXNCTR Transmit Counter Next 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only AC97C 6144D AC97 Controller AC97C_ 0xFFFAC000 0 0x4000 registers AC97C 24 MR Mode Register 0x00000008 32 read-write 0x00000000 ENA AC97 Controller Global Enable 0 1 read-write WRST Warm Reset 1 1 read-write VRA Variable Rate (for Data Slots 3-12) 2 1 read-write ICA Input Channel Assignment Register 0x00000010 32 read-write 0x00000000 CHID3 Channel ID for the input slot 3 0 3 read-write CHID4 Channel ID for the input slot 4 3 3 read-write CHID5 Channel ID for the input slot 5 6 3 read-write CHID6 Channel ID for the input slot 6 9 3 read-write CHID7 Channel ID for the input slot 7 12 3 read-write CHID8 Channel ID for the input slot 8 15 3 read-write CHID9 Channel ID for the input slot 9 18 3 read-write CHID10 Channel ID for the input slot 10 21 3 read-write CHID11 Channel ID for the input slot 11 24 3 read-write CHID12 Channel ID for the input slot 12 27 3 read-write OCA Output Channel Assignment Register 0x00000014 32 read-write 0x00000000 CHID3 Channel ID for the output slot 3 0 3 read-write CHID4 Channel ID for the output slot 4 3 3 read-write CHID5 Channel ID for the output slot 5 6 3 read-write CHID6 Channel ID for the output slot 6 9 3 read-write CHID7 Channel ID for the output slot 7 12 3 read-write CHID8 Channel ID for the output slot 8 15 3 read-write CHID9 Channel ID for the output slot 9 18 3 read-write CHID10 Channel ID for the output slot 10 21 3 read-write CHID11 Channel ID for the output slot 11 24 3 read-write CHID12 Channel ID for the output slot 12 27 3 read-write CARHR Channel A Receive Holding Register 0x00000020 32 read-only 0x00000000 RDATA Receive Data 0 20 read-only CATHR Channel A Transmit Holding Register 0x00000024 32 write-only TDATA Transmit Data 0 20 write-only CASR Channel A Status Register 0x00000028 32 read-only 0x00000000 TXRDY Channel Transmit Ready 0 1 read-only TXEMPTY Channel Transmit Empty 1 1 read-only UNRUN Transmit Underrun 2 1 read-only RXRDY Channel Receive Ready 4 1 read-only OVRUN Receive Overrun 5 1 read-only ENDTX End of Transmission for Channel A 10 1 read-only TXBUFE Transmit Buffer Empty for Channel A 11 1 read-only ENDRX End of Reception for Channel A 14 1 read-only RXBUFF Receive Buffer Full for Channel A 15 1 read-only CAMR Channel A Mode Register 0x0000002C 32 read-write 0x00000000 TXRDY Channel Transmit Ready Interrupt Enable 0 1 read-write TXEMPTY Channel Transmit Empty Interrupt Enable 1 1 read-write UNRUN Transmit Underrun Interrupt Enable 2 1 read-write RXRDY Channel Receive Ready Interrupt Enable 4 1 read-write OVRUN Receive Overrun Interrupt Enable 5 1 read-write ENDTX End of Transmission for Channel A Interrupt Enable 10 1 read-write TXBUFE Transmit Buffer Empty for Channel A Interrupt Enable 11 1 read-write ENDRX End of Reception for Channel A Interrupt Enable 14 1 read-write RXBUFF Receive Buffer Full for Channel A Interrupt Enable 15 1 read-write SIZE Channel A Data Size 16 2 read-write CEM Channel A Endian Mode 18 1 read-write CEN Channel A Enable 21 1 read-write PDCEN Peripheral Data Controller Channel Enable 22 1 read-write CBRHR Channel B Receive Holding Register 0x00000030 32 read-only 0x00000000 RDATA Receive Data 0 20 read-only CBTHR Channel B Transmit Holding Register 0x00000034 32 write-only TDATA Transmit Data 0 20 write-only CBSR Channel B Status Register 0x00000038 32 read-only 0x00000000 TXRDY Channel Transmit Ready 0 1 read-only TXEMPTY Channel Transmit Empty 1 1 read-only UNRUN Transmit Underrun 2 1 read-only RXRDY Channel Receive Ready 4 1 read-only OVRUN Receive Overrun 5 1 read-only ENDTX End of Transmission for Channel B 9 1 read-only TXBUFE Transmit Buffer Empty for Channel B 10 1 read-only ENDRX End of Reception for Channel B 14 1 read-only RXBUFF Receive Buffer Full for Channel B 15 1 read-only CBMR Channel B Mode Register 0x0000003C 32 read-write 0x00000000 TXRDY Channel Transmit Ready Interrupt Enable 0 1 read-write TXEMPTY Channel Transmit Empty Interrupt Enable 1 1 read-write UNRUN Transmit Underrun Interrupt Enable 2 1 read-write RXRDY Channel Receive Ready Interrupt Enable 4 1 read-write OVRUN Receive Overrun Interrupt Enable 5 1 read-write ENDTX End of Transmission for Channel B Interrupt Enable 10 1 read-write TXBUFE Transmit Buffer Empty for Channel B Interrupt Enable 11 1 read-write ENDRX End of Reception for Channel B Interrupt Enable 14 1 read-write RXBUFF Receive Buffer Full for Channel B Interrupt Enable 15 1 read-write SIZE Channel B Data Size 16 2 read-write CEM Channel B Endian Mode 18 1 read-write CEN Channel B Enable 21 1 read-write PDCEN Peripheral Data Controller Channel Enable 22 1 read-write CORHR Codec Channel Receive Holding Register 0x00000040 32 read-only 0x00000000 SDATA Status Data 0 16 read-only COTHR Codec Channel Transmit Holding Register 0x00000044 32 write-only CDATA Command Data 0 16 write-only CADDR CODEC control register index 16 7 write-only READ Read-write command 23 1 write-only COSR Codec Status Register 0x00000048 32 read-only 0x00000000 TXRDY Channel Transmit Ready 0 1 read-only TXEMPTY Channel Transmit Empty 1 1 read-only UNRUN Transmit Underrun 2 1 read-only RXRDY Channel Receive Ready 4 1 read-only OVRUN Receive Overrun 5 1 read-only COMR Codec Mode Register 0x0000004C 32 read-write 0x00000000 TXRDY Channel Transmit Ready Interrupt Enable 0 1 read-write TXEMPTY Channel Transmit Empty Interrupt Enable 1 1 read-write UNRUN Transmit Underrun Interrupt Enable 2 1 read-write RXRDY Channel Receive Ready Interrupt Enable 4 1 read-write OVRUN Receive Overrun Interrupt Enable 5 1 read-write SR Status Register 0x00000050 32 read-only 0x00000000 SOF Start Of Frame 0 1 read-only WKUP Wake Up detection 1 1 read-only COEVT CODEC Channel Event 2 1 read-only CAEVT Channel A Event 3 1 read-only CBEVT Channel B Event 4 1 read-only IER Interrupt Enable Register 0x00000054 32 write-only SOF Start Of Frame 0 1 write-only WKUP Wake Up 1 1 write-only COEVT Codec Event 2 1 write-only CAEVT Channel A Event 3 1 write-only CBEVT Channel B Event 4 1 write-only IDR Interrupt Disable Register 0x00000058 32 write-only SOF Start Of Frame 0 1 write-only WKUP Wake Up 1 1 write-only COEVT Codec Event 2 1 write-only CAEVT Channel A Event 3 1 write-only CBEVT Channel B Event 4 1 write-only IMR Interrupt Mask Register 0x0000005C 32 read-only 0x00000000 SOF Start Of Frame 0 1 read-only WKUP Wake Up 1 1 read-only COEVT Codec Event 2 1 read-only CAEVT Channel A Event 3 1 read-only CBEVT Channel B Event 4 1 read-only RPR Receive Pointer Register 0x00000100 32 read-write 0x00000000 RXPTR Receive Pointer Register 0 32 read-write RCR Receive Counter Register 0x00000104 32 read-write 0x00000000 RXCTR Receive Counter Register 0 16 read-write TPR Transmit Pointer Register 0x00000108 32 read-write 0x00000000 TXPTR Transmit Counter Register 0 32 read-write TCR Transmit Counter Register 0x0000010C 32 read-write 0x00000000 TXCTR Transmit Counter Register 0 16 read-write RNPR Receive Next Pointer Register 0x00000110 32 read-write 0x00000000 RXNPTR Receive Next Pointer 0 32 read-write RNCR Receive Next Counter Register 0x00000114 32 read-write 0x00000000 RXNCTR Receive Next Counter 0 16 read-write TNPR Transmit Next Pointer Register 0x00000118 32 read-write 0x00000000 TXNPTR Transmit Next Pointer 0 32 read-write TNCR Transmit Next Counter Register 0x0000011C 32 read-write 0x00000000 TXNCTR Transmit Counter Next 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only TSADCC 6286D Touch Screen ADC Controller TSADCC_ 0xFFFB0000 0 0x4000 registers TSADCC 20 CR Control Register 0x00000000 32 write-only SWRST Software Reset 0 1 write-only START Start Conversion 1 1 write-only MR Mode Register 0x00000004 32 read-write 0x00000000 TSAMOD Touch Screen ADC Mode 0 2 read-write PDCEN PDC transfer in Touchscreen/Interleaved mode or Manual mode 3 1 read-write LOWRES Resolution Selection 4 1 read-write SLEEP Sleep Mode 5 1 read-write PENDET Pen Detect Selection 6 1 read-write PRES Pressure Measurement Selection 7 1 read-write PRESCAL Prescaler Rate Selection 8 8 read-write STARTUP Start Up Time 16 7 read-write SHTIM Sample & Hold Time for ADC Channels 24 4 read-write PENDBC Pen Detect debouncing period 28 4 read-write TRGR Trigger Register 0x00000008 32 read-write 0x00000000 TRGMOD Trigger Mode 0 3 read-write TRGPER Trigger Period 16 16 read-write TSR Touch Screen Register 0x0000000C 32 read-write 0x00000000 TSFREQ Touch Screen Frequency in Interleaved Mode 0 4 read-write TSSHTIM Sample & Hold Time for Touch Screen Channels 24 4 read-write CHER Channel Enable Register 0x00000010 32 write-only CH0 Channel 0 Enable 0 1 write-only CH1 Channel 1 Enable 1 1 write-only CH2 Channel 2 Enable 2 1 write-only CH3 Channel 3 Enable 3 1 write-only CH4 Channel 4 Enable 4 1 write-only CH5 Channel 5 Enable 5 1 write-only CH6 Channel 6 Enable 6 1 write-only CH7 Channel 7 Enable 7 1 write-only CHDR Channel Disable Register 0x00000014 32 write-only CH0 Channel 0 Disable 0 1 write-only CH1 Channel 1 Disable 1 1 write-only CH2 Channel 2 Disable 2 1 write-only CH3 Channel 3 Disable 3 1 write-only CH4 Channel 4 Disable 4 1 write-only CH5 Channel 5 Disable 5 1 write-only CH6 Channel 6 Disable 6 1 write-only CH7 Channel 7 Disable 7 1 write-only CHSR Channel Status Register 0x00000018 32 read-only 0x00000000 CH0 Channel 0 Status 0 1 read-only CH1 Channel 1 Status 1 1 read-only CH2 Channel 2 Status 2 1 read-only CH3 Channel 3 Status 3 1 read-only CH4 Channel 4 Status 4 1 read-only CH5 Channel 5 Status 5 1 read-only CH6 Channel 6 Status 6 1 read-only CH7 Channel 7 Status 7 1 read-only SR Status Register 0x0000001C 32 read-only 0x000C0000 EOC0 End of Conversion 0 0 1 read-only EOC1 End of Conversion 1 1 1 read-only EOC2 End of Conversion 2 2 1 read-only EOC3 End of Conversion 3 3 1 read-only EOC4 End of Conversion 4 4 1 read-only EOC5 End of Conversion 5 5 1 read-only EOC6 End of Conversion 6 6 1 read-only EOC7 End of Conversion 7 7 1 read-only OVRE0 Overrun Error 0 8 1 read-only OVRE1 Overrun Error 1 9 1 read-only OVRE2 Overrun Error 2 10 1 read-only OVRE3 Overrun Error 3 11 1 read-only OVRE4 Overrun Error 4 12 1 read-only OVRE5 Overrun Error 5 13 1 read-only OVRE6 Overrun Error 6 14 1 read-only OVRE7 Overrun Error 7 15 1 read-only DRDY Data Ready 16 1 read-only GOVRE General Overrun Error 17 1 read-only ENDRX End of RX Buffer 18 1 read-only RXBUFF RX Buffer Full 19 1 read-only PENCNT Pen Contact 20 1 read-only NOCNT No Contact 21 1 read-only EOCXP 24 1 read-only EOCZ1 End of Conversion Z1 Measure 25 1 read-only EOCZ2 End of Conversion Z2 Measure 26 1 read-only OVREXP Overrun Error on X Position 28 1 read-only OVREZ1 Overrun Error on Z1 Measure 29 1 read-only OVREZ2 Overrun Error on Z2 Measure 30 1 read-only LCDR Last Converted Data Register 0x00000020 32 read-only 0x00000000 LDATA Last Data Converted 0 10 read-only IER Interrupt Enable Register 0x00000024 32 write-only EOC0 End of Conversion Interrupt Enable 0 0 1 write-only EOC1 End of Conversion Interrupt Enable 1 1 1 write-only EOC2 End of Conversion Interrupt Enable 2 2 1 write-only EOC3 End of Conversion Interrupt Enable 3 3 1 write-only EOC4 End of Conversion Interrupt Enable 4 4 1 write-only EOC5 End of Conversion Interrupt Enable 5 5 1 write-only EOC6 End of Conversion Interrupt Enable 6 6 1 write-only EOC7 End of Conversion Interrupt Enable 7 7 1 write-only OVRE0 Overrun Error Interrupt Enable 0 8 1 write-only OVRE1 Overrun Error Interrupt Enable 1 9 1 write-only OVRE2 Overrun Error Interrupt Enable 2 10 1 write-only OVRE3 Overrun Error Interrupt Enable 3 11 1 write-only OVRE4 Overrun Error Interrupt Enable 4 12 1 write-only OVRE5 Overrun Error Interrupt Enable 5 13 1 write-only OVRE6 Overrun Error Interrupt Enable 6 14 1 write-only OVRE7 Overrun Error Interrupt Enable 7 15 1 write-only DRDY Data Ready Interrupt Enable 16 1 write-only GOVRE General Overrun Error Interrupt Enable 17 1 write-only ENDRX End of Receive Buffer Interrupt Enable 18 1 write-only RXBUFF Receive Buffer Full Interrupt Enable 19 1 write-only PENCNT Pen Contact 20 1 write-only NOCNT No Contact 21 1 write-only EOCXP 24 1 write-only EOCZ1 End of Conversion Z1 Measure 25 1 write-only EOCZ2 End of Conversion Z2 Measure 26 1 write-only OVREXP Overrun Error Interrupt Enable X Position 28 1 write-only OVREZ1 Overrun Error Interrupt Enable Z1 Measure 29 1 write-only OVREZ2 Overrun Error Interrupt Enable Z2 Measure 30 1 write-only IDR Interrupt Disable Register 0x00000028 32 write-only EOC0 End of Conversion Interrupt Disable 0 0 1 write-only EOC1 End of Conversion Interrupt Disable 1 1 1 write-only EOC2 End of Conversion Interrupt Disable 2 2 1 write-only EOC3 End of Conversion Interrupt Disable 3 3 1 write-only EOC4 End of Conversion Interrupt Disable 4 4 1 write-only EOC5 End of Conversion Interrupt Disable 5 5 1 write-only EOC6 End of Conversion Interrupt Disable 6 6 1 write-only EOC7 End of Conversion Interrupt Disable 7 7 1 write-only OVRE0 Overrun Error Interrupt Disable 0 8 1 write-only OVRE1 Overrun Error Interrupt Disable 1 9 1 write-only OVRE2 Overrun Error Interrupt Disable 2 10 1 write-only OVRE3 Overrun Error Interrupt Disable 3 11 1 write-only OVRE4 Overrun Error Interrupt Disable 4 12 1 write-only OVRE5 Overrun Error Interrupt Disable 5 13 1 write-only OVRE6 Overrun Error Interrupt Disable 6 14 1 write-only OVRE7 Overrun Error Interrupt Disable 7 15 1 write-only DRDY Data Ready Interrupt Disable 16 1 write-only GOVRE General Overrun Error Interrupt Disable 17 1 write-only ENDRX End of Receive Buffer Interrupt Disable 18 1 write-only RXBUFF Receive Buffer Full Interrupt Disable 19 1 write-only PENCNT Pen Contact 20 1 write-only NOCNT No Contact 21 1 write-only EOCXP 24 1 write-only EOCZ1 End of Conversion Z1 Measure 25 1 write-only EOCZ2 End of Conversion Z2 Measure 26 1 write-only OVREXP Overrun Error Interrupt Disable X Position 28 1 write-only OVREZ1 Overrun Error Interrupt Disable Z1 Measure 29 1 write-only OVREZ2 Overrun Error Interrupt Disable Z2 Measure 30 1 write-only IMR Interrupt Mask Register 0x0000002C 32 read-only 0x00000000 EOC0 End of Conversion Interrupt Mask 0 0 1 read-only EOC1 End of Conversion Interrupt Mask 1 1 1 read-only EOC2 End of Conversion Interrupt Mask 2 2 1 read-only EOC3 End of Conversion Interrupt Mask 3 3 1 read-only EOC4 End of Conversion Interrupt Mask 4 4 1 read-only EOC5 End of Conversion Interrupt Mask 5 5 1 read-only EOC6 End of Conversion Interrupt Mask 6 6 1 read-only EOC7 End of Conversion Interrupt Mask 7 7 1 read-only OVRE0 Overrun Error Interrupt Mask 0 8 1 read-only OVRE1 Overrun Error Interrupt Mask 1 9 1 read-only OVRE2 Overrun Error Interrupt Mask 2 10 1 read-only OVRE3 Overrun Error Interrupt Mask 3 11 1 read-only OVRE4 Overrun Error Interrupt Mask 4 12 1 read-only OVRE5 Overrun Error Interrupt Mask 5 13 1 read-only OVRE6 Overrun Error Interrupt Mask 6 14 1 read-only OVRE7 Overrun Error Interrupt Mask 7 15 1 read-only DRDY Data Ready Interrupt Mask 16 1 read-only GOVRE General Overrun Error Interrupt Mask 17 1 read-only ENDRX End of Receive Buffer Interrupt Mask 18 1 read-only RXBUFF Receive Buffer Full Interrupt Mask 19 1 read-only PENCNT Pen Contact 20 1 read-only NOCNT No Contact 21 1 read-only EOCXP 24 1 read-only EOCZ1 End of Conversion Z1 Measure 25 1 read-only EOCZ2 End of Conversion Z2 Measure 26 1 read-only OVREXP Overrun Error Interrupt Mask X Position 28 1 read-only OVREZ1 Overrun Error Interrupt Mask Z1 Measure 29 1 read-only OVREZ2 Overrun Error Interrupt Mask Z2 Measure 30 1 read-only 8 4 0-7 CDR[%s] Channel Data Register 0x00000030 32 read-only DATA Channel Data 0 10 read-only XPDR X Position Data Register 0x00000050 32 read-only 0x00000000 DATA X Position Data 0 10 read-only Z1DR Z1 Data Register 0x00000054 32 read-only 0x00000000 DATA Z1 Measurement Data 0 10 read-only Z2DR Z2 Data Register 0x00000058 32 read-only 0x00000000 Z2 Z2 Measurement Data 0 10 read-only MSCR Manual Switch Command Register 0x00000060 32 read-write XP Switch Command 0 1 read-write XM Switch Command 1 1 read-write YP Switch Command 2 1 read-write YM Switch Command 3 1 read-write WPMR Write Protection Mode Register 0x000000E4 32 read-write WPEN Write Protection of TSADCC_MR, TSADCC_TRGR and TSADCC_TSR 0 1 read-write KEY 8 24 read-write WPSR Write Protection Status Register 0x000000E8 32 write-only WPS Write Protection Status 0 1 write-only OFFSET_ERR Offset error 8 24 write-only RPR Receive Pointer Register 0x00000100 32 read-write 0x00000000 RXPTR Receive Pointer Register 0 32 read-write RCR Receive Counter Register 0x00000104 32 read-write 0x00000000 RXCTR Receive Counter Register 0 16 read-write RNPR Receive Next Pointer Register 0x00000110 32 read-write 0x00000000 RXNPTR Receive Next Pointer 0 32 read-write RNCR Receive Next Counter Register 0x00000114 32 read-write 0x00000000 RXNCTR Receive Next Counter 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only ISI 6350E Image Sensor Interface 0xFFFB4000 0 0x4000 registers ISI 26 ISI_CFG1 ISI Configuration 1 Register 0x00000000 32 read-write 0x00000000 HSYNC_POL Horizontal Synchronization Polarity 2 1 read-write VSYNC_POL Vertical Synchronization Polarity 3 1 read-write PIXCLK_POL Pixel Clock Polarity 4 1 read-write EMB_SYNC Embedded Synchronization 6 1 read-write CRC_SYNC Embedded Synchronization Correction 7 1 read-write FRATE Frame Rate [0..7] 8 3 read-write DISCR Disable Codec Request 11 1 read-write FULL Full Mode is Allowed 12 1 read-write THMASK Threshold Mask 13 2 read-write SLD Start of Line Delay 16 8 read-write SFD Start of Frame Delay 24 8 read-write ISI_CFG2 ISI Configuration 2 Register 0x00000004 32 read-write 0x00000000 IM_VSIZE Vertical Size of the Image Sensor [0..2047]: 0 11 read-write GS_MODE 11 1 read-write RGB_MODE RGB Input Mode: 12 1 read-write GRAYSCALE 13 1 read-write RGB_SWAP 14 1 read-write COL_SPACE Color Space for the Image Data 15 1 read-write IM_HSIZE Horizontal Size of the Image Sensor [0..2047] 16 11 read-write YCC_SWAP Defines the YCC Image Data 28 2 read-write RGB_CFG Defines RGB Pattern when RGB_MODE is set to 1 30 2 read-write ISI_PSIZE ISI Preview Size Register 0x00000008 32 read-write 0x00000000 PREV_VSIZE Vertical Size for the Preview Path 0 10 read-write PREV_HSIZE Horizontal Size for the Preview Path 16 10 read-write ISI_PDECF ISI Preview Decimation Factor Register 0x0000000C 32 read-write 0x00000010 DEC_FACTOR Decimation Factor 0 8 read-write ISI_Y2R_SET0 ISI CSC YCrCb To RGB Set 0 Register 0x00000010 32 read-write 0x6832CC95 C0 Color Space Conversion Matrix Coefficient C0 0 8 read-write C1 Color Space Conversion Matrix Coefficient C1 8 8 read-write C2 Color Space Conversion Matrix Coefficient C2 16 8 read-write C3 Color Space Conversion Matrix Coefficient C3 24 8 read-write ISI_Y2R_SET1 ISI CSC YCrCb To RGB Set 1 Register 0x00000014 32 read-write 0x00007102 C4 Color Space Conversion Matrix Coefficient C4 0 9 read-write Yoff Color Space Conversion Luminance Default Offset 12 1 read-write Croff Color Space Conversion Red Chrominance Default Offset 13 1 read-write Cboff Color Space Conversion Blue Chrominance Default Offset 14 1 read-write ISI_R2Y_SET0 ISI CSC RGB To YCrCb Set 0 Register 0x00000018 32 read-write 0x01324145 C0 Color Space Conversion Matrix Coefficient C0 0 8 read-write C1 Color Space Conversion Matrix Coefficient C1 8 8 read-write C2 Color Space Conversion Matrix Coefficient C2 16 8 read-write Roff Color Space Conversion Red Component Offset 24 1 read-write ISI_R2Y_SET1 ISI CSC RGB To YCrCb Set 1 Register 0x0000001C 32 read-write 0x01245E38 C3 Color Space Conversion Matrix Coefficient C3 0 8 read-write C4 Color Space Conversion Matrix Coefficient C4 8 8 read-write C5 Color Space Conversion Matrix Coefficient C5 16 8 read-write Goff Color Space Conversion Green Component Offset 24 1 read-write ISI_R2Y_SET2 ISI CSC RGB To YCrCb Set 2 Register 0x00000020 32 read-write 0x01384A4B C6 Color Space Conversion Matrix Coefficient C6 0 8 read-write C7 Color Space Conversion Matrix Coefficient C7 8 8 read-write C8 Color Space Conversion Matrix Coefficient C8 16 8 read-write Boff Color Space Conversion Blue Component Offset 24 1 read-write ISI_CR ISI Control Register 0x00000024 32 write-only 0x00000000 ISI_EN ISI Module Enable Request 0 1 write-only ISI_DIS ISI Module Disable Request 1 1 write-only ISI_SRST ISI Software Reset Request 2 1 write-only ISI_CDC ISI Codec Request 8 1 write-only ISI_SR ISI Status Register 0x00000028 32 read-only 0x00000000 ENABLE 0 1 read-only DIS_DONE Module Disable Request has Terminated 1 1 read-only SRST Module Software Reset Request has Terminated 2 1 read-only CDC_PND Pending Codec Request (this bit is a status bit) 8 1 read-only VSYNC Vertical Synchronization 10 1 read-only PXFR_DONE Preview DMA Transfer has Terminated. 16 1 read-only CXFR_DONE Codec DMA Transfer has Terminated. 17 1 read-only SIP Synchronization in Progress (this is a status bit) 19 1 read-only P_OVR Preview Datapath Overflow 24 1 read-only C_OVR Codec Datapath Overflow 25 1 read-only CRC_ERR CRC Synchronization Error 26 1 read-only FR_OVR Frame Rate Overrun 27 1 read-only ISI_IER ISI Interrupt Enable Register 0x0000002C 32 write-only 0x00000000 DIS_DONE Disable Done Interrupt Enable 1 1 write-only SRST Software Reset Interrupt Enable 2 1 write-only VSYNC Vertical Synchronization Interrupt Enable 10 1 write-only PXFR_DONE Preview DMA Transfer Done Interrupt Enable 16 1 write-only CXFR_DONE Codec DMA Transfer Done Interrupt Enable 17 1 write-only P_OVR Preview Datapath Overflow Interrupt Enable 24 1 write-only C_OVR Codec Datapath Overflow Interrupt Enable 25 1 write-only CRC_ERR Embedded Synchronization CRC Error Interrupt Enable 26 1 write-only FR_OVR Frame Rate Overflow Interrupt Enable 27 1 write-only ISI_IDR ISI Interrupt Disable Register 0x00000030 32 write-only 0x00000000 DIS_DONE Disable Done Interrupt Disable 1 1 write-only SRST Software Reset Interrupt Disable 2 1 write-only VSYNC Vertical Synchronization Interrupt Disable 10 1 write-only PXFR_DONE Preview DMA Transfer Done Interrupt Disable 16 1 write-only CXFR_DONE Codec DMA Transfer Done Interrupt Disable 17 1 write-only P_OVR Preview Datapath Overflow Interrupt Disable 24 1 write-only C_OVR Codec Datapath Overflow Interrupt Disable 25 1 write-only CRC_ERR Embedded Synchronization CRC Error Interrupt Disable 26 1 write-only FR_OVR Frame Rate Overflow Interrupt Disable 27 1 write-only ISI_IMR ISI Interrupt Mask Register 0x00000034 32 read-only 0x00000000 DIS_DONE Module Disable Operation Completed 1 1 read-only SRST Software Reset Completed 2 1 read-only VSYNC Vertical Synchronization 10 1 read-only PXFR_DONE Preview DMA Transfer Interrupt 16 1 read-only CXFR_DONE Codec DMA Transfer Interrupt 17 1 read-only P_OVR FIFO Preview Overflow 24 1 read-only C_OVR FIFO Codec Overflow 25 1 read-only CRC_ERR CRC Synchronization Error 26 1 read-only FR_OVR Frame Rate Overrun 27 1 read-only DMA_CHER DMA Channel Enable Register 0x00000038 32 write-only 0x00000000 P_CH_EN Preview Channel Enable 0 1 write-only C_CH_EN Codec Channel Enable 1 1 write-only DMA_CHDR DMA Channel Disable Register 0x0000003C 32 write-only 0x00000000 P_CH_DIS 0 1 write-only C_CH_DIS 1 1 write-only DMA_CHSR DMA Channel Status Register 0x00000040 32 read-only 0x00000000 P_CH_S 0 1 read-only C_CH_S 1 1 read-only DMA_P_ADDR DMA Preview Base Address Register 0x00000044 32 read-write 0x00000000 P_ADDR Preview Image Base Address. (This address is word aligned.) 2 30 read-write DMA_P_CTRL DMA Preview Control Register 0x00000048 32 read-write 0x00000000 P_FETCH Descriptor Fetch Control Field 0 1 read-write P_WB Descriptor Writeback Control Field 1 1 read-write P_IEN Transfer Done Flag Control 2 1 read-write P_DONE (This field is only updated in the memory.) 3 1 read-write DMA_P_DSCR DMA Preview Descriptor Address Register 0x0000004C 32 read-write 0x00000000 P_DSCR Preview Descriptor Base Address (This address is word aligned.) 2 30 read-write DMA_C_ADDR DMA Codec Base Address Register 0x00000050 32 read-write 0x00000000 C_ADDR Codec Image Base Address (This address is word aligned.) 2 30 read-write DMA_C_CTRL DMA Codec Control Register 0x00000054 32 read-write 0x00000000 C_FETCH Descriptor Fetch Control Field 0 1 read-write C_WB Descriptor Writeback Control Field 1 1 read-write C_IEN Transfer Done flag control 2 1 read-write C_DONE (This field is only updated in the memory.) 3 1 read-write DMA_C_DSCR DMA Codec Descriptor Address Register 0x00000058 32 read-write 0x00000000 C_DSCR Codec Descriptor Base Address (This address is word aligned.) 2 30 read-write ISI_WPCR Write Protection Control Register 0x000000E4 32 read-write 0x00000000 WP_EN Write Protection Enable 0 1 read-write WP_KEY Write Protection KEY Password 8 24 read-write ISI_WPSR Write Protection Status Register 0x000000E8 32 read-only 0x00000000 WP_VS Write Protection Violation Status 0 4 read-only WP_VSRC Write Protection Violation Source 8 16 read-only PWM 6044I Pulse Width Modulation Controller PWM_ 0xFFFB8000 0 0x4000 registers PWM 19 MR PWM Mode Register 0x00000000 32 read-write 0x00000000 DIVA CLKA, CLKB Divide Factor 0 8 read-write CLK_OFF CLKA, CLKB clock is turned off 0 CLK_DIV1 CLKA, CLKB clock is clock selected by PREA, PREB 1 PREA 8 4 read-write MCK Master Clock 0x0 MCKDIV2 Master Clock divided by 2 0x1 MCKDIV4 Master Clock divided by 4 0x2 MCKDIV8 Master Clock divided by 8 0x3 MCKDIV16 Master Clock divided by 16 0x4 MCKDIV32 Master Clock divided by 32 0x5 MCKDIV64 Master Clock divided by 64 0x6 MCKDIV128 Master Clock divided by 128 0x7 MCKDIV256 Master Clock divided by 256 0x8 MCKDIV512 Master Clock divided by 512 0x9 MCKDIV1024 Master Clock divided by 1024 0xA DIVB CLKA, CLKB Divide Factor 16 8 read-write CLK_OFF CLKA, CLKB clock is turned off 0 CLK_DIV1 CLKA, CLKB clock is clock selected by PREA, PREB 1 PREB 24 4 read-write MCK Master Clock 0x0 MCKDIV2 Master Clock divided by 2 0x1 MCKDIV4 Master Clock divided by 4 0x2 MCKDIV8 Master Clock divided by 8 0x3 MCKDIV16 Master Clock divided by 16 0x4 MCKDIV32 Master Clock divided by 32 0x5 MCKDIV64 Master Clock divided by 64 0x6 MCKDIV128 Master Clock divided by 128 0x7 MCKDIV256 Master Clock divided by 256 0x8 MCKDIV512 Master Clock divided by 512 0x9 MCKDIV1024 Master Clock divided by 1024 0xA ENA PWM Enable Register 0x00000004 32 write-only CHID0 Channel ID 0 1 write-only CHID1 Channel ID 1 1 write-only CHID2 Channel ID 2 1 write-only CHID3 Channel ID 3 1 write-only DIS PWM Disable Register 0x00000008 32 write-only CHID0 Channel ID 0 1 write-only CHID1 Channel ID 1 1 write-only CHID2 Channel ID 2 1 write-only CHID3 Channel ID 3 1 write-only SR PWM Status Register 0x0000000C 32 read-only 0x00000000 CHID0 Channel ID 0 1 read-only CHID1 Channel ID 1 1 read-only CHID2 Channel ID 2 1 read-only CHID3 Channel ID 3 1 read-only IER PWM Interrupt Enable Register 0x00000010 32 write-only CHID0 Channel ID. 0 1 write-only CHID1 Channel ID. 1 1 write-only CHID2 Channel ID. 2 1 write-only CHID3 Channel ID. 3 1 write-only IDR PWM Interrupt Disable Register 0x00000014 32 write-only CHID0 Channel ID. 0 1 write-only CHID1 Channel ID. 1 1 write-only CHID2 Channel ID. 2 1 write-only CHID3 Channel ID. 3 1 write-only IMR PWM Interrupt Mask Register 0x00000018 32 read-only 0x00000000 CHID0 Channel ID. 0 1 read-only CHID1 Channel ID. 1 1 read-only CHID2 Channel ID. 2 1 read-only CHID3 Channel ID. 3 1 read-only ISR PWM Interrupt Status Register 0x0000001C 32 read-only 0x00000000 CHID0 Channel ID 0 1 read-only CHID1 Channel ID 1 1 read-only CHID2 Channel ID 2 1 read-only CHID3 Channel ID 3 1 read-only CMR0 PWM Channel Mode Register (ch_num = 0) 0x00000200 32 read-write 0x00000000 CPRE Channel Pre-scaler 0 4 read-write MCK Master Clock 0x0 MCKDIV2 Master Clock divided by 2 0x1 MCKDIV4 Master Clock divided by 4 0x2 MCKDIV8 Master Clock divided by 8 0x3 MCKDIV16 Master Clock divided by 16 0x4 MCKDIV32 Master Clock divided by 32 0x5 MCKDIV64 Master Clock divided by 64 0x6 MCKDIV128 Master Clock divided by 128 0x7 MCKDIV256 Master Clock divided by 256 0x8 MCKDIV512 Master Clock divided by 512 0x9 MCKDIV1024 Master Clock divided by 1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC CALG Channel Alignment 8 1 read-write CPOL Channel Polarity 9 1 read-write CPD Channel Update Period 10 1 read-write CDTY0 PWM Channel Duty Cycle Register (ch_num = 0) 0x00000204 32 read-write 0x00000000 CDTY Channel Duty Cycle 0 32 read-write CPRD0 PWM Channel Period Register (ch_num = 0) 0x00000208 32 read-write 0x00000000 CPRD Channel Period 0 32 read-write CCNT0 PWM Channel Counter Register (ch_num = 0) 0x0000020C 32 read-only 0x00000000 CNT Channel Counter Register 0 32 read-only CUPD0 PWM Channel Update Register (ch_num = 0) 0x00000210 32 write-only CUPD 0 32 write-only CMR1 PWM Channel Mode Register (ch_num = 1) 0x00000220 32 read-write 0x00000000 CPRE Channel Pre-scaler 0 4 read-write MCK Master Clock 0x0 MCKDIV2 Master Clock divided by 2 0x1 MCKDIV4 Master Clock divided by 4 0x2 MCKDIV8 Master Clock divided by 8 0x3 MCKDIV16 Master Clock divided by 16 0x4 MCKDIV32 Master Clock divided by 32 0x5 MCKDIV64 Master Clock divided by 64 0x6 MCKDIV128 Master Clock divided by 128 0x7 MCKDIV256 Master Clock divided by 256 0x8 MCKDIV512 Master Clock divided by 512 0x9 MCKDIV1024 Master Clock divided by 1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC CALG Channel Alignment 8 1 read-write CPOL Channel Polarity 9 1 read-write CPD Channel Update Period 10 1 read-write CDTY1 PWM Channel Duty Cycle Register (ch_num = 1) 0x00000224 32 read-write 0x00000000 CDTY Channel Duty Cycle 0 32 read-write CPRD1 PWM Channel Period Register (ch_num = 1) 0x00000228 32 read-write 0x00000000 CPRD Channel Period 0 32 read-write CCNT1 PWM Channel Counter Register (ch_num = 1) 0x0000022C 32 read-only 0x00000000 CNT Channel Counter Register 0 32 read-only CUPD1 PWM Channel Update Register (ch_num = 1) 0x00000230 32 write-only CUPD 0 32 write-only CMR2 PWM Channel Mode Register (ch_num = 2) 0x00000240 32 read-write 0x00000000 CPRE Channel Pre-scaler 0 4 read-write MCK Master Clock 0x0 MCKDIV2 Master Clock divided by 2 0x1 MCKDIV4 Master Clock divided by 4 0x2 MCKDIV8 Master Clock divided by 8 0x3 MCKDIV16 Master Clock divided by 16 0x4 MCKDIV32 Master Clock divided by 32 0x5 MCKDIV64 Master Clock divided by 64 0x6 MCKDIV128 Master Clock divided by 128 0x7 MCKDIV256 Master Clock divided by 256 0x8 MCKDIV512 Master Clock divided by 512 0x9 MCKDIV1024 Master Clock divided by 1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC CALG Channel Alignment 8 1 read-write CPOL Channel Polarity 9 1 read-write CPD Channel Update Period 10 1 read-write CDTY2 PWM Channel Duty Cycle Register (ch_num = 2) 0x00000244 32 read-write 0x00000000 CDTY Channel Duty Cycle 0 32 read-write CPRD2 PWM Channel Period Register (ch_num = 2) 0x00000248 32 read-write 0x00000000 CPRD Channel Period 0 32 read-write CCNT2 PWM Channel Counter Register (ch_num = 2) 0x0000024C 32 read-only 0x00000000 CNT Channel Counter Register 0 32 read-only CUPD2 PWM Channel Update Register (ch_num = 2) 0x00000250 32 write-only CUPD 0 32 write-only CMR3 PWM Channel Mode Register (ch_num = 3) 0x00000260 32 read-write 0x00000000 CPRE Channel Pre-scaler 0 4 read-write MCK Master Clock 0x0 MCKDIV2 Master Clock divided by 2 0x1 MCKDIV4 Master Clock divided by 4 0x2 MCKDIV8 Master Clock divided by 8 0x3 MCKDIV16 Master Clock divided by 16 0x4 MCKDIV32 Master Clock divided by 32 0x5 MCKDIV64 Master Clock divided by 64 0x6 MCKDIV128 Master Clock divided by 128 0x7 MCKDIV256 Master Clock divided by 256 0x8 MCKDIV512 Master Clock divided by 512 0x9 MCKDIV1024 Master Clock divided by 1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC CALG Channel Alignment 8 1 read-write CPOL Channel Polarity 9 1 read-write CPD Channel Update Period 10 1 read-write CDTY3 PWM Channel Duty Cycle Register (ch_num = 3) 0x00000264 32 read-write 0x00000000 CDTY Channel Duty Cycle 0 32 read-write CPRD3 PWM Channel Period Register (ch_num = 3) 0x00000268 32 read-write 0x00000000 CPRD Channel Period 0 32 read-write CCNT3 PWM Channel Counter Register (ch_num = 3) 0x0000026C 32 read-only 0x00000000 CNT Channel Counter Register 0 32 read-only CUPD3 PWM Channel Update Register (ch_num = 3) 0x00000270 32 write-only CUPD 0 32 write-only EMAC 6119F Ethernet MAC 10/100 EMAC_ 0xFFFBC000 0 0x4000 registers EMAC 25 NCR Network Control Register 0x00000000 32 read-write 0x00000000 LB LoopBack 0 1 read-write LLB Loopback local 1 1 read-write RE Receive enable 2 1 read-write TE Transmit enable 3 1 read-write MPE Management port enable 4 1 read-write CLRSTAT Clear statistics registers 5 1 read-write INCSTAT Increment statistics registers 6 1 read-write WESTAT Write enable for statistics registers 7 1 read-write BP Back pressure 8 1 read-write TSTART Start transmission 9 1 read-write THALT Transmit halt 10 1 read-write NCFG Network Configuration Register 0x00000004 32 read-write 0x00000800 SPD Speed 0 1 read-write FD Full Duplex 1 1 read-write JFRAME Jumbo Frames 3 1 read-write CAF Copy All Frames 4 1 read-write NBC No Broadcast 5 1 read-write MTI Multicast Hash Enable 6 1 read-write UNI Unicast Hash Enable 7 1 read-write BIG Receive 1536 bytes frames 8 1 read-write CLK MDC clock divider 10 2 read-write RTY Retry test 12 1 read-write PAE Pause Enable 13 1 read-write RBOF Receive Buffer Offset 14 2 read-write RLCE Receive Length field Checking Enable 16 1 read-write DRFCS Discard Receive FCS 17 1 read-write EFRHD 18 1 read-write IRXFCS Ignore RX FCS 19 1 read-write NSR Network Status Register 0x00000008 32 read-only MDIO 1 1 read-only IDLE 2 1 read-only TSR Transmit Status Register 0x00000014 32 read-write 0x00000000 UBR Used Bit Read 0 1 read-write COL Collision Occurred 1 1 read-write RLE Retry Limit exceeded 2 1 read-write TGO Transmit Go 3 1 read-write BEX Buffers exhausted mid frame 4 1 read-write COMP Transmit Complete 5 1 read-write UND Transmit Underrun 6 1 read-write RBQP Receive Buffer Queue Pointer Register 0x00000018 32 read-write 0x00000000 ADDR Receive buffer queue pointer address 2 30 read-write TBQP Transmit Buffer Queue Pointer Register 0x0000001C 32 read-write 0x00000000 ADDR Transmit buffer queue pointer address 2 30 read-write RSR Receive Status Register 0x00000020 32 read-write 0x00000000 BNA Buffer Not Available 0 1 read-write REC Frame Received 1 1 read-write OVR Receive Overrun 2 1 read-write ISR Interrupt Status Register 0x00000024 32 read-write 0x00000000 MFD Management Frame Done 0 1 read-write RCOMP Receive Complete 1 1 read-write RXUBR Receive Used Bit Read 2 1 read-write TXUBR Transmit Used Bit Read 3 1 read-write TUND Ethernet Transmit Buffer Underrun 4 1 read-write RLE Retry Limit Exceeded 5 1 read-write TXERR Transmit Error 6 1 read-write TCOMP Transmit Complete 7 1 read-write ROVR Receive Overrun 10 1 read-write HRESP Hresp not OK 11 1 read-write PFR Pause Frame Received 12 1 read-write PTZ Pause Time Zero 13 1 read-write IER Interrupt Enable Register 0x00000028 32 write-only MFD Management Frame sent 0 1 write-only RCOMP Receive Complete 1 1 write-only RXUBR Receive Used Bit Read 2 1 write-only TXUBR Transmit Used Bit Read 3 1 write-only TUND Ethernet Transmit Buffer Underrun 4 1 write-only RLE Retry Limit Exceeded 5 1 write-only TXERR 6 1 write-only TCOMP Transmit Complete 7 1 write-only ROVR Receive Overrun 10 1 write-only HRESP Hresp not OK 11 1 write-only PFR Pause Frame Received 12 1 write-only PTZ Pause Time Zero 13 1 write-only IDR Interrupt Disable Register 0x0000002C 32 write-only MFD Management Frame sent 0 1 write-only RCOMP Receive Complete 1 1 write-only RXUBR Receive Used Bit Read 2 1 write-only TXUBR Transmit Used Bit Read 3 1 write-only TUND Ethernet Transmit Buffer Underrun 4 1 write-only RLE Retry Limit Exceeded 5 1 write-only TXERR 6 1 write-only TCOMP Transmit Complete 7 1 write-only ROVR Receive Overrun 10 1 write-only HRESP Hresp not OK 11 1 write-only PFR Pause Frame Received 12 1 write-only PTZ Pause Time Zero 13 1 write-only IMR Interrupt Mask Register 0x00000030 32 read-only 0x00003FFF MFD Management Frame sent 0 1 read-only RCOMP Receive Complete 1 1 read-only RXUBR Receive Used Bit Read 2 1 read-only TXUBR Transmit Used Bit Read 3 1 read-only TUND Ethernet Transmit Buffer Underrun 4 1 read-only RLE Retry Limit Exceeded 5 1 read-only TXERR 6 1 read-only TCOMP Transmit Complete 7 1 read-only ROVR Receive Overrun 10 1 read-only HRESP Hresp not OK 11 1 read-only PFR Pause Frame Received 12 1 read-only PTZ Pause Time Zero 13 1 read-only MAN Phy Maintenance Register 0x00000034 32 read-write 0x00000000 DATA 0 16 read-write CODE 16 2 read-write REGA Register Address 18 5 read-write PHYA PHY Address 23 5 read-write RW Read-write 28 2 read-write SOF Start of frame 30 2 read-write PTR Pause Time Register 0x00000038 32 read-write 0x00000000 PTIME Pause Time 0 16 read-write PFR Pause Frames Received Register 0x0000003C 32 read-write 0x00000000 FROK Pause Frames received OK 0 16 read-write FTO Frames Transmitted Ok Register 0x00000040 32 read-write 0x00000000 FTOK Frames Transmitted OK 0 24 read-write SCF Single Collision Frames Register 0x00000044 32 read-write 0x00000000 SCF Single Collision Frames 0 16 read-write MCF Multiple Collision Frames Register 0x00000048 32 read-write 0x00000000 MCF Multicollision Frames 0 16 read-write FRO Frames Received Ok Register 0x0000004C 32 read-write 0x00000000 FROK Frames Received OK 0 24 read-write FCSE Frame Check Sequence Errors Register 0x00000050 32 read-write 0x00000000 FCSE Frame Check Sequence Errors 0 8 read-write ALE Alignment Errors Register 0x00000054 32 read-write 0x00000000 ALE Alignment Errors 0 8 read-write DTF Deferred Transmission Frames Register 0x00000058 32 read-write 0x00000000 DTF Deferred Transmission Frames 0 16 read-write LCOL Late Collisions Register 0x0000005C 32 read-write 0x00000000 LCOL Late Collisions 0 8 read-write ECOL Excessive Collisions Register 0x00000060 32 read-write 0x00000000 EXCOL Excessive Collisions 0 8 read-write TUND Transmit Underrun Errors Register 0x00000064 32 read-write 0x00000000 TUND Transmit Underruns 0 8 read-write CSE Carrier Sense Errors Register 0x00000068 32 read-write 0x00000000 CSE Carrier Sense Errors 0 8 read-write RRE Receive Resource Errors Register 0x0000006C 32 read-write 0x00000000 RRE Receive Resource Errors 0 16 read-write ROV Receive Overrun Errors Register 0x00000070 32 read-write 0x00000000 ROVR Receive Overrun 0 8 read-write RSE Receive Symbol Errors Register 0x00000074 32 read-write 0x00000000 RSE Receive Symbol Errors 0 8 read-write ELE Excessive Length Errors Register 0x00000078 32 read-write 0x00000000 EXL Excessive Length Errors 0 8 read-write RJA Receive Jabbers Register 0x0000007C 32 read-write 0x00000000 RJB Receive Jabbers 0 8 read-write USF Undersize Frames Register 0x00000080 32 read-write 0x00000000 USF Undersize frames 0 8 read-write STE SQE Test Errors Register 0x00000084 32 read-write 0x00000000 SQER SQE test errors 0 8 read-write RLE Received Length Field Mismatch Register 0x00000088 32 read-write 0x00000000 RLFM Receive Length Field Mismatch 0 8 read-write HRB Hash Register Bottom [31:0] Register 0x00000090 32 read-write 0x00000000 ADDR 0 32 read-write HRT Hash Register Top [63:32] Register 0x00000094 32 read-write 0x00000000 ADDR 0 32 read-write SA1B Specific Address 1 Bottom Register 0x00000098 32 read-write 0x00000000 ADDR 0 32 read-write SA1T Specific Address 1 Top Register 0x0000009C 32 read-write 0x00000000 ADDR 0 16 read-write SA2B Specific Address 2 Bottom Register 0x000000A0 32 read-write 0x00000000 ADDR 0 32 read-write SA2T Specific Address 2 Top Register 0x000000A4 32 read-write 0x00000000 ADDR 0 16 read-write SA3B Specific Address 3 Bottom Register 0x000000A8 32 read-write 0x00000000 ADDR 0 32 read-write SA3T Specific Address 3 Top Register 0x000000AC 32 read-write 0x00000000 ADDR 0 16 read-write SA4B Specific Address 4 Bottom Register 0x000000B0 32 read-write 0x00000000 ADDR 0 32 read-write SA4T Specific Address 4 Top Register 0x000000B4 32 read-write 0x00000000 ADDR 0 16 read-write TID Type ID Checking Register 0x000000B8 32 read-write 0x00000000 TID Type ID checking 0 16 read-write USRIO User Input/Output Register 0x000000C0 32 read-write 0x00000000 RMII 0 1 read-write CLKEN 1 1 read-write TRNG 6334A True Random Number Generator TRNG_ 0xFFFCC000 0 0x4000 registers TRNG 6 CR Control Register 0x00000000 32 write-only ENABLE Enables the TRNG to provide random values 0 1 write-only IER Interrupt Enable Register 0x00000010 32 write-only DATRDY Data Ready Interrupt Enable 0 1 write-only IDR Interrupt Disable Register 0x00000014 32 write-only DATRDY Data Ready Interrupt Disable 0 1 write-only IMR Interrupt Mask Register 0x00000018 32 read-only 0x00000000 DATRDY Data Ready Interrupt Mask 0 1 read-only ISR Interrupt Status Register 0x0000001C 32 read-only 0x00000000 DATRDY Data Ready 0 1 read-only ODATA Output Data Register 0x00000050 32 read-only 0x00000000 ODATA Output Data 0 32 read-only HSMCI1 6449D High Speed MultiMedia Card Interface 1 HSMCI HSMCI1_ 0xFFFD0000 0 0x4000 registers HSMCI1 29 CR Control Register 0x00000000 32 write-only MCIEN Multi-Media Interface Enable 0 1 write-only MCIDIS Multi-Media Interface Disable 1 1 write-only PWSEN Power Save Mode Enable 2 1 write-only PWSDIS Power Save Mode Disable 3 1 write-only SWRST Software Reset 7 1 write-only MR Mode Register 0x00000004 32 read-write 0x00000000 CLKDIV Clock Divider 0 8 read-write PWSDIV Power Saving Divider 8 3 read-write RDPROOF 11 1 read-write WRPROOF 12 1 read-write FBYTE Force Byte Transfer 13 1 read-write PADV Padding Value 14 1 read-write BLKLEN Data Block Length 16 16 read-write DTOR Data Timeout Register 0x00000008 32 read-write 0x00000000 DTOCYC Data Timeout Cycle Number 0 4 read-write DTOMUL Data Timeout Multiplier 4 3 read-write 1 DTOCYC 0x0 16 DTOCYC x 16 0x1 128 DTOCYC x 128 0x2 256 DTOCYC x 256 0x3 1024 DTOCYC x 1024 0x4 4096 DTOCYC x 4096 0x5 65536 DTOCYC x 65536 0x6 1048576 DTOCYC x 1048576 0x7 SDCR SD/SDIO Card Register 0x0000000C 32 read-write 0x00000000 SDCSEL SDCard/SDIO Slot 0 2 read-write SLOTA Slot A is selected. 0x0 SLOTB - 0x1 SLOTC - 0x2 SLOTD - 0x3 SDCBUS SDCard/SDIO Bus Width 6 2 read-write 1 1 bit 0x0 4 4 bit 0x1 8 8 bit 0x2 ARGR Argument Register 0x00000010 32 read-write 0x00000000 ARG Command Argument 0 32 read-write CMDR Command Register 0x00000014 32 write-only CMDNB Command Number 0 6 write-only RSPTYP Response Type 6 2 write-only NORESP No response. 0x0 48_BIT 48-bit response. 0x1 136_BIT 136-bit response. 0x2 R1B R1b response type 0x3 SPCMD Special Command 8 3 write-only STD Not a special CMD. 0x0 INIT Initialization CMD:74 clock cycles for initialization sequence. 0x1 SYNC Synchronized CMD:Wait for the end of the current data block transfer before sending the pending command. 0x2 CE_ATA CE-ATA Completion Signal disable Command.The host cancels the ability for the device to return a command completion signal on the command line. 0x3 IT_CMD Interrupt command:Corresponds to the Interrupt Mode (CMD40). 0x4 IT_RESP Interrupt response:Corresponds to the Interrupt Mode (CMD40). 0x5 BOR Boot Operation Request.Start a boot operation mode, the host processor can read boot data from the MMC device directly. 0x6 EBO End Boot Operation.This command allows the host processor to terminate the boot operation mode. 0x7 OPDCMD Open Drain Command 11 1 write-only PUSHPULL Push pull command. 0 OPENDRAIN Open drain command. 1 MAXLAT Max Latency for Command to Response 12 1 write-only 5 5-cycle max latency. 0 64 64-cycle max latency. 1 TRCMD Transfer Command 16 2 write-only NO_DATA No data transfer 0x0 START_DATA Start data transfer 0x1 STOP_DATA Stop data transfer 0x2 TRDIR Transfer Direction 18 1 write-only WRITE Write. 0 READ Read. 1 TRTYP Transfer Type 19 3 write-only SINGLE MMC/SDCard Single Block 0x0 MULTIPLE MMC/SDCard Multiple Block 0x1 STREAM MMC Stream 0x2 BYTE SDIO Byte 0x4 BLOCK SDIO Block 0x5 IOSPCMD SDIO Special Command 24 2 write-only STD Not an SDIO Special Command 0x0 SUSPEND SDIO Suspend Command 0x1 RESUME SDIO Resume Command 0x2 ATACS ATA with Command Completion Signal 26 1 write-only NORMAL Normal operation mode. 0 COMPLETION This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). 1 BOOT_ACK Boot Operation Acknowledge. 27 1 write-only BLKR Block Register 0x00000018 32 read-write 0x00000000 BCNT MMC/SDIO Block Count - SDIO Byte Count 0 16 read-write MULTIPLE MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. 0x0 BYTE SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. 0x4 BLOCK SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. 0x5 BLKLEN Data Block Length 16 16 read-write CSTOR Completion Signal Timeout Register 0x0000001C 32 read-write 0x00000000 CSTOCYC Completion Signal Timeout Cycle Number 0 4 read-write CSTOMUL Completion Signal Timeout Multiplier 4 3 read-write 1 CSTOCYC x 1 0x0 16 CSTOCYC x 16 0x1 128 CSTOCYC x 128 0x2 256 CSTOCYC x 256 0x3 1024 CSTOCYC x 1024 0x4 4096 CSTOCYC x 4096 0x5 65536 CSTOCYC x 65536 0x6 1048576 CSTOCYC x 1048576 0x7 4 4 0-3 RSPR[%s] Response Register 0x00000020 32 read-only RSP Response 0 32 read-only RDR Receive Data Register 0x00000030 32 read-only 0x00000000 DATA Data to Read 0 32 read-only TDR Transmit Data Register 0x00000034 32 write-only DATA Data to Write 0 32 write-only SR Status Register 0x00000040 32 read-only 0x0000C0E5 CMDRDY Command Ready 0 1 read-only RXRDY Receiver Ready 1 1 read-only TXRDY Transmit Ready 2 1 read-only BLKE Data Block Ended 3 1 read-only DTIP Data Transfer in Progress 4 1 read-only NOTBUSY HSMCI Not Busy 5 1 read-only MCI_SDIOIRQA 8 1 read-only SDIOWAIT SDIO Read Wait Operation Status 12 1 read-only CSRCV CE-ATA Completion Signal Received 13 1 read-only RINDE Response Index Error 16 1 read-only RDIRE Response Direction Error 17 1 read-only RCRCE Response CRC Error 18 1 read-only RENDE Response End Bit Error 19 1 read-only RTOE Response Time-out Error 20 1 read-only DCRCE Data CRC Error 21 1 read-only DTOE Data Time-out Error 22 1 read-only CSTOE Completion Signal Time-out Error 23 1 read-only BLKOVRE DMA Block Overrun Error 24 1 read-only DMADONE DMA Transfer done 25 1 read-only FIFOEMPTY FIFO empty flag 26 1 read-only XFRDONE Transfer Done flag 27 1 read-only ACKRCV Boot Operation Acknowledge Received 28 1 read-only ACKRCVE Boot Operation Acknowledge Error 29 1 read-only OVRE Overrun 30 1 read-only UNRE Underrun 31 1 read-only IER Interrupt Enable Register 0x00000044 32 write-only CMDRDY Command Ready Interrupt Enable 0 1 write-only RXRDY Receiver Ready Interrupt Enable 1 1 write-only TXRDY Transmit Ready Interrupt Enable 2 1 write-only BLKE Data Block Ended Interrupt Enable 3 1 write-only DTIP Data Transfer in Progress Interrupt Enable 4 1 write-only NOTBUSY Data Not Busy Interrupt Enable 5 1 write-only MCI_SDIOIRQA 8 1 write-only SDIOWAIT SDIO Read Wait Operation Status Interrupt Enable 12 1 write-only CSRCV Completion Signal Received Interrupt Enable 13 1 write-only RINDE Response Index Error Interrupt Enable 16 1 write-only RDIRE Response Direction Error Interrupt Enable 17 1 write-only RCRCE Response CRC Error Interrupt Enable 18 1 write-only RENDE Response End Bit Error Interrupt Enable 19 1 write-only RTOE Response Time-out Error Interrupt Enable 20 1 write-only DCRCE Data CRC Error Interrupt Enable 21 1 write-only DTOE Data Time-out Error Interrupt Enable 22 1 write-only CSTOE Completion Signal Timeout Error Interrupt Enable 23 1 write-only BLKOVRE DMA Block Overrun Error Interrupt Enable 24 1 write-only DMADONE DMA Transfer completed Interrupt Enable 25 1 write-only FIFOEMPTY FIFO empty Interrupt enable 26 1 write-only XFRDONE Transfer Done Interrupt enable 27 1 write-only ACKRCV Boot Acknowledge Interrupt Enable 28 1 write-only ACKRCVE Boot Acknowledge Error Interrupt Enable 29 1 write-only OVRE Overrun Interrupt Enable 30 1 write-only UNRE Underrun Interrupt Enable 31 1 write-only IDR Interrupt Disable Register 0x00000048 32 write-only CMDRDY Command Ready Interrupt Disable 0 1 write-only RXRDY Receiver Ready Interrupt Disable 1 1 write-only TXRDY Transmit Ready Interrupt Disable 2 1 write-only BLKE Data Block Ended Interrupt Disable 3 1 write-only DTIP Data Transfer in Progress Interrupt Disable 4 1 write-only NOTBUSY Data Not Busy Interrupt Disable 5 1 write-only MCI_SDIOIRQA 8 1 write-only SDIOWAIT SDIO Read Wait Operation Status Interrupt Disable 12 1 write-only CSRCV Completion Signal received interrupt Disable 13 1 write-only RINDE Response Index Error Interrupt Disable 16 1 write-only RDIRE Response Direction Error Interrupt Disable 17 1 write-only RCRCE Response CRC Error Interrupt Disable 18 1 write-only RENDE Response End Bit Error Interrupt Disable 19 1 write-only RTOE Response Time-out Error Interrupt Disable 20 1 write-only DCRCE Data CRC Error Interrupt Disable 21 1 write-only DTOE Data Time-out Error Interrupt Disable 22 1 write-only CSTOE Completion Signal Time out Error Interrupt Disable 23 1 write-only BLKOVRE DMA Block Overrun Error Interrupt Disable 24 1 write-only DMADONE DMA Transfer completed Interrupt Disable 25 1 write-only FIFOEMPTY FIFO empty Interrupt Disable 26 1 write-only XFRDONE Transfer Done Interrupt Disable 27 1 write-only ACKRCV Boot Acknowledge Interrupt Disable 28 1 write-only ACKRCVE Boot Acknowledge Error Interrupt Disable 29 1 write-only OVRE Overrun Interrupt Disable 30 1 write-only UNRE Underrun Interrupt Disable 31 1 write-only IMR Interrupt Mask Register 0x0000004C 32 read-only 0x00000000 CMDRDY Command Ready Interrupt Mask 0 1 read-only RXRDY Receiver Ready Interrupt Mask 1 1 read-only TXRDY Transmit Ready Interrupt Mask 2 1 read-only BLKE Data Block Ended Interrupt Mask 3 1 read-only DTIP Data Transfer in Progress Interrupt Mask 4 1 read-only NOTBUSY Data Not Busy Interrupt Mask 5 1 read-only MCI_SDIOIRQA 8 1 read-only SDIOWAIT SDIO Read Wait Operation Status Interrupt Mask 12 1 read-only CSRCV Completion Signal Received Interrupt Mask 13 1 read-only RINDE Response Index Error Interrupt Mask 16 1 read-only RDIRE Response Direction Error Interrupt Mask 17 1 read-only RCRCE Response CRC Error Interrupt Mask 18 1 read-only RENDE Response End Bit Error Interrupt Mask 19 1 read-only RTOE Response Time-out Error Interrupt Mask 20 1 read-only DCRCE Data CRC Error Interrupt Mask 21 1 read-only DTOE Data Time-out Error Interrupt Mask 22 1 read-only CSTOE Completion Signal Time-out Error Interrupt Mask 23 1 read-only BLKOVRE DMA Block Overrun Error Interrupt Mask 24 1 read-only DMADONE DMA Transfer Completed Interrupt Mask 25 1 read-only FIFOEMPTY FIFO Empty Interrupt Mask 26 1 read-only XFRDONE Transfer Done Interrupt Mask 27 1 read-only ACKRCV Boot Operation Acknowledge Received Interrupt Mask 28 1 read-only ACKRCVE Boot Operation Acknowledge Error Interrupt Mask 29 1 read-only OVRE Overrun Interrupt Mask 30 1 read-only UNRE Underrun Interrupt Mask 31 1 read-only DMA DMA Configuration Register 0x00000050 32 read-write 0x00000000 OFFSET DMA Write Buffer Offset 0 2 read-write CHKSIZE DMA Channel Read and Write Chunk Size 4 2 read-write 1 1 data available 0x0 4 4 data available 0x1 8 8 data available 0x2 16 16 data available 0x3 DMAEN DMA Hardware Handshaking Enable 8 1 read-write ROPT Read Optimization with padding 12 1 read-write CFG Configuration Register 0x00000054 32 read-write 0x00000000 FIFOMODE HSMCI Internal FIFO control mode 0 1 read-write FERRCTRL Flow Error flag reset control mode 4 1 read-write HSMODE High Speed Mode 8 1 read-write LSYNC Synchronize on the last block 12 1 read-write WPMR Write Protection Mode Register 0x000000E4 32 read-write WP_EN Write Protection Enable 0 1 read-write WP_KEY Write Protection Key password 8 24 read-write WPSR Write Protection Status Register 0x000000E8 32 read-only WP_VS Write Protection Violation Status 0 4 read-only NONE No Write Protection Violation occurred since the last read of this register (WP_SR) 0x0 WRITE Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) 0x1 RESET Software reset had been performed while Write Protection was enabled (since the last read). 0x2 BOTH Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. 0x3 WP_VSRC Write Protection Violation SouRCe 8 16 read-only TC1 6082J Timer Counter 1 TC TC1_ 0xFFFD4000 0 0x4000 registers CCR0 Channel Control Register (channel = 0) 0x00000000 32 write-only CLKEN Counter Clock Enable Command 0 1 write-only CLKDIS Counter Clock Disable Command 1 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR0 Channel Mode Register (channel = 0) 0x00000004 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDBDIS Counter Clock Disable with RB Loading 7 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write WAVE 15 1 read-write LDRA RA Loading Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 CMR0_WAVE_EQ_1 Channel Mode Register (channel = 0) WAVE_EQ_1 0x00000004 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 ENETRG External Event Trigger Enable 12 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UP_RC UP mode with automatic trigger on RC Compare 0x1 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 WAVE 15 1 read-write ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 CV0 Counter Value (channel = 0) 0x00000010 32 read-only 0x00000000 CV Counter Value 0 16 read-only RA0 Register A (channel = 0) 0x00000014 32 read-write 0x00000000 RA Register A 0 16 read-write RB0 Register B (channel = 0) 0x00000018 32 read-write 0x00000000 RB Register B 0 16 read-write RC0 Register C (channel = 0) 0x0000001C 32 read-write 0x00000000 RC Register C 0 16 read-write SR0 Status Register (channel = 0) 0x00000020 32 read-only 0x00000000 COVFS Counter Overflow Status 0 1 read-only LOVRS Load Overrun Status 1 1 read-only CPAS RA Compare Status 2 1 read-only CPBS RB Compare Status 3 1 read-only CPCS RC Compare Status 4 1 read-only LDRAS RA Loading Status 5 1 read-only LDRBS RB Loading Status 6 1 read-only ETRGS External Trigger Status 7 1 read-only CLKSTA Clock Enabling Status 16 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only IER0 Interrupt Enable Register (channel = 0) 0x00000024 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IDR0 Interrupt Disable Register (channel = 0) 0x00000028 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IMR0 Interrupt Mask Register (channel = 0) 0x0000002C 32 read-only 0x00000000 COVFS Counter Overflow 0 1 read-only LOVRS Load Overrun 1 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only ETRGS External Trigger 7 1 read-only CCR1 Channel Control Register (channel = 1) 0x00000040 32 write-only CLKEN Counter Clock Enable Command 0 1 write-only CLKDIS Counter Clock Disable Command 1 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR1 Channel Mode Register (channel = 1) 0x00000044 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDBDIS Counter Clock Disable with RB Loading 7 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write WAVE 15 1 read-write LDRA RA Loading Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 CMR1_WAVE_EQ_1 Channel Mode Register (channel = 1) WAVE_EQ_1 0x00000044 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 ENETRG External Event Trigger Enable 12 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UP_RC UP mode with automatic trigger on RC Compare 0x1 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 WAVE 15 1 read-write ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 CV1 Counter Value (channel = 1) 0x00000050 32 read-only 0x00000000 CV Counter Value 0 16 read-only RA1 Register A (channel = 1) 0x00000054 32 read-write 0x00000000 RA Register A 0 16 read-write RB1 Register B (channel = 1) 0x00000058 32 read-write 0x00000000 RB Register B 0 16 read-write RC1 Register C (channel = 1) 0x0000005C 32 read-write 0x00000000 RC Register C 0 16 read-write SR1 Status Register (channel = 1) 0x00000060 32 read-only 0x00000000 COVFS Counter Overflow Status 0 1 read-only LOVRS Load Overrun Status 1 1 read-only CPAS RA Compare Status 2 1 read-only CPBS RB Compare Status 3 1 read-only CPCS RC Compare Status 4 1 read-only LDRAS RA Loading Status 5 1 read-only LDRBS RB Loading Status 6 1 read-only ETRGS External Trigger Status 7 1 read-only CLKSTA Clock Enabling Status 16 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only IER1 Interrupt Enable Register (channel = 1) 0x00000064 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IDR1 Interrupt Disable Register (channel = 1) 0x00000068 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IMR1 Interrupt Mask Register (channel = 1) 0x0000006C 32 read-only 0x00000000 COVFS Counter Overflow 0 1 read-only LOVRS Load Overrun 1 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only ETRGS External Trigger 7 1 read-only CCR2 Channel Control Register (channel = 2) 0x00000080 32 write-only CLKEN Counter Clock Enable Command 0 1 write-only CLKDIS Counter Clock Disable Command 1 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR2 Channel Mode Register (channel = 2) 0x00000084 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDBDIS Counter Clock Disable with RB Loading 7 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write WAVE 15 1 read-write LDRA RA Loading Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 CMR2_WAVE_EQ_1 Channel Mode Register (channel = 2) WAVE_EQ_1 0x00000084 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 ENETRG External Event Trigger Enable 12 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UP_RC UP mode with automatic trigger on RC Compare 0x1 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 WAVE 15 1 read-write ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 CV2 Counter Value (channel = 2) 0x00000090 32 read-only 0x00000000 CV Counter Value 0 16 read-only RA2 Register A (channel = 2) 0x00000094 32 read-write 0x00000000 RA Register A 0 16 read-write RB2 Register B (channel = 2) 0x00000098 32 read-write 0x00000000 RB Register B 0 16 read-write RC2 Register C (channel = 2) 0x0000009C 32 read-write 0x00000000 RC Register C 0 16 read-write SR2 Status Register (channel = 2) 0x000000A0 32 read-only 0x00000000 COVFS Counter Overflow Status 0 1 read-only LOVRS Load Overrun Status 1 1 read-only CPAS RA Compare Status 2 1 read-only CPBS RB Compare Status 3 1 read-only CPCS RC Compare Status 4 1 read-only LDRAS RA Loading Status 5 1 read-only LDRBS RB Loading Status 6 1 read-only ETRGS External Trigger Status 7 1 read-only CLKSTA Clock Enabling Status 16 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only IER2 Interrupt Enable Register (channel = 2) 0x000000A4 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IDR2 Interrupt Disable Register (channel = 2) 0x000000A8 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IMR2 Interrupt Mask Register (channel = 2) 0x000000AC 32 read-only 0x00000000 COVFS Counter Overflow 0 1 read-only LOVRS Load Overrun 1 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only ETRGS External Trigger 7 1 read-only BCR Block Control Register 0x000000C0 32 write-only SYNC Synchro Command 0 1 write-only BMR Block Mode Register 0x000000C4 32 read-write 0x00000000 TC0XC0S External Clock Signal 0 Selection 0 2 read-write TCLK0 Signal connected to XC0: TCLK0 0x0 TCLK1 Signal connected to XC0: TCLK1 0x2 TCLK2 Signal connected to XC0: TCLK2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 read-write TCLK0 Signal connected to XC1: TCLK0 0x0 TCLK1 Signal connected to XC1: TCLK1 0x2 TCLK2 Signal connected to XC1: TCLK2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 read-write TCLK0 Signal connected to XC2: TCLK0 0x0 TCLK1 Signal connected to XC2: TCLK1 0x2 TCLK2 Signal connected to XC2: TCLK2 0x3 DDRSDRC1 6304S DDR_SDR SDRAM Controller 1 EBI DDRSDRC1_ 0xFFFFE400 0 0x200 registers MR DDRSDRC Mode Register 0x00000000 32 read-write 0x00000000 MODE DDRSDRC Command Mode 0 3 read-write RTR DDRSDRC Refresh Timer Register 0x00000004 32 read-write 0x00000000 COUNT DDRSDRC Refresh Timer Count 0 12 read-write CR DDRSDRC Configuration Register 0x00000008 32 read-write 0x00007024 NC Number of Column Bits 0 2 read-write NR Number of Row Bits 2 2 read-write CAS CAS Latency 4 3 read-write DLL Reset DLL 7 1 read-write DIC Output Driver Impedance Control 8 1 read-write DIS_DLL Disable DLL 9 1 read-write OCD Off-chip Driver 12 3 read-write EBISHARE External Bus Interface is Shared 16 1 read-write ACTBST ACTIVE Bank X to Burst Stop Read Access Bank Y 18 1 read-write TPR0 DDRSDRC Timing Parameter 0 Register 0x0000000C 32 read-write 0x20227225 TRAS Active to Precharge Delay 0 4 read-write TRCD Row to Column Delay 4 4 read-write TWR Write Recovery Delay 8 4 read-write TRC Row Cycle Delay 12 4 read-write TRP Row Precharge Delay 16 4 read-write TRRD Active bankA to Active bankB 20 4 read-write TWTR Internal Write to Read Delay 24 3 read-write REDUCE_WRRD Reduce Write to Read Delay 27 1 read-write TMRD Load Mode Register Command to Active or Refresh Command 28 4 read-write TPR1 DDRSDRC Timing Parameter 1 Register 0x00000010 32 read-write 0x03C80808 TRFC Row Cycle Delay 0 5 read-write TXSNR Exit Self Refresh Delay to Non-read Command 8 8 read-write TXSRD ExiT Self Refresh Delay to Read Command 16 8 read-write TXP Exit Power-down Delay to First Command 24 4 read-write TPR2 DDRSDRC Timing Parameter 2 Register 0x00000014 32 read-write 0x00002062 TXARD Exit Active Power Down Delay to Read Command in Mode "Fast Exit". 0 4 read-write TXARDS Exit Active Power Down Delay to Read Command in Mode "Slow Exit". 4 4 read-write TRPA Row Precharge All Delay 8 4 read-write TRTP Read to Precharge 12 3 read-write LPR DDRSDRC Low-power Register 0x0000001C 32 read-write 0x00010000 LPCB Low-power Command Bit 0 2 read-write CLK_FR Clock Frozen Command Bit 2 1 read-write PASR Partial Array Self Refresh 4 3 read-write TCR Temperature Compensated Self Refresh 8 2 read-write DS Drive Strength 10 2 read-write TIMEOUT Low Power Mode 12 2 read-write APDE Active Power Down Exit Time 16 1 read-write UPD_MR Update Load Mode Register and Extended Mode Register 20 2 read-write MD DDRSDRC Memory Device Register 0x00000020 32 read-write 0x00000010 MD Memory Device 0 3 read-write DBW Data Bus Width 4 1 read-write DLL DDRSDRC DLL Information Register 0x00000024 32 read-only 0x00000001 MDINC DLL Master Delay Increment 0 1 read-only MDDEC DLL Master Delay Decrement 1 1 read-only MDOVF DLL Master Delay Overflow Flag 2 1 read-only MDVAL DLL Master Delay Value 8 8 read-only HS DDRSDRC High Speed Register 0x0000002C 32 read-write 0x00000000 DIS_ANTICIP_READ Anticip Read Access 2 1 read-write 4 4 0-3 DELAY[%s] DDRSDRC Delay I/O Register 0x00000040 32 read-write DELAY1 Delay1..Delay8 0 4 read-write DELAY2 Delay1..Delay8 4 4 read-write DELAY3 Delay1..Delay8 8 4 read-write DELAY4 Delay1..Delay8 12 4 read-write DELAY5 Delay1..Delay8 16 4 read-write DELAY6 Delay1..Delay8 20 4 read-write DELAY7 Delay1..Delay8 24 4 read-write DELAY8 Delay1..Delay8 28 4 read-write WPMR DDRSDRC Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write WPSR DDRSDRC Write Protect Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only DDRSDRC0 6304S DDR_SDR SDRAM Controller 0 DDRSDRC DDRSDRC0_ 0xFFFFE600 0 0x200 registers MR DDRSDRC Mode Register 0x00000000 32 read-write 0x00000000 MODE DDRSDRC Command Mode 0 3 read-write RTR DDRSDRC Refresh Timer Register 0x00000004 32 read-write 0x00000000 COUNT DDRSDRC Refresh Timer Count 0 12 read-write CR DDRSDRC Configuration Register 0x00000008 32 read-write 0x00007024 NC Number of Column Bits 0 2 read-write NR Number of Row Bits 2 2 read-write CAS CAS Latency 4 3 read-write DLL Reset DLL 7 1 read-write DIC Output Driver Impedance Control 8 1 read-write DIS_DLL Disable DLL 9 1 read-write OCD Off-chip Driver 12 3 read-write EBISHARE External Bus Interface is Shared 16 1 read-write ACTBST ACTIVE Bank X to Burst Stop Read Access Bank Y 18 1 read-write TPR0 DDRSDRC Timing Parameter 0 Register 0x0000000C 32 read-write 0x20227225 TRAS Active to Precharge Delay 0 4 read-write TRCD Row to Column Delay 4 4 read-write TWR Write Recovery Delay 8 4 read-write TRC Row Cycle Delay 12 4 read-write TRP Row Precharge Delay 16 4 read-write TRRD Active bankA to Active bankB 20 4 read-write TWTR Internal Write to Read Delay 24 3 read-write REDUCE_WRRD Reduce Write to Read Delay 27 1 read-write TMRD Load Mode Register Command to Active or Refresh Command 28 4 read-write TPR1 DDRSDRC Timing Parameter 1 Register 0x00000010 32 read-write 0x03C80808 TRFC Row Cycle Delay 0 5 read-write TXSNR Exit Self Refresh Delay to Non-read Command 8 8 read-write TXSRD ExiT Self Refresh Delay to Read Command 16 8 read-write TXP Exit Power-down Delay to First Command 24 4 read-write TPR2 DDRSDRC Timing Parameter 2 Register 0x00000014 32 read-write 0x00002062 TXARD Exit Active Power Down Delay to Read Command in Mode "Fast Exit". 0 4 read-write TXARDS Exit Active Power Down Delay to Read Command in Mode "Slow Exit". 4 4 read-write TRPA Row Precharge All Delay 8 4 read-write TRTP Read to Precharge 12 3 read-write LPR DDRSDRC Low-power Register 0x0000001C 32 read-write 0x00010000 LPCB Low-power Command Bit 0 2 read-write CLK_FR Clock Frozen Command Bit 2 1 read-write PASR Partial Array Self Refresh 4 3 read-write TCR Temperature Compensated Self Refresh 8 2 read-write DS Drive Strength 10 2 read-write TIMEOUT Low Power Mode 12 2 read-write APDE Active Power Down Exit Time 16 1 read-write UPD_MR Update Load Mode Register and Extended Mode Register 20 2 read-write MD DDRSDRC Memory Device Register 0x00000020 32 read-write 0x00000010 MD Memory Device 0 3 read-write DBW Data Bus Width 4 1 read-write DLL DDRSDRC DLL Information Register 0x00000024 32 read-only 0x00000001 MDINC DLL Master Delay Increment 0 1 read-only MDDEC DLL Master Delay Decrement 1 1 read-only MDOVF DLL Master Delay Overflow Flag 2 1 read-only MDVAL DLL Master Delay Value 8 8 read-only HS DDRSDRC High Speed Register 0x0000002C 32 read-write 0x00000000 DIS_ANTICIP_READ Anticip Read Access 2 1 read-write 4 4 0-3 DELAY[%s] DDRSDRC Delay I/O Register 0x00000040 32 read-write DELAY1 Delay1..Delay8 0 4 read-write DELAY2 Delay1..Delay8 4 4 read-write DELAY3 Delay1..Delay8 8 4 read-write DELAY4 Delay1..Delay8 12 4 read-write DELAY5 Delay1..Delay8 16 4 read-write DELAY6 Delay1..Delay8 20 4 read-write DELAY7 Delay1..Delay8 24 4 read-write DELAY8 Delay1..Delay8 28 4 read-write WPMR DDRSDRC Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write WPSR DDRSDRC Write Protect Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only SMC 6105J Static Memory Controller EBI SMC_ 0xFFFFE800 0 0x200 registers SETUP0 SMC Setup Register (CS_number = 0) 0x00000000 32 read-write 0x01010101 NWE_SETUP NWE Setup Length 0 6 read-write NCS_WR_SETUP NCS Setup Length in WRITE Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NCS_RD_SETUP NCS Setup Length in READ Access 24 6 read-write PULSE0 SMC Pulse Register (CS_number = 0) 0x00000004 32 read-write 0x01010101 NWE_PULSE NWE Pulse Length 0 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write CYCLE0 SMC Cycle Register (CS_number = 0) 0x00000008 32 read-write 0x00030003 NWE_CYCLE Total Write Cycle Length 0 9 read-write NRD_CYCLE Total Read Cycle Length 16 9 read-write MODE0 SMC Mode Register (CS_number = 0) 0x0000000C 32 read-write 0x10001000 READ_MODE 0 1 read-write WRITE_MODE 1 1 read-write EXNW_MODE NWAIT Mode 4 2 read-write BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 2 read-write TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write PMEN Page Mode Enabled 24 1 read-write PS Page Size 28 2 read-write SETUP1 SMC Setup Register (CS_number = 1) 0x00000010 32 read-write 0x01010101 NWE_SETUP NWE Setup Length 0 6 read-write NCS_WR_SETUP NCS Setup Length in WRITE Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NCS_RD_SETUP NCS Setup Length in READ Access 24 6 read-write PULSE1 SMC Pulse Register (CS_number = 1) 0x00000014 32 read-write 0x01010101 NWE_PULSE NWE Pulse Length 0 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write CYCLE1 SMC Cycle Register (CS_number = 1) 0x00000018 32 read-write 0x00030003 NWE_CYCLE Total Write Cycle Length 0 9 read-write NRD_CYCLE Total Read Cycle Length 16 9 read-write MODE1 SMC Mode Register (CS_number = 1) 0x0000001C 32 read-write 0x10001000 READ_MODE 0 1 read-write WRITE_MODE 1 1 read-write EXNW_MODE NWAIT Mode 4 2 read-write BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 2 read-write TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write PMEN Page Mode Enabled 24 1 read-write PS Page Size 28 2 read-write SETUP2 SMC Setup Register (CS_number = 2) 0x00000020 32 read-write 0x01010101 NWE_SETUP NWE Setup Length 0 6 read-write NCS_WR_SETUP NCS Setup Length in WRITE Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NCS_RD_SETUP NCS Setup Length in READ Access 24 6 read-write PULSE2 SMC Pulse Register (CS_number = 2) 0x00000024 32 read-write 0x01010101 NWE_PULSE NWE Pulse Length 0 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write CYCLE2 SMC Cycle Register (CS_number = 2) 0x00000028 32 read-write 0x00030003 NWE_CYCLE Total Write Cycle Length 0 9 read-write NRD_CYCLE Total Read Cycle Length 16 9 read-write MODE2 SMC Mode Register (CS_number = 2) 0x0000002C 32 read-write 0x10001000 READ_MODE 0 1 read-write WRITE_MODE 1 1 read-write EXNW_MODE NWAIT Mode 4 2 read-write BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 2 read-write TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write PMEN Page Mode Enabled 24 1 read-write PS Page Size 28 2 read-write SETUP3 SMC Setup Register (CS_number = 3) 0x00000030 32 read-write 0x01010101 NWE_SETUP NWE Setup Length 0 6 read-write NCS_WR_SETUP NCS Setup Length in WRITE Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NCS_RD_SETUP NCS Setup Length in READ Access 24 6 read-write PULSE3 SMC Pulse Register (CS_number = 3) 0x00000034 32 read-write 0x01010101 NWE_PULSE NWE Pulse Length 0 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write CYCLE3 SMC Cycle Register (CS_number = 3) 0x00000038 32 read-write 0x00030003 NWE_CYCLE Total Write Cycle Length 0 9 read-write NRD_CYCLE Total Read Cycle Length 16 9 read-write MODE3 SMC Mode Register (CS_number = 3) 0x0000003C 32 read-write 0x10001000 READ_MODE 0 1 read-write WRITE_MODE 1 1 read-write EXNW_MODE NWAIT Mode 4 2 read-write BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 2 read-write TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write PMEN Page Mode Enabled 24 1 read-write PS Page Size 28 2 read-write SETUP4 SMC Setup Register (CS_number = 4) 0x00000040 32 read-write 0x01010101 NWE_SETUP NWE Setup Length 0 6 read-write NCS_WR_SETUP NCS Setup Length in WRITE Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NCS_RD_SETUP NCS Setup Length in READ Access 24 6 read-write PULSE4 SMC Pulse Register (CS_number = 4) 0x00000044 32 read-write 0x01010101 NWE_PULSE NWE Pulse Length 0 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write CYCLE4 SMC Cycle Register (CS_number = 4) 0x00000048 32 read-write 0x00030003 NWE_CYCLE Total Write Cycle Length 0 9 read-write NRD_CYCLE Total Read Cycle Length 16 9 read-write MODE4 SMC Mode Register (CS_number = 4) 0x0000004C 32 read-write 0x10001000 READ_MODE 0 1 read-write WRITE_MODE 1 1 read-write EXNW_MODE NWAIT Mode 4 2 read-write BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 2 read-write TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write PMEN Page Mode Enabled 24 1 read-write PS Page Size 28 2 read-write SETUP5 SMC Setup Register (CS_number = 5) 0x00000050 32 read-write 0x01010101 NWE_SETUP NWE Setup Length 0 6 read-write NCS_WR_SETUP NCS Setup Length in WRITE Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NCS_RD_SETUP NCS Setup Length in READ Access 24 6 read-write PULSE5 SMC Pulse Register (CS_number = 5) 0x00000054 32 read-write 0x01010101 NWE_PULSE NWE Pulse Length 0 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write CYCLE5 SMC Cycle Register (CS_number = 5) 0x00000058 32 read-write 0x00030003 NWE_CYCLE Total Write Cycle Length 0 9 read-write NRD_CYCLE Total Read Cycle Length 16 9 read-write MODE5 SMC Mode Register (CS_number = 5) 0x0000005C 32 read-write 0x10001000 READ_MODE 0 1 read-write WRITE_MODE 1 1 read-write EXNW_MODE NWAIT Mode 4 2 read-write BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 2 read-write TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write PMEN Page Mode Enabled 24 1 read-write PS Page Size 28 2 read-write DELAY1 SMC Delay on I/O 0x000000C0 32 read-write 0x00000000 Delay1 0 4 read-write Delay2 4 4 read-write Delay3 8 4 read-write Delay4 12 4 read-write Delay5 16 4 read-write Delay6 20 4 read-write Delay7 24 4 read-write Delay8 28 4 read-write DELAY2 SMC Delay on I/O 0x000000C4 32 read-write 0x00000000 DELAY3 SMC Delay on I/O 0x000000C8 32 read-write 0x00000000 DELAY4 SMC Delay on I/O 0x000000CC 32 read-write 0x00000000 DELAY5 SMC Delay on I/O 0x000000D0 32 read-write 0x00000000 DELAY6 SMC Delay on I/O 0x000000D4 32 read-write 0x00000000 DELAY7 SMC Delay on I/O 0x000000D8 32 read-write 0x00000000 DELAY8 SMC Delay on I/O 0x000000DC 32 read-write 0x00000000 MATRIX 6468A AHB Bus Matrix MATRIX_ 0xFFFFEA00 0 0x200 registers 11 4 0-10 MCFG[%s] Master Configuration Register 0x00000000 32 read-write ULBT Undefined Length Burst Type 0 3 read-write 8 4 0-7 SCFG[%s] Slave Configuration Register 0x00000040 32 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 4 read-write PRAS0 Priority Register A for Slave 0 0x00000080 32 read-write 0x00000000 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRBS0 Priority Register B for Slave 0 0x00000084 32 read-write 0x00000000 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write M10PR Master 10 Priority 8 2 read-write PRAS1 Priority Register A for Slave 1 0x00000088 32 read-write 0x00000000 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRBS1 Priority Register B for Slave 1 0x0000008C 32 read-write 0x00000000 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write M10PR Master 10 Priority 8 2 read-write PRAS2 Priority Register A for Slave 2 0x00000090 32 read-write 0x00000000 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRBS2 Priority Register B for Slave 2 0x00000094 32 read-write 0x00000000 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write M10PR Master 10 Priority 8 2 read-write PRAS3 Priority Register A for Slave 3 0x00000098 32 read-write 0x00000000 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRBS3 Priority Register B for Slave 3 0x0000009C 32 read-write 0x00000000 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write M10PR Master 10 Priority 8 2 read-write PRAS4 Priority Register A for Slave 4 0x000000A0 32 read-write 0x00000000 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRBS4 Priority Register B for Slave 4 0x000000A4 32 read-write 0x00000000 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write M10PR Master 10 Priority 8 2 read-write PRAS5 Priority Register A for Slave 5 0x000000A8 32 read-write 0x00000000 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRBS5 Priority Register B for Slave 5 0x000000AC 32 read-write 0x00000000 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write M10PR Master 10 Priority 8 2 read-write PRAS6 Priority Register A for Slave 6 0x000000B0 32 read-write 0x00000000 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRBS6 Priority Register B for Slave 6 0x000000B4 32 read-write 0x00000000 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write M10PR Master 10 Priority 8 2 read-write PRAS7 Priority Register A for Slave 7 0x000000B8 32 read-write 0x00000000 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRBS7 Priority Register B for Slave 7 0x000000BC 32 read-write 0x00000000 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write M10PR Master 10 Priority 8 2 read-write MRCR Master Remap Control Register 0x00000100 32 read-write 0x00000000 RCB0 0 1 read-write RCB1 1 1 read-write RCB2 2 1 read-write RCB3 3 1 read-write RCB4 4 1 read-write RCB5 5 1 read-write RCB6 6 1 read-write RCB7 7 1 read-write RCB8 8 1 read-write RCB9 9 1 read-write RCB10 10 1 read-write WPMR Write Protect Mode Register 0x000001E4 32 read-write 0x00000000 WPEN Write Protect ENable 0 1 read-write WPKEY Write Protect KEY (Write-only) 8 24 read-write WPSR Write Protect Status Register 0x000001E8 32 read-only 0x00000000 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only DMAC 6233G DMA Controller DMAC_ 0xFFFFEC00 0 0x200 registers DMAC 21 GCFG DMAC Global Configuration Register 0x00000000 32 read-write 0x00000010 ARB_CFG 4 1 read-write EN DMAC Enable Register 0x00000004 32 read-write 0x00000000 ENABLE 0 1 read-write SREQ DMAC Software Single Request Register 0x00000008 32 read-write 0x00000000 SSREQ0 0 1 read-write DSREQ0 1 1 read-write SSREQ1 2 1 read-write DSREQ1 3 1 read-write SSREQ2 4 1 read-write DSREQ2 5 1 read-write SSREQ3 6 1 read-write DSREQ3 7 1 read-write SSREQ4 8 1 read-write DSREQ4 9 1 read-write SSREQ5 10 1 read-write DSREQ5 11 1 read-write SSREQ6 12 1 read-write DSREQ6 13 1 read-write SSREQ7 14 1 read-write DSREQ7 15 1 read-write CREQ DMAC Software Chunk Transfer Request Register 0x0000000C 32 read-write 0x00000000 SCREQ0 0 1 read-write DCREQ0 1 1 read-write SCREQ1 2 1 read-write DCREQ1 3 1 read-write SCREQ2 4 1 read-write DCREQ2 5 1 read-write SCREQ3 6 1 read-write DCREQ3 7 1 read-write SCREQ4 8 1 read-write DCREQ4 9 1 read-write SCREQ5 10 1 read-write DCREQ5 11 1 read-write SCREQ6 12 1 read-write DCREQ6 13 1 read-write SCREQ7 14 1 read-write DCREQ7 15 1 read-write LAST DMAC Software Last Transfer Flag Register 0x00000010 32 read-write 0x00000000 SLAST0 0 1 read-write DLAST0 1 1 read-write SLAST1 2 1 read-write DLAST1 3 1 read-write SLAST2 4 1 read-write DLAST2 5 1 read-write SLAST3 6 1 read-write DLAST3 7 1 read-write SLAST4 8 1 read-write DLAST4 9 1 read-write SLAST5 10 1 read-write DLAST5 11 1 read-write SLAST6 12 1 read-write DLAST6 13 1 read-write SLAST7 14 1 read-write DLAST7 15 1 read-write EBCIER DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. 0x00000018 32 write-only BTC0 Buffer Transfer Completed [7:0] 0 1 write-only BTC1 Buffer Transfer Completed [7:0] 1 1 write-only BTC2 Buffer Transfer Completed [7:0] 2 1 write-only BTC3 Buffer Transfer Completed [7:0] 3 1 write-only BTC4 Buffer Transfer Completed [7:0] 4 1 write-only BTC5 Buffer Transfer Completed [7:0] 5 1 write-only BTC6 Buffer Transfer Completed [7:0] 6 1 write-only BTC7 Buffer Transfer Completed [7:0] 7 1 write-only CBTC0 Chained Buffer Transfer Completed [7:0] 8 1 write-only CBTC1 Chained Buffer Transfer Completed [7:0] 9 1 write-only CBTC2 Chained Buffer Transfer Completed [7:0] 10 1 write-only CBTC3 Chained Buffer Transfer Completed [7:0] 11 1 write-only CBTC4 Chained Buffer Transfer Completed [7:0] 12 1 write-only CBTC5 Chained Buffer Transfer Completed [7:0] 13 1 write-only CBTC6 Chained Buffer Transfer Completed [7:0] 14 1 write-only CBTC7 Chained Buffer Transfer Completed [7:0] 15 1 write-only ERR0 Access Error [7:0] 16 1 write-only ERR1 Access Error [7:0] 17 1 write-only ERR2 Access Error [7:0] 18 1 write-only ERR3 Access Error [7:0] 19 1 write-only ERR4 Access Error [7:0] 20 1 write-only ERR5 Access Error [7:0] 21 1 write-only ERR6 Access Error [7:0] 22 1 write-only ERR7 Access Error [7:0] 23 1 write-only EBCIDR DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. 0x0000001C 32 write-only BTC0 Buffer Transfer Completed [7:0] 0 1 write-only BTC1 Buffer Transfer Completed [7:0] 1 1 write-only BTC2 Buffer Transfer Completed [7:0] 2 1 write-only BTC3 Buffer Transfer Completed [7:0] 3 1 write-only BTC4 Buffer Transfer Completed [7:0] 4 1 write-only BTC5 Buffer Transfer Completed [7:0] 5 1 write-only BTC6 Buffer Transfer Completed [7:0] 6 1 write-only BTC7 Buffer Transfer Completed [7:0] 7 1 write-only CBTC0 Chained Buffer Transfer Completed [7:0] 8 1 write-only CBTC1 Chained Buffer Transfer Completed [7:0] 9 1 write-only CBTC2 Chained Buffer Transfer Completed [7:0] 10 1 write-only CBTC3 Chained Buffer Transfer Completed [7:0] 11 1 write-only CBTC4 Chained Buffer Transfer Completed [7:0] 12 1 write-only CBTC5 Chained Buffer Transfer Completed [7:0] 13 1 write-only CBTC6 Chained Buffer Transfer Completed [7:0] 14 1 write-only CBTC7 Chained Buffer Transfer Completed [7:0] 15 1 write-only ERR0 Access Error [7:0] 16 1 write-only ERR1 Access Error [7:0] 17 1 write-only ERR2 Access Error [7:0] 18 1 write-only ERR3 Access Error [7:0] 19 1 write-only ERR4 Access Error [7:0] 20 1 write-only ERR5 Access Error [7:0] 21 1 write-only ERR6 Access Error [7:0] 22 1 write-only ERR7 Access Error [7:0] 23 1 write-only EBCIMR DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. 0x00000020 32 read-only 0x00000000 BTC0 Buffer Transfer Completed [7:0] 0 1 read-only BTC1 Buffer Transfer Completed [7:0] 1 1 read-only BTC2 Buffer Transfer Completed [7:0] 2 1 read-only BTC3 Buffer Transfer Completed [7:0] 3 1 read-only BTC4 Buffer Transfer Completed [7:0] 4 1 read-only BTC5 Buffer Transfer Completed [7:0] 5 1 read-only BTC6 Buffer Transfer Completed [7:0] 6 1 read-only BTC7 Buffer Transfer Completed [7:0] 7 1 read-only CBTC0 Chained Buffer Transfer Completed [7:0] 8 1 read-only CBTC1 Chained Buffer Transfer Completed [7:0] 9 1 read-only CBTC2 Chained Buffer Transfer Completed [7:0] 10 1 read-only CBTC3 Chained Buffer Transfer Completed [7:0] 11 1 read-only CBTC4 Chained Buffer Transfer Completed [7:0] 12 1 read-only CBTC5 Chained Buffer Transfer Completed [7:0] 13 1 read-only CBTC6 Chained Buffer Transfer Completed [7:0] 14 1 read-only CBTC7 Chained Buffer Transfer Completed [7:0] 15 1 read-only ERR0 Access Error [7:0] 16 1 read-only ERR1 Access Error [7:0] 17 1 read-only ERR2 Access Error [7:0] 18 1 read-only ERR3 Access Error [7:0] 19 1 read-only ERR4 Access Error [7:0] 20 1 read-only ERR5 Access Error [7:0] 21 1 read-only ERR6 Access Error [7:0] 22 1 read-only ERR7 Access Error [7:0] 23 1 read-only EBCISR DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. 0x00000024 32 read-only 0x00000000 BTC0 Buffer Transfer Completed [7:0] 0 1 read-only BTC1 Buffer Transfer Completed [7:0] 1 1 read-only BTC2 Buffer Transfer Completed [7:0] 2 1 read-only BTC3 Buffer Transfer Completed [7:0] 3 1 read-only BTC4 Buffer Transfer Completed [7:0] 4 1 read-only BTC5 Buffer Transfer Completed [7:0] 5 1 read-only BTC6 Buffer Transfer Completed [7:0] 6 1 read-only BTC7 Buffer Transfer Completed [7:0] 7 1 read-only CBTC0 Chained Buffer Transfer Completed [7:0] 8 1 read-only CBTC1 Chained Buffer Transfer Completed [7:0] 9 1 read-only CBTC2 Chained Buffer Transfer Completed [7:0] 10 1 read-only CBTC3 Chained Buffer Transfer Completed [7:0] 11 1 read-only CBTC4 Chained Buffer Transfer Completed [7:0] 12 1 read-only CBTC5 Chained Buffer Transfer Completed [7:0] 13 1 read-only CBTC6 Chained Buffer Transfer Completed [7:0] 14 1 read-only CBTC7 Chained Buffer Transfer Completed [7:0] 15 1 read-only ERR0 Access Error [7:0] 16 1 read-only ERR1 Access Error [7:0] 17 1 read-only ERR2 Access Error [7:0] 18 1 read-only ERR3 Access Error [7:0] 19 1 read-only ERR4 Access Error [7:0] 20 1 read-only ERR5 Access Error [7:0] 21 1 read-only ERR6 Access Error [7:0] 22 1 read-only ERR7 Access Error [7:0] 23 1 read-only CHER DMAC Channel Handler Enable Register 0x00000028 32 write-only ENA0 [7:0] 0 1 write-only ENA1 [7:0] 1 1 write-only ENA2 [7:0] 2 1 write-only ENA3 [7:0] 3 1 write-only ENA4 [7:0] 4 1 write-only ENA5 [7:0] 5 1 write-only ENA6 [7:0] 6 1 write-only ENA7 [7:0] 7 1 write-only SUSP0 [7:0] 8 1 write-only SUSP1 [7:0] 9 1 write-only SUSP2 [7:0] 10 1 write-only SUSP3 [7:0] 11 1 write-only SUSP4 [7:0] 12 1 write-only SUSP5 [7:0] 13 1 write-only SUSP6 [7:0] 14 1 write-only SUSP7 [7:0] 15 1 write-only KEEP0 [7:0] 24 1 write-only KEEP1 [7:0] 25 1 write-only KEEP2 [7:0] 26 1 write-only KEEP3 [7:0] 27 1 write-only KEEP4 [7:0] 28 1 write-only KEEP5 [7:0] 29 1 write-only KEEP6 [7:0] 30 1 write-only KEEP7 [7:0] 31 1 write-only CHDR DMAC Channel Handler Disable Register 0x0000002C 32 write-only DIS0 [7:0] 0 1 write-only DIS1 [7:0] 1 1 write-only DIS2 [7:0] 2 1 write-only DIS3 [7:0] 3 1 write-only DIS4 [7:0] 4 1 write-only DIS5 [7:0] 5 1 write-only DIS6 [7:0] 6 1 write-only DIS7 [7:0] 7 1 write-only RES0 [7:0] 8 1 write-only RES1 [7:0] 9 1 write-only RES2 [7:0] 10 1 write-only RES3 [7:0] 11 1 write-only RES4 [7:0] 12 1 write-only RES5 [7:0] 13 1 write-only RES6 [7:0] 14 1 write-only RES7 [7:0] 15 1 write-only CHSR DMAC Channel Handler Status Register 0x00000030 32 read-only 0x00FF0000 ENA0 [7:0] 0 1 read-only ENA1 [7:0] 1 1 read-only ENA2 [7:0] 2 1 read-only ENA3 [7:0] 3 1 read-only ENA4 [7:0] 4 1 read-only ENA5 [7:0] 5 1 read-only ENA6 [7:0] 6 1 read-only ENA7 [7:0] 7 1 read-only SUSP0 [7:0] 8 1 read-only SUSP1 [7:0] 9 1 read-only SUSP2 [7:0] 10 1 read-only SUSP3 [7:0] 11 1 read-only SUSP4 [7:0] 12 1 read-only SUSP5 [7:0] 13 1 read-only SUSP6 [7:0] 14 1 read-only SUSP7 [7:0] 15 1 read-only EMPT0 [7:0] 16 1 read-only EMPT1 [7:0] 17 1 read-only EMPT2 [7:0] 18 1 read-only EMPT3 [7:0] 19 1 read-only EMPT4 [7:0] 20 1 read-only EMPT5 [7:0] 21 1 read-only EMPT6 [7:0] 22 1 read-only EMPT7 [7:0] 23 1 read-only STAL0 [7:0] 24 1 read-only STAL1 [7:0] 25 1 read-only STAL2 [7:0] 26 1 read-only STAL3 [7:0] 27 1 read-only STAL4 [7:0] 28 1 read-only STAL5 [7:0] 29 1 read-only STAL6 [7:0] 30 1 read-only STAL7 [7:0] 31 1 read-only SADDR0 DMAC Channel Source Address Register (ch_num = 0) 0x0000003C 32 read-write 0x00000000 SADDR 0 32 read-write DADDR0 DMAC Channel Destination Address Register (ch_num = 0) 0x00000040 32 read-write 0x00000000 DADDR 0 32 read-write DSCR0 DMAC Channel Descriptor Address Register (ch_num = 0) 0x00000044 32 read-write 0x00000000 DSCR_IF 0 2 read-write AHB_IFO The buffer transfer descriptor is fetched via AHB-Lite Interface 0 0x0 AHB_IF1 The buffer transfer descriptor is fetched via AHB-Lite Interface 1 0x1 AHB_IF2 The buffer transfer descriptor is fetched via AHB-Lite Interface 2 0x2 DSCR 2 30 read-write CTRLA0 DMAC Channel Control A Register (ch_num = 0) 0x00000048 32 read-write 0x00000000 BTSIZE 0 16 read-write SCSIZE 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 CHK_32 32 data transferred 0x4 CHK_64 64 data transferred 0x5 CHK_128 128 data transferred 0x6 CHK_256 256 data transferred 0x7 DCSIZE 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 CHK_32 32 data transferred 0x4 CHK_64 64 data transferred 0x5 CHK_128 128 data transferred 0x6 CHK_256 256 data transferred 0x7 SRC_WIDTH 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DST_WIDTH 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DONE 31 1 read-write CTRLB0 DMAC Channel Control B Register (ch_num = 0) 0x0000004C 32 read-write 0x00000000 SIF Source Interface Selection Field 0 2 read-write AHB_IFO The source transfer is done via AHB-Lite Interface 0 0x0 AHB_IF1 The source transfer is done via AHB-Lite Interface 1 0x1 AHB_IF2 The source transfer is done via AHB-Lite Interface 2 0x2 DIF Destination Interface Selection Field 4 2 read-write AHB_IFO The destination transfer is done via AHB-Lite Interface 0 0x0 AHB_IF1 The destination transfer is done via AHB-Lite Interface 1 0x1 AHB_IF2 The destination transfer is done via AHB-Lite Interface 2 0x2 SRC_DSCR 16 1 read-write DST_DSCR 20 1 read-write FC 21 3 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 PER2MEM_PER_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x4 MEM2PER_PER_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x5 PER2PER_SPER_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x6 PER2PER_DPER_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x7 SRC_INCR 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 DST_INCR 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 IEN 30 1 read-write AUTO 31 1 read-write CFG0 DMAC Channel Configuration Register (ch_num = 0) 0x00000050 32 read-write 0x01000000 SRC_PER 0 4 read-write DST_PER 4 4 read-write SRC_REP 8 1 read-write SRC_H2SEL 9 1 read-write DST_REP 12 1 read-write DST_H2SEL 13 1 read-write SOD 16 1 read-write LOCK_IF 20 1 read-write LOCK_B 21 1 read-write LOCK_IF_L 22 1 read-write AHB_PROT 24 3 read-write FIFOCFG 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 SADDR1 DMAC Channel Source Address Register (ch_num = 1) 0x00000064 32 read-write 0x00000000 SADDR 0 32 read-write DADDR1 DMAC Channel Destination Address Register (ch_num = 1) 0x00000068 32 read-write 0x00000000 DADDR 0 32 read-write DSCR1 DMAC Channel Descriptor Address Register (ch_num = 1) 0x0000006C 32 read-write 0x00000000 DSCR_IF 0 2 read-write AHB_IFO The buffer transfer descriptor is fetched via AHB-Lite Interface 0 0x0 AHB_IF1 The buffer transfer descriptor is fetched via AHB-Lite Interface 1 0x1 AHB_IF2 The buffer transfer descriptor is fetched via AHB-Lite Interface 2 0x2 DSCR 2 30 read-write CTRLA1 DMAC Channel Control A Register (ch_num = 1) 0x00000070 32 read-write 0x00000000 BTSIZE 0 16 read-write SCSIZE 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 CHK_32 32 data transferred 0x4 CHK_64 64 data transferred 0x5 CHK_128 128 data transferred 0x6 CHK_256 256 data transferred 0x7 DCSIZE 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 CHK_32 32 data transferred 0x4 CHK_64 64 data transferred 0x5 CHK_128 128 data transferred 0x6 CHK_256 256 data transferred 0x7 SRC_WIDTH 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DST_WIDTH 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DONE 31 1 read-write CTRLB1 DMAC Channel Control B Register (ch_num = 1) 0x00000074 32 read-write 0x00000000 SIF Source Interface Selection Field 0 2 read-write AHB_IFO The source transfer is done via AHB-Lite Interface 0 0x0 AHB_IF1 The source transfer is done via AHB-Lite Interface 1 0x1 AHB_IF2 The source transfer is done via AHB-Lite Interface 2 0x2 DIF Destination Interface Selection Field 4 2 read-write AHB_IFO The destination transfer is done via AHB-Lite Interface 0 0x0 AHB_IF1 The destination transfer is done via AHB-Lite Interface 1 0x1 AHB_IF2 The destination transfer is done via AHB-Lite Interface 2 0x2 SRC_DSCR 16 1 read-write DST_DSCR 20 1 read-write FC 21 3 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 PER2MEM_PER_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x4 MEM2PER_PER_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x5 PER2PER_SPER_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x6 PER2PER_DPER_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x7 SRC_INCR 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 DST_INCR 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 IEN 30 1 read-write AUTO 31 1 read-write CFG1 DMAC Channel Configuration Register (ch_num = 1) 0x00000078 32 read-write 0x01000000 SRC_PER 0 4 read-write DST_PER 4 4 read-write SRC_REP 8 1 read-write SRC_H2SEL 9 1 read-write DST_REP 12 1 read-write DST_H2SEL 13 1 read-write SOD 16 1 read-write LOCK_IF 20 1 read-write LOCK_B 21 1 read-write LOCK_IF_L 22 1 read-write AHB_PROT 24 3 read-write FIFOCFG 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 SADDR2 DMAC Channel Source Address Register (ch_num = 2) 0x0000008C 32 read-write 0x00000000 SADDR 0 32 read-write DADDR2 DMAC Channel Destination Address Register (ch_num = 2) 0x00000090 32 read-write 0x00000000 DADDR 0 32 read-write DSCR2 DMAC Channel Descriptor Address Register (ch_num = 2) 0x00000094 32 read-write 0x00000000 DSCR_IF 0 2 read-write AHB_IFO The buffer transfer descriptor is fetched via AHB-Lite Interface 0 0x0 AHB_IF1 The buffer transfer descriptor is fetched via AHB-Lite Interface 1 0x1 AHB_IF2 The buffer transfer descriptor is fetched via AHB-Lite Interface 2 0x2 DSCR 2 30 read-write CTRLA2 DMAC Channel Control A Register (ch_num = 2) 0x00000098 32 read-write 0x00000000 BTSIZE 0 16 read-write SCSIZE 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 CHK_32 32 data transferred 0x4 CHK_64 64 data transferred 0x5 CHK_128 128 data transferred 0x6 CHK_256 256 data transferred 0x7 DCSIZE 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 CHK_32 32 data transferred 0x4 CHK_64 64 data transferred 0x5 CHK_128 128 data transferred 0x6 CHK_256 256 data transferred 0x7 SRC_WIDTH 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DST_WIDTH 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DONE 31 1 read-write CTRLB2 DMAC Channel Control B Register (ch_num = 2) 0x0000009C 32 read-write 0x00000000 SIF Source Interface Selection Field 0 2 read-write AHB_IFO The source transfer is done via AHB-Lite Interface 0 0x0 AHB_IF1 The source transfer is done via AHB-Lite Interface 1 0x1 AHB_IF2 The source transfer is done via AHB-Lite Interface 2 0x2 DIF Destination Interface Selection Field 4 2 read-write AHB_IFO The destination transfer is done via AHB-Lite Interface 0 0x0 AHB_IF1 The destination transfer is done via AHB-Lite Interface 1 0x1 AHB_IF2 The destination transfer is done via AHB-Lite Interface 2 0x2 SRC_DSCR 16 1 read-write DST_DSCR 20 1 read-write FC 21 3 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 PER2MEM_PER_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x4 MEM2PER_PER_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x5 PER2PER_SPER_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x6 PER2PER_DPER_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x7 SRC_INCR 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 DST_INCR 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 IEN 30 1 read-write AUTO 31 1 read-write CFG2 DMAC Channel Configuration Register (ch_num = 2) 0x000000A0 32 read-write 0x01000000 SRC_PER 0 4 read-write DST_PER 4 4 read-write SRC_REP 8 1 read-write SRC_H2SEL 9 1 read-write DST_REP 12 1 read-write DST_H2SEL 13 1 read-write SOD 16 1 read-write LOCK_IF 20 1 read-write LOCK_B 21 1 read-write LOCK_IF_L 22 1 read-write AHB_PROT 24 3 read-write FIFOCFG 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 SADDR3 DMAC Channel Source Address Register (ch_num = 3) 0x000000B4 32 read-write 0x00000000 SADDR 0 32 read-write DADDR3 DMAC Channel Destination Address Register (ch_num = 3) 0x000000B8 32 read-write 0x00000000 DADDR 0 32 read-write DSCR3 DMAC Channel Descriptor Address Register (ch_num = 3) 0x000000BC 32 read-write 0x00000000 DSCR_IF 0 2 read-write AHB_IFO The buffer transfer descriptor is fetched via AHB-Lite Interface 0 0x0 AHB_IF1 The buffer transfer descriptor is fetched via AHB-Lite Interface 1 0x1 AHB_IF2 The buffer transfer descriptor is fetched via AHB-Lite Interface 2 0x2 DSCR 2 30 read-write CTRLA3 DMAC Channel Control A Register (ch_num = 3) 0x000000C0 32 read-write 0x00000000 BTSIZE 0 16 read-write SCSIZE 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 CHK_32 32 data transferred 0x4 CHK_64 64 data transferred 0x5 CHK_128 128 data transferred 0x6 CHK_256 256 data transferred 0x7 DCSIZE 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 CHK_32 32 data transferred 0x4 CHK_64 64 data transferred 0x5 CHK_128 128 data transferred 0x6 CHK_256 256 data transferred 0x7 SRC_WIDTH 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DST_WIDTH 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DONE 31 1 read-write CTRLB3 DMAC Channel Control B Register (ch_num = 3) 0x000000C4 32 read-write 0x00000000 SIF Source Interface Selection Field 0 2 read-write AHB_IFO The source transfer is done via AHB-Lite Interface 0 0x0 AHB_IF1 The source transfer is done via AHB-Lite Interface 1 0x1 AHB_IF2 The source transfer is done via AHB-Lite Interface 2 0x2 DIF Destination Interface Selection Field 4 2 read-write AHB_IFO The destination transfer is done via AHB-Lite Interface 0 0x0 AHB_IF1 The destination transfer is done via AHB-Lite Interface 1 0x1 AHB_IF2 The destination transfer is done via AHB-Lite Interface 2 0x2 SRC_DSCR 16 1 read-write DST_DSCR 20 1 read-write FC 21 3 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 PER2MEM_PER_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x4 MEM2PER_PER_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x5 PER2PER_SPER_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x6 PER2PER_DPER_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x7 SRC_INCR 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 DST_INCR 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 IEN 30 1 read-write AUTO 31 1 read-write CFG3 DMAC Channel Configuration Register (ch_num = 3) 0x000000C8 32 read-write 0x01000000 SRC_PER 0 4 read-write DST_PER 4 4 read-write SRC_REP 8 1 read-write SRC_H2SEL 9 1 read-write DST_REP 12 1 read-write DST_H2SEL 13 1 read-write SOD 16 1 read-write LOCK_IF 20 1 read-write LOCK_B 21 1 read-write LOCK_IF_L 22 1 read-write AHB_PROT 24 3 read-write FIFOCFG 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 SADDR4 DMAC Channel Source Address Register (ch_num = 4) 0x000000DC 32 read-write 0x00000000 SADDR 0 32 read-write DADDR4 DMAC Channel Destination Address Register (ch_num = 4) 0x000000E0 32 read-write 0x00000000 DADDR 0 32 read-write DSCR4 DMAC Channel Descriptor Address Register (ch_num = 4) 0x000000E4 32 read-write 0x00000000 DSCR_IF 0 2 read-write AHB_IFO The buffer transfer descriptor is fetched via AHB-Lite Interface 0 0x0 AHB_IF1 The buffer transfer descriptor is fetched via AHB-Lite Interface 1 0x1 AHB_IF2 The buffer transfer descriptor is fetched via AHB-Lite Interface 2 0x2 DSCR 2 30 read-write CTRLA4 DMAC Channel Control A Register (ch_num = 4) 0x000000E8 32 read-write 0x00000000 BTSIZE 0 16 read-write SCSIZE 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 CHK_32 32 data transferred 0x4 CHK_64 64 data transferred 0x5 CHK_128 128 data transferred 0x6 CHK_256 256 data transferred 0x7 DCSIZE 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 CHK_32 32 data transferred 0x4 CHK_64 64 data transferred 0x5 CHK_128 128 data transferred 0x6 CHK_256 256 data transferred 0x7 SRC_WIDTH 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DST_WIDTH 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DONE 31 1 read-write CTRLB4 DMAC Channel Control B Register (ch_num = 4) 0x000000EC 32 read-write 0x00000000 SIF Source Interface Selection Field 0 2 read-write AHB_IFO The source transfer is done via AHB-Lite Interface 0 0x0 AHB_IF1 The source transfer is done via AHB-Lite Interface 1 0x1 AHB_IF2 The source transfer is done via AHB-Lite Interface 2 0x2 DIF Destination Interface Selection Field 4 2 read-write AHB_IFO The destination transfer is done via AHB-Lite Interface 0 0x0 AHB_IF1 The destination transfer is done via AHB-Lite Interface 1 0x1 AHB_IF2 The destination transfer is done via AHB-Lite Interface 2 0x2 SRC_DSCR 16 1 read-write DST_DSCR 20 1 read-write FC 21 3 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 PER2MEM_PER_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x4 MEM2PER_PER_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x5 PER2PER_SPER_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x6 PER2PER_DPER_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x7 SRC_INCR 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 DST_INCR 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 IEN 30 1 read-write AUTO 31 1 read-write CFG4 DMAC Channel Configuration Register (ch_num = 4) 0x000000F0 32 read-write 0x01000000 SRC_PER 0 4 read-write DST_PER 4 4 read-write SRC_REP 8 1 read-write SRC_H2SEL 9 1 read-write DST_REP 12 1 read-write DST_H2SEL 13 1 read-write SOD 16 1 read-write LOCK_IF 20 1 read-write LOCK_B 21 1 read-write LOCK_IF_L 22 1 read-write AHB_PROT 24 3 read-write FIFOCFG 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 SADDR5 DMAC Channel Source Address Register (ch_num = 5) 0x00000104 32 read-write 0x00000000 SADDR 0 32 read-write DADDR5 DMAC Channel Destination Address Register (ch_num = 5) 0x00000108 32 read-write 0x00000000 DADDR 0 32 read-write DSCR5 DMAC Channel Descriptor Address Register (ch_num = 5) 0x0000010C 32 read-write 0x00000000 DSCR_IF 0 2 read-write AHB_IFO The buffer transfer descriptor is fetched via AHB-Lite Interface 0 0x0 AHB_IF1 The buffer transfer descriptor is fetched via AHB-Lite Interface 1 0x1 AHB_IF2 The buffer transfer descriptor is fetched via AHB-Lite Interface 2 0x2 DSCR 2 30 read-write CTRLA5 DMAC Channel Control A Register (ch_num = 5) 0x00000110 32 read-write 0x00000000 BTSIZE 0 16 read-write SCSIZE 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 CHK_32 32 data transferred 0x4 CHK_64 64 data transferred 0x5 CHK_128 128 data transferred 0x6 CHK_256 256 data transferred 0x7 DCSIZE 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 CHK_32 32 data transferred 0x4 CHK_64 64 data transferred 0x5 CHK_128 128 data transferred 0x6 CHK_256 256 data transferred 0x7 SRC_WIDTH 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DST_WIDTH 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DONE 31 1 read-write CTRLB5 DMAC Channel Control B Register (ch_num = 5) 0x00000114 32 read-write 0x00000000 SIF Source Interface Selection Field 0 2 read-write AHB_IFO The source transfer is done via AHB-Lite Interface 0 0x0 AHB_IF1 The source transfer is done via AHB-Lite Interface 1 0x1 AHB_IF2 The source transfer is done via AHB-Lite Interface 2 0x2 DIF Destination Interface Selection Field 4 2 read-write AHB_IFO The destination transfer is done via AHB-Lite Interface 0 0x0 AHB_IF1 The destination transfer is done via AHB-Lite Interface 1 0x1 AHB_IF2 The destination transfer is done via AHB-Lite Interface 2 0x2 SRC_DSCR 16 1 read-write DST_DSCR 20 1 read-write FC 21 3 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 PER2MEM_PER_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x4 MEM2PER_PER_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x5 PER2PER_SPER_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x6 PER2PER_DPER_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x7 SRC_INCR 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 DST_INCR 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 IEN 30 1 read-write AUTO 31 1 read-write CFG5 DMAC Channel Configuration Register (ch_num = 5) 0x00000118 32 read-write 0x01000000 SRC_PER 0 4 read-write DST_PER 4 4 read-write SRC_REP 8 1 read-write SRC_H2SEL 9 1 read-write DST_REP 12 1 read-write DST_H2SEL 13 1 read-write SOD 16 1 read-write LOCK_IF 20 1 read-write LOCK_B 21 1 read-write LOCK_IF_L 22 1 read-write AHB_PROT 24 3 read-write FIFOCFG 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 SADDR6 DMAC Channel Source Address Register (ch_num = 6) 0x0000012C 32 read-write 0x00000000 SADDR 0 32 read-write DADDR6 DMAC Channel Destination Address Register (ch_num = 6) 0x00000130 32 read-write 0x00000000 DADDR 0 32 read-write DSCR6 DMAC Channel Descriptor Address Register (ch_num = 6) 0x00000134 32 read-write 0x00000000 DSCR_IF 0 2 read-write AHB_IFO The buffer transfer descriptor is fetched via AHB-Lite Interface 0 0x0 AHB_IF1 The buffer transfer descriptor is fetched via AHB-Lite Interface 1 0x1 AHB_IF2 The buffer transfer descriptor is fetched via AHB-Lite Interface 2 0x2 DSCR 2 30 read-write CTRLA6 DMAC Channel Control A Register (ch_num = 6) 0x00000138 32 read-write 0x00000000 BTSIZE 0 16 read-write SCSIZE 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 CHK_32 32 data transferred 0x4 CHK_64 64 data transferred 0x5 CHK_128 128 data transferred 0x6 CHK_256 256 data transferred 0x7 DCSIZE 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 CHK_32 32 data transferred 0x4 CHK_64 64 data transferred 0x5 CHK_128 128 data transferred 0x6 CHK_256 256 data transferred 0x7 SRC_WIDTH 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DST_WIDTH 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DONE 31 1 read-write CTRLB6 DMAC Channel Control B Register (ch_num = 6) 0x0000013C 32 read-write 0x00000000 SIF Source Interface Selection Field 0 2 read-write AHB_IFO The source transfer is done via AHB-Lite Interface 0 0x0 AHB_IF1 The source transfer is done via AHB-Lite Interface 1 0x1 AHB_IF2 The source transfer is done via AHB-Lite Interface 2 0x2 DIF Destination Interface Selection Field 4 2 read-write AHB_IFO The destination transfer is done via AHB-Lite Interface 0 0x0 AHB_IF1 The destination transfer is done via AHB-Lite Interface 1 0x1 AHB_IF2 The destination transfer is done via AHB-Lite Interface 2 0x2 SRC_DSCR 16 1 read-write DST_DSCR 20 1 read-write FC 21 3 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 PER2MEM_PER_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x4 MEM2PER_PER_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x5 PER2PER_SPER_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x6 PER2PER_DPER_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x7 SRC_INCR 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 DST_INCR 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 IEN 30 1 read-write AUTO 31 1 read-write CFG6 DMAC Channel Configuration Register (ch_num = 6) 0x00000140 32 read-write 0x01000000 SRC_PER 0 4 read-write DST_PER 4 4 read-write SRC_REP 8 1 read-write SRC_H2SEL 9 1 read-write DST_REP 12 1 read-write DST_H2SEL 13 1 read-write SOD 16 1 read-write LOCK_IF 20 1 read-write LOCK_B 21 1 read-write LOCK_IF_L 22 1 read-write AHB_PROT 24 3 read-write FIFOCFG 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 SADDR7 DMAC Channel Source Address Register (ch_num = 7) 0x00000154 32 read-write 0x00000000 SADDR 0 32 read-write DADDR7 DMAC Channel Destination Address Register (ch_num = 7) 0x00000158 32 read-write 0x00000000 DADDR 0 32 read-write DSCR7 DMAC Channel Descriptor Address Register (ch_num = 7) 0x0000015C 32 read-write 0x00000000 DSCR_IF 0 2 read-write AHB_IFO The buffer transfer descriptor is fetched via AHB-Lite Interface 0 0x0 AHB_IF1 The buffer transfer descriptor is fetched via AHB-Lite Interface 1 0x1 AHB_IF2 The buffer transfer descriptor is fetched via AHB-Lite Interface 2 0x2 DSCR 2 30 read-write CTRLA7 DMAC Channel Control A Register (ch_num = 7) 0x00000160 32 read-write 0x00000000 BTSIZE 0 16 read-write SCSIZE 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 CHK_32 32 data transferred 0x4 CHK_64 64 data transferred 0x5 CHK_128 128 data transferred 0x6 CHK_256 256 data transferred 0x7 DCSIZE 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 CHK_32 32 data transferred 0x4 CHK_64 64 data transferred 0x5 CHK_128 128 data transferred 0x6 CHK_256 256 data transferred 0x7 SRC_WIDTH 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DST_WIDTH 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DONE 31 1 read-write CTRLB7 DMAC Channel Control B Register (ch_num = 7) 0x00000164 32 read-write 0x00000000 SIF Source Interface Selection Field 0 2 read-write AHB_IFO The source transfer is done via AHB-Lite Interface 0 0x0 AHB_IF1 The source transfer is done via AHB-Lite Interface 1 0x1 AHB_IF2 The source transfer is done via AHB-Lite Interface 2 0x2 DIF Destination Interface Selection Field 4 2 read-write AHB_IFO The destination transfer is done via AHB-Lite Interface 0 0x0 AHB_IF1 The destination transfer is done via AHB-Lite Interface 1 0x1 AHB_IF2 The destination transfer is done via AHB-Lite Interface 2 0x2 SRC_DSCR 16 1 read-write DST_DSCR 20 1 read-write FC 21 3 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 PER2MEM_PER_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x4 MEM2PER_PER_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x5 PER2PER_SPER_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x6 PER2PER_DPER_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x7 SRC_INCR 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 DST_INCR 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 IEN 30 1 read-write AUTO 31 1 read-write CFG7 DMAC Channel Configuration Register (ch_num = 7) 0x00000168 32 read-write 0x01000000 SRC_PER 0 4 read-write DST_PER 4 4 read-write SRC_REP 8 1 read-write SRC_H2SEL 9 1 read-write DST_REP 12 1 read-write DST_H2SEL 13 1 read-write SOD 16 1 read-write LOCK_IF 20 1 read-write LOCK_B 21 1 read-write LOCK_IF_L 22 1 read-write AHB_PROT 24 3 read-write FIFOCFG 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 WPMR Write Protect Mode Register 0x000001E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY 8 24 read-write WPSR Write Protect Status Register 0x000001E8 32 read-only 0x00000000 WPVS 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only DBGU 6059K Debug Unit DBGU_ 0xFFFFEE00 0 0x200 registers CR Control Register 0x00000000 32 write-only RSTRX Reset Receiver 2 1 write-only RSTTX Reset Transmitter 3 1 write-only RXEN Receiver Enable 4 1 write-only RXDIS Receiver Disable 5 1 write-only TXEN Transmitter Enable 6 1 write-only TXDIS Transmitter Disable 7 1 write-only RSTSTA Reset Status Bits 8 1 write-only MR Mode Register 0x00000004 32 read-write 0x00000000 PAR Parity Type 9 3 read-write CHMODE Channel Mode 14 2 read-write IER Interrupt Enable Register 0x00000008 32 write-only RXRDY Enable RXRDY Interrupt 0 1 write-only TXRDY Enable TXRDY Interrupt 1 1 write-only ENDRX Enable End of Receive Transfer Interrupt 3 1 write-only ENDTX Enable End of Transmit Interrupt 4 1 write-only OVRE Enable Overrun Error Interrupt 5 1 write-only FRAME Enable Framing Error Interrupt 6 1 write-only PARE Enable Parity Error Interrupt 7 1 write-only TXEMPTY Enable TXEMPTY Interrupt 9 1 write-only TXBUFE Enable Buffer Empty Interrupt 11 1 write-only RXBUFF Enable Buffer Full Interrupt 12 1 write-only COMMTX Enable COMMTX (from ARM) Interrupt 30 1 write-only COMMRX Enable COMMRX (from ARM) Interrupt 31 1 write-only IDR Interrupt Disable Register 0x0000000C 32 write-only RXRDY Disable RXRDY Interrupt 0 1 write-only TXRDY Disable TXRDY Interrupt 1 1 write-only ENDRX Disable End of Receive Transfer Interrupt 3 1 write-only ENDTX Disable End of Transmit Interrupt 4 1 write-only OVRE Disable Overrun Error Interrupt 5 1 write-only FRAME Disable Framing Error Interrupt 6 1 write-only PARE Disable Parity Error Interrupt 7 1 write-only TXEMPTY Disable TXEMPTY Interrupt 9 1 write-only TXBUFE Disable Buffer Empty Interrupt 11 1 write-only RXBUFF Disable Buffer Full Interrupt 12 1 write-only COMMTX Disable COMMTX (from ARM) Interrupt 30 1 write-only COMMRX Disable COMMRX (from ARM) Interrupt 31 1 write-only IMR Interrupt Mask Register 0x00000010 32 read-only 0x00000000 RXRDY Mask RXRDY Interrupt 0 1 read-only TXRDY Disable TXRDY Interrupt 1 1 read-only ENDRX Mask End of Receive Transfer Interrupt 3 1 read-only ENDTX Mask End of Transmit Interrupt 4 1 read-only OVRE Mask Overrun Error Interrupt 5 1 read-only FRAME Mask Framing Error Interrupt 6 1 read-only PARE Mask Parity Error Interrupt 7 1 read-only TXEMPTY Mask TXEMPTY Interrupt 9 1 read-only TXBUFE Mask TXBUFE Interrupt 11 1 read-only RXBUFF Mask RXBUFF Interrupt 12 1 read-only COMMTX Mask COMMTX Interrupt 30 1 read-only COMMRX Mask COMMRX Interrupt 31 1 read-only SR Status Register 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only ENDRX End of Receiver Transfer 3 1 read-only ENDTX End of Transmitter Transfer 4 1 read-only OVRE Overrun Error 5 1 read-only FRAME Framing Error 6 1 read-only PARE Parity Error 7 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXBUFE Transmission Buffer Empty 11 1 read-only RXBUFF Receive Buffer Full 12 1 read-only COMMTX Debug Communication Channel Write Status 30 1 read-only COMMRX Debug Communication Channel Read Status 31 1 read-only RHR Receive Holding Register 0x00000018 32 read-only 0x00000000 RXCHR Received Character 0 8 read-only THR Transmit Holding Register 0x0000001C 32 write-only TXCHR Character to be Transmitted 0 8 write-only BRGR Baud Rate Generator Register 0x00000020 32 read-write 0x00000000 CD Clock Divisor 0 16 read-write CIDR Chip ID Register 0x00000040 32 read-only VERSION Version of the Device 0 5 read-only EPROC Embedded Processor 5 3 read-only NVPSIZ Nonvolatile Program Memory Size 8 4 read-only NVPSIZ2 12 4 read-only SRAMSIZ Internal SRAM Size 16 4 read-only ARCH Architecture Identifier 20 8 read-only NVPTYP Nonvolatile Program Memory Type 28 3 read-only EXT Extension Flag 31 1 read-only EXID Chip ID Extension Register 0x00000044 32 read-only EXID Chip ID Extension 0 32 read-only FNR Force NTRST Register 0x00000048 32 read-write 0x00000000 FNTRST Force NTRST 0 1 read-write RPR Receive Pointer Register 0x00000100 32 read-write 0x00000000 RXPTR Receive Pointer Register 0 32 read-write RCR Receive Counter Register 0x00000104 32 read-write 0x00000000 RXCTR Receive Counter Register 0 16 read-write TPR Transmit Pointer Register 0x00000108 32 read-write 0x00000000 TXPTR Transmit Counter Register 0 32 read-write TCR Transmit Counter Register 0x0000010C 32 read-write 0x00000000 TXCTR Transmit Counter Register 0 16 read-write RNPR Receive Next Pointer Register 0x00000110 32 read-write 0x00000000 RXNPTR Receive Next Pointer 0 32 read-write RNCR Receive Next Counter Register 0x00000114 32 read-write 0x00000000 RXNCTR Receive Next Counter 0 16 read-write TNPR Transmit Next Pointer Register 0x00000118 32 read-write 0x00000000 TXNPTR Transmit Next Pointer 0 32 read-write TNCR Transmit Next Counter Register 0x0000011C 32 read-write 0x00000000 TXNCTR Transmit Counter Next 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only AIC 6075F Advanced Interrupt Controller AIC_ 0xFFFFF000 0 0x200 registers FIQ 0 IRQ 31 32 4 0-31 SMR[%s] Source Mode Register 0x00000000 32 read-write PRIOR Priority Level 0 3 read-write SRCTYPE Interrupt Source Type 5 2 read-write 32 4 0-31 SVR[%s] Source Vector Register 0x00000080 32 read-write VECTOR Source Vector 0 32 read-write IVR Interrupt Vector Register 0x00000100 32 read-only 0x00000000 IRQV Interrupt Vector Register 0 32 read-only FVR FIQ Interrupt Vector Register 0x00000104 32 read-only 0x00000000 FIQV FIQ Vector Register 0 32 read-only ISR Interrupt Status Register 0x00000108 32 read-only 0x00000000 IRQID Current Interrupt Identifier 0 5 read-only IPR Interrupt Pending Register 0x0000010C 32 read-only 0x00000000 FIQ Interrupt Pending 0 1 read-only SYS Interrupt Pending 1 1 read-only PID2 Interrupt Pending 2 1 read-only PID3 Interrupt Pending 3 1 read-only PID4 Interrupt Pending 4 1 read-only PID5 Interrupt Pending 5 1 read-only PID6 Interrupt Pending 6 1 read-only PID7 Interrupt Pending 7 1 read-only PID8 Interrupt Pending 8 1 read-only PID9 Interrupt Pending 9 1 read-only PID10 Interrupt Pending 10 1 read-only PID11 Interrupt Pending 11 1 read-only PID12 Interrupt Pending 12 1 read-only PID13 Interrupt Pending 13 1 read-only PID14 Interrupt Pending 14 1 read-only PID15 Interrupt Pending 15 1 read-only PID16 Interrupt Pending 16 1 read-only PID17 Interrupt Pending 17 1 read-only PID18 Interrupt Pending 18 1 read-only PID19 Interrupt Pending 19 1 read-only PID20 Interrupt Pending 20 1 read-only PID21 Interrupt Pending 21 1 read-only PID22 Interrupt Pending 22 1 read-only PID23 Interrupt Pending 23 1 read-only PID24 Interrupt Pending 24 1 read-only PID25 Interrupt Pending 25 1 read-only PID26 Interrupt Pending 26 1 read-only PID27 Interrupt Pending 27 1 read-only PID28 Interrupt Pending 28 1 read-only PID29 Interrupt Pending 29 1 read-only PID30 Interrupt Pending 30 1 read-only PID31 Interrupt Pending 31 1 read-only IMR Interrupt Mask Register 0x00000110 32 read-only 0x00000000 FIQ Interrupt Mask 0 1 read-only SYS Interrupt Mask 1 1 read-only PID2 Interrupt Mask 2 1 read-only PID3 Interrupt Mask 3 1 read-only PID4 Interrupt Mask 4 1 read-only PID5 Interrupt Mask 5 1 read-only PID6 Interrupt Mask 6 1 read-only PID7 Interrupt Mask 7 1 read-only PID8 Interrupt Mask 8 1 read-only PID9 Interrupt Mask 9 1 read-only PID10 Interrupt Mask 10 1 read-only PID11 Interrupt Mask 11 1 read-only PID12 Interrupt Mask 12 1 read-only PID13 Interrupt Mask 13 1 read-only PID14 Interrupt Mask 14 1 read-only PID15 Interrupt Mask 15 1 read-only PID16 Interrupt Mask 16 1 read-only PID17 Interrupt Mask 17 1 read-only PID18 Interrupt Mask 18 1 read-only PID19 Interrupt Mask 19 1 read-only PID20 Interrupt Mask 20 1 read-only PID21 Interrupt Mask 21 1 read-only PID22 Interrupt Mask 22 1 read-only PID23 Interrupt Mask 23 1 read-only PID24 Interrupt Mask 24 1 read-only PID25 Interrupt Mask 25 1 read-only PID26 Interrupt Mask 26 1 read-only PID27 Interrupt Mask 27 1 read-only PID28 Interrupt Mask 28 1 read-only PID29 Interrupt Mask 29 1 read-only PID30 Interrupt Mask 30 1 read-only PID31 Interrupt Mask 31 1 read-only CISR Core Interrupt Status Register 0x00000114 32 read-only 0x00000000 NFIQ NFIQ Status 0 1 read-only NIRQ NIRQ Status 1 1 read-only IECR Interrupt Enable Command Register 0x00000120 32 write-only FIQ Interrupt Enable 0 1 write-only SYS Interrupt Enable 1 1 write-only PID2 Interrupt Enable 2 1 write-only PID3 Interrupt Enable 3 1 write-only PID4 Interrupt Enable 4 1 write-only PID5 Interrupt Enable 5 1 write-only PID6 Interrupt Enable 6 1 write-only PID7 Interrupt Enable 7 1 write-only PID8 Interrupt Enable 8 1 write-only PID9 Interrupt Enable 9 1 write-only PID10 Interrupt Enable 10 1 write-only PID11 Interrupt Enable 11 1 write-only PID12 Interrupt Enable 12 1 write-only PID13 Interrupt Enable 13 1 write-only PID14 Interrupt Enable 14 1 write-only PID15 Interrupt Enable 15 1 write-only PID16 Interrupt Enable 16 1 write-only PID17 Interrupt Enable 17 1 write-only PID18 Interrupt Enable 18 1 write-only PID19 Interrupt Enable 19 1 write-only PID20 Interrupt Enable 20 1 write-only PID21 Interrupt Enable 21 1 write-only PID22 Interrupt Enable 22 1 write-only PID23 Interrupt Enable 23 1 write-only PID24 Interrupt Enable 24 1 write-only PID25 Interrupt Enable 25 1 write-only PID26 Interrupt Enable 26 1 write-only PID27 Interrupt Enable 27 1 write-only PID28 Interrupt Enable 28 1 write-only PID29 Interrupt Enable 29 1 write-only PID30 Interrupt Enable 30 1 write-only PID31 Interrupt Enable 31 1 write-only IDCR Interrupt Disable Command Register 0x00000124 32 write-only FIQ Interrupt Disable 0 1 write-only SYS Interrupt Disable 1 1 write-only PID2 Interrupt Disable 2 1 write-only PID3 Interrupt Disable 3 1 write-only PID4 Interrupt Disable 4 1 write-only PID5 Interrupt Disable 5 1 write-only PID6 Interrupt Disable 6 1 write-only PID7 Interrupt Disable 7 1 write-only PID8 Interrupt Disable 8 1 write-only PID9 Interrupt Disable 9 1 write-only PID10 Interrupt Disable 10 1 write-only PID11 Interrupt Disable 11 1 write-only PID12 Interrupt Disable 12 1 write-only PID13 Interrupt Disable 13 1 write-only PID14 Interrupt Disable 14 1 write-only PID15 Interrupt Disable 15 1 write-only PID16 Interrupt Disable 16 1 write-only PID17 Interrupt Disable 17 1 write-only PID18 Interrupt Disable 18 1 write-only PID19 Interrupt Disable 19 1 write-only PID20 Interrupt Disable 20 1 write-only PID21 Interrupt Disable 21 1 write-only PID22 Interrupt Disable 22 1 write-only PID23 Interrupt Disable 23 1 write-only PID24 Interrupt Disable 24 1 write-only PID25 Interrupt Disable 25 1 write-only PID26 Interrupt Disable 26 1 write-only PID27 Interrupt Disable 27 1 write-only PID28 Interrupt Disable 28 1 write-only PID29 Interrupt Disable 29 1 write-only PID30 Interrupt Disable 30 1 write-only PID31 Interrupt Disable 31 1 write-only ICCR Interrupt Clear Command Register 0x00000128 32 write-only FIQ Interrupt Clear 0 1 write-only SYS Interrupt Clear 1 1 write-only PID2 Interrupt Clear 2 1 write-only PID3 Interrupt Clear 3 1 write-only PID4 Interrupt Clear 4 1 write-only PID5 Interrupt Clear 5 1 write-only PID6 Interrupt Clear 6 1 write-only PID7 Interrupt Clear 7 1 write-only PID8 Interrupt Clear 8 1 write-only PID9 Interrupt Clear 9 1 write-only PID10 Interrupt Clear 10 1 write-only PID11 Interrupt Clear 11 1 write-only PID12 Interrupt Clear 12 1 write-only PID13 Interrupt Clear 13 1 write-only PID14 Interrupt Clear 14 1 write-only PID15 Interrupt Clear 15 1 write-only PID16 Interrupt Clear 16 1 write-only PID17 Interrupt Clear 17 1 write-only PID18 Interrupt Clear 18 1 write-only PID19 Interrupt Clear 19 1 write-only PID20 Interrupt Clear 20 1 write-only PID21 Interrupt Clear 21 1 write-only PID22 Interrupt Clear 22 1 write-only PID23 Interrupt Clear 23 1 write-only PID24 Interrupt Clear 24 1 write-only PID25 Interrupt Clear 25 1 write-only PID26 Interrupt Clear 26 1 write-only PID27 Interrupt Clear 27 1 write-only PID28 Interrupt Clear 28 1 write-only PID29 Interrupt Clear 29 1 write-only PID30 Interrupt Clear 30 1 write-only PID31 Interrupt Clear 31 1 write-only ISCR Interrupt Set Command Register 0x0000012C 32 write-only FIQ Interrupt Set 0 1 write-only SYS Interrupt Set 1 1 write-only PID2 Interrupt Set 2 1 write-only PID3 Interrupt Set 3 1 write-only PID4 Interrupt Set 4 1 write-only PID5 Interrupt Set 5 1 write-only PID6 Interrupt Set 6 1 write-only PID7 Interrupt Set 7 1 write-only PID8 Interrupt Set 8 1 write-only PID9 Interrupt Set 9 1 write-only PID10 Interrupt Set 10 1 write-only PID11 Interrupt Set 11 1 write-only PID12 Interrupt Set 12 1 write-only PID13 Interrupt Set 13 1 write-only PID14 Interrupt Set 14 1 write-only PID15 Interrupt Set 15 1 write-only PID16 Interrupt Set 16 1 write-only PID17 Interrupt Set 17 1 write-only PID18 Interrupt Set 18 1 write-only PID19 Interrupt Set 19 1 write-only PID20 Interrupt Set 20 1 write-only PID21 Interrupt Set 21 1 write-only PID22 Interrupt Set 22 1 write-only PID23 Interrupt Set 23 1 write-only PID24 Interrupt Set 24 1 write-only PID25 Interrupt Set 25 1 write-only PID26 Interrupt Set 26 1 write-only PID27 Interrupt Set 27 1 write-only PID28 Interrupt Set 28 1 write-only PID29 Interrupt Set 29 1 write-only PID30 Interrupt Set 30 1 write-only PID31 Interrupt Set 31 1 write-only EOICR End of Interrupt Command Register 0x00000130 32 write-only SPU Spurious Interrupt Vector Register 0x00000134 32 read-write 0x00000000 SIVR Spurious Interrupt Vector Register 0 32 read-write DCR Debug Control Register 0x00000138 32 read-write 0x00000000 PROT Protection Mode 0 1 read-write GMSK General Mask 1 1 read-write FFER Fast Forcing Enable Register 0x00000140 32 write-only SYS Fast Forcing Enable 1 1 write-only PID2 Fast Forcing Enable 2 1 write-only PID3 Fast Forcing Enable 3 1 write-only PID4 Fast Forcing Enable 4 1 write-only PID5 Fast Forcing Enable 5 1 write-only PID6 Fast Forcing Enable 6 1 write-only PID7 Fast Forcing Enable 7 1 write-only PID8 Fast Forcing Enable 8 1 write-only PID9 Fast Forcing Enable 9 1 write-only PID10 Fast Forcing Enable 10 1 write-only PID11 Fast Forcing Enable 11 1 write-only PID12 Fast Forcing Enable 12 1 write-only PID13 Fast Forcing Enable 13 1 write-only PID14 Fast Forcing Enable 14 1 write-only PID15 Fast Forcing Enable 15 1 write-only PID16 Fast Forcing Enable 16 1 write-only PID17 Fast Forcing Enable 17 1 write-only PID18 Fast Forcing Enable 18 1 write-only PID19 Fast Forcing Enable 19 1 write-only PID20 Fast Forcing Enable 20 1 write-only PID21 Fast Forcing Enable 21 1 write-only PID22 Fast Forcing Enable 22 1 write-only PID23 Fast Forcing Enable 23 1 write-only PID24 Fast Forcing Enable 24 1 write-only PID25 Fast Forcing Enable 25 1 write-only PID26 Fast Forcing Enable 26 1 write-only PID27 Fast Forcing Enable 27 1 write-only PID28 Fast Forcing Enable 28 1 write-only PID29 Fast Forcing Enable 29 1 write-only PID30 Fast Forcing Enable 30 1 write-only PID31 Fast Forcing Enable 31 1 write-only FFDR Fast Forcing Disable Register 0x00000144 32 write-only SYS Fast Forcing Disable 1 1 write-only PID2 Fast Forcing Disable 2 1 write-only PID3 Fast Forcing Disable 3 1 write-only PID4 Fast Forcing Disable 4 1 write-only PID5 Fast Forcing Disable 5 1 write-only PID6 Fast Forcing Disable 6 1 write-only PID7 Fast Forcing Disable 7 1 write-only PID8 Fast Forcing Disable 8 1 write-only PID9 Fast Forcing Disable 9 1 write-only PID10 Fast Forcing Disable 10 1 write-only PID11 Fast Forcing Disable 11 1 write-only PID12 Fast Forcing Disable 12 1 write-only PID13 Fast Forcing Disable 13 1 write-only PID14 Fast Forcing Disable 14 1 write-only PID15 Fast Forcing Disable 15 1 write-only PID16 Fast Forcing Disable 16 1 write-only PID17 Fast Forcing Disable 17 1 write-only PID18 Fast Forcing Disable 18 1 write-only PID19 Fast Forcing Disable 19 1 write-only PID20 Fast Forcing Disable 20 1 write-only PID21 Fast Forcing Disable 21 1 write-only PID22 Fast Forcing Disable 22 1 write-only PID23 Fast Forcing Disable 23 1 write-only PID24 Fast Forcing Disable 24 1 write-only PID25 Fast Forcing Disable 25 1 write-only PID26 Fast Forcing Disable 26 1 write-only PID27 Fast Forcing Disable 27 1 write-only PID28 Fast Forcing Disable 28 1 write-only PID29 Fast Forcing Disable 29 1 write-only PID30 Fast Forcing Disable 30 1 write-only PID31 Fast Forcing Disable 31 1 write-only FFSR Fast Forcing Status Register 0x00000148 32 read-only 0x00000000 SYS Fast Forcing Status 1 1 read-only PID2 Fast Forcing Status 2 1 read-only PID3 Fast Forcing Status 3 1 read-only PID4 Fast Forcing Status 4 1 read-only PID5 Fast Forcing Status 5 1 read-only PID6 Fast Forcing Status 6 1 read-only PID7 Fast Forcing Status 7 1 read-only PID8 Fast Forcing Status 8 1 read-only PID9 Fast Forcing Status 9 1 read-only PID10 Fast Forcing Status 10 1 read-only PID11 Fast Forcing Status 11 1 read-only PID12 Fast Forcing Status 12 1 read-only PID13 Fast Forcing Status 13 1 read-only PID14 Fast Forcing Status 14 1 read-only PID15 Fast Forcing Status 15 1 read-only PID16 Fast Forcing Status 16 1 read-only PID17 Fast Forcing Status 17 1 read-only PID18 Fast Forcing Status 18 1 read-only PID19 Fast Forcing Status 19 1 read-only PID20 Fast Forcing Status 20 1 read-only PID21 Fast Forcing Status 21 1 read-only PID22 Fast Forcing Status 22 1 read-only PID23 Fast Forcing Status 23 1 read-only PID24 Fast Forcing Status 24 1 read-only PID25 Fast Forcing Status 25 1 read-only PID26 Fast Forcing Status 26 1 read-only PID27 Fast Forcing Status 27 1 read-only PID28 Fast Forcing Status 28 1 read-only PID29 Fast Forcing Status 29 1 read-only PID30 Fast Forcing Status 30 1 read-only PID31 Fast Forcing Status 31 1 read-only PIOA 6057F Parallel Input/Output Controller A PIO PIOA_ 0xFFFFF200 0 0x200 registers PIOA 2 PER PIO Enable Register 0x00000000 32 write-only P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P2 PIO Enable 2 1 write-only P3 PIO Enable 3 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only PDR PIO Disable Register 0x00000004 32 write-only P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P2 PIO Disable 2 1 write-only P3 PIO Disable 3 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only PSR PIO Status Register 0x00000008 32 read-only P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P2 PIO Status 2 1 read-only P3 PIO Status 3 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only OER Output Enable Register 0x00000010 32 write-only P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P2 Output Enable 2 1 write-only P3 Output Enable 3 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only ODR Output Disable Register 0x00000014 32 write-only P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P2 Output Disable 2 1 write-only P3 Output Disable 3 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only OSR Output Status Register 0x00000018 32 read-only 0x00000000 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P2 Output Status 2 1 read-only P3 Output Status 3 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only IFER Glitch Input Filter Enable Register 0x00000020 32 write-only P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P2 Input Filter Enable 2 1 write-only P3 Input Filter Enable 3 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only IFDR Glitch Input Filter Disable Register 0x00000024 32 write-only P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P2 Input Filter Disable 2 1 write-only P3 Input Filter Disable 3 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only IFSR Glitch Input Filter Status Register 0x00000028 32 read-only 0x00000000 P0 Input Filer Status 0 1 read-only P1 Input Filer Status 1 1 read-only P2 Input Filer Status 2 1 read-only P3 Input Filer Status 3 1 read-only P4 Input Filer Status 4 1 read-only P5 Input Filer Status 5 1 read-only P6 Input Filer Status 6 1 read-only P7 Input Filer Status 7 1 read-only P8 Input Filer Status 8 1 read-only P9 Input Filer Status 9 1 read-only P10 Input Filer Status 10 1 read-only P11 Input Filer Status 11 1 read-only P12 Input Filer Status 12 1 read-only P13 Input Filer Status 13 1 read-only P14 Input Filer Status 14 1 read-only P15 Input Filer Status 15 1 read-only P16 Input Filer Status 16 1 read-only P17 Input Filer Status 17 1 read-only P18 Input Filer Status 18 1 read-only P19 Input Filer Status 19 1 read-only P20 Input Filer Status 20 1 read-only P21 Input Filer Status 21 1 read-only P22 Input Filer Status 22 1 read-only P23 Input Filer Status 23 1 read-only P24 Input Filer Status 24 1 read-only P25 Input Filer Status 25 1 read-only P26 Input Filer Status 26 1 read-only P27 Input Filer Status 27 1 read-only P28 Input Filer Status 28 1 read-only P29 Input Filer Status 29 1 read-only P30 Input Filer Status 30 1 read-only P31 Input Filer Status 31 1 read-only SODR Set Output Data Register 0x00000030 32 write-only P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P2 Set Output Data 2 1 write-only P3 Set Output Data 3 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only CODR Clear Output Data Register 0x00000034 32 write-only P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P2 Clear Output Data 2 1 write-only P3 Clear Output Data 3 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only ODSR Output Data Status Register 0x00000038 32 read-write P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P2 Output Data Status 2 1 read-write P3 Output Data Status 3 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write PDSR Pin Data Status Register 0x0000003C 32 read-only P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P2 Output Data Status 2 1 read-only P3 Output Data Status 3 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only IER Interrupt Enable Register 0x00000040 32 write-only P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only IDR Interrupt Disable Register 0x00000044 32 write-only P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only IMR Interrupt Mask Register 0x00000048 32 read-only 0x00000000 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only ISR Interrupt Status Register 0x0000004C 32 read-only 0x00000000 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P2 Input Change Interrupt Status 2 1 read-only P3 Input Change Interrupt Status 3 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only MDER Multi-driver Enable Register 0x00000050 32 write-only P0 Multi Drive Enable. 0 1 write-only P1 Multi Drive Enable. 1 1 write-only P2 Multi Drive Enable. 2 1 write-only P3 Multi Drive Enable. 3 1 write-only P4 Multi Drive Enable. 4 1 write-only P5 Multi Drive Enable. 5 1 write-only P6 Multi Drive Enable. 6 1 write-only P7 Multi Drive Enable. 7 1 write-only P8 Multi Drive Enable. 8 1 write-only P9 Multi Drive Enable. 9 1 write-only P10 Multi Drive Enable. 10 1 write-only P11 Multi Drive Enable. 11 1 write-only P12 Multi Drive Enable. 12 1 write-only P13 Multi Drive Enable. 13 1 write-only P14 Multi Drive Enable. 14 1 write-only P15 Multi Drive Enable. 15 1 write-only P16 Multi Drive Enable. 16 1 write-only P17 Multi Drive Enable. 17 1 write-only P18 Multi Drive Enable. 18 1 write-only P19 Multi Drive Enable. 19 1 write-only P20 Multi Drive Enable. 20 1 write-only P21 Multi Drive Enable. 21 1 write-only P22 Multi Drive Enable. 22 1 write-only P23 Multi Drive Enable. 23 1 write-only P24 Multi Drive Enable. 24 1 write-only P25 Multi Drive Enable. 25 1 write-only P26 Multi Drive Enable. 26 1 write-only P27 Multi Drive Enable. 27 1 write-only P28 Multi Drive Enable. 28 1 write-only P29 Multi Drive Enable. 29 1 write-only P30 Multi Drive Enable. 30 1 write-only P31 Multi Drive Enable. 31 1 write-only MDDR Multi-driver Disable Register 0x00000054 32 write-only P0 Multi Drive Disable. 0 1 write-only P1 Multi Drive Disable. 1 1 write-only P2 Multi Drive Disable. 2 1 write-only P3 Multi Drive Disable. 3 1 write-only P4 Multi Drive Disable. 4 1 write-only P5 Multi Drive Disable. 5 1 write-only P6 Multi Drive Disable. 6 1 write-only P7 Multi Drive Disable. 7 1 write-only P8 Multi Drive Disable. 8 1 write-only P9 Multi Drive Disable. 9 1 write-only P10 Multi Drive Disable. 10 1 write-only P11 Multi Drive Disable. 11 1 write-only P12 Multi Drive Disable. 12 1 write-only P13 Multi Drive Disable. 13 1 write-only P14 Multi Drive Disable. 14 1 write-only P15 Multi Drive Disable. 15 1 write-only P16 Multi Drive Disable. 16 1 write-only P17 Multi Drive Disable. 17 1 write-only P18 Multi Drive Disable. 18 1 write-only P19 Multi Drive Disable. 19 1 write-only P20 Multi Drive Disable. 20 1 write-only P21 Multi Drive Disable. 21 1 write-only P22 Multi Drive Disable. 22 1 write-only P23 Multi Drive Disable. 23 1 write-only P24 Multi Drive Disable. 24 1 write-only P25 Multi Drive Disable. 25 1 write-only P26 Multi Drive Disable. 26 1 write-only P27 Multi Drive Disable. 27 1 write-only P28 Multi Drive Disable. 28 1 write-only P29 Multi Drive Disable. 29 1 write-only P30 Multi Drive Disable. 30 1 write-only P31 Multi Drive Disable. 31 1 write-only MDSR Multi-driver Status Register 0x00000058 32 read-only 0x00000000 P0 Multi Drive Status. 0 1 read-only P1 Multi Drive Status. 1 1 read-only P2 Multi Drive Status. 2 1 read-only P3 Multi Drive Status. 3 1 read-only P4 Multi Drive Status. 4 1 read-only P5 Multi Drive Status. 5 1 read-only P6 Multi Drive Status. 6 1 read-only P7 Multi Drive Status. 7 1 read-only P8 Multi Drive Status. 8 1 read-only P9 Multi Drive Status. 9 1 read-only P10 Multi Drive Status. 10 1 read-only P11 Multi Drive Status. 11 1 read-only P12 Multi Drive Status. 12 1 read-only P13 Multi Drive Status. 13 1 read-only P14 Multi Drive Status. 14 1 read-only P15 Multi Drive Status. 15 1 read-only P16 Multi Drive Status. 16 1 read-only P17 Multi Drive Status. 17 1 read-only P18 Multi Drive Status. 18 1 read-only P19 Multi Drive Status. 19 1 read-only P20 Multi Drive Status. 20 1 read-only P21 Multi Drive Status. 21 1 read-only P22 Multi Drive Status. 22 1 read-only P23 Multi Drive Status. 23 1 read-only P24 Multi Drive Status. 24 1 read-only P25 Multi Drive Status. 25 1 read-only P26 Multi Drive Status. 26 1 read-only P27 Multi Drive Status. 27 1 read-only P28 Multi Drive Status. 28 1 read-only P29 Multi Drive Status. 29 1 read-only P30 Multi Drive Status. 30 1 read-only P31 Multi Drive Status. 31 1 read-only PUDR Pull-up Disable Register 0x00000060 32 write-only P0 Pull Up Disable. 0 1 write-only P1 Pull Up Disable. 1 1 write-only P2 Pull Up Disable. 2 1 write-only P3 Pull Up Disable. 3 1 write-only P4 Pull Up Disable. 4 1 write-only P5 Pull Up Disable. 5 1 write-only P6 Pull Up Disable. 6 1 write-only P7 Pull Up Disable. 7 1 write-only P8 Pull Up Disable. 8 1 write-only P9 Pull Up Disable. 9 1 write-only P10 Pull Up Disable. 10 1 write-only P11 Pull Up Disable. 11 1 write-only P12 Pull Up Disable. 12 1 write-only P13 Pull Up Disable. 13 1 write-only P14 Pull Up Disable. 14 1 write-only P15 Pull Up Disable. 15 1 write-only P16 Pull Up Disable. 16 1 write-only P17 Pull Up Disable. 17 1 write-only P18 Pull Up Disable. 18 1 write-only P19 Pull Up Disable. 19 1 write-only P20 Pull Up Disable. 20 1 write-only P21 Pull Up Disable. 21 1 write-only P22 Pull Up Disable. 22 1 write-only P23 Pull Up Disable. 23 1 write-only P24 Pull Up Disable. 24 1 write-only P25 Pull Up Disable. 25 1 write-only P26 Pull Up Disable. 26 1 write-only P27 Pull Up Disable. 27 1 write-only P28 Pull Up Disable. 28 1 write-only P29 Pull Up Disable. 29 1 write-only P30 Pull Up Disable. 30 1 write-only P31 Pull Up Disable. 31 1 write-only PUER Pull-up Enable Register 0x00000064 32 write-only P0 Pull Up Enable. 0 1 write-only P1 Pull Up Enable. 1 1 write-only P2 Pull Up Enable. 2 1 write-only P3 Pull Up Enable. 3 1 write-only P4 Pull Up Enable. 4 1 write-only P5 Pull Up Enable. 5 1 write-only P6 Pull Up Enable. 6 1 write-only P7 Pull Up Enable. 7 1 write-only P8 Pull Up Enable. 8 1 write-only P9 Pull Up Enable. 9 1 write-only P10 Pull Up Enable. 10 1 write-only P11 Pull Up Enable. 11 1 write-only P12 Pull Up Enable. 12 1 write-only P13 Pull Up Enable. 13 1 write-only P14 Pull Up Enable. 14 1 write-only P15 Pull Up Enable. 15 1 write-only P16 Pull Up Enable. 16 1 write-only P17 Pull Up Enable. 17 1 write-only P18 Pull Up Enable. 18 1 write-only P19 Pull Up Enable. 19 1 write-only P20 Pull Up Enable. 20 1 write-only P21 Pull Up Enable. 21 1 write-only P22 Pull Up Enable. 22 1 write-only P23 Pull Up Enable. 23 1 write-only P24 Pull Up Enable. 24 1 write-only P25 Pull Up Enable. 25 1 write-only P26 Pull Up Enable. 26 1 write-only P27 Pull Up Enable. 27 1 write-only P28 Pull Up Enable. 28 1 write-only P29 Pull Up Enable. 29 1 write-only P30 Pull Up Enable. 30 1 write-only P31 Pull Up Enable. 31 1 write-only PUSR Pad Pull-up Status Register 0x00000068 32 read-only 0x00000000 P0 Pull Up Status. 0 1 read-only P1 Pull Up Status. 1 1 read-only P2 Pull Up Status. 2 1 read-only P3 Pull Up Status. 3 1 read-only P4 Pull Up Status. 4 1 read-only P5 Pull Up Status. 5 1 read-only P6 Pull Up Status. 6 1 read-only P7 Pull Up Status. 7 1 read-only P8 Pull Up Status. 8 1 read-only P9 Pull Up Status. 9 1 read-only P10 Pull Up Status. 10 1 read-only P11 Pull Up Status. 11 1 read-only P12 Pull Up Status. 12 1 read-only P13 Pull Up Status. 13 1 read-only P14 Pull Up Status. 14 1 read-only P15 Pull Up Status. 15 1 read-only P16 Pull Up Status. 16 1 read-only P17 Pull Up Status. 17 1 read-only P18 Pull Up Status. 18 1 read-only P19 Pull Up Status. 19 1 read-only P20 Pull Up Status. 20 1 read-only P21 Pull Up Status. 21 1 read-only P22 Pull Up Status. 22 1 read-only P23 Pull Up Status. 23 1 read-only P24 Pull Up Status. 24 1 read-only P25 Pull Up Status. 25 1 read-only P26 Pull Up Status. 26 1 read-only P27 Pull Up Status. 27 1 read-only P28 Pull Up Status. 28 1 read-only P29 Pull Up Status. 29 1 read-only P30 Pull Up Status. 30 1 read-only P31 Pull Up Status. 31 1 read-only ASR Peripheral A Select Register 0x00000070 32 write-only P0 Peripheral A Select. 0 1 write-only P1 Peripheral A Select. 1 1 write-only P2 Peripheral A Select. 2 1 write-only P3 Peripheral A Select. 3 1 write-only P4 Peripheral A Select. 4 1 write-only P5 Peripheral A Select. 5 1 write-only P6 Peripheral A Select. 6 1 write-only P7 Peripheral A Select. 7 1 write-only P8 Peripheral A Select. 8 1 write-only P9 Peripheral A Select. 9 1 write-only P10 Peripheral A Select. 10 1 write-only P11 Peripheral A Select. 11 1 write-only P12 Peripheral A Select. 12 1 write-only P13 Peripheral A Select. 13 1 write-only P14 Peripheral A Select. 14 1 write-only P15 Peripheral A Select. 15 1 write-only P16 Peripheral A Select. 16 1 write-only P17 Peripheral A Select. 17 1 write-only P18 Peripheral A Select. 18 1 write-only P19 Peripheral A Select. 19 1 write-only P20 Peripheral A Select. 20 1 write-only P21 Peripheral A Select. 21 1 write-only P22 Peripheral A Select. 22 1 write-only P23 Peripheral A Select. 23 1 write-only P24 Peripheral A Select. 24 1 write-only P25 Peripheral A Select. 25 1 write-only P26 Peripheral A Select. 26 1 write-only P27 Peripheral A Select. 27 1 write-only P28 Peripheral A Select. 28 1 write-only P29 Peripheral A Select. 29 1 write-only P30 Peripheral A Select. 30 1 write-only P31 Peripheral A Select. 31 1 write-only BSR Peripheral B Select Register 0x00000074 32 write-only P0 Peripheral B Select. 0 1 write-only P1 Peripheral B Select. 1 1 write-only P2 Peripheral B Select. 2 1 write-only P3 Peripheral B Select. 3 1 write-only P4 Peripheral B Select. 4 1 write-only P5 Peripheral B Select. 5 1 write-only P6 Peripheral B Select. 6 1 write-only P7 Peripheral B Select. 7 1 write-only P8 Peripheral B Select. 8 1 write-only P9 Peripheral B Select. 9 1 write-only P10 Peripheral B Select. 10 1 write-only P11 Peripheral B Select. 11 1 write-only P12 Peripheral B Select. 12 1 write-only P13 Peripheral B Select. 13 1 write-only P14 Peripheral B Select. 14 1 write-only P15 Peripheral B Select. 15 1 write-only P16 Peripheral B Select. 16 1 write-only P17 Peripheral B Select. 17 1 write-only P18 Peripheral B Select. 18 1 write-only P19 Peripheral B Select. 19 1 write-only P20 Peripheral B Select. 20 1 write-only P21 Peripheral B Select. 21 1 write-only P22 Peripheral B Select. 22 1 write-only P23 Peripheral B Select. 23 1 write-only P24 Peripheral B Select. 24 1 write-only P25 Peripheral B Select. 25 1 write-only P26 Peripheral B Select. 26 1 write-only P27 Peripheral B Select. 27 1 write-only P28 Peripheral B Select. 28 1 write-only P29 Peripheral B Select. 29 1 write-only P30 Peripheral B Select. 30 1 write-only P31 Peripheral B Select. 31 1 write-only ABSR AB Status Register 0x00000078 32 read-only 0x00000000 P0 Peripheral A B Status. 0 1 read-only P1 Peripheral A B Status. 1 1 read-only P2 Peripheral A B Status. 2 1 read-only P3 Peripheral A B Status. 3 1 read-only P4 Peripheral A B Status. 4 1 read-only P5 Peripheral A B Status. 5 1 read-only P6 Peripheral A B Status. 6 1 read-only P7 Peripheral A B Status. 7 1 read-only P8 Peripheral A B Status. 8 1 read-only P9 Peripheral A B Status. 9 1 read-only P10 Peripheral A B Status. 10 1 read-only P11 Peripheral A B Status. 11 1 read-only P12 Peripheral A B Status. 12 1 read-only P13 Peripheral A B Status. 13 1 read-only P14 Peripheral A B Status. 14 1 read-only P15 Peripheral A B Status. 15 1 read-only P16 Peripheral A B Status. 16 1 read-only P17 Peripheral A B Status. 17 1 read-only P18 Peripheral A B Status. 18 1 read-only P19 Peripheral A B Status. 19 1 read-only P20 Peripheral A B Status. 20 1 read-only P21 Peripheral A B Status. 21 1 read-only P22 Peripheral A B Status. 22 1 read-only P23 Peripheral A B Status. 23 1 read-only P24 Peripheral A B Status. 24 1 read-only P25 Peripheral A B Status. 25 1 read-only P26 Peripheral A B Status. 26 1 read-only P27 Peripheral A B Status. 27 1 read-only P28 Peripheral A B Status. 28 1 read-only P29 Peripheral A B Status. 29 1 read-only P30 Peripheral A B Status. 30 1 read-only P31 Peripheral A B Status. 31 1 read-only OWER Output Write Enable 0x000000A0 32 write-only P0 Output Write Enable. 0 1 write-only P1 Output Write Enable. 1 1 write-only P2 Output Write Enable. 2 1 write-only P3 Output Write Enable. 3 1 write-only P4 Output Write Enable. 4 1 write-only P5 Output Write Enable. 5 1 write-only P6 Output Write Enable. 6 1 write-only P7 Output Write Enable. 7 1 write-only P8 Output Write Enable. 8 1 write-only P9 Output Write Enable. 9 1 write-only P10 Output Write Enable. 10 1 write-only P11 Output Write Enable. 11 1 write-only P12 Output Write Enable. 12 1 write-only P13 Output Write Enable. 13 1 write-only P14 Output Write Enable. 14 1 write-only P15 Output Write Enable. 15 1 write-only P16 Output Write Enable. 16 1 write-only P17 Output Write Enable. 17 1 write-only P18 Output Write Enable. 18 1 write-only P19 Output Write Enable. 19 1 write-only P20 Output Write Enable. 20 1 write-only P21 Output Write Enable. 21 1 write-only P22 Output Write Enable. 22 1 write-only P23 Output Write Enable. 23 1 write-only P24 Output Write Enable. 24 1 write-only P25 Output Write Enable. 25 1 write-only P26 Output Write Enable. 26 1 write-only P27 Output Write Enable. 27 1 write-only P28 Output Write Enable. 28 1 write-only P29 Output Write Enable. 29 1 write-only P30 Output Write Enable. 30 1 write-only P31 Output Write Enable. 31 1 write-only OWDR Output Write Disable 0x000000A4 32 write-only P0 Output Write Disable. 0 1 write-only P1 Output Write Disable. 1 1 write-only P2 Output Write Disable. 2 1 write-only P3 Output Write Disable. 3 1 write-only P4 Output Write Disable. 4 1 write-only P5 Output Write Disable. 5 1 write-only P6 Output Write Disable. 6 1 write-only P7 Output Write Disable. 7 1 write-only P8 Output Write Disable. 8 1 write-only P9 Output Write Disable. 9 1 write-only P10 Output Write Disable. 10 1 write-only P11 Output Write Disable. 11 1 write-only P12 Output Write Disable. 12 1 write-only P13 Output Write Disable. 13 1 write-only P14 Output Write Disable. 14 1 write-only P15 Output Write Disable. 15 1 write-only P16 Output Write Disable. 16 1 write-only P17 Output Write Disable. 17 1 write-only P18 Output Write Disable. 18 1 write-only P19 Output Write Disable. 19 1 write-only P20 Output Write Disable. 20 1 write-only P21 Output Write Disable. 21 1 write-only P22 Output Write Disable. 22 1 write-only P23 Output Write Disable. 23 1 write-only P24 Output Write Disable. 24 1 write-only P25 Output Write Disable. 25 1 write-only P26 Output Write Disable. 26 1 write-only P27 Output Write Disable. 27 1 write-only P28 Output Write Disable. 28 1 write-only P29 Output Write Disable. 29 1 write-only P30 Output Write Disable. 30 1 write-only P31 Output Write Disable. 31 1 write-only OWSR Output Write Status Register 0x000000A8 32 read-only 0x00000000 P0 Output Write Status. 0 1 read-only P1 Output Write Status. 1 1 read-only P2 Output Write Status. 2 1 read-only P3 Output Write Status. 3 1 read-only P4 Output Write Status. 4 1 read-only P5 Output Write Status. 5 1 read-only P6 Output Write Status. 6 1 read-only P7 Output Write Status. 7 1 read-only P8 Output Write Status. 8 1 read-only P9 Output Write Status. 9 1 read-only P10 Output Write Status. 10 1 read-only P11 Output Write Status. 11 1 read-only P12 Output Write Status. 12 1 read-only P13 Output Write Status. 13 1 read-only P14 Output Write Status. 14 1 read-only P15 Output Write Status. 15 1 read-only P16 Output Write Status. 16 1 read-only P17 Output Write Status. 17 1 read-only P18 Output Write Status. 18 1 read-only P19 Output Write Status. 19 1 read-only P20 Output Write Status. 20 1 read-only P21 Output Write Status. 21 1 read-only P22 Output Write Status. 22 1 read-only P23 Output Write Status. 23 1 read-only P24 Output Write Status. 24 1 read-only P25 Output Write Status. 25 1 read-only P26 Output Write Status. 26 1 read-only P27 Output Write Status. 27 1 read-only P28 Output Write Status. 28 1 read-only P29 Output Write Status. 29 1 read-only P30 Output Write Status. 30 1 read-only P31 Output Write Status. 31 1 read-only 4 4 0-3 DELAYR[%s] I/O Delay Register 0x000000C0 32 read-write Delay0 0 4 read-write Delay1 4 4 read-write Delay2 8 4 read-write Delay3 12 4 read-write Delay4 16 4 read-write Delay5 20 4 read-write Delay6 24 4 read-write Delay7 28 4 read-write WPMR Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write WPSR Write Protect Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protect Enable 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only PIOB 6057F Parallel Input/Output Controller B PIO PIOB_ 0xFFFFF400 0 0x200 registers PIOB 3 PER PIO Enable Register 0x00000000 32 write-only P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P2 PIO Enable 2 1 write-only P3 PIO Enable 3 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only PDR PIO Disable Register 0x00000004 32 write-only P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P2 PIO Disable 2 1 write-only P3 PIO Disable 3 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only PSR PIO Status Register 0x00000008 32 read-only P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P2 PIO Status 2 1 read-only P3 PIO Status 3 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only OER Output Enable Register 0x00000010 32 write-only P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P2 Output Enable 2 1 write-only P3 Output Enable 3 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only ODR Output Disable Register 0x00000014 32 write-only P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P2 Output Disable 2 1 write-only P3 Output Disable 3 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only OSR Output Status Register 0x00000018 32 read-only 0x00000000 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P2 Output Status 2 1 read-only P3 Output Status 3 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only IFER Glitch Input Filter Enable Register 0x00000020 32 write-only P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P2 Input Filter Enable 2 1 write-only P3 Input Filter Enable 3 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only IFDR Glitch Input Filter Disable Register 0x00000024 32 write-only P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P2 Input Filter Disable 2 1 write-only P3 Input Filter Disable 3 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only IFSR Glitch Input Filter Status Register 0x00000028 32 read-only 0x00000000 P0 Input Filer Status 0 1 read-only P1 Input Filer Status 1 1 read-only P2 Input Filer Status 2 1 read-only P3 Input Filer Status 3 1 read-only P4 Input Filer Status 4 1 read-only P5 Input Filer Status 5 1 read-only P6 Input Filer Status 6 1 read-only P7 Input Filer Status 7 1 read-only P8 Input Filer Status 8 1 read-only P9 Input Filer Status 9 1 read-only P10 Input Filer Status 10 1 read-only P11 Input Filer Status 11 1 read-only P12 Input Filer Status 12 1 read-only P13 Input Filer Status 13 1 read-only P14 Input Filer Status 14 1 read-only P15 Input Filer Status 15 1 read-only P16 Input Filer Status 16 1 read-only P17 Input Filer Status 17 1 read-only P18 Input Filer Status 18 1 read-only P19 Input Filer Status 19 1 read-only P20 Input Filer Status 20 1 read-only P21 Input Filer Status 21 1 read-only P22 Input Filer Status 22 1 read-only P23 Input Filer Status 23 1 read-only P24 Input Filer Status 24 1 read-only P25 Input Filer Status 25 1 read-only P26 Input Filer Status 26 1 read-only P27 Input Filer Status 27 1 read-only P28 Input Filer Status 28 1 read-only P29 Input Filer Status 29 1 read-only P30 Input Filer Status 30 1 read-only P31 Input Filer Status 31 1 read-only SODR Set Output Data Register 0x00000030 32 write-only P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P2 Set Output Data 2 1 write-only P3 Set Output Data 3 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only CODR Clear Output Data Register 0x00000034 32 write-only P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P2 Clear Output Data 2 1 write-only P3 Clear Output Data 3 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only ODSR Output Data Status Register 0x00000038 32 read-write P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P2 Output Data Status 2 1 read-write P3 Output Data Status 3 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write PDSR Pin Data Status Register 0x0000003C 32 read-only P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P2 Output Data Status 2 1 read-only P3 Output Data Status 3 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only IER Interrupt Enable Register 0x00000040 32 write-only P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only IDR Interrupt Disable Register 0x00000044 32 write-only P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only IMR Interrupt Mask Register 0x00000048 32 read-only 0x00000000 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only ISR Interrupt Status Register 0x0000004C 32 read-only 0x00000000 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P2 Input Change Interrupt Status 2 1 read-only P3 Input Change Interrupt Status 3 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only MDER Multi-driver Enable Register 0x00000050 32 write-only P0 Multi Drive Enable. 0 1 write-only P1 Multi Drive Enable. 1 1 write-only P2 Multi Drive Enable. 2 1 write-only P3 Multi Drive Enable. 3 1 write-only P4 Multi Drive Enable. 4 1 write-only P5 Multi Drive Enable. 5 1 write-only P6 Multi Drive Enable. 6 1 write-only P7 Multi Drive Enable. 7 1 write-only P8 Multi Drive Enable. 8 1 write-only P9 Multi Drive Enable. 9 1 write-only P10 Multi Drive Enable. 10 1 write-only P11 Multi Drive Enable. 11 1 write-only P12 Multi Drive Enable. 12 1 write-only P13 Multi Drive Enable. 13 1 write-only P14 Multi Drive Enable. 14 1 write-only P15 Multi Drive Enable. 15 1 write-only P16 Multi Drive Enable. 16 1 write-only P17 Multi Drive Enable. 17 1 write-only P18 Multi Drive Enable. 18 1 write-only P19 Multi Drive Enable. 19 1 write-only P20 Multi Drive Enable. 20 1 write-only P21 Multi Drive Enable. 21 1 write-only P22 Multi Drive Enable. 22 1 write-only P23 Multi Drive Enable. 23 1 write-only P24 Multi Drive Enable. 24 1 write-only P25 Multi Drive Enable. 25 1 write-only P26 Multi Drive Enable. 26 1 write-only P27 Multi Drive Enable. 27 1 write-only P28 Multi Drive Enable. 28 1 write-only P29 Multi Drive Enable. 29 1 write-only P30 Multi Drive Enable. 30 1 write-only P31 Multi Drive Enable. 31 1 write-only MDDR Multi-driver Disable Register 0x00000054 32 write-only P0 Multi Drive Disable. 0 1 write-only P1 Multi Drive Disable. 1 1 write-only P2 Multi Drive Disable. 2 1 write-only P3 Multi Drive Disable. 3 1 write-only P4 Multi Drive Disable. 4 1 write-only P5 Multi Drive Disable. 5 1 write-only P6 Multi Drive Disable. 6 1 write-only P7 Multi Drive Disable. 7 1 write-only P8 Multi Drive Disable. 8 1 write-only P9 Multi Drive Disable. 9 1 write-only P10 Multi Drive Disable. 10 1 write-only P11 Multi Drive Disable. 11 1 write-only P12 Multi Drive Disable. 12 1 write-only P13 Multi Drive Disable. 13 1 write-only P14 Multi Drive Disable. 14 1 write-only P15 Multi Drive Disable. 15 1 write-only P16 Multi Drive Disable. 16 1 write-only P17 Multi Drive Disable. 17 1 write-only P18 Multi Drive Disable. 18 1 write-only P19 Multi Drive Disable. 19 1 write-only P20 Multi Drive Disable. 20 1 write-only P21 Multi Drive Disable. 21 1 write-only P22 Multi Drive Disable. 22 1 write-only P23 Multi Drive Disable. 23 1 write-only P24 Multi Drive Disable. 24 1 write-only P25 Multi Drive Disable. 25 1 write-only P26 Multi Drive Disable. 26 1 write-only P27 Multi Drive Disable. 27 1 write-only P28 Multi Drive Disable. 28 1 write-only P29 Multi Drive Disable. 29 1 write-only P30 Multi Drive Disable. 30 1 write-only P31 Multi Drive Disable. 31 1 write-only MDSR Multi-driver Status Register 0x00000058 32 read-only 0x00000000 P0 Multi Drive Status. 0 1 read-only P1 Multi Drive Status. 1 1 read-only P2 Multi Drive Status. 2 1 read-only P3 Multi Drive Status. 3 1 read-only P4 Multi Drive Status. 4 1 read-only P5 Multi Drive Status. 5 1 read-only P6 Multi Drive Status. 6 1 read-only P7 Multi Drive Status. 7 1 read-only P8 Multi Drive Status. 8 1 read-only P9 Multi Drive Status. 9 1 read-only P10 Multi Drive Status. 10 1 read-only P11 Multi Drive Status. 11 1 read-only P12 Multi Drive Status. 12 1 read-only P13 Multi Drive Status. 13 1 read-only P14 Multi Drive Status. 14 1 read-only P15 Multi Drive Status. 15 1 read-only P16 Multi Drive Status. 16 1 read-only P17 Multi Drive Status. 17 1 read-only P18 Multi Drive Status. 18 1 read-only P19 Multi Drive Status. 19 1 read-only P20 Multi Drive Status. 20 1 read-only P21 Multi Drive Status. 21 1 read-only P22 Multi Drive Status. 22 1 read-only P23 Multi Drive Status. 23 1 read-only P24 Multi Drive Status. 24 1 read-only P25 Multi Drive Status. 25 1 read-only P26 Multi Drive Status. 26 1 read-only P27 Multi Drive Status. 27 1 read-only P28 Multi Drive Status. 28 1 read-only P29 Multi Drive Status. 29 1 read-only P30 Multi Drive Status. 30 1 read-only P31 Multi Drive Status. 31 1 read-only PUDR Pull-up Disable Register 0x00000060 32 write-only P0 Pull Up Disable. 0 1 write-only P1 Pull Up Disable. 1 1 write-only P2 Pull Up Disable. 2 1 write-only P3 Pull Up Disable. 3 1 write-only P4 Pull Up Disable. 4 1 write-only P5 Pull Up Disable. 5 1 write-only P6 Pull Up Disable. 6 1 write-only P7 Pull Up Disable. 7 1 write-only P8 Pull Up Disable. 8 1 write-only P9 Pull Up Disable. 9 1 write-only P10 Pull Up Disable. 10 1 write-only P11 Pull Up Disable. 11 1 write-only P12 Pull Up Disable. 12 1 write-only P13 Pull Up Disable. 13 1 write-only P14 Pull Up Disable. 14 1 write-only P15 Pull Up Disable. 15 1 write-only P16 Pull Up Disable. 16 1 write-only P17 Pull Up Disable. 17 1 write-only P18 Pull Up Disable. 18 1 write-only P19 Pull Up Disable. 19 1 write-only P20 Pull Up Disable. 20 1 write-only P21 Pull Up Disable. 21 1 write-only P22 Pull Up Disable. 22 1 write-only P23 Pull Up Disable. 23 1 write-only P24 Pull Up Disable. 24 1 write-only P25 Pull Up Disable. 25 1 write-only P26 Pull Up Disable. 26 1 write-only P27 Pull Up Disable. 27 1 write-only P28 Pull Up Disable. 28 1 write-only P29 Pull Up Disable. 29 1 write-only P30 Pull Up Disable. 30 1 write-only P31 Pull Up Disable. 31 1 write-only PUER Pull-up Enable Register 0x00000064 32 write-only P0 Pull Up Enable. 0 1 write-only P1 Pull Up Enable. 1 1 write-only P2 Pull Up Enable. 2 1 write-only P3 Pull Up Enable. 3 1 write-only P4 Pull Up Enable. 4 1 write-only P5 Pull Up Enable. 5 1 write-only P6 Pull Up Enable. 6 1 write-only P7 Pull Up Enable. 7 1 write-only P8 Pull Up Enable. 8 1 write-only P9 Pull Up Enable. 9 1 write-only P10 Pull Up Enable. 10 1 write-only P11 Pull Up Enable. 11 1 write-only P12 Pull Up Enable. 12 1 write-only P13 Pull Up Enable. 13 1 write-only P14 Pull Up Enable. 14 1 write-only P15 Pull Up Enable. 15 1 write-only P16 Pull Up Enable. 16 1 write-only P17 Pull Up Enable. 17 1 write-only P18 Pull Up Enable. 18 1 write-only P19 Pull Up Enable. 19 1 write-only P20 Pull Up Enable. 20 1 write-only P21 Pull Up Enable. 21 1 write-only P22 Pull Up Enable. 22 1 write-only P23 Pull Up Enable. 23 1 write-only P24 Pull Up Enable. 24 1 write-only P25 Pull Up Enable. 25 1 write-only P26 Pull Up Enable. 26 1 write-only P27 Pull Up Enable. 27 1 write-only P28 Pull Up Enable. 28 1 write-only P29 Pull Up Enable. 29 1 write-only P30 Pull Up Enable. 30 1 write-only P31 Pull Up Enable. 31 1 write-only PUSR Pad Pull-up Status Register 0x00000068 32 read-only 0x00000000 P0 Pull Up Status. 0 1 read-only P1 Pull Up Status. 1 1 read-only P2 Pull Up Status. 2 1 read-only P3 Pull Up Status. 3 1 read-only P4 Pull Up Status. 4 1 read-only P5 Pull Up Status. 5 1 read-only P6 Pull Up Status. 6 1 read-only P7 Pull Up Status. 7 1 read-only P8 Pull Up Status. 8 1 read-only P9 Pull Up Status. 9 1 read-only P10 Pull Up Status. 10 1 read-only P11 Pull Up Status. 11 1 read-only P12 Pull Up Status. 12 1 read-only P13 Pull Up Status. 13 1 read-only P14 Pull Up Status. 14 1 read-only P15 Pull Up Status. 15 1 read-only P16 Pull Up Status. 16 1 read-only P17 Pull Up Status. 17 1 read-only P18 Pull Up Status. 18 1 read-only P19 Pull Up Status. 19 1 read-only P20 Pull Up Status. 20 1 read-only P21 Pull Up Status. 21 1 read-only P22 Pull Up Status. 22 1 read-only P23 Pull Up Status. 23 1 read-only P24 Pull Up Status. 24 1 read-only P25 Pull Up Status. 25 1 read-only P26 Pull Up Status. 26 1 read-only P27 Pull Up Status. 27 1 read-only P28 Pull Up Status. 28 1 read-only P29 Pull Up Status. 29 1 read-only P30 Pull Up Status. 30 1 read-only P31 Pull Up Status. 31 1 read-only ASR Peripheral A Select Register 0x00000070 32 write-only P0 Peripheral A Select. 0 1 write-only P1 Peripheral A Select. 1 1 write-only P2 Peripheral A Select. 2 1 write-only P3 Peripheral A Select. 3 1 write-only P4 Peripheral A Select. 4 1 write-only P5 Peripheral A Select. 5 1 write-only P6 Peripheral A Select. 6 1 write-only P7 Peripheral A Select. 7 1 write-only P8 Peripheral A Select. 8 1 write-only P9 Peripheral A Select. 9 1 write-only P10 Peripheral A Select. 10 1 write-only P11 Peripheral A Select. 11 1 write-only P12 Peripheral A Select. 12 1 write-only P13 Peripheral A Select. 13 1 write-only P14 Peripheral A Select. 14 1 write-only P15 Peripheral A Select. 15 1 write-only P16 Peripheral A Select. 16 1 write-only P17 Peripheral A Select. 17 1 write-only P18 Peripheral A Select. 18 1 write-only P19 Peripheral A Select. 19 1 write-only P20 Peripheral A Select. 20 1 write-only P21 Peripheral A Select. 21 1 write-only P22 Peripheral A Select. 22 1 write-only P23 Peripheral A Select. 23 1 write-only P24 Peripheral A Select. 24 1 write-only P25 Peripheral A Select. 25 1 write-only P26 Peripheral A Select. 26 1 write-only P27 Peripheral A Select. 27 1 write-only P28 Peripheral A Select. 28 1 write-only P29 Peripheral A Select. 29 1 write-only P30 Peripheral A Select. 30 1 write-only P31 Peripheral A Select. 31 1 write-only BSR Peripheral B Select Register 0x00000074 32 write-only P0 Peripheral B Select. 0 1 write-only P1 Peripheral B Select. 1 1 write-only P2 Peripheral B Select. 2 1 write-only P3 Peripheral B Select. 3 1 write-only P4 Peripheral B Select. 4 1 write-only P5 Peripheral B Select. 5 1 write-only P6 Peripheral B Select. 6 1 write-only P7 Peripheral B Select. 7 1 write-only P8 Peripheral B Select. 8 1 write-only P9 Peripheral B Select. 9 1 write-only P10 Peripheral B Select. 10 1 write-only P11 Peripheral B Select. 11 1 write-only P12 Peripheral B Select. 12 1 write-only P13 Peripheral B Select. 13 1 write-only P14 Peripheral B Select. 14 1 write-only P15 Peripheral B Select. 15 1 write-only P16 Peripheral B Select. 16 1 write-only P17 Peripheral B Select. 17 1 write-only P18 Peripheral B Select. 18 1 write-only P19 Peripheral B Select. 19 1 write-only P20 Peripheral B Select. 20 1 write-only P21 Peripheral B Select. 21 1 write-only P22 Peripheral B Select. 22 1 write-only P23 Peripheral B Select. 23 1 write-only P24 Peripheral B Select. 24 1 write-only P25 Peripheral B Select. 25 1 write-only P26 Peripheral B Select. 26 1 write-only P27 Peripheral B Select. 27 1 write-only P28 Peripheral B Select. 28 1 write-only P29 Peripheral B Select. 29 1 write-only P30 Peripheral B Select. 30 1 write-only P31 Peripheral B Select. 31 1 write-only ABSR AB Status Register 0x00000078 32 read-only 0x00000000 P0 Peripheral A B Status. 0 1 read-only P1 Peripheral A B Status. 1 1 read-only P2 Peripheral A B Status. 2 1 read-only P3 Peripheral A B Status. 3 1 read-only P4 Peripheral A B Status. 4 1 read-only P5 Peripheral A B Status. 5 1 read-only P6 Peripheral A B Status. 6 1 read-only P7 Peripheral A B Status. 7 1 read-only P8 Peripheral A B Status. 8 1 read-only P9 Peripheral A B Status. 9 1 read-only P10 Peripheral A B Status. 10 1 read-only P11 Peripheral A B Status. 11 1 read-only P12 Peripheral A B Status. 12 1 read-only P13 Peripheral A B Status. 13 1 read-only P14 Peripheral A B Status. 14 1 read-only P15 Peripheral A B Status. 15 1 read-only P16 Peripheral A B Status. 16 1 read-only P17 Peripheral A B Status. 17 1 read-only P18 Peripheral A B Status. 18 1 read-only P19 Peripheral A B Status. 19 1 read-only P20 Peripheral A B Status. 20 1 read-only P21 Peripheral A B Status. 21 1 read-only P22 Peripheral A B Status. 22 1 read-only P23 Peripheral A B Status. 23 1 read-only P24 Peripheral A B Status. 24 1 read-only P25 Peripheral A B Status. 25 1 read-only P26 Peripheral A B Status. 26 1 read-only P27 Peripheral A B Status. 27 1 read-only P28 Peripheral A B Status. 28 1 read-only P29 Peripheral A B Status. 29 1 read-only P30 Peripheral A B Status. 30 1 read-only P31 Peripheral A B Status. 31 1 read-only OWER Output Write Enable 0x000000A0 32 write-only P0 Output Write Enable. 0 1 write-only P1 Output Write Enable. 1 1 write-only P2 Output Write Enable. 2 1 write-only P3 Output Write Enable. 3 1 write-only P4 Output Write Enable. 4 1 write-only P5 Output Write Enable. 5 1 write-only P6 Output Write Enable. 6 1 write-only P7 Output Write Enable. 7 1 write-only P8 Output Write Enable. 8 1 write-only P9 Output Write Enable. 9 1 write-only P10 Output Write Enable. 10 1 write-only P11 Output Write Enable. 11 1 write-only P12 Output Write Enable. 12 1 write-only P13 Output Write Enable. 13 1 write-only P14 Output Write Enable. 14 1 write-only P15 Output Write Enable. 15 1 write-only P16 Output Write Enable. 16 1 write-only P17 Output Write Enable. 17 1 write-only P18 Output Write Enable. 18 1 write-only P19 Output Write Enable. 19 1 write-only P20 Output Write Enable. 20 1 write-only P21 Output Write Enable. 21 1 write-only P22 Output Write Enable. 22 1 write-only P23 Output Write Enable. 23 1 write-only P24 Output Write Enable. 24 1 write-only P25 Output Write Enable. 25 1 write-only P26 Output Write Enable. 26 1 write-only P27 Output Write Enable. 27 1 write-only P28 Output Write Enable. 28 1 write-only P29 Output Write Enable. 29 1 write-only P30 Output Write Enable. 30 1 write-only P31 Output Write Enable. 31 1 write-only OWDR Output Write Disable 0x000000A4 32 write-only P0 Output Write Disable. 0 1 write-only P1 Output Write Disable. 1 1 write-only P2 Output Write Disable. 2 1 write-only P3 Output Write Disable. 3 1 write-only P4 Output Write Disable. 4 1 write-only P5 Output Write Disable. 5 1 write-only P6 Output Write Disable. 6 1 write-only P7 Output Write Disable. 7 1 write-only P8 Output Write Disable. 8 1 write-only P9 Output Write Disable. 9 1 write-only P10 Output Write Disable. 10 1 write-only P11 Output Write Disable. 11 1 write-only P12 Output Write Disable. 12 1 write-only P13 Output Write Disable. 13 1 write-only P14 Output Write Disable. 14 1 write-only P15 Output Write Disable. 15 1 write-only P16 Output Write Disable. 16 1 write-only P17 Output Write Disable. 17 1 write-only P18 Output Write Disable. 18 1 write-only P19 Output Write Disable. 19 1 write-only P20 Output Write Disable. 20 1 write-only P21 Output Write Disable. 21 1 write-only P22 Output Write Disable. 22 1 write-only P23 Output Write Disable. 23 1 write-only P24 Output Write Disable. 24 1 write-only P25 Output Write Disable. 25 1 write-only P26 Output Write Disable. 26 1 write-only P27 Output Write Disable. 27 1 write-only P28 Output Write Disable. 28 1 write-only P29 Output Write Disable. 29 1 write-only P30 Output Write Disable. 30 1 write-only P31 Output Write Disable. 31 1 write-only OWSR Output Write Status Register 0x000000A8 32 read-only 0x00000000 P0 Output Write Status. 0 1 read-only P1 Output Write Status. 1 1 read-only P2 Output Write Status. 2 1 read-only P3 Output Write Status. 3 1 read-only P4 Output Write Status. 4 1 read-only P5 Output Write Status. 5 1 read-only P6 Output Write Status. 6 1 read-only P7 Output Write Status. 7 1 read-only P8 Output Write Status. 8 1 read-only P9 Output Write Status. 9 1 read-only P10 Output Write Status. 10 1 read-only P11 Output Write Status. 11 1 read-only P12 Output Write Status. 12 1 read-only P13 Output Write Status. 13 1 read-only P14 Output Write Status. 14 1 read-only P15 Output Write Status. 15 1 read-only P16 Output Write Status. 16 1 read-only P17 Output Write Status. 17 1 read-only P18 Output Write Status. 18 1 read-only P19 Output Write Status. 19 1 read-only P20 Output Write Status. 20 1 read-only P21 Output Write Status. 21 1 read-only P22 Output Write Status. 22 1 read-only P23 Output Write Status. 23 1 read-only P24 Output Write Status. 24 1 read-only P25 Output Write Status. 25 1 read-only P26 Output Write Status. 26 1 read-only P27 Output Write Status. 27 1 read-only P28 Output Write Status. 28 1 read-only P29 Output Write Status. 29 1 read-only P30 Output Write Status. 30 1 read-only P31 Output Write Status. 31 1 read-only 4 4 0-3 DELAYR[%s] I/O Delay Register 0x000000C0 32 read-write Delay0 0 4 read-write Delay1 4 4 read-write Delay2 8 4 read-write Delay3 12 4 read-write Delay4 16 4 read-write Delay5 20 4 read-write Delay6 24 4 read-write Delay7 28 4 read-write WPMR Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write WPSR Write Protect Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protect Enable 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only PIOC 6057F Parallel Input/Output Controller C PIO PIOC_ 0xFFFFF600 0 0x200 registers PIOC 4 PER PIO Enable Register 0x00000000 32 write-only P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P2 PIO Enable 2 1 write-only P3 PIO Enable 3 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only PDR PIO Disable Register 0x00000004 32 write-only P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P2 PIO Disable 2 1 write-only P3 PIO Disable 3 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only PSR PIO Status Register 0x00000008 32 read-only P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P2 PIO Status 2 1 read-only P3 PIO Status 3 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only OER Output Enable Register 0x00000010 32 write-only P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P2 Output Enable 2 1 write-only P3 Output Enable 3 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only ODR Output Disable Register 0x00000014 32 write-only P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P2 Output Disable 2 1 write-only P3 Output Disable 3 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only OSR Output Status Register 0x00000018 32 read-only 0x00000000 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P2 Output Status 2 1 read-only P3 Output Status 3 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only IFER Glitch Input Filter Enable Register 0x00000020 32 write-only P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P2 Input Filter Enable 2 1 write-only P3 Input Filter Enable 3 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only IFDR Glitch Input Filter Disable Register 0x00000024 32 write-only P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P2 Input Filter Disable 2 1 write-only P3 Input Filter Disable 3 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only IFSR Glitch Input Filter Status Register 0x00000028 32 read-only 0x00000000 P0 Input Filer Status 0 1 read-only P1 Input Filer Status 1 1 read-only P2 Input Filer Status 2 1 read-only P3 Input Filer Status 3 1 read-only P4 Input Filer Status 4 1 read-only P5 Input Filer Status 5 1 read-only P6 Input Filer Status 6 1 read-only P7 Input Filer Status 7 1 read-only P8 Input Filer Status 8 1 read-only P9 Input Filer Status 9 1 read-only P10 Input Filer Status 10 1 read-only P11 Input Filer Status 11 1 read-only P12 Input Filer Status 12 1 read-only P13 Input Filer Status 13 1 read-only P14 Input Filer Status 14 1 read-only P15 Input Filer Status 15 1 read-only P16 Input Filer Status 16 1 read-only P17 Input Filer Status 17 1 read-only P18 Input Filer Status 18 1 read-only P19 Input Filer Status 19 1 read-only P20 Input Filer Status 20 1 read-only P21 Input Filer Status 21 1 read-only P22 Input Filer Status 22 1 read-only P23 Input Filer Status 23 1 read-only P24 Input Filer Status 24 1 read-only P25 Input Filer Status 25 1 read-only P26 Input Filer Status 26 1 read-only P27 Input Filer Status 27 1 read-only P28 Input Filer Status 28 1 read-only P29 Input Filer Status 29 1 read-only P30 Input Filer Status 30 1 read-only P31 Input Filer Status 31 1 read-only SODR Set Output Data Register 0x00000030 32 write-only P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P2 Set Output Data 2 1 write-only P3 Set Output Data 3 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only CODR Clear Output Data Register 0x00000034 32 write-only P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P2 Clear Output Data 2 1 write-only P3 Clear Output Data 3 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only ODSR Output Data Status Register 0x00000038 32 read-write P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P2 Output Data Status 2 1 read-write P3 Output Data Status 3 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write PDSR Pin Data Status Register 0x0000003C 32 read-only P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P2 Output Data Status 2 1 read-only P3 Output Data Status 3 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only IER Interrupt Enable Register 0x00000040 32 write-only P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only IDR Interrupt Disable Register 0x00000044 32 write-only P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only IMR Interrupt Mask Register 0x00000048 32 read-only 0x00000000 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only ISR Interrupt Status Register 0x0000004C 32 read-only 0x00000000 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P2 Input Change Interrupt Status 2 1 read-only P3 Input Change Interrupt Status 3 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only MDER Multi-driver Enable Register 0x00000050 32 write-only P0 Multi Drive Enable. 0 1 write-only P1 Multi Drive Enable. 1 1 write-only P2 Multi Drive Enable. 2 1 write-only P3 Multi Drive Enable. 3 1 write-only P4 Multi Drive Enable. 4 1 write-only P5 Multi Drive Enable. 5 1 write-only P6 Multi Drive Enable. 6 1 write-only P7 Multi Drive Enable. 7 1 write-only P8 Multi Drive Enable. 8 1 write-only P9 Multi Drive Enable. 9 1 write-only P10 Multi Drive Enable. 10 1 write-only P11 Multi Drive Enable. 11 1 write-only P12 Multi Drive Enable. 12 1 write-only P13 Multi Drive Enable. 13 1 write-only P14 Multi Drive Enable. 14 1 write-only P15 Multi Drive Enable. 15 1 write-only P16 Multi Drive Enable. 16 1 write-only P17 Multi Drive Enable. 17 1 write-only P18 Multi Drive Enable. 18 1 write-only P19 Multi Drive Enable. 19 1 write-only P20 Multi Drive Enable. 20 1 write-only P21 Multi Drive Enable. 21 1 write-only P22 Multi Drive Enable. 22 1 write-only P23 Multi Drive Enable. 23 1 write-only P24 Multi Drive Enable. 24 1 write-only P25 Multi Drive Enable. 25 1 write-only P26 Multi Drive Enable. 26 1 write-only P27 Multi Drive Enable. 27 1 write-only P28 Multi Drive Enable. 28 1 write-only P29 Multi Drive Enable. 29 1 write-only P30 Multi Drive Enable. 30 1 write-only P31 Multi Drive Enable. 31 1 write-only MDDR Multi-driver Disable Register 0x00000054 32 write-only P0 Multi Drive Disable. 0 1 write-only P1 Multi Drive Disable. 1 1 write-only P2 Multi Drive Disable. 2 1 write-only P3 Multi Drive Disable. 3 1 write-only P4 Multi Drive Disable. 4 1 write-only P5 Multi Drive Disable. 5 1 write-only P6 Multi Drive Disable. 6 1 write-only P7 Multi Drive Disable. 7 1 write-only P8 Multi Drive Disable. 8 1 write-only P9 Multi Drive Disable. 9 1 write-only P10 Multi Drive Disable. 10 1 write-only P11 Multi Drive Disable. 11 1 write-only P12 Multi Drive Disable. 12 1 write-only P13 Multi Drive Disable. 13 1 write-only P14 Multi Drive Disable. 14 1 write-only P15 Multi Drive Disable. 15 1 write-only P16 Multi Drive Disable. 16 1 write-only P17 Multi Drive Disable. 17 1 write-only P18 Multi Drive Disable. 18 1 write-only P19 Multi Drive Disable. 19 1 write-only P20 Multi Drive Disable. 20 1 write-only P21 Multi Drive Disable. 21 1 write-only P22 Multi Drive Disable. 22 1 write-only P23 Multi Drive Disable. 23 1 write-only P24 Multi Drive Disable. 24 1 write-only P25 Multi Drive Disable. 25 1 write-only P26 Multi Drive Disable. 26 1 write-only P27 Multi Drive Disable. 27 1 write-only P28 Multi Drive Disable. 28 1 write-only P29 Multi Drive Disable. 29 1 write-only P30 Multi Drive Disable. 30 1 write-only P31 Multi Drive Disable. 31 1 write-only MDSR Multi-driver Status Register 0x00000058 32 read-only 0x00000000 P0 Multi Drive Status. 0 1 read-only P1 Multi Drive Status. 1 1 read-only P2 Multi Drive Status. 2 1 read-only P3 Multi Drive Status. 3 1 read-only P4 Multi Drive Status. 4 1 read-only P5 Multi Drive Status. 5 1 read-only P6 Multi Drive Status. 6 1 read-only P7 Multi Drive Status. 7 1 read-only P8 Multi Drive Status. 8 1 read-only P9 Multi Drive Status. 9 1 read-only P10 Multi Drive Status. 10 1 read-only P11 Multi Drive Status. 11 1 read-only P12 Multi Drive Status. 12 1 read-only P13 Multi Drive Status. 13 1 read-only P14 Multi Drive Status. 14 1 read-only P15 Multi Drive Status. 15 1 read-only P16 Multi Drive Status. 16 1 read-only P17 Multi Drive Status. 17 1 read-only P18 Multi Drive Status. 18 1 read-only P19 Multi Drive Status. 19 1 read-only P20 Multi Drive Status. 20 1 read-only P21 Multi Drive Status. 21 1 read-only P22 Multi Drive Status. 22 1 read-only P23 Multi Drive Status. 23 1 read-only P24 Multi Drive Status. 24 1 read-only P25 Multi Drive Status. 25 1 read-only P26 Multi Drive Status. 26 1 read-only P27 Multi Drive Status. 27 1 read-only P28 Multi Drive Status. 28 1 read-only P29 Multi Drive Status. 29 1 read-only P30 Multi Drive Status. 30 1 read-only P31 Multi Drive Status. 31 1 read-only PUDR Pull-up Disable Register 0x00000060 32 write-only P0 Pull Up Disable. 0 1 write-only P1 Pull Up Disable. 1 1 write-only P2 Pull Up Disable. 2 1 write-only P3 Pull Up Disable. 3 1 write-only P4 Pull Up Disable. 4 1 write-only P5 Pull Up Disable. 5 1 write-only P6 Pull Up Disable. 6 1 write-only P7 Pull Up Disable. 7 1 write-only P8 Pull Up Disable. 8 1 write-only P9 Pull Up Disable. 9 1 write-only P10 Pull Up Disable. 10 1 write-only P11 Pull Up Disable. 11 1 write-only P12 Pull Up Disable. 12 1 write-only P13 Pull Up Disable. 13 1 write-only P14 Pull Up Disable. 14 1 write-only P15 Pull Up Disable. 15 1 write-only P16 Pull Up Disable. 16 1 write-only P17 Pull Up Disable. 17 1 write-only P18 Pull Up Disable. 18 1 write-only P19 Pull Up Disable. 19 1 write-only P20 Pull Up Disable. 20 1 write-only P21 Pull Up Disable. 21 1 write-only P22 Pull Up Disable. 22 1 write-only P23 Pull Up Disable. 23 1 write-only P24 Pull Up Disable. 24 1 write-only P25 Pull Up Disable. 25 1 write-only P26 Pull Up Disable. 26 1 write-only P27 Pull Up Disable. 27 1 write-only P28 Pull Up Disable. 28 1 write-only P29 Pull Up Disable. 29 1 write-only P30 Pull Up Disable. 30 1 write-only P31 Pull Up Disable. 31 1 write-only PUER Pull-up Enable Register 0x00000064 32 write-only P0 Pull Up Enable. 0 1 write-only P1 Pull Up Enable. 1 1 write-only P2 Pull Up Enable. 2 1 write-only P3 Pull Up Enable. 3 1 write-only P4 Pull Up Enable. 4 1 write-only P5 Pull Up Enable. 5 1 write-only P6 Pull Up Enable. 6 1 write-only P7 Pull Up Enable. 7 1 write-only P8 Pull Up Enable. 8 1 write-only P9 Pull Up Enable. 9 1 write-only P10 Pull Up Enable. 10 1 write-only P11 Pull Up Enable. 11 1 write-only P12 Pull Up Enable. 12 1 write-only P13 Pull Up Enable. 13 1 write-only P14 Pull Up Enable. 14 1 write-only P15 Pull Up Enable. 15 1 write-only P16 Pull Up Enable. 16 1 write-only P17 Pull Up Enable. 17 1 write-only P18 Pull Up Enable. 18 1 write-only P19 Pull Up Enable. 19 1 write-only P20 Pull Up Enable. 20 1 write-only P21 Pull Up Enable. 21 1 write-only P22 Pull Up Enable. 22 1 write-only P23 Pull Up Enable. 23 1 write-only P24 Pull Up Enable. 24 1 write-only P25 Pull Up Enable. 25 1 write-only P26 Pull Up Enable. 26 1 write-only P27 Pull Up Enable. 27 1 write-only P28 Pull Up Enable. 28 1 write-only P29 Pull Up Enable. 29 1 write-only P30 Pull Up Enable. 30 1 write-only P31 Pull Up Enable. 31 1 write-only PUSR Pad Pull-up Status Register 0x00000068 32 read-only 0x00000000 P0 Pull Up Status. 0 1 read-only P1 Pull Up Status. 1 1 read-only P2 Pull Up Status. 2 1 read-only P3 Pull Up Status. 3 1 read-only P4 Pull Up Status. 4 1 read-only P5 Pull Up Status. 5 1 read-only P6 Pull Up Status. 6 1 read-only P7 Pull Up Status. 7 1 read-only P8 Pull Up Status. 8 1 read-only P9 Pull Up Status. 9 1 read-only P10 Pull Up Status. 10 1 read-only P11 Pull Up Status. 11 1 read-only P12 Pull Up Status. 12 1 read-only P13 Pull Up Status. 13 1 read-only P14 Pull Up Status. 14 1 read-only P15 Pull Up Status. 15 1 read-only P16 Pull Up Status. 16 1 read-only P17 Pull Up Status. 17 1 read-only P18 Pull Up Status. 18 1 read-only P19 Pull Up Status. 19 1 read-only P20 Pull Up Status. 20 1 read-only P21 Pull Up Status. 21 1 read-only P22 Pull Up Status. 22 1 read-only P23 Pull Up Status. 23 1 read-only P24 Pull Up Status. 24 1 read-only P25 Pull Up Status. 25 1 read-only P26 Pull Up Status. 26 1 read-only P27 Pull Up Status. 27 1 read-only P28 Pull Up Status. 28 1 read-only P29 Pull Up Status. 29 1 read-only P30 Pull Up Status. 30 1 read-only P31 Pull Up Status. 31 1 read-only ASR Peripheral A Select Register 0x00000070 32 write-only P0 Peripheral A Select. 0 1 write-only P1 Peripheral A Select. 1 1 write-only P2 Peripheral A Select. 2 1 write-only P3 Peripheral A Select. 3 1 write-only P4 Peripheral A Select. 4 1 write-only P5 Peripheral A Select. 5 1 write-only P6 Peripheral A Select. 6 1 write-only P7 Peripheral A Select. 7 1 write-only P8 Peripheral A Select. 8 1 write-only P9 Peripheral A Select. 9 1 write-only P10 Peripheral A Select. 10 1 write-only P11 Peripheral A Select. 11 1 write-only P12 Peripheral A Select. 12 1 write-only P13 Peripheral A Select. 13 1 write-only P14 Peripheral A Select. 14 1 write-only P15 Peripheral A Select. 15 1 write-only P16 Peripheral A Select. 16 1 write-only P17 Peripheral A Select. 17 1 write-only P18 Peripheral A Select. 18 1 write-only P19 Peripheral A Select. 19 1 write-only P20 Peripheral A Select. 20 1 write-only P21 Peripheral A Select. 21 1 write-only P22 Peripheral A Select. 22 1 write-only P23 Peripheral A Select. 23 1 write-only P24 Peripheral A Select. 24 1 write-only P25 Peripheral A Select. 25 1 write-only P26 Peripheral A Select. 26 1 write-only P27 Peripheral A Select. 27 1 write-only P28 Peripheral A Select. 28 1 write-only P29 Peripheral A Select. 29 1 write-only P30 Peripheral A Select. 30 1 write-only P31 Peripheral A Select. 31 1 write-only BSR Peripheral B Select Register 0x00000074 32 write-only P0 Peripheral B Select. 0 1 write-only P1 Peripheral B Select. 1 1 write-only P2 Peripheral B Select. 2 1 write-only P3 Peripheral B Select. 3 1 write-only P4 Peripheral B Select. 4 1 write-only P5 Peripheral B Select. 5 1 write-only P6 Peripheral B Select. 6 1 write-only P7 Peripheral B Select. 7 1 write-only P8 Peripheral B Select. 8 1 write-only P9 Peripheral B Select. 9 1 write-only P10 Peripheral B Select. 10 1 write-only P11 Peripheral B Select. 11 1 write-only P12 Peripheral B Select. 12 1 write-only P13 Peripheral B Select. 13 1 write-only P14 Peripheral B Select. 14 1 write-only P15 Peripheral B Select. 15 1 write-only P16 Peripheral B Select. 16 1 write-only P17 Peripheral B Select. 17 1 write-only P18 Peripheral B Select. 18 1 write-only P19 Peripheral B Select. 19 1 write-only P20 Peripheral B Select. 20 1 write-only P21 Peripheral B Select. 21 1 write-only P22 Peripheral B Select. 22 1 write-only P23 Peripheral B Select. 23 1 write-only P24 Peripheral B Select. 24 1 write-only P25 Peripheral B Select. 25 1 write-only P26 Peripheral B Select. 26 1 write-only P27 Peripheral B Select. 27 1 write-only P28 Peripheral B Select. 28 1 write-only P29 Peripheral B Select. 29 1 write-only P30 Peripheral B Select. 30 1 write-only P31 Peripheral B Select. 31 1 write-only ABSR AB Status Register 0x00000078 32 read-only 0x00000000 P0 Peripheral A B Status. 0 1 read-only P1 Peripheral A B Status. 1 1 read-only P2 Peripheral A B Status. 2 1 read-only P3 Peripheral A B Status. 3 1 read-only P4 Peripheral A B Status. 4 1 read-only P5 Peripheral A B Status. 5 1 read-only P6 Peripheral A B Status. 6 1 read-only P7 Peripheral A B Status. 7 1 read-only P8 Peripheral A B Status. 8 1 read-only P9 Peripheral A B Status. 9 1 read-only P10 Peripheral A B Status. 10 1 read-only P11 Peripheral A B Status. 11 1 read-only P12 Peripheral A B Status. 12 1 read-only P13 Peripheral A B Status. 13 1 read-only P14 Peripheral A B Status. 14 1 read-only P15 Peripheral A B Status. 15 1 read-only P16 Peripheral A B Status. 16 1 read-only P17 Peripheral A B Status. 17 1 read-only P18 Peripheral A B Status. 18 1 read-only P19 Peripheral A B Status. 19 1 read-only P20 Peripheral A B Status. 20 1 read-only P21 Peripheral A B Status. 21 1 read-only P22 Peripheral A B Status. 22 1 read-only P23 Peripheral A B Status. 23 1 read-only P24 Peripheral A B Status. 24 1 read-only P25 Peripheral A B Status. 25 1 read-only P26 Peripheral A B Status. 26 1 read-only P27 Peripheral A B Status. 27 1 read-only P28 Peripheral A B Status. 28 1 read-only P29 Peripheral A B Status. 29 1 read-only P30 Peripheral A B Status. 30 1 read-only P31 Peripheral A B Status. 31 1 read-only OWER Output Write Enable 0x000000A0 32 write-only P0 Output Write Enable. 0 1 write-only P1 Output Write Enable. 1 1 write-only P2 Output Write Enable. 2 1 write-only P3 Output Write Enable. 3 1 write-only P4 Output Write Enable. 4 1 write-only P5 Output Write Enable. 5 1 write-only P6 Output Write Enable. 6 1 write-only P7 Output Write Enable. 7 1 write-only P8 Output Write Enable. 8 1 write-only P9 Output Write Enable. 9 1 write-only P10 Output Write Enable. 10 1 write-only P11 Output Write Enable. 11 1 write-only P12 Output Write Enable. 12 1 write-only P13 Output Write Enable. 13 1 write-only P14 Output Write Enable. 14 1 write-only P15 Output Write Enable. 15 1 write-only P16 Output Write Enable. 16 1 write-only P17 Output Write Enable. 17 1 write-only P18 Output Write Enable. 18 1 write-only P19 Output Write Enable. 19 1 write-only P20 Output Write Enable. 20 1 write-only P21 Output Write Enable. 21 1 write-only P22 Output Write Enable. 22 1 write-only P23 Output Write Enable. 23 1 write-only P24 Output Write Enable. 24 1 write-only P25 Output Write Enable. 25 1 write-only P26 Output Write Enable. 26 1 write-only P27 Output Write Enable. 27 1 write-only P28 Output Write Enable. 28 1 write-only P29 Output Write Enable. 29 1 write-only P30 Output Write Enable. 30 1 write-only P31 Output Write Enable. 31 1 write-only OWDR Output Write Disable 0x000000A4 32 write-only P0 Output Write Disable. 0 1 write-only P1 Output Write Disable. 1 1 write-only P2 Output Write Disable. 2 1 write-only P3 Output Write Disable. 3 1 write-only P4 Output Write Disable. 4 1 write-only P5 Output Write Disable. 5 1 write-only P6 Output Write Disable. 6 1 write-only P7 Output Write Disable. 7 1 write-only P8 Output Write Disable. 8 1 write-only P9 Output Write Disable. 9 1 write-only P10 Output Write Disable. 10 1 write-only P11 Output Write Disable. 11 1 write-only P12 Output Write Disable. 12 1 write-only P13 Output Write Disable. 13 1 write-only P14 Output Write Disable. 14 1 write-only P15 Output Write Disable. 15 1 write-only P16 Output Write Disable. 16 1 write-only P17 Output Write Disable. 17 1 write-only P18 Output Write Disable. 18 1 write-only P19 Output Write Disable. 19 1 write-only P20 Output Write Disable. 20 1 write-only P21 Output Write Disable. 21 1 write-only P22 Output Write Disable. 22 1 write-only P23 Output Write Disable. 23 1 write-only P24 Output Write Disable. 24 1 write-only P25 Output Write Disable. 25 1 write-only P26 Output Write Disable. 26 1 write-only P27 Output Write Disable. 27 1 write-only P28 Output Write Disable. 28 1 write-only P29 Output Write Disable. 29 1 write-only P30 Output Write Disable. 30 1 write-only P31 Output Write Disable. 31 1 write-only OWSR Output Write Status Register 0x000000A8 32 read-only 0x00000000 P0 Output Write Status. 0 1 read-only P1 Output Write Status. 1 1 read-only P2 Output Write Status. 2 1 read-only P3 Output Write Status. 3 1 read-only P4 Output Write Status. 4 1 read-only P5 Output Write Status. 5 1 read-only P6 Output Write Status. 6 1 read-only P7 Output Write Status. 7 1 read-only P8 Output Write Status. 8 1 read-only P9 Output Write Status. 9 1 read-only P10 Output Write Status. 10 1 read-only P11 Output Write Status. 11 1 read-only P12 Output Write Status. 12 1 read-only P13 Output Write Status. 13 1 read-only P14 Output Write Status. 14 1 read-only P15 Output Write Status. 15 1 read-only P16 Output Write Status. 16 1 read-only P17 Output Write Status. 17 1 read-only P18 Output Write Status. 18 1 read-only P19 Output Write Status. 19 1 read-only P20 Output Write Status. 20 1 read-only P21 Output Write Status. 21 1 read-only P22 Output Write Status. 22 1 read-only P23 Output Write Status. 23 1 read-only P24 Output Write Status. 24 1 read-only P25 Output Write Status. 25 1 read-only P26 Output Write Status. 26 1 read-only P27 Output Write Status. 27 1 read-only P28 Output Write Status. 28 1 read-only P29 Output Write Status. 29 1 read-only P30 Output Write Status. 30 1 read-only P31 Output Write Status. 31 1 read-only 4 4 0-3 DELAYR[%s] I/O Delay Register 0x000000C0 32 read-write Delay0 0 4 read-write Delay1 4 4 read-write Delay2 8 4 read-write Delay3 12 4 read-write Delay4 16 4 read-write Delay5 20 4 read-write Delay6 24 4 read-write Delay7 28 4 read-write WPMR Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write WPSR Write Protect Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protect Enable 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only PIOD 6057F Parallel Input/Output Controller D PIO PIOD_ 0xFFFFF800 0 0x200 registers PIOD 5 PER PIO Enable Register 0x00000000 32 write-only P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P2 PIO Enable 2 1 write-only P3 PIO Enable 3 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only PDR PIO Disable Register 0x00000004 32 write-only P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P2 PIO Disable 2 1 write-only P3 PIO Disable 3 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only PSR PIO Status Register 0x00000008 32 read-only P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P2 PIO Status 2 1 read-only P3 PIO Status 3 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only OER Output Enable Register 0x00000010 32 write-only P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P2 Output Enable 2 1 write-only P3 Output Enable 3 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only ODR Output Disable Register 0x00000014 32 write-only P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P2 Output Disable 2 1 write-only P3 Output Disable 3 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only OSR Output Status Register 0x00000018 32 read-only 0x00000000 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P2 Output Status 2 1 read-only P3 Output Status 3 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only IFER Glitch Input Filter Enable Register 0x00000020 32 write-only P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P2 Input Filter Enable 2 1 write-only P3 Input Filter Enable 3 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only IFDR Glitch Input Filter Disable Register 0x00000024 32 write-only P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P2 Input Filter Disable 2 1 write-only P3 Input Filter Disable 3 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only IFSR Glitch Input Filter Status Register 0x00000028 32 read-only 0x00000000 P0 Input Filer Status 0 1 read-only P1 Input Filer Status 1 1 read-only P2 Input Filer Status 2 1 read-only P3 Input Filer Status 3 1 read-only P4 Input Filer Status 4 1 read-only P5 Input Filer Status 5 1 read-only P6 Input Filer Status 6 1 read-only P7 Input Filer Status 7 1 read-only P8 Input Filer Status 8 1 read-only P9 Input Filer Status 9 1 read-only P10 Input Filer Status 10 1 read-only P11 Input Filer Status 11 1 read-only P12 Input Filer Status 12 1 read-only P13 Input Filer Status 13 1 read-only P14 Input Filer Status 14 1 read-only P15 Input Filer Status 15 1 read-only P16 Input Filer Status 16 1 read-only P17 Input Filer Status 17 1 read-only P18 Input Filer Status 18 1 read-only P19 Input Filer Status 19 1 read-only P20 Input Filer Status 20 1 read-only P21 Input Filer Status 21 1 read-only P22 Input Filer Status 22 1 read-only P23 Input Filer Status 23 1 read-only P24 Input Filer Status 24 1 read-only P25 Input Filer Status 25 1 read-only P26 Input Filer Status 26 1 read-only P27 Input Filer Status 27 1 read-only P28 Input Filer Status 28 1 read-only P29 Input Filer Status 29 1 read-only P30 Input Filer Status 30 1 read-only P31 Input Filer Status 31 1 read-only SODR Set Output Data Register 0x00000030 32 write-only P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P2 Set Output Data 2 1 write-only P3 Set Output Data 3 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only CODR Clear Output Data Register 0x00000034 32 write-only P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P2 Clear Output Data 2 1 write-only P3 Clear Output Data 3 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only ODSR Output Data Status Register 0x00000038 32 read-write P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P2 Output Data Status 2 1 read-write P3 Output Data Status 3 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write PDSR Pin Data Status Register 0x0000003C 32 read-only P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P2 Output Data Status 2 1 read-only P3 Output Data Status 3 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only IER Interrupt Enable Register 0x00000040 32 write-only P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only IDR Interrupt Disable Register 0x00000044 32 write-only P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only IMR Interrupt Mask Register 0x00000048 32 read-only 0x00000000 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only ISR Interrupt Status Register 0x0000004C 32 read-only 0x00000000 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P2 Input Change Interrupt Status 2 1 read-only P3 Input Change Interrupt Status 3 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only MDER Multi-driver Enable Register 0x00000050 32 write-only P0 Multi Drive Enable. 0 1 write-only P1 Multi Drive Enable. 1 1 write-only P2 Multi Drive Enable. 2 1 write-only P3 Multi Drive Enable. 3 1 write-only P4 Multi Drive Enable. 4 1 write-only P5 Multi Drive Enable. 5 1 write-only P6 Multi Drive Enable. 6 1 write-only P7 Multi Drive Enable. 7 1 write-only P8 Multi Drive Enable. 8 1 write-only P9 Multi Drive Enable. 9 1 write-only P10 Multi Drive Enable. 10 1 write-only P11 Multi Drive Enable. 11 1 write-only P12 Multi Drive Enable. 12 1 write-only P13 Multi Drive Enable. 13 1 write-only P14 Multi Drive Enable. 14 1 write-only P15 Multi Drive Enable. 15 1 write-only P16 Multi Drive Enable. 16 1 write-only P17 Multi Drive Enable. 17 1 write-only P18 Multi Drive Enable. 18 1 write-only P19 Multi Drive Enable. 19 1 write-only P20 Multi Drive Enable. 20 1 write-only P21 Multi Drive Enable. 21 1 write-only P22 Multi Drive Enable. 22 1 write-only P23 Multi Drive Enable. 23 1 write-only P24 Multi Drive Enable. 24 1 write-only P25 Multi Drive Enable. 25 1 write-only P26 Multi Drive Enable. 26 1 write-only P27 Multi Drive Enable. 27 1 write-only P28 Multi Drive Enable. 28 1 write-only P29 Multi Drive Enable. 29 1 write-only P30 Multi Drive Enable. 30 1 write-only P31 Multi Drive Enable. 31 1 write-only MDDR Multi-driver Disable Register 0x00000054 32 write-only P0 Multi Drive Disable. 0 1 write-only P1 Multi Drive Disable. 1 1 write-only P2 Multi Drive Disable. 2 1 write-only P3 Multi Drive Disable. 3 1 write-only P4 Multi Drive Disable. 4 1 write-only P5 Multi Drive Disable. 5 1 write-only P6 Multi Drive Disable. 6 1 write-only P7 Multi Drive Disable. 7 1 write-only P8 Multi Drive Disable. 8 1 write-only P9 Multi Drive Disable. 9 1 write-only P10 Multi Drive Disable. 10 1 write-only P11 Multi Drive Disable. 11 1 write-only P12 Multi Drive Disable. 12 1 write-only P13 Multi Drive Disable. 13 1 write-only P14 Multi Drive Disable. 14 1 write-only P15 Multi Drive Disable. 15 1 write-only P16 Multi Drive Disable. 16 1 write-only P17 Multi Drive Disable. 17 1 write-only P18 Multi Drive Disable. 18 1 write-only P19 Multi Drive Disable. 19 1 write-only P20 Multi Drive Disable. 20 1 write-only P21 Multi Drive Disable. 21 1 write-only P22 Multi Drive Disable. 22 1 write-only P23 Multi Drive Disable. 23 1 write-only P24 Multi Drive Disable. 24 1 write-only P25 Multi Drive Disable. 25 1 write-only P26 Multi Drive Disable. 26 1 write-only P27 Multi Drive Disable. 27 1 write-only P28 Multi Drive Disable. 28 1 write-only P29 Multi Drive Disable. 29 1 write-only P30 Multi Drive Disable. 30 1 write-only P31 Multi Drive Disable. 31 1 write-only MDSR Multi-driver Status Register 0x00000058 32 read-only 0x00000000 P0 Multi Drive Status. 0 1 read-only P1 Multi Drive Status. 1 1 read-only P2 Multi Drive Status. 2 1 read-only P3 Multi Drive Status. 3 1 read-only P4 Multi Drive Status. 4 1 read-only P5 Multi Drive Status. 5 1 read-only P6 Multi Drive Status. 6 1 read-only P7 Multi Drive Status. 7 1 read-only P8 Multi Drive Status. 8 1 read-only P9 Multi Drive Status. 9 1 read-only P10 Multi Drive Status. 10 1 read-only P11 Multi Drive Status. 11 1 read-only P12 Multi Drive Status. 12 1 read-only P13 Multi Drive Status. 13 1 read-only P14 Multi Drive Status. 14 1 read-only P15 Multi Drive Status. 15 1 read-only P16 Multi Drive Status. 16 1 read-only P17 Multi Drive Status. 17 1 read-only P18 Multi Drive Status. 18 1 read-only P19 Multi Drive Status. 19 1 read-only P20 Multi Drive Status. 20 1 read-only P21 Multi Drive Status. 21 1 read-only P22 Multi Drive Status. 22 1 read-only P23 Multi Drive Status. 23 1 read-only P24 Multi Drive Status. 24 1 read-only P25 Multi Drive Status. 25 1 read-only P26 Multi Drive Status. 26 1 read-only P27 Multi Drive Status. 27 1 read-only P28 Multi Drive Status. 28 1 read-only P29 Multi Drive Status. 29 1 read-only P30 Multi Drive Status. 30 1 read-only P31 Multi Drive Status. 31 1 read-only PUDR Pull-up Disable Register 0x00000060 32 write-only P0 Pull Up Disable. 0 1 write-only P1 Pull Up Disable. 1 1 write-only P2 Pull Up Disable. 2 1 write-only P3 Pull Up Disable. 3 1 write-only P4 Pull Up Disable. 4 1 write-only P5 Pull Up Disable. 5 1 write-only P6 Pull Up Disable. 6 1 write-only P7 Pull Up Disable. 7 1 write-only P8 Pull Up Disable. 8 1 write-only P9 Pull Up Disable. 9 1 write-only P10 Pull Up Disable. 10 1 write-only P11 Pull Up Disable. 11 1 write-only P12 Pull Up Disable. 12 1 write-only P13 Pull Up Disable. 13 1 write-only P14 Pull Up Disable. 14 1 write-only P15 Pull Up Disable. 15 1 write-only P16 Pull Up Disable. 16 1 write-only P17 Pull Up Disable. 17 1 write-only P18 Pull Up Disable. 18 1 write-only P19 Pull Up Disable. 19 1 write-only P20 Pull Up Disable. 20 1 write-only P21 Pull Up Disable. 21 1 write-only P22 Pull Up Disable. 22 1 write-only P23 Pull Up Disable. 23 1 write-only P24 Pull Up Disable. 24 1 write-only P25 Pull Up Disable. 25 1 write-only P26 Pull Up Disable. 26 1 write-only P27 Pull Up Disable. 27 1 write-only P28 Pull Up Disable. 28 1 write-only P29 Pull Up Disable. 29 1 write-only P30 Pull Up Disable. 30 1 write-only P31 Pull Up Disable. 31 1 write-only PUER Pull-up Enable Register 0x00000064 32 write-only P0 Pull Up Enable. 0 1 write-only P1 Pull Up Enable. 1 1 write-only P2 Pull Up Enable. 2 1 write-only P3 Pull Up Enable. 3 1 write-only P4 Pull Up Enable. 4 1 write-only P5 Pull Up Enable. 5 1 write-only P6 Pull Up Enable. 6 1 write-only P7 Pull Up Enable. 7 1 write-only P8 Pull Up Enable. 8 1 write-only P9 Pull Up Enable. 9 1 write-only P10 Pull Up Enable. 10 1 write-only P11 Pull Up Enable. 11 1 write-only P12 Pull Up Enable. 12 1 write-only P13 Pull Up Enable. 13 1 write-only P14 Pull Up Enable. 14 1 write-only P15 Pull Up Enable. 15 1 write-only P16 Pull Up Enable. 16 1 write-only P17 Pull Up Enable. 17 1 write-only P18 Pull Up Enable. 18 1 write-only P19 Pull Up Enable. 19 1 write-only P20 Pull Up Enable. 20 1 write-only P21 Pull Up Enable. 21 1 write-only P22 Pull Up Enable. 22 1 write-only P23 Pull Up Enable. 23 1 write-only P24 Pull Up Enable. 24 1 write-only P25 Pull Up Enable. 25 1 write-only P26 Pull Up Enable. 26 1 write-only P27 Pull Up Enable. 27 1 write-only P28 Pull Up Enable. 28 1 write-only P29 Pull Up Enable. 29 1 write-only P30 Pull Up Enable. 30 1 write-only P31 Pull Up Enable. 31 1 write-only PUSR Pad Pull-up Status Register 0x00000068 32 read-only 0x00000000 P0 Pull Up Status. 0 1 read-only P1 Pull Up Status. 1 1 read-only P2 Pull Up Status. 2 1 read-only P3 Pull Up Status. 3 1 read-only P4 Pull Up Status. 4 1 read-only P5 Pull Up Status. 5 1 read-only P6 Pull Up Status. 6 1 read-only P7 Pull Up Status. 7 1 read-only P8 Pull Up Status. 8 1 read-only P9 Pull Up Status. 9 1 read-only P10 Pull Up Status. 10 1 read-only P11 Pull Up Status. 11 1 read-only P12 Pull Up Status. 12 1 read-only P13 Pull Up Status. 13 1 read-only P14 Pull Up Status. 14 1 read-only P15 Pull Up Status. 15 1 read-only P16 Pull Up Status. 16 1 read-only P17 Pull Up Status. 17 1 read-only P18 Pull Up Status. 18 1 read-only P19 Pull Up Status. 19 1 read-only P20 Pull Up Status. 20 1 read-only P21 Pull Up Status. 21 1 read-only P22 Pull Up Status. 22 1 read-only P23 Pull Up Status. 23 1 read-only P24 Pull Up Status. 24 1 read-only P25 Pull Up Status. 25 1 read-only P26 Pull Up Status. 26 1 read-only P27 Pull Up Status. 27 1 read-only P28 Pull Up Status. 28 1 read-only P29 Pull Up Status. 29 1 read-only P30 Pull Up Status. 30 1 read-only P31 Pull Up Status. 31 1 read-only ASR Peripheral A Select Register 0x00000070 32 write-only P0 Peripheral A Select. 0 1 write-only P1 Peripheral A Select. 1 1 write-only P2 Peripheral A Select. 2 1 write-only P3 Peripheral A Select. 3 1 write-only P4 Peripheral A Select. 4 1 write-only P5 Peripheral A Select. 5 1 write-only P6 Peripheral A Select. 6 1 write-only P7 Peripheral A Select. 7 1 write-only P8 Peripheral A Select. 8 1 write-only P9 Peripheral A Select. 9 1 write-only P10 Peripheral A Select. 10 1 write-only P11 Peripheral A Select. 11 1 write-only P12 Peripheral A Select. 12 1 write-only P13 Peripheral A Select. 13 1 write-only P14 Peripheral A Select. 14 1 write-only P15 Peripheral A Select. 15 1 write-only P16 Peripheral A Select. 16 1 write-only P17 Peripheral A Select. 17 1 write-only P18 Peripheral A Select. 18 1 write-only P19 Peripheral A Select. 19 1 write-only P20 Peripheral A Select. 20 1 write-only P21 Peripheral A Select. 21 1 write-only P22 Peripheral A Select. 22 1 write-only P23 Peripheral A Select. 23 1 write-only P24 Peripheral A Select. 24 1 write-only P25 Peripheral A Select. 25 1 write-only P26 Peripheral A Select. 26 1 write-only P27 Peripheral A Select. 27 1 write-only P28 Peripheral A Select. 28 1 write-only P29 Peripheral A Select. 29 1 write-only P30 Peripheral A Select. 30 1 write-only P31 Peripheral A Select. 31 1 write-only BSR Peripheral B Select Register 0x00000074 32 write-only P0 Peripheral B Select. 0 1 write-only P1 Peripheral B Select. 1 1 write-only P2 Peripheral B Select. 2 1 write-only P3 Peripheral B Select. 3 1 write-only P4 Peripheral B Select. 4 1 write-only P5 Peripheral B Select. 5 1 write-only P6 Peripheral B Select. 6 1 write-only P7 Peripheral B Select. 7 1 write-only P8 Peripheral B Select. 8 1 write-only P9 Peripheral B Select. 9 1 write-only P10 Peripheral B Select. 10 1 write-only P11 Peripheral B Select. 11 1 write-only P12 Peripheral B Select. 12 1 write-only P13 Peripheral B Select. 13 1 write-only P14 Peripheral B Select. 14 1 write-only P15 Peripheral B Select. 15 1 write-only P16 Peripheral B Select. 16 1 write-only P17 Peripheral B Select. 17 1 write-only P18 Peripheral B Select. 18 1 write-only P19 Peripheral B Select. 19 1 write-only P20 Peripheral B Select. 20 1 write-only P21 Peripheral B Select. 21 1 write-only P22 Peripheral B Select. 22 1 write-only P23 Peripheral B Select. 23 1 write-only P24 Peripheral B Select. 24 1 write-only P25 Peripheral B Select. 25 1 write-only P26 Peripheral B Select. 26 1 write-only P27 Peripheral B Select. 27 1 write-only P28 Peripheral B Select. 28 1 write-only P29 Peripheral B Select. 29 1 write-only P30 Peripheral B Select. 30 1 write-only P31 Peripheral B Select. 31 1 write-only ABSR AB Status Register 0x00000078 32 read-only 0x00000000 P0 Peripheral A B Status. 0 1 read-only P1 Peripheral A B Status. 1 1 read-only P2 Peripheral A B Status. 2 1 read-only P3 Peripheral A B Status. 3 1 read-only P4 Peripheral A B Status. 4 1 read-only P5 Peripheral A B Status. 5 1 read-only P6 Peripheral A B Status. 6 1 read-only P7 Peripheral A B Status. 7 1 read-only P8 Peripheral A B Status. 8 1 read-only P9 Peripheral A B Status. 9 1 read-only P10 Peripheral A B Status. 10 1 read-only P11 Peripheral A B Status. 11 1 read-only P12 Peripheral A B Status. 12 1 read-only P13 Peripheral A B Status. 13 1 read-only P14 Peripheral A B Status. 14 1 read-only P15 Peripheral A B Status. 15 1 read-only P16 Peripheral A B Status. 16 1 read-only P17 Peripheral A B Status. 17 1 read-only P18 Peripheral A B Status. 18 1 read-only P19 Peripheral A B Status. 19 1 read-only P20 Peripheral A B Status. 20 1 read-only P21 Peripheral A B Status. 21 1 read-only P22 Peripheral A B Status. 22 1 read-only P23 Peripheral A B Status. 23 1 read-only P24 Peripheral A B Status. 24 1 read-only P25 Peripheral A B Status. 25 1 read-only P26 Peripheral A B Status. 26 1 read-only P27 Peripheral A B Status. 27 1 read-only P28 Peripheral A B Status. 28 1 read-only P29 Peripheral A B Status. 29 1 read-only P30 Peripheral A B Status. 30 1 read-only P31 Peripheral A B Status. 31 1 read-only OWER Output Write Enable 0x000000A0 32 write-only P0 Output Write Enable. 0 1 write-only P1 Output Write Enable. 1 1 write-only P2 Output Write Enable. 2 1 write-only P3 Output Write Enable. 3 1 write-only P4 Output Write Enable. 4 1 write-only P5 Output Write Enable. 5 1 write-only P6 Output Write Enable. 6 1 write-only P7 Output Write Enable. 7 1 write-only P8 Output Write Enable. 8 1 write-only P9 Output Write Enable. 9 1 write-only P10 Output Write Enable. 10 1 write-only P11 Output Write Enable. 11 1 write-only P12 Output Write Enable. 12 1 write-only P13 Output Write Enable. 13 1 write-only P14 Output Write Enable. 14 1 write-only P15 Output Write Enable. 15 1 write-only P16 Output Write Enable. 16 1 write-only P17 Output Write Enable. 17 1 write-only P18 Output Write Enable. 18 1 write-only P19 Output Write Enable. 19 1 write-only P20 Output Write Enable. 20 1 write-only P21 Output Write Enable. 21 1 write-only P22 Output Write Enable. 22 1 write-only P23 Output Write Enable. 23 1 write-only P24 Output Write Enable. 24 1 write-only P25 Output Write Enable. 25 1 write-only P26 Output Write Enable. 26 1 write-only P27 Output Write Enable. 27 1 write-only P28 Output Write Enable. 28 1 write-only P29 Output Write Enable. 29 1 write-only P30 Output Write Enable. 30 1 write-only P31 Output Write Enable. 31 1 write-only OWDR Output Write Disable 0x000000A4 32 write-only P0 Output Write Disable. 0 1 write-only P1 Output Write Disable. 1 1 write-only P2 Output Write Disable. 2 1 write-only P3 Output Write Disable. 3 1 write-only P4 Output Write Disable. 4 1 write-only P5 Output Write Disable. 5 1 write-only P6 Output Write Disable. 6 1 write-only P7 Output Write Disable. 7 1 write-only P8 Output Write Disable. 8 1 write-only P9 Output Write Disable. 9 1 write-only P10 Output Write Disable. 10 1 write-only P11 Output Write Disable. 11 1 write-only P12 Output Write Disable. 12 1 write-only P13 Output Write Disable. 13 1 write-only P14 Output Write Disable. 14 1 write-only P15 Output Write Disable. 15 1 write-only P16 Output Write Disable. 16 1 write-only P17 Output Write Disable. 17 1 write-only P18 Output Write Disable. 18 1 write-only P19 Output Write Disable. 19 1 write-only P20 Output Write Disable. 20 1 write-only P21 Output Write Disable. 21 1 write-only P22 Output Write Disable. 22 1 write-only P23 Output Write Disable. 23 1 write-only P24 Output Write Disable. 24 1 write-only P25 Output Write Disable. 25 1 write-only P26 Output Write Disable. 26 1 write-only P27 Output Write Disable. 27 1 write-only P28 Output Write Disable. 28 1 write-only P29 Output Write Disable. 29 1 write-only P30 Output Write Disable. 30 1 write-only P31 Output Write Disable. 31 1 write-only OWSR Output Write Status Register 0x000000A8 32 read-only 0x00000000 P0 Output Write Status. 0 1 read-only P1 Output Write Status. 1 1 read-only P2 Output Write Status. 2 1 read-only P3 Output Write Status. 3 1 read-only P4 Output Write Status. 4 1 read-only P5 Output Write Status. 5 1 read-only P6 Output Write Status. 6 1 read-only P7 Output Write Status. 7 1 read-only P8 Output Write Status. 8 1 read-only P9 Output Write Status. 9 1 read-only P10 Output Write Status. 10 1 read-only P11 Output Write Status. 11 1 read-only P12 Output Write Status. 12 1 read-only P13 Output Write Status. 13 1 read-only P14 Output Write Status. 14 1 read-only P15 Output Write Status. 15 1 read-only P16 Output Write Status. 16 1 read-only P17 Output Write Status. 17 1 read-only P18 Output Write Status. 18 1 read-only P19 Output Write Status. 19 1 read-only P20 Output Write Status. 20 1 read-only P21 Output Write Status. 21 1 read-only P22 Output Write Status. 22 1 read-only P23 Output Write Status. 23 1 read-only P24 Output Write Status. 24 1 read-only P25 Output Write Status. 25 1 read-only P26 Output Write Status. 26 1 read-only P27 Output Write Status. 27 1 read-only P28 Output Write Status. 28 1 read-only P29 Output Write Status. 29 1 read-only P30 Output Write Status. 30 1 read-only P31 Output Write Status. 31 1 read-only 4 4 0-3 DELAYR[%s] I/O Delay Register 0x000000C0 32 read-write Delay0 0 4 read-write Delay1 4 4 read-write Delay2 8 4 read-write Delay3 12 4 read-write Delay4 16 4 read-write Delay5 20 4 read-write Delay6 24 4 read-write Delay7 28 4 read-write WPMR Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write WPSR Write Protect Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protect Enable 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only PIOE 6057F Parallel Input/Output Controller E PIO PIOE_ 0xFFFFFA00 0 0x200 registers PER PIO Enable Register 0x00000000 32 write-only P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P2 PIO Enable 2 1 write-only P3 PIO Enable 3 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only PDR PIO Disable Register 0x00000004 32 write-only P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P2 PIO Disable 2 1 write-only P3 PIO Disable 3 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only PSR PIO Status Register 0x00000008 32 read-only P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P2 PIO Status 2 1 read-only P3 PIO Status 3 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only OER Output Enable Register 0x00000010 32 write-only P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P2 Output Enable 2 1 write-only P3 Output Enable 3 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only ODR Output Disable Register 0x00000014 32 write-only P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P2 Output Disable 2 1 write-only P3 Output Disable 3 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only OSR Output Status Register 0x00000018 32 read-only 0x00000000 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P2 Output Status 2 1 read-only P3 Output Status 3 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only IFER Glitch Input Filter Enable Register 0x00000020 32 write-only P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P2 Input Filter Enable 2 1 write-only P3 Input Filter Enable 3 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only IFDR Glitch Input Filter Disable Register 0x00000024 32 write-only P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P2 Input Filter Disable 2 1 write-only P3 Input Filter Disable 3 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only IFSR Glitch Input Filter Status Register 0x00000028 32 read-only 0x00000000 P0 Input Filer Status 0 1 read-only P1 Input Filer Status 1 1 read-only P2 Input Filer Status 2 1 read-only P3 Input Filer Status 3 1 read-only P4 Input Filer Status 4 1 read-only P5 Input Filer Status 5 1 read-only P6 Input Filer Status 6 1 read-only P7 Input Filer Status 7 1 read-only P8 Input Filer Status 8 1 read-only P9 Input Filer Status 9 1 read-only P10 Input Filer Status 10 1 read-only P11 Input Filer Status 11 1 read-only P12 Input Filer Status 12 1 read-only P13 Input Filer Status 13 1 read-only P14 Input Filer Status 14 1 read-only P15 Input Filer Status 15 1 read-only P16 Input Filer Status 16 1 read-only P17 Input Filer Status 17 1 read-only P18 Input Filer Status 18 1 read-only P19 Input Filer Status 19 1 read-only P20 Input Filer Status 20 1 read-only P21 Input Filer Status 21 1 read-only P22 Input Filer Status 22 1 read-only P23 Input Filer Status 23 1 read-only P24 Input Filer Status 24 1 read-only P25 Input Filer Status 25 1 read-only P26 Input Filer Status 26 1 read-only P27 Input Filer Status 27 1 read-only P28 Input Filer Status 28 1 read-only P29 Input Filer Status 29 1 read-only P30 Input Filer Status 30 1 read-only P31 Input Filer Status 31 1 read-only SODR Set Output Data Register 0x00000030 32 write-only P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P2 Set Output Data 2 1 write-only P3 Set Output Data 3 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only CODR Clear Output Data Register 0x00000034 32 write-only P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P2 Clear Output Data 2 1 write-only P3 Clear Output Data 3 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only ODSR Output Data Status Register 0x00000038 32 read-write P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P2 Output Data Status 2 1 read-write P3 Output Data Status 3 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write PDSR Pin Data Status Register 0x0000003C 32 read-only P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P2 Output Data Status 2 1 read-only P3 Output Data Status 3 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only IER Interrupt Enable Register 0x00000040 32 write-only P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only IDR Interrupt Disable Register 0x00000044 32 write-only P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only IMR Interrupt Mask Register 0x00000048 32 read-only 0x00000000 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only ISR Interrupt Status Register 0x0000004C 32 read-only 0x00000000 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P2 Input Change Interrupt Status 2 1 read-only P3 Input Change Interrupt Status 3 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only MDER Multi-driver Enable Register 0x00000050 32 write-only P0 Multi Drive Enable. 0 1 write-only P1 Multi Drive Enable. 1 1 write-only P2 Multi Drive Enable. 2 1 write-only P3 Multi Drive Enable. 3 1 write-only P4 Multi Drive Enable. 4 1 write-only P5 Multi Drive Enable. 5 1 write-only P6 Multi Drive Enable. 6 1 write-only P7 Multi Drive Enable. 7 1 write-only P8 Multi Drive Enable. 8 1 write-only P9 Multi Drive Enable. 9 1 write-only P10 Multi Drive Enable. 10 1 write-only P11 Multi Drive Enable. 11 1 write-only P12 Multi Drive Enable. 12 1 write-only P13 Multi Drive Enable. 13 1 write-only P14 Multi Drive Enable. 14 1 write-only P15 Multi Drive Enable. 15 1 write-only P16 Multi Drive Enable. 16 1 write-only P17 Multi Drive Enable. 17 1 write-only P18 Multi Drive Enable. 18 1 write-only P19 Multi Drive Enable. 19 1 write-only P20 Multi Drive Enable. 20 1 write-only P21 Multi Drive Enable. 21 1 write-only P22 Multi Drive Enable. 22 1 write-only P23 Multi Drive Enable. 23 1 write-only P24 Multi Drive Enable. 24 1 write-only P25 Multi Drive Enable. 25 1 write-only P26 Multi Drive Enable. 26 1 write-only P27 Multi Drive Enable. 27 1 write-only P28 Multi Drive Enable. 28 1 write-only P29 Multi Drive Enable. 29 1 write-only P30 Multi Drive Enable. 30 1 write-only P31 Multi Drive Enable. 31 1 write-only MDDR Multi-driver Disable Register 0x00000054 32 write-only P0 Multi Drive Disable. 0 1 write-only P1 Multi Drive Disable. 1 1 write-only P2 Multi Drive Disable. 2 1 write-only P3 Multi Drive Disable. 3 1 write-only P4 Multi Drive Disable. 4 1 write-only P5 Multi Drive Disable. 5 1 write-only P6 Multi Drive Disable. 6 1 write-only P7 Multi Drive Disable. 7 1 write-only P8 Multi Drive Disable. 8 1 write-only P9 Multi Drive Disable. 9 1 write-only P10 Multi Drive Disable. 10 1 write-only P11 Multi Drive Disable. 11 1 write-only P12 Multi Drive Disable. 12 1 write-only P13 Multi Drive Disable. 13 1 write-only P14 Multi Drive Disable. 14 1 write-only P15 Multi Drive Disable. 15 1 write-only P16 Multi Drive Disable. 16 1 write-only P17 Multi Drive Disable. 17 1 write-only P18 Multi Drive Disable. 18 1 write-only P19 Multi Drive Disable. 19 1 write-only P20 Multi Drive Disable. 20 1 write-only P21 Multi Drive Disable. 21 1 write-only P22 Multi Drive Disable. 22 1 write-only P23 Multi Drive Disable. 23 1 write-only P24 Multi Drive Disable. 24 1 write-only P25 Multi Drive Disable. 25 1 write-only P26 Multi Drive Disable. 26 1 write-only P27 Multi Drive Disable. 27 1 write-only P28 Multi Drive Disable. 28 1 write-only P29 Multi Drive Disable. 29 1 write-only P30 Multi Drive Disable. 30 1 write-only P31 Multi Drive Disable. 31 1 write-only MDSR Multi-driver Status Register 0x00000058 32 read-only 0x00000000 P0 Multi Drive Status. 0 1 read-only P1 Multi Drive Status. 1 1 read-only P2 Multi Drive Status. 2 1 read-only P3 Multi Drive Status. 3 1 read-only P4 Multi Drive Status. 4 1 read-only P5 Multi Drive Status. 5 1 read-only P6 Multi Drive Status. 6 1 read-only P7 Multi Drive Status. 7 1 read-only P8 Multi Drive Status. 8 1 read-only P9 Multi Drive Status. 9 1 read-only P10 Multi Drive Status. 10 1 read-only P11 Multi Drive Status. 11 1 read-only P12 Multi Drive Status. 12 1 read-only P13 Multi Drive Status. 13 1 read-only P14 Multi Drive Status. 14 1 read-only P15 Multi Drive Status. 15 1 read-only P16 Multi Drive Status. 16 1 read-only P17 Multi Drive Status. 17 1 read-only P18 Multi Drive Status. 18 1 read-only P19 Multi Drive Status. 19 1 read-only P20 Multi Drive Status. 20 1 read-only P21 Multi Drive Status. 21 1 read-only P22 Multi Drive Status. 22 1 read-only P23 Multi Drive Status. 23 1 read-only P24 Multi Drive Status. 24 1 read-only P25 Multi Drive Status. 25 1 read-only P26 Multi Drive Status. 26 1 read-only P27 Multi Drive Status. 27 1 read-only P28 Multi Drive Status. 28 1 read-only P29 Multi Drive Status. 29 1 read-only P30 Multi Drive Status. 30 1 read-only P31 Multi Drive Status. 31 1 read-only PUDR Pull-up Disable Register 0x00000060 32 write-only P0 Pull Up Disable. 0 1 write-only P1 Pull Up Disable. 1 1 write-only P2 Pull Up Disable. 2 1 write-only P3 Pull Up Disable. 3 1 write-only P4 Pull Up Disable. 4 1 write-only P5 Pull Up Disable. 5 1 write-only P6 Pull Up Disable. 6 1 write-only P7 Pull Up Disable. 7 1 write-only P8 Pull Up Disable. 8 1 write-only P9 Pull Up Disable. 9 1 write-only P10 Pull Up Disable. 10 1 write-only P11 Pull Up Disable. 11 1 write-only P12 Pull Up Disable. 12 1 write-only P13 Pull Up Disable. 13 1 write-only P14 Pull Up Disable. 14 1 write-only P15 Pull Up Disable. 15 1 write-only P16 Pull Up Disable. 16 1 write-only P17 Pull Up Disable. 17 1 write-only P18 Pull Up Disable. 18 1 write-only P19 Pull Up Disable. 19 1 write-only P20 Pull Up Disable. 20 1 write-only P21 Pull Up Disable. 21 1 write-only P22 Pull Up Disable. 22 1 write-only P23 Pull Up Disable. 23 1 write-only P24 Pull Up Disable. 24 1 write-only P25 Pull Up Disable. 25 1 write-only P26 Pull Up Disable. 26 1 write-only P27 Pull Up Disable. 27 1 write-only P28 Pull Up Disable. 28 1 write-only P29 Pull Up Disable. 29 1 write-only P30 Pull Up Disable. 30 1 write-only P31 Pull Up Disable. 31 1 write-only PUER Pull-up Enable Register 0x00000064 32 write-only P0 Pull Up Enable. 0 1 write-only P1 Pull Up Enable. 1 1 write-only P2 Pull Up Enable. 2 1 write-only P3 Pull Up Enable. 3 1 write-only P4 Pull Up Enable. 4 1 write-only P5 Pull Up Enable. 5 1 write-only P6 Pull Up Enable. 6 1 write-only P7 Pull Up Enable. 7 1 write-only P8 Pull Up Enable. 8 1 write-only P9 Pull Up Enable. 9 1 write-only P10 Pull Up Enable. 10 1 write-only P11 Pull Up Enable. 11 1 write-only P12 Pull Up Enable. 12 1 write-only P13 Pull Up Enable. 13 1 write-only P14 Pull Up Enable. 14 1 write-only P15 Pull Up Enable. 15 1 write-only P16 Pull Up Enable. 16 1 write-only P17 Pull Up Enable. 17 1 write-only P18 Pull Up Enable. 18 1 write-only P19 Pull Up Enable. 19 1 write-only P20 Pull Up Enable. 20 1 write-only P21 Pull Up Enable. 21 1 write-only P22 Pull Up Enable. 22 1 write-only P23 Pull Up Enable. 23 1 write-only P24 Pull Up Enable. 24 1 write-only P25 Pull Up Enable. 25 1 write-only P26 Pull Up Enable. 26 1 write-only P27 Pull Up Enable. 27 1 write-only P28 Pull Up Enable. 28 1 write-only P29 Pull Up Enable. 29 1 write-only P30 Pull Up Enable. 30 1 write-only P31 Pull Up Enable. 31 1 write-only PUSR Pad Pull-up Status Register 0x00000068 32 read-only 0x00000000 P0 Pull Up Status. 0 1 read-only P1 Pull Up Status. 1 1 read-only P2 Pull Up Status. 2 1 read-only P3 Pull Up Status. 3 1 read-only P4 Pull Up Status. 4 1 read-only P5 Pull Up Status. 5 1 read-only P6 Pull Up Status. 6 1 read-only P7 Pull Up Status. 7 1 read-only P8 Pull Up Status. 8 1 read-only P9 Pull Up Status. 9 1 read-only P10 Pull Up Status. 10 1 read-only P11 Pull Up Status. 11 1 read-only P12 Pull Up Status. 12 1 read-only P13 Pull Up Status. 13 1 read-only P14 Pull Up Status. 14 1 read-only P15 Pull Up Status. 15 1 read-only P16 Pull Up Status. 16 1 read-only P17 Pull Up Status. 17 1 read-only P18 Pull Up Status. 18 1 read-only P19 Pull Up Status. 19 1 read-only P20 Pull Up Status. 20 1 read-only P21 Pull Up Status. 21 1 read-only P22 Pull Up Status. 22 1 read-only P23 Pull Up Status. 23 1 read-only P24 Pull Up Status. 24 1 read-only P25 Pull Up Status. 25 1 read-only P26 Pull Up Status. 26 1 read-only P27 Pull Up Status. 27 1 read-only P28 Pull Up Status. 28 1 read-only P29 Pull Up Status. 29 1 read-only P30 Pull Up Status. 30 1 read-only P31 Pull Up Status. 31 1 read-only ASR Peripheral A Select Register 0x00000070 32 write-only P0 Peripheral A Select. 0 1 write-only P1 Peripheral A Select. 1 1 write-only P2 Peripheral A Select. 2 1 write-only P3 Peripheral A Select. 3 1 write-only P4 Peripheral A Select. 4 1 write-only P5 Peripheral A Select. 5 1 write-only P6 Peripheral A Select. 6 1 write-only P7 Peripheral A Select. 7 1 write-only P8 Peripheral A Select. 8 1 write-only P9 Peripheral A Select. 9 1 write-only P10 Peripheral A Select. 10 1 write-only P11 Peripheral A Select. 11 1 write-only P12 Peripheral A Select. 12 1 write-only P13 Peripheral A Select. 13 1 write-only P14 Peripheral A Select. 14 1 write-only P15 Peripheral A Select. 15 1 write-only P16 Peripheral A Select. 16 1 write-only P17 Peripheral A Select. 17 1 write-only P18 Peripheral A Select. 18 1 write-only P19 Peripheral A Select. 19 1 write-only P20 Peripheral A Select. 20 1 write-only P21 Peripheral A Select. 21 1 write-only P22 Peripheral A Select. 22 1 write-only P23 Peripheral A Select. 23 1 write-only P24 Peripheral A Select. 24 1 write-only P25 Peripheral A Select. 25 1 write-only P26 Peripheral A Select. 26 1 write-only P27 Peripheral A Select. 27 1 write-only P28 Peripheral A Select. 28 1 write-only P29 Peripheral A Select. 29 1 write-only P30 Peripheral A Select. 30 1 write-only P31 Peripheral A Select. 31 1 write-only BSR Peripheral B Select Register 0x00000074 32 write-only P0 Peripheral B Select. 0 1 write-only P1 Peripheral B Select. 1 1 write-only P2 Peripheral B Select. 2 1 write-only P3 Peripheral B Select. 3 1 write-only P4 Peripheral B Select. 4 1 write-only P5 Peripheral B Select. 5 1 write-only P6 Peripheral B Select. 6 1 write-only P7 Peripheral B Select. 7 1 write-only P8 Peripheral B Select. 8 1 write-only P9 Peripheral B Select. 9 1 write-only P10 Peripheral B Select. 10 1 write-only P11 Peripheral B Select. 11 1 write-only P12 Peripheral B Select. 12 1 write-only P13 Peripheral B Select. 13 1 write-only P14 Peripheral B Select. 14 1 write-only P15 Peripheral B Select. 15 1 write-only P16 Peripheral B Select. 16 1 write-only P17 Peripheral B Select. 17 1 write-only P18 Peripheral B Select. 18 1 write-only P19 Peripheral B Select. 19 1 write-only P20 Peripheral B Select. 20 1 write-only P21 Peripheral B Select. 21 1 write-only P22 Peripheral B Select. 22 1 write-only P23 Peripheral B Select. 23 1 write-only P24 Peripheral B Select. 24 1 write-only P25 Peripheral B Select. 25 1 write-only P26 Peripheral B Select. 26 1 write-only P27 Peripheral B Select. 27 1 write-only P28 Peripheral B Select. 28 1 write-only P29 Peripheral B Select. 29 1 write-only P30 Peripheral B Select. 30 1 write-only P31 Peripheral B Select. 31 1 write-only ABSR AB Status Register 0x00000078 32 read-only 0x00000000 P0 Peripheral A B Status. 0 1 read-only P1 Peripheral A B Status. 1 1 read-only P2 Peripheral A B Status. 2 1 read-only P3 Peripheral A B Status. 3 1 read-only P4 Peripheral A B Status. 4 1 read-only P5 Peripheral A B Status. 5 1 read-only P6 Peripheral A B Status. 6 1 read-only P7 Peripheral A B Status. 7 1 read-only P8 Peripheral A B Status. 8 1 read-only P9 Peripheral A B Status. 9 1 read-only P10 Peripheral A B Status. 10 1 read-only P11 Peripheral A B Status. 11 1 read-only P12 Peripheral A B Status. 12 1 read-only P13 Peripheral A B Status. 13 1 read-only P14 Peripheral A B Status. 14 1 read-only P15 Peripheral A B Status. 15 1 read-only P16 Peripheral A B Status. 16 1 read-only P17 Peripheral A B Status. 17 1 read-only P18 Peripheral A B Status. 18 1 read-only P19 Peripheral A B Status. 19 1 read-only P20 Peripheral A B Status. 20 1 read-only P21 Peripheral A B Status. 21 1 read-only P22 Peripheral A B Status. 22 1 read-only P23 Peripheral A B Status. 23 1 read-only P24 Peripheral A B Status. 24 1 read-only P25 Peripheral A B Status. 25 1 read-only P26 Peripheral A B Status. 26 1 read-only P27 Peripheral A B Status. 27 1 read-only P28 Peripheral A B Status. 28 1 read-only P29 Peripheral A B Status. 29 1 read-only P30 Peripheral A B Status. 30 1 read-only P31 Peripheral A B Status. 31 1 read-only OWER Output Write Enable 0x000000A0 32 write-only P0 Output Write Enable. 0 1 write-only P1 Output Write Enable. 1 1 write-only P2 Output Write Enable. 2 1 write-only P3 Output Write Enable. 3 1 write-only P4 Output Write Enable. 4 1 write-only P5 Output Write Enable. 5 1 write-only P6 Output Write Enable. 6 1 write-only P7 Output Write Enable. 7 1 write-only P8 Output Write Enable. 8 1 write-only P9 Output Write Enable. 9 1 write-only P10 Output Write Enable. 10 1 write-only P11 Output Write Enable. 11 1 write-only P12 Output Write Enable. 12 1 write-only P13 Output Write Enable. 13 1 write-only P14 Output Write Enable. 14 1 write-only P15 Output Write Enable. 15 1 write-only P16 Output Write Enable. 16 1 write-only P17 Output Write Enable. 17 1 write-only P18 Output Write Enable. 18 1 write-only P19 Output Write Enable. 19 1 write-only P20 Output Write Enable. 20 1 write-only P21 Output Write Enable. 21 1 write-only P22 Output Write Enable. 22 1 write-only P23 Output Write Enable. 23 1 write-only P24 Output Write Enable. 24 1 write-only P25 Output Write Enable. 25 1 write-only P26 Output Write Enable. 26 1 write-only P27 Output Write Enable. 27 1 write-only P28 Output Write Enable. 28 1 write-only P29 Output Write Enable. 29 1 write-only P30 Output Write Enable. 30 1 write-only P31 Output Write Enable. 31 1 write-only OWDR Output Write Disable 0x000000A4 32 write-only P0 Output Write Disable. 0 1 write-only P1 Output Write Disable. 1 1 write-only P2 Output Write Disable. 2 1 write-only P3 Output Write Disable. 3 1 write-only P4 Output Write Disable. 4 1 write-only P5 Output Write Disable. 5 1 write-only P6 Output Write Disable. 6 1 write-only P7 Output Write Disable. 7 1 write-only P8 Output Write Disable. 8 1 write-only P9 Output Write Disable. 9 1 write-only P10 Output Write Disable. 10 1 write-only P11 Output Write Disable. 11 1 write-only P12 Output Write Disable. 12 1 write-only P13 Output Write Disable. 13 1 write-only P14 Output Write Disable. 14 1 write-only P15 Output Write Disable. 15 1 write-only P16 Output Write Disable. 16 1 write-only P17 Output Write Disable. 17 1 write-only P18 Output Write Disable. 18 1 write-only P19 Output Write Disable. 19 1 write-only P20 Output Write Disable. 20 1 write-only P21 Output Write Disable. 21 1 write-only P22 Output Write Disable. 22 1 write-only P23 Output Write Disable. 23 1 write-only P24 Output Write Disable. 24 1 write-only P25 Output Write Disable. 25 1 write-only P26 Output Write Disable. 26 1 write-only P27 Output Write Disable. 27 1 write-only P28 Output Write Disable. 28 1 write-only P29 Output Write Disable. 29 1 write-only P30 Output Write Disable. 30 1 write-only P31 Output Write Disable. 31 1 write-only OWSR Output Write Status Register 0x000000A8 32 read-only 0x00000000 P0 Output Write Status. 0 1 read-only P1 Output Write Status. 1 1 read-only P2 Output Write Status. 2 1 read-only P3 Output Write Status. 3 1 read-only P4 Output Write Status. 4 1 read-only P5 Output Write Status. 5 1 read-only P6 Output Write Status. 6 1 read-only P7 Output Write Status. 7 1 read-only P8 Output Write Status. 8 1 read-only P9 Output Write Status. 9 1 read-only P10 Output Write Status. 10 1 read-only P11 Output Write Status. 11 1 read-only P12 Output Write Status. 12 1 read-only P13 Output Write Status. 13 1 read-only P14 Output Write Status. 14 1 read-only P15 Output Write Status. 15 1 read-only P16 Output Write Status. 16 1 read-only P17 Output Write Status. 17 1 read-only P18 Output Write Status. 18 1 read-only P19 Output Write Status. 19 1 read-only P20 Output Write Status. 20 1 read-only P21 Output Write Status. 21 1 read-only P22 Output Write Status. 22 1 read-only P23 Output Write Status. 23 1 read-only P24 Output Write Status. 24 1 read-only P25 Output Write Status. 25 1 read-only P26 Output Write Status. 26 1 read-only P27 Output Write Status. 27 1 read-only P28 Output Write Status. 28 1 read-only P29 Output Write Status. 29 1 read-only P30 Output Write Status. 30 1 read-only P31 Output Write Status. 31 1 read-only 4 4 0-3 DELAYR[%s] I/O Delay Register 0x000000C0 32 read-write Delay0 0 4 read-write Delay1 4 4 read-write Delay2 8 4 read-write Delay3 12 4 read-write Delay4 16 4 read-write Delay5 20 4 read-write Delay6 24 4 read-write Delay7 28 4 read-write WPMR Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write WPSR Write Protect Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protect Enable 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only PMC 6357A Power Management Controller 0xFFFFFC00 0 0x100 registers PMC_SCER System Clock Enable Register 0x00000000 32 write-only DDRCK DDR Clock Enable 2 1 write-only UHP USB Host OHCI Clocks Enable 6 1 write-only PCK0 Programmable Clock 0 Output Enable 8 1 write-only PCK1 Programmable Clock 1 Output Enable 9 1 write-only PMC_SCDR System Clock Disable Register 0x00000004 32 write-only PCK Processor Clock Disable 0 1 write-only DDRCK DDR Clock Disable 2 1 write-only UHP USB Host OHCI Clock Disable 6 1 write-only PCK0 Programmable Clock 0 Output Disable 8 1 write-only PCK1 Programmable Clock 1 Output Disable 9 1 write-only PMC_SCSR System Clock Status Register 0x00000008 32 read-only 0x00000001 PCK Processor Clock Status 0 1 read-only DDRCK DDR Clock Status 2 1 read-only UHP USB Host Port Clock Status 6 1 read-only PCK0 Programmable Clock 0 Output Status 8 1 read-only PCK1 Programmable Clock 1 Output Status 9 1 read-only PMC_PCER Peripheral Clock Enable Register 0x00000010 32 write-only PID2 Peripheral Clock 2 Enable 2 1 write-only PID3 Peripheral Clock 3 Enable 3 1 write-only PID4 Peripheral Clock 4 Enable 4 1 write-only PID5 Peripheral Clock 5 Enable 5 1 write-only PID6 Peripheral Clock 6 Enable 6 1 write-only PID7 Peripheral Clock 7 Enable 7 1 write-only PID8 Peripheral Clock 8 Enable 8 1 write-only PID9 Peripheral Clock 9 Enable 9 1 write-only PID10 Peripheral Clock 10 Enable 10 1 write-only PID11 Peripheral Clock 11 Enable 11 1 write-only PID12 Peripheral Clock 12 Enable 12 1 write-only PID13 Peripheral Clock 13 Enable 13 1 write-only PID14 Peripheral Clock 14 Enable 14 1 write-only PID15 Peripheral Clock 15 Enable 15 1 write-only PID16 Peripheral Clock 16 Enable 16 1 write-only PID17 Peripheral Clock 17 Enable 17 1 write-only PID18 Peripheral Clock 18 Enable 18 1 write-only PID19 Peripheral Clock 19 Enable 19 1 write-only PID20 Peripheral Clock 20 Enable 20 1 write-only PID21 Peripheral Clock 21 Enable 21 1 write-only PID22 Peripheral Clock 22 Enable 22 1 write-only PID23 Peripheral Clock 23 Enable 23 1 write-only PID24 Peripheral Clock 24 Enable 24 1 write-only PID25 Peripheral Clock 25 Enable 25 1 write-only PID26 Peripheral Clock 26 Enable 26 1 write-only PID27 Peripheral Clock 27 Enable 27 1 write-only PID28 Peripheral Clock 28 Enable 28 1 write-only PID29 Peripheral Clock 29 Enable 29 1 write-only PID30 Peripheral Clock 30 Enable 30 1 write-only PID31 Peripheral Clock 31 Enable 31 1 write-only PMC_PCDR Peripheral Clock Disable Register 0x00000014 32 write-only PID2 Peripheral Clock 2 Disable 2 1 write-only PID3 Peripheral Clock 3 Disable 3 1 write-only PID4 Peripheral Clock 4 Disable 4 1 write-only PID5 Peripheral Clock 5 Disable 5 1 write-only PID6 Peripheral Clock 6 Disable 6 1 write-only PID7 Peripheral Clock 7 Disable 7 1 write-only PID8 Peripheral Clock 8 Disable 8 1 write-only PID9 Peripheral Clock 9 Disable 9 1 write-only PID10 Peripheral Clock 10 Disable 10 1 write-only PID11 Peripheral Clock 11 Disable 11 1 write-only PID12 Peripheral Clock 12 Disable 12 1 write-only PID13 Peripheral Clock 13 Disable 13 1 write-only PID14 Peripheral Clock 14 Disable 14 1 write-only PID15 Peripheral Clock 15 Disable 15 1 write-only PID16 Peripheral Clock 16 Disable 16 1 write-only PID17 Peripheral Clock 17 Disable 17 1 write-only PID18 Peripheral Clock 18 Disable 18 1 write-only PID19 Peripheral Clock 19 Disable 19 1 write-only PID20 Peripheral Clock 20 Disable 20 1 write-only PID21 Peripheral Clock 21 Disable 21 1 write-only PID22 Peripheral Clock 22 Disable 22 1 write-only PID23 Peripheral Clock 23 Disable 23 1 write-only PID24 Peripheral Clock 24 Disable 24 1 write-only PID25 Peripheral Clock 25 Disable 25 1 write-only PID26 Peripheral Clock 26 Disable 26 1 write-only PID27 Peripheral Clock 27 Disable 27 1 write-only PID28 Peripheral Clock 28 Disable 28 1 write-only PID29 Peripheral Clock 29 Disable 29 1 write-only PID30 Peripheral Clock 30 Disable 30 1 write-only PID31 Peripheral Clock 31 Disable 31 1 write-only PMC_PCSR Peripheral Clock Status Register 0x00000018 32 read-only 0x00000000 PID2 Peripheral Clock 2 Status 2 1 read-only PID3 Peripheral Clock 3 Status 3 1 read-only PID4 Peripheral Clock 4 Status 4 1 read-only PID5 Peripheral Clock 5 Status 5 1 read-only PID6 Peripheral Clock 6 Status 6 1 read-only PID7 Peripheral Clock 7 Status 7 1 read-only PID8 Peripheral Clock 8 Status 8 1 read-only PID9 Peripheral Clock 9 Status 9 1 read-only PID10 Peripheral Clock 10 Status 10 1 read-only PID11 Peripheral Clock 11 Status 11 1 read-only PID12 Peripheral Clock 12 Status 12 1 read-only PID13 Peripheral Clock 13 Status 13 1 read-only PID14 Peripheral Clock 14 Status 14 1 read-only PID15 Peripheral Clock 15 Status 15 1 read-only PID16 Peripheral Clock 16 Status 16 1 read-only PID17 Peripheral Clock 17 Status 17 1 read-only PID18 Peripheral Clock 18 Status 18 1 read-only PID19 Peripheral Clock 19 Status 19 1 read-only PID20 Peripheral Clock 20 Status 20 1 read-only PID21 Peripheral Clock 21 Status 21 1 read-only PID22 Peripheral Clock 22 Status 22 1 read-only PID23 Peripheral Clock 23 Status 23 1 read-only PID24 Peripheral Clock 24 Status 24 1 read-only PID25 Peripheral Clock 25 Status 25 1 read-only PID26 Peripheral Clock 26 Status 26 1 read-only PID27 Peripheral Clock 27 Status 27 1 read-only PID28 Peripheral Clock 28 Status 28 1 read-only PID29 Peripheral Clock 29 Status 29 1 read-only PID30 Peripheral Clock 30 Status 30 1 read-only PID31 Peripheral Clock 31 Status 31 1 read-only CKGR_UCKR UTMI Clock Register 0x0000001C 32 read-write 0x10200800 UPLLEN UTMI PLL Enable 16 1 read-write PLLCOUNT UTMI PLL Start-up Time 20 4 read-write BIASEN UTMI BIAS Enable 24 1 read-write BIASCOUNT UTMI BIAS Start-up Time 28 4 read-write CKGR_MOR Main Oscillator Register 0x00000020 32 read-write 0x00000000 MOSCEN Main Oscillator Enable 0 1 read-write OSCBYPASS Oscillator Bypass 1 1 read-write OSCOUNT Main Oscillator Start-up Time 8 8 read-write CKGR_MCFR Main Clock Frequency Register 0x00000024 32 read-only 0x00000000 MAINF Main Clock Frequency 0 16 read-only MAINRDY Main Clock Ready 16 1 read-only CKGR_PLLAR PLLA Register 0x00000028 32 read-write 0x00003F00 DIVA Divider A 0 8 read-write PLLACOUNT PLLA Counter 8 6 read-write OUTA PLLA Clock Frequency Range 14 2 read-write MULA PLLA Multiplier 16 8 read-write STUCKTO1 29 1 read-write PMC_MCKR Master Clock Register 0x00000030 32 read-write 0x00000000 CSS Master/Processor Clock Source Selection 0 2 read-write PRES Master/Processor Clock Prescaler 2 3 read-write MDIV Master Clock Division 8 2 read-write PLLADIV2 PLLA divisor by 2 12 1 read-write PMC_USB USB Clock Register 0x00000038 32 read-write 0x00000000 USBS USB OHCI Input clock selection 0 1 read-write USBDIV Divider for USB OHCI Clock. 8 4 read-write 2 4 0-1 PMC_PCK[%s] Programmable Clock 0 Register 0x00000040 32 read-write CSS Master Clock Selection 0 2 read-write PRES Programmable Clock Prescaler 2 3 read-write SLCKMCK Slow Clock or Master Clock Selection 8 1 read-write PMC_IER Interrupt Enable Register 0x00000060 32 write-only MOSCS Main Oscillator Status Interrupt Enable 0 1 write-only LOCKA PLL Lock Interrupt Enable 1 1 write-only MCKRDY Master Clock Ready Interrupt Enable 3 1 write-only LOCKU UTMI PLL Lock Interrupt Enable 6 1 write-only PCKRDY0 Programmable Clock Ready 0 Interrupt Enable 8 1 write-only PCKRDY1 Programmable Clock Ready 1 Interrupt Enable 9 1 write-only PMC_IDR Interrupt Disable Register 0x00000064 32 write-only MOSCS Main Oscillator Status Interrupt Disable 0 1 write-only LOCKA PLLA Lock Interrupt Disable 1 1 write-only MCKRDY Master Clock Ready Interrupt Disable 3 1 write-only LOCKU UTMI PLL Lock Interrupt Disable 6 1 write-only PCKRDY0 Programmable Clock Ready 0 Interrupt Disable 8 1 write-only PCKRDY1 Programmable Clock Ready 1 Interrupt Disable 9 1 write-only PMC_SR Status Register 0x00000068 32 read-only 0x00000008 MOSCS MOSCS Flag Status 0 1 read-only LOCKA PLLA Lock Status 1 1 read-only MCKRDY Master Clock Status 3 1 read-only LOCKU UPLL Lock Status 6 1 read-only PCKRDY0 Programmable Clock Ready Status 8 1 read-only PCKRDY1 Programmable Clock Ready Status 9 1 read-only PMC_IMR Interrupt Mask Register 0x0000006C 32 read-only 0x00000000 MOSCS Main Oscillator Status Interrupt Mask 0 1 read-only LOCKA PLLA Lock Interrupt Mask 1 1 read-only MCKRDY Master Clock Ready Interrupt Mask 3 1 read-only LOCKU UTMI PLL Lock Interrupt Mask 6 1 read-only PCKRDY0 Programmable Clock Ready 0 Interrupt Mask 8 1 read-only PCKRDY1 Programmable Clock Ready 1 Interrupt Mask 9 1 read-only RSTC 6098I Reset Controller SYSC RSTC_ 0xFFFFFD00 0 0x200 registers CR Control Register 0x00000000 32 write-only PROCRST Processor Reset 0 1 write-only PERRST Peripheral Reset 2 1 write-only EXTRST External Reset 3 1 write-only KEY Password 24 8 write-only SR Status Register 0x00000004 32 read-only 0x00000001 URSTS User Reset Status 0 1 read-only RSTTYP Reset Type 8 3 read-only NRSTL NRST Pin Level 16 1 read-only SRCMP Software Reset Command in Progress 17 1 read-only MR Mode Register 0x00000008 32 read-write URSTEN User Reset Enable 0 1 read-write URSTIEN User Reset Interrupt Enable 4 1 read-write ERSTL External Reset Length 8 4 read-write KEY Password 24 8 read-write SHDWC 6122J Shutdown Controller SYSC SHDWC_ 0xFFFFFD10 0 0x200 registers CR Shutdown Control Register 0x00000000 32 write-only SHDW Shutdown Command 0 1 write-only KEY Password 24 8 write-only MR Shutdown Mode Register 0x00000004 32 read-write 0x00000003 WKMODE0 Wake-up Mode 0 0 2 read-write CPTWK0 Counter on Wake-up 0 4 4 read-write RTTWKEN Real-time Timer Wake-up Enable 16 1 read-write RTCWKEN Real-time Clock Wake-up Enable 17 1 read-write SR Shutdown Status Register 0x00000008 32 read-only 0x00000000 WAKEUP0 Wake-up 0 Status 0 1 read-only RTTWK Real-time Timer Wake-up 16 1 read-only RTCWK Real-time Clock Wake-up 17 1 read-only RTT 6081D Real-time Timer SYSC RTT_ 0xFFFFFD20 0 0x200 registers MR Mode Register 0x00000000 32 read-write 0x00008000 RTPRES Real-time Timer Prescaler Value 0 16 read-write ALMIEN Alarm Interrupt Enable 16 1 read-write RTTINCIEN Real-time Timer Increment Interrupt Enable 17 1 read-write RTTRST Real-time Timer Restart 18 1 read-write AR Alarm Register 0x00000004 32 read-write 0xFFFFFFFF ALMV Alarm Value 0 32 read-write VR Value Register 0x00000008 32 read-only 0x00000000 CRTV Current Real-time Value 0 32 read-only SR Status Register 0x0000000C 32 read-only 0x00000000 ALMS Real-time Alarm Status 0 1 read-only RTTINC Real-time Timer Increment 1 1 read-only PIT 6079B Periodic Interval Timer SYSC PIT_ 0xFFFFFD30 0 0x200 registers MR Mode Register 0x00000000 32 read-write 0x000FFFFF PIV Periodic Interval Value 0 20 read-write PITEN Period Interval Timer Enabled 24 1 read-write PITIEN Periodic Interval Timer Interrupt Enable 25 1 read-write SR Status Register 0x00000004 32 read-only 0x00000000 PITS Periodic Interval Timer Status 0 1 read-only PIVR Periodic Interval Value Register 0x00000008 32 read-only 0x00000000 CPIV Current Periodic Interval Value 0 20 read-only PICNT Periodic Interval Counter 20 12 read-only PIIR Periodic Interval Image Register 0x0000000C 32 read-only 0x00000000 CPIV Current Periodic Interval Value 0 20 read-only PICNT Periodic Interval Counter 20 12 read-only WDT 6080B Watchdog Timer SYSC WDT_ 0xFFFFFD40 0 0x200 registers CR Control Register 0x00000000 32 write-only WDRSTT Watchdog Restart 0 1 write-only KEY Password 24 8 write-only MR Mode Register 0x00000004 32 read-write 0x3FFF2FFF WDV Watchdog Counter Value 0 12 read-write WDFIEN Watchdog Fault Interrupt Enable 12 1 read-write WDRSTEN Watchdog Reset Enable 13 1 read-write WDRPROC Watchdog Reset Processor 14 1 read-write WDDIS Watchdog Disable 15 1 read-write WDD Watchdog Delta Value 16 12 read-write WDDBGHLT Watchdog Debug Halt 28 1 read-write WDIDLEHLT Watchdog Idle Halt 29 1 read-write SR Status Register 0x00000008 32 read-only 0x00000000 WDUNF Watchdog Underflow 0 1 read-only WDERR Watchdog Error 1 1 read-only GPBR 6378A General Purpose Backup Register SYSC GPBR_ 0xFFFFFD60 0 0x200 registers GPBR0 General Purpose Backup Register 0 0x00000000 32 read-write GPBR_VALUE0 Value of GPBR x 0 32 read-write GPBR1 General Purpose Backup Register 1 0x00000004 32 read-write GPBR_VALUE1 Value of GPBR x 0 32 read-write GPBR2 General Purpose Backup Register 2 0x00000008 32 read-write GPBR_VALUE2 Value of GPBR x 0 32 read-write GPBR3 General Purpose Backup Register 3 0x0000000C 32 read-write GPBR_VALUE3 Value of GPBR x 0 32 read-write RTC 6056H Real-time Clock RTC_ 0xFFFFFDB0 0 0x30 registers CR Control Register 0x00000000 32 read-write 0x00000000 UPDTIM Update Request Time Register 0 1 read-write UPDCAL Update Request Calendar Register 1 1 read-write TIMEVSEL Time Event Selection 8 2 read-write MINUTE Minute change 0x0 HOUR Hour change 0x1 MIDNIGHT Every day at midnight 0x2 NOON Every day at noon 0x3 CALEVSEL Calendar Event Selection 16 2 read-write WEEK Week change (every Monday at time 00:00:00) 0x0 MONTH Month change (every 01 of each month at time 00:00:00) 0x1 YEAR Year change (every January 1 at time 00:00:00) 0x2 MR Mode Register 0x00000004 32 read-write 0x00000000 HRMOD 12-/24-hour Mode 0 1 read-write TIMR Time Register 0x00000008 32 read-write 0x00000000 SEC Current Second 0 7 read-write MIN Current Minute 8 7 read-write HOUR Current Hour 16 6 read-write AMPM Ante Meridiem Post Meridiem Indicator 22 1 read-write CALR Calendar Register 0x0000000C 32 read-write 0x01210720 CENT Current Century 0 7 read-write YEAR Current Year 8 8 read-write MONTH Current Month 16 5 read-write DAY Current Day in Current Week 21 3 read-write DATE Current Day in Current Month 24 6 read-write TIMALR Time Alarm Register 0x00000010 32 read-write 0x00000000 SEC Second Alarm 0 7 read-write SECEN Second Alarm Enable 7 1 read-write MIN Minute Alarm 8 7 read-write MINEN Minute Alarm Enable 15 1 read-write HOUR Hour Alarm 16 6 read-write AMPM AM/PM Indicator 22 1 read-write HOUREN Hour Alarm Enable 23 1 read-write CALALR Calendar Alarm Register 0x00000014 32 read-write 0x01010000 MONTH Month Alarm 16 5 read-write MTHEN Month Alarm Enable 23 1 read-write DATE Date Alarm 24 6 read-write DATEEN Date Alarm Enable 31 1 read-write SR Status Register 0x00000018 32 read-only 0x00000000 ACKUPD Acknowledge for Update 0 1 read-only ALARM Alarm Flag 1 1 read-only SEC Second Event 2 1 read-only TIMEV Time Event 3 1 read-only CALEV Calendar Event 4 1 read-only SCCR Status Clear Command Register 0x0000001C 32 write-only ACKCLR Acknowledge Clear 0 1 write-only ALRCLR Alarm Clear 1 1 write-only SECCLR Second Clear 2 1 write-only TIMCLR Time Clear 3 1 write-only CALCLR Calendar Clear 4 1 write-only IER Interrupt Enable Register 0x00000020 32 write-only ACKEN Acknowledge Update Interrupt Enable 0 1 write-only ALREN Alarm Interrupt Enable 1 1 write-only SECEN Second Event Interrupt Enable 2 1 write-only TIMEN Time Event Interrupt Enable 3 1 write-only CALEN Calendar Event Interrupt Enable 4 1 write-only IDR Interrupt Disable Register 0x00000024 32 write-only ACKDIS Acknowledge Update Interrupt Disable 0 1 write-only ALRDIS Alarm Interrupt Disable 1 1 write-only SECDIS Second Event Interrupt Disable 2 1 write-only TIMDIS Time Event Interrupt Disable 3 1 write-only CALDIS Calendar Event Interrupt Disable 4 1 write-only IMR Interrupt Mask Register 0x00000028 32 read-only 0x00000000 ACK Acknowledge Update Interrupt Mask 0 1 read-only ALR Alarm Interrupt Mask 1 1 read-only SEC Second Event Interrupt Mask 2 1 read-only TIM Time Event Interrupt Mask 3 1 read-only CAL Calendar Event Interrupt Mask 4 1 read-only VER Valid Entry Register 0x0000002C 32 read-only 0x00000000 NVTIM Non-valid Time 0 1 read-only NVCAL Non-valid Calendar 1 1 read-only NVTIMALR Non-valid Time Alarm 2 1 read-only NVCALALR Non-valid Calendar Alarm 3 1 read-only