Keil ArteryTek AT32F421xx_v2 AT32F421 1.0 ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 200MHz, etc. ARM Limited (ARM) is supplying this software for use with Cortex-M\n processor based microcontroller, but can be equally used for other\n suitable processor architectures. This file can be freely distributed.\n Modifications to this file shall be clearly marked.\n \n THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. CM4 r0p1 little false true 4 false 8 32 32 read-write 0x00000000 0xFFFFFFFF PWC Power control PWC 0x40007000 0x0 0x400 registers CTRL CTRL Power control register (PWC_CTRL) 0x0 0x20 read-write 0x00000000 VRSEL Voltage regulator state select when deepsleep mode 0 1 LPSEL Low power mode select when Cortex-M4F sleepdeep 1 1 CLSWEF Clear SWEF flag 2 1 CLSEF Clear SEF flag 3 1 PVMEN Power voltage monitoring enable 4 1 PVMSEL Power voltage monitoring boundary select 5 3 BPWEN Battery powered domain write enable 8 1 CTRLSTS CTRLSTS Power control and status register (PWC_CTRLSTS) 0x4 0x20 0x00000000 SWEF Standby wake-up event flag 0 1 read-only SEF Standby mode entry flag 1 1 read-only PVMOF Power voltage monitoring output flag 2 1 read-only SWPEN1 Standby wake-up pin1 enable 8 1 read-write SWPEN2 Standby wake-up pin2 enable 9 1 read-write SWPEN6 Standby wake-up pin2 enable 13 1 read-write SWPEN7 Standby wake-up pin2 enable 14 1 read-write CTRL2 CTRL2 Power control and status register2 (PWC_CTRL2) 0x20 0x20 0x00000000 VREXLPEN Voltage regulator extra low power mode enable 5 1 read-write CRM Clock and reset management CRM 0x40021000 0x0 0x400 registers CRM CRM global interrupt 4 CTRL CTRL Clock control register 0x0 0x20 0x00000083 HICKEN High speed internal clock enable 0 1 read-write HICKSTBL High speed internal clock ready flag 1 1 read-only HICKTRIM High speed internal clock trimming 2 6 read-write HICKCAL High speed internal clock calibration 8 8 read-only HEXTEN High speed exernal crystal enable 16 1 read-write HEXTSTBL High speed exernal crystal ready flag 17 1 read-only HEXTBYPS High speed exernal crystal bypass 18 1 read-write CFDEN Clock failure detection enable 19 1 read-write PLLEN PLL enable 24 1 read-write PLLSTBL PLL clock ready flag 25 1 read-only CFG CFG Clock configuration register (CRM_CFG) 0x4 0x20 0x00000000 SCLKSEL System clock select 0 2 read-write SCLKSTS System Clock select Status 2 2 read-only AHBDIV AHB division 4 4 read-write APB1DIV APB1 division 8 3 read-write APB2DIV APB2 division 11 3 read-write ADCDIV1_0 ADC division bit1 and bit0 14 2 read-write PLLRCS PLL reference clock select 16 1 read-write PLLHEXTDIV HEXT division selection for PLL entry clock 17 1 read-write PLLMULT3_0 PLL Multiplication Factor bit3 to bit0 18 4 read-write CLKOUT_SEL Clock output selection bit2 to bit0 24 3 read-write ADCDIV2 ADC division bit2 28 1 read-write PLLMULT5_4 PLL Multiplication Factor bit5 and bit4 29 2 read-write CLKINT CLKINT Clock interrupt register (CRM_CLKINT) 0x8 0x20 0x00000000 LICKSTBLF LICK ready interrupt flag 0 1 read-only LEXTSTBLF LEXT ready interrupt flag 1 1 read-only HICKSTBLF HICK ready interrupt flag 2 1 read-only HEXTSTBLF HEXT ready interrupt flag 3 1 read-only PLLSTBLF PLL ready interrupt flag 4 1 read-only CFDF Clock failure detection interrupt flag 7 1 read-only LICKSTBLIEN LICK ready interrupt enable 8 1 read-write LEXTSTBLIEN LEXT ready interrupt enable 9 1 read-write HICKSTBLIEN HICK ready interrupt enable 10 1 read-write HEXTSTBLIEN HEXT ready interrupt enable 11 1 read-write PLLSTBLIEN PLL ready interrupt enable 12 1 read-write LICKSTBLFC LICK ready interrupt clear 16 1 write-only LEXTSTBLFC LEXT ready interrupt clear 17 1 write-only HICKSTBLFC HICK ready interrupt clear 18 1 write-only HEXTSTBLFC HEXT ready interrupt clear 19 1 write-only PLLSTBLFC PLL ready interrupt clear 20 1 write-only CFDFC Clock failure detection interrupt clear 23 1 write-only APB2RST APB2RST APB2 peripheral reset register (CRM_APB2RST) 0xC 0x20 read-write 0x000000000 SCFGCMPRST System config and comparator reset 0 1 EXINTRST External interrupt reset 1 1 ADCRST ADC reset 9 1 TMR1RST TMR1 reset 11 1 SPI1RST SPI1 reset 12 1 USART1RST USART1 reset 14 1 TMR15RST Timer15 reset 16 1 TMR16RST Timer16 reset 17 1 TMR17RST Timer17 reset 18 1 APB1RST APB1RST APB1 peripheral reset register (CRM_APB1RST) 0x10 0x20 read-write 0x00000000 TMR3RST Timer 3 reset 1 1 TMR6RST Timer 6 reset 4 1 TMR14RST Timer 14 reset 8 1 WWDTRST Window watchdog timer reset 11 1 SPI2RST SPI2 reset 14 1 USART2RST USART 2 reset 17 1 I2C1RST I2C1 reset 21 1 I2C2RST I2C2 reset 22 1 PWCRST Power controller reset 28 1 AHBEN AHBEN AHB Peripheral Clock enable register (CRM_AHBEN) 0x14 0x20 read-write 0x00000014 DMAEN DMA clock enable 0 1 SRAMEN SRAM interface clock enable 2 1 FLASHEN FLASH clock enable 4 1 CRCEN CRC clock enable 6 1 GPIOAEN I/O port A clock enable 17 1 GPIOBEN I/O port B clock enable 18 1 GPIOCEN I/O port C clock enable 19 1 GPIOFEN I/O port F clock enable 22 1 APB2EN APB2EN APB2 peripheral clock enable register (CRM_APB2EN) 0x18 0x20 read-write 0x00000000 SCFGCMPEN Syscfg and comparator clock enable 0 1 ADCEN ADC clock enable 9 1 TMR1EN Timer1 clock enable 11 1 SPI1EN SPI1 clock enable 12 1 USART1EN USART1 clock enable 14 1 TMR15EN Timer15 clock enable 16 1 TMR16EN Timer16 clock enable 17 1 TMR17EN Timer17 clock enable 18 1 APB1EN APB1EN APB1 peripheral clock enable register (CRM_APB1EN) 0x1C 0x20 read-write 0x00000000 TMR3EN Timer3 clock enable 1 1 TMR6EN Timer6 clock enable 4 1 TMR14EN Timer14 clock enable 8 1 WWDTEN Window watchdog timer clock enable 11 1 SPI2EN SPI2 clock enable 14 1 USART2EN USART2 clock enable 17 1 I2C1EN I2C1 clock enable 21 1 I2C2EN I2C2 clock enable 22 1 PWCEN Power clock enable 28 1 BPDC BPDC Battery powered domain control register (CRM_BPDC) 0x20 0x20 0x00000000 LEXTEN Low speed external crystal enable 0 1 read-write LEXTSTBL Low speed external crystal ready 1 1 read-only LEXTBYPS Low speed external crystal bypass 2 1 read-write ERTCSEL ERTC clock selection 8 2 read-write ERTCEN ERTC clock enable 15 1 read-write BPDRST Battery powered domain software reset 16 1 read-write CTRLSTS CTRLSTS Control/status register (CRM_CTRLSTS) 0x24 0x20 0x0C000000 LICKEN Low speed internal clock enable 0 1 read-write LICKSTBL Low speed internal clock ready 1 1 read-only RSTFC Reset flag clear 24 1 read-write NRSTF PIN reset flag 26 1 read-write PORRSTF POR/LVR reset flag 27 1 read-write SWRSTF Software reset flag 28 1 read-write WDTRSTF Watchdog timer reset flag 29 1 read-write WWDTRSTF Window watchdog timer reset flag 30 1 read-write LPRSTF Low-power reset flag 31 1 read-write AHBRST AHBRST AHB reset register 0x28 0x20 0x00000000 GPIOARST IO port A reset 17 1 GPIOBRST IO port B reset 18 1 GPIOCRST IO port C reset 19 1 GPIOFRST IO port F reset 22 1 PLL PLL PLL configuration register (CRM_PLL) 0x2C 0x20 0x00001F10 PLL_FR PLL_FR 0 3 read-write PLL_MS PLL_MS 4 4 read-write PLL_NS PLL_NS 8 9 read-write PLL_FREF PLL entry clock reference frequency 24 3 read-write PLLCFGEN PLL config enable 31 1 read-write MISC1 MISC1 Miscellaneous register1 0x30 0x20 0x00000000 HICKCAL_KEY HICKCAL write key value 0 8 read-write CLKOUT_SEL3 Clock output bit3 16 1 read-write HICKDIV HICK 6 divider selection 25 1 read-write CLKOUTDIV Clock output division 28 4 read-write MISC2 MISC2 Miscellaneous register2 0x54 0x20 0x0000000D AUTO_STEP_EN AUTO_STEP_EN 4 2 read-write HICK_TO_SCLK HICK to system clock 9 1 read-write GPIOA General purpose I/Os GPIO 0x48000000 0x0 0x400 registers CFGR CFGR GPIO configuration register 0x0 0x20 read-write 0x00000000 IOMC15 GPIOx pin 15 mode configurate 30 2 IOMC14 GPIOx pin 14 mode configurate 28 2 IOMC13 GPIOx pin 13 mode configurate 26 2 IOMC12 GPIOx pin 12 mode configurate 24 2 IOMC11 GPIOx pin 11 mode configurate 22 2 IOMC10 GPIOx pin 10 mode configurate 20 2 IOMC9 GPIOx pin 9 mode configurate 18 2 IOMC8 GPIOx pin 8 mode configurate 16 2 IOMC7 GPIOx pin 7 mode configurate 14 2 IOMC6 GPIOx pin 6 mode configurate 12 2 IOMC5 GPIOx pin 5 mode configurate 10 2 IOMC4 GPIOx pin 4 mode configurate 8 2 IOMC3 GPIOx pin 3 mode configurate 6 2 IOMC2 GPIOx pin 2 mode configurate 4 2 IOMC1 GPIOx pin 1 mode configurate 2 2 IOMC0 GPIOx pin 0 mode configurate 0 2 OMODE OMODE GPIO output mode register 0x4 0x20 read-write 0x00000000 OM15 GPIOx pin 15 outpu mode configurate 15 1 OM14 GPIOx pin 14 outpu mode configurate 14 1 OM13 GPIOx pin 13 outpu mode configurate 13 1 OM12 GPIOx pin 12 outpu mode configurate 12 1 OM11 GPIOx pin 11 outpu mode configurate 11 1 OM10 GPIOx pin 10 outpu mode configurate 10 1 OM9 GPIOx pin 9 outpu mode configurate 9 1 OM8 GPIOx pin 8 outpu mode configurate 8 1 OM7 GPIOx pin 7 outpu mode configurate 7 1 OM6 GPIOx pin 6 outpu mode configurate 6 1 OM5 GPIOx pin 5 outpu mode configurate 5 1 OM4 GPIOx pin 4 outpu mode configurate 4 1 OM3 GPIOx pin 3 outpu mode configurate 3 1 OM2 GPIOx pin 2 outpu mode configurate 2 1 OM1 GPIOx pin 1 outpu mode configurate 1 1 OM0 GPIOx pin 0 outpu mode configurate 0 1 ODRVR ODRVR GPIO drive capability register 0x8 0x20 read-write 0x00000000 ODRV15 GPIOx pin 15 output drive capability 30 2 ODRV14 GPIOx pin 14 output drive capability 28 2 ODRV13 GPIOx pin 13 output drive capability 26 2 ODRV12 GPIOx pin 12 output drive capability 24 2 ODRV11 GPIOx pin 11 output drive capability 22 2 ODRV10 GPIOx pin 10 output drive capability 20 2 ODRV9 GPIOx pin 9 output drive capability 18 2 ODRV8 GPIOx pin 8 output drive capability 16 2 ODRV7 GPIOx pin 7 output drive capability 14 2 ODRV6 GPIOx pin 6 output drive capability 12 2 ODRV5 GPIOx pin 5 output drive capability 10 2 ODRV4 GPIOx pin 4 output drive capability 8 2 ODRV3 GPIOx pin 3 output drive capability 6 2 ODRV2 GPIOx pin 2 output drive capability 4 2 ODRV1 GPIOx pin 1 output drive capability 2 2 ODRV0 GPIOx pin 0 output drive capability 0 2 PULL PULL GPIO pull-up/pull-down register 0xC 0x20 read-write 0x00000000 PULL15 GPIOx pin 15 pull configuration 30 2 PULL14 GPIOx pin 14 pull configuration 28 2 PULL13 GPIOx pin 13 pull configuration 26 2 PULL12 GPIOx pin 12 pull configuration 24 2 PULL11 GPIOx pin 11 pull configuration 22 2 PULL10 GPIOx pin 10 pull configuration 20 2 PULL9 GPIOx pin 9 pull configuration 18 2 PULL8 GPIOx pin 8 pull configuration 16 2 PULL7 GPIOx pin 7 pull configuration 14 2 PULL6 GPIOx pin 6 pull configuration 12 2 PULL5 GPIOx pin 5 pull configuration 10 2 PULL4 GPIOx pin 4 pull configuration 8 2 PULL3 GPIOx pin 3 pull configuration 6 2 PULL2 GPIOx pin 2 pull configuration 4 2 PULL1 GPIOx pin 1 pull configuration 2 2 PULL0 GPIOx pin 0 pull configuration 0 2 IDT IDT GPIO input data register 0x10 0x20 read-only 0x00000000 IDT0 Port input data 0 1 IDT1 Port input data 1 1 IDT2 Port input data 2 1 IDT3 Port input data 3 1 IDT4 Port input data 4 1 IDT5 Port input data 5 1 IDT6 Port input data 6 1 IDT7 Port input data 7 1 IDT8 Port input data 8 1 IDT9 Port input data 9 1 IDT10 Port input data 10 1 IDT11 Port input data 11 1 IDT12 Port input data 12 1 IDT13 Port input data 13 1 IDT14 Port input data 14 1 IDT15 Port input data 15 1 ODT ODT GPIO output data register 0x14 0x20 read-write 0x00000000 ODT0 Port output data 0 1 ODT1 Port output data 1 1 ODT2 Port output data 2 1 ODT3 Port output data 3 1 ODT4 Port output data 4 1 ODT5 Port output data 5 1 ODT6 Port output data 6 1 ODT7 Port output data 7 1 ODT8 Port output data 8 1 ODT9 Port output data 9 1 ODT10 Port output data 10 1 ODT11 Port output data 11 1 ODT12 Port output data 12 1 ODT13 Port output data 13 1 ODT14 Port output data 14 1 ODT15 Port output data 15 1 SCR SCR Port bit set/clear register 0x18 0x20 write-only 0x00000000 IOSB0 Set bit 0 0 1 IOSB1 Set bit 1 1 1 IOSB2 Set bit 1 2 1 IOSB3 Set bit 3 3 1 IOSB4 Set bit 4 4 1 IOSB5 Set bit 5 5 1 IOSB6 Set bit 6 6 1 IOSB7 Set bit 7 7 1 IOSB8 Set bit 8 8 1 IOSB9 Set bit 9 9 1 IOSB10 Set bit 10 10 1 IOSB11 Set bit 11 11 1 IOSB12 Set bit 12 12 1 IOSB13 Set bit 13 13 1 IOSB14 Set bit 14 14 1 IOSB15 Set bit 15 15 1 IOCB0 Clear bit 0 16 1 IOCB1 Clear bit 1 17 1 IOCB2 Clear bit 2 18 1 IOCB3 Clear bit 3 19 1 IOCB4 Clear bit 4 20 1 IOCB5 Clear bit 5 21 1 IOCB6 Clear bit 6 22 1 IOCB7 Clear bit 7 23 1 IOCB8 Clear bit 8 24 1 IOCB9 Clear bit 9 25 1 IOCB10 Clear bit 10 26 1 IOCB11 Clear bit 11 27 1 IOCB12 Clear bit 12 28 1 IOCB13 Clear bit 13 29 1 IOCB14 Clear bit 14 30 1 IOCB15 Clear bit 15 31 1 WPR WPR Port write protect register 0x1C 0x20 read-write 0x00000000 WPEN0 Write protect enable 0 0 1 WPEN1 Write protect enable 1 1 1 WPEN2 Write protect enable 2 2 1 WPEN3 Write protect enable 3 3 1 WPEN4 Write protect enable 4 4 1 WPEN5 Write protect enable 5 5 1 WPEN6 Write protect enable 6 6 1 WPEN7 Write protect enable 7 7 1 WPEN8 Write protect enable 8 8 1 WPEN9 Write protect enable 9 9 1 WPEN10 Write protect enable 10 10 1 WPEN11 Write protect enable 11 11 1 WPEN12 Write protect enable 12 12 1 WPEN13 Write protect enable 13 13 1 WPEN14 Write protect enable 14 14 1 WPEN15 Write protect enable 15 15 1 WPSEQ Write protect sequence 16 1 MUXL MUXL GPIO muxing function low register 0x20 0x20 read-write 0x00000000 MUXL7 GPIOx pin 7 muxing 28 4 MUXL6 GPIOx pin 6 muxing 24 4 MUXL5 GPIOx pin 5 muxing 20 4 MUXL4 GPIOx pin 4 muxing 16 4 MUXL3 GPIOx pin 3 muxing 12 4 MUXL2 GPIOx pin 2 muxing 8 4 MUXL1 GPIOx pin 1 muxing 4 4 MUXL0 GPIOx pin 0 muxing 0 4 MUXH MUXH GPIO muxing function high register 0x24 0x20 read-write 0x00000000 MUXH15 GPIOx pin 15 muxing 28 4 MUXH14 GPIOx pin 14 muxing 24 4 MUXH13 GPIOx pin 13 muxing 20 4 MUXH12 GPIOx pin 12 muxing 16 4 MUXH11 GPIOx pin 11 muxing 12 4 MUXH10 GPIOx pin 10 muxing 8 4 MUXH9 GPIOx pin 9 muxing 4 4 MUXH8 GPIOx pin 8 muxing 0 4 CLR CLR GPIO bit reset register 0x28 0x20 write-only 0x00000000 IOCB0 Clear bit 0 0 1 IOCB1 Clear bit 1 1 1 IOCB2 Clear bit 1 2 1 IOCB3 Clear bit 3 3 1 IOCB4 Clear bit 4 4 1 IOCB5 Clear bit 5 5 1 IOCB6 Clear bit 6 6 1 IOCB7 Clear bit 7 7 1 IOCB8 Clear bit 8 8 1 IOCB9 Clear bit 9 9 1 IOCB10 Clear bit 10 10 1 IOCB11 Clear bit 11 11 1 IOCB12 Clear bit 12 12 1 IOCB13 Clear bit 13 13 1 IOCB14 Clear bit 14 14 1 IOCB15 Clear bit 15 15 1 HDRV HDRV Huge current driver 0x3C 0x20 read-write 0x00000000 HDRV0 Port x driver bit y 0 1 HDRV1 Port x driver bit y 1 1 HDRV2 Port x driver bit y 2 1 HDRV3 Port x driver bit y 3 1 HDRV4 Port x driver bit y 4 1 HDRV5 Port x driver bit y 5 1 HDRV6 Port x driver bit y 6 1 HDRV7 Port x driver bit y 7 1 HDRV8 Port x driver bit y 8 1 HDRV9 Port x driver bit y 9 1 HDRV10 Port x driver bit y 10 1 HDRV11 Port x driver bit y 11 1 HDRV12 Port x driver bit y 12 1 HDRV13 Port x driver bit y 13 1 HDRV14 Port x driver bit y 14 1 HDRV15 Port x driver bit y 15 1 GPIOB 0x48000400 GPIOC 0x48000800 GPIOF 0x48001400 EXINT EXINT EXINT 0x40010400 0x0 0x400 registers PVM PVM interrupt connect to EXTI line16 1 ERTC ERTC interrupt connect to EXTI line17_19 2 EXTINT1_0 EXINT Line1_0 interrupt 5 EXTINT3_2 EXINT Line3_2 interrupt 6 EXTINT15_4 EXINT Line15_4 interrupt 7 INTEN INTEN Interrupt enable register (EXTINT_INTEN) 0x0 0x20 read-write 0x00000000 INTEN0 Interrupt enable or disable on line 0 0 1 INTEN1 Interrupt enable or disable on line 1 1 1 INTEN2 Interrupt enable or disable on line 2 2 1 INTEN3 Interrupt enable or disable on line 3 3 1 INTEN4 Interrupt enable or disable on line 4 4 1 INTEN5 Interrupt enable or disable on line 5 5 1 INTEN6 Interrupt enable or disable on line 6 6 1 INTEN7 Interrupt enable or disable on line 7 7 1 INTEN8 Interrupt enable or disable on line 8 8 1 INTEN9 Interrupt enable or disable on line 9 9 1 INTEN10 Interrupt enable or disable on line 10 10 1 INTEN11 Interrupt enable or disable on line 11 11 1 INTEN12 Interrupt enable or disable on line 12 12 1 INTEN13 Interrupt enable or disable on line 13 13 1 INTEN14 Interrupt enable or disable on line 14 14 1 INTEN15 Interrupt enable or disable on line 15 15 1 INTEN16 Interrupt enable or disable on line 16 16 1 INTEN17 Interrupt enable or disable on line 17 17 1 INTEN19 Interrupt enable or disable on line 19 19 1 INTEN21 Interrupt enable or disable on line 21 21 1 EVTEN EVTEN Event enable register (EXTINT_EVTEN) 0x4 0x20 read-write 0x00000000 EVTEN0 Event enable or disable on line 0 0 1 EVTEN1 Event enable or disable on line 1 1 1 EVTEN2 Event enable or disable on line 2 2 1 EVTEN3 Event enable or disable on line 3 3 1 EVTEN4 Event enable or disable on line 4 4 1 EVTEN5 Event enable or disable on line 5 5 1 EVTEN6 Event enable or disable on line 6 6 1 EVTEN7 Event enable or disable on line 7 7 1 EVTEN8 Event enable or disable on line 8 8 1 EVTEN9 Event enable or disable on line 9 9 1 EVTEN10 Event enable or disable on line 10 10 1 EVTEN11 Event enable or disable on line 11 11 1 EVTEN12 Event enable or disable on line 12 12 1 EVTEN13 Event enable or disable on line 13 13 1 EVTEN14 Event enable or disable on line 14 14 1 EVTEN15 Event enable or disable on line 15 15 1 EVTEN16 Event enable or disable on line 16 16 1 EVTEN17 Event enable or disable on line 17 17 1 EVTEN19 Event enable or disable on line 19 19 1 EVTEN21 Event enable or disable on line 21 21 1 POLCFG1 POLCFG1 Rising polarity configuration register(EXTINT_POLCFG1) 0x8 0x20 read-write 0x00000000 RP0 Rising polarity configuration bit of line 0 0 1 RP1 Rising polarity configuration bit of line 1 1 1 RP2 Rising polarity configuration bit of line 2 2 1 RP3 Rising polarity configuration bit of line 3 3 1 RP4 Rising polarity configuration bit of line 4 4 1 RP5 Rising polarity configuration bit of line 5 5 1 RP6 Rising polarity configuration bit of linee 6 6 1 RP7 Rising polarity configuration bit of line 7 7 1 RP8 Rising polarity configuration bit of line 8 8 1 RP9 Rising polarity configuration bit of line 9 9 1 RP10 Rising polarity configuration bit of line 10 10 1 RP11 Rising polarity configuration bit of line 11 11 1 RP12 Rising polarity configuration bit of line 12 12 1 RP13 Rising polarity configuration bit of line 13 13 1 RP14 Rising polarity configuration bit of line 14 14 1 RP15 Rising polarity configuration bit of line 15 15 1 RP16 Rising polarity configuration bit of line 16 16 1 RP17 Rising polarity configuration bit of line 17 17 1 RP19 Rising polarity configuration bit of line 19 19 1 RP21 Rising polarity configuration bit of line 21 21 1 POLCFG2 POLCFG2 Falling polarity configuration register(EXTINT_POLCFG2) 0xC 0x20 read-write 0x00000000 FP0 Falling polarity event configuration bit of line 0 0 1 FP1 Falling polarity event configuration bit of line 1 1 1 FP2 Falling polarity event configuration bit of line 2 2 1 FP3 Falling polarity event configuration bit of line 3 3 1 FP4 Falling polarity event configuration bit of line 4 4 1 FP5 Falling polarity event configuration bit of line 5 5 1 FP6 Falling polarity event configuration bit of line 6 6 1 FP7 Falling polarity event configuration bit of line 7 7 1 FP8 Falling polarity event configuration bit of line 8 8 1 FP9 Falling polarity event configuration bit of line 9 9 1 FP10 Falling polarity event configuration bit of line 10 10 1 FP11 Falling polarity event configuration bit of line 11 11 1 FP12 Falling polarity event configuration bit of line 12 12 1 FP13 Falling polarity event configuration bit of line 13 13 1 FP14 Falling polarity event configuration bit of line 14 14 1 FP15 Falling polarity event configuration bit of line 15 15 1 FP16 Falling polarity event configuration bit of line 16 16 1 FP17 Falling polarity event configuration bit of line 17 17 1 FP19 Falling polarity event configuration bit of line 19 19 1 FP21 Falling polarity event configuration bit of line 21 21 1 SWTRG SWTRG Software triggle register (EXTINT_SWIE) 0x10 0x20 read-write 0x00000000 SWT0 Software triggle on line 0 0 1 SWT1 Software triggle on line 1 1 1 SWT2 Software triggle on line 2 2 1 SWT3 Software triggle on line 3 3 1 SWT4 Software triggle on line 4 4 1 SWT5 Software triggle on line 5 5 1 SWT6 Software triggle on line 6 6 1 SWT7 Software triggle on line 7 7 1 SWT8 Software triggle on line 8 8 1 SWT9 Software triggle on line 9 9 1 SWT10 Software triggle on line 10 10 1 SWT11 Software triggle on line 11 11 1 SWT12 Software triggle on line 12 12 1 SWT13 Software triggle on line 13 13 1 SWT14 Software triggle on line 14 14 1 SWT15 Software triggle on line 15 15 1 SWT16 Software triggle on line 16 16 1 SWT17 Software triggle on line 17 17 1 SWT19 Software triggle on line 19 19 1 SWT21 Software triggle on line 21 21 1 INTSTS INTSTS Interrupt status register (EXTINT_INTSTS) 0x14 0x20 read-write 0x00000000 LINE0 Line 0 state bit 0 1 LINE1 Line 1 state bit 1 1 LINE2 Line 2 state bit 2 1 LINE3 Line 3 state bit 3 1 LINE4 Line 4 state bit 4 1 LINE5 Line 5 state bit 5 1 LINE6 Line 6 state bit 6 1 LINE7 Line 7 state bit 7 1 LINE8 Line 8 state bit 8 1 LINE9 Line 9 state bit 9 1 LINE10 Line 10 state bit 10 1 LINE11 Line 11 state bit 11 1 LINE12 Line 12 state bit 12 1 LINE13 Line 13 state bit 13 1 LINE14 Line 14 state bit 14 1 LINE15 Line 15 state bit 15 1 LINE16 Line 16 state bit 16 1 LINE17 Line 17 state bit 17 1 LINE19 Line 19 state bit 19 1 LINE21 Line 21 state bit 21 1 DMA1 DMA controller DMA 0x40020000 0x0 0x400 registers DMA1_Channel1 DMA1 Channel1 global interrupt 9 DMA1_Channel3_2 DMA1 Channel2 global interrupt 10 DMA1_Channel5_4 DMA1 Channel3 global interrupt 11 STS STS DMA status register (DMA_STS) 0x0 0x20 read-only 0x00000000 GF1 Channel 1 Global event flag 0 1 FDTF1 Channel 1 full data transfer event flag 1 1 HDTF1 Channel 1 half data transfer event flag 2 1 DTERRF1 Channel 1 data transfer error event flag 3 1 GF2 Channel 2 Global event flag 4 1 FDTF2 Channel 2 full data transfer event flag 5 1 HDTF2 Channel 2 half data transfer event flag 6 1 DTERRF2 Channel 2 data transfer error event flag 7 1 GF3 Channel 3 Global event flag 8 1 FDTF3 Channel 3 full data transfer event flag 9 1 HDTF3 Channel 3 half data transfer event flag 10 1 DTERRF3 Channel 3 data transfer error event flag 11 1 GF4 Channel 4 Global event flag 12 1 FDTF4 Channel 4 full data transfer event flag 13 1 HDTF4 Channel 4 half data transfer event flag 14 1 DTERRF4 Channel 4 data transfer error event flag 15 1 GF5 Channel 5 Global event flag 16 1 FDTF5 Channel 5 full data transfer event flag 17 1 HDTF5 Channel 5 half data transfer event flag 18 1 DTERRF5 Channel 5 data transfer error event flag 19 1 CLR CLR DMA flag clear register (DMA_CLR) 0x4 0x20 read-write 0x00000000 GFC1 Channel 1 Global flag clear 0 1 GFC2 Channel 2 Global flag clear 4 1 GFC3 Channel 3 Global flag clear 8 1 GFC4 Channel 4 Global flag clear 12 1 GFC5 Channel 5 Global flag clear 16 1 FDTFC1 Channel 1 full data transfer flag clear 1 1 FDTFC2 Channel 2 full data transfer flag clear 5 1 FDTFC3 Channel 3 full data transfer flag clear 9 1 FDTFC4 Channel 4 full data transfer flag clear 13 1 FDTFC5 Channel 5 full data transfer flag clear 17 1 HDTFC1 Channel 1 half data transfer flag clear 2 1 HDTFC2 Channel 2 half data transfer flag clear 6 1 HDTFC3 Channel 3 half data transfer flag clear 10 1 HDTFC4 Channel 4 half data transfer flag clear 14 1 HDTFC5 Channel 5 half data transfer flag clear 18 1 DTERRFC1 Channel 1 data transfer error flag clear 3 1 DTERRFC2 Channel 2 data transfer error flag clear 7 1 DTERRFC3 Channel 3 data transfer error flag clear 11 1 DTERRFC4 Channel 4 data transfer error flag clear 15 1 DTERRFC5 Channel 5 data transfer error flag clear 19 1 C1CTRL C1CTRL DMA channel configuration register 0x8 0x20 read-write 0x00000000 CHEN Channel enable 0 1 FDTIEN Full data transfer interrupt enable 1 1 HDTIEN Half data transfer interrupt enable 2 1 DTERRIEN Data transfer error interrupt enable 3 1 DTD Data transfer direction 4 1 LM Loop mode 5 1 PINCM Peripheral address increment mode 6 1 MINCM Memory address increment mode 7 1 PWIDTH Peripheral data bit width 8 2 MWIDTH Memory data bit width 10 2 CHPL Channel Priority level 12 2 M2M Memory to memory mode 14 1 C1DTCNT C1DTCNT DMA channel 1 number of data to transfer register 0xC 0x20 read-write 0x00000000 CNT Number of data to transfer 0 16 C1PADDR C1PADDR DMA channel 1 peripheral base address register 0x10 0x20 read-write 0x00000000 PADDR Peripheral address 0 32 C1MADDR C1MADDR DMA channel 1 memory base address register 0x14 0x20 read-write 0x00000000 MADDR Memory address 0 32 C2CTRL C2CTRL DMA channel configuration register 0x1C 0x20 read-write 0x00000000 CHEN Channel enable 0 1 FDTIEN Full data transfer interrupt enable 1 1 HDTIEN Half data transfer interrupt enable 2 1 DTERRIEN Data transfer error interrupt enable 3 1 DTD Data transfer direction 4 1 LM Loop mode 5 1 PINCM Peripheral address increment mode 6 1 MINCM Memory address increment mode 7 1 PWIDTH Peripheral data bit width 8 2 MWIDTH Memory data bit width 10 2 CHPL Channel Priority level 12 2 M2M Memory to memory mode 14 1 C2DTCNT C2DTCNT DMA channel 2 number of data to transfer register 0x20 0x20 read-write 0x00000000 CNT Number of data to transfer 0 16 C2PADDR C2PADDR DMA channel 2 peripheral base address register 0x24 0x20 read-write 0x00000000 PADDR Peripheral address 0 32 C2MADDR C2MADDR DMA channel 2 memory base address register 0x28 0x20 read-write 0x00000000 MADDR Memory address 0 32 C3CTRL C3CTRL DMA channel configuration register 0x30 0x20 read-write 0x00000000 CHEN Channel enable 0 1 FDTIEN Full data transfer interrupt enable 1 1 HDTIEN Half data transfer interrupt enable 2 1 DTERRIEN Data transfer error interrupt enable 3 1 DTD Data transfer direction 4 1 LM Loop mode 5 1 PINCM Peripheral address increment mode 6 1 MINCM Memory address increment mode 7 1 PWIDTH Peripheral data bit width 8 2 MWIDTH Memory data bit width 10 2 CHPL Channel Priority level 12 2 M2M Memory to memory mode 14 1 C3DTCNT C3DTCNT DMA channel 3 number of data to transfer register 0x34 0x20 read-write 0x00000000 CNT Number of data to transfer 0 16 C3PADDR C3PADDR DMA channel 3 peripheral base address register 0x38 0x20 read-write 0x00000000 PADDR Peripheral address 0 32 C3MADDR C3MADDR DMA channel 3 memory base address register 0x3C 0x20 read-write 0x00000000 MADDR Memory address 0 32 C4CTRL C4CTRL DMA channel configuration register 0x44 0x20 read-write 0x00000000 CHEN Channel enable 0 1 FDTIEN Full data transfer interrupt enable 1 1 HDTIEN Half data transfer interrupt enable 2 1 DTERRIEN Data transfer error interrupt enable 3 1 DTD Data transfer direction 4 1 LM Loop mode 5 1 PINCM Peripheral address increment mode 6 1 MINCM Memory address increment mode 7 1 PWIDTH Peripheral data bit width 8 2 MWIDTH Memory data bit width 10 2 CHPL Channel Priority level 12 2 M2M Memory to memory mode 14 1 C4DTCNT C4DTCNT DMA channel 4 number of data to transfer register 0x48 0x20 read-write 0x00000000 CNT Number of data to transfer 0 16 C4PADDR C4PADDR DMA channel 4 peripheral base address register 0x4C 0x20 read-write 0x00000000 PADDR Peripheral address 0 32 C4MADDR C4MADDR DMA channel 4 memory base address register 0x50 0x20 read-write 0x00000000 MADDR Memory address 0 32 C5CTRL C5CTRL DMA channel configuration register 0x58 0x20 read-write 0x00000000 CHEN Channel enable 0 1 FDTIEN Full data transfer interrupt enable 1 1 HDTIEN Half data transfer interrupt enable 2 1 DTERRIEN Data transfer error interrupt enable 3 1 DTD Data transfer direction 4 1 LM Loop mode 5 1 PINCM Peripheral address increment mode 6 1 MINCM Memory address increment mode 7 1 PWIDTH Peripheral data bit width 8 2 MWIDTH Memory data bit width 10 2 CHPL Channel Priority level 12 2 M2M Memory to memory mode 14 1 C5DTCNT C5DTCNT DMA channel 5 number of data to transfer register 0x5C 0x20 read-write 0x00000000 CNT Number of data to transfer 0 16 C5PADDR C5PADDR DMA channel 5 peripheral base address register 0x60 0x20 read-write 0x00000000 PADDR Peripheral address 0 32 C5MADDR C5MADDR DMA channel 5 memory base address register 0x64 0x20 read-write 0x00000000 MADDR Memory address 0 32 ERTC Real-time clock ERTC 0x40002800 0x0 0x400 registers TIME TIME time register 0x0 0x20 read-write 0x00000000 AMPM AM/PM notation 22 1 HT Hour tens 20 2 HU Hour units 16 4 MT Minute tens 12 3 MU Minute units 8 4 ST Second tens 4 3 SU Second units 0 4 DATE DATE date register 0x4 0x20 read-write 0x00002101 YT Year tens 20 4 YU Year units 16 4 WK Week 13 3 MT Month tens 12 1 MU Month units 8 4 DT Date tens 4 2 DU Date units 0 4 CTRL CTRL control register 0x8 0x20 read-write 0x00000000 CALOEN Calibration output enable 23 1 OUTSEL Output source selection 21 2 OUTP Output polarity 20 1 CALOSEL Calibration output selection 19 1 BPR Battery power domain data register 18 1 DEC1H Decrease 1 hour 17 1 ADD1H Add 1 hour 16 1 TSIEN Timestamp interrupt enable 15 1 ALAIEN Alarm A interrupt enable 12 1 TSEN Timestamp enable 11 1 ALAEN Alarm A enable 8 1 HM Hour mode 6 1 DREN Date/time register direct read enable 5 1 RCDEN Reference clock detection enable 4 1 TSEDG Timestamp trigger edge 3 1 STS STS initialization and status register 0xC 0x20 0x00000007 ALAWF Alarm A register allows write flag 0 1 read-only TADJF Time adjustment flag 3 1 read-write INITF Calendar initialization flag 4 1 read-only UPDF Calendar update flag 5 1 read-write IMF Enter initialization mode flag 6 1 read-only IMEN Initialization mode enable 7 1 read-write ALAF Alarm A flag 8 1 read-write TSF Timestamp flag 11 1 read-write TSOF Timestamp overflow flag 12 1 read-write TP1F Tamper detection 1 flag 13 1 read-write CALUPDF Calibration value update completed flag 16 1 read-only DIV DIV Diveder register 0x10 0x20 read-write 0x007F00FF DIVA Diveder A 16 7 DIVB Diveder B 0 15 ALA ALA Alarm A register 0x1C 0x20 read-write 0x00000000 MASK4 Date/week mask 31 1 WKSEL Date/week mode select 30 1 DT Date tens 28 2 DU Date units 24 4 MASK3 Hours mask 23 1 AMPM AM/PM 22 1 HT Hour tens 20 2 HU Hour units 16 4 MASK2 Minutes mask 15 1 MT Minute tens 12 3 MU Minute units 8 4 MASK1 Seconds mask 7 1 ST Second tens 4 3 SU Second units 0 4 WP WP write protection register 0x24 0x20 write-only 0x00000000 CMD Command register 0 8 SBS SBS sub second register 0x28 0x20 read-only 0x00000000 SBS Sub second value 0 16 TADJ TADJ time adjust register 0x2C 0x20 write-only 0x00000000 ADD1S Add 1 second 31 1 DECSBS Decrease sub-second value 0 15 TSTM TSTM time stamp time register 0x30 0x20 read-only 0x00000000 AMPM AMPM 22 1 HT Hour tens 20 2 HU Hour units 16 4 MT Minute tens 12 3 MU Minute units 8 4 ST Second tens 4 3 SU Second units 0 4 TSDT TSDT timestamp date register 0x34 0x20 read-only 0x00000000 WK Week 13 3 MT Month tens 12 1 MU Month units 8 4 DT Date tens 4 2 DU Date units 0 4 TSSBS TSSBS timestamp sub second register 0x38 0x20 read-only 0x00000000 SBS Sub second value 0 16 SCAL SCAL calibration register 0x3C 0x20 read-write 0x00000000 ADD Add ERTC clock 15 1 CAL8 8-second calibration period 14 1 CAL16 16 second calibration period 13 1 DEC Decrease ERTC clock 0 9 TAMP TAMP tamper and alternate function configuration register 0x40 0x20 read-write 0x00000000 OUTTYPE Output type 18 1 TPPU Tamper detection pull-up 15 1 TPPR Tamper detection pre-charge time 13 2 TPFLT Tamper detection filter time 11 2 TPFREQ Tamper detection frequency 8 3 TPTSEN Tamper detection timestamp enable 7 1 TPIEN Tamper detection interrupt enable 2 1 TP1EDG Tamper detection 1 valid edge 1 1 TP1EN Tamper detection 1 enable 0 1 ALASBS ALASBS alarm A sub second register 0x44 0x20 read-write 0x00000000 SBSMSK Sub-second mask 24 4 SBS Sub-seconds value 0 15 BPR1DT BPR1DT Battery powered domain register 0x50 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR2DT BPR2DT Battery powered domain register 0x54 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR3DT BPR3DT Battery powered domain register 0x58 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR4DT BPR4DT Battery powered domain register 0x5C 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR5DT BPR5DT Battery powered domain register 0x60 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 WDT Watchdog WDT 0x40003000 0x0 0x400 registers CMD CMD Command register 0x0 0x20 read-write 0x00000000 CMD Command register 0 16 DIV DIV Division register 0x4 0x20 read-write 0x00000000 DIV Division divider 0 3 RLD RLD Reload register 0x8 0x20 read-write 0x00000FFF RLD Reload value 0 12 STS STS Status register 0xC 0x20 read-write 0x00000000 DIVF Division value update complete flag 0 1 RLDF Reload value update complete flag 1 1 WWDT Window watchdog WWDT 0x40002C00 0x0 0x400 registers WWDT Window Watchdog interrupt 0 CTRL CTRL Control register 0x0 0x20 read-write 0x0000007F CNT Decrement counter 0 7 WWDTEN Window watchdog enable 7 1 CFG CFG Configuration register 0x4 0x20 read-write 0x0000007F WIN Window value 0 7 DIV Clock division value 7 2 RLDIEN Reload counter interrupt 9 1 STS STS Status register 0x8 0x20 read-write 0x00000000 RLDF Reload counter interrupt flag 0 1 TMR1 Advanced timer TIMER 0x40012C00 0x0 0x400 registers TMR1_CH TMR1 channel interrupt 14 TMR1_BRK_OVF_TRG_HALL TMR1 overflow brake trigger hall interrupt 13 CTRL1 CTRL1 Control register 1 0x0 0x20 read-write 0x0000 CLKDIV Clock divider 8 2 PRBEN Period buffer enable 7 1 TWCMSEL Two-way count mode selection 5 2 OWCDIR One-way count direction 4 1 OCMEN One cycle mode enable 3 1 OVFS Overflow event source 2 1 OVFEN Overflow event enable 1 1 TMREN TMR enable 0 1 CTRL2 CTRL2 Control register 2 0x4 0x20 read-write 0x0000 C4IOS Channel 4 idle output state 14 1 C3CIOS Channel 3 complementary idle output state 13 1 C3IOS Channel 3 idle output state 12 1 C2CIOS Channel 2 complementary idle output state 11 1 C2IOS Channel 2 idle output state 10 1 C1CIOS Channel 1 complementary idle output state 9 1 C1IOS Channel 1 idle output state 8 1 C1INSEL C1IN selection 7 1 PTOS Primary TMR output selection 4 3 DRS DMA request source 3 1 CCFS Channel control bit fresh select 2 1 CBCTRL Channel buffer control 0 1 STCTRL STCTRL Subordinate TMR control register 0x8 0x20 read-write 0x0000 ESP External signal polarity 15 1 ECMBEN External clock mode B enable 14 1 ESDIV External signal divider 12 2 ESF External signal filter 8 4 STS Subordinate TMR synchronization 7 1 STIS Subordinate TMR input selection 4 3 SMSEL Subordinate TMR mode selection 0 3 IDEN IDEN Interrupt/DMA enable register 0xC 0x20 read-write 0x0000 TDEN Trigger DMA request enable 14 1 HALLDE HALL DMA request enable 13 1 C4DEN Channel 4 DMA request enable 12 1 C3DEN Channel 3 DMA request enable 11 1 C2DEN Channel 2 DMA request enable 10 1 C1DEN Channel 1 DMA request enable 9 1 OVFDEN Overflow DMA request enable 8 1 BRKIE Brake interrupt enable 7 1 TIEN Trigger interrupt enable 6 1 HALLIEN HALL interrupt enable 5 1 C4IEN Channel 4 interrupt enable 4 1 C3IEN Channel 3 interrupt enable 3 1 C2IEN Channel 2 interrupt enable 2 1 C1IEN Channel 1 interrupt enable 1 1 OVFIEN Overflow interrupt enable 0 1 ISTS ISTS Interrupt status register 0x10 0x20 read-write 0x0000 C4RF Channel 4 recapture flag 12 1 C3RF Channel 3 recapture flag 11 1 C2RF Channel 2 recapture flag 10 1 C1RF Channel 1 recapture flag 9 1 BRKIF Brake interrupt flag 7 1 TRGIF Trigger interrupt flag 6 1 HALLIF HALL interrupt flag 5 1 C4IF Channel 4 interrupt flag 4 1 C3IF Channel 3 interrupt flag 3 1 C2IF Channel 2 interrupt flag 2 1 C1IF Channel 1 interrupt flag 1 1 OVFIF Overflow interrupt flag 0 1 SWEVT SWEVT Software event register 0x14 0x20 read-write 0x0000 BRKSWTR Brake event triggered by software 7 1 TRGSWTR Trigger event triggered by software 6 1 HALLSWTR HALL event triggered by software 5 1 C4SWTR Channel 4 event triggered by software 4 1 C3SWTR Channel 3 event triggered by software 3 1 C2SWTR Channel 2 event triggered by software 2 1 C1SWTR Channel 1 event triggered by software 1 1 OVFSWTR Overflow event triggered by software 0 1 CM1_OUTPUT CM1_OUTPUT Channel output mode register 0x18 0x20 read-write 0x00000000 C2OSEN Channel 2 output switch enable 15 1 C2OCTRL Channel 2 output control 12 3 C2OBEN Channel 2 output buffer enable 11 1 C2OIEN Channel 2 output immediately enable 10 1 C2C Channel 2 configure 8 2 C1OSEN Channel 1 output switch enable 7 1 C1OCTRL Channel 1 output control 4 3 C1OBEN Channel 1 output buffer enable 3 1 C1OIEN Channel 1 output immediately enable 2 1 C1C Channel 1 configure 0 2 CM1_INPUT CM1_INPUT Channel input mode register 1 CM1_OUTPUT 0x18 0x20 read-write 0x00000000 C2DF Channel 2 digital filter 12 4 C2IDIV Channel 2 input divider 10 2 C2C Channel 2 configure 8 2 C1DF Channel 1 digital filter 4 4 C1IDIV Channel 1 input divider 2 2 C1C Channel 1 configure 0 2 CM2_OUTPUT CM2_OUTPUT Channel output mode register 2 0x1C 0x20 read-write 0x00000000 C4OSEN Channel 4 output switch enable 15 1 C4OCTRL Channel 4 output control 12 3 C4OBEN Channel 4 output buffer enable 11 1 C4OIEN Channel 4 output immediately enable 10 1 C4C Channel 4 configure 8 2 C3OSEN Channel 3 output switch enable 7 1 C3OCTRL Channel 3 output control 4 3 C3OBEN Channel 3 output buffer enable 3 1 C3OIEN Channel 3 output immediately enable 2 1 C3C Channel 3 configure 0 2 CM2_INPUT CM2_INPUT Channel input mode register 2 CM2_OUTPUT 0x1C 0x20 read-write 0x00000000 C4DF Channel 4 digital filter 12 4 C4IDIV Channel 4 input divider 10 2 C4C Channel 4 configure 8 2 C3DF Channel 3 digital filter 4 4 C3IDIV Channel 3 input divider 2 2 C3C Channel 3 configure 0 2 CCTRL CCTRL Channel control register 0x20 0x20 read-write 0x0000 C4P Channel 4 Polarity 13 1 C4EN Channel 4 enable 12 1 C3CP Channel 3 complementary polarity 11 1 C3CEN Channel 3 complementary enable 10 1 C3P Channel 3 Polarity 9 1 C3EN Channel 3 enable 8 1 C2CP Channel 2 complementary polarity 7 1 C2CEN Channel 2 complementary enable 6 1 C2P Channel 2 Polarity 5 1 C2EN Channel 2 enable 4 1 C1CP Channel 1 complementary polarity 3 1 C1CEN Channel 1 complementary enable 2 1 C1P Channel 1 Polarity 1 1 C1EN Channel 1 enable 0 1 CVAL CVAL Counter value 0x24 0x20 read-write 0x00000000 CVAL Counter value 0 16 DIV DIV Divider value 0x28 0x20 read-write 0x0000 DIV Divider value 0 16 PR PR Period value 0x2C 0x20 read-write 0x00000000 PR Period value 0 16 RPR RPR Repetition of period value 0x30 0x20 read-write 0x0000 RPR Repetition of period value 0 8 C1DT C1DT Channel 1 data register 0x34 0x20 read-write 0x00000000 C1DT Channel 1 data register 0 16 C2DT C2DT Channel 2 data register 0x38 0x20 read-write 0x00000000 C2DT Channel 2 data register 0 16 C3DT C3DT Channel 3 data register 0x3C 0x20 read-write 0x00000000 C3DT Channel 3 data register 0 16 C4DT C4DT Channel 4 data register 0x40 0x20 read-write 0x00000000 C4DT Channel 4 data register 0 16 BRK BRK Brake register 0x44 0x20 read-write 0x0000 OEN Output enable 15 1 AOEN Automatic output enable 14 1 BRKV Brake input validity 13 1 BRKEN Brake enable 12 1 FCSOEN Frozen channel status when holistic output enable 11 1 FCSODIS Frozen channel status when holistic output disable 10 1 WPC Write protected configuration 8 2 DTC Dead-time configuration 0 8 DMACTRL DMACTRL DMA control register 0x48 0x20 read-write 0x0000 DTB DMA transfer bytes 8 5 ADDR DMA transfer address offset 0 5 DMADT DMADT DMA data register 0x4C 0x20 read-write 0x0000 DMADT DMA data register 0 16 TMR3 General purpose timer TIMER 0x40000400 0x0 0x400 registers TMR3 TMR3 global interrupt 16 CTRL1 CTRL1 Control register 1 0x0 0x20 read-write 0x0000 CLKDIV Clock divider 8 2 PRBEN Period buffer enable 7 1 TWCMSEL Two-way count mode selection 5 2 OWCDIR One-way count direction 4 1 OCMEN One cycle mode enable 3 1 OVFS Overflow event source 2 1 OVFEN Overflow event enable 1 1 TMREN TMR enable 0 1 CTRL2 CTRL2 Control register 2 0x4 0x20 read-write 0x0000 C1INSEL C1IN selection 7 1 PTOS Primary TMR output selection 4 3 DRS DMA request source 3 1 STCTRL STCTRL Subordinate TMR control register 0x8 0x20 read-write 0x0000 ESP External signal polarity 15 1 ECMBEN External clock mode B enable 14 1 ESDIV External signal divider 12 2 ESF External signal filter 8 4 STS Subordinate TMR synchronization 7 1 STIS Subordinate TMR input selection 4 3 SMSEL Subordinate TMR mode selection 0 3 IDEN IDEN Interrupt/DMA enable register 0xC 0x20 read-write 0x0000 TDEN Trigger DMA request enable 14 1 C4DEN Channel 4 DMA request enable 12 1 C3DEN Channel 3 DMA request enable 11 1 C2DEN Channel 2 DMA request enable 10 1 C1DEN Channel 1 DMA request enable 9 1 OVFDEN Overflow DMA request enable 8 1 TIEN Trigger interrupt enable 6 1 C4IEN Channel 4 interrupt enable 4 1 C3IEN Channel 3 interrupt enable 3 1 C2IEN Channel 2 interrupt enable 2 1 C1IEN Channel 1 interrupt enable 1 1 OVFIEN Overflow interrupt enable 0 1 ISTS ISTS Interrupt status register 0x10 0x20 read-write 0x0000 C4RF Channel 4 recapture flag 12 1 C3RF Channel 3 recapture flag 11 1 C2RF Channel 2 recapture flag 10 1 C1RF Channel 1 recapture flag 9 1 TRGIF Trigger interrupt flag 6 1 C4IF Channel 4 interrupt flag 4 1 C3IF Channel 3 interrupt flag 3 1 C2IF Channel 2 interrupt flag 2 1 C1IF Channel 1 interrupt flag 1 1 OVFIF Overflow interrupt flag 0 1 SWEVT SWEVT Software event register 0x14 0x20 read-write 0x0000 TRGSWTR Trigger event triggered by software 6 1 C4SWTR Channel 4 event triggered by software 4 1 C3SWTR Channel 3 event triggered by software 3 1 C2SWTR Channel 2 event triggered by software 2 1 C1SWTR Channel 1 event triggered by software 1 1 OVFSWTR Overflow event triggered by software 0 1 CM1_OUTPUT CM1_OUTPUT Channel output mode register 0x18 0x20 read-write 0x00000000 C2OSEN Channel 2 output switch enable 15 1 C2OCTRL Channel 2 output control 12 3 C2OBEN Channel 2 output buffer enable 11 1 C2OIEN Channel 2 output immediately enable 10 1 C2C Channel 2 configure 8 2 C1OSEN Channel 1 output switch enable 7 1 C1OCTRL Channel 1 output control 4 3 C1OBEN Channel 1 output buffer enable 3 1 C1OIEN Channel 1 output immediately enable 2 1 C1C Channel 1 configure 0 2 CM1_INPUT CM1_INPUT Channel input mode register 1 CM1_OUTPUT 0x18 0x20 read-write 0x00000000 C2DF Channel 2 digital filter 12 4 C2IDIV Channel 2 input divider 10 2 C2C Channel 2 configure 8 2 C1DF Channel 1 digital filter 4 4 C1IDIV Channel 1 input divider 2 2 C1C Channel 1 configure 0 2 CM2_OUTPUT CM2_OUTPUT Channel output mode register 2 0x1C 0x20 read-write 0x00000000 C4OSEN Channel 4 output switch enable 15 1 C4OCTRL Channel 4 output control 12 3 C4OBEN Channel 4 output buffer enable 11 1 C4OIEN Channel 4 output immediately enable 10 1 C4C Channel 4 configure 8 2 C3OSEN Channel 3 output switch enable 7 1 C3OCTRL Channel 3 output control 4 3 C3OBEN Channel 3 output buffer enable 3 1 C3OIEN Channel 3 output immediately enable 2 1 C3C Channel 3 configure 0 2 CM2_INPUT CM2_INPUT Channel input mode register 2 CM2_OUTPUT 0x1C 0x20 read-write 0x00000000 C4DF Channel 4 digital filter 12 4 C4IDIV Channel 4 input divider 10 2 C4C Channel 4 configure 8 2 C3DF Channel 3 digital filter 4 4 C3IDIV Channel 3 input divider 2 2 C3C Channel 3 configure 0 2 CCTRL CCTRL Channel control register 0x20 0x20 read-write 0x0000 C4P Channel 4 Polarity 13 1 C4EN Channel 4 enable 12 1 C3P Channel 3 Polarity 9 1 C3EN Channel 3 enable 8 1 C2P Channel 2 Polarity 5 1 C2EN Channel 2 enable 4 1 C1P Channel 1 Polarity 1 1 C1EN Channel 1 enable 0 1 CVAL CVAL Counter value 0x24 0x20 read-write 0x00000000 CVAL Counter value 0 16 DIV DIV Divider value 0x28 0x20 read-write 0x0000 DIV Divider value 0 16 PR PR Period value 0x2C 0x20 read-write 0x00000000 PR Period value 0 16 C1DT C1DT Channel 1 data register 0x34 0x20 read-write 0x00000000 C1DT Channel 1 data register 0 16 C2DT C2DT Channel 2 data register 0x38 0x20 read-write 0x00000000 C2DT Channel 2 data register 0 16 C3DT C3DT Channel 3 data register 0x3C 0x20 read-write 0x00000000 C3DT Channel 3 data register 0 16 C4DT C4DT Channel 4 data register 0x40 0x20 read-write 0x00000000 C4DT Channel 4 data register 0 16 DMACTRL DMACTRL DMA control register 0x48 0x20 read-write 0x0000 DTB DMA transfer bytes 8 5 ADDR DMA transfer address offset 0 5 DMADT DMADT DMA data register 0x4C 0x20 read-write 0x0000 DMADT DMA data register 0 16 TMR14 General purpose timer TIMER 0x40002000 0x0 0x400 registers TMR14 TMR14 global interrupt 19 CTRL1 CTRL1 Control register 1 0x0 0x20 read-write 0x0000 CLKDIV Clock divider 8 2 PRBEN Period buffer enable 7 1 OVFS Overflow event source 2 1 OVFEN Overflow event enable 1 1 TMREN TMR enable 0 1 IDEN IDEN Interrupt/DMA enable register 0xC 0x20 read-write 0x0000 C1IEN Channel 1 interrupt enable 1 1 OVFIEN Overflow interrupt enable 0 1 ISTS ISTS Interrupt status register 0x10 0x20 read-write 0x0000 C1RF Channel 1 recapture flag 9 1 C1IF Channel 1 interrupt flag 1 1 OVFIF Overflow interrupt flag 0 1 SWEVT SWEVT Software event register 0x14 0x20 read-write 0x0000 C1SWTR Channel 1 event triggered by software 1 1 OVFSWTR Overflow event triggered by software 0 1 CM1_OUTPUT CM1_OUTPUT Channel output mode register 0x18 0x20 read-write 0x00000000 C1OCTRL Channel 1 output control 4 3 C1OBEN Channel 1 output buffer enable 3 1 C1OIEN Channel 1 output immediately enable 2 1 C1C Channel 1 configure 0 2 CM1_INPUT CM1_INPUT Channel input mode register 1 CM1_OUTPUT 0x18 0x20 read-write 0x00000000 C1DF Channel 1 digital filter 4 4 C1IDIV Channel 1 input divider 2 2 C1C Channel 1 configure 0 2 CCTRL CCTRL Channel control register 0x20 0x20 read-write 0x0000 C1CP Channel 1 complementary polarity 3 1 C1P Channel 1 Polarity 1 1 C1EN Channel 1 enable 0 1 CVAL CVAL Counter value 0x24 0x20 read-write 0x00000000 CVAL Counter value 0 16 DIV DIV Divider value 0x28 0x20 read-write 0x0000 DIV Divider value 0 16 PR PR Period value 0x2C 0x20 read-write 0x00000000 PR Period value 0 16 C1DT C1DT Channel 1 data register 0x34 0x20 read-write 0x00000000 C1DT Channel 1 data register 0 16 TMR15 Advanced timer TIMER 0x40014000 0x0 0x400 registers TMR15 TMR15 global interrupt 20 CTRL1 CTRL1 Control register 1 0x0 0x20 read-write 0x0000 CLKDIV Clock divider 8 2 PRBEN Period buffer enable 7 1 OCMEN One cycle mode enable 3 1 OVFS Overflow event source 2 1 OVFEN Overflow event enable 1 1 TMREN TMR enable 0 1 CTRL2 CTRL2 Control register 2 0x4 0x20 read-write 0x0000 C2IOS Channel 2 idle output state 10 1 C1CIOS Channel 1 complementary idle output state 9 1 C1IOS Channel 1 idle output state 8 1 PTOS Primary TMR output selection 4 3 DRS DMA request source 3 1 CCFS Channel control bit fresh select 2 1 CBCTRL Channel buffer control 0 1 STCTRL STCTRL Subordinate TMR control register 0x8 0x20 read-write 0x0000 STS Subordinate TMR synchronization 7 1 STIS Subordinate TMR input selection 4 3 SMSEL Subordinate TMR mode selection 0 3 IDEN IDEN Interrupt/DMA enable register 0xC 0x20 read-write 0x0000 TDEN Trigger DMA request enable 14 1 HALLDE HALL DMA request enable 13 1 C2DEN Channel 2 DMA request enable 10 1 C1DEN Channel 1 DMA request enable 9 1 OVFDEN Overflow DMA request enable 8 1 BRKIE Brake interrupt enable 7 1 TIEN Trigger interrupt enable 6 1 HALLIEN HALL interrupt enable 5 1 C2IEN Channel 2 interrupt enable 2 1 C1IEN Channel 1 interrupt enable 1 1 OVFIEN Overflow interrupt enable 0 1 ISTS ISTS Interrupt status register 0x10 0x20 read-write 0x0000 C2RF Channel 2 recapture flag 10 1 C1RF Channel 1 recapture flag 9 1 BRKIF Brake interrupt flag 7 1 TRGIF Trigger interrupt flag 6 1 HALLIF HALL interrupt flag 5 1 C2IF Channel 2 interrupt flag 2 1 C1IF Channel 1 interrupt flag 1 1 OVFIF Overflow interrupt flag 0 1 SWEVT SWEVT Software event register 0x14 0x20 read-write 0x0000 BRKSWTR Brake event triggered by software 7 1 TRGSWTR Trigger event triggered by software 6 1 HALLSWTR HALL event triggered by software 5 1 C2SWTR Channel 2 event triggered by software 2 1 C1SWTR Channel 1 event triggered by software 1 1 OVFSWTR Overflow event triggered by software 0 1 CM1_OUTPUT CM1_OUTPUT Channel output mode register 0x18 0x20 read-write 0x00000000 C2OSEN Channel 2 output switch enable 15 1 C2OCTRL Channel 2 output control 12 3 C2OBEN Channel 2 output buffer enable 11 1 C2OIEN Channel 2 output immediately enable 10 1 C2C Channel 2 configure 8 2 C1OSEN Channel 1 output switch enable 7 1 C1OCTRL Channel 1 output control 4 3 C1OBEN Channel 1 output buffer enable 3 1 C1OIEN Channel 1 output immediately enable 2 1 C1C Channel 1 configure 0 2 CM1_INPUT CM1_INPUT Channel input mode register 1 CM1_OUTPUT 0x18 0x20 read-write 0x00000000 C2DF Channel 2 digital filter 12 4 C2IDIV Channel 2 input divider 10 2 C2C Channel 2 configure 8 2 C1DF Channel 1 digital filter 4 4 C1IDIV Channel 1 input divider 2 2 C1C Channel 1 configure 0 2 CCTRL CCTRL Channel control register 0x20 0x20 read-write 0x0000 C2P Channel 2 Polarity 5 1 C2EN Channel 2 enable 4 1 C1CP Channel 1 complementary polarity 3 1 C1CEN Channel 1 complementary enable 2 1 C1P Channel 1 Polarity 1 1 C1EN Channel 1 enable 0 1 CVAL CVAL Counter value 0x24 0x20 read-write 0x00000000 CVAL Counter value 0 16 DIV DIV Divider value 0x28 0x20 read-write 0x0000 DIV Divider value 0 16 PR PR Period value 0x2C 0x20 read-write 0x00000000 PR Period value 0 16 RPR RPR Repetition of period value 0x30 0x20 read-write 0x0000 RPR Repetition of period value 0 8 C1DT C1DT Channel 1 data register 0x34 0x20 read-write 0x00000000 C1DT Channel 1 data register 0 16 C2DT C2DT Channel 2 data register 0x38 0x20 read-write 0x00000000 C2DT Channel 2 data register 0 16 BRK BRK Brake register 0x44 0x20 read-write 0x0000 OEN Output enable 15 1 AOEN Automatic output enable 14 1 BRKV Brake input validity 13 1 BRKEN Brake enable 12 1 FCSOEN Frozen channel status when holistic output enable 11 1 FCSODIS Frozen channel status when holistic output disable 10 1 WPC Write protected configuration 8 2 DTC Dead-time configuration 0 8 DMACTRL DMACTRL DMA control register 0x48 0x20 read-write 0x0000 DTB DMA transfer bytes 8 5 ADDR DMA transfer address offset 0 5 DMADT DMADT DMA data register 0x4C 0x20 read-write 0x0000 DMADT DMA data register 0 16 TMR16 General purpose timer TIMER 0x40014400 0x0 0x400 registers TMR16 TMR16 global interrupt 21 CTRL1 CTRL1 Control register 1 0x0 0x20 read-write 0x0000 CLKDIV Clock divider 8 2 PRBEN Period buffer enable 7 1 OCMEN One cycle mode enable 3 1 OVFS Overflow event source 2 1 OVFEN Overflow event enable 1 1 TMREN TMR enable 0 1 CTRL2 CTRL2 Control register 2 0x4 0x20 read-write 0x0000 C1CIOS Channel 1 complementary idle output state 9 1 C1IOS Channel 1 idle output state 8 1 DRS DMA request source 3 1 CCFS Channel control bit fresh select 2 1 CBCTRL Channel buffer control 0 1 IDEN IDEN Interrupt/DMA enable register 0xC 0x20 read-write 0x0000 C1DEN Channel 1 DMA request enable 9 1 OVFDEN Overflow DMA request enable 8 1 BRKIE Brake interrupt enable 7 1 HALLIEN HALL interrupt enable 5 1 C1IEN Channel 1 interrupt enable 1 1 OVFIEN Overflow interrupt enable 0 1 ISTS ISTS Interrupt status register 0x10 0x20 read-write 0x0000 C1RF Channel 1 recapture flag 9 1 BRKIF Brake interrupt flag 7 1 HALLIF HALL interrupt flag 5 1 C4IF Channel 4 interrupt flag 4 1 C1IF Channel 1 interrupt flag 1 1 OVFIF Overflow interrupt flag 0 1 SWEVT SWEVT Software event register 0x14 0x20 read-write 0x0000 BRKSWTR Brake event triggered by software 7 1 HALLSWTR HALL event triggered by software 5 1 C1SWTR Channel 1 event triggered by software 1 1 OVFSWTR Overflow event triggered by software 0 1 CM1_OUTPUT CM1_OUTPUT Channel output mode register 0x18 0x20 read-write 0x00000000 C1OSEN Channel 1 output switch enable 7 1 C1OCTRL Channel 1 output control 4 3 C1OBEN Channel 1 output buffer enable 3 1 C1OIEN Channel 1 output immediately enable 2 1 C1C Channel 1 configure 0 2 CM1_INPUT CM1_INPUT Channel input mode register 1 CM1_OUTPUT 0x18 0x20 read-write 0x00000000 C1DF Channel 1 digital filter 4 4 C1IDIV Channel 1 input divider 2 2 C1C Channel 1 configure 0 2 CCTRL CCTRL Channel control register 0x20 0x20 read-write 0x0000 C1CP Channel 1 complementary polarity 3 1 C1CEN Channel 1 complementary enable 2 1 C1P Channel 1 Polarity 1 1 C1EN Channel 1 enable 0 1 CVAL CVAL Counter value 0x24 0x20 read-write 0x00000000 CVAL Counter value 0 16 DIV DIV Divider value 0x28 0x20 read-write 0x0000 DIV Divider value 0 16 PR PR Period value 0x2C 0x20 read-write 0x00000000 PR Period value 0 16 RPR RPR Repetition of period value 0x30 0x20 read-write 0x0000 RPR Repetition of period value 0 8 C1DT C1DT Channel 1 data register 0x34 0x20 read-write 0x00000000 C1DT Channel 1 data register 0 16 BRK BRK Brake register 0x44 0x20 read-write 0x0000 OEN Output enable 15 1 AOEN Automatic output enable 14 1 BRKV Brake input validity 13 1 BRKEN Brake enable 12 1 FCSOEN Frozen channel status when holistic output enable 11 1 FCSODIS Frozen channel status when holistic output disable 10 1 WPC Write protected configuration 8 2 DTC Dead-time configuration 0 8 DMACTRL DMACTRL DMA control register 0x48 0x20 read-write 0x0000 DTB DMA transfer bytes 8 5 ADDR DMA transfer address offset 0 5 DMADT DMADT DMA data register 0x4C 0x20 read-write 0x0000 DMADT DMA data register 0 16 TMR17 0x40014800 TMR17 TMR17 global interrupt 22 TMR6 Basic timer TIMER 0x40001000 0x0 0x400 registers TMR6 TMR6 global interrupt 17 CTRL1 CTRL1 Control register 1 0x0 0x20 read-write 0x0000 PRBEN Period buffer enable 7 1 OCMEN One cycle mode enable 3 1 OVFS Overflow event source 2 1 OVFEN Overflow event enable 1 1 TMREN TMR enable 0 1 CTRL2 CTRL2 Control register 2 0x4 0x20 read-write 0x0000 PTOS Primary TMR output selection 4 3 IDEN IDEN Interrupt/DMA enable register 0xC 0x20 read-write 0x0000 OVFDEN Overflow DMA request enable 8 1 OVFIEN Overflow interrupt enable 0 1 ISTS ISTS Interrupt status register 0x10 0x20 read-write 0x0000 OVFIF Overflow interrupt flag 0 1 SWEVT SWEVT Software event register 0x14 0x20 read-write 0x0000 OVFSWTR Overflow event triggered by software 0 1 CVAL CVAL Counter value 0x24 0x20 read-write 0x00000000 CVAL Counter value 0 16 DIV DIV Divider value 0x28 0x20 read-write 0x0000 DIV Divider value 0 16 PR PR Period value 0x2C 0x20 read-write 0x00000000 PR Period value 0 16 I2C1 Inter integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EVT I2C1 event interrupt 31 I2C1_ERR I2C1 error interrupt 32 CTRL1 CTRL1 Control register 1 0x0 0x20 read-write 0x0000 RESET I2C peripheral reset 15 1 SMBALERT SMBus alert pin set 13 1 PECTEN Request PEC transmission enable 12 1 MACKCTRL Master receiving mode acknowledge control 11 1 ACKEN Acknowledge enable 10 1 GENSTOP Stop generation 9 1 GENSTART Start generation 8 1 STRETCH Clock stretching mode 7 1 GCAEN General call address enable 6 1 PECEN PEC calculation enable 5 1 ARPEN SMBus address resolution protocol enable 4 1 SMBMODE SMBus device mode 3 1 PERMODE I2C peripheral mode 1 1 I2CEN Peripheral enable 0 1 CTRL2 CTRL2 Control register 2 0x4 0x20 read-write 0x0000 DMAEND DMA transfer end indication 12 1 DMAEN DMA transfer enable 11 1 DATAIEN Data transmission interrupt enable 10 1 EVTIEN Event interrupt enable 9 1 ERRIEN Error interrupt enable 8 1 CLKFREQ Input clock frequency 0 8 OADDR1 OADDR1 Own address register 1 0x8 0x20 read-write 0x0000 ADDR1MODE Address mode 15 1 ADDR1 Own address 1 0 10 OADDR2 OADDR2 Own address register 2 0xC 0x20 read-write 0x0000 ADDR2 Own address 2 1 7 ADDR2EN Own address 2 enable 0 1 DT DT Data register 0x10 0x20 read-write 0x0000 DT data register 0 8 STS1 STS1 Status register 1 0x14 0x20 0x0000 ALERTF SMBus alert 15 1 read-write TMOUT Timeout error 14 1 read-write PECERR PEC receive error 12 1 read-write OUF Overflow or underflow 11 1 read-write ACKFAIL Acknowledge failure 10 1 read-write ARLOST Arbitration lost (master mode) 9 1 read-write BUSERR Bus error 8 1 read-write TDBE Transmit data buffer empty (transmitters) 7 1 read-only RDBF Receive data buffer full (receivers) 6 1 read-only STOPF Stop detection (slave mode) 4 1 read-only ADDRHF address header match (Master mode) 3 1 read-only TDC Transmit data complete 2 1 read-only ADDR7F Address sent (master mode)/matched (slave mode) 1 1 read-only STARTF Start bit (Master mode) 0 1 read-only STS2 STS2 Status register 2 0x18 0x20 read-only 0x0000 PECVAL PEC value 8 8 ADDR2F Received address 2 7 1 HOSTADDRF SMBus host address receiving 6 1 DEVADDRF SMBus device address receiving 5 1 GCADDRF General call address reception 4 1 DIRF Transmission direction 2 1 BUSYF Bus busy 1 1 TRMODE Transmission mode 0 1 CLKCTRL CLKCTRL Clock control register 0x1C 0x20 read-write 0x0000 SPEEDMODE Speed mode selection 15 1 DUTYMODE Fast mode duty cycle 14 1 SPEED I2C bus speed config 0 12 TMRISE TMRISE TRISE register 0x20 0x20 read-write 0x0002 RISETIME I2C bus rise time 0 6 I2C2 0x40005800 I2C2_EVT I2C2 event interrupt 33 I2C2_ERR I2C2 error interrupt 34 SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 35 CTRL1 CTRL1 control register 1 0x0 0x20 read-write 0x0000 SLBEN Single line bidirectional half-duplex enable 15 1 SLBTD Single line bidirectional half-duplex transmission direction 14 1 CCEN CRC calculation enable 13 1 NTC Next transmission CRC 12 1 FBN frame bit num 11 1 ORA Only receive active 10 1 SWCSEN Software CS enable 9 1 SWCSIL Software CS internal level 8 1 LTF LSB transmit first 7 1 SPIEN SPI enable 6 1 MDIV2_0 Master clock frequency division bit2-0 3 3 MSTEN Master enable 2 1 CLKPOL Clock polarity 1 1 CLKPHA Clock phase 0 1 CTRL2 CTRL2 control register 2 0x4 0x20 read-write 0x0000 MDIV3 Master clock frequency division bit3 8 1 TDBEIE Transmit data buffer empty interrupt enable 7 1 RDBFIE Receive data buffer full interrupt enable 6 1 ERRIE Error interrupt enable 5 1 HWCSOE Hardware CS output enable 2 1 DMATEN DMA transmit enable 1 1 DMAREN DMA receive enable 0 1 STS STS status register 0x8 0x20 0x0002 BF Busy flag 7 1 read-only ROERR Receiver overflow error 6 1 read-only MMERR Master mode error 5 1 read-only CCERR CRC calculation error 4 1 read-write TUERR Transmitter underload error 3 1 read-only ACS Audio channel state 2 1 read-only TDBE Transmit data buffer empty 1 1 read-only RDBF Receive data buffer full 0 1 read-only DT DT data register 0xC 0x20 read-write 0x0000 DT Data value 0 16 CPOLY CPOLY CRC polynomial register 0x10 0x20 read-write 0x0007 CPOLY CRC polynomial 0 16 RCRC RCRC Receive CRC register 0x14 0x20 read-only 0x0000 RCRC Receive CRC 0 16 TCRC TCRC Transmit CRC register 0x18 0x20 read-only 0x0000 TCRC Transmit CRC 0 16 I2SCTRL I2SCTRL I2S control register 0x1C 0x20 read-write 0x0000 I2SMSEL I2S mode select 11 1 I2SEN I2S Enable 10 1 OPERSEL I2S operation select 8 2 PCMFSSEL PCM frame synchronization select 7 1 STDSEL I2S standard select 4 2 I2SCLKPOL I2S clock polarity 3 1 I2SDBN I2S data bit num 1 2 I2SCBN I2S channel bit num 0 1 I2SCLK I2SCLK I2S clock register 0x20 0x20 read-write 00000010 I2SDIV9_8 I2S division bit9 and bit8 10 2 I2SMCLKOE I2S master clock output enable 9 1 I2SODD Odd result for I2S division 8 1 I2SDIV7_0 I2S division bit7 to bit0 0 8 SPI2 0x40003800 SPI2 SPI2 global interrupt 36 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 27 STS STS Status register 0x0 0x20 0x00C0 CTSCF CTS change flag 9 1 read-write BFF Break frame flag 8 1 read-write TDBE Transmit data buffer empty 7 1 read-only TDC Transmit data complete 6 1 read-write RDBF Receive data buffer full 5 1 read-write IDLEF IDLE flag 4 1 read-only ROERR Receiver overflow error 3 1 read-only NERR Noise error 2 1 read-only FERR Framing error 1 1 read-only PERR Parity error 0 1 read-only DT DT Data register 0x4 0x20 read-write 0x00000000 DT Data value 0 9 BAUDR BAUDR Baud rate register 0x8 0x20 read-write 0x0000 DIV Division 0 16 CTRL1 CTRL1 Control register 1 0xC 0x20 read-write 0x0000 UEN USART enable 13 1 DBN Data bit num 12 1 WUM Wake up mode 11 1 PEN Parity enable 10 1 PSEL Parity selection 9 1 PERRIEN PERR interrupt enable 8 1 TDBEIEN TDBE interrupt enable 7 1 TDCIEN TDC interrupt enable 6 1 RDBFIEN RDBF interrupt enable 5 1 IDLEIEN IDLE interrupt enable 4 1 TEN Transmitter enable 3 1 REN Receiver enable 2 1 RM Receiver mute 1 1 SBF Send break frame 0 1 CTRL2 CTRL2 Control register 2 0x10 0x20 read-write 0x0000 TRPSWAP Transmit receive pin swap 15 1 LINEN LIN mode enable 14 1 STOPBN STOP bit num 12 2 CLKEN Clock enable 11 1 CLKPOL Clock polarity 10 1 CLKPHA Clock phase 9 1 LBCP Last bit clock pulse 8 1 BFIEN Break frame interrupt enable 6 1 BFBN Break frame bit num 5 1 ID USART identification 0 4 CTRL3 CTRL3 Control register 3 0x14 0x20 read-write 0x0000 CTSCFIEN CTSCF interrupt enable 10 1 CTSEN CTS enable 9 1 RTSEN RTS enable 8 1 DMATEN DMA transmitter enable 7 1 DMAREN DMA receiver enable 6 1 SCMEN Smartcard mode enable 5 1 SCNACKEN Smartcard NACK enable 4 1 SLBEN Single line bidirectional half-duplex enable 3 1 IRDALP IrDA low-power mode 2 1 IRDAEN IrDA enable 1 1 ERRIEN Error interrupt enable 0 1 GDIV GDIV Guard time and division register 0x18 0x20 read-write 0x0000 SCGT Smart card guard time value 8 8 ISDIV IrDA/smartcard division value 0 8 USART2 0x40004400 USART2 USART2 global interrupt 28 ADC Analog to digital converter ADC 0x40012400 0x0 0x400 registers ADC1_2 ADC1 and ADC2 global interrupt 18 STS STS status register 0x0 0x20 read-write 0x00000000 OCCS Ordinary channel conversion start flag 4 1 PCCS Preempted channel conversion start flag 3 1 PCCE Preempted channels conversion end flag 2 1 CCE Channels conversion end flag 1 1 VMOR Voltage monitoring out of range flag 0 1 CTRL1 CTRL1 control register 1 0x4 0x20 read-write 0x00000000 OCVMEN Voltage monitoring enable on ordinary channels 23 1 PCVMEN Voltage monitoring enable on preempted channels 22 1 OCPCNT Partitioned mode conversion count of ordinary channels 13 3 PCPEN Partitioned mode enable on preempted channels 12 1 OCPEN Partitioned mode enable on ordinary channels 11 1 PCAUTOEN Preempted group automatic conversion enable after ordinary group 10 1 VMSGEN Voltage monitoring enable on a single channel 9 1 SQEN Sequence mode enable 8 1 PCCEIEN Conversion end interrupt enable for preempted channels 7 1 VMORIEN Voltage monitoring out of range interrupt enable 6 1 CCEIEN Channel conversion end interrupt enable 5 1 VMCSEL Voltage monitoring channel select 0 5 CTRL2 CTRL2 control register 2 0x8 0x20 read-write 0x00000000 ITSRVEN Internal temperature sensor and VINTRV enable 23 1 OCSWTRG Conversion trigger by software of ordinary channels 22 1 PCSWTRG Conversion trigger by software of preempted channels 21 1 OCTEN Trigger mode enable for ordinary channels conversion 20 1 OCTESEL Low bit of trigger event select for ordinary channels conversion 17 3 PCTEN Trigger mode enable for preempted channels conversion 15 1 PCTESEL Low bit of trigger event select for preempted channels conversion 12 3 DTALIGN Data alignment 11 1 OCDMAEN DMA transfer enable of ordinary channels 8 1 ADCALINIT initialize A/D calibration 3 1 ADCAL A/D Calibration 2 1 RPEN Repeat mode enable 1 1 ADCEN A/D converter enable 0 1 SPT1 SPT1 sample time register 1 0xC 0x20 read-write 0x00000000 CSPT17 Selection sample time of channel ADC_IN17 21 3 CSPT16 Selection sample time of channel ADC_IN16 18 3 CSPT15 Selection sample time of channel ADC_IN15 15 3 CSPT14 Selection sample time of channel ADC_IN14 12 3 CSPT13 Selection sample time of channel ADC_IN13 9 3 CSPT12 Selection sample time of channel ADC_IN12 6 3 CSPT11 Selection sample time of channel ADC_IN11 3 3 CSPT10 Selection sample time of channel ADC_IN10 0 3 SPT2 SPT2 sample time register 2 0x10 0x20 read-write 0x00000000 CSPT9 Selection sample time of channel ADC_IN9 27 3 CSPT8 Selection sample time of channel ADC_IN8 24 3 CSPT7 Selection sample time of channel ADC_IN7 21 3 CSPT6 Selection sample time of channel ADC_IN6 18 3 CSPT5 Selection sample time of channel ADC_IN5 15 3 CSPT4 Selection sample time of channel ADC_IN4 12 3 CSPT3 Selection sample time of channel ADC_IN3 9 3 CSPT2 Selection sample time of channel ADC_IN2 6 3 CSPT1 Selection sample time of channel ADC_IN1 3 3 CSPT0 Selection sample time of channel ADC_IN0 0 3 PCDTO1 PCDTO1 Preempted channel 1 data offset register 0x14 0x20 read-write 0x00000000 PCDTO1 Data offset for Preempted channel 1 0 12 PCDTO2 PCDTO2 Preempted channel 2 data offset register 0x18 0x20 read-write 0x00000000 PCDTO2 Data offset for Preempted channel 2 0 12 PCDTO3 PCDTO3 Preempted channel 3 data offset register 0x1C 0x20 read-write 0x00000000 PCDTO3 Data offset for Preempted channel 3 0 12 PCDTO4 PCDTO4 Preempted channel 4 data offset register 0x20 0x20 read-write 0x00000000 PCDTO4 Data offset for Preempted channel 4 0 12 VMHB VMHB Voltage monitoring high boundary register 0x24 0x20 read-write 0x00000FFF VMHB Voltage monitoring high boundary 0 12 VMLB VMLB Voltage monitoring low boundary register 0x28 0x20 read-write 0x00000000 VMLB Voltage monitoring low boundary 0 12 OSQ1 OSQ1 Ordinary sequence register 1 0x2C 0x20 read-write 0x00000000 OCLEN Ordinary conversion sequence length 20 4 OSN16 Number of 16th conversion in ordinary sequence 15 5 OSN15 Number of 15th conversion in ordinary sequence 10 5 OSN14 Number of 14th conversion in ordinary sequence 5 5 OSN13 Number of 13th conversion in ordinary sequence 0 5 OSQ2 OSQ2 Ordinary sequence register 2 0x30 0x20 read-write 0x00000000 OSN12 Number of 12th conversion in ordinary sequence 25 5 OSN11 Number of 11th conversion in ordinary sequence 20 5 OSN10 Number of 10th conversion in ordinary sequence 15 5 OSN9 Number of 8th conversion in ordinary sequence 10 5 OSN8 Number of 7th conversion in ordinary sequence 5 5 OSN7 Number of 13th conversion in ordinary sequence 0 5 OSQ3 OSQ3 Ordinary sequence register 3 0x34 0x20 read-write 0x00000000 OSN6 Number of 6th conversion in ordinary sequence 25 5 OSN5 Number of 5th conversion in ordinary sequence 20 5 OSN4 Number of 4th conversion in ordinary sequence 15 5 OSN3 number of 3rd conversion in ordinary sequence 10 5 OSN2 Number of 2nd conversion in ordinary sequence 5 5 OSN1 Number of 1st conversion in ordinary sequence 0 5 PSQ PSQ Preempted sequence register 0x38 0x20 read-write 0x00000000 PCLEN Preempted conversion sequence length 20 2 PSN4 Number of 4th conversion in Preempted sequence 15 5 PSN3 Number of 3rd conversion in Preempted sequence 10 5 PSN2 Number of 2nd conversion in Preempted sequence 5 5 PSN1 Number of 1st conversion in Preempted sequence 0 5 PDT1 PDT1 Preempted data register 1 0x3C 0x20 read-only 0x00000000 PDT1 Preempted data 0 16 PDT2 PDT2 Preempted data register 2 0x40 0x20 read-only 0x00000000 PDT2 Preempted data 0 16 PDT3 PDT3 Preempted data register 3 0x44 0x20 read-only 0x00000000 PDT3 Preempted data 0 16 PDT4 PDT4 Preempted data register 4 0x48 0x20 read-only 0x00000000 PDT4 Preempted data 0 16 ODT ODT Ordinary data register 0x4C 0x20 read-only 0x00000000 ODT Conversion data of ordinary channel 0 16 CMP Comparator CMP 0x4001001C 0x0 0x3E4 registers ADC_CMP ADC and CMP interrupt 12 CTRLSTS CTRLSTS CMP control/status register 0x0 0x20 0x00000000 CMPEN Comparator enable bit 0 1 read-write CMPIS Comparator input shift 1 1 read-write CMPSSEL Comparator speed selection 2 2 read-write CMPINVSEL Comparator inverting selection 4 3 read-write CMPNINVSEL Comparator non-inverting input selection 7 2 read-write CMPTAG Comparator output target 10 3 read-write CMPP Comparator polarity 15 1 read-write CMPHYST Comparator hysteresis 16 2 read-write CMPBLANKING Comparator blanking 18 3 read-write BRGEN Comparator brgen 22 1 read-write SCALEN Comparator scalen 23 1 read-write CMPVALUE Comparator output value 30 1 read-only CMPWP Comparator write protect 31 1 read-write G_FILTER_EN G_FILTER_EN G_FILTER_EN 0x8 0x20 read-write 0x0000 GFE Glitch filter enable 0 1 HIGH_PULSE HIGH_PULSE HIGH_PULSE 0xC 0x20 read-write 0x0000 H_PULSE_CNT High pulse Count 0 6 LOW_PULSE LOW_PULSE LOW_PULSE 0x10 0x20 read-write 0x0000 L_PULSE_CNT Low pulse Count 0 6 DEBUG Debug support DEBUG 0xE0042000 0x0 0x400 registers IDCODE IDCODE DEBUG_IDCODE 0x0 0x20 read-only 0x0 PID PID 0 32 CTRL CTRL DEBUG_CTRL 0x4 0x20 read-write 0x0 SLEEP_DEBUG SLEEP_DEBUG 0 1 DEEPSLEEP_DEBUG DEEPSLEEP_DEBUG 1 1 STANDBY_DEBUG STANDBY_DEBUG 2 1 WDT_PAUSE WDT_PAUSE 8 1 WWDT_PAUSE WWDT_PAUSE 9 1 TMR1_PAUSE TMR1_PAUSE 10 1 TMR3_PAUSE TMR3_PAUSE 12 1 ERTC_PAUSE ERTC_PAUSE 14 1 I2C1_SMBUS_TIMEOUT I2C1_SMBUS_TIMEOUT 15 1 I2C2_SMBUS_TIMEOUT I2C2_SMBUS_TIMEOUT 16 1 TMR6_PAUSE TMR6_PAUSE 19 1 ERTC_512_PAUSE ERTC_512_PAUSE 21 1 TMR15_PAUSE TMR15_PAUSE 22 1 TMR16_PAUSE TMR16_PAUSE 23 1 TMR17_PAUSE TMR17_PAUSE 24 1 TMR14_PAUSE TMR14_PAUSE 27 1 CRC CRC calculation unit CRC 0x40023000 0x0 0x400 registers DT DT Data register 0x0 0x20 read-write 0xFFFFFFFF DT Data Register 0 32 CDT CDT Common data register 0x4 0x20 read-write 0x00000000 CDT Common Data 0 1 CTRL CTRL Control register 0x8 0x20 read-write 0x00000000 RST Reset bit 0 1 POLY_SIZE Polynomial size 3 2 REVID Reverse input data 5 2 REVOD Reverse output data 7 1 IDT IDT Initial data register 0x10 0x20 read-write 0xFFFFFFFF IDT Initial Data 0 32 POLY POLY Polynomial coefficient register 0x14 0x20 read-write 0x04C11DB7 POLY polynomial coefficient 0 32 FLASH Flash memory controler FLASH 0x40022000 0x0 0x400 registers FLASH Flash global interrupt 3 PSR PSR Performance selection register 0x0 0x20 0x00000030 WTCYC Wait cycle 0 3 read-write HFCYC_EN Half cycle acceleration access enable 3 1 read-write PFT_EN Prefetch enable 4 1 read-write PFT_ENF Prefetch enabled flag 5 1 read-only PFT_EN2 Prefetch enable 2 6 1 read-write PFT_ENF2 Prefetch enabled flag 2 7 1 read-only PFT_LAT_DIS Prefetch latency disable 8 1 read-write UNLOCK UNLOCK Unlock register 0x4 0x20 write-only 0x00000000 UKVAL Unlock key value 0 32 USD_UNLOCK USD_UNLOCK USD unlock register 0x8 0x20 write-only 0x00000000 USD_UKVAL User system data Unlock key value 0 32 STS STS Status register 0xC 0x20 0x00000000 ODF Operate done flag 5 1 read-write EPPERR Erase/program protection error 4 1 read-write PRGMERR program error 2 1 read-write OBF Operate busy flag 0 1 read-only CTRL CTRL Control register 0x10 0x20 read-write 0x00020080 FPRGM Flash program 0 1 SECERS Sector erase 1 1 BANKERS Bank erase 2 1 USDPRGM User system data program 4 1 USDERS User system data erase 5 1 ERSTR Erasing start 6 1 OPLK Operation lock 7 1 USDULKS User system data unlock success 9 1 ERRIE Error interrupt enable 10 1 ODFIE Operation done flag interrupt enable 12 1 FAP_HL_DIS FAP high level disable 16 1 LPMEN Low power mode enable 17 1 ADDR ADDR Address register 0x14 0x20 write-only 0x00000000 FA Flash Address 0 32 USD USD User system data register 0x1C 0x20 read-only 0x03FFFFFC USDERR User system data error 0 1 FAP FLASH access protection 1 1 nWDT_ATO_EN WDT auto enable 2 1 nDEPSLP_RST Deepsleep reset 3 1 nSTDBY_RST Standby reset 4 1 nBOOT1 boot1 6 1 USER_D0 User data 0 10 8 USER_D1 User data 1 18 8 FAP_HL FAP high level 26 1 EPPS EPPS Erase/program protection status register 0x20 0x20 read-only 0xFFFFFFFF EPPS Erase/program protection status 0 32 SLIB_STS0 SLIB_STS0 sLib status 0 register 0x74 0x20 0x00000000 BTM_AP_ENF Boot memory store application code enabled flag 0 1 EM_SLIB_ENF Extension memory sLib enabled flag 2 1 SLIB_ENF sLib enabled flag 3 1 EM_SLIB_INST_SS Extension memory sLib instruction start sector 16 8 SLIB_STS1 SLIB_STS1 sLib status 1 register 0x78 0x20 0x00000000 SLIB_SS sLib start sector 0 11 SLIB_INST_SS sLib instruction start sector 11 11 SLIB_ES sLib end sector 22 10 SLIB_PWD_CLR SLIB_PWD_CLR SLIB password clear register 0x7C 0x20 0x00000000 write-only SLIB_PCLR_VAL sLib password clear value 0 32 SLIB_MISC_STS SLIB_MISC_STS sLib misc status register 0x80 0x20 0x01000000 SLIB_PWD_ERR sLib password error 0 1 read-only SLIB_PWD_OK sLib password ok 1 1 read-only SLIB_ULKF sLib unlock flag 2 1 read-only CRC_ADDR CRC_ADDR Flash CRC data start address register 0x84 0x20 write-only 0x00000000 CRC_ADDR CRC address 0 32 CRC_CTRL CRC_CTRL Flash CRC controll register 0x88 0x20 0x00000000 CRC_SN CRC sector numbler 0 16 read-write CRC_STRT CRC start 16 1 write-only CRC_CHKR CRC_CHKR FLASH CRC check result register 0x8C 0x20 read-only 0x00000000 FCRC_OUT CRC32 verification result of flash user code or SLIB code 0 32 SLIB_SET_PWD SLIB_SET_PWD sLib password setting register 0x160 0x20 write-only 0x00000000 SLIB_PSET_VAL sLib password setting val 0 32 SLIB_SET_RANGE SLIB_SET_RANGE Configure sLib range register 0x164 0x20 write-only 0x00000000 SLIB_SS_SET sLib start sector setting 0 11 SLIB_ISS_SET sLib instruction start sector setting 11 11 SLIB_ES_SET sLib end sector setting 22 10 EM_SLIB_SET EM_SLIB_SET Extension momery slib set register 0x168 0x20 write-only 0x00000000 EM_SLIB_SET Extension memory sLib setting 0 16 EM_SLIB_ISS_SET Extension memory sLib instruction start sector setting 16 8 BTM_MODE_SET BTM_MODE_SET Boot memory mode setting register 0x16C 0x20 write-only 0x00000000 BTM_MODE_SET Boot memory mode setting 0 8 SLIB_UNLOCK SLIB_UNLOCK sLib unlock register 0x170 0x20 write-only 0x00000000 SLIB_UKVAL sLib unlock key value 0 32 NVIC Nested Vectored Interrupt Controller NVIC 0xE000E000 0x0 0x1001 registers ICTR ICTR Interrupt Controller Type Register 0x4 0x20 read-only 0x00000000 INTLINESNUM Total number of interrupt lines in groups 0 4 STIR STIR Software Triggered Interrupt Register 0xF00 0x20 write-only 0x00000000 INTID interrupt to be triggered 0 9 ISER0 ISER0 Interrupt Set-Enable Register 0x100 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER1 ISER1 Interrupt Set-Enable Register 0x104 0x20 read-write 0x00000000 SETENA SETENA 0 32 ICER0 ICER0 Interrupt Clear-Enable Register 0x180 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER1 ICER1 Interrupt Clear-Enable Register 0x184 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ISPR0 ISPR0 Interrupt Set-Pending Register 0x200 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR1 ISPR1 Interrupt Set-Pending Register 0x204 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ICPR0 ICPR0 Interrupt Clear-Pending Register 0x280 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR1 ICPR1 Interrupt Clear-Pending Register 0x284 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 IABR0 IABR0 Interrupt Active Bit Register 0x300 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR1 IABR1 Interrupt Active Bit Register 0x304 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IPR0 IPR0 Interrupt Priority Register 0x400 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR1 IPR1 Interrupt Priority Register 0x404 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR2 IPR2 Interrupt Priority Register 0x408 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR3 IPR3 Interrupt Priority Register 0x40C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR4 IPR4 Interrupt Priority Register 0x410 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR5 IPR5 Interrupt Priority Register 0x414 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR6 IPR6 Interrupt Priority Register 0x418 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR7 IPR7 Interrupt Priority Register 0x41C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR8 IPR8 Interrupt Priority Register 0x420 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR9 IPR9 Interrupt Priority Register 0x424 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR10 IPR10 Interrupt Priority Register 0x428 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR11 IPR11 Interrupt Priority Register 0x42C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR12 IPR12 Interrupt Priority Register 0x430 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR13 IPR13 Interrupt Priority Register 0x434 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR14 IPR14 Interrupt Priority Register 0x438 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 SCFG System configuration controller SCFG 0x40010000 0x0 0x1C registers CFG1 CFG1 configuration register 1 0x0 0x20 read-write 0x00000000 TMR17_DMA_RMP TMR17 DMA remap 12 1 TMR16_DMA_RMP TMR16 DMA remap 11 1 USART1_RX_DMA_RMP USART1 receive DMA remap 10 1 USART1_TX_DMA_RMP USART1 transmit DMA remap 9 1 ADC_DMA_RMP ADC DMA remap 8 1 IR_SRC_SEL IRTMR source select 6 2 IR_POL IRTMR Polariyt select 5 1 PA11_12_RMP PA11 PA12 Remap 4 1 MEM_MAP_SEL Memory address mapping selection bits 0 2 EXINTC1 EXINTC1 external interrupt configuration register 1 0x8 0x20 read-write 0x0000 EXINT3 EXINT 3 configuration bits 12 4 EXINT2 EXINT 2 configuration bits 8 4 EXINT1 EXINT 1 configuration bits 4 4 EXINT0 EXINT 0 configuration bits 0 4 EXINTC2 EXINTC2 external interrupt configuration register 2 0xC 0x20 read-write 0x0000 EXINT7 EXINT 7 configuration bits 12 4 EXINT6 EXINT 6 configuration bits 8 4 EXINT5 EXINT 5 configuration bits 4 4 EXINT4 EXINT 4 configuration bits 0 4 EXINTC3 EXINTC3 external interrupt configuration register 3 0x10 0x20 read-write 0x0000 EXINT11 EXINT 11 configuration bits 12 4 EXINT10 EXINT 10 configuration bits 8 4 EXINT9 EXINT 9 configuration bits 4 4 EXINT8 EXINT 8 configuration bits 0 4 EXINTC4 EXINTC4 external interrupt configuration register 4 0x14 0x20 read-write 0x0000 EXINT15 EXINT 15 configuration bits 12 4 EXINT14 EXINT 14 configuration bits 8 4 EXINT13 EXINT 13 configuration bits 4 4 EXINT12 EXINT 12 configuration bits 0 4